sparc.c revision 102780
1264790Sbapt/* Subroutines for insn-output.c for Sun SPARC. 2264790Sbapt Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3272955Srodrigc 1999, 2000, 2001 Free Software Foundation, Inc. 4264790Sbapt Contributed by Michael Tiemann (tiemann@cygnus.com) 5264790Sbapt 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6264790Sbapt at Cygnus Support. 7264790Sbapt 8264790SbaptThis file is part of GNU CC. 9264790Sbapt 10264790SbaptGNU CC is free software; you can redistribute it and/or modify 11264790Sbaptit under the terms of the GNU General Public License as published by 12264790Sbaptthe Free Software Foundation; either version 2, or (at your option) 13264790Sbaptany later version. 14264790Sbapt 15264790SbaptGNU CC is distributed in the hope that it will be useful, 16264790Sbaptbut WITHOUT ANY WARRANTY; without even the implied warranty of 17264790SbaptMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18264790SbaptGNU General Public License for more details. 19264790Sbapt 20264790SbaptYou should have received a copy of the GNU General Public License 21264790Sbaptalong with GNU CC; see the file COPYING. If not, write to 22264790Sbaptthe Free Software Foundation, 59 Temple Place - Suite 330, 23264790SbaptBoston, MA 02111-1307, USA. */ 24264790Sbapt 25264790Sbapt#include "config.h" 26264790Sbapt#include "system.h" 27264790Sbapt#include "tree.h" 28264790Sbapt#include "rtl.h" 29264790Sbapt#include "regs.h" 30264790Sbapt#include "hard-reg-set.h" 31264790Sbapt#include "real.h" 32264790Sbapt#include "insn-config.h" 33264790Sbapt#include "conditions.h" 34264790Sbapt#include "output.h" 35264790Sbapt#include "insn-attr.h" 36264790Sbapt#include "flags.h" 37264790Sbapt#include "function.h" 38264790Sbapt#include "expr.h" 39264790Sbapt#include "optabs.h" 40264790Sbapt#include "libfuncs.h" 41264790Sbapt#include "recog.h" 42264790Sbapt#include "toplev.h" 43264790Sbapt#include "ggc.h" 44264790Sbapt#include "tm_p.h" 45264790Sbapt#include "debug.h" 46264790Sbapt#include "target.h" 47264790Sbapt#include "target-def.h" 48264790Sbapt 49264790Sbapt/* 1 if the caller has placed an "unimp" insn immediately after the call. 50264790Sbapt This is used in v8 code when calling a function that returns a structure. 51264790Sbapt v9 doesn't have this. Be careful to have this test be the same as that 52264790Sbapt used on the call. */ 53264790Sbapt 54264790Sbapt#define SKIP_CALLERS_UNIMP_P \ 55264790Sbapt(!TARGET_ARCH64 && current_function_returns_struct \ 56264790Sbapt && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 57264790Sbapt && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \ 58264790Sbapt == INTEGER_CST)) 59264790Sbapt 60264790Sbapt/* Global variables for machine-dependent things. */ 61264790Sbapt 62264790Sbapt/* Size of frame. Need to know this to emit return insns from leaf procedures. 63264790Sbapt ACTUAL_FSIZE is set by compute_frame_size() which is called during the 64264790Sbapt reload pass. This is important as the value is later used in insn 65264790Sbapt scheduling (to see what can go in a delay slot). 66264790Sbapt APPARENT_FSIZE is the size of the stack less the register save area and less 67264790Sbapt the outgoing argument area. It is used when saving call preserved regs. */ 68264790Sbaptstatic int apparent_fsize; 69264790Sbaptstatic int actual_fsize; 70264790Sbapt 71264790Sbapt/* Number of live general or floating point registers needed to be 72264790Sbapt saved (as 4-byte quantities). */ 73264790Sbaptstatic int num_gfregs; 74264790Sbapt 75264790Sbapt/* Save the operands last given to a compare for use when we 76264790Sbapt generate a scc or bcc insn. */ 77264790Sbaptrtx sparc_compare_op0, sparc_compare_op1; 78264790Sbapt 79264790Sbapt/* Coordinate with the md file wrt special insns created by 80264790Sbapt sparc_nonflat_function_epilogue. */ 81264790Sbaptbool sparc_emitting_epilogue; 82264790Sbapt 83264790Sbapt#ifdef LEAF_REGISTERS 84264790Sbapt 85264790Sbapt/* Vector to say how input registers are mapped to output registers. 86264790Sbapt HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to 87264790Sbapt eliminate it. You must use -fomit-frame-pointer to get that. */ 88264790Sbaptchar leaf_reg_remap[] = 89264790Sbapt{ 0, 1, 2, 3, 4, 5, 6, 7, 90264790Sbapt -1, -1, -1, -1, -1, -1, 14, -1, 91264790Sbapt -1, -1, -1, -1, -1, -1, -1, -1, 92264790Sbapt 8, 9, 10, 11, 12, 13, -1, 15, 93264790Sbapt 94264790Sbapt 32, 33, 34, 35, 36, 37, 38, 39, 95264790Sbapt 40, 41, 42, 43, 44, 45, 46, 47, 96264790Sbapt 48, 49, 50, 51, 52, 53, 54, 55, 97264790Sbapt 56, 57, 58, 59, 60, 61, 62, 63, 98264790Sbapt 64, 65, 66, 67, 68, 69, 70, 71, 99264790Sbapt 72, 73, 74, 75, 76, 77, 78, 79, 100264790Sbapt 80, 81, 82, 83, 84, 85, 86, 87, 101264790Sbapt 88, 89, 90, 91, 92, 93, 94, 95, 102264790Sbapt 96, 97, 98, 99, 100}; 103264790Sbapt 104264790Sbapt/* Vector, indexed by hard register number, which contains 1 105264790Sbapt for a register that is allowable in a candidate for leaf 106264790Sbapt function treatment. */ 107264790Sbaptchar sparc_leaf_regs[] = 108264790Sbapt{ 1, 1, 1, 1, 1, 1, 1, 1, 109264790Sbapt 0, 0, 0, 0, 0, 0, 1, 0, 110264790Sbapt 0, 0, 0, 0, 0, 0, 0, 0, 111264790Sbapt 1, 1, 1, 1, 1, 1, 0, 1, 112264790Sbapt 1, 1, 1, 1, 1, 1, 1, 1, 113264790Sbapt 1, 1, 1, 1, 1, 1, 1, 1, 114264790Sbapt 1, 1, 1, 1, 1, 1, 1, 1, 115264790Sbapt 1, 1, 1, 1, 1, 1, 1, 1, 116264790Sbapt 1, 1, 1, 1, 1, 1, 1, 1, 117264790Sbapt 1, 1, 1, 1, 1, 1, 1, 1, 118264790Sbapt 1, 1, 1, 1, 1, 1, 1, 1, 119264790Sbapt 1, 1, 1, 1, 1, 1, 1, 1, 120264790Sbapt 1, 1, 1, 1, 1}; 121264790Sbapt 122264790Sbapt#endif 123264790Sbapt 124264790Sbapt/* Name of where we pretend to think the frame pointer points. 125264790Sbapt Normally, this is "%fp", but if we are in a leaf procedure, 126264790Sbapt this is "%sp+something". We record "something" separately as it may be 127264790Sbapt too big for reg+constant addressing. */ 128264790Sbapt 129264790Sbaptstatic const char *frame_base_name; 130264790Sbaptstatic int frame_base_offset; 131264790Sbapt 132264790Sbaptstatic void sparc_init_modes PARAMS ((void)); 133264790Sbaptstatic int save_regs PARAMS ((FILE *, int, int, const char *, 134264790Sbapt int, int, int)); 135264790Sbaptstatic int restore_regs PARAMS ((FILE *, int, int, const char *, int, int)); 136264790Sbaptstatic void build_big_number PARAMS ((FILE *, int, const char *)); 137264790Sbaptstatic int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *, 138264790Sbapt enum machine_mode, tree, int, int, 139264790Sbapt int *, int *)); 140264790Sbapt 141264790Sbaptstatic int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 142264790Sbaptstatic int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 143264790Sbaptstatic int ultrasparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 144264790Sbapt 145264790Sbaptstatic void sparc_output_addr_vec PARAMS ((rtx)); 146264790Sbaptstatic void sparc_output_addr_diff_vec PARAMS ((rtx)); 147264790Sbaptstatic void sparc_output_deferred_case_vectors PARAMS ((void)); 148264790Sbaptstatic void sparc_add_gc_roots PARAMS ((void)); 149264790Sbaptstatic void mark_ultrasparc_pipeline_state PARAMS ((void *)); 150264790Sbaptstatic int check_return_regs PARAMS ((rtx)); 151264790Sbaptstatic int epilogue_renumber PARAMS ((rtx *, int)); 152264790Sbaptstatic bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int)); 153264790Sbaptstatic int ultra_cmove_results_ready_p PARAMS ((rtx)); 154264790Sbaptstatic int ultra_fpmode_conflict_exists PARAMS ((enum machine_mode)); 155264790Sbaptstatic rtx *ultra_find_type PARAMS ((int, rtx *, int)); 156264790Sbaptstatic void ultra_build_types_avail PARAMS ((rtx *, int)); 157264790Sbaptstatic void ultra_flush_pipeline PARAMS ((void)); 158264790Sbaptstatic void ultra_rescan_pipeline_state PARAMS ((rtx *, int)); 159264790Sbaptstatic int set_extends PARAMS ((rtx)); 160264790Sbaptstatic void output_restore_regs PARAMS ((FILE *, int)); 161264790Sbaptstatic void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); 162264790Sbaptstatic void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); 163264790Sbaptstatic void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); 164264790Sbaptstatic void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); 165264790Sbaptstatic void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT, 166264790Sbapt int)); 167264790Sbaptstatic void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT, 168264790Sbapt int)); 169264790Sbapt#ifdef OBJECT_FORMAT_ELF 170264790Sbaptstatic void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int)); 171264790Sbapt#endif 172264790Sbaptstatic void ultrasparc_sched_reorder PARAMS ((FILE *, int, rtx *, int)); 173264790Sbaptstatic int ultrasparc_variable_issue PARAMS ((rtx)); 174264790Sbaptstatic void ultrasparc_sched_init PARAMS ((void)); 175264790Sbapt 176264790Sbaptstatic int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 177264790Sbaptstatic int sparc_issue_rate PARAMS ((void)); 178264790Sbaptstatic int sparc_variable_issue PARAMS ((FILE *, int, rtx, int)); 179264790Sbaptstatic void sparc_sched_init PARAMS ((FILE *, int, int)); 180264790Sbaptstatic int sparc_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int)); 181264790Sbapt 182264790Sbaptstatic void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *)); 183264790Sbaptstatic void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *)); 184264790Sbaptstatic void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *)); 185264790Sbaptstatic void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *)); 186264790Sbaptstatic void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *)); 187264790Sbapt 188264790Sbapt/* Option handling. */ 189264790Sbapt 190264790Sbapt/* Code model option as passed by user. */ 191264790Sbaptconst char *sparc_cmodel_string; 192264790Sbapt/* Parsed value. */ 193264790Sbaptenum cmodel sparc_cmodel; 194264790Sbapt 195264790Sbaptchar sparc_hard_reg_printed[8]; 196264790Sbapt 197264790Sbaptstruct sparc_cpu_select sparc_select[] = 198264790Sbapt{ 199264790Sbapt /* switch name, tune arch */ 200264790Sbapt { (char *)0, "default", 1, 1 }, 201264790Sbapt { (char *)0, "-mcpu=", 1, 1 }, 202264790Sbapt { (char *)0, "-mtune=", 1, 0 }, 203264790Sbapt { 0, 0, 0, 0 } 204264790Sbapt}; 205264790Sbapt 206264790Sbapt/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ 207264790Sbaptenum processor_type sparc_cpu; 208264790Sbapt 209264790Sbapt/* Initialize the GCC target structure. */ 210264790Sbapt 211264790Sbapt/* The sparc default is to use .half rather than .short for aligned 212264790Sbapt HI objects. Use .word instead of .long on non-ELF systems. */ 213264790Sbapt#undef TARGET_ASM_ALIGNED_HI_OP 214264790Sbapt#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 215264790Sbapt#ifndef OBJECT_FORMAT_ELF 216264790Sbapt#undef TARGET_ASM_ALIGNED_SI_OP 217264790Sbapt#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 218264790Sbapt#endif 219264790Sbapt 220264790Sbapt#undef TARGET_ASM_UNALIGNED_HI_OP 221264790Sbapt#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" 222264790Sbapt#undef TARGET_ASM_UNALIGNED_SI_OP 223264790Sbapt#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" 224264790Sbapt#undef TARGET_ASM_UNALIGNED_DI_OP 225264790Sbapt#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" 226264790Sbapt 227264790Sbapt/* The target hook has to handle DI-mode values. */ 228264790Sbapt#undef TARGET_ASM_INTEGER 229264790Sbapt#define TARGET_ASM_INTEGER sparc_assemble_integer 230264790Sbapt 231264790Sbapt#undef TARGET_ASM_FUNCTION_PROLOGUE 232264790Sbapt#define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue 233264790Sbapt#undef TARGET_ASM_FUNCTION_EPILOGUE 234264790Sbapt#define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue 235264790Sbapt 236264790Sbapt#undef TARGET_SCHED_ADJUST_COST 237264790Sbapt#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost 238264790Sbapt#undef TARGET_SCHED_ISSUE_RATE 239264790Sbapt#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate 240264790Sbapt#undef TARGET_SCHED_VARIABLE_ISSUE 241264790Sbapt#define TARGET_SCHED_VARIABLE_ISSUE sparc_variable_issue 242264790Sbapt#undef TARGET_SCHED_INIT 243264790Sbapt#define TARGET_SCHED_INIT sparc_sched_init 244264790Sbapt#undef TARGET_SCHED_REORDER 245264790Sbapt#define TARGET_SCHED_REORDER sparc_sched_reorder 246264790Sbapt 247264790Sbaptstruct gcc_target targetm = TARGET_INITIALIZER; 248264790Sbapt 249264790Sbapt/* Validate and override various options, and do some machine dependent 250264790Sbapt initialization. */ 251264790Sbapt 252264790Sbaptvoid 253264790Sbaptsparc_override_options () 254264790Sbapt{ 255264790Sbapt static struct code_model { 256264790Sbapt const char *const name; 257264790Sbapt const int value; 258264790Sbapt } const cmodels[] = { 259264790Sbapt { "32", CM_32 }, 260264790Sbapt { "medlow", CM_MEDLOW }, 261264790Sbapt { "medmid", CM_MEDMID }, 262264790Sbapt { "medany", CM_MEDANY }, 263264790Sbapt { "embmedany", CM_EMBMEDANY }, 264264790Sbapt { 0, 0 } 265264790Sbapt }; 266264790Sbapt const struct code_model *cmodel; 267264790Sbapt /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ 268264790Sbapt static struct cpu_default { 269264790Sbapt const int cpu; 270264790Sbapt const char *const name; 271264790Sbapt } const cpu_default[] = { 272264790Sbapt /* There must be one entry here for each TARGET_CPU value. */ 273264790Sbapt { TARGET_CPU_sparc, "cypress" }, 274264790Sbapt { TARGET_CPU_sparclet, "tsc701" }, 275264790Sbapt { TARGET_CPU_sparclite, "f930" }, 276264790Sbapt { TARGET_CPU_v8, "v8" }, 277264790Sbapt { TARGET_CPU_hypersparc, "hypersparc" }, 278264790Sbapt { TARGET_CPU_sparclite86x, "sparclite86x" }, 279264790Sbapt { TARGET_CPU_supersparc, "supersparc" }, 280264790Sbapt { TARGET_CPU_v9, "v9" }, 281264790Sbapt { TARGET_CPU_ultrasparc, "ultrasparc" }, 282264790Sbapt { 0, 0 } 283264790Sbapt }; 284264790Sbapt const struct cpu_default *def; 285264790Sbapt /* Table of values for -m{cpu,tune}=. */ 286264790Sbapt static struct cpu_table { 287264790Sbapt const char *const name; 288264790Sbapt const enum processor_type processor; 289264790Sbapt const int disable; 290264790Sbapt const int enable; 291264790Sbapt } const cpu_table[] = { 292264790Sbapt { "v7", PROCESSOR_V7, MASK_ISA, 0 }, 293264790Sbapt { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, 294264790Sbapt { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, 295264790Sbapt /* TI TMS390Z55 supersparc */ 296264790Sbapt { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, 297264790Sbapt { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, 298264790Sbapt /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. 299264790Sbapt The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ 300264790Sbapt { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, 301264790Sbapt { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, 302264790Sbapt { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, 303264790Sbapt { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, 304264790Sbapt MASK_SPARCLITE }, 305264790Sbapt { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, 306264790Sbapt /* TEMIC sparclet */ 307264790Sbapt { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, 308264790Sbapt { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, 309264790Sbapt /* TI ultrasparc I, II, IIi */ 310264790Sbapt { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 311264790Sbapt /* Although insns using %y are deprecated, it is a clear win on current 312264790Sbapt ultrasparcs. */ 313264790Sbapt |MASK_DEPRECATED_V8_INSNS}, 314264790Sbapt { 0, 0, 0, 0 } 315264790Sbapt }; 316264790Sbapt const struct cpu_table *cpu; 317264790Sbapt const struct sparc_cpu_select *sel; 318264790Sbapt int fpu; 319264790Sbapt 320264790Sbapt#ifndef SPARC_BI_ARCH 321264790Sbapt /* Check for unsupported architecture size. */ 322264790Sbapt if (! TARGET_64BIT != DEFAULT_ARCH32_P) 323264790Sbapt error ("%s is not supported by this configuration", 324264790Sbapt DEFAULT_ARCH32_P ? "-m64" : "-m32"); 325264790Sbapt#endif 326264790Sbapt 327264790Sbapt /* We force all 64bit archs to use 128 bit long double */ 328264790Sbapt if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) 329264790Sbapt { 330264790Sbapt error ("-mlong-double-64 not allowed with -m64"); 331264790Sbapt target_flags |= MASK_LONG_DOUBLE_128; 332264790Sbapt } 333264790Sbapt 334264790Sbapt /* Code model selection. */ 335264790Sbapt sparc_cmodel = SPARC_DEFAULT_CMODEL; 336264790Sbapt 337264790Sbapt#ifdef SPARC_BI_ARCH 338264790Sbapt if (TARGET_ARCH32) 339264790Sbapt sparc_cmodel = CM_32; 340264790Sbapt#endif 341264790Sbapt 342264790Sbapt if (sparc_cmodel_string != NULL) 343264790Sbapt { 344264790Sbapt if (TARGET_ARCH64) 345264790Sbapt { 346264790Sbapt for (cmodel = &cmodels[0]; cmodel->name; cmodel++) 347264790Sbapt if (strcmp (sparc_cmodel_string, cmodel->name) == 0) 348264790Sbapt break; 349264790Sbapt if (cmodel->name == NULL) 350264790Sbapt error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); 351264790Sbapt else 352264790Sbapt sparc_cmodel = cmodel->value; 353264790Sbapt } 354264790Sbapt else 355264790Sbapt error ("-mcmodel= is not supported on 32 bit systems"); 356264790Sbapt } 357264790Sbapt 358264790Sbapt fpu = TARGET_FPU; /* save current -mfpu status */ 359264790Sbapt 360264790Sbapt /* Set the default CPU. */ 361264790Sbapt for (def = &cpu_default[0]; def->name; ++def) 362264790Sbapt if (def->cpu == TARGET_CPU_DEFAULT) 363264790Sbapt break; 364264790Sbapt if (! def->name) 365264790Sbapt abort (); 366264790Sbapt sparc_select[0].string = def->name; 367264790Sbapt 368264790Sbapt for (sel = &sparc_select[0]; sel->name; ++sel) 369264790Sbapt { 370264790Sbapt if (sel->string) 371264790Sbapt { 372264790Sbapt for (cpu = &cpu_table[0]; cpu->name; ++cpu) 373264790Sbapt if (! strcmp (sel->string, cpu->name)) 374264790Sbapt { 375264790Sbapt if (sel->set_tune_p) 376264790Sbapt sparc_cpu = cpu->processor; 377264790Sbapt 378264790Sbapt if (sel->set_arch_p) 379264790Sbapt { 380264790Sbapt target_flags &= ~cpu->disable; 381264790Sbapt target_flags |= cpu->enable; 382264790Sbapt } 383264790Sbapt break; 384264790Sbapt } 385264790Sbapt 386264790Sbapt if (! cpu->name) 387264790Sbapt error ("bad value (%s) for %s switch", sel->string, sel->name); 388264790Sbapt } 389264790Sbapt } 390272955Srodrigc 391272955Srodrigc /* If -mfpu or -mno-fpu was explicitly used, don't override with 392272955Srodrigc the processor default. Clear MASK_FPU_SET to avoid confusing 393272955Srodrigc the reverse mapping from switch values to names. */ 394272955Srodrigc if (TARGET_FPU_SET) 395272955Srodrigc { 396272955Srodrigc target_flags = (target_flags & ~MASK_FPU) | fpu; 397272955Srodrigc target_flags &= ~MASK_FPU_SET; 398272955Srodrigc } 399272955Srodrigc 400272955Srodrigc /* Don't allow -mvis if FPU is disabled. */ 401272955Srodrigc if (! TARGET_FPU) 402272955Srodrigc target_flags &= ~MASK_VIS; 403272955Srodrigc 404272955Srodrigc /* -mvis assumes UltraSPARC+, so we are sure v9 instructions 405272955Srodrigc are available. 406272955Srodrigc -m64 also implies v9. */ 407272955Srodrigc if (TARGET_VIS || TARGET_ARCH64) 408272955Srodrigc { 409272955Srodrigc target_flags |= MASK_V9; 410272955Srodrigc target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); 411272955Srodrigc } 412272955Srodrigc 413272955Srodrigc /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ 414272955Srodrigc if (TARGET_V9 && TARGET_ARCH32) 415272955Srodrigc target_flags |= MASK_DEPRECATED_V8_INSNS; 416264790Sbapt 417264790Sbapt /* V8PLUS requires V9, makes no sense in 64 bit mode. */ 418264790Sbapt if (! TARGET_V9 || TARGET_ARCH64) 419264790Sbapt target_flags &= ~MASK_V8PLUS; 420264790Sbapt 421264790Sbapt /* Don't use stack biasing in 32 bit mode. */ 422264790Sbapt if (TARGET_ARCH32) 423264790Sbapt target_flags &= ~MASK_STACK_BIAS; 424264790Sbapt 425264790Sbapt /* Supply a default value for align_functions. */ 426264790Sbapt if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC) 427264790Sbapt align_functions = 32; 428264790Sbapt 429264790Sbapt /* Validate PCC_STRUCT_RETURN. */ 430264790Sbapt if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) 431264790Sbapt flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); 432264790Sbapt 433264790Sbapt /* Only use .uaxword when compiling for a 64-bit target. */ 434264790Sbapt if (!TARGET_ARCH64) 435264790Sbapt targetm.asm_out.unaligned_op.di = NULL; 436264790Sbapt 437264790Sbapt /* Do various machine dependent initializations. */ 438264790Sbapt sparc_init_modes (); 439264790Sbapt 440264790Sbapt /* Register global variables with the garbage collector. */ 441264790Sbapt sparc_add_gc_roots (); 442264790Sbapt} 443264790Sbapt 444264790Sbapt/* Miscellaneous utilities. */ 445264790Sbapt 446264790Sbapt/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move 447264790Sbapt or branch on register contents instructions. */ 448264790Sbapt 449264790Sbaptint 450264790Sbaptv9_regcmp_p (code) 451264790Sbapt enum rtx_code code; 452264790Sbapt{ 453264790Sbapt return (code == EQ || code == NE || code == GE || code == LT 454264790Sbapt || code == LE || code == GT); 455264790Sbapt} 456264790Sbapt 457264790Sbapt 458264790Sbapt/* Operand constraints. */ 459264790Sbapt 460264790Sbapt/* Return non-zero only if OP is a register of mode MODE, 461264790Sbapt or const0_rtx. */ 462264790Sbapt 463264790Sbaptint 464264790Sbaptreg_or_0_operand (op, mode) 465264790Sbapt rtx op; 466264790Sbapt enum machine_mode mode; 467264790Sbapt{ 468264790Sbapt if (register_operand (op, mode)) 469264790Sbapt return 1; 470264790Sbapt if (op == const0_rtx) 471264790Sbapt return 1; 472264790Sbapt if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE 473264790Sbapt && CONST_DOUBLE_HIGH (op) == 0 474264790Sbapt && CONST_DOUBLE_LOW (op) == 0) 475264790Sbapt return 1; 476264790Sbapt if (fp_zero_operand (op, mode)) 477264790Sbapt return 1; 478264790Sbapt return 0; 479264790Sbapt} 480264790Sbapt 481264790Sbapt/* Nonzero if OP is a floating point value with value 0.0. */ 482264790Sbapt 483264790Sbaptint 484264790Sbaptfp_zero_operand (op, mode) 485264790Sbapt rtx op; 486264790Sbapt enum machine_mode mode; 487264790Sbapt{ 488264790Sbapt if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT) 489264790Sbapt return 0; 490264790Sbapt return op == CONST0_RTX (mode); 491264790Sbapt} 492264790Sbapt 493264790Sbapt/* Nonzero if OP is a register operand in floating point register. */ 494264790Sbapt 495264790Sbaptint 496264790Sbaptfp_register_operand (op, mode) 497264790Sbapt rtx op; 498264790Sbapt enum machine_mode mode; 499264790Sbapt{ 500264790Sbapt if (! register_operand (op, mode)) 501264790Sbapt return 0; 502264790Sbapt if (GET_CODE (op) == SUBREG) 503264790Sbapt op = SUBREG_REG (op); 504264790Sbapt return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op)); 505264790Sbapt} 506264790Sbapt 507264790Sbapt/* Nonzero if OP is a floating point constant which can 508264790Sbapt be loaded into an integer register using a single 509264790Sbapt sethi instruction. */ 510264790Sbapt 511264790Sbaptint 512264790Sbaptfp_sethi_p (op) 513264790Sbapt rtx op; 514264790Sbapt{ 515264790Sbapt if (GET_CODE (op) == CONST_DOUBLE) 516264790Sbapt { 517264790Sbapt REAL_VALUE_TYPE r; 518264790Sbapt long i; 519264790Sbapt 520264790Sbapt REAL_VALUE_FROM_CONST_DOUBLE (r, op); 521264790Sbapt if (REAL_VALUES_EQUAL (r, dconst0) && 522264790Sbapt ! REAL_VALUE_MINUS_ZERO (r)) 523264790Sbapt return 0; 524264790Sbapt REAL_VALUE_TO_TARGET_SINGLE (r, i); 525264790Sbapt if (SPARC_SETHI_P (i)) 526264790Sbapt return 1; 527264790Sbapt } 528264790Sbapt 529264790Sbapt return 0; 530264790Sbapt} 531264790Sbapt 532264790Sbapt/* Nonzero if OP is a floating point constant which can 533264790Sbapt be loaded into an integer register using a single 534264790Sbapt mov instruction. */ 535264790Sbapt 536264790Sbaptint 537264790Sbaptfp_mov_p (op) 538264790Sbapt rtx op; 539264790Sbapt{ 540264790Sbapt if (GET_CODE (op) == CONST_DOUBLE) 541264790Sbapt { 542264790Sbapt REAL_VALUE_TYPE r; 543264790Sbapt long i; 544264790Sbapt 545264790Sbapt REAL_VALUE_FROM_CONST_DOUBLE (r, op); 546264790Sbapt if (REAL_VALUES_EQUAL (r, dconst0) && 547264790Sbapt ! REAL_VALUE_MINUS_ZERO (r)) 548264790Sbapt return 0; 549264790Sbapt REAL_VALUE_TO_TARGET_SINGLE (r, i); 550264790Sbapt if (SPARC_SIMM13_P (i)) 551264790Sbapt return 1; 552264790Sbapt } 553264790Sbapt 554264790Sbapt return 0; 555264790Sbapt} 556264790Sbapt 557264790Sbapt/* Nonzero if OP is a floating point constant which can 558264790Sbapt be loaded into an integer register using a high/losum 559264790Sbapt instruction sequence. */ 560264790Sbapt 561264790Sbaptint 562264790Sbaptfp_high_losum_p (op) 563264790Sbapt rtx op; 564264790Sbapt{ 565264790Sbapt /* The constraints calling this should only be in 566264790Sbapt SFmode move insns, so any constant which cannot 567264790Sbapt be moved using a single insn will do. */ 568264790Sbapt if (GET_CODE (op) == CONST_DOUBLE) 569264790Sbapt { 570264790Sbapt REAL_VALUE_TYPE r; 571264790Sbapt long i; 572264790Sbapt 573264790Sbapt REAL_VALUE_FROM_CONST_DOUBLE (r, op); 574264790Sbapt if (REAL_VALUES_EQUAL (r, dconst0) && 575264790Sbapt ! REAL_VALUE_MINUS_ZERO (r)) 576264790Sbapt return 0; 577264790Sbapt REAL_VALUE_TO_TARGET_SINGLE (r, i); 578264790Sbapt if (! SPARC_SETHI_P (i) 579264790Sbapt && ! SPARC_SIMM13_P (i)) 580264790Sbapt return 1; 581264790Sbapt } 582264790Sbapt 583264790Sbapt return 0; 584264790Sbapt} 585264790Sbapt 586264790Sbapt/* Nonzero if OP is an integer register. */ 587264790Sbapt 588264790Sbaptint 589264790Sbaptintreg_operand (op, mode) 590264790Sbapt rtx op; 591264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 592264790Sbapt{ 593264790Sbapt return (register_operand (op, SImode) 594264790Sbapt || (TARGET_ARCH64 && register_operand (op, DImode))); 595264790Sbapt} 596264790Sbapt 597264790Sbapt/* Nonzero if OP is a floating point condition code register. */ 598264790Sbapt 599264790Sbaptint 600264790Sbaptfcc_reg_operand (op, mode) 601264790Sbapt rtx op; 602264790Sbapt enum machine_mode mode; 603264790Sbapt{ 604264790Sbapt /* This can happen when recog is called from combine. Op may be a MEM. 605264790Sbapt Fail instead of calling abort in this case. */ 606264790Sbapt if (GET_CODE (op) != REG) 607264790Sbapt return 0; 608264790Sbapt 609264790Sbapt if (mode != VOIDmode && mode != GET_MODE (op)) 610264790Sbapt return 0; 611264790Sbapt if (mode == VOIDmode 612264790Sbapt && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 613264790Sbapt return 0; 614264790Sbapt 615264790Sbapt#if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */ 616264790Sbapt if (reg_renumber == 0) 617264790Sbapt return REGNO (op) >= FIRST_PSEUDO_REGISTER; 618264790Sbapt return REGNO_OK_FOR_CCFP_P (REGNO (op)); 619264790Sbapt#else 620264790Sbapt return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4; 621264790Sbapt#endif 622264790Sbapt} 623264790Sbapt 624264790Sbapt/* Nonzero if OP is a floating point condition code fcc0 register. */ 625264790Sbapt 626264790Sbaptint 627264790Sbaptfcc0_reg_operand (op, mode) 628264790Sbapt rtx op; 629264790Sbapt enum machine_mode mode; 630264790Sbapt{ 631264790Sbapt /* This can happen when recog is called from combine. Op may be a MEM. 632264790Sbapt Fail instead of calling abort in this case. */ 633264790Sbapt if (GET_CODE (op) != REG) 634264790Sbapt return 0; 635264790Sbapt 636264790Sbapt if (mode != VOIDmode && mode != GET_MODE (op)) 637264790Sbapt return 0; 638264790Sbapt if (mode == VOIDmode 639264790Sbapt && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode)) 640264790Sbapt return 0; 641264790Sbapt 642264790Sbapt return REGNO (op) == SPARC_FCC_REG; 643264790Sbapt} 644264790Sbapt 645264790Sbapt/* Nonzero if OP is an integer or floating point condition code register. */ 646264790Sbapt 647264790Sbaptint 648264790Sbapticc_or_fcc_reg_operand (op, mode) 649264790Sbapt rtx op; 650264790Sbapt enum machine_mode mode; 651264790Sbapt{ 652264790Sbapt if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG) 653264790Sbapt { 654264790Sbapt if (mode != VOIDmode && mode != GET_MODE (op)) 655264790Sbapt return 0; 656264790Sbapt if (mode == VOIDmode 657264790Sbapt && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode) 658264790Sbapt return 0; 659264790Sbapt return 1; 660264790Sbapt } 661264790Sbapt 662272955Srodrigc return fcc_reg_operand (op, mode); 663264790Sbapt} 664264790Sbapt 665264790Sbapt/* Nonzero if OP can appear as the dest of a RESTORE insn. */ 666264790Sbaptint 667264790Sbaptrestore_operand (op, mode) 668264790Sbapt rtx op; 669264790Sbapt enum machine_mode mode; 670264790Sbapt{ 671264790Sbapt return (GET_CODE (op) == REG && GET_MODE (op) == mode 672264790Sbapt && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32))); 673264790Sbapt} 674264790Sbapt 675264790Sbapt/* Call insn on SPARC can take a PC-relative constant address, or any regular 676264790Sbapt memory address. */ 677264790Sbapt 678264790Sbaptint 679272955Srodrigccall_operand (op, mode) 680264790Sbapt rtx op; 681264790Sbapt enum machine_mode mode; 682264790Sbapt{ 683264790Sbapt if (GET_CODE (op) != MEM) 684264790Sbapt abort (); 685264790Sbapt op = XEXP (op, 0); 686264790Sbapt return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 687264790Sbapt} 688272955Srodrigc 689264790Sbaptint 690264790Sbaptcall_operand_address (op, mode) 691264790Sbapt rtx op; 692264790Sbapt enum machine_mode mode; 693264790Sbapt{ 694264790Sbapt return (symbolic_operand (op, mode) || memory_address_p (Pmode, op)); 695264790Sbapt} 696264790Sbapt 697272955Srodrigc/* Returns 1 if OP is either a symbol reference or a sum of a symbol 698264790Sbapt reference and a constant. */ 699264790Sbapt 700264790Sbaptint 701264790Sbaptsymbolic_operand (op, mode) 702264790Sbapt register rtx op; 703264790Sbapt enum machine_mode mode; 704264790Sbapt{ 705264790Sbapt enum machine_mode omode = GET_MODE (op); 706272955Srodrigc 707264790Sbapt if (omode != mode && omode != VOIDmode && mode != VOIDmode) 708264790Sbapt return 0; 709264790Sbapt 710264790Sbapt switch (GET_CODE (op)) 711264790Sbapt { 712264790Sbapt case SYMBOL_REF: 713264790Sbapt case LABEL_REF: 714264790Sbapt return 1; 715272955Srodrigc 716264790Sbapt case CONST: 717264790Sbapt op = XEXP (op, 0); 718264790Sbapt return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF 719264790Sbapt || GET_CODE (XEXP (op, 0)) == LABEL_REF) 720264790Sbapt && GET_CODE (XEXP (op, 1)) == CONST_INT); 721264790Sbapt 722264790Sbapt default: 723264790Sbapt return 0; 724272955Srodrigc } 725264790Sbapt} 726264790Sbapt 727264790Sbapt/* Return truth value of statement that OP is a symbolic memory 728264790Sbapt operand of mode MODE. */ 729264790Sbapt 730264790Sbaptint 731264790Sbaptsymbolic_memory_operand (op, mode) 732264790Sbapt rtx op; 733272955Srodrigc enum machine_mode mode ATTRIBUTE_UNUSED; 734264790Sbapt{ 735264790Sbapt if (GET_CODE (op) == SUBREG) 736264790Sbapt op = SUBREG_REG (op); 737264790Sbapt if (GET_CODE (op) != MEM) 738264790Sbapt return 0; 739264790Sbapt op = XEXP (op, 0); 740264790Sbapt return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST 741264790Sbapt || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); 742272955Srodrigc} 743264790Sbapt 744264790Sbapt/* Return truth value of statement that OP is a LABEL_REF of mode MODE. */ 745264790Sbapt 746264790Sbaptint 747264790Sbaptlabel_ref_operand (op, mode) 748264790Sbapt rtx op; 749264790Sbapt enum machine_mode mode; 750264790Sbapt{ 751272955Srodrigc if (GET_CODE (op) != LABEL_REF) 752264790Sbapt return 0; 753264790Sbapt if (GET_MODE (op) != mode) 754264790Sbapt return 0; 755264790Sbapt return 1; 756264790Sbapt} 757264790Sbapt 758264790Sbapt/* Return 1 if the operand is an argument used in generating pic references 759264790Sbapt in either the medium/low or medium/anywhere code models of sparc64. */ 760272955Srodrigc 761264790Sbaptint 762264790Sbaptsp64_medium_pic_operand (op, mode) 763264790Sbapt rtx op; 764264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 765264790Sbapt{ 766264790Sbapt /* Check for (const (minus (symbol_ref:GOT) 767264790Sbapt (const (minus (label) (pc))))). */ 768264790Sbapt if (GET_CODE (op) != CONST) 769272955Srodrigc return 0; 770264790Sbapt op = XEXP (op, 0); 771264790Sbapt if (GET_CODE (op) != MINUS) 772264790Sbapt return 0; 773264790Sbapt if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF) 774264790Sbapt return 0; 775264790Sbapt /* ??? Ensure symbol is GOT. */ 776264790Sbapt if (GET_CODE (XEXP (op, 1)) != CONST) 777264790Sbapt return 0; 778272955Srodrigc if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS) 779264790Sbapt return 0; 780264790Sbapt return 1; 781264790Sbapt} 782264790Sbapt 783264790Sbapt/* Return 1 if the operand is a data segment reference. This includes 784264790Sbapt the readonly data segment, or in other words anything but the text segment. 785264790Sbapt This is needed in the medium/anywhere code model on v9. These values 786264790Sbapt are accessed with EMBMEDANY_BASE_REG. */ 787272955Srodrigc 788264790Sbaptint 789264790Sbaptdata_segment_operand (op, mode) 790264790Sbapt rtx op; 791264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 792264790Sbapt{ 793264790Sbapt switch (GET_CODE (op)) 794264790Sbapt { 795264790Sbapt case SYMBOL_REF : 796272955Srodrigc return ! SYMBOL_REF_FLAG (op); 797264790Sbapt case PLUS : 798264790Sbapt /* Assume canonical format of symbol + constant. 799264790Sbapt Fall through. */ 800264790Sbapt case CONST : 801264790Sbapt return data_segment_operand (XEXP (op, 0), VOIDmode); 802264790Sbapt default : 803264790Sbapt return 0; 804264790Sbapt } 805272955Srodrigc} 806264790Sbapt 807264790Sbapt/* Return 1 if the operand is a text segment reference. 808264790Sbapt This is needed in the medium/anywhere code model on v9. */ 809264790Sbapt 810264790Sbaptint 811264790Sbapttext_segment_operand (op, mode) 812264790Sbapt rtx op; 813264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 814272955Srodrigc{ 815264790Sbapt switch (GET_CODE (op)) 816264790Sbapt { 817264790Sbapt case LABEL_REF : 818264790Sbapt return 1; 819264790Sbapt case SYMBOL_REF : 820264790Sbapt return SYMBOL_REF_FLAG (op); 821264790Sbapt case PLUS : 822264790Sbapt /* Assume canonical format of symbol + constant. 823272955Srodrigc Fall through. */ 824264790Sbapt case CONST : 825264790Sbapt return text_segment_operand (XEXP (op, 0), VOIDmode); 826264790Sbapt default : 827264790Sbapt return 0; 828264790Sbapt } 829264790Sbapt} 830264790Sbapt 831264790Sbapt/* Return 1 if the operand is either a register or a memory operand that is 832272955Srodrigc not symbolic. */ 833264790Sbapt 834264790Sbaptint 835264790Sbaptreg_or_nonsymb_mem_operand (op, mode) 836264790Sbapt register rtx op; 837264790Sbapt enum machine_mode mode; 838264790Sbapt{ 839264790Sbapt if (register_operand (op, mode)) 840264790Sbapt return 1; 841272955Srodrigc 842264790Sbapt if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) 843264790Sbapt return 1; 844264790Sbapt 845264790Sbapt return 0; 846264790Sbapt} 847264790Sbapt 848264790Sbaptint 849264790Sbaptsplittable_symbolic_memory_operand (op, mode) 850272955Srodrigc rtx op; 851264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 852264790Sbapt{ 853264790Sbapt if (GET_CODE (op) != MEM) 854264790Sbapt return 0; 855264790Sbapt if (! symbolic_operand (XEXP (op, 0), Pmode)) 856264790Sbapt return 0; 857264790Sbapt return 1; 858264790Sbapt} 859272955Srodrigc 860264790Sbaptint 861264790Sbaptsplittable_immediate_memory_operand (op, mode) 862264790Sbapt rtx op; 863264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 864264790Sbapt{ 865264790Sbapt if (GET_CODE (op) != MEM) 866264790Sbapt return 0; 867264790Sbapt if (! immediate_operand (XEXP (op, 0), Pmode)) 868272955Srodrigc return 0; 869264790Sbapt return 1; 870264790Sbapt} 871264790Sbapt 872264790Sbapt/* Return truth value of whether OP is EQ or NE. */ 873264790Sbapt 874264790Sbaptint 875264790Sbapteq_or_neq (op, mode) 876264790Sbapt rtx op; 877272955Srodrigc enum machine_mode mode ATTRIBUTE_UNUSED; 878264790Sbapt{ 879264790Sbapt return (GET_CODE (op) == EQ || GET_CODE (op) == NE); 880264790Sbapt} 881264790Sbapt 882264790Sbapt/* Return 1 if this is a comparison operator, but not an EQ, NE, GEU, 883264790Sbapt or LTU for non-floating-point. We handle those specially. */ 884264790Sbapt 885264790Sbaptint 886272955Srodrigcnormal_comp_operator (op, mode) 887264790Sbapt rtx op; 888264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 889264790Sbapt{ 890264790Sbapt enum rtx_code code = GET_CODE (op); 891264790Sbapt 892264790Sbapt if (GET_RTX_CLASS (code) != '<') 893264790Sbapt return 0; 894264790Sbapt 895272955Srodrigc if (GET_MODE (XEXP (op, 0)) == CCFPmode 896264790Sbapt || GET_MODE (XEXP (op, 0)) == CCFPEmode) 897264790Sbapt return 1; 898264790Sbapt 899264790Sbapt return (code != NE && code != EQ && code != GEU && code != LTU); 900264790Sbapt} 901264790Sbapt 902264790Sbapt/* Return 1 if this is a comparison operator. This allows the use of 903264790Sbapt MATCH_OPERATOR to recognize all the branch insns. */ 904272955Srodrigc 905264790Sbaptint 906264790Sbaptnoov_compare_op (op, mode) 907264790Sbapt register rtx op; 908264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 909264790Sbapt{ 910264790Sbapt enum rtx_code code = GET_CODE (op); 911264790Sbapt 912264790Sbapt if (GET_RTX_CLASS (code) != '<') 913272955Srodrigc return 0; 914264790Sbapt 915264790Sbapt if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode 916264790Sbapt || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 917264790Sbapt /* These are the only branches which work with CC_NOOVmode. */ 918264790Sbapt return (code == EQ || code == NE || code == GE || code == LT); 919264790Sbapt return 1; 920264790Sbapt} 921264790Sbapt 922272955Srodrigc/* Return 1 if this is a 64-bit comparison operator. This allows the use of 923264790Sbapt MATCH_OPERATOR to recognize all the branch insns. */ 924264790Sbapt 925264790Sbaptint 926264790Sbaptnoov_compare64_op (op, mode) 927264790Sbapt register rtx op; 928264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 929264790Sbapt{ 930264790Sbapt enum rtx_code code = GET_CODE (op); 931272955Srodrigc 932264790Sbapt if (! TARGET_V9) 933264790Sbapt return 0; 934264790Sbapt 935264790Sbapt if (GET_RTX_CLASS (code) != '<') 936264790Sbapt return 0; 937264790Sbapt 938264790Sbapt if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode) 939264790Sbapt /* These are the only branches which work with CCX_NOOVmode. */ 940272955Srodrigc return (code == EQ || code == NE || code == GE || code == LT); 941264790Sbapt return (GET_MODE (XEXP (op, 0)) == CCXmode); 942264790Sbapt} 943264790Sbapt 944264790Sbapt/* Nonzero if OP is a comparison operator suitable for use in v9 945264790Sbapt conditional move or branch on register contents instructions. */ 946264790Sbapt 947264790Sbaptint 948264790Sbaptv9_regcmp_op (op, mode) 949264790Sbapt register rtx op; 950272955Srodrigc enum machine_mode mode ATTRIBUTE_UNUSED; 951264790Sbapt{ 952264790Sbapt enum rtx_code code = GET_CODE (op); 953264790Sbapt 954264790Sbapt if (GET_RTX_CLASS (code) != '<') 955264790Sbapt return 0; 956264790Sbapt 957264790Sbapt return v9_regcmp_p (code); 958264790Sbapt} 959272955Srodrigc 960264790Sbapt/* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */ 961264790Sbapt 962264790Sbaptint 963264790Sbaptextend_op (op, mode) 964264790Sbapt rtx op; 965264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 966264790Sbapt{ 967264790Sbapt return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND; 968272955Srodrigc} 969264790Sbapt 970264790Sbapt/* Return nonzero if OP is an operator of mode MODE which can set 971264790Sbapt the condition codes explicitly. We do not include PLUS and MINUS 972264790Sbapt because these require CC_NOOVmode, which we handle explicitly. */ 973264790Sbapt 974264790Sbaptint 975264790Sbaptcc_arithop (op, mode) 976264790Sbapt rtx op; 977272955Srodrigc enum machine_mode mode ATTRIBUTE_UNUSED; 978264790Sbapt{ 979264790Sbapt if (GET_CODE (op) == AND 980264790Sbapt || GET_CODE (op) == IOR 981264790Sbapt || GET_CODE (op) == XOR) 982264790Sbapt return 1; 983264790Sbapt 984264790Sbapt return 0; 985264790Sbapt} 986272955Srodrigc 987264790Sbapt/* Return nonzero if OP is an operator of mode MODE which can bitwise 988264790Sbapt complement its second operand and set the condition codes explicitly. */ 989264790Sbapt 990264790Sbaptint 991264790Sbaptcc_arithopn (op, mode) 992264790Sbapt rtx op; 993264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 994264790Sbapt{ 995272955Srodrigc /* XOR is not here because combine canonicalizes (xor (not ...) ...) 996264790Sbapt and (xor ... (not ...)) to (not (xor ...)). */ 997264790Sbapt return (GET_CODE (op) == AND 998264790Sbapt || GET_CODE (op) == IOR); 999264790Sbapt} 1000264790Sbapt 1001264790Sbapt/* Return true if OP is a register, or is a CONST_INT that can fit in a 1002264790Sbapt signed 13 bit immediate field. This is an acceptable SImode operand for 1003264790Sbapt most 3 address instructions. */ 1004272955Srodrigc 1005264790Sbaptint 1006264790Sbaptarith_operand (op, mode) 1007264790Sbapt rtx op; 1008264790Sbapt enum machine_mode mode; 1009264790Sbapt{ 1010264790Sbapt if (register_operand (op, mode)) 1011264790Sbapt return 1; 1012264790Sbapt if (GET_CODE (op) != CONST_INT) 1013272955Srodrigc return 0; 1014264790Sbapt return SMALL_INT32 (op); 1015264790Sbapt} 1016264790Sbapt 1017264790Sbapt/* Return true if OP is a constant 4096 */ 1018264790Sbapt 1019264790Sbaptint 1020264790Sbaptarith_4096_operand (op, mode) 1021264790Sbapt rtx op; 1022272955Srodrigc enum machine_mode mode ATTRIBUTE_UNUSED; 1023264790Sbapt{ 1024264790Sbapt if (GET_CODE (op) != CONST_INT) 1025264790Sbapt return 0; 1026264790Sbapt else 1027264790Sbapt return INTVAL (op) == 4096; 1028264790Sbapt} 1029264790Sbapt 1030264790Sbapt/* Return true if OP is suitable as second operand for add/sub */ 1031272955Srodrigc 1032264790Sbaptint 1033264790Sbaptarith_add_operand (op, mode) 1034264790Sbapt rtx op; 1035264790Sbapt enum machine_mode mode; 1036264790Sbapt{ 1037264790Sbapt return arith_operand (op, mode) || arith_4096_operand (op, mode); 1038264790Sbapt} 1039264790Sbapt 1040272955Srodrigc/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the 1041264790Sbapt immediate field of OR and XOR instructions. Used for 64-bit 1042264790Sbapt constant formation patterns. */ 1043264790Sbaptint 1044264790Sbaptconst64_operand (op, mode) 1045264790Sbapt rtx op; 1046264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 1047264790Sbapt{ 1048264790Sbapt return ((GET_CODE (op) == CONST_INT 1049272955Srodrigc && SPARC_SIMM13_P (INTVAL (op))) 1050264790Sbapt#if HOST_BITS_PER_WIDE_INT != 64 1051264790Sbapt || (GET_CODE (op) == CONST_DOUBLE 1052264790Sbapt && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1053264790Sbapt && (CONST_DOUBLE_HIGH (op) == 1054264790Sbapt ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ? 1055264790Sbapt (HOST_WIDE_INT)-1 : 0))) 1056264790Sbapt#endif 1057264790Sbapt ); 1058272955Srodrigc} 1059264790Sbapt 1060264790Sbapt/* The same, but only for sethi instructions. */ 1061264790Sbaptint 1062264790Sbaptconst64_high_operand (op, mode) 1063264790Sbapt rtx op; 1064264790Sbapt enum machine_mode mode; 1065264790Sbapt{ 1066264790Sbapt return ((GET_CODE (op) == CONST_INT 1067272955Srodrigc && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1068264790Sbapt && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1069264790Sbapt ) 1070264790Sbapt || (GET_CODE (op) == CONST_DOUBLE 1071264790Sbapt && CONST_DOUBLE_HIGH (op) == 0 1072264790Sbapt && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0 1073264790Sbapt && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))); 1074264790Sbapt} 1075264790Sbapt 1076272955Srodrigc/* Return true if OP is a register, or is a CONST_INT that can fit in a 1077264790Sbapt signed 11 bit immediate field. This is an acceptable SImode operand for 1078264790Sbapt the movcc instructions. */ 1079264790Sbapt 1080264790Sbaptint 1081264790Sbaptarith11_operand (op, mode) 1082264790Sbapt rtx op; 1083264790Sbapt enum machine_mode mode; 1084264790Sbapt{ 1085272955Srodrigc return (register_operand (op, mode) 1086264790Sbapt || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op)))); 1087264790Sbapt} 1088264790Sbapt 1089264790Sbapt/* Return true if OP is a register, or is a CONST_INT that can fit in a 1090264790Sbapt signed 10 bit immediate field. This is an acceptable SImode operand for 1091264790Sbapt the movrcc instructions. */ 1092264790Sbapt 1093264790Sbaptint 1094272955Srodrigcarith10_operand (op, mode) 1095264790Sbapt rtx op; 1096264790Sbapt enum machine_mode mode; 1097264790Sbapt{ 1098264790Sbapt return (register_operand (op, mode) 1099264790Sbapt || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op)))); 1100264790Sbapt} 1101264790Sbapt 1102264790Sbapt/* Return true if OP is a register, is a CONST_INT that fits in a 13 bit 1103272955Srodrigc immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit 1104264790Sbapt immediate field. 1105264790Sbapt v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1106264790Sbapt can fit in a 13 bit immediate field. This is an acceptable DImode operand 1107264790Sbapt for most 3 address instructions. */ 1108264790Sbapt 1109264790Sbaptint 1110264790Sbaptarith_double_operand (op, mode) 1111264790Sbapt rtx op; 1112272955Srodrigc enum machine_mode mode; 1113264790Sbapt{ 1114264790Sbapt return (register_operand (op, mode) 1115264790Sbapt || (GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1116264790Sbapt || (! TARGET_ARCH64 1117264790Sbapt && GET_CODE (op) == CONST_DOUBLE 1118264790Sbapt && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1119264790Sbapt && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000) 1120264790Sbapt || (TARGET_ARCH64 1121272955Srodrigc && GET_CODE (op) == CONST_DOUBLE 1122264790Sbapt && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000 1123264790Sbapt && ((CONST_DOUBLE_HIGH (op) == -1 1124264790Sbapt && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000) 1125264790Sbapt || (CONST_DOUBLE_HIGH (op) == 0 1126264790Sbapt && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); 1127264790Sbapt} 1128264790Sbapt 1129264790Sbapt/* Return true if OP is a constant 4096 for DImode on ARCH64 */ 1130272955Srodrigc 1131264790Sbaptint 1132264790Sbaptarith_double_4096_operand (op, mode) 1133264790Sbapt rtx op; 1134264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 1135264790Sbapt{ 1136264790Sbapt return (TARGET_ARCH64 && 1137264790Sbapt ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) || 1138264790Sbapt (GET_CODE (op) == CONST_DOUBLE && 1139272955Srodrigc CONST_DOUBLE_LOW (op) == 4096 && 1140264790Sbapt CONST_DOUBLE_HIGH (op) == 0))); 1141264790Sbapt} 1142264790Sbapt 1143264790Sbapt/* Return true if OP is suitable as second operand for add/sub in DImode */ 1144264790Sbapt 1145264790Sbaptint 1146264790Sbaptarith_double_add_operand (op, mode) 1147264790Sbapt rtx op; 1148272955Srodrigc enum machine_mode mode; 1149264790Sbapt{ 1150264790Sbapt return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode); 1151264790Sbapt} 1152264790Sbapt 1153264790Sbapt/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1154264790Sbapt can fit in an 11 bit immediate field. This is an acceptable DImode 1155264790Sbapt operand for the movcc instructions. */ 1156264790Sbapt/* ??? Replace with arith11_operand? */ 1157272955Srodrigc 1158264790Sbaptint 1159264790Sbaptarith11_double_operand (op, mode) 1160264790Sbapt rtx op; 1161264790Sbapt enum machine_mode mode; 1162264790Sbapt{ 1163264790Sbapt return (register_operand (op, mode) 1164264790Sbapt || (GET_CODE (op) == CONST_DOUBLE 1165264790Sbapt && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1166272955Srodrigc && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800 1167264790Sbapt && ((CONST_DOUBLE_HIGH (op) == -1 1168264790Sbapt && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400) 1169264790Sbapt || (CONST_DOUBLE_HIGH (op) == 0 1170264790Sbapt && (CONST_DOUBLE_LOW (op) & 0x400) == 0))) 1171264790Sbapt || (GET_CODE (op) == CONST_INT 1172264790Sbapt && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1173264790Sbapt && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800)); 1174264790Sbapt} 1175272955Srodrigc 1176264790Sbapt/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that 1177264790Sbapt can fit in an 10 bit immediate field. This is an acceptable DImode 1178264790Sbapt operand for the movrcc instructions. */ 1179264790Sbapt/* ??? Replace with arith10_operand? */ 1180264790Sbapt 1181264790Sbaptint 1182264790Sbaptarith10_double_operand (op, mode) 1183264790Sbapt rtx op; 1184272955Srodrigc enum machine_mode mode; 1185264790Sbapt{ 1186264790Sbapt return (register_operand (op, mode) 1187264790Sbapt || (GET_CODE (op) == CONST_DOUBLE 1188264790Sbapt && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1189264790Sbapt && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400 1190264790Sbapt && ((CONST_DOUBLE_HIGH (op) == -1 1191264790Sbapt && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200) 1192264790Sbapt || (CONST_DOUBLE_HIGH (op) == 0 1193272955Srodrigc && (CONST_DOUBLE_LOW (op) & 0x200) == 0))) 1194264790Sbapt || (GET_CODE (op) == CONST_INT 1195264790Sbapt && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode) 1196264790Sbapt && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400)); 1197264790Sbapt} 1198264790Sbapt 1199264790Sbapt/* Return truth value of whether OP is an integer which fits the 1200264790Sbapt range constraining immediate operands in most three-address insns, 1201264790Sbapt which have a 13 bit immediate field. */ 1202264790Sbapt 1203264790Sbaptint 1204264790Sbaptsmall_int (op, mode) 1205264790Sbapt rtx op; 1206272955Srodrigc enum machine_mode mode ATTRIBUTE_UNUSED; 1207264790Sbapt{ 1208264790Sbapt return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); 1209272955Srodrigc} 1210272955Srodrigc 1211264790Sbaptint 1212264790Sbaptsmall_int_or_double (op, mode) 1213264790Sbapt rtx op; 1214264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 1215264790Sbapt{ 1216264790Sbapt return ((GET_CODE (op) == CONST_INT && SMALL_INT (op)) 1217264790Sbapt || (GET_CODE (op) == CONST_DOUBLE 1218264790Sbapt && CONST_DOUBLE_HIGH (op) == 0 1219264790Sbapt && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))); 1220264790Sbapt} 1221264790Sbapt 1222264790Sbapt/* Recognize operand values for the umul instruction. That instruction sign 1223264790Sbapt extends immediate values just like all other sparc instructions, but 1224264790Sbapt interprets the extended result as an unsigned number. */ 1225264790Sbapt 1226264790Sbaptint 1227264790Sbaptuns_small_int (op, mode) 1228264790Sbapt rtx op; 1229264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 1230264790Sbapt{ 1231264790Sbapt#if HOST_BITS_PER_WIDE_INT > 32 1232264790Sbapt /* All allowed constants will fit a CONST_INT. */ 1233264790Sbapt return (GET_CODE (op) == CONST_INT 1234264790Sbapt && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) 1235264790Sbapt || (INTVAL (op) >= 0xFFFFF000 1236264790Sbapt && INTVAL (op) <= 0xFFFFFFFF))); 1237264790Sbapt#else 1238264790Sbapt return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) 1239264790Sbapt || (GET_CODE (op) == CONST_DOUBLE 1240264790Sbapt && CONST_DOUBLE_HIGH (op) == 0 1241264790Sbapt && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); 1242264790Sbapt#endif 1243264790Sbapt} 1244264790Sbapt 1245264790Sbaptint 1246264790Sbaptuns_arith_operand (op, mode) 1247264790Sbapt rtx op; 1248264790Sbapt enum machine_mode mode; 1249264790Sbapt{ 1250264790Sbapt return register_operand (op, mode) || uns_small_int (op, mode); 1251264790Sbapt} 1252264790Sbapt 1253264790Sbapt/* Return truth value of statement that OP is a call-clobbered register. */ 1254264790Sbaptint 1255264790Sbaptclobbered_register (op, mode) 1256264790Sbapt rtx op; 1257264790Sbapt enum machine_mode mode ATTRIBUTE_UNUSED; 1258264790Sbapt{ 1259264790Sbapt return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]); 1260264790Sbapt} 1261264790Sbapt 1262264790Sbapt/* Return 1 if OP is a valid operand for the source of a move insn. */ 1263264790Sbapt 1264264790Sbaptint 1265264790Sbaptinput_operand (op, mode) 1266264790Sbapt rtx op; 1267264790Sbapt enum machine_mode mode; 1268264790Sbapt{ 1269264790Sbapt /* If both modes are non-void they must be the same. */ 1270264790Sbapt if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op)) 1271264790Sbapt return 0; 1272264790Sbapt 1273264790Sbapt /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ 1274264790Sbapt if (GET_CODE (op) == CONST && GET_CODE (XEXP (op, 0)) == CONSTANT_P_RTX) 1275264790Sbapt return 1; 1276264790Sbapt 1277264790Sbapt /* Allow any one instruction integer constant, and all CONST_INT 1278264790Sbapt variants when we are working in DImode and !arch64. */ 1279264790Sbapt if (GET_MODE_CLASS (mode) == MODE_INT 1280264790Sbapt && ((GET_CODE (op) == CONST_INT 1281264790Sbapt && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode)) 1282264790Sbapt || SPARC_SIMM13_P (INTVAL (op)) 1283264790Sbapt || (mode == DImode 1284264790Sbapt && ! TARGET_ARCH64))) 1285264790Sbapt || (TARGET_ARCH64 1286264790Sbapt && GET_CODE (op) == CONST_DOUBLE 1287264790Sbapt && ((CONST_DOUBLE_HIGH (op) == 0 1288264790Sbapt && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))) 1289264790Sbapt || 1290264790Sbapt#if HOST_BITS_PER_WIDE_INT == 64 1291264790Sbapt (CONST_DOUBLE_HIGH (op) == 0 1292264790Sbapt && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))) 1293264790Sbapt#else 1294264790Sbapt (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)) 1295264790Sbapt && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0 1296264790Sbapt && CONST_DOUBLE_HIGH (op) == 0) 1297264790Sbapt || (CONST_DOUBLE_HIGH (op) == -1 1298264790Sbapt && CONST_DOUBLE_LOW (op) & 0x80000000) != 0)) 1299264790Sbapt#endif 1300264790Sbapt )))) 1301264790Sbapt return 1; 1302264790Sbapt 1303264790Sbapt /* If !arch64 and this is a DImode const, allow it so that 1304264790Sbapt the splits can be generated. */ 1305264790Sbapt if (! TARGET_ARCH64 1306264790Sbapt && mode == DImode 1307264790Sbapt && GET_CODE (op) == CONST_DOUBLE) 1308264790Sbapt return 1; 1309264790Sbapt 1310264790Sbapt if (register_operand (op, mode)) 1311264790Sbapt return 1; 1312264790Sbapt 1313264790Sbapt if (GET_MODE_CLASS (mode) == MODE_FLOAT 1314264790Sbapt && GET_CODE (op) == CONST_DOUBLE) 1315264790Sbapt return 1; 1316264790Sbapt 1317264790Sbapt /* If this is a SUBREG, look inside so that we handle 1318264790Sbapt paradoxical ones. */ 1319264790Sbapt if (GET_CODE (op) == SUBREG) 1320264790Sbapt op = SUBREG_REG (op); 1321264790Sbapt 1322264790Sbapt /* Check for valid MEM forms. */ 1323264790Sbapt if (GET_CODE (op) == MEM) 1324264790Sbapt { 1325264790Sbapt rtx inside = XEXP (op, 0); 1326264790Sbapt 1327264790Sbapt if (GET_CODE (inside) == LO_SUM) 1328264790Sbapt { 1329264790Sbapt /* We can't allow these because all of the splits 1330264790Sbapt (eventually as they trickle down into DFmode 1331264790Sbapt splits) require offsettable memory references. */ 1332264790Sbapt if (! TARGET_V9 1333264790Sbapt && GET_MODE (op) == TFmode) 1334264790Sbapt return 0; 1335264790Sbapt 1336264790Sbapt return (register_operand (XEXP (inside, 0), Pmode) 1337264790Sbapt && CONSTANT_P (XEXP (inside, 1))); 1338264790Sbapt } 1339264790Sbapt return memory_address_p (mode, inside); 1340264790Sbapt } 1341264790Sbapt 1342264790Sbapt return 0; 1343264790Sbapt} 1344264790Sbapt 1345264790Sbapt 1346264790Sbapt/* We know it can't be done in one insn when we get here, 1347264790Sbapt the movsi expander guarentees this. */ 1348264790Sbaptvoid 1349264790Sbaptsparc_emit_set_const32 (op0, op1) 1350264790Sbapt rtx op0; 1351264790Sbapt rtx op1; 1352264790Sbapt{ 1353264790Sbapt enum machine_mode mode = GET_MODE (op0); 1354264790Sbapt rtx temp; 1355264790Sbapt 1356264790Sbapt if (GET_CODE (op1) == CONST_INT) 1357264790Sbapt { 1358264790Sbapt HOST_WIDE_INT value = INTVAL (op1); 1359264790Sbapt 1360264790Sbapt if (SPARC_SETHI_P (value & GET_MODE_MASK (mode)) 1361264790Sbapt || SPARC_SIMM13_P (value)) 1362264790Sbapt abort (); 1363264790Sbapt } 1364264790Sbapt 1365264790Sbapt /* Full 2-insn decomposition is needed. */ 1366264790Sbapt if (reload_in_progress || reload_completed) 1367264790Sbapt temp = op0; 1368264790Sbapt else 1369264790Sbapt temp = gen_reg_rtx (mode); 1370264790Sbapt 1371264790Sbapt if (GET_CODE (op1) == CONST_INT) 1372264790Sbapt { 1373264790Sbapt /* Emit them as real moves instead of a HIGH/LO_SUM, 1374264790Sbapt this way CSE can see everything and reuse intermediate 1375264790Sbapt values if it wants. */ 1376264790Sbapt if (TARGET_ARCH64 1377264790Sbapt && HOST_BITS_PER_WIDE_INT != 64 1378264790Sbapt && (INTVAL (op1) & 0x80000000) != 0) 1379264790Sbapt emit_insn (gen_rtx_SET 1380264790Sbapt (VOIDmode, temp, 1381264790Sbapt gen_rtx_CONST_DOUBLE (VOIDmode, 1382264790Sbapt INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, 1383264790Sbapt 0))); 1384264790Sbapt else 1385264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, temp, 1386264790Sbapt GEN_INT (INTVAL (op1) 1387264790Sbapt & ~(HOST_WIDE_INT)0x3ff))); 1388264790Sbapt 1389264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, 1390264790Sbapt op0, 1391264790Sbapt gen_rtx_IOR (mode, temp, 1392264790Sbapt GEN_INT (INTVAL (op1) & 0x3ff)))); 1393264790Sbapt } 1394272955Srodrigc else 1395272955Srodrigc { 1396264790Sbapt /* A symbol, emit in the traditional way. */ 1397264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, temp, 1398264790Sbapt gen_rtx_HIGH (mode, op1))); 1399264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, 1400264790Sbapt op0, gen_rtx_LO_SUM (mode, temp, op1))); 1401264790Sbapt 1402264790Sbapt } 1403264790Sbapt} 1404264790Sbapt 1405264790Sbapt 1406264790Sbapt/* Sparc-v9 code-model support. */ 1407264790Sbaptvoid 1408264790Sbaptsparc_emit_set_symbolic_const64 (op0, op1, temp1) 1409264790Sbapt rtx op0; 1410264790Sbapt rtx op1; 1411264790Sbapt rtx temp1; 1412264790Sbapt{ 1413264790Sbapt rtx ti_temp1 = 0; 1414264790Sbapt 1415264790Sbapt if (temp1 && GET_MODE (temp1) == TImode) 1416264790Sbapt { 1417264790Sbapt ti_temp1 = temp1; 1418264790Sbapt temp1 = gen_rtx_REG (DImode, REGNO (temp1)); 1419264790Sbapt } 1420264790Sbapt 1421264790Sbapt switch (sparc_cmodel) 1422264790Sbapt { 1423264790Sbapt case CM_MEDLOW: 1424264790Sbapt /* The range spanned by all instructions in the object is less 1425264790Sbapt than 2^31 bytes (2GB) and the distance from any instruction 1426264790Sbapt to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1427264790Sbapt than 2^31 bytes (2GB). 1428264790Sbapt 1429264790Sbapt The executable must be in the low 4TB of the virtual address 1430264790Sbapt space. 1431264790Sbapt 1432264790Sbapt sethi %hi(symbol), %temp 1433264790Sbapt or %temp, %lo(symbol), %reg */ 1434264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); 1435264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); 1436264790Sbapt break; 1437264790Sbapt 1438264790Sbapt case CM_MEDMID: 1439264790Sbapt /* The range spanned by all instructions in the object is less 1440264790Sbapt than 2^31 bytes (2GB) and the distance from any instruction 1441264790Sbapt to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1442264790Sbapt than 2^31 bytes (2GB). 1443264790Sbapt 1444264790Sbapt The executable must be in the low 16TB of the virtual address 1445264790Sbapt space. 1446264790Sbapt 1447264790Sbapt sethi %h44(symbol), %temp1 1448264790Sbapt or %temp1, %m44(symbol), %temp2 1449264790Sbapt sllx %temp2, 12, %temp3 1450264790Sbapt or %temp3, %l44(symbol), %reg */ 1451264790Sbapt emit_insn (gen_seth44 (op0, op1)); 1452264790Sbapt emit_insn (gen_setm44 (op0, op0, op1)); 1453264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, temp1, 1454264790Sbapt gen_rtx_ASHIFT (DImode, op0, GEN_INT (12)))); 1455264790Sbapt emit_insn (gen_setl44 (op0, temp1, op1)); 1456264790Sbapt break; 1457264790Sbapt 1458264790Sbapt case CM_MEDANY: 1459264790Sbapt /* The range spanned by all instructions in the object is less 1460264790Sbapt than 2^31 bytes (2GB) and the distance from any instruction 1461264790Sbapt to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1462264790Sbapt than 2^31 bytes (2GB). 1463264790Sbapt 1464264790Sbapt The executable can be placed anywhere in the virtual address 1465264790Sbapt space. 1466264790Sbapt 1467264790Sbapt sethi %hh(symbol), %temp1 1468264790Sbapt sethi %lm(symbol), %temp2 1469264790Sbapt or %temp1, %hm(symbol), %temp3 1470264790Sbapt or %temp2, %lo(symbol), %temp4 1471264790Sbapt sllx %temp3, 32, %temp5 1472264790Sbapt or %temp4, %temp5, %reg */ 1473264790Sbapt 1474264790Sbapt /* It is possible that one of the registers we got for operands[2] 1475264790Sbapt might coincide with that of operands[0] (which is why we made 1476264790Sbapt it TImode). Pick the other one to use as our scratch. */ 1477264790Sbapt if (rtx_equal_p (temp1, op0)) 1478264790Sbapt { 1479264790Sbapt if (ti_temp1) 1480264790Sbapt temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); 1481264790Sbapt else 1482264790Sbapt abort(); 1483264790Sbapt } 1484264790Sbapt 1485264790Sbapt emit_insn (gen_sethh (op0, op1)); 1486264790Sbapt emit_insn (gen_setlm (temp1, op1)); 1487264790Sbapt emit_insn (gen_sethm (op0, op0, op1)); 1488264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1489264790Sbapt gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); 1490264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1491272955Srodrigc gen_rtx_PLUS (DImode, op0, temp1))); 1492264790Sbapt emit_insn (gen_setlo (op0, op0, op1)); 1493272955Srodrigc break; 1494264790Sbapt 1495264790Sbapt case CM_EMBMEDANY: 1496272955Srodrigc /* Old old old backwards compatibility kruft here. 1497264790Sbapt Essentially it is MEDLOW with a fixed 64-bit 1498264790Sbapt virtual base added to all data segment addresses. 1499264790Sbapt Text-segment stuff is computed like MEDANY, we can't 1500264790Sbapt reuse the code above because the relocation knobs 1501264790Sbapt look different. 1502264790Sbapt 1503264790Sbapt Data segment: sethi %hi(symbol), %temp1 1504264790Sbapt or %temp1, %lo(symbol), %temp2 1505264790Sbapt add %temp2, EMBMEDANY_BASE_REG, %reg 1506264790Sbapt 1507264790Sbapt Text segment: sethi %uhi(symbol), %temp1 1508264790Sbapt sethi %hi(symbol), %temp2 1509264790Sbapt or %temp1, %ulo(symbol), %temp3 1510264790Sbapt or %temp2, %lo(symbol), %temp4 1511264790Sbapt sllx %temp3, 32, %temp5 1512264790Sbapt or %temp4, %temp5, %reg */ 1513264790Sbapt if (data_segment_operand (op1, GET_MODE (op1))) 1514264790Sbapt { 1515264790Sbapt emit_insn (gen_embmedany_sethi (temp1, op1)); 1516264790Sbapt emit_insn (gen_embmedany_brsum (op0, temp1)); 1517264790Sbapt emit_insn (gen_embmedany_losum (op0, op0, op1)); 1518264790Sbapt } 1519264790Sbapt else 1520264790Sbapt { 1521264790Sbapt /* It is possible that one of the registers we got for operands[2] 1522264790Sbapt might coincide with that of operands[0] (which is why we made 1523264790Sbapt it TImode). Pick the other one to use as our scratch. */ 1524264790Sbapt if (rtx_equal_p (temp1, op0)) 1525264790Sbapt { 1526264790Sbapt if (ti_temp1) 1527264790Sbapt temp1 = gen_rtx_REG (DImode, REGNO (temp1) + 1); 1528264790Sbapt else 1529264790Sbapt abort(); 1530264790Sbapt } 1531264790Sbapt 1532264790Sbapt emit_insn (gen_embmedany_textuhi (op0, op1)); 1533264790Sbapt emit_insn (gen_embmedany_texthi (temp1, op1)); 1534264790Sbapt emit_insn (gen_embmedany_textulo (op0, op0, op1)); 1535264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1536264790Sbapt gen_rtx_ASHIFT (DImode, op0, GEN_INT (32)))); 1537264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1538264790Sbapt gen_rtx_PLUS (DImode, op0, temp1))); 1539264790Sbapt emit_insn (gen_embmedany_textlo (op0, op0, op1)); 1540264790Sbapt } 1541264790Sbapt break; 1542264790Sbapt 1543264790Sbapt default: 1544264790Sbapt abort(); 1545264790Sbapt } 1546264790Sbapt} 1547264790Sbapt 1548264790Sbapt/* These avoid problems when cross compiling. If we do not 1549264790Sbapt go through all this hair then the optimizer will see 1550264790Sbapt invalid REG_EQUAL notes or in some cases none at all. */ 1551272955Srodrigcstatic void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT)); 1552264790Sbaptstatic rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT)); 1553264790Sbaptstatic rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT)); 1554264790Sbaptstatic rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT)); 1555264790Sbapt 1556264790Sbapt#if HOST_BITS_PER_WIDE_INT == 64 1557264790Sbapt#define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff) 1558264790Sbapt#define GEN_INT64(__x) GEN_INT (__x) 1559264790Sbapt#else 1560264790Sbapt#define GEN_HIGHINT64(__x) \ 1561264790Sbapt gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & ~(HOST_WIDE_INT)0x3ff, 0) 1562264790Sbapt#define GEN_INT64(__x) \ 1563264790Sbapt gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & 0xffffffff, \ 1564264790Sbapt ((__x) & 0x80000000 \ 1565264790Sbapt ? -1 : 0)) 1566264790Sbapt#endif 1567264790Sbapt 1568264790Sbapt/* The optimizer is not to assume anything about exactly 1569264790Sbapt which bits are set for a HIGH, they are unspecified. 1570264790Sbapt Unfortunately this leads to many missed optimizations 1571264790Sbapt during CSE. We mask out the non-HIGH bits, and matches 1572264790Sbapt a plain movdi, to alleviate this problem. */ 1573264790Sbaptstatic void 1574264790Sbaptsparc_emit_set_safe_HIGH64 (dest, val) 1575264790Sbapt rtx dest; 1576264790Sbapt HOST_WIDE_INT val; 1577264790Sbapt{ 1578264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val))); 1579264790Sbapt} 1580264790Sbapt 1581264790Sbaptstatic rtx 1582264790Sbaptgen_safe_SET64 (dest, val) 1583264790Sbapt rtx dest; 1584264790Sbapt HOST_WIDE_INT val; 1585264790Sbapt{ 1586264790Sbapt return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val)); 1587264790Sbapt} 1588264790Sbapt 1589264790Sbaptstatic rtx 1590264790Sbaptgen_safe_OR64 (src, val) 1591264790Sbapt rtx src; 1592264790Sbapt HOST_WIDE_INT val; 1593264790Sbapt{ 1594264790Sbapt return gen_rtx_IOR (DImode, src, GEN_INT64 (val)); 1595264790Sbapt} 1596264790Sbapt 1597264790Sbaptstatic rtx 1598264790Sbaptgen_safe_XOR64 (src, val) 1599264790Sbapt rtx src; 1600264790Sbapt HOST_WIDE_INT val; 1601264790Sbapt{ 1602264790Sbapt return gen_rtx_XOR (DImode, src, GEN_INT64 (val)); 1603264790Sbapt} 1604264790Sbapt 1605264790Sbapt/* Worker routines for 64-bit constant formation on arch64. 1606264790Sbapt One of the key things to be doing in these emissions is 1607264790Sbapt to create as many temp REGs as possible. This makes it 1608264790Sbapt possible for half-built constants to be used later when 1609264790Sbapt such values are similar to something required later on. 1610264790Sbapt Without doing this, the optimizer cannot see such 1611264790Sbapt opportunities. */ 1612264790Sbapt 1613264790Sbaptstatic void sparc_emit_set_const64_quick1 1614264790Sbapt PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int)); 1615264790Sbapt 1616264790Sbaptstatic void 1617264790Sbaptsparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg) 1618264790Sbapt rtx op0; 1619264790Sbapt rtx temp; 1620264790Sbapt unsigned HOST_WIDE_INT low_bits; 1621264790Sbapt int is_neg; 1622264790Sbapt{ 1623264790Sbapt unsigned HOST_WIDE_INT high_bits; 1624264790Sbapt 1625264790Sbapt if (is_neg) 1626264790Sbapt high_bits = (~low_bits) & 0xffffffff; 1627264790Sbapt else 1628264790Sbapt high_bits = low_bits; 1629264790Sbapt 1630264790Sbapt sparc_emit_set_safe_HIGH64 (temp, high_bits); 1631264790Sbapt if (!is_neg) 1632264790Sbapt { 1633264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1634264790Sbapt gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1635264790Sbapt } 1636264790Sbapt else 1637264790Sbapt { 1638264790Sbapt /* If we are XOR'ing with -1, then we should emit a one's complement 1639264790Sbapt instead. This way the combiner will notice logical operations 1640264790Sbapt such as ANDN later on and substitute. */ 1641264790Sbapt if ((low_bits & 0x3ff) == 0x3ff) 1642264790Sbapt { 1643264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1644264790Sbapt gen_rtx_NOT (DImode, temp))); 1645272955Srodrigc } 1646264790Sbapt else 1647272955Srodrigc { 1648264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1649264790Sbapt gen_safe_XOR64 (temp, 1650272955Srodrigc (-(HOST_WIDE_INT)0x400 1651264790Sbapt | (low_bits & 0x3ff))))); 1652272955Srodrigc } 1653264790Sbapt } 1654264790Sbapt} 1655264790Sbapt 1656264790Sbaptstatic void sparc_emit_set_const64_quick2 1657264790Sbapt PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, 1658264790Sbapt unsigned HOST_WIDE_INT, int)); 1659264790Sbapt 1660264790Sbaptstatic void 1661272955Srodrigcsparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count) 1662264790Sbapt rtx op0; 1663272955Srodrigc rtx temp; 1664264790Sbapt unsigned HOST_WIDE_INT high_bits; 1665264790Sbapt unsigned HOST_WIDE_INT low_immediate; 1666272955Srodrigc int shift_count; 1667264790Sbapt{ 1668264790Sbapt rtx temp2 = op0; 1669264790Sbapt 1670264790Sbapt if ((high_bits & 0xfffffc00) != 0) 1671264790Sbapt { 1672264790Sbapt sparc_emit_set_safe_HIGH64 (temp, high_bits); 1673264790Sbapt if ((high_bits & ~0xfffffc00) != 0) 1674264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1675264790Sbapt gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1676264790Sbapt else 1677264790Sbapt temp2 = temp; 1678264790Sbapt } 1679264790Sbapt else 1680264790Sbapt { 1681264790Sbapt emit_insn (gen_safe_SET64 (temp, high_bits)); 1682264790Sbapt temp2 = temp; 1683264790Sbapt } 1684264790Sbapt 1685264790Sbapt /* Now shift it up into place. */ 1686264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1687264790Sbapt gen_rtx_ASHIFT (DImode, temp2, 1688264790Sbapt GEN_INT (shift_count)))); 1689264790Sbapt 1690264790Sbapt /* If there is a low immediate part piece, finish up by 1691264790Sbapt putting that in as well. */ 1692264790Sbapt if (low_immediate != 0) 1693264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1694264790Sbapt gen_safe_OR64 (op0, low_immediate))); 1695264790Sbapt} 1696272955Srodrigc 1697264790Sbaptstatic void sparc_emit_set_const64_longway 1698272955Srodrigc PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); 1699264790Sbapt 1700264790Sbapt/* Full 64-bit constant decomposition. Even though this is the 1701272955Srodrigc 'worst' case, we still optimize a few things away. */ 1702264790Sbaptstatic void 1703264790Sbaptsparc_emit_set_const64_longway (op0, temp, high_bits, low_bits) 1704264790Sbapt rtx op0; 1705264790Sbapt rtx temp; 1706264790Sbapt unsigned HOST_WIDE_INT high_bits; 1707264790Sbapt unsigned HOST_WIDE_INT low_bits; 1708264790Sbapt{ 1709264790Sbapt rtx sub_temp; 1710264790Sbapt 1711264790Sbapt if (reload_in_progress || reload_completed) 1712264790Sbapt sub_temp = op0; 1713264790Sbapt else 1714264790Sbapt sub_temp = gen_reg_rtx (DImode); 1715264790Sbapt 1716264790Sbapt if ((high_bits & 0xfffffc00) != 0) 1717264790Sbapt { 1718264790Sbapt sparc_emit_set_safe_HIGH64 (temp, high_bits); 1719264790Sbapt if ((high_bits & ~0xfffffc00) != 0) 1720264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, 1721264790Sbapt sub_temp, 1722264790Sbapt gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1723264790Sbapt else 1724264790Sbapt sub_temp = temp; 1725264790Sbapt } 1726264790Sbapt else 1727264790Sbapt { 1728264790Sbapt emit_insn (gen_safe_SET64 (temp, high_bits)); 1729264790Sbapt sub_temp = temp; 1730264790Sbapt } 1731264790Sbapt 1732264790Sbapt if (!reload_in_progress && !reload_completed) 1733264790Sbapt { 1734264790Sbapt rtx temp2 = gen_reg_rtx (DImode); 1735264790Sbapt rtx temp3 = gen_reg_rtx (DImode); 1736264790Sbapt rtx temp4 = gen_reg_rtx (DImode); 1737264790Sbapt 1738264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, temp4, 1739264790Sbapt gen_rtx_ASHIFT (DImode, sub_temp, 1740264790Sbapt GEN_INT (32)))); 1741264790Sbapt 1742264790Sbapt sparc_emit_set_safe_HIGH64 (temp2, low_bits); 1743264790Sbapt if ((low_bits & ~0xfffffc00) != 0) 1744264790Sbapt { 1745264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, temp3, 1746264790Sbapt gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); 1747264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1748264790Sbapt gen_rtx_PLUS (DImode, temp4, temp3))); 1749264790Sbapt } 1750264790Sbapt else 1751264790Sbapt { 1752264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1753264790Sbapt gen_rtx_PLUS (DImode, temp4, temp2))); 1754264790Sbapt } 1755264790Sbapt } 1756264790Sbapt else 1757264790Sbapt { 1758264790Sbapt rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); 1759264790Sbapt rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); 1760264790Sbapt rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); 1761264790Sbapt int to_shift = 12; 1762264790Sbapt 1763264790Sbapt /* We are in the middle of reload, so this is really 1764264790Sbapt painful. However we do still make an attempt to 1765264790Sbapt avoid emitting truly stupid code. */ 1766264790Sbapt if (low1 != const0_rtx) 1767264790Sbapt { 1768264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1769264790Sbapt gen_rtx_ASHIFT (DImode, sub_temp, 1770264790Sbapt GEN_INT (to_shift)))); 1771264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1772264790Sbapt gen_rtx_IOR (DImode, op0, low1))); 1773264790Sbapt sub_temp = op0; 1774264790Sbapt to_shift = 12; 1775264790Sbapt } 1776264790Sbapt else 1777264790Sbapt { 1778264790Sbapt to_shift += 12; 1779264790Sbapt } 1780264790Sbapt if (low2 != const0_rtx) 1781264790Sbapt { 1782264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1783264790Sbapt gen_rtx_ASHIFT (DImode, sub_temp, 1784264790Sbapt GEN_INT (to_shift)))); 1785264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1786264790Sbapt gen_rtx_IOR (DImode, op0, low2))); 1787264790Sbapt sub_temp = op0; 1788264790Sbapt to_shift = 8; 1789264790Sbapt } 1790264790Sbapt else 1791264790Sbapt { 1792264790Sbapt to_shift += 8; 1793264790Sbapt } 1794264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1795264790Sbapt gen_rtx_ASHIFT (DImode, sub_temp, 1796264790Sbapt GEN_INT (to_shift)))); 1797264790Sbapt if (low3 != const0_rtx) 1798264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 1799264790Sbapt gen_rtx_IOR (DImode, op0, low3))); 1800264790Sbapt /* phew... */ 1801264790Sbapt } 1802264790Sbapt} 1803264790Sbapt 1804264790Sbapt/* Analyze a 64-bit constant for certain properties. */ 1805264790Sbaptstatic void analyze_64bit_constant 1806264790Sbapt PARAMS ((unsigned HOST_WIDE_INT, 1807264790Sbapt unsigned HOST_WIDE_INT, 1808264790Sbapt int *, int *, int *)); 1809264790Sbapt 1810264790Sbaptstatic void 1811264790Sbaptanalyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp) 1812264790Sbapt unsigned HOST_WIDE_INT high_bits, low_bits; 1813264790Sbapt int *hbsp, *lbsp, *abbasp; 1814264790Sbapt{ 1815264790Sbapt int lowest_bit_set, highest_bit_set, all_bits_between_are_set; 1816264790Sbapt int i; 1817264790Sbapt 1818264790Sbapt lowest_bit_set = highest_bit_set = -1; 1819264790Sbapt i = 0; 1820264790Sbapt do 1821264790Sbapt { 1822264790Sbapt if ((lowest_bit_set == -1) 1823264790Sbapt && ((low_bits >> i) & 1)) 1824264790Sbapt lowest_bit_set = i; 1825264790Sbapt if ((highest_bit_set == -1) 1826264790Sbapt && ((high_bits >> (32 - i - 1)) & 1)) 1827264790Sbapt highest_bit_set = (64 - i - 1); 1828264790Sbapt } 1829264790Sbapt while (++i < 32 1830264790Sbapt && ((highest_bit_set == -1) 1831264790Sbapt || (lowest_bit_set == -1))); 1832264790Sbapt if (i == 32) 1833264790Sbapt { 1834264790Sbapt i = 0; 1835264790Sbapt do 1836264790Sbapt { 1837264790Sbapt if ((lowest_bit_set == -1) 1838264790Sbapt && ((high_bits >> i) & 1)) 1839264790Sbapt lowest_bit_set = i + 32; 1840264790Sbapt if ((highest_bit_set == -1) 1841264790Sbapt && ((low_bits >> (32 - i - 1)) & 1)) 1842264790Sbapt highest_bit_set = 32 - i - 1; 1843264790Sbapt } 1844264790Sbapt while (++i < 32 1845264790Sbapt && ((highest_bit_set == -1) 1846264790Sbapt || (lowest_bit_set == -1))); 1847264790Sbapt } 1848264790Sbapt /* If there are no bits set this should have gone out 1849264790Sbapt as one instruction! */ 1850264790Sbapt if (lowest_bit_set == -1 1851264790Sbapt || highest_bit_set == -1) 1852264790Sbapt abort (); 1853264790Sbapt all_bits_between_are_set = 1; 1854264790Sbapt for (i = lowest_bit_set; i <= highest_bit_set; i++) 1855264790Sbapt { 1856264790Sbapt if (i < 32) 1857264790Sbapt { 1858264790Sbapt if ((low_bits & (1 << i)) != 0) 1859264790Sbapt continue; 1860264790Sbapt } 1861264790Sbapt else 1862264790Sbapt { 1863264790Sbapt if ((high_bits & (1 << (i - 32))) != 0) 1864264790Sbapt continue; 1865264790Sbapt } 1866264790Sbapt all_bits_between_are_set = 0; 1867264790Sbapt break; 1868264790Sbapt } 1869264790Sbapt *hbsp = highest_bit_set; 1870264790Sbapt *lbsp = lowest_bit_set; 1871264790Sbapt *abbasp = all_bits_between_are_set; 1872264790Sbapt} 1873264790Sbapt 1874264790Sbaptstatic int const64_is_2insns 1875264790Sbapt PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT)); 1876264790Sbapt 1877264790Sbaptstatic int 1878264790Sbaptconst64_is_2insns (high_bits, low_bits) 1879264790Sbapt unsigned HOST_WIDE_INT high_bits, low_bits; 1880264790Sbapt{ 1881264790Sbapt int highest_bit_set, lowest_bit_set, all_bits_between_are_set; 1882264790Sbapt 1883264790Sbapt if (high_bits == 0 1884264790Sbapt || high_bits == 0xffffffff) 1885264790Sbapt return 1; 1886264790Sbapt 1887264790Sbapt analyze_64bit_constant (high_bits, low_bits, 1888264790Sbapt &highest_bit_set, &lowest_bit_set, 1889264790Sbapt &all_bits_between_are_set); 1890264790Sbapt 1891264790Sbapt if ((highest_bit_set == 63 1892264790Sbapt || lowest_bit_set == 0) 1893264790Sbapt && all_bits_between_are_set != 0) 1894264790Sbapt return 1; 1895264790Sbapt 1896264790Sbapt if ((highest_bit_set - lowest_bit_set) < 21) 1897264790Sbapt return 1; 1898264790Sbapt 1899264790Sbapt return 0; 1900264790Sbapt} 1901264790Sbapt 1902264790Sbaptstatic unsigned HOST_WIDE_INT create_simple_focus_bits 1903264790Sbapt PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT, 1904264790Sbapt int, int)); 1905264790Sbapt 1906264790Sbaptstatic unsigned HOST_WIDE_INT 1907264790Sbaptcreate_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift) 1908264790Sbapt unsigned HOST_WIDE_INT high_bits, low_bits; 1909264790Sbapt int lowest_bit_set, shift; 1910264790Sbapt{ 1911264790Sbapt HOST_WIDE_INT hi, lo; 1912264790Sbapt 1913264790Sbapt if (lowest_bit_set < 32) 1914264790Sbapt { 1915264790Sbapt lo = (low_bits >> lowest_bit_set) << shift; 1916264790Sbapt hi = ((high_bits << (32 - lowest_bit_set)) << shift); 1917264790Sbapt } 1918264790Sbapt else 1919264790Sbapt { 1920264790Sbapt lo = 0; 1921264790Sbapt hi = ((high_bits >> (lowest_bit_set - 32)) << shift); 1922264790Sbapt } 1923264790Sbapt if (hi & lo) 1924264790Sbapt abort (); 1925264790Sbapt return (hi | lo); 1926264790Sbapt} 1927264790Sbapt 1928264790Sbapt/* Here we are sure to be arch64 and this is an integer constant 1929264790Sbapt being loaded into a register. Emit the most efficient 1930264790Sbapt insn sequence possible. Detection of all the 1-insn cases 1931264790Sbapt has been done already. */ 1932264790Sbaptvoid 1933264790Sbaptsparc_emit_set_const64 (op0, op1) 1934264790Sbapt rtx op0; 1935264790Sbapt rtx op1; 1936264790Sbapt{ 1937264790Sbapt unsigned HOST_WIDE_INT high_bits, low_bits; 1938264790Sbapt int lowest_bit_set, highest_bit_set; 1939264790Sbapt int all_bits_between_are_set; 1940264790Sbapt rtx temp; 1941264790Sbapt 1942264790Sbapt /* Sanity check that we know what we are working with. */ 1943264790Sbapt if (! TARGET_ARCH64) 1944264790Sbapt abort (); 1945264790Sbapt 1946264790Sbapt if (GET_CODE (op0) != SUBREG) 1947264790Sbapt { 1948264790Sbapt if (GET_CODE (op0) != REG 1949264790Sbapt || (REGNO (op0) >= SPARC_FIRST_FP_REG 1950264790Sbapt && REGNO (op0) <= SPARC_LAST_V9_FP_REG)) 1951264790Sbapt abort (); 1952264790Sbapt } 1953264790Sbapt 1954264790Sbapt if (reload_in_progress || reload_completed) 1955264790Sbapt temp = op0; 1956264790Sbapt else 1957264790Sbapt temp = gen_reg_rtx (DImode); 1958264790Sbapt 1959264790Sbapt if (GET_CODE (op1) != CONST_DOUBLE 1960264790Sbapt && GET_CODE (op1) != CONST_INT) 1961264790Sbapt { 1962264790Sbapt sparc_emit_set_symbolic_const64 (op0, op1, temp); 1963264790Sbapt return; 1964264790Sbapt } 1965264790Sbapt 1966264790Sbapt if (GET_CODE (op1) == CONST_DOUBLE) 1967264790Sbapt { 1968264790Sbapt#if HOST_BITS_PER_WIDE_INT == 64 1969264790Sbapt high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff; 1970264790Sbapt low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff; 1971264790Sbapt#else 1972264790Sbapt high_bits = CONST_DOUBLE_HIGH (op1); 1973264790Sbapt low_bits = CONST_DOUBLE_LOW (op1); 1974264790Sbapt#endif 1975264790Sbapt } 1976264790Sbapt else 1977264790Sbapt { 1978264790Sbapt#if HOST_BITS_PER_WIDE_INT == 64 1979264790Sbapt high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); 1980264790Sbapt low_bits = (INTVAL (op1) & 0xffffffff); 1981264790Sbapt#else 1982264790Sbapt high_bits = ((INTVAL (op1) < 0) ? 1983264790Sbapt 0xffffffff : 1984264790Sbapt 0x00000000); 1985264790Sbapt low_bits = INTVAL (op1); 1986264790Sbapt#endif 1987264790Sbapt } 1988264790Sbapt 1989264790Sbapt /* low_bits bits 0 --> 31 1990264790Sbapt high_bits bits 32 --> 63 */ 1991264790Sbapt 1992264790Sbapt analyze_64bit_constant (high_bits, low_bits, 1993264790Sbapt &highest_bit_set, &lowest_bit_set, 1994264790Sbapt &all_bits_between_are_set); 1995264790Sbapt 1996264790Sbapt /* First try for a 2-insn sequence. */ 1997264790Sbapt 1998264790Sbapt /* These situations are preferred because the optimizer can 1999264790Sbapt * do more things with them: 2000264790Sbapt * 1) mov -1, %reg 2001264790Sbapt * sllx %reg, shift, %reg 2002264790Sbapt * 2) mov -1, %reg 2003264790Sbapt * srlx %reg, shift, %reg 2004264790Sbapt * 3) mov some_small_const, %reg 2005264790Sbapt * sllx %reg, shift, %reg 2006264790Sbapt */ 2007264790Sbapt if (((highest_bit_set == 63 2008264790Sbapt || lowest_bit_set == 0) 2009264790Sbapt && all_bits_between_are_set != 0) 2010264790Sbapt || ((highest_bit_set - lowest_bit_set) < 12)) 2011264790Sbapt { 2012264790Sbapt HOST_WIDE_INT the_const = -1; 2013264790Sbapt int shift = lowest_bit_set; 2014264790Sbapt 2015264790Sbapt if ((highest_bit_set != 63 2016264790Sbapt && lowest_bit_set != 0) 2017264790Sbapt || all_bits_between_are_set == 0) 2018264790Sbapt { 2019264790Sbapt the_const = 2020264790Sbapt create_simple_focus_bits (high_bits, low_bits, 2021264790Sbapt lowest_bit_set, 0); 2022264790Sbapt } 2023264790Sbapt else if (lowest_bit_set == 0) 2024264790Sbapt shift = -(63 - highest_bit_set); 2025264790Sbapt 2026264790Sbapt if (! SPARC_SIMM13_P (the_const)) 2027264790Sbapt abort (); 2028264790Sbapt 2029264790Sbapt emit_insn (gen_safe_SET64 (temp, the_const)); 2030264790Sbapt if (shift > 0) 2031264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, 2032264790Sbapt op0, 2033264790Sbapt gen_rtx_ASHIFT (DImode, 2034264790Sbapt temp, 2035264790Sbapt GEN_INT (shift)))); 2036264790Sbapt else if (shift < 0) 2037264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, 2038264790Sbapt op0, 2039264790Sbapt gen_rtx_LSHIFTRT (DImode, 2040264790Sbapt temp, 2041264790Sbapt GEN_INT (-shift)))); 2042264790Sbapt else 2043264790Sbapt abort (); 2044264790Sbapt return; 2045264790Sbapt } 2046264790Sbapt 2047264790Sbapt /* Now a range of 22 or less bits set somewhere. 2048264790Sbapt * 1) sethi %hi(focus_bits), %reg 2049264790Sbapt * sllx %reg, shift, %reg 2050264790Sbapt * 2) sethi %hi(focus_bits), %reg 2051264790Sbapt * srlx %reg, shift, %reg 2052264790Sbapt */ 2053264790Sbapt if ((highest_bit_set - lowest_bit_set) < 21) 2054264790Sbapt { 2055264790Sbapt unsigned HOST_WIDE_INT focus_bits = 2056264790Sbapt create_simple_focus_bits (high_bits, low_bits, 2057264790Sbapt lowest_bit_set, 10); 2058264790Sbapt 2059264790Sbapt if (! SPARC_SETHI_P (focus_bits)) 2060264790Sbapt abort (); 2061264790Sbapt 2062264790Sbapt sparc_emit_set_safe_HIGH64 (temp, focus_bits); 2063264790Sbapt 2064264790Sbapt /* If lowest_bit_set == 10 then a sethi alone could have done it. */ 2065264790Sbapt if (lowest_bit_set < 10) 2066264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, 2067264790Sbapt op0, 2068264790Sbapt gen_rtx_LSHIFTRT (DImode, temp, 2069264790Sbapt GEN_INT (10 - lowest_bit_set)))); 2070264790Sbapt else if (lowest_bit_set > 10) 2071264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, 2072264790Sbapt op0, 2073264790Sbapt gen_rtx_ASHIFT (DImode, temp, 2074264790Sbapt GEN_INT (lowest_bit_set - 10)))); 2075264790Sbapt else 2076264790Sbapt abort (); 2077264790Sbapt return; 2078264790Sbapt } 2079264790Sbapt 2080264790Sbapt /* 1) sethi %hi(low_bits), %reg 2081264790Sbapt * or %reg, %lo(low_bits), %reg 2082264790Sbapt * 2) sethi %hi(~low_bits), %reg 2083264790Sbapt * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg 2084264790Sbapt */ 2085264790Sbapt if (high_bits == 0 2086264790Sbapt || high_bits == 0xffffffff) 2087264790Sbapt { 2088264790Sbapt sparc_emit_set_const64_quick1 (op0, temp, low_bits, 2089264790Sbapt (high_bits == 0xffffffff)); 2090264790Sbapt return; 2091264790Sbapt } 2092264790Sbapt 2093264790Sbapt /* Now, try 3-insn sequences. */ 2094264790Sbapt 2095264790Sbapt /* 1) sethi %hi(high_bits), %reg 2096264790Sbapt * or %reg, %lo(high_bits), %reg 2097264790Sbapt * sllx %reg, 32, %reg 2098264790Sbapt */ 2099264790Sbapt if (low_bits == 0) 2100264790Sbapt { 2101264790Sbapt sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); 2102264790Sbapt return; 2103264790Sbapt } 2104264790Sbapt 2105264790Sbapt /* We may be able to do something quick 2106264790Sbapt when the constant is negated, so try that. */ 2107264790Sbapt if (const64_is_2insns ((~high_bits) & 0xffffffff, 2108264790Sbapt (~low_bits) & 0xfffffc00)) 2109264790Sbapt { 2110264790Sbapt /* NOTE: The trailing bits get XOR'd so we need the 2111264790Sbapt non-negated bits, not the negated ones. */ 2112264790Sbapt unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; 2113264790Sbapt 2114264790Sbapt if ((((~high_bits) & 0xffffffff) == 0 2115264790Sbapt && ((~low_bits) & 0x80000000) == 0) 2116264790Sbapt || (((~high_bits) & 0xffffffff) == 0xffffffff 2117264790Sbapt && ((~low_bits) & 0x80000000) != 0)) 2118264790Sbapt { 2119264790Sbapt int fast_int = (~low_bits & 0xffffffff); 2120264790Sbapt 2121272955Srodrigc if ((SPARC_SETHI_P (fast_int) 2122264790Sbapt && (~high_bits & 0xffffffff) == 0) 2123264790Sbapt || SPARC_SIMM13_P (fast_int)) 2124264790Sbapt emit_insn (gen_safe_SET64 (temp, fast_int)); 2125264790Sbapt else 2126264790Sbapt sparc_emit_set_const64 (temp, GEN_INT64 (fast_int)); 2127264790Sbapt } 2128264790Sbapt else 2129264790Sbapt { 2130264790Sbapt rtx negated_const; 2131264790Sbapt#if HOST_BITS_PER_WIDE_INT == 64 2132264790Sbapt negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | 2133264790Sbapt (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); 2134264790Sbapt#else 2135264790Sbapt negated_const = gen_rtx_CONST_DOUBLE (DImode, 2136264790Sbapt (~low_bits) & 0xfffffc00, 2137264790Sbapt (~high_bits) & 0xffffffff); 2138264790Sbapt#endif 2139264790Sbapt sparc_emit_set_const64 (temp, negated_const); 2140264790Sbapt } 2141264790Sbapt 2142264790Sbapt /* If we are XOR'ing with -1, then we should emit a one's complement 2143264790Sbapt instead. This way the combiner will notice logical operations 2144264790Sbapt such as ANDN later on and substitute. */ 2145264790Sbapt if (trailing_bits == 0x3ff) 2146264790Sbapt { 2147264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, op0, 2148264790Sbapt gen_rtx_NOT (DImode, temp))); 2149264790Sbapt } 2150264790Sbapt else 2151264790Sbapt { 2152264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, 2153264790Sbapt op0, 2154264790Sbapt gen_safe_XOR64 (temp, 2155264790Sbapt (-0x400 | trailing_bits)))); 2156264790Sbapt } 2157264790Sbapt return; 2158264790Sbapt } 2159264790Sbapt 2160264790Sbapt /* 1) sethi %hi(xxx), %reg 2161264790Sbapt * or %reg, %lo(xxx), %reg 2162264790Sbapt * sllx %reg, yyy, %reg 2163264790Sbapt * 2164264790Sbapt * ??? This is just a generalized version of the low_bits==0 2165264790Sbapt * thing above, FIXME... 2166264790Sbapt */ 2167264790Sbapt if ((highest_bit_set - lowest_bit_set) < 32) 2168264790Sbapt { 2169264790Sbapt unsigned HOST_WIDE_INT focus_bits = 2170264790Sbapt create_simple_focus_bits (high_bits, low_bits, 2171264790Sbapt lowest_bit_set, 0); 2172272955Srodrigc 2173272955Srodrigc /* We can't get here in this state. */ 2174264790Sbapt if (highest_bit_set < 32 2175264790Sbapt || lowest_bit_set >= 32) 2176264790Sbapt abort (); 2177264790Sbapt 2178264790Sbapt /* So what we know is that the set bits straddle the 2179264790Sbapt middle of the 64-bit word. */ 2180264790Sbapt sparc_emit_set_const64_quick2 (op0, temp, 2181264790Sbapt focus_bits, 0, 2182264790Sbapt lowest_bit_set); 2183264790Sbapt return; 2184264790Sbapt } 2185264790Sbapt 2186264790Sbapt /* 1) sethi %hi(high_bits), %reg 2187264790Sbapt * or %reg, %lo(high_bits), %reg 2188264790Sbapt * sllx %reg, 32, %reg 2189264790Sbapt * or %reg, low_bits, %reg 2190264790Sbapt */ 2191264790Sbapt if (SPARC_SIMM13_P(low_bits) 2192264790Sbapt && ((int)low_bits > 0)) 2193264790Sbapt { 2194264790Sbapt sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); 2195264790Sbapt return; 2196264790Sbapt } 2197264790Sbapt 2198264790Sbapt /* The easiest way when all else fails, is full decomposition. */ 2199264790Sbapt#if 0 2200264790Sbapt printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", 2201264790Sbapt high_bits, low_bits, ~high_bits, ~low_bits); 2202264790Sbapt#endif 2203264790Sbapt sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); 2204264790Sbapt} 2205264790Sbapt 2206264790Sbapt/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2207264790Sbapt return the mode to be used for the comparison. For floating-point, 2208264790Sbapt CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 2209264790Sbapt is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2210264790Sbapt processing is needed. */ 2211264790Sbapt 2212264790Sbaptenum machine_mode 2213264790Sbaptselect_cc_mode (op, x, y) 2214264790Sbapt enum rtx_code op; 2215264790Sbapt rtx x; 2216264790Sbapt rtx y ATTRIBUTE_UNUSED; 2217264790Sbapt{ 2218264790Sbapt if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2219264790Sbapt { 2220264790Sbapt switch (op) 2221264790Sbapt { 2222264790Sbapt case EQ: 2223264790Sbapt case NE: 2224264790Sbapt case UNORDERED: 2225264790Sbapt case ORDERED: 2226264790Sbapt case UNLT: 2227264790Sbapt case UNLE: 2228264790Sbapt case UNGT: 2229264790Sbapt case UNGE: 2230264790Sbapt case UNEQ: 2231264790Sbapt case LTGT: 2232264790Sbapt return CCFPmode; 2233264790Sbapt 2234264790Sbapt case LT: 2235264790Sbapt case LE: 2236264790Sbapt case GT: 2237264790Sbapt case GE: 2238264790Sbapt return CCFPEmode; 2239264790Sbapt 2240264790Sbapt default: 2241264790Sbapt abort (); 2242264790Sbapt } 2243264790Sbapt } 2244264790Sbapt else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 2245264790Sbapt || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) 2246264790Sbapt { 2247264790Sbapt if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2248264790Sbapt return CCX_NOOVmode; 2249264790Sbapt else 2250264790Sbapt return CC_NOOVmode; 2251264790Sbapt } 2252264790Sbapt else 2253264790Sbapt { 2254264790Sbapt if (TARGET_ARCH64 && GET_MODE (x) == DImode) 2255264790Sbapt return CCXmode; 2256264790Sbapt else 2257264790Sbapt return CCmode; 2258264790Sbapt } 2259264790Sbapt} 2260264790Sbapt 2261264790Sbapt/* X and Y are two things to compare using CODE. Emit the compare insn and 2262264790Sbapt return the rtx for the cc reg in the proper mode. */ 2263264790Sbapt 2264264790Sbaptrtx 2265264790Sbaptgen_compare_reg (code, x, y) 2266264790Sbapt enum rtx_code code; 2267264790Sbapt rtx x, y; 2268264790Sbapt{ 2269264790Sbapt enum machine_mode mode = SELECT_CC_MODE (code, x, y); 2270264790Sbapt rtx cc_reg; 2271264790Sbapt 2272264790Sbapt /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the 2273264790Sbapt fcc regs (cse can't tell they're really call clobbered regs and will 2274264790Sbapt remove a duplicate comparison even if there is an intervening function 2275264790Sbapt call - it will then try to reload the cc reg via an int reg which is why 2276272955Srodrigc we need the movcc patterns). It is possible to provide the movcc 2277264790Sbapt patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two 2278272955Srodrigc registers (say %g1,%g5) and it takes about 6 insns. A better fix would be 2279264790Sbapt to tell cse that CCFPE mode registers (even pseudos) are call 2280264790Sbapt clobbered. */ 2281272955Srodrigc 2282264790Sbapt /* ??? This is an experiment. Rather than making changes to cse which may 2283264790Sbapt or may not be easy/clean, we do our own cse. This is possible because 2284264790Sbapt we will generate hard registers. Cse knows they're call clobbered (it 2285264790Sbapt doesn't know the same thing about pseudos). If we guess wrong, no big 2286264790Sbapt deal, but if we win, great! */ 2287264790Sbapt 2288264790Sbapt if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2289264790Sbapt#if 1 /* experiment */ 2290264790Sbapt { 2291264790Sbapt int reg; 2292264790Sbapt /* We cycle through the registers to ensure they're all exercised. */ 2293264790Sbapt static int next_fcc_reg = 0; 2294264790Sbapt /* Previous x,y for each fcc reg. */ 2295264790Sbapt static rtx prev_args[4][2]; 2296264790Sbapt 2297264790Sbapt /* Scan prev_args for x,y. */ 2298264790Sbapt for (reg = 0; reg < 4; reg++) 2299264790Sbapt if (prev_args[reg][0] == x && prev_args[reg][1] == y) 2300264790Sbapt break; 2301264790Sbapt if (reg == 4) 2302264790Sbapt { 2303264790Sbapt reg = next_fcc_reg; 2304264790Sbapt prev_args[reg][0] = x; 2305264790Sbapt prev_args[reg][1] = y; 2306264790Sbapt next_fcc_reg = (next_fcc_reg + 1) & 3; 2307264790Sbapt } 2308264790Sbapt cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); 2309264790Sbapt } 2310264790Sbapt#else 2311264790Sbapt cc_reg = gen_reg_rtx (mode); 2312264790Sbapt#endif /* ! experiment */ 2313264790Sbapt else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2314264790Sbapt cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); 2315264790Sbapt else 2316264790Sbapt cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); 2317264790Sbapt 2318264790Sbapt emit_insn (gen_rtx_SET (VOIDmode, cc_reg, 2319264790Sbapt gen_rtx_COMPARE (mode, x, y))); 2320264790Sbapt 2321264790Sbapt return cc_reg; 2322264790Sbapt} 2323264790Sbapt 2324264790Sbapt/* This function is used for v9 only. 2325264790Sbapt CODE is the code for an Scc's comparison. 2326264790Sbapt OPERANDS[0] is the target of the Scc insn. 2327264790Sbapt OPERANDS[1] is the value we compare against const0_rtx (which hasn't 2328264790Sbapt been generated yet). 2329264790Sbapt 2330264790Sbapt This function is needed to turn 2331264790Sbapt 2332264790Sbapt (set (reg:SI 110) 2333264790Sbapt (gt (reg:CCX 100 %icc) 2334264790Sbapt (const_int 0))) 2335264790Sbapt into 2336264790Sbapt (set (reg:SI 110) 2337264790Sbapt (gt:DI (reg:CCX 100 %icc) 2338264790Sbapt (const_int 0))) 2339264790Sbapt 2340264790Sbapt IE: The instruction recognizer needs to see the mode of the comparison to 2341264790Sbapt find the right instruction. We could use "gt:DI" right in the 2342264790Sbapt define_expand, but leaving it out allows us to handle DI, SI, etc. 2343264790Sbapt 2344264790Sbapt We refer to the global sparc compare operands sparc_compare_op0 and 2345264790Sbapt sparc_compare_op1. */ 2346264790Sbapt 2347264790Sbaptint 2348264790Sbaptgen_v9_scc (compare_code, operands) 2349264790Sbapt enum rtx_code compare_code; 2350264790Sbapt register rtx *operands; 2351264790Sbapt{ 2352264790Sbapt rtx temp, op0, op1; 2353264790Sbapt 2354264790Sbapt if (! TARGET_ARCH64 2355264790Sbapt && (GET_MODE (sparc_compare_op0) == DImode 2356264790Sbapt || GET_MODE (operands[0]) == DImode)) 2357 return 0; 2358 2359 op0 = sparc_compare_op0; 2360 op1 = sparc_compare_op1; 2361 2362 /* Try to use the movrCC insns. */ 2363 if (TARGET_ARCH64 2364 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT 2365 && op1 == const0_rtx 2366 && v9_regcmp_p (compare_code)) 2367 { 2368 /* Special case for op0 != 0. This can be done with one instruction if 2369 operands[0] == sparc_compare_op0. */ 2370 2371 if (compare_code == NE 2372 && GET_MODE (operands[0]) == DImode 2373 && rtx_equal_p (op0, operands[0])) 2374 { 2375 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2376 gen_rtx_IF_THEN_ELSE (DImode, 2377 gen_rtx_fmt_ee (compare_code, DImode, 2378 op0, const0_rtx), 2379 const1_rtx, 2380 operands[0]))); 2381 return 1; 2382 } 2383 2384 if (reg_overlap_mentioned_p (operands[0], op0)) 2385 { 2386 /* Handle the case where operands[0] == sparc_compare_op0. 2387 We "early clobber" the result. */ 2388 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); 2389 emit_move_insn (op0, sparc_compare_op0); 2390 } 2391 2392 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2393 if (GET_MODE (op0) != DImode) 2394 { 2395 temp = gen_reg_rtx (DImode); 2396 convert_move (temp, op0, 0); 2397 } 2398 else 2399 temp = op0; 2400 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2401 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2402 gen_rtx_fmt_ee (compare_code, DImode, 2403 temp, const0_rtx), 2404 const1_rtx, 2405 operands[0]))); 2406 return 1; 2407 } 2408 else 2409 { 2410 operands[1] = gen_compare_reg (compare_code, op0, op1); 2411 2412 switch (GET_MODE (operands[1])) 2413 { 2414 case CCmode : 2415 case CCXmode : 2416 case CCFPEmode : 2417 case CCFPmode : 2418 break; 2419 default : 2420 abort (); 2421 } 2422 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2423 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2424 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2425 gen_rtx_fmt_ee (compare_code, 2426 GET_MODE (operands[1]), 2427 operands[1], const0_rtx), 2428 const1_rtx, operands[0]))); 2429 return 1; 2430 } 2431} 2432 2433/* Emit a conditional jump insn for the v9 architecture using comparison code 2434 CODE and jump target LABEL. 2435 This function exists to take advantage of the v9 brxx insns. */ 2436 2437void 2438emit_v9_brxx_insn (code, op0, label) 2439 enum rtx_code code; 2440 rtx op0, label; 2441{ 2442 emit_jump_insn (gen_rtx_SET (VOIDmode, 2443 pc_rtx, 2444 gen_rtx_IF_THEN_ELSE (VOIDmode, 2445 gen_rtx_fmt_ee (code, GET_MODE (op0), 2446 op0, const0_rtx), 2447 gen_rtx_LABEL_REF (VOIDmode, label), 2448 pc_rtx))); 2449} 2450 2451/* Generate a DFmode part of a hard TFmode register. 2452 REG is the TFmode hard register, LOW is 1 for the 2453 low 64bit of the register and 0 otherwise. 2454 */ 2455rtx 2456gen_df_reg (reg, low) 2457 rtx reg; 2458 int low; 2459{ 2460 int regno = REGNO (reg); 2461 2462 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) 2463 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; 2464 return gen_rtx_REG (DFmode, regno); 2465} 2466 2467/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. 2468 Unlike normal calls, TFmode operands are passed by reference. It is 2469 assumed that no more than 3 operands are required. */ 2470 2471static void 2472emit_soft_tfmode_libcall (func_name, nargs, operands) 2473 const char *func_name; 2474 int nargs; 2475 rtx *operands; 2476{ 2477 rtx ret_slot = NULL, arg[3], func_sym; 2478 int i; 2479 2480 /* We only expect to be called for conversions, unary, and binary ops. */ 2481 if (nargs < 2 || nargs > 3) 2482 abort (); 2483 2484 for (i = 0; i < nargs; ++i) 2485 { 2486 rtx this_arg = operands[i]; 2487 rtx this_slot; 2488 2489 /* TFmode arguments and return values are passed by reference. */ 2490 if (GET_MODE (this_arg) == TFmode) 2491 { 2492 int force_stack_temp; 2493 2494 force_stack_temp = 0; 2495 if (TARGET_BUGGY_QP_LIB && i == 0) 2496 force_stack_temp = 1; 2497 2498 if (GET_CODE (this_arg) == MEM 2499 && ! force_stack_temp) 2500 this_arg = XEXP (this_arg, 0); 2501 else if (CONSTANT_P (this_arg) 2502 && ! force_stack_temp) 2503 { 2504 this_slot = force_const_mem (TFmode, this_arg); 2505 this_arg = XEXP (this_slot, 0); 2506 } 2507 else 2508 { 2509 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); 2510 2511 /* Operand 0 is the return value. We'll copy it out later. */ 2512 if (i > 0) 2513 emit_move_insn (this_slot, this_arg); 2514 else 2515 ret_slot = this_slot; 2516 2517 this_arg = XEXP (this_slot, 0); 2518 } 2519 } 2520 2521 arg[i] = this_arg; 2522 } 2523 2524 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); 2525 2526 if (GET_MODE (operands[0]) == TFmode) 2527 { 2528 if (nargs == 2) 2529 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, 2530 arg[0], GET_MODE (arg[0]), 2531 arg[1], GET_MODE (arg[1])); 2532 else 2533 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, 2534 arg[0], GET_MODE (arg[0]), 2535 arg[1], GET_MODE (arg[1]), 2536 arg[2], GET_MODE (arg[2])); 2537 2538 if (ret_slot) 2539 emit_move_insn (operands[0], ret_slot); 2540 } 2541 else 2542 { 2543 rtx ret; 2544 2545 if (nargs != 2) 2546 abort (); 2547 2548 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, 2549 GET_MODE (operands[0]), 1, 2550 arg[1], GET_MODE (arg[1])); 2551 2552 if (ret != operands[0]) 2553 emit_move_insn (operands[0], ret); 2554 } 2555} 2556 2557/* Expand soft-float TFmode calls to sparc abi routines. */ 2558 2559static void 2560emit_soft_tfmode_binop (code, operands) 2561 enum rtx_code code; 2562 rtx *operands; 2563{ 2564 const char *func; 2565 2566 switch (code) 2567 { 2568 case PLUS: 2569 func = "_Qp_add"; 2570 break; 2571 case MINUS: 2572 func = "_Qp_sub"; 2573 break; 2574 case MULT: 2575 func = "_Qp_mul"; 2576 break; 2577 case DIV: 2578 func = "_Qp_div"; 2579 break; 2580 default: 2581 abort (); 2582 } 2583 2584 emit_soft_tfmode_libcall (func, 3, operands); 2585} 2586 2587static void 2588emit_soft_tfmode_unop (code, operands) 2589 enum rtx_code code; 2590 rtx *operands; 2591{ 2592 const char *func; 2593 2594 switch (code) 2595 { 2596 case SQRT: 2597 func = "_Qp_sqrt"; 2598 break; 2599 default: 2600 abort (); 2601 } 2602 2603 emit_soft_tfmode_libcall (func, 2, operands); 2604} 2605 2606static void 2607emit_soft_tfmode_cvt (code, operands) 2608 enum rtx_code code; 2609 rtx *operands; 2610{ 2611 const char *func; 2612 2613 switch (code) 2614 { 2615 case FLOAT_EXTEND: 2616 switch (GET_MODE (operands[1])) 2617 { 2618 case SFmode: 2619 func = "_Qp_stoq"; 2620 break; 2621 case DFmode: 2622 func = "_Qp_dtoq"; 2623 break; 2624 default: 2625 abort (); 2626 } 2627 break; 2628 2629 case FLOAT_TRUNCATE: 2630 switch (GET_MODE (operands[0])) 2631 { 2632 case SFmode: 2633 func = "_Qp_qtos"; 2634 break; 2635 case DFmode: 2636 func = "_Qp_qtod"; 2637 break; 2638 default: 2639 abort (); 2640 } 2641 break; 2642 2643 case FLOAT: 2644 switch (GET_MODE (operands[1])) 2645 { 2646 case SImode: 2647 func = "_Qp_itoq"; 2648 break; 2649 case DImode: 2650 func = "_Qp_xtoq"; 2651 break; 2652 default: 2653 abort (); 2654 } 2655 break; 2656 2657 case UNSIGNED_FLOAT: 2658 switch (GET_MODE (operands[1])) 2659 { 2660 case SImode: 2661 func = "_Qp_uitoq"; 2662 break; 2663 case DImode: 2664 func = "_Qp_uxtoq"; 2665 break; 2666 default: 2667 abort (); 2668 } 2669 break; 2670 2671 case FIX: 2672 switch (GET_MODE (operands[0])) 2673 { 2674 case SImode: 2675 func = "_Qp_qtoi"; 2676 break; 2677 case DImode: 2678 func = "_Qp_qtox"; 2679 break; 2680 default: 2681 abort (); 2682 } 2683 break; 2684 2685 case UNSIGNED_FIX: 2686 switch (GET_MODE (operands[0])) 2687 { 2688 case SImode: 2689 func = "_Qp_qtoui"; 2690 break; 2691 case DImode: 2692 func = "_Qp_qtoux"; 2693 break; 2694 default: 2695 abort (); 2696 } 2697 break; 2698 2699 default: 2700 abort (); 2701 } 2702 2703 emit_soft_tfmode_libcall (func, 2, operands); 2704} 2705 2706/* Expand a hard-float tfmode operation. All arguments must be in 2707 registers. */ 2708 2709static void 2710emit_hard_tfmode_operation (code, operands) 2711 enum rtx_code code; 2712 rtx *operands; 2713{ 2714 rtx op, dest; 2715 2716 if (GET_RTX_CLASS (code) == '1') 2717 { 2718 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2719 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); 2720 } 2721 else 2722 { 2723 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2724 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 2725 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), 2726 operands[1], operands[2]); 2727 } 2728 2729 if (register_operand (operands[0], VOIDmode)) 2730 dest = operands[0]; 2731 else 2732 dest = gen_reg_rtx (GET_MODE (operands[0])); 2733 2734 emit_insn (gen_rtx_SET (VOIDmode, dest, op)); 2735 2736 if (dest != operands[0]) 2737 emit_move_insn (operands[0], dest); 2738} 2739 2740void 2741emit_tfmode_binop (code, operands) 2742 enum rtx_code code; 2743 rtx *operands; 2744{ 2745 if (TARGET_HARD_QUAD) 2746 emit_hard_tfmode_operation (code, operands); 2747 else 2748 emit_soft_tfmode_binop (code, operands); 2749} 2750 2751void 2752emit_tfmode_unop (code, operands) 2753 enum rtx_code code; 2754 rtx *operands; 2755{ 2756 if (TARGET_HARD_QUAD) 2757 emit_hard_tfmode_operation (code, operands); 2758 else 2759 emit_soft_tfmode_unop (code, operands); 2760} 2761 2762void 2763emit_tfmode_cvt (code, operands) 2764 enum rtx_code code; 2765 rtx *operands; 2766{ 2767 if (TARGET_HARD_QUAD) 2768 emit_hard_tfmode_operation (code, operands); 2769 else 2770 emit_soft_tfmode_cvt (code, operands); 2771} 2772 2773/* Return nonzero if a return peephole merging return with 2774 setting of output register is ok. */ 2775int 2776leaf_return_peephole_ok () 2777{ 2778 return (actual_fsize == 0); 2779} 2780 2781/* Return nonzero if a branch/jump/call instruction will be emitting 2782 nop into its delay slot. */ 2783 2784int 2785empty_delay_slot (insn) 2786 rtx insn; 2787{ 2788 rtx seq; 2789 2790 /* If no previous instruction (should not happen), return true. */ 2791 if (PREV_INSN (insn) == NULL) 2792 return 1; 2793 2794 seq = NEXT_INSN (PREV_INSN (insn)); 2795 if (GET_CODE (PATTERN (seq)) == SEQUENCE) 2796 return 0; 2797 2798 return 1; 2799} 2800 2801/* Return nonzero if TRIAL can go into the function epilogue's 2802 delay slot. SLOT is the slot we are trying to fill. */ 2803 2804int 2805eligible_for_epilogue_delay (trial, slot) 2806 rtx trial; 2807 int slot; 2808{ 2809 rtx pat, src; 2810 2811 if (slot >= 1) 2812 return 0; 2813 2814 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2815 return 0; 2816 2817 if (get_attr_length (trial) != 1) 2818 return 0; 2819 2820 /* If there are any call-saved registers, we should scan TRIAL if it 2821 does not reference them. For now just make it easy. */ 2822 if (num_gfregs) 2823 return 0; 2824 2825 /* If the function uses __builtin_eh_return, the eh_return machinery 2826 occupies the delay slot. */ 2827 if (current_function_calls_eh_return) 2828 return 0; 2829 2830 /* In the case of a true leaf function, anything can go into the delay slot. 2831 A delay slot only exists however if the frame size is zero, otherwise 2832 we will put an insn to adjust the stack after the return. */ 2833 if (current_function_uses_only_leaf_regs) 2834 { 2835 if (leaf_return_peephole_ok ()) 2836 return ((get_attr_in_uncond_branch_delay (trial) 2837 == IN_BRANCH_DELAY_TRUE)); 2838 return 0; 2839 } 2840 2841 pat = PATTERN (trial); 2842 2843 /* Otherwise, only operations which can be done in tandem with 2844 a `restore' or `return' insn can go into the delay slot. */ 2845 if (GET_CODE (SET_DEST (pat)) != REG 2846 || REGNO (SET_DEST (pat)) < 24) 2847 return 0; 2848 2849 /* If this instruction sets up floating point register and we have a return 2850 instruction, it can probably go in. But restore will not work 2851 with FP_REGS. */ 2852 if (REGNO (SET_DEST (pat)) >= 32) 2853 { 2854 if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2855 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2856 return 1; 2857 return 0; 2858 } 2859 2860 /* The set of insns matched here must agree precisely with the set of 2861 patterns paired with a RETURN in sparc.md. */ 2862 2863 src = SET_SRC (pat); 2864 2865 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */ 2866 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2867 && arith_operand (src, GET_MODE (src))) 2868 { 2869 if (TARGET_ARCH64) 2870 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2871 else 2872 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 2873 } 2874 2875 /* This matches "*return_di". */ 2876 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2877 && arith_double_operand (src, GET_MODE (src))) 2878 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2879 2880 /* This matches "*return_sf_no_fpu". */ 2881 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 2882 && register_operand (src, SFmode)) 2883 return 1; 2884 2885 /* If we have return instruction, anything that does not use 2886 local or output registers and can go into a delay slot wins. */ 2887 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1) 2888 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE)) 2889 return 1; 2890 2891 /* This matches "*return_addsi". */ 2892 else if (GET_CODE (src) == PLUS 2893 && arith_operand (XEXP (src, 0), SImode) 2894 && arith_operand (XEXP (src, 1), SImode) 2895 && (register_operand (XEXP (src, 0), SImode) 2896 || register_operand (XEXP (src, 1), SImode))) 2897 return 1; 2898 2899 /* This matches "*return_adddi". */ 2900 else if (GET_CODE (src) == PLUS 2901 && arith_double_operand (XEXP (src, 0), DImode) 2902 && arith_double_operand (XEXP (src, 1), DImode) 2903 && (register_operand (XEXP (src, 0), DImode) 2904 || register_operand (XEXP (src, 1), DImode))) 2905 return 1; 2906 2907 /* This can match "*return_losum_[sd]i". 2908 Catch only some cases, so that return_losum* don't have 2909 to be too big. */ 2910 else if (GET_CODE (src) == LO_SUM 2911 && ! TARGET_CM_MEDMID 2912 && ((register_operand (XEXP (src, 0), SImode) 2913 && immediate_operand (XEXP (src, 1), SImode)) 2914 || (TARGET_ARCH64 2915 && register_operand (XEXP (src, 0), DImode) 2916 && immediate_operand (XEXP (src, 1), DImode)))) 2917 return 1; 2918 2919 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */ 2920 else if (GET_CODE (src) == ASHIFT 2921 && (register_operand (XEXP (src, 0), SImode) 2922 || register_operand (XEXP (src, 0), DImode)) 2923 && XEXP (src, 1) == const1_rtx) 2924 return 1; 2925 2926 return 0; 2927} 2928 2929/* Return nonzero if TRIAL can go into the sibling call 2930 delay slot. */ 2931 2932int 2933eligible_for_sibcall_delay (trial) 2934 rtx trial; 2935{ 2936 rtx pat, src; 2937 2938 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2939 return 0; 2940 2941 if (get_attr_length (trial) != 1) 2942 return 0; 2943 2944 pat = PATTERN (trial); 2945 2946 if (current_function_uses_only_leaf_regs) 2947 { 2948 /* If the tail call is done using the call instruction, 2949 we have to restore %o7 in the delay slot. */ 2950 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic) 2951 return 0; 2952 2953 /* %g1 is used to build the function address */ 2954 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) 2955 return 0; 2956 2957 return 1; 2958 } 2959 2960 /* Otherwise, only operations which can be done in tandem with 2961 a `restore' insn can go into the delay slot. */ 2962 if (GET_CODE (SET_DEST (pat)) != REG 2963 || REGNO (SET_DEST (pat)) < 24 2964 || REGNO (SET_DEST (pat)) >= 32) 2965 return 0; 2966 2967 /* If it mentions %o7, it can't go in, because sibcall will clobber it 2968 in most cases. */ 2969 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) 2970 return 0; 2971 2972 src = SET_SRC (pat); 2973 2974 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2975 && arith_operand (src, GET_MODE (src))) 2976 { 2977 if (TARGET_ARCH64) 2978 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2979 else 2980 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 2981 } 2982 2983 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2984 && arith_double_operand (src, GET_MODE (src))) 2985 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2986 2987 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode) 2988 && register_operand (src, SFmode)) 2989 return 1; 2990 2991 else if (GET_CODE (src) == PLUS 2992 && arith_operand (XEXP (src, 0), SImode) 2993 && arith_operand (XEXP (src, 1), SImode) 2994 && (register_operand (XEXP (src, 0), SImode) 2995 || register_operand (XEXP (src, 1), SImode))) 2996 return 1; 2997 2998 else if (GET_CODE (src) == PLUS 2999 && arith_double_operand (XEXP (src, 0), DImode) 3000 && arith_double_operand (XEXP (src, 1), DImode) 3001 && (register_operand (XEXP (src, 0), DImode) 3002 || register_operand (XEXP (src, 1), DImode))) 3003 return 1; 3004 3005 else if (GET_CODE (src) == LO_SUM 3006 && ! TARGET_CM_MEDMID 3007 && ((register_operand (XEXP (src, 0), SImode) 3008 && immediate_operand (XEXP (src, 1), SImode)) 3009 || (TARGET_ARCH64 3010 && register_operand (XEXP (src, 0), DImode) 3011 && immediate_operand (XEXP (src, 1), DImode)))) 3012 return 1; 3013 3014 else if (GET_CODE (src) == ASHIFT 3015 && (register_operand (XEXP (src, 0), SImode) 3016 || register_operand (XEXP (src, 0), DImode)) 3017 && XEXP (src, 1) == const1_rtx) 3018 return 1; 3019 3020 return 0; 3021} 3022 3023static int 3024check_return_regs (x) 3025 rtx x; 3026{ 3027 switch (GET_CODE (x)) 3028 { 3029 case REG: 3030 return IN_OR_GLOBAL_P (x); 3031 3032 case CONST_INT: 3033 case CONST_DOUBLE: 3034 case CONST: 3035 case SYMBOL_REF: 3036 case LABEL_REF: 3037 return 1; 3038 3039 case SET: 3040 case IOR: 3041 case AND: 3042 case XOR: 3043 case PLUS: 3044 case MINUS: 3045 if (check_return_regs (XEXP (x, 1)) == 0) 3046 return 0; 3047 case NOT: 3048 case NEG: 3049 case MEM: 3050 return check_return_regs (XEXP (x, 0)); 3051 3052 default: 3053 return 0; 3054 } 3055 3056} 3057 3058/* Return 1 if TRIAL references only in and global registers. */ 3059int 3060eligible_for_return_delay (trial) 3061 rtx trial; 3062{ 3063 if (GET_CODE (PATTERN (trial)) != SET) 3064 return 0; 3065 3066 return check_return_regs (PATTERN (trial)); 3067} 3068 3069int 3070short_branch (uid1, uid2) 3071 int uid1, uid2; 3072{ 3073 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); 3074 3075 /* Leave a few words of "slop". */ 3076 if (delta >= -1023 && delta <= 1022) 3077 return 1; 3078 3079 return 0; 3080} 3081 3082/* Return non-zero if REG is not used after INSN. 3083 We assume REG is a reload reg, and therefore does 3084 not live past labels or calls or jumps. */ 3085int 3086reg_unused_after (reg, insn) 3087 rtx reg; 3088 rtx insn; 3089{ 3090 enum rtx_code code, prev_code = UNKNOWN; 3091 3092 while ((insn = NEXT_INSN (insn))) 3093 { 3094 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) 3095 return 1; 3096 3097 code = GET_CODE (insn); 3098 if (GET_CODE (insn) == CODE_LABEL) 3099 return 1; 3100 3101 if (GET_RTX_CLASS (code) == 'i') 3102 { 3103 rtx set = single_set (insn); 3104 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); 3105 if (set && in_src) 3106 return 0; 3107 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) 3108 return 1; 3109 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) 3110 return 0; 3111 } 3112 prev_code = code; 3113 } 3114 return 1; 3115} 3116 3117/* The table we use to reference PIC data. */ 3118static rtx global_offset_table; 3119 3120/* The function we use to get at it. */ 3121static rtx get_pc_symbol; 3122static char get_pc_symbol_name[256]; 3123 3124/* Ensure that we are not using patterns that are not OK with PIC. */ 3125 3126int 3127check_pic (i) 3128 int i; 3129{ 3130 switch (flag_pic) 3131 { 3132 case 1: 3133 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF 3134 || (GET_CODE (recog_data.operand[i]) == CONST 3135 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS 3136 && (XEXP (XEXP (recog_data.operand[i], 0), 0) 3137 == global_offset_table) 3138 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) 3139 == CONST)))) 3140 abort (); 3141 case 2: 3142 default: 3143 return 1; 3144 } 3145} 3146 3147/* Return true if X is an address which needs a temporary register when 3148 reloaded while generating PIC code. */ 3149 3150int 3151pic_address_needs_scratch (x) 3152 rtx x; 3153{ 3154 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ 3155 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS 3156 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 3157 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 3158 && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) 3159 return 1; 3160 3161 return 0; 3162} 3163 3164/* Legitimize PIC addresses. If the address is already position-independent, 3165 we return ORIG. Newly generated position-independent addresses go into a 3166 reg. This is REG if non zero, otherwise we allocate register(s) as 3167 necessary. */ 3168 3169rtx 3170legitimize_pic_address (orig, mode, reg) 3171 rtx orig; 3172 enum machine_mode mode ATTRIBUTE_UNUSED; 3173 rtx reg; 3174{ 3175 if (GET_CODE (orig) == SYMBOL_REF) 3176 { 3177 rtx pic_ref, address; 3178 rtx insn; 3179 3180 if (reg == 0) 3181 { 3182 if (reload_in_progress || reload_completed) 3183 abort (); 3184 else 3185 reg = gen_reg_rtx (Pmode); 3186 } 3187 3188 if (flag_pic == 2) 3189 { 3190 /* If not during reload, allocate another temp reg here for loading 3191 in the address, so that these instructions can be optimized 3192 properly. */ 3193 rtx temp_reg = ((reload_in_progress || reload_completed) 3194 ? reg : gen_reg_rtx (Pmode)); 3195 3196 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse 3197 won't get confused into thinking that these two instructions 3198 are loading in the true address of the symbol. If in the 3199 future a PIC rtx exists, that should be used instead. */ 3200 if (Pmode == SImode) 3201 { 3202 emit_insn (gen_movsi_high_pic (temp_reg, orig)); 3203 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); 3204 } 3205 else 3206 { 3207 emit_insn (gen_movdi_high_pic (temp_reg, orig)); 3208 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); 3209 } 3210 address = temp_reg; 3211 } 3212 else 3213 address = orig; 3214 3215 pic_ref = gen_rtx_MEM (Pmode, 3216 gen_rtx_PLUS (Pmode, 3217 pic_offset_table_rtx, address)); 3218 current_function_uses_pic_offset_table = 1; 3219 RTX_UNCHANGING_P (pic_ref) = 1; 3220 insn = emit_move_insn (reg, pic_ref); 3221 /* Put a REG_EQUAL note on this insn, so that it can be optimized 3222 by loop. */ 3223 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, 3224 REG_NOTES (insn)); 3225 return reg; 3226 } 3227 else if (GET_CODE (orig) == CONST) 3228 { 3229 rtx base, offset; 3230 3231 if (GET_CODE (XEXP (orig, 0)) == PLUS 3232 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 3233 return orig; 3234 3235 if (reg == 0) 3236 { 3237 if (reload_in_progress || reload_completed) 3238 abort (); 3239 else 3240 reg = gen_reg_rtx (Pmode); 3241 } 3242 3243 if (GET_CODE (XEXP (orig, 0)) == PLUS) 3244 { 3245 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 3246 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 3247 base == reg ? 0 : reg); 3248 } 3249 else 3250 abort (); 3251 3252 if (GET_CODE (offset) == CONST_INT) 3253 { 3254 if (SMALL_INT (offset)) 3255 return plus_constant (base, INTVAL (offset)); 3256 else if (! reload_in_progress && ! reload_completed) 3257 offset = force_reg (Pmode, offset); 3258 else 3259 /* If we reach here, then something is seriously wrong. */ 3260 abort (); 3261 } 3262 return gen_rtx_PLUS (Pmode, base, offset); 3263 } 3264 else if (GET_CODE (orig) == LABEL_REF) 3265 /* ??? Why do we do this? */ 3266 /* Now movsi_pic_label_ref uses it, but we ought to be checking that 3267 the register is live instead, in case it is eliminated. */ 3268 current_function_uses_pic_offset_table = 1; 3269 3270 return orig; 3271} 3272 3273/* Emit special PIC prologues. */ 3274 3275void 3276load_pic_register () 3277{ 3278 /* Labels to get the PC in the prologue of this function. */ 3279 int orig_flag_pic = flag_pic; 3280 3281 if (! flag_pic) 3282 abort (); 3283 3284 /* If we haven't emitted the special get_pc helper function, do so now. */ 3285 if (get_pc_symbol_name[0] == 0) 3286 { 3287 int align; 3288 3289 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0); 3290 text_section (); 3291 3292 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 3293 if (align > 0) 3294 ASM_OUTPUT_ALIGN (asm_out_file, align); 3295 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LGETPC", 0); 3296 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file); 3297 } 3298 3299 /* Initialize every time through, since we can't easily 3300 know this to be permanent. */ 3301 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3302 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name); 3303 flag_pic = 0; 3304 3305 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, 3306 get_pc_symbol)); 3307 3308 flag_pic = orig_flag_pic; 3309 3310 /* Need to emit this whether or not we obey regdecls, 3311 since setjmp/longjmp can cause life info to screw up. 3312 ??? In the case where we don't obey regdecls, this is not sufficient 3313 since we may not fall out the bottom. */ 3314 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); 3315} 3316 3317/* Return 1 if RTX is a MEM which is known to be aligned to at 3318 least a DESIRED byte boundary. */ 3319 3320int 3321mem_min_alignment (mem, desired) 3322 rtx mem; 3323 int desired; 3324{ 3325 rtx addr, base, offset; 3326 3327 /* If it's not a MEM we can't accept it. */ 3328 if (GET_CODE (mem) != MEM) 3329 return 0; 3330 3331 addr = XEXP (mem, 0); 3332 base = offset = NULL_RTX; 3333 if (GET_CODE (addr) == PLUS) 3334 { 3335 if (GET_CODE (XEXP (addr, 0)) == REG) 3336 { 3337 base = XEXP (addr, 0); 3338 3339 /* What we are saying here is that if the base 3340 REG is aligned properly, the compiler will make 3341 sure any REG based index upon it will be so 3342 as well. */ 3343 if (GET_CODE (XEXP (addr, 1)) == CONST_INT) 3344 offset = XEXP (addr, 1); 3345 else 3346 offset = const0_rtx; 3347 } 3348 } 3349 else if (GET_CODE (addr) == REG) 3350 { 3351 base = addr; 3352 offset = const0_rtx; 3353 } 3354 3355 if (base != NULL_RTX) 3356 { 3357 int regno = REGNO (base); 3358 3359 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) 3360 { 3361 /* Check if the compiler has recorded some information 3362 about the alignment of the base REG. If reload has 3363 completed, we already matched with proper alignments. 3364 If not running global_alloc, reload might give us 3365 unaligned pointer to local stack though. */ 3366 if (((cfun != 0 3367 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) 3368 || (optimize && reload_completed)) 3369 && (INTVAL (offset) & (desired - 1)) == 0) 3370 return 1; 3371 } 3372 else 3373 { 3374 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) 3375 return 1; 3376 } 3377 } 3378 else if (! TARGET_UNALIGNED_DOUBLES 3379 || CONSTANT_P (addr) 3380 || GET_CODE (addr) == LO_SUM) 3381 { 3382 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES 3383 is true, in which case we can only assume that an access is aligned if 3384 it is to a constant address, or the address involves a LO_SUM. */ 3385 return 1; 3386 } 3387 3388 /* An obviously unaligned address. */ 3389 return 0; 3390} 3391 3392 3393/* Vectors to keep interesting information about registers where it can easily 3394 be got. We use to use the actual mode value as the bit number, but there 3395 are more than 32 modes now. Instead we use two tables: one indexed by 3396 hard register number, and one indexed by mode. */ 3397 3398/* The purpose of sparc_mode_class is to shrink the range of modes so that 3399 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is 3400 mapped into one sparc_mode_class mode. */ 3401 3402enum sparc_mode_class { 3403 S_MODE, D_MODE, T_MODE, O_MODE, 3404 SF_MODE, DF_MODE, TF_MODE, OF_MODE, 3405 CC_MODE, CCFP_MODE 3406}; 3407 3408/* Modes for single-word and smaller quantities. */ 3409#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) 3410 3411/* Modes for double-word and smaller quantities. */ 3412#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) 3413 3414/* Modes for quad-word and smaller quantities. */ 3415#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) 3416 3417/* Modes for 8-word and smaller quantities. */ 3418#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) 3419 3420/* Modes for single-float quantities. We must allow any single word or 3421 smaller quantity. This is because the fix/float conversion instructions 3422 take integer inputs/outputs from the float registers. */ 3423#define SF_MODES (S_MODES) 3424 3425/* Modes for double-float and smaller quantities. */ 3426#define DF_MODES (S_MODES | D_MODES) 3427 3428/* Modes for double-float only quantities. */ 3429#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) 3430 3431/* Modes for quad-float only quantities. */ 3432#define TF_ONLY_MODES (1 << (int) TF_MODE) 3433 3434/* Modes for quad-float and smaller quantities. */ 3435#define TF_MODES (DF_MODES | TF_ONLY_MODES) 3436 3437/* Modes for quad-float and double-float quantities. */ 3438#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) 3439 3440/* Modes for quad-float pair only quantities. */ 3441#define OF_ONLY_MODES (1 << (int) OF_MODE) 3442 3443/* Modes for quad-float pairs and smaller quantities. */ 3444#define OF_MODES (TF_MODES | OF_ONLY_MODES) 3445 3446#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) 3447 3448/* Modes for condition codes. */ 3449#define CC_MODES (1 << (int) CC_MODE) 3450#define CCFP_MODES (1 << (int) CCFP_MODE) 3451 3452/* Value is 1 if register/mode pair is acceptable on sparc. 3453 The funny mixture of D and T modes is because integer operations 3454 do not specially operate on tetra quantities, so non-quad-aligned 3455 registers can hold quadword quantities (except %o4 and %i4 because 3456 they cross fixed registers). */ 3457 3458/* This points to either the 32 bit or the 64 bit version. */ 3459const int *hard_regno_mode_classes; 3460 3461static const int hard_32bit_mode_classes[] = { 3462 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3463 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3464 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3465 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3466 3467 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3468 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3469 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3470 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3471 3472 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3473 and none can hold SFmode/SImode values. */ 3474 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3475 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3476 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3477 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3478 3479 /* %fcc[0123] */ 3480 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3481 3482 /* %icc */ 3483 CC_MODES 3484}; 3485 3486static const int hard_64bit_mode_classes[] = { 3487 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3488 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3489 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3490 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3491 3492 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3493 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3494 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3495 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3496 3497 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3498 and none can hold SFmode/SImode values. */ 3499 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3500 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3501 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3502 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3503 3504 /* %fcc[0123] */ 3505 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3506 3507 /* %icc */ 3508 CC_MODES 3509}; 3510 3511int sparc_mode_class [NUM_MACHINE_MODES]; 3512 3513enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 3514 3515static void 3516sparc_init_modes () 3517{ 3518 int i; 3519 3520 for (i = 0; i < NUM_MACHINE_MODES; i++) 3521 { 3522 switch (GET_MODE_CLASS (i)) 3523 { 3524 case MODE_INT: 3525 case MODE_PARTIAL_INT: 3526 case MODE_COMPLEX_INT: 3527 if (GET_MODE_SIZE (i) <= 4) 3528 sparc_mode_class[i] = 1 << (int) S_MODE; 3529 else if (GET_MODE_SIZE (i) == 8) 3530 sparc_mode_class[i] = 1 << (int) D_MODE; 3531 else if (GET_MODE_SIZE (i) == 16) 3532 sparc_mode_class[i] = 1 << (int) T_MODE; 3533 else if (GET_MODE_SIZE (i) == 32) 3534 sparc_mode_class[i] = 1 << (int) O_MODE; 3535 else 3536 sparc_mode_class[i] = 0; 3537 break; 3538 case MODE_FLOAT: 3539 case MODE_COMPLEX_FLOAT: 3540 if (GET_MODE_SIZE (i) <= 4) 3541 sparc_mode_class[i] = 1 << (int) SF_MODE; 3542 else if (GET_MODE_SIZE (i) == 8) 3543 sparc_mode_class[i] = 1 << (int) DF_MODE; 3544 else if (GET_MODE_SIZE (i) == 16) 3545 sparc_mode_class[i] = 1 << (int) TF_MODE; 3546 else if (GET_MODE_SIZE (i) == 32) 3547 sparc_mode_class[i] = 1 << (int) OF_MODE; 3548 else 3549 sparc_mode_class[i] = 0; 3550 break; 3551 case MODE_CC: 3552 default: 3553 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so 3554 we must explicitly check for them here. */ 3555 if (i == (int) CCFPmode || i == (int) CCFPEmode) 3556 sparc_mode_class[i] = 1 << (int) CCFP_MODE; 3557 else if (i == (int) CCmode || i == (int) CC_NOOVmode 3558 || i == (int) CCXmode || i == (int) CCX_NOOVmode) 3559 sparc_mode_class[i] = 1 << (int) CC_MODE; 3560 else 3561 sparc_mode_class[i] = 0; 3562 break; 3563 } 3564 } 3565 3566 if (TARGET_ARCH64) 3567 hard_regno_mode_classes = hard_64bit_mode_classes; 3568 else 3569 hard_regno_mode_classes = hard_32bit_mode_classes; 3570 3571 /* Initialize the array used by REGNO_REG_CLASS. */ 3572 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3573 { 3574 if (i < 16 && TARGET_V8PLUS) 3575 sparc_regno_reg_class[i] = I64_REGS; 3576 else if (i < 32 || i == FRAME_POINTER_REGNUM) 3577 sparc_regno_reg_class[i] = GENERAL_REGS; 3578 else if (i < 64) 3579 sparc_regno_reg_class[i] = FP_REGS; 3580 else if (i < 96) 3581 sparc_regno_reg_class[i] = EXTRA_FP_REGS; 3582 else if (i < 100) 3583 sparc_regno_reg_class[i] = FPCC_REGS; 3584 else 3585 sparc_regno_reg_class[i] = NO_REGS; 3586 } 3587} 3588 3589/* Save non call used registers from LOW to HIGH at BASE+OFFSET. 3590 N_REGS is the number of 4-byte regs saved thus far. This applies even to 3591 v9 int regs as it simplifies the code. */ 3592 3593static int 3594save_regs (file, low, high, base, offset, n_regs, real_offset) 3595 FILE *file; 3596 int low, high; 3597 const char *base; 3598 int offset; 3599 int n_regs; 3600 int real_offset; 3601{ 3602 int i; 3603 3604 if (TARGET_ARCH64 && high <= 32) 3605 { 3606 for (i = low; i < high; i++) 3607 { 3608 if (regs_ever_live[i] && ! call_used_regs[i]) 3609 { 3610 fprintf (file, "\tstx\t%s, [%s+%d]\n", 3611 reg_names[i], base, offset + 4 * n_regs); 3612 if (dwarf2out_do_frame ()) 3613 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 3614 n_regs += 2; 3615 } 3616 } 3617 } 3618 else 3619 { 3620 for (i = low; i < high; i += 2) 3621 { 3622 if (regs_ever_live[i] && ! call_used_regs[i]) 3623 { 3624 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3625 { 3626 fprintf (file, "\tstd\t%s, [%s+%d]\n", 3627 reg_names[i], base, offset + 4 * n_regs); 3628 if (dwarf2out_do_frame ()) 3629 { 3630 char *l = dwarf2out_cfi_label (); 3631 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs); 3632 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4); 3633 } 3634 n_regs += 2; 3635 } 3636 else 3637 { 3638 fprintf (file, "\tst\t%s, [%s+%d]\n", 3639 reg_names[i], base, offset + 4 * n_regs); 3640 if (dwarf2out_do_frame ()) 3641 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs); 3642 n_regs += 2; 3643 } 3644 } 3645 else 3646 { 3647 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3648 { 3649 fprintf (file, "\tst\t%s, [%s+%d]\n", 3650 reg_names[i+1], base, offset + 4 * n_regs + 4); 3651 if (dwarf2out_do_frame ()) 3652 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4); 3653 n_regs += 2; 3654 } 3655 } 3656 } 3657 } 3658 return n_regs; 3659} 3660 3661/* Restore non call used registers from LOW to HIGH at BASE+OFFSET. 3662 3663 N_REGS is the number of 4-byte regs saved thus far. This applies even to 3664 v9 int regs as it simplifies the code. */ 3665 3666static int 3667restore_regs (file, low, high, base, offset, n_regs) 3668 FILE *file; 3669 int low, high; 3670 const char *base; 3671 int offset; 3672 int n_regs; 3673{ 3674 int i; 3675 3676 if (TARGET_ARCH64 && high <= 32) 3677 { 3678 for (i = low; i < high; i++) 3679 { 3680 if (regs_ever_live[i] && ! call_used_regs[i]) 3681 fprintf (file, "\tldx\t[%s+%d], %s\n", 3682 base, offset + 4 * n_regs, reg_names[i]), 3683 n_regs += 2; 3684 } 3685 } 3686 else 3687 { 3688 for (i = low; i < high; i += 2) 3689 { 3690 if (regs_ever_live[i] && ! call_used_regs[i]) 3691 if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3692 fprintf (file, "\tldd\t[%s+%d], %s\n", 3693 base, offset + 4 * n_regs, reg_names[i]), 3694 n_regs += 2; 3695 else 3696 fprintf (file, "\tld\t[%s+%d], %s\n", 3697 base, offset + 4 * n_regs, reg_names[i]), 3698 n_regs += 2; 3699 else if (regs_ever_live[i+1] && ! call_used_regs[i+1]) 3700 fprintf (file, "\tld\t[%s+%d], %s\n", 3701 base, offset + 4 * n_regs + 4, reg_names[i+1]), 3702 n_regs += 2; 3703 } 3704 } 3705 return n_regs; 3706} 3707 3708/* Compute the frame size required by the function. This function is called 3709 during the reload pass and also by output_function_prologue(). */ 3710 3711int 3712compute_frame_size (size, leaf_function) 3713 int size; 3714 int leaf_function; 3715{ 3716 int n_regs = 0, i; 3717 int outgoing_args_size = (current_function_outgoing_args_size 3718 + REG_PARM_STACK_SPACE (current_function_decl)); 3719 3720 /* N_REGS is the number of 4-byte regs saved thus far. This applies 3721 even to v9 int regs to be consistent with save_regs/restore_regs. */ 3722 3723 if (TARGET_ARCH64) 3724 { 3725 for (i = 0; i < 8; i++) 3726 if (regs_ever_live[i] && ! call_used_regs[i]) 3727 n_regs += 2; 3728 } 3729 else 3730 { 3731 for (i = 0; i < 8; i += 2) 3732 if ((regs_ever_live[i] && ! call_used_regs[i]) 3733 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 3734 n_regs += 2; 3735 } 3736 3737 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) 3738 if ((regs_ever_live[i] && ! call_used_regs[i]) 3739 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 3740 n_regs += 2; 3741 3742 /* Set up values for use in `function_epilogue'. */ 3743 num_gfregs = n_regs; 3744 3745 if (leaf_function && n_regs == 0 3746 && size == 0 && current_function_outgoing_args_size == 0) 3747 { 3748 actual_fsize = apparent_fsize = 0; 3749 } 3750 else 3751 { 3752 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ 3753 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; 3754 apparent_fsize += n_regs * 4; 3755 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); 3756 } 3757 3758 /* Make sure nothing can clobber our register windows. 3759 If a SAVE must be done, or there is a stack-local variable, 3760 the register window area must be allocated. 3761 ??? For v8 we apparently need an additional 8 bytes of reserved space. */ 3762 if (leaf_function == 0 || size > 0) 3763 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8); 3764 3765 return SPARC_STACK_ALIGN (actual_fsize); 3766} 3767 3768/* Build a (32 bit) big number in a register. */ 3769/* ??? We may be able to use the set macro here too. */ 3770 3771static void 3772build_big_number (file, num, reg) 3773 FILE *file; 3774 int num; 3775 const char *reg; 3776{ 3777 if (num >= 0 || ! TARGET_ARCH64) 3778 { 3779 fprintf (file, "\tsethi\t%%hi(%d), %s\n", num, reg); 3780 if ((num & 0x3ff) != 0) 3781 fprintf (file, "\tor\t%s, %%lo(%d), %s\n", reg, num, reg); 3782 } 3783 else /* num < 0 && TARGET_ARCH64 */ 3784 { 3785 /* Sethi does not sign extend, so we must use a little trickery 3786 to use it for negative numbers. Invert the constant before 3787 loading it in, then use xor immediate to invert the loaded bits 3788 (along with the upper 32 bits) to the desired constant. This 3789 works because the sethi and immediate fields overlap. */ 3790 int asize = num; 3791 int inv = ~asize; 3792 int low = -0x400 + (asize & 0x3FF); 3793 3794 fprintf (file, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n", 3795 inv, reg, reg, low, reg); 3796 } 3797} 3798 3799/* Output any necessary .register pseudo-ops. */ 3800void 3801sparc_output_scratch_registers (file) 3802 FILE *file ATTRIBUTE_UNUSED; 3803{ 3804#ifdef HAVE_AS_REGISTER_PSEUDO_OP 3805 int i; 3806 3807 if (TARGET_ARCH32) 3808 return; 3809 3810 /* Check if %g[2367] were used without 3811 .register being printed for them already. */ 3812 for (i = 2; i < 8; i++) 3813 { 3814 if (regs_ever_live [i] 3815 && ! sparc_hard_reg_printed [i]) 3816 { 3817 sparc_hard_reg_printed [i] = 1; 3818 fprintf (file, "\t.register\t%%g%d, #scratch\n", i); 3819 } 3820 if (i == 3) i = 5; 3821 } 3822#endif 3823} 3824 3825/* This function generates the assembly code for function entry. 3826 FILE is a stdio stream to output the code to. 3827 SIZE is an int: how many units of temporary storage to allocate. 3828 Refer to the array `regs_ever_live' to determine which registers 3829 to save; `regs_ever_live[I]' is nonzero if register number I 3830 is ever used in the function. This macro is responsible for 3831 knowing which registers should not be saved even if used. */ 3832 3833/* On SPARC, move-double insns between fpu and cpu need an 8-byte block 3834 of memory. If any fpu reg is used in the function, we allocate 3835 such a block here, at the bottom of the frame, just in case it's needed. 3836 3837 If this function is a leaf procedure, then we may choose not 3838 to do a "save" insn. The decision about whether or not 3839 to do this is made in regclass.c. */ 3840 3841static void 3842sparc_output_function_prologue (file, size) 3843 FILE *file; 3844 HOST_WIDE_INT size; 3845{ 3846 if (TARGET_FLAT) 3847 sparc_flat_function_prologue (file, size); 3848 else 3849 sparc_nonflat_function_prologue (file, size, 3850 current_function_uses_only_leaf_regs); 3851} 3852 3853/* Output code for the function prologue. */ 3854 3855static void 3856sparc_nonflat_function_prologue (file, size, leaf_function) 3857 FILE *file; 3858 HOST_WIDE_INT size; 3859 int leaf_function; 3860{ 3861 sparc_output_scratch_registers (file); 3862 3863 /* Need to use actual_fsize, since we are also allocating 3864 space for our callee (and our own register save area). */ 3865 actual_fsize = compute_frame_size (size, leaf_function); 3866 3867 if (leaf_function) 3868 { 3869 frame_base_name = "%sp"; 3870 frame_base_offset = actual_fsize + SPARC_STACK_BIAS; 3871 } 3872 else 3873 { 3874 frame_base_name = "%fp"; 3875 frame_base_offset = SPARC_STACK_BIAS; 3876 } 3877 3878 /* This is only for the human reader. */ 3879 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 3880 3881 if (actual_fsize == 0) 3882 /* do nothing. */ ; 3883 else if (! leaf_function) 3884 { 3885 if (actual_fsize <= 4096) 3886 fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize); 3887 else if (actual_fsize <= 8192) 3888 { 3889 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n"); 3890 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); 3891 } 3892 else 3893 { 3894 build_big_number (file, -actual_fsize, "%g1"); 3895 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n"); 3896 } 3897 } 3898 else /* leaf function */ 3899 { 3900 if (actual_fsize <= 4096) 3901 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize); 3902 else if (actual_fsize <= 8192) 3903 { 3904 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n"); 3905 fprintf (file, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize - 4096); 3906 } 3907 else 3908 { 3909 build_big_number (file, -actual_fsize, "%g1"); 3910 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n"); 3911 } 3912 } 3913 3914 if (dwarf2out_do_frame () && actual_fsize) 3915 { 3916 char *label = dwarf2out_cfi_label (); 3917 3918 /* The canonical frame address refers to the top of the frame. */ 3919 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM 3920 : HARD_FRAME_POINTER_REGNUM), 3921 frame_base_offset); 3922 3923 if (! leaf_function) 3924 { 3925 /* Note the register window save. This tells the unwinder that 3926 it needs to restore the window registers from the previous 3927 frame's window save area at 0(cfa). */ 3928 dwarf2out_window_save (label); 3929 3930 /* The return address (-8) is now in %i7. */ 3931 dwarf2out_return_reg (label, 31); 3932 } 3933 } 3934 3935 /* If doing anything with PIC, do it now. */ 3936 if (! flag_pic) 3937 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 3938 3939 /* Call saved registers are saved just above the outgoing argument area. */ 3940 if (num_gfregs) 3941 { 3942 int offset, real_offset, n_regs; 3943 const char *base; 3944 3945 real_offset = -apparent_fsize; 3946 offset = -apparent_fsize + frame_base_offset; 3947 if (offset < -4096 || offset + num_gfregs * 4 > 4096) 3948 { 3949 /* ??? This might be optimized a little as %g1 might already have a 3950 value close enough that a single add insn will do. */ 3951 /* ??? Although, all of this is probably only a temporary fix 3952 because if %g1 can hold a function result, then 3953 output_function_epilogue will lose (the result will get 3954 clobbered). */ 3955 build_big_number (file, offset, "%g1"); 3956 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 3957 base = "%g1"; 3958 offset = 0; 3959 } 3960 else 3961 { 3962 base = frame_base_name; 3963 } 3964 3965 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset); 3966 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs, 3967 real_offset); 3968 } 3969} 3970 3971/* Output code to restore any call saved registers. */ 3972 3973static void 3974output_restore_regs (file, leaf_function) 3975 FILE *file; 3976 int leaf_function ATTRIBUTE_UNUSED; 3977{ 3978 int offset, n_regs; 3979 const char *base; 3980 3981 offset = -apparent_fsize + frame_base_offset; 3982 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/) 3983 { 3984 build_big_number (file, offset, "%g1"); 3985 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name); 3986 base = "%g1"; 3987 offset = 0; 3988 } 3989 else 3990 { 3991 base = frame_base_name; 3992 } 3993 3994 n_regs = restore_regs (file, 0, 8, base, offset, 0); 3995 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs); 3996} 3997 3998/* This function generates the assembly code for function exit, 3999 on machines that need it. 4000 4001 The function epilogue should not depend on the current stack pointer! 4002 It should use the frame pointer only. This is mandatory because 4003 of alloca; we also take advantage of it to omit stack adjustments 4004 before returning. */ 4005 4006static void 4007sparc_output_function_epilogue (file, size) 4008 FILE *file; 4009 HOST_WIDE_INT size; 4010{ 4011 if (TARGET_FLAT) 4012 sparc_flat_function_epilogue (file, size); 4013 else 4014 sparc_nonflat_function_epilogue (file, size, 4015 current_function_uses_only_leaf_regs); 4016} 4017 4018/* Output code for the function epilogue. */ 4019 4020static void 4021sparc_nonflat_function_epilogue (file, size, leaf_function) 4022 FILE *file; 4023 HOST_WIDE_INT size ATTRIBUTE_UNUSED; 4024 int leaf_function; 4025{ 4026 const char *ret; 4027 4028 if (current_function_epilogue_delay_list == 0) 4029 { 4030 /* If code does not drop into the epilogue, we need 4031 do nothing except output pending case vectors. 4032 4033 We have to still output a dummy nop for the sake of 4034 sane backtraces. Otherwise, if the last two instructions 4035 of a function were call foo; dslot; this can make the return 4036 PC of foo (ie. address of call instruction plus 8) point to 4037 the first instruction in the next function. */ 4038 rtx insn; 4039 4040 fputs("\tnop\n", file); 4041 4042 insn = get_last_insn (); 4043 if (GET_CODE (insn) == NOTE) 4044 insn = prev_nonnote_insn (insn); 4045 if (insn && GET_CODE (insn) == BARRIER) 4046 goto output_vectors; 4047 } 4048 4049 if (num_gfregs) 4050 output_restore_regs (file, leaf_function); 4051 4052 /* Work out how to skip the caller's unimp instruction if required. */ 4053 if (leaf_function) 4054 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl"); 4055 else 4056 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret"); 4057 4058 if (! leaf_function) 4059 { 4060 if (current_function_calls_eh_return) 4061 { 4062 if (current_function_epilogue_delay_list) 4063 abort (); 4064 if (SKIP_CALLERS_UNIMP_P) 4065 abort (); 4066 4067 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file); 4068 } 4069 /* If we wound up with things in our delay slot, flush them here. */ 4070 else if (current_function_epilogue_delay_list) 4071 { 4072 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0)); 4073 4074 if (TARGET_V9 && ! epilogue_renumber (&delay, 1)) 4075 { 4076 epilogue_renumber (&delay, 0); 4077 fputs (SKIP_CALLERS_UNIMP_P 4078 ? "\treturn\t%i7+12\n" 4079 : "\treturn\t%i7+8\n", file); 4080 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4081 file, 1, 0, 0); 4082 } 4083 else 4084 { 4085 rtx insn, src; 4086 4087 if (GET_CODE (delay) != SET) 4088 abort(); 4089 4090 src = SET_SRC (delay); 4091 if (GET_CODE (src) == ASHIFT) 4092 { 4093 if (XEXP (src, 1) != const1_rtx) 4094 abort(); 4095 SET_SRC (delay) 4096 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0), 4097 XEXP (src, 0)); 4098 } 4099 4100 insn = gen_rtx_PARALLEL (VOIDmode, 4101 gen_rtvec (2, delay, 4102 gen_rtx_RETURN (VOIDmode))); 4103 insn = emit_jump_insn (insn); 4104 4105 sparc_emitting_epilogue = true; 4106 final_scan_insn (insn, file, 1, 0, 1); 4107 sparc_emitting_epilogue = false; 4108 } 4109 } 4110 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P) 4111 fputs ("\treturn\t%i7+8\n\tnop\n", file); 4112 else 4113 fprintf (file, "\t%s\n\trestore\n", ret); 4114 } 4115 /* All of the following cases are for leaf functions. */ 4116 else if (current_function_calls_eh_return) 4117 abort (); 4118 else if (current_function_epilogue_delay_list) 4119 { 4120 /* eligible_for_epilogue_delay_slot ensures that if this is a 4121 leaf function, then we will only have insn in the delay slot 4122 if the frame size is zero, thus no adjust for the stack is 4123 needed here. */ 4124 if (actual_fsize != 0) 4125 abort (); 4126 fprintf (file, "\t%s\n", ret); 4127 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0), 4128 file, 1, 0, 1); 4129 } 4130 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to 4131 avoid generating confusing assembly language output. */ 4132 else if (actual_fsize == 0) 4133 fprintf (file, "\t%s\n\tnop\n", ret); 4134 else if (actual_fsize <= 4096) 4135 fprintf (file, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret, actual_fsize); 4136 else if (actual_fsize <= 8192) 4137 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n", 4138 ret, actual_fsize - 4096); 4139 else if ((actual_fsize & 0x3ff) == 0) 4140 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", 4141 actual_fsize, ret); 4142 else 4143 fprintf (file, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n", 4144 actual_fsize, actual_fsize, ret); 4145 4146 output_vectors: 4147 sparc_output_deferred_case_vectors (); 4148} 4149 4150/* Output a sibling call. */ 4151 4152const char * 4153output_sibcall (insn, call_operand) 4154 rtx insn, call_operand; 4155{ 4156 int leaf_regs = current_function_uses_only_leaf_regs; 4157 rtx operands[3]; 4158 int delay_slot = dbr_sequence_length () > 0; 4159 4160 if (num_gfregs) 4161 { 4162 /* Call to restore global regs might clobber 4163 the delay slot. Instead of checking for this 4164 output the delay slot now. */ 4165 if (delay_slot) 4166 { 4167 rtx delay = NEXT_INSN (insn); 4168 4169 if (! delay) 4170 abort (); 4171 4172 final_scan_insn (delay, asm_out_file, 1, 0, 1); 4173 PATTERN (delay) = gen_blockage (); 4174 INSN_CODE (delay) = -1; 4175 delay_slot = 0; 4176 } 4177 output_restore_regs (asm_out_file, leaf_regs); 4178 } 4179 4180 operands[0] = call_operand; 4181 4182 if (leaf_regs) 4183 { 4184#ifdef HAVE_AS_RELAX_OPTION 4185 /* If as and ld are relaxing tail call insns into branch always, 4186 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can 4187 be optimized. With sethi/jmpl as nor ld has no easy way how to 4188 find out if somebody does not branch between the sethi and jmpl. */ 4189 int spare_slot = 0; 4190#else 4191 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic); 4192#endif 4193 int size = 0; 4194 4195 if ((actual_fsize || ! spare_slot) && delay_slot) 4196 { 4197 rtx delay = NEXT_INSN (insn); 4198 4199 if (! delay) 4200 abort (); 4201 4202 final_scan_insn (delay, asm_out_file, 1, 0, 1); 4203 PATTERN (delay) = gen_blockage (); 4204 INSN_CODE (delay) = -1; 4205 delay_slot = 0; 4206 } 4207 if (actual_fsize) 4208 { 4209 if (actual_fsize <= 4096) 4210 size = actual_fsize; 4211 else if (actual_fsize <= 8192) 4212 { 4213 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file); 4214 size = actual_fsize - 4096; 4215 } 4216 else if ((actual_fsize & 0x3ff) == 0) 4217 fprintf (asm_out_file, 4218 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n", 4219 actual_fsize); 4220 else 4221 { 4222 fprintf (asm_out_file, 4223 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n", 4224 actual_fsize, actual_fsize); 4225 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file); 4226 } 4227 } 4228 if (spare_slot) 4229 { 4230 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands); 4231 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands); 4232 if (size) 4233 fprintf (asm_out_file, "\t sub\t%%sp, -%d, %%sp\n", size); 4234 else if (! delay_slot) 4235 fputs ("\t nop\n", asm_out_file); 4236 } 4237 else 4238 { 4239 if (size) 4240 fprintf (asm_out_file, "\tsub\t%%sp, -%d, %%sp\n", size); 4241 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize 4242 it into branch if possible. */ 4243 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands); 4244 output_asm_insn ("call\t%a0, 0", operands); 4245 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands); 4246 } 4247 return ""; 4248 } 4249 4250 output_asm_insn ("call\t%a0, 0", operands); 4251 if (delay_slot) 4252 { 4253 rtx delay = NEXT_INSN (insn), pat; 4254 4255 if (! delay) 4256 abort (); 4257 4258 pat = PATTERN (delay); 4259 if (GET_CODE (pat) != SET) 4260 abort (); 4261 4262 operands[0] = SET_DEST (pat); 4263 pat = SET_SRC (pat); 4264 switch (GET_CODE (pat)) 4265 { 4266 case PLUS: 4267 operands[1] = XEXP (pat, 0); 4268 operands[2] = XEXP (pat, 1); 4269 output_asm_insn (" restore %r1, %2, %Y0", operands); 4270 break; 4271 case LO_SUM: 4272 operands[1] = XEXP (pat, 0); 4273 operands[2] = XEXP (pat, 1); 4274 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); 4275 break; 4276 case ASHIFT: 4277 operands[1] = XEXP (pat, 0); 4278 output_asm_insn (" restore %r1, %r1, %Y0", operands); 4279 break; 4280 default: 4281 operands[1] = pat; 4282 output_asm_insn (" restore %%g0, %1, %Y0", operands); 4283 break; 4284 } 4285 PATTERN (delay) = gen_blockage (); 4286 INSN_CODE (delay) = -1; 4287 } 4288 else 4289 fputs ("\t restore\n", asm_out_file); 4290 return ""; 4291} 4292 4293/* Functions for handling argument passing. 4294 4295 For v8 the first six args are normally in registers and the rest are 4296 pushed. Any arg that starts within the first 6 words is at least 4297 partially passed in a register unless its data type forbids. 4298 4299 For v9, the argument registers are laid out as an array of 16 elements 4300 and arguments are added sequentially. The first 6 int args and up to the 4301 first 16 fp args (depending on size) are passed in regs. 4302 4303 Slot Stack Integral Float Float in structure Double Long Double 4304 ---- ----- -------- ----- ------------------ ------ ----------- 4305 15 [SP+248] %f31 %f30,%f31 %d30 4306 14 [SP+240] %f29 %f28,%f29 %d28 %q28 4307 13 [SP+232] %f27 %f26,%f27 %d26 4308 12 [SP+224] %f25 %f24,%f25 %d24 %q24 4309 11 [SP+216] %f23 %f22,%f23 %d22 4310 10 [SP+208] %f21 %f20,%f21 %d20 %q20 4311 9 [SP+200] %f19 %f18,%f19 %d18 4312 8 [SP+192] %f17 %f16,%f17 %d16 %q16 4313 7 [SP+184] %f15 %f14,%f15 %d14 4314 6 [SP+176] %f13 %f12,%f13 %d12 %q12 4315 5 [SP+168] %o5 %f11 %f10,%f11 %d10 4316 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 4317 3 [SP+152] %o3 %f7 %f6,%f7 %d6 4318 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 4319 1 [SP+136] %o1 %f3 %f2,%f3 %d2 4320 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 4321 4322 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. 4323 4324 Integral arguments are always passed as 64 bit quantities appropriately 4325 extended. 4326 4327 Passing of floating point values is handled as follows. 4328 If a prototype is in scope: 4329 If the value is in a named argument (i.e. not a stdarg function or a 4330 value not part of the `...') then the value is passed in the appropriate 4331 fp reg. 4332 If the value is part of the `...' and is passed in one of the first 6 4333 slots then the value is passed in the appropriate int reg. 4334 If the value is part of the `...' and is not passed in one of the first 6 4335 slots then the value is passed in memory. 4336 If a prototype is not in scope: 4337 If the value is one of the first 6 arguments the value is passed in the 4338 appropriate integer reg and the appropriate fp reg. 4339 If the value is not one of the first 6 arguments the value is passed in 4340 the appropriate fp reg and in memory. 4341 */ 4342 4343/* Maximum number of int regs for args. */ 4344#define SPARC_INT_ARG_MAX 6 4345/* Maximum number of fp regs for args. */ 4346#define SPARC_FP_ARG_MAX 16 4347 4348#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 4349 4350/* Handle the INIT_CUMULATIVE_ARGS macro. 4351 Initialize a variable CUM of type CUMULATIVE_ARGS 4352 for a call to a function whose data type is FNTYPE. 4353 For a library call, FNTYPE is 0. */ 4354 4355void 4356init_cumulative_args (cum, fntype, libname, indirect) 4357 CUMULATIVE_ARGS *cum; 4358 tree fntype; 4359 rtx libname ATTRIBUTE_UNUSED; 4360 int indirect ATTRIBUTE_UNUSED; 4361{ 4362 cum->words = 0; 4363 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); 4364 cum->libcall_p = fntype == 0; 4365} 4366 4367/* Compute the slot number to pass an argument in. 4368 Returns the slot number or -1 if passing on the stack. 4369 4370 CUM is a variable of type CUMULATIVE_ARGS which gives info about 4371 the preceding args and about the function being called. 4372 MODE is the argument's machine mode. 4373 TYPE is the data type of the argument (as a tree). 4374 This is null for libcalls where that information may 4375 not be available. 4376 NAMED is nonzero if this argument is a named parameter 4377 (otherwise it is an extra parameter matching an ellipsis). 4378 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. 4379 *PREGNO records the register number to use if scalar type. 4380 *PPADDING records the amount of padding needed in words. */ 4381 4382static int 4383function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) 4384 const CUMULATIVE_ARGS *cum; 4385 enum machine_mode mode; 4386 tree type; 4387 int named; 4388 int incoming_p; 4389 int *pregno; 4390 int *ppadding; 4391{ 4392 int regbase = (incoming_p 4393 ? SPARC_INCOMING_INT_ARG_FIRST 4394 : SPARC_OUTGOING_INT_ARG_FIRST); 4395 int slotno = cum->words; 4396 int regno; 4397 4398 *ppadding = 0; 4399 4400 if (type != 0 && TREE_ADDRESSABLE (type)) 4401 return -1; 4402 if (TARGET_ARCH32 4403 && type != 0 && mode == BLKmode 4404 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) 4405 return -1; 4406 4407 switch (mode) 4408 { 4409 case VOIDmode : 4410 /* MODE is VOIDmode when generating the actual call. 4411 See emit_call_1. */ 4412 return -1; 4413 4414 case QImode : case CQImode : 4415 case HImode : case CHImode : 4416 case SImode : case CSImode : 4417 case DImode : case CDImode : 4418 case TImode : case CTImode : 4419 if (slotno >= SPARC_INT_ARG_MAX) 4420 return -1; 4421 regno = regbase + slotno; 4422 break; 4423 4424 case SFmode : case SCmode : 4425 case DFmode : case DCmode : 4426 case TFmode : case TCmode : 4427 if (TARGET_ARCH32) 4428 { 4429 if (slotno >= SPARC_INT_ARG_MAX) 4430 return -1; 4431 regno = regbase + slotno; 4432 } 4433 else 4434 { 4435 if ((mode == TFmode || mode == TCmode) 4436 && (slotno & 1) != 0) 4437 slotno++, *ppadding = 1; 4438 if (TARGET_FPU && named) 4439 { 4440 if (slotno >= SPARC_FP_ARG_MAX) 4441 return -1; 4442 regno = SPARC_FP_ARG_FIRST + slotno * 2; 4443 if (mode == SFmode) 4444 regno++; 4445 } 4446 else 4447 { 4448 if (slotno >= SPARC_INT_ARG_MAX) 4449 return -1; 4450 regno = regbase + slotno; 4451 } 4452 } 4453 break; 4454 4455 case BLKmode : 4456 /* For sparc64, objects requiring 16 byte alignment get it. */ 4457 if (TARGET_ARCH64) 4458 { 4459 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0) 4460 slotno++, *ppadding = 1; 4461 } 4462 4463 if (TARGET_ARCH32 4464 || (type && TREE_CODE (type) == UNION_TYPE)) 4465 { 4466 if (slotno >= SPARC_INT_ARG_MAX) 4467 return -1; 4468 regno = regbase + slotno; 4469 } 4470 else 4471 { 4472 tree field; 4473 int intregs_p = 0, fpregs_p = 0; 4474 /* The ABI obviously doesn't specify how packed 4475 structures are passed. These are defined to be passed 4476 in int regs if possible, otherwise memory. */ 4477 int packed_p = 0; 4478 4479 /* First see what kinds of registers we need. */ 4480 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4481 { 4482 if (TREE_CODE (field) == FIELD_DECL) 4483 { 4484 if (TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 4485 && TARGET_FPU) 4486 fpregs_p = 1; 4487 else 4488 intregs_p = 1; 4489 if (DECL_PACKED (field)) 4490 packed_p = 1; 4491 } 4492 } 4493 if (packed_p || !named) 4494 fpregs_p = 0, intregs_p = 1; 4495 4496 /* If all arg slots are filled, then must pass on stack. */ 4497 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) 4498 return -1; 4499 /* If there are only int args and all int arg slots are filled, 4500 then must pass on stack. */ 4501 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) 4502 return -1; 4503 /* Note that even if all int arg slots are filled, fp members may 4504 still be passed in regs if such regs are available. 4505 *PREGNO isn't set because there may be more than one, it's up 4506 to the caller to compute them. */ 4507 return slotno; 4508 } 4509 break; 4510 4511 default : 4512 abort (); 4513 } 4514 4515 *pregno = regno; 4516 return slotno; 4517} 4518 4519/* Handle recursive register counting for structure field layout. */ 4520 4521struct function_arg_record_value_parms 4522{ 4523 rtx ret; 4524 int slotno, named, regbase; 4525 unsigned int nregs; 4526 int intoffset; 4527}; 4528 4529static void function_arg_record_value_3 4530 PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *)); 4531static void function_arg_record_value_2 4532 PARAMS ((tree, HOST_WIDE_INT, 4533 struct function_arg_record_value_parms *)); 4534static void function_arg_record_value_1 4535 PARAMS ((tree, HOST_WIDE_INT, 4536 struct function_arg_record_value_parms *)); 4537static rtx function_arg_record_value 4538 PARAMS ((tree, enum machine_mode, int, int, int)); 4539 4540/* A subroutine of function_arg_record_value. Traverse the structure 4541 recusively and determine how many registers will be required. */ 4542 4543static void 4544function_arg_record_value_1 (type, startbitpos, parms) 4545 tree type; 4546 HOST_WIDE_INT startbitpos; 4547 struct function_arg_record_value_parms *parms; 4548{ 4549 tree field; 4550 4551 /* The ABI obviously doesn't specify how packed structures are 4552 passed. These are defined to be passed in int regs if possible, 4553 otherwise memory. */ 4554 int packed_p = 0; 4555 4556 /* We need to compute how many registers are needed so we can 4557 allocate the PARALLEL but before we can do that we need to know 4558 whether there are any packed fields. If there are, int regs are 4559 used regardless of whether there are fp values present. */ 4560 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4561 { 4562 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 4563 { 4564 packed_p = 1; 4565 break; 4566 } 4567 } 4568 4569 /* Compute how many registers we need. */ 4570 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4571 { 4572 if (TREE_CODE (field) == FIELD_DECL) 4573 { 4574 HOST_WIDE_INT bitpos = startbitpos; 4575 4576 if (DECL_SIZE (field) != 0 4577 && host_integerp (bit_position (field), 1)) 4578 bitpos += int_bit_position (field); 4579 4580 /* ??? FIXME: else assume zero offset. */ 4581 4582 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4583 function_arg_record_value_1 (TREE_TYPE (field), bitpos, parms); 4584 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 4585 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE 4586 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) 4587 == REAL_TYPE))) 4588 && TARGET_FPU 4589 && ! packed_p 4590 && parms->named) 4591 { 4592 if (parms->intoffset != -1) 4593 { 4594 int intslots, this_slotno; 4595 4596 intslots = (bitpos - parms->intoffset + BITS_PER_WORD - 1) 4597 / BITS_PER_WORD; 4598 this_slotno = parms->slotno + parms->intoffset 4599 / BITS_PER_WORD; 4600 4601 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); 4602 intslots = MAX (intslots, 0); 4603 parms->nregs += intslots; 4604 parms->intoffset = -1; 4605 } 4606 4607 /* There's no need to check this_slotno < SPARC_FP_ARG MAX. 4608 If it wasn't true we wouldn't be here. */ 4609 parms->nregs += 1; 4610 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 4611 parms->nregs += 1; 4612 } 4613 else 4614 { 4615 if (parms->intoffset == -1) 4616 parms->intoffset = bitpos; 4617 } 4618 } 4619 } 4620} 4621 4622/* A subroutine of function_arg_record_value. Assign the bits of the 4623 structure between parms->intoffset and bitpos to integer registers. */ 4624 4625static void 4626function_arg_record_value_3 (bitpos, parms) 4627 HOST_WIDE_INT bitpos; 4628 struct function_arg_record_value_parms *parms; 4629{ 4630 enum machine_mode mode; 4631 unsigned int regno; 4632 unsigned int startbit, endbit; 4633 int this_slotno, intslots, intoffset; 4634 rtx reg; 4635 4636 if (parms->intoffset == -1) 4637 return; 4638 4639 intoffset = parms->intoffset; 4640 parms->intoffset = -1; 4641 4642 startbit = intoffset & -BITS_PER_WORD; 4643 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4644 intslots = (endbit - startbit) / BITS_PER_WORD; 4645 this_slotno = parms->slotno + intoffset / BITS_PER_WORD; 4646 4647 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); 4648 if (intslots <= 0) 4649 return; 4650 4651 /* If this is the trailing part of a word, only load that much into 4652 the register. Otherwise load the whole register. Note that in 4653 the latter case we may pick up unwanted bits. It's not a problem 4654 at the moment but may wish to revisit. */ 4655 4656 if (intoffset % BITS_PER_WORD != 0) 4657 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, 4658 MODE_INT, 0); 4659 else 4660 mode = word_mode; 4661 4662 intoffset /= BITS_PER_UNIT; 4663 do 4664 { 4665 regno = parms->regbase + this_slotno; 4666 reg = gen_rtx_REG (mode, regno); 4667 XVECEXP (parms->ret, 0, parms->nregs) 4668 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); 4669 4670 this_slotno += 1; 4671 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; 4672 parms->nregs += 1; 4673 intslots -= 1; 4674 } 4675 while (intslots > 0); 4676} 4677 4678/* A subroutine of function_arg_record_value. Traverse the structure 4679 recursively and assign bits to floating point registers. Track which 4680 bits in between need integer registers; invoke function_arg_record_value_3 4681 to make that happen. */ 4682 4683static void 4684function_arg_record_value_2 (type, startbitpos, parms) 4685 tree type; 4686 HOST_WIDE_INT startbitpos; 4687 struct function_arg_record_value_parms *parms; 4688{ 4689 tree field; 4690 int packed_p = 0; 4691 4692 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4693 { 4694 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 4695 { 4696 packed_p = 1; 4697 break; 4698 } 4699 } 4700 4701 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4702 { 4703 if (TREE_CODE (field) == FIELD_DECL) 4704 { 4705 HOST_WIDE_INT bitpos = startbitpos; 4706 4707 if (DECL_SIZE (field) != 0 4708 && host_integerp (bit_position (field), 1)) 4709 bitpos += int_bit_position (field); 4710 4711 /* ??? FIXME: else assume zero offset. */ 4712 4713 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4714 function_arg_record_value_2 (TREE_TYPE (field), bitpos, parms); 4715 else if ((TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 4716 || (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE 4717 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field))) 4718 == REAL_TYPE))) 4719 && TARGET_FPU 4720 && ! packed_p 4721 && parms->named) 4722 { 4723 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; 4724 int regno; 4725 enum machine_mode mode = DECL_MODE (field); 4726 rtx reg; 4727 4728 function_arg_record_value_3 (bitpos, parms); 4729 regno = SPARC_FP_ARG_FIRST + this_slotno * 2 4730 + ((mode == SFmode || mode == SCmode) 4731 && (bitpos & 32) != 0); 4732 switch (mode) 4733 { 4734 case SCmode: mode = SFmode; break; 4735 case DCmode: mode = DFmode; break; 4736 case TCmode: mode = TFmode; break; 4737 default: break; 4738 } 4739 reg = gen_rtx_REG (mode, regno); 4740 XVECEXP (parms->ret, 0, parms->nregs) 4741 = gen_rtx_EXPR_LIST (VOIDmode, reg, 4742 GEN_INT (bitpos / BITS_PER_UNIT)); 4743 parms->nregs += 1; 4744 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 4745 { 4746 regno += GET_MODE_SIZE (mode) / 4; 4747 reg = gen_rtx_REG (mode, regno); 4748 XVECEXP (parms->ret, 0, parms->nregs) 4749 = gen_rtx_EXPR_LIST (VOIDmode, reg, 4750 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) 4751 / BITS_PER_UNIT)); 4752 parms->nregs += 1; 4753 } 4754 } 4755 else 4756 { 4757 if (parms->intoffset == -1) 4758 parms->intoffset = bitpos; 4759 } 4760 } 4761 } 4762} 4763 4764/* Used by function_arg and function_value to implement the complex 4765 Sparc64 structure calling conventions. */ 4766 4767static rtx 4768function_arg_record_value (type, mode, slotno, named, regbase) 4769 tree type; 4770 enum machine_mode mode; 4771 int slotno, named, regbase; 4772{ 4773 HOST_WIDE_INT typesize = int_size_in_bytes (type); 4774 struct function_arg_record_value_parms parms; 4775 unsigned int nregs; 4776 4777 parms.ret = NULL_RTX; 4778 parms.slotno = slotno; 4779 parms.named = named; 4780 parms.regbase = regbase; 4781 4782 /* Compute how many registers we need. */ 4783 parms.nregs = 0; 4784 parms.intoffset = 0; 4785 function_arg_record_value_1 (type, 0, &parms); 4786 4787 if (parms.intoffset != -1) 4788 { 4789 unsigned int startbit, endbit; 4790 int intslots, this_slotno; 4791 4792 startbit = parms.intoffset & -BITS_PER_WORD; 4793 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4794 intslots = (endbit - startbit) / BITS_PER_WORD; 4795 this_slotno = slotno + parms.intoffset / BITS_PER_WORD; 4796 4797 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); 4798 intslots = MAX (intslots, 0); 4799 4800 parms.nregs += intslots; 4801 } 4802 nregs = parms.nregs; 4803 4804 /* Allocate the vector and handle some annoying special cases. */ 4805 if (nregs == 0) 4806 { 4807 /* ??? Empty structure has no value? Duh? */ 4808 if (typesize <= 0) 4809 { 4810 /* Though there's nothing really to store, return a word register 4811 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL 4812 leads to breakage due to the fact that there are zero bytes to 4813 load. */ 4814 return gen_rtx_REG (mode, regbase); 4815 } 4816 else 4817 { 4818 /* ??? C++ has structures with no fields, and yet a size. Give up 4819 for now and pass everything back in integer registers. */ 4820 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 4821 } 4822 if (nregs + slotno > SPARC_INT_ARG_MAX) 4823 nregs = SPARC_INT_ARG_MAX - slotno; 4824 } 4825 if (nregs == 0) 4826 abort (); 4827 4828 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); 4829 4830 /* Fill in the entries. */ 4831 parms.nregs = 0; 4832 parms.intoffset = 0; 4833 function_arg_record_value_2 (type, 0, &parms); 4834 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); 4835 4836 if (parms.nregs != nregs) 4837 abort (); 4838 4839 return parms.ret; 4840} 4841 4842/* Handle the FUNCTION_ARG macro. 4843 Determine where to put an argument to a function. 4844 Value is zero to push the argument on the stack, 4845 or a hard register in which to store the argument. 4846 4847 CUM is a variable of type CUMULATIVE_ARGS which gives info about 4848 the preceding args and about the function being called. 4849 MODE is the argument's machine mode. 4850 TYPE is the data type of the argument (as a tree). 4851 This is null for libcalls where that information may 4852 not be available. 4853 NAMED is nonzero if this argument is a named parameter 4854 (otherwise it is an extra parameter matching an ellipsis). 4855 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ 4856 4857rtx 4858function_arg (cum, mode, type, named, incoming_p) 4859 const CUMULATIVE_ARGS *cum; 4860 enum machine_mode mode; 4861 tree type; 4862 int named; 4863 int incoming_p; 4864{ 4865 int regbase = (incoming_p 4866 ? SPARC_INCOMING_INT_ARG_FIRST 4867 : SPARC_OUTGOING_INT_ARG_FIRST); 4868 int slotno, regno, padding; 4869 rtx reg; 4870 4871 slotno = function_arg_slotno (cum, mode, type, named, incoming_p, 4872 ®no, &padding); 4873 4874 if (slotno == -1) 4875 return 0; 4876 4877 if (TARGET_ARCH32) 4878 { 4879 reg = gen_rtx_REG (mode, regno); 4880 return reg; 4881 } 4882 4883 /* v9 fp args in reg slots beyond the int reg slots get passed in regs 4884 but also have the slot allocated for them. 4885 If no prototype is in scope fp values in register slots get passed 4886 in two places, either fp regs and int regs or fp regs and memory. */ 4887 if ((GET_MODE_CLASS (mode) == MODE_FLOAT 4888 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 4889 && SPARC_FP_REG_P (regno)) 4890 { 4891 reg = gen_rtx_REG (mode, regno); 4892 if (cum->prototype_p || cum->libcall_p) 4893 { 4894 /* "* 2" because fp reg numbers are recorded in 4 byte 4895 quantities. */ 4896#if 0 4897 /* ??? This will cause the value to be passed in the fp reg and 4898 in the stack. When a prototype exists we want to pass the 4899 value in the reg but reserve space on the stack. That's an 4900 optimization, and is deferred [for a bit]. */ 4901 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) 4902 return gen_rtx_PARALLEL (mode, 4903 gen_rtvec (2, 4904 gen_rtx_EXPR_LIST (VOIDmode, 4905 NULL_RTX, const0_rtx), 4906 gen_rtx_EXPR_LIST (VOIDmode, 4907 reg, const0_rtx))); 4908 else 4909#else 4910 /* ??? It seems that passing back a register even when past 4911 the area declared by REG_PARM_STACK_SPACE will allocate 4912 space appropriately, and will not copy the data onto the 4913 stack, exactly as we desire. 4914 4915 This is due to locate_and_pad_parm being called in 4916 expand_call whenever reg_parm_stack_space > 0, which 4917 while benefical to our example here, would seem to be 4918 in error from what had been intended. Ho hum... -- r~ */ 4919#endif 4920 return reg; 4921 } 4922 else 4923 { 4924 rtx v0, v1; 4925 4926 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) 4927 { 4928 int intreg; 4929 4930 /* On incoming, we don't need to know that the value 4931 is passed in %f0 and %i0, and it confuses other parts 4932 causing needless spillage even on the simplest cases. */ 4933 if (incoming_p) 4934 return reg; 4935 4936 intreg = (SPARC_OUTGOING_INT_ARG_FIRST 4937 + (regno - SPARC_FP_ARG_FIRST) / 2); 4938 4939 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 4940 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), 4941 const0_rtx); 4942 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 4943 } 4944 else 4945 { 4946 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 4947 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 4948 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 4949 } 4950 } 4951 } 4952 else if (type && TREE_CODE (type) == RECORD_TYPE) 4953 { 4954 /* Structures up to 16 bytes in size are passed in arg slots on the 4955 stack and are promoted to registers where possible. */ 4956 4957 if (int_size_in_bytes (type) > 16) 4958 abort (); /* shouldn't get here */ 4959 4960 return function_arg_record_value (type, mode, slotno, named, regbase); 4961 } 4962 else if (type && TREE_CODE (type) == UNION_TYPE) 4963 { 4964 enum machine_mode mode; 4965 int bytes = int_size_in_bytes (type); 4966 4967 if (bytes > 16) 4968 abort (); 4969 4970 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); 4971 reg = gen_rtx_REG (mode, regno); 4972 } 4973 else 4974 { 4975 /* Scalar or complex int. */ 4976 reg = gen_rtx_REG (mode, regno); 4977 } 4978 4979 return reg; 4980} 4981 4982/* Handle the FUNCTION_ARG_PARTIAL_NREGS macro. 4983 For an arg passed partly in registers and partly in memory, 4984 this is the number of registers used. 4985 For args passed entirely in registers or entirely in memory, zero. 4986 4987 Any arg that starts in the first 6 regs but won't entirely fit in them 4988 needs partial registers on v8. On v9, structures with integer 4989 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp 4990 values that begin in the last fp reg [where "last fp reg" varies with the 4991 mode] will be split between that reg and memory. */ 4992 4993int 4994function_arg_partial_nregs (cum, mode, type, named) 4995 const CUMULATIVE_ARGS *cum; 4996 enum machine_mode mode; 4997 tree type; 4998 int named; 4999{ 5000 int slotno, regno, padding; 5001 5002 /* We pass 0 for incoming_p here, it doesn't matter. */ 5003 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5004 5005 if (slotno == -1) 5006 return 0; 5007 5008 if (TARGET_ARCH32) 5009 { 5010 if ((slotno + (mode == BLKmode 5011 ? ROUND_ADVANCE (int_size_in_bytes (type)) 5012 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) 5013 > NPARM_REGS (SImode)) 5014 return NPARM_REGS (SImode) - slotno; 5015 return 0; 5016 } 5017 else 5018 { 5019 if (type && AGGREGATE_TYPE_P (type)) 5020 { 5021 int size = int_size_in_bytes (type); 5022 int align = TYPE_ALIGN (type); 5023 5024 if (align == 16) 5025 slotno += slotno & 1; 5026 if (size > 8 && size <= 16 5027 && slotno == SPARC_INT_ARG_MAX - 1) 5028 return 1; 5029 } 5030 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT 5031 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 5032 && ! TARGET_FPU)) 5033 { 5034 if (GET_MODE_ALIGNMENT (mode) == 128) 5035 { 5036 slotno += slotno & 1; 5037 if (slotno == SPARC_INT_ARG_MAX - 2) 5038 return 1; 5039 } 5040 else 5041 { 5042 if (slotno == SPARC_INT_ARG_MAX - 1) 5043 return 1; 5044 } 5045 } 5046 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5047 { 5048 if (GET_MODE_ALIGNMENT (mode) == 128) 5049 slotno += slotno & 1; 5050 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) 5051 > SPARC_FP_ARG_MAX) 5052 return 1; 5053 } 5054 return 0; 5055 } 5056} 5057 5058/* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro. 5059 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and 5060 quad-precision floats by invisible reference. 5061 v9: Aggregates greater than 16 bytes are passed by reference. 5062 For Pascal, also pass arrays by reference. */ 5063 5064int 5065function_arg_pass_by_reference (cum, mode, type, named) 5066 const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; 5067 enum machine_mode mode; 5068 tree type; 5069 int named ATTRIBUTE_UNUSED; 5070{ 5071 if (TARGET_ARCH32) 5072 { 5073 return ((type && AGGREGATE_TYPE_P (type)) 5074 || mode == TFmode || mode == TCmode); 5075 } 5076 else 5077 { 5078 return ((type && TREE_CODE (type) == ARRAY_TYPE) 5079 /* Consider complex values as aggregates, so care for TCmode. */ 5080 || GET_MODE_SIZE (mode) > 16 5081 || (type 5082 && AGGREGATE_TYPE_P (type) 5083 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)); 5084 } 5085} 5086 5087/* Handle the FUNCTION_ARG_ADVANCE macro. 5088 Update the data in CUM to advance over an argument 5089 of mode MODE and data type TYPE. 5090 TYPE is null for libcalls where that information may not be available. */ 5091 5092void 5093function_arg_advance (cum, mode, type, named) 5094 CUMULATIVE_ARGS *cum; 5095 enum machine_mode mode; 5096 tree type; 5097 int named; 5098{ 5099 int slotno, regno, padding; 5100 5101 /* We pass 0 for incoming_p here, it doesn't matter. */ 5102 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5103 5104 /* If register required leading padding, add it. */ 5105 if (slotno != -1) 5106 cum->words += padding; 5107 5108 if (TARGET_ARCH32) 5109 { 5110 cum->words += (mode != BLKmode 5111 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5112 : ROUND_ADVANCE (int_size_in_bytes (type))); 5113 } 5114 else 5115 { 5116 if (type && AGGREGATE_TYPE_P (type)) 5117 { 5118 int size = int_size_in_bytes (type); 5119 5120 if (size <= 8) 5121 ++cum->words; 5122 else if (size <= 16) 5123 cum->words += 2; 5124 else /* passed by reference */ 5125 ++cum->words; 5126 } 5127 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT) 5128 { 5129 cum->words += 2; 5130 } 5131 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5132 { 5133 cum->words += GET_MODE_SIZE (mode) / UNITS_PER_WORD; 5134 } 5135 else 5136 { 5137 cum->words += (mode != BLKmode 5138 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5139 : ROUND_ADVANCE (int_size_in_bytes (type))); 5140 } 5141 } 5142} 5143 5144/* Handle the FUNCTION_ARG_PADDING macro. 5145 For the 64 bit ABI structs are always stored left shifted in their 5146 argument slot. */ 5147 5148enum direction 5149function_arg_padding (mode, type) 5150 enum machine_mode mode; 5151 tree type; 5152{ 5153 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) 5154 return upward; 5155 5156 /* This is the default definition. */ 5157 return (! BYTES_BIG_ENDIAN 5158 ? upward 5159 : ((mode == BLKmode 5160 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST 5161 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT)) 5162 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) 5163 ? downward : upward)); 5164} 5165 5166/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. 5167 For v9, function return values are subject to the same rules as arguments, 5168 except that up to 32-bytes may be returned in registers. */ 5169 5170rtx 5171function_value (type, mode, incoming_p) 5172 tree type; 5173 enum machine_mode mode; 5174 int incoming_p; 5175{ 5176 int regno; 5177 int regbase = (incoming_p 5178 ? SPARC_OUTGOING_INT_ARG_FIRST 5179 : SPARC_INCOMING_INT_ARG_FIRST); 5180 5181 if (TARGET_ARCH64 && type) 5182 { 5183 if (TREE_CODE (type) == RECORD_TYPE) 5184 { 5185 /* Structures up to 32 bytes in size are passed in registers, 5186 promoted to fp registers where possible. */ 5187 5188 if (int_size_in_bytes (type) > 32) 5189 abort (); /* shouldn't get here */ 5190 5191 return function_arg_record_value (type, mode, 0, 1, regbase); 5192 } 5193 else if (AGGREGATE_TYPE_P (type)) 5194 { 5195 /* All other aggregate types are passed in an integer register 5196 in a mode corresponding to the size of the type. */ 5197 HOST_WIDE_INT bytes = int_size_in_bytes (type); 5198 5199 if (bytes > 32) 5200 abort (); 5201 5202 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0); 5203 } 5204 } 5205 5206 if (TARGET_ARCH64 5207 && GET_MODE_CLASS (mode) == MODE_INT 5208 && GET_MODE_SIZE (mode) < UNITS_PER_WORD 5209 && type && ! AGGREGATE_TYPE_P (type)) 5210 mode = DImode; 5211 5212 if (incoming_p) 5213 regno = BASE_RETURN_VALUE_REG (mode); 5214 else 5215 regno = BASE_OUTGOING_VALUE_REG (mode); 5216 5217 return gen_rtx_REG (mode, regno); 5218} 5219 5220/* Do what is necessary for `va_start'. We look at the current function 5221 to determine if stdarg or varargs is used and return the address of 5222 the first unnamed parameter. */ 5223 5224rtx 5225sparc_builtin_saveregs () 5226{ 5227 int first_reg = current_function_args_info.words; 5228 rtx address; 5229 int regno; 5230 5231 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++) 5232 emit_move_insn (gen_rtx_MEM (word_mode, 5233 gen_rtx_PLUS (Pmode, 5234 frame_pointer_rtx, 5235 GEN_INT (FIRST_PARM_OFFSET (0) 5236 + (UNITS_PER_WORD 5237 * regno)))), 5238 gen_rtx_REG (word_mode, 5239 BASE_INCOMING_ARG_REG (word_mode) + regno)); 5240 5241 address = gen_rtx_PLUS (Pmode, 5242 frame_pointer_rtx, 5243 GEN_INT (FIRST_PARM_OFFSET (0) 5244 + UNITS_PER_WORD * first_reg)); 5245 5246 return address; 5247} 5248 5249/* Implement `va_start' for varargs and stdarg. */ 5250 5251void 5252sparc_va_start (stdarg_p, valist, nextarg) 5253 int stdarg_p ATTRIBUTE_UNUSED; 5254 tree valist; 5255 rtx nextarg; 5256{ 5257 nextarg = expand_builtin_saveregs (); 5258 std_expand_builtin_va_start (1, valist, nextarg); 5259} 5260 5261/* Implement `va_arg'. */ 5262 5263rtx 5264sparc_va_arg (valist, type) 5265 tree valist, type; 5266{ 5267 HOST_WIDE_INT size, rsize, align; 5268 tree addr, incr; 5269 rtx addr_rtx; 5270 int indirect = 0; 5271 5272 /* Round up sizeof(type) to a word. */ 5273 size = int_size_in_bytes (type); 5274 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; 5275 align = 0; 5276 5277 if (TARGET_ARCH64) 5278 { 5279 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) 5280 align = 2 * UNITS_PER_WORD; 5281 5282 if (AGGREGATE_TYPE_P (type)) 5283 { 5284 if ((unsigned HOST_WIDE_INT) size > 16) 5285 { 5286 indirect = 1; 5287 size = rsize = UNITS_PER_WORD; 5288 } 5289 /* SPARC v9 ABI states that structures up to 8 bytes in size are 5290 given one 8 byte slot. */ 5291 else if (size == 0) 5292 size = rsize = UNITS_PER_WORD; 5293 else 5294 size = rsize; 5295 } 5296 } 5297 else 5298 { 5299 if (AGGREGATE_TYPE_P (type) 5300 || TYPE_MODE (type) == TFmode 5301 || TYPE_MODE (type) == TCmode) 5302 { 5303 indirect = 1; 5304 size = rsize = UNITS_PER_WORD; 5305 } 5306 } 5307 5308 incr = valist; 5309 if (align) 5310 { 5311 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5312 build_int_2 (align - 1, 0))); 5313 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr, 5314 build_int_2 (-align, -1))); 5315 } 5316 5317 addr = incr = save_expr (incr); 5318 if (BYTES_BIG_ENDIAN && size < rsize) 5319 { 5320 addr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5321 build_int_2 (rsize - size, 0))); 5322 } 5323 incr = fold (build (PLUS_EXPR, ptr_type_node, incr, 5324 build_int_2 (rsize, 0))); 5325 5326 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr); 5327 TREE_SIDE_EFFECTS (incr) = 1; 5328 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL); 5329 5330 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL); 5331 5332 /* If the address isn't aligned properly for the type, 5333 we may need to copy to a temporary. 5334 FIXME: This is inefficient. Usually we can do this 5335 in registers. */ 5336 if (align == 0 5337 && TYPE_ALIGN (type) > BITS_PER_WORD 5338 && !indirect) 5339 { 5340 /* FIXME: We really need to specify that the temporary is live 5341 for the whole function because expand_builtin_va_arg wants 5342 the alias set to be get_varargs_alias_set (), but in this 5343 case the alias set is that for TYPE and if the memory gets 5344 reused it will be reused with alias set TYPE. */ 5345 rtx tmp = assign_temp (type, 0, 1, 0); 5346 rtx dest_addr; 5347 5348 addr_rtx = force_reg (Pmode, addr_rtx); 5349 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx); 5350 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5351 set_mem_align (addr_rtx, BITS_PER_WORD); 5352 tmp = shallow_copy_rtx (tmp); 5353 PUT_MODE (tmp, BLKmode); 5354 set_mem_alias_set (tmp, 0); 5355 5356 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize)); 5357 if (dest_addr != NULL_RTX) 5358 addr_rtx = dest_addr; 5359 else 5360 addr_rtx = XCEXP (tmp, 0, MEM); 5361 } 5362 5363 if (indirect) 5364 { 5365 addr_rtx = force_reg (Pmode, addr_rtx); 5366 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx); 5367 set_mem_alias_set (addr_rtx, get_varargs_alias_set ()); 5368 } 5369 5370 return addr_rtx; 5371} 5372 5373/* Return the string to output a conditional branch to LABEL, which is 5374 the operand number of the label. OP is the conditional expression. 5375 XEXP (OP, 0) is assumed to be a condition code register (integer or 5376 floating point) and its mode specifies what kind of comparison we made. 5377 5378 REVERSED is non-zero if we should reverse the sense of the comparison. 5379 5380 ANNUL is non-zero if we should generate an annulling branch. 5381 5382 NOOP is non-zero if we have to follow this branch by a noop. 5383 5384 INSN, if set, is the insn. */ 5385 5386char * 5387output_cbranch (op, dest, label, reversed, annul, noop, insn) 5388 rtx op, dest; 5389 int label; 5390 int reversed, annul, noop; 5391 rtx insn; 5392{ 5393 static char string[50]; 5394 enum rtx_code code = GET_CODE (op); 5395 rtx cc_reg = XEXP (op, 0); 5396 enum machine_mode mode = GET_MODE (cc_reg); 5397 const char *labelno, *branch; 5398 int spaces = 8, far; 5399 char *p; 5400 5401 /* v9 branches are limited to +-1MB. If it is too far away, 5402 change 5403 5404 bne,pt %xcc, .LC30 5405 5406 to 5407 5408 be,pn %xcc, .+12 5409 nop 5410 ba .LC30 5411 5412 and 5413 5414 fbne,a,pn %fcc2, .LC29 5415 5416 to 5417 5418 fbe,pt %fcc2, .+16 5419 nop 5420 ba .LC29 */ 5421 5422 far = get_attr_length (insn) >= 3; 5423 if (reversed ^ far) 5424 { 5425 /* Reversal of FP compares takes care -- an ordered compare 5426 becomes an unordered compare and vice versa. */ 5427 if (mode == CCFPmode || mode == CCFPEmode) 5428 code = reverse_condition_maybe_unordered (code); 5429 else 5430 code = reverse_condition (code); 5431 } 5432 5433 /* Start by writing the branch condition. */ 5434 if (mode == CCFPmode || mode == CCFPEmode) 5435 { 5436 switch (code) 5437 { 5438 case NE: 5439 branch = "fbne"; 5440 break; 5441 case EQ: 5442 branch = "fbe"; 5443 break; 5444 case GE: 5445 branch = "fbge"; 5446 break; 5447 case GT: 5448 branch = "fbg"; 5449 break; 5450 case LE: 5451 branch = "fble"; 5452 break; 5453 case LT: 5454 branch = "fbl"; 5455 break; 5456 case UNORDERED: 5457 branch = "fbu"; 5458 break; 5459 case ORDERED: 5460 branch = "fbo"; 5461 break; 5462 case UNGT: 5463 branch = "fbug"; 5464 break; 5465 case UNLT: 5466 branch = "fbul"; 5467 break; 5468 case UNEQ: 5469 branch = "fbue"; 5470 break; 5471 case UNGE: 5472 branch = "fbuge"; 5473 break; 5474 case UNLE: 5475 branch = "fbule"; 5476 break; 5477 case LTGT: 5478 branch = "fblg"; 5479 break; 5480 5481 default: 5482 abort (); 5483 } 5484 5485 /* ??? !v9: FP branches cannot be preceded by another floating point 5486 insn. Because there is currently no concept of pre-delay slots, 5487 we can fix this only by always emitting a nop before a floating 5488 point branch. */ 5489 5490 string[0] = '\0'; 5491 if (! TARGET_V9) 5492 strcpy (string, "nop\n\t"); 5493 strcat (string, branch); 5494 } 5495 else 5496 { 5497 switch (code) 5498 { 5499 case NE: 5500 branch = "bne"; 5501 break; 5502 case EQ: 5503 branch = "be"; 5504 break; 5505 case GE: 5506 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 5507 branch = "bpos"; 5508 else 5509 branch = "bge"; 5510 break; 5511 case GT: 5512 branch = "bg"; 5513 break; 5514 case LE: 5515 branch = "ble"; 5516 break; 5517 case LT: 5518 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 5519 branch = "bneg"; 5520 else 5521 branch = "bl"; 5522 break; 5523 case GEU: 5524 branch = "bgeu"; 5525 break; 5526 case GTU: 5527 branch = "bgu"; 5528 break; 5529 case LEU: 5530 branch = "bleu"; 5531 break; 5532 case LTU: 5533 branch = "blu"; 5534 break; 5535 5536 default: 5537 abort (); 5538 } 5539 strcpy (string, branch); 5540 } 5541 spaces -= strlen (branch); 5542 p = strchr (string, '\0'); 5543 5544 /* Now add the annulling, the label, and a possible noop. */ 5545 if (annul && ! far) 5546 { 5547 strcpy (p, ",a"); 5548 p += 2; 5549 spaces -= 2; 5550 } 5551 5552 if (! TARGET_V9) 5553 labelno = ""; 5554 else 5555 { 5556 rtx note; 5557 int v8 = 0; 5558 5559 if (! far && insn && INSN_ADDRESSES_SET_P ()) 5560 { 5561 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 5562 - INSN_ADDRESSES (INSN_UID (insn))); 5563 /* Leave some instructions for "slop". */ 5564 if (delta < -260000 || delta >= 260000) 5565 v8 = 1; 5566 } 5567 5568 if (mode == CCFPmode || mode == CCFPEmode) 5569 { 5570 static char v9_fcc_labelno[] = "%%fccX, "; 5571 /* Set the char indicating the number of the fcc reg to use. */ 5572 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; 5573 labelno = v9_fcc_labelno; 5574 if (v8) 5575 { 5576 if (REGNO (cc_reg) == SPARC_FCC_REG) 5577 labelno = ""; 5578 else 5579 abort (); 5580 } 5581 } 5582 else if (mode == CCXmode || mode == CCX_NOOVmode) 5583 { 5584 labelno = "%%xcc, "; 5585 if (v8) 5586 abort (); 5587 } 5588 else 5589 { 5590 labelno = "%%icc, "; 5591 if (v8) 5592 labelno = ""; 5593 } 5594 5595 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 5596 { 5597 strcpy (p, 5598 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 5599 ? ",pt" : ",pn"); 5600 p += 3; 5601 spaces -= 3; 5602 } 5603 } 5604 if (spaces > 0) 5605 *p++ = '\t'; 5606 else 5607 *p++ = ' '; 5608 strcpy (p, labelno); 5609 p = strchr (p, '\0'); 5610 if (far) 5611 { 5612 strcpy (p, ".+12\n\tnop\n\tb\t"); 5613 if (annul || noop) 5614 p[3] = '6'; 5615 p += 13; 5616 } 5617 *p++ = '%'; 5618 *p++ = 'l'; 5619 /* Set the char indicating the number of the operand containing the 5620 label_ref. */ 5621 *p++ = label + '0'; 5622 *p = '\0'; 5623 if (noop) 5624 strcpy (p, "\n\tnop"); 5625 5626 return string; 5627} 5628 5629/* Emit a library call comparison between floating point X and Y. 5630 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). 5631 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode 5632 values as arguments instead of the TFmode registers themselves, 5633 that's why we cannot call emit_float_lib_cmp. */ 5634void 5635sparc_emit_float_lib_cmp (x, y, comparison) 5636 rtx x, y; 5637 enum rtx_code comparison; 5638{ 5639 const char *qpfunc; 5640 rtx slot0, slot1, result, tem, tem2; 5641 enum machine_mode mode; 5642 5643 switch (comparison) 5644 { 5645 case EQ: 5646 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; 5647 break; 5648 5649 case NE: 5650 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; 5651 break; 5652 5653 case GT: 5654 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; 5655 break; 5656 5657 case GE: 5658 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; 5659 break; 5660 5661 case LT: 5662 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; 5663 break; 5664 5665 case LE: 5666 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; 5667 break; 5668 5669 case ORDERED: 5670 case UNORDERED: 5671 case UNGT: 5672 case UNLT: 5673 case UNEQ: 5674 case UNGE: 5675 case UNLE: 5676 case LTGT: 5677 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; 5678 break; 5679 5680 default: 5681 abort(); 5682 break; 5683 } 5684 5685 if (TARGET_ARCH64) 5686 { 5687 if (GET_CODE (x) != MEM) 5688 { 5689 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 5690 emit_insn (gen_rtx_SET (VOIDmode, slot0, x)); 5691 } 5692 else 5693 slot0 = x; 5694 5695 if (GET_CODE (y) != MEM) 5696 { 5697 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 5698 emit_insn (gen_rtx_SET (VOIDmode, slot1, y)); 5699 } 5700 else 5701 slot1 = y; 5702 5703 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 5704 DImode, 2, 5705 XEXP (slot0, 0), Pmode, 5706 XEXP (slot1, 0), Pmode); 5707 5708 mode = DImode; 5709 } 5710 else 5711 { 5712 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 5713 SImode, 2, 5714 x, TFmode, y, TFmode); 5715 5716 mode = SImode; 5717 } 5718 5719 5720 /* Immediately move the result of the libcall into a pseudo 5721 register so reload doesn't clobber the value if it needs 5722 the return register for a spill reg. */ 5723 result = gen_reg_rtx (mode); 5724 emit_move_insn (result, hard_libcall_value (mode)); 5725 5726 switch (comparison) 5727 { 5728 default: 5729 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); 5730 break; 5731 case ORDERED: 5732 case UNORDERED: 5733 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, 5734 NULL_RTX, mode, 0); 5735 break; 5736 case UNGT: 5737 case UNGE: 5738 emit_cmp_insn (result, const1_rtx, 5739 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); 5740 break; 5741 case UNLE: 5742 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); 5743 break; 5744 case UNLT: 5745 tem = gen_reg_rtx (mode); 5746 if (TARGET_ARCH32) 5747 emit_insn (gen_andsi3 (tem, result, const1_rtx)); 5748 else 5749 emit_insn (gen_anddi3 (tem, result, const1_rtx)); 5750 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); 5751 break; 5752 case UNEQ: 5753 case LTGT: 5754 tem = gen_reg_rtx (mode); 5755 if (TARGET_ARCH32) 5756 emit_insn (gen_addsi3 (tem, result, const1_rtx)); 5757 else 5758 emit_insn (gen_adddi3 (tem, result, const1_rtx)); 5759 tem2 = gen_reg_rtx (mode); 5760 if (TARGET_ARCH32) 5761 emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); 5762 else 5763 emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); 5764 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, 5765 NULL_RTX, mode, 0); 5766 break; 5767 } 5768} 5769 5770/* Generate an unsigned DImode to FP conversion. This is the same code 5771 optabs would emit if we didn't have TFmode patterns. */ 5772 5773void 5774sparc_emit_floatunsdi (operands) 5775 rtx operands[2]; 5776{ 5777 rtx neglab, donelab, i0, i1, f0, in, out; 5778 enum machine_mode mode; 5779 5780 out = operands[0]; 5781 in = force_reg (DImode, operands[1]); 5782 mode = GET_MODE (out); 5783 neglab = gen_label_rtx (); 5784 donelab = gen_label_rtx (); 5785 i0 = gen_reg_rtx (DImode); 5786 i1 = gen_reg_rtx (DImode); 5787 f0 = gen_reg_rtx (mode); 5788 5789 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); 5790 5791 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); 5792 emit_jump_insn (gen_jump (donelab)); 5793 emit_barrier (); 5794 5795 emit_label (neglab); 5796 5797 emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); 5798 emit_insn (gen_anddi3 (i1, in, const1_rtx)); 5799 emit_insn (gen_iordi3 (i0, i0, i1)); 5800 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); 5801 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); 5802 5803 emit_label (donelab); 5804} 5805 5806/* Return the string to output a conditional branch to LABEL, testing 5807 register REG. LABEL is the operand number of the label; REG is the 5808 operand number of the reg. OP is the conditional expression. The mode 5809 of REG says what kind of comparison we made. 5810 5811 REVERSED is non-zero if we should reverse the sense of the comparison. 5812 5813 ANNUL is non-zero if we should generate an annulling branch. 5814 5815 NOOP is non-zero if we have to follow this branch by a noop. */ 5816 5817char * 5818output_v9branch (op, dest, reg, label, reversed, annul, noop, insn) 5819 rtx op, dest; 5820 int reg, label; 5821 int reversed, annul, noop; 5822 rtx insn; 5823{ 5824 static char string[50]; 5825 enum rtx_code code = GET_CODE (op); 5826 enum machine_mode mode = GET_MODE (XEXP (op, 0)); 5827 rtx note; 5828 int far; 5829 char *p; 5830 5831 /* branch on register are limited to +-128KB. If it is too far away, 5832 change 5833 5834 brnz,pt %g1, .LC30 5835 5836 to 5837 5838 brz,pn %g1, .+12 5839 nop 5840 ba,pt %xcc, .LC30 5841 5842 and 5843 5844 brgez,a,pn %o1, .LC29 5845 5846 to 5847 5848 brlz,pt %o1, .+16 5849 nop 5850 ba,pt %xcc, .LC29 */ 5851 5852 far = get_attr_length (insn) >= 3; 5853 5854 /* If not floating-point or if EQ or NE, we can just reverse the code. */ 5855 if (reversed ^ far) 5856 code = reverse_condition (code); 5857 5858 /* Only 64 bit versions of these instructions exist. */ 5859 if (mode != DImode) 5860 abort (); 5861 5862 /* Start by writing the branch condition. */ 5863 5864 switch (code) 5865 { 5866 case NE: 5867 strcpy (string, "brnz"); 5868 break; 5869 5870 case EQ: 5871 strcpy (string, "brz"); 5872 break; 5873 5874 case GE: 5875 strcpy (string, "brgez"); 5876 break; 5877 5878 case LT: 5879 strcpy (string, "brlz"); 5880 break; 5881 5882 case LE: 5883 strcpy (string, "brlez"); 5884 break; 5885 5886 case GT: 5887 strcpy (string, "brgz"); 5888 break; 5889 5890 default: 5891 abort (); 5892 } 5893 5894 p = strchr (string, '\0'); 5895 5896 /* Now add the annulling, reg, label, and nop. */ 5897 if (annul && ! far) 5898 { 5899 strcpy (p, ",a"); 5900 p += 2; 5901 } 5902 5903 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 5904 { 5905 strcpy (p, 5906 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 5907 ? ",pt" : ",pn"); 5908 p += 3; 5909 } 5910 5911 *p = p < string + 8 ? '\t' : ' '; 5912 p++; 5913 *p++ = '%'; 5914 *p++ = '0' + reg; 5915 *p++ = ','; 5916 *p++ = ' '; 5917 if (far) 5918 { 5919 int veryfar = 1, delta; 5920 5921 if (INSN_ADDRESSES_SET_P ()) 5922 { 5923 delta = (INSN_ADDRESSES (INSN_UID (dest)) 5924 - INSN_ADDRESSES (INSN_UID (insn))); 5925 /* Leave some instructions for "slop". */ 5926 if (delta >= -260000 && delta < 260000) 5927 veryfar = 0; 5928 } 5929 5930 strcpy (p, ".+12\n\tnop\n\t"); 5931 if (annul || noop) 5932 p[3] = '6'; 5933 p += 11; 5934 if (veryfar) 5935 { 5936 strcpy (p, "b\t"); 5937 p += 2; 5938 } 5939 else 5940 { 5941 strcpy (p, "ba,pt\t%%xcc, "); 5942 p += 13; 5943 } 5944 } 5945 *p++ = '%'; 5946 *p++ = 'l'; 5947 *p++ = '0' + label; 5948 *p = '\0'; 5949 5950 if (noop) 5951 strcpy (p, "\n\tnop"); 5952 5953 return string; 5954} 5955 5956/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. 5957 Such instructions cannot be used in the delay slot of return insn on v9. 5958 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. 5959 */ 5960 5961static int 5962epilogue_renumber (where, test) 5963 register rtx *where; 5964 int test; 5965{ 5966 register const char *fmt; 5967 register int i; 5968 register enum rtx_code code; 5969 5970 if (*where == 0) 5971 return 0; 5972 5973 code = GET_CODE (*where); 5974 5975 switch (code) 5976 { 5977 case REG: 5978 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ 5979 return 1; 5980 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) 5981 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); 5982 case SCRATCH: 5983 case CC0: 5984 case PC: 5985 case CONST_INT: 5986 case CONST_DOUBLE: 5987 return 0; 5988 5989 /* Do not replace the frame pointer with the stack pointer because 5990 it can cause the delayed instruction to load below the stack. 5991 This occurs when instructions like: 5992 5993 (set (reg/i:SI 24 %i0) 5994 (mem/f:SI (plus:SI (reg/f:SI 30 %fp) 5995 (const_int -20 [0xffffffec])) 0)) 5996 5997 are in the return delayed slot. */ 5998 case PLUS: 5999 if (GET_CODE (XEXP (*where, 0)) == REG 6000 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM 6001 && (GET_CODE (XEXP (*where, 1)) != CONST_INT 6002 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) 6003 return 1; 6004 break; 6005 6006 case MEM: 6007 if (SPARC_STACK_BIAS 6008 && GET_CODE (XEXP (*where, 0)) == REG 6009 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) 6010 return 1; 6011 break; 6012 6013 default: 6014 break; 6015 } 6016 6017 fmt = GET_RTX_FORMAT (code); 6018 6019 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 6020 { 6021 if (fmt[i] == 'E') 6022 { 6023 register int j; 6024 for (j = XVECLEN (*where, i) - 1; j >= 0; j--) 6025 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) 6026 return 1; 6027 } 6028 else if (fmt[i] == 'e' 6029 && epilogue_renumber (&(XEXP (*where, i)), test)) 6030 return 1; 6031 } 6032 return 0; 6033} 6034 6035/* Leaf functions and non-leaf functions have different needs. */ 6036 6037static const int 6038reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; 6039 6040static const int 6041reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; 6042 6043static const int *const reg_alloc_orders[] = { 6044 reg_leaf_alloc_order, 6045 reg_nonleaf_alloc_order}; 6046 6047void 6048order_regs_for_local_alloc () 6049{ 6050 static int last_order_nonleaf = 1; 6051 6052 if (regs_ever_live[15] != last_order_nonleaf) 6053 { 6054 last_order_nonleaf = !last_order_nonleaf; 6055 memcpy ((char *) reg_alloc_order, 6056 (const char *) reg_alloc_orders[last_order_nonleaf], 6057 FIRST_PSEUDO_REGISTER * sizeof (int)); 6058 } 6059} 6060 6061/* Return 1 if REG and MEM are legitimate enough to allow the various 6062 mem<-->reg splits to be run. */ 6063 6064int 6065sparc_splitdi_legitimate (reg, mem) 6066 rtx reg; 6067 rtx mem; 6068{ 6069 /* Punt if we are here by mistake. */ 6070 if (! reload_completed) 6071 abort (); 6072 6073 /* We must have an offsettable memory reference. */ 6074 if (! offsettable_memref_p (mem)) 6075 return 0; 6076 6077 /* If we have legitimate args for ldd/std, we do not want 6078 the split to happen. */ 6079 if ((REGNO (reg) % 2) == 0 6080 && mem_min_alignment (mem, 8)) 6081 return 0; 6082 6083 /* Success. */ 6084 return 1; 6085} 6086 6087/* Return 1 if x and y are some kind of REG and they refer to 6088 different hard registers. This test is guarenteed to be 6089 run after reload. */ 6090 6091int 6092sparc_absnegfloat_split_legitimate (x, y) 6093 rtx x, y; 6094{ 6095 if (GET_CODE (x) != REG) 6096 return 0; 6097 if (GET_CODE (y) != REG) 6098 return 0; 6099 if (REGNO (x) == REGNO (y)) 6100 return 0; 6101 return 1; 6102} 6103 6104/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. 6105 This makes them candidates for using ldd and std insns. 6106 6107 Note reg1 and reg2 *must* be hard registers. */ 6108 6109int 6110registers_ok_for_ldd_peep (reg1, reg2) 6111 rtx reg1, reg2; 6112{ 6113 /* We might have been passed a SUBREG. */ 6114 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 6115 return 0; 6116 6117 if (REGNO (reg1) % 2 != 0) 6118 return 0; 6119 6120 /* Integer ldd is deprecated in SPARC V9 */ 6121 if (TARGET_V9 && REGNO (reg1) < 32) 6122 return 0; 6123 6124 return (REGNO (reg1) == REGNO (reg2) - 1); 6125} 6126 6127/* Return 1 if the addresses in mem1 and mem2 are suitable for use in 6128 an ldd or std insn. 6129 6130 This can only happen when addr1 and addr2, the addresses in mem1 6131 and mem2, are consecutive memory locations (addr1 + 4 == addr2). 6132 addr1 must also be aligned on a 64-bit boundary. 6133 6134 Also iff dependent_reg_rtx is not null it should not be used to 6135 compute the address for mem1, i.e. we cannot optimize a sequence 6136 like: 6137 ld [%o0], %o0 6138 ld [%o0 + 4], %o1 6139 to 6140 ldd [%o0], %o0 6141 nor: 6142 ld [%g3 + 4], %g3 6143 ld [%g3], %g2 6144 to 6145 ldd [%g3], %g2 6146 6147 But, note that the transformation from: 6148 ld [%g2 + 4], %g3 6149 ld [%g2], %g2 6150 to 6151 ldd [%g2], %g2 6152 is perfectly fine. Thus, the peephole2 patterns always pass us 6153 the destination register of the first load, never the second one. 6154 6155 For stores we don't have a similar problem, so dependent_reg_rtx is 6156 NULL_RTX. */ 6157 6158int 6159mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx) 6160 rtx mem1, mem2, dependent_reg_rtx; 6161{ 6162 rtx addr1, addr2; 6163 unsigned int reg1; 6164 int offset1; 6165 6166 /* The mems cannot be volatile. */ 6167 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) 6168 return 0; 6169 6170 /* MEM1 should be aligned on a 64-bit boundary. */ 6171 if (MEM_ALIGN (mem1) < 64) 6172 return 0; 6173 6174 addr1 = XEXP (mem1, 0); 6175 addr2 = XEXP (mem2, 0); 6176 6177 /* Extract a register number and offset (if used) from the first addr. */ 6178 if (GET_CODE (addr1) == PLUS) 6179 { 6180 /* If not a REG, return zero. */ 6181 if (GET_CODE (XEXP (addr1, 0)) != REG) 6182 return 0; 6183 else 6184 { 6185 reg1 = REGNO (XEXP (addr1, 0)); 6186 /* The offset must be constant! */ 6187 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) 6188 return 0; 6189 offset1 = INTVAL (XEXP (addr1, 1)); 6190 } 6191 } 6192 else if (GET_CODE (addr1) != REG) 6193 return 0; 6194 else 6195 { 6196 reg1 = REGNO (addr1); 6197 /* This was a simple (mem (reg)) expression. Offset is 0. */ 6198 offset1 = 0; 6199 } 6200 6201 /* Make sure the second address is a (mem (plus (reg) (const_int). */ 6202 if (GET_CODE (addr2) != PLUS) 6203 return 0; 6204 6205 if (GET_CODE (XEXP (addr2, 0)) != REG 6206 || GET_CODE (XEXP (addr2, 1)) != CONST_INT) 6207 return 0; 6208 6209 if (reg1 != REGNO (XEXP (addr2, 0))) 6210 return 0; 6211 6212 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) 6213 return 0; 6214 6215 /* The first offset must be evenly divisible by 8 to ensure the 6216 address is 64 bit aligned. */ 6217 if (offset1 % 8 != 0) 6218 return 0; 6219 6220 /* The offset for the second addr must be 4 more than the first addr. */ 6221 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) 6222 return 0; 6223 6224 /* All the tests passed. addr1 and addr2 are valid for ldd and std 6225 instructions. */ 6226 return 1; 6227} 6228 6229/* Return 1 if reg is a pseudo, or is the first register in 6230 a hard register pair. This makes it a candidate for use in 6231 ldd and std insns. */ 6232 6233int 6234register_ok_for_ldd (reg) 6235 rtx reg; 6236{ 6237 /* We might have been passed a SUBREG. */ 6238 if (GET_CODE (reg) != REG) 6239 return 0; 6240 6241 if (REGNO (reg) < FIRST_PSEUDO_REGISTER) 6242 return (REGNO (reg) % 2 == 0); 6243 else 6244 return 1; 6245} 6246 6247/* Print operand X (an rtx) in assembler syntax to file FILE. 6248 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 6249 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 6250 6251void 6252print_operand (file, x, code) 6253 FILE *file; 6254 rtx x; 6255 int code; 6256{ 6257 switch (code) 6258 { 6259 case '#': 6260 /* Output a 'nop' if there's nothing for the delay slot. */ 6261 if (dbr_sequence_length () == 0) 6262 fputs ("\n\t nop", file); 6263 return; 6264 case '*': 6265 /* Output an annul flag if there's nothing for the delay slot and we 6266 are optimizing. This is always used with '(' below. */ 6267 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; 6268 this is a dbx bug. So, we only do this when optimizing. */ 6269 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush. 6270 Always emit a nop in case the next instruction is a branch. */ 6271 if (dbr_sequence_length () == 0 6272 && (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6273 fputs (",a", file); 6274 return; 6275 case '(': 6276 /* Output a 'nop' if there's nothing for the delay slot and we are 6277 not optimizing. This is always used with '*' above. */ 6278 if (dbr_sequence_length () == 0 6279 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6280 fputs ("\n\t nop", file); 6281 return; 6282 case '_': 6283 /* Output the Embedded Medium/Anywhere code model base register. */ 6284 fputs (EMBMEDANY_BASE_REG, file); 6285 return; 6286 case '@': 6287 /* Print out what we are using as the frame pointer. This might 6288 be %fp, or might be %sp+offset. */ 6289 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */ 6290 fprintf (file, "%s+%d", frame_base_name, frame_base_offset); 6291 return; 6292 case 'Y': 6293 /* Adjust the operand to take into account a RESTORE operation. */ 6294 if (GET_CODE (x) == CONST_INT) 6295 break; 6296 else if (GET_CODE (x) != REG) 6297 output_operand_lossage ("invalid %%Y operand"); 6298 else if (REGNO (x) < 8) 6299 fputs (reg_names[REGNO (x)], file); 6300 else if (REGNO (x) >= 24 && REGNO (x) < 32) 6301 fputs (reg_names[REGNO (x)-16], file); 6302 else 6303 output_operand_lossage ("invalid %%Y operand"); 6304 return; 6305 case 'L': 6306 /* Print out the low order register name of a register pair. */ 6307 if (WORDS_BIG_ENDIAN) 6308 fputs (reg_names[REGNO (x)+1], file); 6309 else 6310 fputs (reg_names[REGNO (x)], file); 6311 return; 6312 case 'H': 6313 /* Print out the high order register name of a register pair. */ 6314 if (WORDS_BIG_ENDIAN) 6315 fputs (reg_names[REGNO (x)], file); 6316 else 6317 fputs (reg_names[REGNO (x)+1], file); 6318 return; 6319 case 'R': 6320 /* Print out the second register name of a register pair or quad. 6321 I.e., R (%o0) => %o1. */ 6322 fputs (reg_names[REGNO (x)+1], file); 6323 return; 6324 case 'S': 6325 /* Print out the third register name of a register quad. 6326 I.e., S (%o0) => %o2. */ 6327 fputs (reg_names[REGNO (x)+2], file); 6328 return; 6329 case 'T': 6330 /* Print out the fourth register name of a register quad. 6331 I.e., T (%o0) => %o3. */ 6332 fputs (reg_names[REGNO (x)+3], file); 6333 return; 6334 case 'x': 6335 /* Print a condition code register. */ 6336 if (REGNO (x) == SPARC_ICC_REG) 6337 { 6338 /* We don't handle CC[X]_NOOVmode because they're not supposed 6339 to occur here. */ 6340 if (GET_MODE (x) == CCmode) 6341 fputs ("%icc", file); 6342 else if (GET_MODE (x) == CCXmode) 6343 fputs ("%xcc", file); 6344 else 6345 abort (); 6346 } 6347 else 6348 /* %fccN register */ 6349 fputs (reg_names[REGNO (x)], file); 6350 return; 6351 case 'm': 6352 /* Print the operand's address only. */ 6353 output_address (XEXP (x, 0)); 6354 return; 6355 case 'r': 6356 /* In this case we need a register. Use %g0 if the 6357 operand is const0_rtx. */ 6358 if (x == const0_rtx 6359 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) 6360 { 6361 fputs ("%g0", file); 6362 return; 6363 } 6364 else 6365 break; 6366 6367 case 'A': 6368 switch (GET_CODE (x)) 6369 { 6370 case IOR: fputs ("or", file); break; 6371 case AND: fputs ("and", file); break; 6372 case XOR: fputs ("xor", file); break; 6373 default: output_operand_lossage ("invalid %%A operand"); 6374 } 6375 return; 6376 6377 case 'B': 6378 switch (GET_CODE (x)) 6379 { 6380 case IOR: fputs ("orn", file); break; 6381 case AND: fputs ("andn", file); break; 6382 case XOR: fputs ("xnor", file); break; 6383 default: output_operand_lossage ("invalid %%B operand"); 6384 } 6385 return; 6386 6387 /* These are used by the conditional move instructions. */ 6388 case 'c' : 6389 case 'C': 6390 { 6391 enum rtx_code rc = GET_CODE (x); 6392 6393 if (code == 'c') 6394 { 6395 enum machine_mode mode = GET_MODE (XEXP (x, 0)); 6396 if (mode == CCFPmode || mode == CCFPEmode) 6397 rc = reverse_condition_maybe_unordered (GET_CODE (x)); 6398 else 6399 rc = reverse_condition (GET_CODE (x)); 6400 } 6401 switch (rc) 6402 { 6403 case NE: fputs ("ne", file); break; 6404 case EQ: fputs ("e", file); break; 6405 case GE: fputs ("ge", file); break; 6406 case GT: fputs ("g", file); break; 6407 case LE: fputs ("le", file); break; 6408 case LT: fputs ("l", file); break; 6409 case GEU: fputs ("geu", file); break; 6410 case GTU: fputs ("gu", file); break; 6411 case LEU: fputs ("leu", file); break; 6412 case LTU: fputs ("lu", file); break; 6413 case LTGT: fputs ("lg", file); break; 6414 case UNORDERED: fputs ("u", file); break; 6415 case ORDERED: fputs ("o", file); break; 6416 case UNLT: fputs ("ul", file); break; 6417 case UNLE: fputs ("ule", file); break; 6418 case UNGT: fputs ("ug", file); break; 6419 case UNGE: fputs ("uge", file); break; 6420 case UNEQ: fputs ("ue", file); break; 6421 default: output_operand_lossage (code == 'c' 6422 ? "invalid %%c operand" 6423 : "invalid %%C operand"); 6424 } 6425 return; 6426 } 6427 6428 /* These are used by the movr instruction pattern. */ 6429 case 'd': 6430 case 'D': 6431 { 6432 enum rtx_code rc = (code == 'd' 6433 ? reverse_condition (GET_CODE (x)) 6434 : GET_CODE (x)); 6435 switch (rc) 6436 { 6437 case NE: fputs ("ne", file); break; 6438 case EQ: fputs ("e", file); break; 6439 case GE: fputs ("gez", file); break; 6440 case LT: fputs ("lz", file); break; 6441 case LE: fputs ("lez", file); break; 6442 case GT: fputs ("gz", file); break; 6443 default: output_operand_lossage (code == 'd' 6444 ? "invalid %%d operand" 6445 : "invalid %%D operand"); 6446 } 6447 return; 6448 } 6449 6450 case 'b': 6451 { 6452 /* Print a sign-extended character. */ 6453 int i = trunc_int_for_mode (INTVAL (x), QImode); 6454 fprintf (file, "%d", i); 6455 return; 6456 } 6457 6458 case 'f': 6459 /* Operand must be a MEM; write its address. */ 6460 if (GET_CODE (x) != MEM) 6461 output_operand_lossage ("invalid %%f operand"); 6462 output_address (XEXP (x, 0)); 6463 return; 6464 6465 case 0: 6466 /* Do nothing special. */ 6467 break; 6468 6469 default: 6470 /* Undocumented flag. */ 6471 output_operand_lossage ("invalid operand output code"); 6472 } 6473 6474 if (GET_CODE (x) == REG) 6475 fputs (reg_names[REGNO (x)], file); 6476 else if (GET_CODE (x) == MEM) 6477 { 6478 fputc ('[', file); 6479 /* Poor Sun assembler doesn't understand absolute addressing. */ 6480 if (CONSTANT_P (XEXP (x, 0))) 6481 fputs ("%g0+", file); 6482 output_address (XEXP (x, 0)); 6483 fputc (']', file); 6484 } 6485 else if (GET_CODE (x) == HIGH) 6486 { 6487 fputs ("%hi(", file); 6488 output_addr_const (file, XEXP (x, 0)); 6489 fputc (')', file); 6490 } 6491 else if (GET_CODE (x) == LO_SUM) 6492 { 6493 print_operand (file, XEXP (x, 0), 0); 6494 if (TARGET_CM_MEDMID) 6495 fputs ("+%l44(", file); 6496 else 6497 fputs ("+%lo(", file); 6498 output_addr_const (file, XEXP (x, 1)); 6499 fputc (')', file); 6500 } 6501 else if (GET_CODE (x) == CONST_DOUBLE 6502 && (GET_MODE (x) == VOIDmode 6503 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) 6504 { 6505 if (CONST_DOUBLE_HIGH (x) == 0) 6506 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); 6507 else if (CONST_DOUBLE_HIGH (x) == -1 6508 && CONST_DOUBLE_LOW (x) < 0) 6509 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); 6510 else 6511 output_operand_lossage ("long long constant not a valid immediate operand"); 6512 } 6513 else if (GET_CODE (x) == CONST_DOUBLE) 6514 output_operand_lossage ("floating point constant not a valid immediate operand"); 6515 else { output_addr_const (file, x); } 6516} 6517 6518/* Target hook for assembling integer objects. The sparc version has 6519 special handling for aligned DI-mode objects. */ 6520 6521static bool 6522sparc_assemble_integer (x, size, aligned_p) 6523 rtx x; 6524 unsigned int size; 6525 int aligned_p; 6526{ 6527 /* ??? We only output .xword's for symbols and only then in environments 6528 where the assembler can handle them. */ 6529 if (aligned_p && size == 8 6530 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) 6531 { 6532 if (TARGET_V9) 6533 { 6534 assemble_integer_with_op ("\t.xword\t", x); 6535 return true; 6536 } 6537 else 6538 { 6539 assemble_aligned_integer (4, const0_rtx); 6540 assemble_aligned_integer (4, x); 6541 return true; 6542 } 6543 } 6544 return default_assemble_integer (x, size, aligned_p); 6545} 6546 6547/* Return the value of a code used in the .proc pseudo-op that says 6548 what kind of result this function returns. For non-C types, we pick 6549 the closest C type. */ 6550 6551#ifndef CHAR_TYPE_SIZE 6552#define CHAR_TYPE_SIZE BITS_PER_UNIT 6553#endif 6554 6555#ifndef SHORT_TYPE_SIZE 6556#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) 6557#endif 6558 6559#ifndef INT_TYPE_SIZE 6560#define INT_TYPE_SIZE BITS_PER_WORD 6561#endif 6562 6563#ifndef LONG_TYPE_SIZE 6564#define LONG_TYPE_SIZE BITS_PER_WORD 6565#endif 6566 6567#ifndef LONG_LONG_TYPE_SIZE 6568#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) 6569#endif 6570 6571#ifndef FLOAT_TYPE_SIZE 6572#define FLOAT_TYPE_SIZE BITS_PER_WORD 6573#endif 6574 6575#ifndef DOUBLE_TYPE_SIZE 6576#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 6577#endif 6578 6579#ifndef LONG_DOUBLE_TYPE_SIZE 6580#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 6581#endif 6582 6583unsigned long 6584sparc_type_code (type) 6585 register tree type; 6586{ 6587 register unsigned long qualifiers = 0; 6588 register unsigned shift; 6589 6590 /* Only the first 30 bits of the qualifier are valid. We must refrain from 6591 setting more, since some assemblers will give an error for this. Also, 6592 we must be careful to avoid shifts of 32 bits or more to avoid getting 6593 unpredictable results. */ 6594 6595 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) 6596 { 6597 switch (TREE_CODE (type)) 6598 { 6599 case ERROR_MARK: 6600 return qualifiers; 6601 6602 case ARRAY_TYPE: 6603 qualifiers |= (3 << shift); 6604 break; 6605 6606 case FUNCTION_TYPE: 6607 case METHOD_TYPE: 6608 qualifiers |= (2 << shift); 6609 break; 6610 6611 case POINTER_TYPE: 6612 case REFERENCE_TYPE: 6613 case OFFSET_TYPE: 6614 qualifiers |= (1 << shift); 6615 break; 6616 6617 case RECORD_TYPE: 6618 return (qualifiers | 8); 6619 6620 case UNION_TYPE: 6621 case QUAL_UNION_TYPE: 6622 return (qualifiers | 9); 6623 6624 case ENUMERAL_TYPE: 6625 return (qualifiers | 10); 6626 6627 case VOID_TYPE: 6628 return (qualifiers | 16); 6629 6630 case INTEGER_TYPE: 6631 /* If this is a range type, consider it to be the underlying 6632 type. */ 6633 if (TREE_TYPE (type) != 0) 6634 break; 6635 6636 /* Carefully distinguish all the standard types of C, 6637 without messing up if the language is not C. We do this by 6638 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to 6639 look at both the names and the above fields, but that's redundant. 6640 Any type whose size is between two C types will be considered 6641 to be the wider of the two types. Also, we do not have a 6642 special code to use for "long long", so anything wider than 6643 long is treated the same. Note that we can't distinguish 6644 between "int" and "long" in this code if they are the same 6645 size, but that's fine, since neither can the assembler. */ 6646 6647 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) 6648 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2)); 6649 6650 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) 6651 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3)); 6652 6653 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) 6654 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4)); 6655 6656 else 6657 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5)); 6658 6659 case REAL_TYPE: 6660 /* If this is a range type, consider it to be the underlying 6661 type. */ 6662 if (TREE_TYPE (type) != 0) 6663 break; 6664 6665 /* Carefully distinguish all the standard types of C, 6666 without messing up if the language is not C. */ 6667 6668 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) 6669 return (qualifiers | 6); 6670 6671 else 6672 return (qualifiers | 7); 6673 6674 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ 6675 /* ??? We need to distinguish between double and float complex types, 6676 but I don't know how yet because I can't reach this code from 6677 existing front-ends. */ 6678 return (qualifiers | 7); /* Who knows? */ 6679 6680 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */ 6681 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */ 6682 case FILE_TYPE: /* GNU Pascal FILE type. */ 6683 case SET_TYPE: /* GNU Pascal SET type. */ 6684 case LANG_TYPE: /* ? */ 6685 return qualifiers; 6686 6687 default: 6688 abort (); /* Not a type! */ 6689 } 6690 } 6691 6692 return qualifiers; 6693} 6694 6695/* Nested function support. */ 6696 6697/* Emit RTL insns to initialize the variable parts of a trampoline. 6698 FNADDR is an RTX for the address of the function's pure code. 6699 CXT is an RTX for the static chain value for the function. 6700 6701 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi 6702 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes 6703 (to store insns). This is a bit excessive. Perhaps a different 6704 mechanism would be better here. 6705 6706 Emit enough FLUSH insns to synchronize the data and instruction caches. */ 6707 6708void 6709sparc_initialize_trampoline (tramp, fnaddr, cxt) 6710 rtx tramp, fnaddr, cxt; 6711{ 6712 /* SPARC 32 bit trampoline: 6713 6714 sethi %hi(fn), %g1 6715 sethi %hi(static), %g2 6716 jmp %g1+%lo(fn) 6717 or %g2, %lo(static), %g2 6718 6719 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii 6720 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii 6721 */ 6722#ifdef TRANSFER_FROM_TRAMPOLINE 6723 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 6724 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 6725#endif 6726 6727 emit_move_insn 6728 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), 6729 expand_binop (SImode, ior_optab, 6730 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 6731 size_int (10), 0, 1), 6732 GEN_INT (trunc_int_for_mode (0x03000000, SImode)), 6733 NULL_RTX, 1, OPTAB_DIRECT)); 6734 6735 emit_move_insn 6736 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 6737 expand_binop (SImode, ior_optab, 6738 expand_shift (RSHIFT_EXPR, SImode, cxt, 6739 size_int (10), 0, 1), 6740 GEN_INT (trunc_int_for_mode (0x05000000, SImode)), 6741 NULL_RTX, 1, OPTAB_DIRECT)); 6742 6743 emit_move_insn 6744 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 6745 expand_binop (SImode, ior_optab, 6746 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), 6747 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), 6748 NULL_RTX, 1, OPTAB_DIRECT)); 6749 6750 emit_move_insn 6751 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 6752 expand_binop (SImode, ior_optab, 6753 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), 6754 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), 6755 NULL_RTX, 1, OPTAB_DIRECT)); 6756 6757 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is 6758 aligned on a 16 byte boundary so one flush clears it all. */ 6759 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); 6760 if (sparc_cpu != PROCESSOR_ULTRASPARC) 6761 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, 6762 plus_constant (tramp, 8))))); 6763} 6764 6765/* The 64 bit version is simpler because it makes more sense to load the 6766 values as "immediate" data out of the trampoline. It's also easier since 6767 we can read the PC without clobbering a register. */ 6768 6769void 6770sparc64_initialize_trampoline (tramp, fnaddr, cxt) 6771 rtx tramp, fnaddr, cxt; 6772{ 6773#ifdef TRANSFER_FROM_TRAMPOLINE 6774 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), 6775 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 6776#endif 6777 6778 /* 6779 rd %pc, %g1 6780 ldx [%g1+24], %g5 6781 jmp %g5 6782 ldx [%g1+16], %g5 6783 +16 bytes data 6784 */ 6785 6786 emit_move_insn (gen_rtx_MEM (SImode, tramp), 6787 GEN_INT (trunc_int_for_mode (0x83414000, SImode))); 6788 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 6789 GEN_INT (trunc_int_for_mode (0xca586018, SImode))); 6790 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 6791 GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); 6792 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 6793 GEN_INT (trunc_int_for_mode (0xca586010, SImode))); 6794 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); 6795 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); 6796 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); 6797 6798 if (sparc_cpu != PROCESSOR_ULTRASPARC) 6799 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); 6800} 6801 6802/* Subroutines to support a flat (single) register window calling 6803 convention. */ 6804 6805/* Single-register window sparc stack frames look like: 6806 6807 Before call After call 6808 +-----------------------+ +-----------------------+ 6809 high | | | | 6810 mem | caller's temps. | | caller's temps. | 6811 | | | | 6812 +-----------------------+ +-----------------------+ 6813 | | | | 6814 | arguments on stack. | | arguments on stack. | 6815 | | | | 6816 +-----------------------+FP+92->+-----------------------+ 6817 | 6 words to save | | 6 words to save | 6818 | arguments passed | | arguments passed | 6819 | in registers, even | | in registers, even | 6820 | if not passed. | | if not passed. | 6821 SP+68->+-----------------------+FP+68->+-----------------------+ 6822 | 1 word struct addr | | 1 word struct addr | 6823 +-----------------------+FP+64->+-----------------------+ 6824 | | | | 6825 | 16 word reg save area | | 16 word reg save area | 6826 | | | | 6827 SP->+-----------------------+ FP->+-----------------------+ 6828 | 4 word area for | 6829 | fp/alu reg moves | 6830 FP-16->+-----------------------+ 6831 | | 6832 | local variables | 6833 | | 6834 +-----------------------+ 6835 | | 6836 | fp register save | 6837 | | 6838 +-----------------------+ 6839 | | 6840 | gp register save | 6841 | | 6842 +-----------------------+ 6843 | | 6844 | alloca allocations | 6845 | | 6846 +-----------------------+ 6847 | | 6848 | arguments on stack | 6849 | | 6850 SP+92->+-----------------------+ 6851 | 6 words to save | 6852 | arguments passed | 6853 | in registers, even | 6854 low | if not passed. | 6855 memory SP+68->+-----------------------+ 6856 | 1 word struct addr | 6857 SP+64->+-----------------------+ 6858 | | 6859 I 16 word reg save area | 6860 | | 6861 SP->+-----------------------+ */ 6862 6863/* Structure to be filled in by sparc_flat_compute_frame_size with register 6864 save masks, and offsets for the current function. */ 6865 6866struct sparc_frame_info 6867{ 6868 unsigned long total_size; /* # bytes that the entire frame takes up. */ 6869 unsigned long var_size; /* # bytes that variables take up. */ 6870 unsigned long args_size; /* # bytes that outgoing arguments take up. */ 6871 unsigned long extra_size; /* # bytes of extra gunk. */ 6872 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ 6873 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ 6874 unsigned long gmask; /* Mask of saved gp registers. */ 6875 unsigned long fmask; /* Mask of saved fp registers. */ 6876 unsigned long reg_offset; /* Offset from new sp to store regs. */ 6877 int initialized; /* Nonzero if frame size already calculated. */ 6878}; 6879 6880/* Current frame information calculated by sparc_flat_compute_frame_size. */ 6881struct sparc_frame_info current_frame_info; 6882 6883/* Zero structure to initialize current_frame_info. */ 6884struct sparc_frame_info zero_frame_info; 6885 6886/* Tell prologue and epilogue if register REGNO should be saved / restored. */ 6887 6888#define RETURN_ADDR_REGNUM 15 6889#define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM)) 6890#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) 6891 6892#define MUST_SAVE_REGISTER(regno) \ 6893 ((regs_ever_live[regno] && !call_used_regs[regno]) \ 6894 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ 6895 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM])) 6896 6897/* Return the bytes needed to compute the frame pointer from the current 6898 stack pointer. */ 6899 6900unsigned long 6901sparc_flat_compute_frame_size (size) 6902 int size; /* # of var. bytes allocated. */ 6903{ 6904 int regno; 6905 unsigned long total_size; /* # bytes that the entire frame takes up. */ 6906 unsigned long var_size; /* # bytes that variables take up. */ 6907 unsigned long args_size; /* # bytes that outgoing arguments take up. */ 6908 unsigned long extra_size; /* # extra bytes. */ 6909 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */ 6910 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */ 6911 unsigned long gmask; /* Mask of saved gp registers. */ 6912 unsigned long fmask; /* Mask of saved fp registers. */ 6913 unsigned long reg_offset; /* Offset to register save area. */ 6914 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */ 6915 6916 /* This is the size of the 16 word reg save area, 1 word struct addr 6917 area, and 4 word fp/alu register copy area. */ 6918 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0); 6919 var_size = size; 6920 gp_reg_size = 0; 6921 fp_reg_size = 0; 6922 gmask = 0; 6923 fmask = 0; 6924 reg_offset = 0; 6925 need_aligned_p = 0; 6926 6927 args_size = 0; 6928 if (!leaf_function_p ()) 6929 { 6930 /* Also include the size needed for the 6 parameter registers. */ 6931 args_size = current_function_outgoing_args_size + 24; 6932 } 6933 total_size = var_size + args_size; 6934 6935 /* Calculate space needed for gp registers. */ 6936 for (regno = 1; regno <= 31; regno++) 6937 { 6938 if (MUST_SAVE_REGISTER (regno)) 6939 { 6940 /* If we need to save two regs in a row, ensure there's room to bump 6941 up the address to align it to a doubleword boundary. */ 6942 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1)) 6943 { 6944 if (gp_reg_size % 8 != 0) 6945 gp_reg_size += 4; 6946 gp_reg_size += 2 * UNITS_PER_WORD; 6947 gmask |= 3 << regno; 6948 regno++; 6949 need_aligned_p = 1; 6950 } 6951 else 6952 { 6953 gp_reg_size += UNITS_PER_WORD; 6954 gmask |= 1 << regno; 6955 } 6956 } 6957 } 6958 6959 /* Calculate space needed for fp registers. */ 6960 for (regno = 32; regno <= 63; regno++) 6961 { 6962 if (regs_ever_live[regno] && !call_used_regs[regno]) 6963 { 6964 fp_reg_size += UNITS_PER_WORD; 6965 fmask |= 1 << (regno - 32); 6966 } 6967 } 6968 6969 if (gmask || fmask) 6970 { 6971 int n; 6972 reg_offset = FIRST_PARM_OFFSET(0) + args_size; 6973 /* Ensure save area is 8 byte aligned if we need it. */ 6974 n = reg_offset % 8; 6975 if (need_aligned_p && n != 0) 6976 { 6977 total_size += 8 - n; 6978 reg_offset += 8 - n; 6979 } 6980 total_size += gp_reg_size + fp_reg_size; 6981 } 6982 6983 /* If we must allocate a stack frame at all, we must also allocate 6984 room for register window spillage, so as to be binary compatible 6985 with libraries and operating systems that do not use -mflat. */ 6986 if (total_size > 0) 6987 total_size += extra_size; 6988 else 6989 extra_size = 0; 6990 6991 total_size = SPARC_STACK_ALIGN (total_size); 6992 6993 /* Save other computed information. */ 6994 current_frame_info.total_size = total_size; 6995 current_frame_info.var_size = var_size; 6996 current_frame_info.args_size = args_size; 6997 current_frame_info.extra_size = extra_size; 6998 current_frame_info.gp_reg_size = gp_reg_size; 6999 current_frame_info.fp_reg_size = fp_reg_size; 7000 current_frame_info.gmask = gmask; 7001 current_frame_info.fmask = fmask; 7002 current_frame_info.reg_offset = reg_offset; 7003 current_frame_info.initialized = reload_completed; 7004 7005 /* Ok, we're done. */ 7006 return total_size; 7007} 7008 7009/* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset 7010 OFFSET. 7011 7012 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for 7013 appropriate alignment and use DOUBLEWORD_OP when we can. We assume 7014 [BASE_REG+OFFSET] will always be a valid address. 7015 7016 WORD_OP is either "st" for save, "ld" for restore. 7017 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */ 7018 7019void 7020sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op, 7021 doubleword_op, base_offset) 7022 FILE *file; 7023 const char *base_reg; 7024 unsigned int offset; 7025 unsigned long gmask; 7026 unsigned long fmask; 7027 const char *word_op; 7028 const char *doubleword_op; 7029 unsigned long base_offset; 7030{ 7031 int regno; 7032 7033 if (gmask == 0 && fmask == 0) 7034 return; 7035 7036 /* Save registers starting from high to low. We've already saved the 7037 previous frame pointer and previous return address for the debugger's 7038 sake. The debugger allows us to not need a nop in the epilog if at least 7039 one register is reloaded in addition to return address. */ 7040 7041 if (gmask) 7042 { 7043 for (regno = 1; regno <= 31; regno++) 7044 { 7045 if ((gmask & (1L << regno)) != 0) 7046 { 7047 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0)) 7048 { 7049 /* We can save two registers in a row. If we're not at a 7050 double word boundary, move to one. 7051 sparc_flat_compute_frame_size ensures there's room to do 7052 this. */ 7053 if (offset % 8 != 0) 7054 offset += UNITS_PER_WORD; 7055 7056 if (word_op[0] == 's') 7057 { 7058 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7059 doubleword_op, reg_names[regno], 7060 base_reg, offset); 7061 if (dwarf2out_do_frame ()) 7062 { 7063 char *l = dwarf2out_cfi_label (); 7064 dwarf2out_reg_save (l, regno, offset + base_offset); 7065 dwarf2out_reg_save 7066 (l, regno+1, offset+base_offset + UNITS_PER_WORD); 7067 } 7068 } 7069 else 7070 fprintf (file, "\t%s\t[%s+%d], %s\n", 7071 doubleword_op, base_reg, offset, 7072 reg_names[regno]); 7073 7074 offset += 2 * UNITS_PER_WORD; 7075 regno++; 7076 } 7077 else 7078 { 7079 if (word_op[0] == 's') 7080 { 7081 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7082 word_op, reg_names[regno], 7083 base_reg, offset); 7084 if (dwarf2out_do_frame ()) 7085 dwarf2out_reg_save ("", regno, offset + base_offset); 7086 } 7087 else 7088 fprintf (file, "\t%s\t[%s+%d], %s\n", 7089 word_op, base_reg, offset, reg_names[regno]); 7090 7091 offset += UNITS_PER_WORD; 7092 } 7093 } 7094 } 7095 } 7096 7097 if (fmask) 7098 { 7099 for (regno = 32; regno <= 63; regno++) 7100 { 7101 if ((fmask & (1L << (regno - 32))) != 0) 7102 { 7103 if (word_op[0] == 's') 7104 { 7105 fprintf (file, "\t%s\t%s, [%s+%d]\n", 7106 word_op, reg_names[regno], 7107 base_reg, offset); 7108 if (dwarf2out_do_frame ()) 7109 dwarf2out_reg_save ("", regno, offset + base_offset); 7110 } 7111 else 7112 fprintf (file, "\t%s\t[%s+%d], %s\n", 7113 word_op, base_reg, offset, reg_names[regno]); 7114 7115 offset += UNITS_PER_WORD; 7116 } 7117 } 7118 } 7119} 7120 7121/* Set up the stack and frame (if desired) for the function. */ 7122 7123static void 7124sparc_flat_function_prologue (file, size) 7125 FILE *file; 7126 HOST_WIDE_INT size; 7127{ 7128 const char *sp_str = reg_names[STACK_POINTER_REGNUM]; 7129 unsigned long gmask = current_frame_info.gmask; 7130 7131 sparc_output_scratch_registers (file); 7132 7133 /* This is only for the human reader. */ 7134 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START); 7135 fprintf (file, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n", 7136 ASM_COMMENT_START, 7137 current_frame_info.var_size, 7138 current_frame_info.gp_reg_size / 4, 7139 current_frame_info.fp_reg_size / 4, 7140 current_function_outgoing_args_size, 7141 current_frame_info.extra_size); 7142 7143 size = SPARC_STACK_ALIGN (size); 7144 size = (! current_frame_info.initialized 7145 ? sparc_flat_compute_frame_size (size) 7146 : current_frame_info.total_size); 7147 7148 /* These cases shouldn't happen. Catch them now. */ 7149 if (size == 0 && (gmask || current_frame_info.fmask)) 7150 abort (); 7151 7152 /* Allocate our stack frame by decrementing %sp. 7153 At present, the only algorithm gdb can use to determine if this is a 7154 flat frame is if we always set %i7 if we set %sp. This can be optimized 7155 in the future by putting in some sort of debugging information that says 7156 this is a `flat' function. However, there is still the case of debugging 7157 code without such debugging information (including cases where most fns 7158 have such info, but there is one that doesn't). So, always do this now 7159 so we don't get a lot of code out there that gdb can't handle. 7160 If the frame pointer isn't needn't then that's ok - gdb won't be able to 7161 distinguish us from a non-flat function but there won't (and shouldn't) 7162 be any differences anyway. The return pc is saved (if necessary) right 7163 after %i7 so gdb won't have to look too far to find it. */ 7164 if (size > 0) 7165 { 7166 unsigned int reg_offset = current_frame_info.reg_offset; 7167 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 7168 static const char *const t1_str = "%g1"; 7169 7170 /* Things get a little tricky if local variables take up more than ~4096 7171 bytes and outgoing arguments take up more than ~4096 bytes. When that 7172 happens, the register save area can't be accessed from either end of 7173 the frame. Handle this by decrementing %sp to the start of the gp 7174 register save area, save the regs, update %i7, and then set %sp to its 7175 final value. Given that we only have one scratch register to play 7176 with it is the cheapest solution, and it helps gdb out as it won't 7177 slow down recognition of flat functions. 7178 Don't change the order of insns emitted here without checking with 7179 the gdb folk first. */ 7180 7181 /* Is the entire register save area offsettable from %sp? */ 7182 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) 7183 { 7184 if (size <= 4096) 7185 { 7186 fprintf (file, "\tadd\t%s, %d, %s\n", 7187 sp_str, (int) -size, sp_str); 7188 if (gmask & HARD_FRAME_POINTER_MASK) 7189 { 7190 fprintf (file, "\tst\t%s, [%s+%d]\n", 7191 fp_str, sp_str, reg_offset); 7192 fprintf (file, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n", 7193 sp_str, (int) -size, fp_str, ASM_COMMENT_START); 7194 reg_offset += 4; 7195 } 7196 } 7197 else 7198 { 7199 fprintf (file, "\tset\t"); 7200 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); 7201 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", 7202 t1_str, sp_str, t1_str, sp_str); 7203 if (gmask & HARD_FRAME_POINTER_MASK) 7204 { 7205 fprintf (file, "\tst\t%s, [%s+%d]\n", 7206 fp_str, sp_str, reg_offset); 7207 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7208 sp_str, t1_str, fp_str, ASM_COMMENT_START); 7209 reg_offset += 4; 7210 } 7211 } 7212 if (dwarf2out_do_frame ()) 7213 { 7214 char *l = dwarf2out_cfi_label (); 7215 if (gmask & HARD_FRAME_POINTER_MASK) 7216 { 7217 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7218 reg_offset - 4 - size); 7219 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7220 } 7221 else 7222 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size); 7223 } 7224 if (gmask & RETURN_ADDR_MASK) 7225 { 7226 fprintf (file, "\tst\t%s, [%s+%d]\n", 7227 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset); 7228 if (dwarf2out_do_frame ()) 7229 dwarf2out_return_save ("", reg_offset - size); 7230 reg_offset += 4; 7231 } 7232 sparc_flat_save_restore (file, sp_str, reg_offset, 7233 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7234 current_frame_info.fmask, 7235 "st", "std", -size); 7236 } 7237 else 7238 { 7239 /* Subtract %sp in two steps, but make sure there is always a 7240 64 byte register save area, and %sp is properly aligned. */ 7241 /* Amount to decrement %sp by, the first time. */ 7242 unsigned HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16; 7243 /* Offset to register save area from %sp. */ 7244 unsigned HOST_WIDE_INT offset = size1 - (size - reg_offset); 7245 7246 if (size1 <= 4096) 7247 { 7248 fprintf (file, "\tadd\t%s, %d, %s\n", 7249 sp_str, (int) -size1, sp_str); 7250 if (gmask & HARD_FRAME_POINTER_MASK) 7251 { 7252 fprintf (file, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n", 7253 fp_str, sp_str, (int) offset, sp_str, (int) -size1, 7254 fp_str, ASM_COMMENT_START); 7255 offset += 4; 7256 } 7257 } 7258 else 7259 { 7260 fprintf (file, "\tset\t"); 7261 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); 7262 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", 7263 t1_str, sp_str, t1_str, sp_str); 7264 if (gmask & HARD_FRAME_POINTER_MASK) 7265 { 7266 fprintf (file, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n", 7267 fp_str, sp_str, (int) offset, sp_str, t1_str, 7268 fp_str, ASM_COMMENT_START); 7269 offset += 4; 7270 } 7271 } 7272 if (dwarf2out_do_frame ()) 7273 { 7274 char *l = dwarf2out_cfi_label (); 7275 if (gmask & HARD_FRAME_POINTER_MASK) 7276 { 7277 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM, 7278 offset - 4 - size1); 7279 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0); 7280 } 7281 else 7282 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1); 7283 } 7284 if (gmask & RETURN_ADDR_MASK) 7285 { 7286 fprintf (file, "\tst\t%s, [%s+%d]\n", 7287 reg_names[RETURN_ADDR_REGNUM], sp_str, (int) offset); 7288 if (dwarf2out_do_frame ()) 7289 /* offset - size1 == reg_offset - size 7290 if reg_offset were updated above like offset. */ 7291 dwarf2out_return_save ("", offset - size1); 7292 offset += 4; 7293 } 7294 sparc_flat_save_restore (file, sp_str, offset, 7295 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7296 current_frame_info.fmask, 7297 "st", "std", -size1); 7298 fprintf (file, "\tset\t"); 7299 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size - size1); 7300 fprintf (file, ", %s\n\tsub\t%s, %s, %s\n", 7301 t1_str, sp_str, t1_str, sp_str); 7302 if (dwarf2out_do_frame ()) 7303 if (! (gmask & HARD_FRAME_POINTER_MASK)) 7304 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size); 7305 } 7306 } 7307 7308 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START); 7309} 7310 7311/* Do any necessary cleanup after a function to restore stack, frame, 7312 and regs. */ 7313 7314static void 7315sparc_flat_function_epilogue (file, size) 7316 FILE *file; 7317 HOST_WIDE_INT size; 7318{ 7319 rtx epilogue_delay = current_function_epilogue_delay_list; 7320 int noepilogue = FALSE; 7321 7322 /* This is only for the human reader. */ 7323 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START); 7324 7325 /* The epilogue does not depend on any registers, but the stack 7326 registers, so we assume that if we have 1 pending nop, it can be 7327 ignored, and 2 it must be filled (2 nops occur for integer 7328 multiply and divide). */ 7329 7330 size = SPARC_STACK_ALIGN (size); 7331 size = (!current_frame_info.initialized 7332 ? sparc_flat_compute_frame_size (size) 7333 : current_frame_info.total_size); 7334 7335 if (size == 0 && epilogue_delay == 0) 7336 { 7337 rtx insn = get_last_insn (); 7338 7339 /* If the last insn was a BARRIER, we don't have to write any code 7340 because a jump (aka return) was put there. */ 7341 if (GET_CODE (insn) == NOTE) 7342 insn = prev_nonnote_insn (insn); 7343 if (insn && GET_CODE (insn) == BARRIER) 7344 noepilogue = TRUE; 7345 } 7346 7347 if (!noepilogue) 7348 { 7349 unsigned HOST_WIDE_INT reg_offset = current_frame_info.reg_offset; 7350 unsigned HOST_WIDE_INT size1; 7351 const char *const sp_str = reg_names[STACK_POINTER_REGNUM]; 7352 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM]; 7353 static const char *const t1_str = "%g1"; 7354 7355 /* In the reload sequence, we don't need to fill the load delay 7356 slots for most of the loads, also see if we can fill the final 7357 delay slot if not otherwise filled by the reload sequence. */ 7358 7359 if (size > 4095) 7360 { 7361 fprintf (file, "\tset\t"); 7362 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); 7363 fprintf (file, ", %s\n", t1_str); 7364 } 7365 7366 if (frame_pointer_needed) 7367 { 7368 if (size > 4095) 7369 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n", 7370 fp_str, t1_str, sp_str, ASM_COMMENT_START); 7371 else 7372 fprintf (file,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n", 7373 fp_str, (int) size, sp_str, ASM_COMMENT_START); 7374 } 7375 7376 /* Is the entire register save area offsettable from %sp? */ 7377 if (reg_offset < 4096 - 64 * (unsigned) UNITS_PER_WORD) 7378 { 7379 size1 = 0; 7380 } 7381 else 7382 { 7383 /* Restore %sp in two steps, but make sure there is always a 7384 64 byte register save area, and %sp is properly aligned. */ 7385 /* Amount to increment %sp by, the first time. */ 7386 size1 = ((reg_offset - 64 - 16) + 15) & -16; 7387 /* Offset to register save area from %sp. */ 7388 reg_offset = size1 - reg_offset; 7389 7390 fprintf (file, "\tset\t"); 7391 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size1); 7392 fprintf (file, ", %s\n\tadd\t%s, %s, %s\n", 7393 t1_str, sp_str, t1_str, sp_str); 7394 } 7395 7396 /* We must restore the frame pointer and return address reg first 7397 because they are treated specially by the prologue output code. */ 7398 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK) 7399 { 7400 fprintf (file, "\tld\t[%s+%d], %s\n", 7401 sp_str, (int) reg_offset, fp_str); 7402 reg_offset += 4; 7403 } 7404 if (current_frame_info.gmask & RETURN_ADDR_MASK) 7405 { 7406 fprintf (file, "\tld\t[%s+%d], %s\n", 7407 sp_str, (int) reg_offset, reg_names[RETURN_ADDR_REGNUM]); 7408 reg_offset += 4; 7409 } 7410 7411 /* Restore any remaining saved registers. */ 7412 sparc_flat_save_restore (file, sp_str, reg_offset, 7413 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK), 7414 current_frame_info.fmask, 7415 "ld", "ldd", 0); 7416 7417 /* If we had to increment %sp in two steps, record it so the second 7418 restoration in the epilogue finishes up. */ 7419 if (size1 > 0) 7420 { 7421 size -= size1; 7422 if (size > 4095) 7423 { 7424 fprintf (file, "\tset\t"); 7425 fprintf (file, HOST_WIDE_INT_PRINT_DEC, size); 7426 fprintf (file, ", %s\n", t1_str); 7427 } 7428 } 7429 7430 if (current_function_returns_struct) 7431 fprintf (file, "\tjmp\t%%o7+12\n"); 7432 else 7433 fprintf (file, "\tretl\n"); 7434 7435 /* If the only register saved is the return address, we need a 7436 nop, unless we have an instruction to put into it. Otherwise 7437 we don't since reloading multiple registers doesn't reference 7438 the register being loaded. */ 7439 7440 if (epilogue_delay) 7441 { 7442 if (size) 7443 abort (); 7444 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1); 7445 } 7446 7447 else if (size > 4095) 7448 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str); 7449 7450 else if (size > 0) 7451 fprintf (file, "\tadd\t%s, %d, %s\n", sp_str, (int) size, sp_str); 7452 7453 else 7454 fprintf (file, "\tnop\n"); 7455 } 7456 7457 /* Reset state info for each function. */ 7458 current_frame_info = zero_frame_info; 7459 7460 sparc_output_deferred_case_vectors (); 7461} 7462 7463/* Define the number of delay slots needed for the function epilogue. 7464 7465 On the sparc, we need a slot if either no stack has been allocated, 7466 or the only register saved is the return register. */ 7467 7468int 7469sparc_flat_epilogue_delay_slots () 7470{ 7471 if (!current_frame_info.initialized) 7472 (void) sparc_flat_compute_frame_size (get_frame_size ()); 7473 7474 if (current_frame_info.total_size == 0) 7475 return 1; 7476 7477 return 0; 7478} 7479 7480/* Return true if TRIAL is a valid insn for the epilogue delay slot. 7481 Any single length instruction which doesn't reference the stack or frame 7482 pointer is OK. */ 7483 7484int 7485sparc_flat_eligible_for_epilogue_delay (trial, slot) 7486 rtx trial; 7487 int slot ATTRIBUTE_UNUSED; 7488{ 7489 rtx pat = PATTERN (trial); 7490 7491 if (get_attr_length (trial) != 1) 7492 return 0; 7493 7494 if (! reg_mentioned_p (stack_pointer_rtx, pat) 7495 && ! reg_mentioned_p (frame_pointer_rtx, pat)) 7496 return 1; 7497 7498 return 0; 7499} 7500 7501/* Adjust the cost of a scheduling dependency. Return the new cost of 7502 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ 7503 7504static int 7505supersparc_adjust_cost (insn, link, dep_insn, cost) 7506 rtx insn; 7507 rtx link; 7508 rtx dep_insn; 7509 int cost; 7510{ 7511 enum attr_type insn_type; 7512 7513 if (! recog_memoized (insn)) 7514 return 0; 7515 7516 insn_type = get_attr_type (insn); 7517 7518 if (REG_NOTE_KIND (link) == 0) 7519 { 7520 /* Data dependency; DEP_INSN writes a register that INSN reads some 7521 cycles later. */ 7522 7523 /* if a load, then the dependence must be on the memory address; 7524 add an extra "cycle". Note that the cost could be two cycles 7525 if the reg was written late in an instruction group; we ca not tell 7526 here. */ 7527 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) 7528 return cost + 3; 7529 7530 /* Get the delay only if the address of the store is the dependence. */ 7531 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) 7532 { 7533 rtx pat = PATTERN(insn); 7534 rtx dep_pat = PATTERN (dep_insn); 7535 7536 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 7537 return cost; /* This should not happen! */ 7538 7539 /* The dependency between the two instructions was on the data that 7540 is being stored. Assume that this implies that the address of the 7541 store is not dependent. */ 7542 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 7543 return cost; 7544 7545 return cost + 3; /* An approximation. */ 7546 } 7547 7548 /* A shift instruction cannot receive its data from an instruction 7549 in the same cycle; add a one cycle penalty. */ 7550 if (insn_type == TYPE_SHIFT) 7551 return cost + 3; /* Split before cascade into shift. */ 7552 } 7553 else 7554 { 7555 /* Anti- or output- dependency; DEP_INSN reads/writes a register that 7556 INSN writes some cycles later. */ 7557 7558 /* These are only significant for the fpu unit; writing a fp reg before 7559 the fpu has finished with it stalls the processor. */ 7560 7561 /* Reusing an integer register causes no problems. */ 7562 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 7563 return 0; 7564 } 7565 7566 return cost; 7567} 7568 7569static int 7570hypersparc_adjust_cost (insn, link, dep_insn, cost) 7571 rtx insn; 7572 rtx link; 7573 rtx dep_insn; 7574 int cost; 7575{ 7576 enum attr_type insn_type, dep_type; 7577 rtx pat = PATTERN(insn); 7578 rtx dep_pat = PATTERN (dep_insn); 7579 7580 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) 7581 return cost; 7582 7583 insn_type = get_attr_type (insn); 7584 dep_type = get_attr_type (dep_insn); 7585 7586 switch (REG_NOTE_KIND (link)) 7587 { 7588 case 0: 7589 /* Data dependency; DEP_INSN writes a register that INSN reads some 7590 cycles later. */ 7591 7592 switch (insn_type) 7593 { 7594 case TYPE_STORE: 7595 case TYPE_FPSTORE: 7596 /* Get the delay iff the address of the store is the dependence. */ 7597 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 7598 return cost; 7599 7600 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 7601 return cost; 7602 return cost + 3; 7603 7604 case TYPE_LOAD: 7605 case TYPE_SLOAD: 7606 case TYPE_FPLOAD: 7607 /* If a load, then the dependence must be on the memory address. If 7608 the addresses aren't equal, then it might be a false dependency */ 7609 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) 7610 { 7611 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET 7612 || GET_CODE (SET_DEST (dep_pat)) != MEM 7613 || GET_CODE (SET_SRC (pat)) != MEM 7614 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), 7615 XEXP (SET_SRC (pat), 0))) 7616 return cost + 2; 7617 7618 return cost + 8; 7619 } 7620 break; 7621 7622 case TYPE_BRANCH: 7623 /* Compare to branch latency is 0. There is no benefit from 7624 separating compare and branch. */ 7625 if (dep_type == TYPE_COMPARE) 7626 return 0; 7627 /* Floating point compare to branch latency is less than 7628 compare to conditional move. */ 7629 if (dep_type == TYPE_FPCMP) 7630 return cost - 1; 7631 break; 7632 default: 7633 break; 7634 } 7635 break; 7636 7637 case REG_DEP_ANTI: 7638 /* Anti-dependencies only penalize the fpu unit. */ 7639 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 7640 return 0; 7641 break; 7642 7643 default: 7644 break; 7645 } 7646 7647 return cost; 7648} 7649 7650static int 7651ultrasparc_adjust_cost (insn, link, dep_insn, cost) 7652 rtx insn; 7653 rtx link; 7654 rtx dep_insn; 7655 int cost; 7656{ 7657 enum attr_type insn_type, dep_type; 7658 rtx pat = PATTERN(insn); 7659 rtx dep_pat = PATTERN (dep_insn); 7660 7661 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) 7662 return cost; 7663 7664 insn_type = get_attr_type (insn); 7665 dep_type = get_attr_type (dep_insn); 7666 7667 /* Nothing issues in parallel with integer multiplies, so 7668 mark as zero cost since the scheduler can not do anything 7669 about it. */ 7670 if (insn_type == TYPE_IMUL || insn_type == TYPE_IDIV) 7671 return 0; 7672 7673#define SLOW_FP(dep_type) \ 7674(dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \ 7675 dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD) 7676 7677 switch (REG_NOTE_KIND (link)) 7678 { 7679 case 0: 7680 /* Data dependency; DEP_INSN writes a register that INSN reads some 7681 cycles later. */ 7682 7683 if (dep_type == TYPE_CMOVE) 7684 { 7685 /* Instructions that read the result of conditional moves cannot 7686 be in the same group or the following group. */ 7687 return cost + 1; 7688 } 7689 7690 switch (insn_type) 7691 { 7692 /* UltraSPARC can dual issue a store and an instruction setting 7693 the value stored, except for divide and square root. */ 7694 case TYPE_FPSTORE: 7695 if (! SLOW_FP (dep_type)) 7696 return 0; 7697 return cost; 7698 7699 case TYPE_STORE: 7700 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 7701 return cost; 7702 7703 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 7704 /* The dependency between the two instructions is on the data 7705 that is being stored. Assume that the address of the store 7706 is not also dependent. */ 7707 return 0; 7708 return cost; 7709 7710 case TYPE_LOAD: 7711 case TYPE_SLOAD: 7712 case TYPE_FPLOAD: 7713 /* A load does not return data until at least 11 cycles after 7714 a store to the same location. 3 cycles are accounted for 7715 in the load latency; add the other 8 here. */ 7716 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) 7717 { 7718 /* If the addresses are not equal this may be a false 7719 dependency because pointer aliasing could not be 7720 determined. Add only 2 cycles in that case. 2 is 7721 an arbitrary compromise between 8, which would cause 7722 the scheduler to generate worse code elsewhere to 7723 compensate for a dependency which might not really 7724 exist, and 0. */ 7725 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET 7726 || GET_CODE (SET_SRC (pat)) != MEM 7727 || GET_CODE (SET_DEST (dep_pat)) != MEM 7728 || ! rtx_equal_p (XEXP (SET_SRC (pat), 0), 7729 XEXP (SET_DEST (dep_pat), 0))) 7730 return cost + 2; 7731 7732 return cost + 8; 7733 } 7734 return cost; 7735 7736 case TYPE_BRANCH: 7737 /* Compare to branch latency is 0. There is no benefit from 7738 separating compare and branch. */ 7739 if (dep_type == TYPE_COMPARE) 7740 return 0; 7741 /* Floating point compare to branch latency is less than 7742 compare to conditional move. */ 7743 if (dep_type == TYPE_FPCMP) 7744 return cost - 1; 7745 return cost; 7746 7747 case TYPE_FPCMOVE: 7748 /* FMOVR class instructions can not issue in the same cycle 7749 or the cycle after an instruction which writes any 7750 integer register. Model this as cost 2 for dependent 7751 instructions. */ 7752 if (dep_type == TYPE_IALU 7753 && cost < 2) 7754 return 2; 7755 /* Otherwise check as for integer conditional moves. */ 7756 7757 case TYPE_CMOVE: 7758 /* Conditional moves involving integer registers wait until 7759 3 cycles after loads return data. The interlock applies 7760 to all loads, not just dependent loads, but that is hard 7761 to model. */ 7762 if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD) 7763 return cost + 3; 7764 return cost; 7765 7766 default: 7767 break; 7768 } 7769 break; 7770 7771 case REG_DEP_ANTI: 7772 /* Divide and square root lock destination registers for full latency. */ 7773 if (! SLOW_FP (dep_type)) 7774 return 0; 7775 break; 7776 7777 case REG_DEP_OUTPUT: 7778 /* IEU and FPU instruction that have the same destination 7779 register cannot be grouped together. */ 7780 return cost + 1; 7781 7782 default: 7783 break; 7784 } 7785 7786 /* Other costs not accounted for: 7787 - Single precision floating point loads lock the other half of 7788 the even/odd register pair. 7789 - Several hazards associated with ldd/std are ignored because these 7790 instructions are rarely generated for V9. 7791 - The floating point pipeline can not have both a single and double 7792 precision operation active at the same time. Format conversions 7793 and graphics instructions are given honorary double precision status. 7794 - call and jmpl are always the first instruction in a group. */ 7795 7796 return cost; 7797 7798#undef SLOW_FP 7799} 7800 7801static int 7802sparc_adjust_cost(insn, link, dep, cost) 7803 rtx insn; 7804 rtx link; 7805 rtx dep; 7806 int cost; 7807{ 7808 switch (sparc_cpu) 7809 { 7810 case PROCESSOR_SUPERSPARC: 7811 cost = supersparc_adjust_cost (insn, link, dep, cost); 7812 break; 7813 case PROCESSOR_HYPERSPARC: 7814 case PROCESSOR_SPARCLITE86X: 7815 cost = hypersparc_adjust_cost (insn, link, dep, cost); 7816 break; 7817 case PROCESSOR_ULTRASPARC: 7818 cost = ultrasparc_adjust_cost (insn, link, dep, cost); 7819 break; 7820 default: 7821 break; 7822 } 7823 return cost; 7824} 7825 7826/* This describes the state of the UltraSPARC pipeline during 7827 instruction scheduling. */ 7828 7829#define TMASK(__x) ((unsigned)1 << ((int)(__x))) 7830#define UMASK(__x) ((unsigned)1 << ((int)(__x))) 7831 7832enum ultra_code { NONE=0, /* no insn at all */ 7833 IEU0, /* shifts and conditional moves */ 7834 IEU1, /* condition code setting insns, calls+jumps */ 7835 IEUN, /* all other single cycle ieu insns */ 7836 LSU, /* loads and stores */ 7837 CTI, /* branches */ 7838 FPM, /* FPU pipeline 1, multiplies and divides */ 7839 FPA, /* FPU pipeline 2, all other operations */ 7840 SINGLE, /* single issue instructions */ 7841 NUM_ULTRA_CODES }; 7842 7843static enum ultra_code ultra_code_from_mask PARAMS ((int)); 7844static void ultra_schedule_insn PARAMS ((rtx *, rtx *, int, enum ultra_code)); 7845 7846static const char *const ultra_code_names[NUM_ULTRA_CODES] = { 7847 "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI", 7848 "FPM", "FPA", "SINGLE" }; 7849 7850struct ultrasparc_pipeline_state { 7851 /* The insns in this group. */ 7852 rtx group[4]; 7853 7854 /* The code for each insn. */ 7855 enum ultra_code codes[4]; 7856 7857 /* Which insns in this group have been committed by the 7858 scheduler. This is how we determine how many more 7859 can issue this cycle. */ 7860 char commit[4]; 7861 7862 /* How many insns in this group. */ 7863 char group_size; 7864 7865 /* Mask of free slots still in this group. */ 7866 char free_slot_mask; 7867 7868 /* The slotter uses the following to determine what other 7869 insn types can still make their way into this group. */ 7870 char contents [NUM_ULTRA_CODES]; 7871 char num_ieu_insns; 7872}; 7873 7874#define ULTRA_NUM_HIST 8 7875static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST]; 7876static int ultra_cur_hist; 7877static int ultra_cycles_elapsed; 7878 7879#define ultra_pipe (ultra_pipe_hist[ultra_cur_hist]) 7880 7881/* Given TYPE_MASK compute the ultra_code it has. */ 7882static enum ultra_code 7883ultra_code_from_mask (type_mask) 7884 int type_mask; 7885{ 7886 if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE))) 7887 return IEU0; 7888 else if (type_mask & (TMASK (TYPE_COMPARE) | 7889 TMASK (TYPE_CALL) | 7890 TMASK (TYPE_SIBCALL) | 7891 TMASK (TYPE_UNCOND_BRANCH))) 7892 return IEU1; 7893 else if (type_mask & TMASK (TYPE_IALU)) 7894 return IEUN; 7895 else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | 7896 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | 7897 TMASK (TYPE_FPSTORE))) 7898 return LSU; 7899 else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) | 7900 TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) | 7901 TMASK (TYPE_FPSQRTD))) 7902 return FPM; 7903 else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | 7904 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP))) 7905 return FPA; 7906 else if (type_mask & TMASK (TYPE_BRANCH)) 7907 return CTI; 7908 7909 return SINGLE; 7910} 7911 7912/* Check INSN (a conditional move) and make sure that it's 7913 results are available at this cycle. Return 1 if the 7914 results are in fact ready. */ 7915static int 7916ultra_cmove_results_ready_p (insn) 7917 rtx insn; 7918{ 7919 struct ultrasparc_pipeline_state *up; 7920 int entry, slot; 7921 7922 /* If this got dispatched in the previous 7923 group, the results are not ready. */ 7924 entry = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1); 7925 up = &ultra_pipe_hist[entry]; 7926 slot = 4; 7927 while (--slot >= 0) 7928 if (up->group[slot] == insn) 7929 return 0; 7930 7931 return 1; 7932} 7933 7934/* Walk backwards in pipeline history looking for FPU 7935 operations which use a mode different than FPMODE and 7936 will create a stall if an insn using FPMODE were to be 7937 dispatched this cycle. */ 7938static int 7939ultra_fpmode_conflict_exists (fpmode) 7940 enum machine_mode fpmode; 7941{ 7942 int hist_ent; 7943 int hist_lim; 7944 7945 hist_ent = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1); 7946 if (ultra_cycles_elapsed < 4) 7947 hist_lim = ultra_cycles_elapsed; 7948 else 7949 hist_lim = 4; 7950 while (hist_lim > 0) 7951 { 7952 struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent]; 7953 int slot = 4; 7954 7955 while (--slot >= 0) 7956 { 7957 rtx insn = up->group[slot]; 7958 enum machine_mode this_mode; 7959 rtx pat; 7960 7961 if (! insn 7962 || GET_CODE (insn) != INSN 7963 || (pat = PATTERN (insn)) == 0 7964 || GET_CODE (pat) != SET) 7965 continue; 7966 7967 this_mode = GET_MODE (SET_DEST (pat)); 7968 if ((this_mode != SFmode 7969 && this_mode != DFmode) 7970 || this_mode == fpmode) 7971 continue; 7972 7973 /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then 7974 we will get a stall. Loads and stores are independent 7975 of these rules. */ 7976 if (GET_CODE (SET_SRC (pat)) != ABS 7977 && GET_CODE (SET_SRC (pat)) != NEG 7978 && ((TMASK (get_attr_type (insn)) & 7979 (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | 7980 TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) | 7981 TMASK (TYPE_FPSQRTD) | 7982 TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0)) 7983 return 1; 7984 } 7985 hist_lim--; 7986 hist_ent = (hist_ent - 1) & (ULTRA_NUM_HIST - 1); 7987 } 7988 7989 /* No conflicts, safe to dispatch. */ 7990 return 0; 7991} 7992 7993/* Find an instruction in LIST which has one of the 7994 type attributes enumerated in TYPE_MASK. START 7995 says where to begin the search. 7996 7997 NOTE: This scheme depends upon the fact that we 7998 have less than 32 distinct type attributes. */ 7999 8000static int ultra_types_avail; 8001 8002static rtx * 8003ultra_find_type (type_mask, list, start) 8004 int type_mask; 8005 rtx *list; 8006 int start; 8007{ 8008 int i; 8009 8010 /* Short circuit if no such insn exists in the ready 8011 at the moment. */ 8012 if ((type_mask & ultra_types_avail) == 0) 8013 return 0; 8014 8015 for (i = start; i >= 0; i--) 8016 { 8017 rtx insn = list[i]; 8018 8019 if (recog_memoized (insn) >= 0 8020 && (TMASK(get_attr_type (insn)) & type_mask)) 8021 { 8022 enum machine_mode fpmode = SFmode; 8023 rtx pat = 0; 8024 int slot; 8025 int check_depend = 0; 8026 int check_fpmode_conflict = 0; 8027 8028 if (GET_CODE (insn) == INSN 8029 && (pat = PATTERN(insn)) != 0 8030 && GET_CODE (pat) == SET 8031 && !(type_mask & (TMASK (TYPE_STORE) | 8032 TMASK (TYPE_FPSTORE)))) 8033 { 8034 check_depend = 1; 8035 if (GET_MODE (SET_DEST (pat)) == SFmode 8036 || GET_MODE (SET_DEST (pat)) == DFmode) 8037 { 8038 fpmode = GET_MODE (SET_DEST (pat)); 8039 check_fpmode_conflict = 1; 8040 } 8041 } 8042 8043 slot = 4; 8044 while(--slot >= 0) 8045 { 8046 rtx slot_insn = ultra_pipe.group[slot]; 8047 rtx slot_pat; 8048 8049 /* Already issued, bad dependency, or FPU 8050 mode conflict. */ 8051 if (slot_insn != 0 8052 && (slot_pat = PATTERN (slot_insn)) != 0 8053 && ((insn == slot_insn) 8054 || (check_depend == 1 8055 && GET_CODE (slot_insn) == INSN 8056 && GET_CODE (slot_pat) == SET 8057 && ((GET_CODE (SET_DEST (slot_pat)) == REG 8058 && GET_CODE (SET_SRC (pat)) == REG 8059 && REGNO (SET_DEST (slot_pat)) == 8060 REGNO (SET_SRC (pat))) 8061 || (GET_CODE (SET_DEST (slot_pat)) == SUBREG 8062 && GET_CODE (SET_SRC (pat)) == SUBREG 8063 && REGNO (SUBREG_REG (SET_DEST (slot_pat))) == 8064 REGNO (SUBREG_REG (SET_SRC (pat))) 8065 && SUBREG_BYTE (SET_DEST (slot_pat)) == 8066 SUBREG_BYTE (SET_SRC (pat))))) 8067 || (check_fpmode_conflict == 1 8068 && GET_CODE (slot_insn) == INSN 8069 && GET_CODE (slot_pat) == SET 8070 && (GET_MODE (SET_DEST (slot_pat)) == SFmode 8071 || GET_MODE (SET_DEST (slot_pat)) == DFmode) 8072 && GET_MODE (SET_DEST (slot_pat)) != fpmode))) 8073 goto next; 8074 } 8075 8076 /* Check for peculiar result availability and dispatch 8077 interference situations. */ 8078 if (pat != 0 8079 && ultra_cycles_elapsed > 0) 8080 { 8081 rtx link; 8082 8083 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) 8084 { 8085 rtx link_insn = XEXP (link, 0); 8086 if (GET_CODE (link_insn) == INSN 8087 && recog_memoized (link_insn) >= 0 8088 && (TMASK (get_attr_type (link_insn)) & 8089 (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE))) 8090 && ! ultra_cmove_results_ready_p (link_insn)) 8091 goto next; 8092 } 8093 8094 if (check_fpmode_conflict 8095 && ultra_fpmode_conflict_exists (fpmode)) 8096 goto next; 8097 } 8098 8099 return &list[i]; 8100 } 8101 next: 8102 ; 8103 } 8104 return 0; 8105} 8106 8107static void 8108ultra_build_types_avail (ready, n_ready) 8109 rtx *ready; 8110 int n_ready; 8111{ 8112 int i = n_ready - 1; 8113 8114 ultra_types_avail = 0; 8115 while(i >= 0) 8116 { 8117 rtx insn = ready[i]; 8118 8119 if (recog_memoized (insn) >= 0) 8120 ultra_types_avail |= TMASK (get_attr_type (insn)); 8121 8122 i -= 1; 8123 } 8124} 8125 8126/* Place insn pointed to my IP into the pipeline. 8127 Make element THIS of READY be that insn if it 8128 is not already. TYPE indicates the pipeline class 8129 this insn falls into. */ 8130static void 8131ultra_schedule_insn (ip, ready, this, type) 8132 rtx *ip; 8133 rtx *ready; 8134 int this; 8135 enum ultra_code type; 8136{ 8137 int pipe_slot; 8138 char mask = ultra_pipe.free_slot_mask; 8139 rtx temp; 8140 8141 /* Obtain free slot. */ 8142 for (pipe_slot = 0; pipe_slot < 4; pipe_slot++) 8143 if ((mask & (1 << pipe_slot)) != 0) 8144 break; 8145 if (pipe_slot == 4) 8146 abort (); 8147 8148 /* In it goes, and it hasn't been committed yet. */ 8149 ultra_pipe.group[pipe_slot] = *ip; 8150 ultra_pipe.codes[pipe_slot] = type; 8151 ultra_pipe.contents[type] = 1; 8152 if (UMASK (type) & 8153 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) 8154 ultra_pipe.num_ieu_insns += 1; 8155 8156 ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot)); 8157 ultra_pipe.group_size += 1; 8158 ultra_pipe.commit[pipe_slot] = 0; 8159 8160 /* Update ready list. */ 8161 temp = *ip; 8162 while (ip != &ready[this]) 8163 { 8164 ip[0] = ip[1]; 8165 ++ip; 8166 } 8167 *ip = temp; 8168} 8169 8170/* Advance to the next pipeline group. */ 8171static void 8172ultra_flush_pipeline () 8173{ 8174 ultra_cur_hist = (ultra_cur_hist + 1) & (ULTRA_NUM_HIST - 1); 8175 ultra_cycles_elapsed += 1; 8176 memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe); 8177 ultra_pipe.free_slot_mask = 0xf; 8178} 8179 8180/* Init our data structures for this current block. */ 8181static void 8182ultrasparc_sched_init () 8183{ 8184 memset ((char *) ultra_pipe_hist, 0, sizeof ultra_pipe_hist); 8185 ultra_cur_hist = 0; 8186 ultra_cycles_elapsed = 0; 8187 ultra_pipe.free_slot_mask = 0xf; 8188} 8189 8190static void 8191sparc_sched_init (dump, sched_verbose, max_ready) 8192 FILE *dump ATTRIBUTE_UNUSED; 8193 int sched_verbose ATTRIBUTE_UNUSED; 8194 int max_ready ATTRIBUTE_UNUSED; 8195{ 8196 if (sparc_cpu == PROCESSOR_ULTRASPARC) 8197 ultrasparc_sched_init (); 8198} 8199 8200/* INSN has been scheduled, update pipeline commit state 8201 and return how many instructions are still to be 8202 scheduled in this group. */ 8203static int 8204ultrasparc_variable_issue (insn) 8205 rtx insn; 8206{ 8207 struct ultrasparc_pipeline_state *up = &ultra_pipe; 8208 int i, left_to_fire; 8209 8210 left_to_fire = 0; 8211 for (i = 0; i < 4; i++) 8212 { 8213 if (up->group[i] == 0) 8214 continue; 8215 8216 if (up->group[i] == insn) 8217 { 8218 up->commit[i] = 1; 8219 } 8220 else if (! up->commit[i]) 8221 left_to_fire++; 8222 } 8223 8224 return left_to_fire; 8225} 8226 8227static int 8228sparc_variable_issue (dump, sched_verbose, insn, cim) 8229 FILE *dump ATTRIBUTE_UNUSED; 8230 int sched_verbose ATTRIBUTE_UNUSED; 8231 rtx insn; 8232 int cim; 8233{ 8234 if (sparc_cpu == PROCESSOR_ULTRASPARC) 8235 return ultrasparc_variable_issue (insn); 8236 else 8237 return cim - 1; 8238} 8239 8240/* In actual_hazard_this_instance, we may have yanked some 8241 instructions from the ready list due to conflict cost 8242 adjustments. If so, and such an insn was in our pipeline 8243 group, remove it and update state. */ 8244static void 8245ultra_rescan_pipeline_state (ready, n_ready) 8246 rtx *ready; 8247 int n_ready; 8248{ 8249 struct ultrasparc_pipeline_state *up = &ultra_pipe; 8250 int i; 8251 8252 for (i = 0; i < 4; i++) 8253 { 8254 rtx insn = up->group[i]; 8255 int j; 8256 8257 if (! insn) 8258 continue; 8259 8260 /* If it has been committed, then it was removed from 8261 the ready list because it was actually scheduled, 8262 and that is not the case we are searching for here. */ 8263 if (up->commit[i] != 0) 8264 continue; 8265 8266 for (j = n_ready - 1; j >= 0; j--) 8267 if (ready[j] == insn) 8268 break; 8269 8270 /* If we didn't find it, toss it. */ 8271 if (j < 0) 8272 { 8273 enum ultra_code ucode = up->codes[i]; 8274 8275 up->group[i] = 0; 8276 up->codes[i] = NONE; 8277 up->contents[ucode] = 0; 8278 if (UMASK (ucode) & 8279 (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) 8280 up->num_ieu_insns -= 1; 8281 8282 up->free_slot_mask |= (1 << i); 8283 up->group_size -= 1; 8284 up->commit[i] = 0; 8285 } 8286 } 8287} 8288 8289static void 8290ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) 8291 FILE *dump; 8292 int sched_verbose; 8293 rtx *ready; 8294 int n_ready; 8295{ 8296 struct ultrasparc_pipeline_state *up = &ultra_pipe; 8297 int i, this_insn; 8298 8299 if (sched_verbose) 8300 { 8301 int n; 8302 8303 fprintf (dump, "\n;;\tUltraSPARC Looking at ["); 8304 for (n = n_ready - 1; n >= 0; n--) 8305 { 8306 rtx insn = ready[n]; 8307 enum ultra_code ucode; 8308 8309 if (recog_memoized (insn) < 0) 8310 continue; 8311 ucode = ultra_code_from_mask (TMASK (get_attr_type (insn))); 8312 if (n != 0) 8313 fprintf (dump, "%s(%d) ", 8314 ultra_code_names[ucode], 8315 INSN_UID (insn)); 8316 else 8317 fprintf (dump, "%s(%d)", 8318 ultra_code_names[ucode], 8319 INSN_UID (insn)); 8320 } 8321 fprintf (dump, "]\n"); 8322 } 8323 8324 this_insn = n_ready - 1; 8325 8326 /* Skip over junk we don't understand. */ 8327 while ((this_insn >= 0) 8328 && recog_memoized (ready[this_insn]) < 0) 8329 this_insn--; 8330 8331 ultra_build_types_avail (ready, this_insn + 1); 8332 8333 while (this_insn >= 0) { 8334 int old_group_size = up->group_size; 8335 8336 if (up->group_size != 0) 8337 { 8338 int num_committed; 8339 8340 num_committed = (up->commit[0] + up->commit[1] + 8341 up->commit[2] + up->commit[3]); 8342 /* If nothing has been commited from our group, or all of 8343 them have. Clear out the (current cycle's) pipeline 8344 state and start afresh. */ 8345 if (num_committed == 0 8346 || num_committed == up->group_size) 8347 { 8348 ultra_flush_pipeline (); 8349 up = &ultra_pipe; 8350 old_group_size = 0; 8351 } 8352 else 8353 { 8354 /* OK, some ready list insns got requeued and thus removed 8355 from the ready list. Account for this fact. */ 8356 ultra_rescan_pipeline_state (ready, n_ready); 8357 8358 /* Something "changed", make this look like a newly 8359 formed group so the code at the end of the loop 8360 knows that progress was in fact made. */ 8361 if (up->group_size != old_group_size) 8362 old_group_size = 0; 8363 } 8364 } 8365 8366 if (up->group_size == 0) 8367 { 8368 /* If the pipeline is (still) empty and we have any single 8369 group insns, get them out now as this is a good time. */ 8370 rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_IDIV) | 8371 TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) | 8372 TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)), 8373 ready, this_insn); 8374 if (ip) 8375 { 8376 ultra_schedule_insn (ip, ready, this_insn, SINGLE); 8377 break; 8378 } 8379 8380 /* If we are not in the process of emptying out the pipe, try to 8381 obtain an instruction which must be the first in it's group. */ 8382 ip = ultra_find_type ((TMASK (TYPE_CALL) | 8383 TMASK (TYPE_SIBCALL) | 8384 TMASK (TYPE_CALL_NO_DELAY_SLOT) | 8385 TMASK (TYPE_UNCOND_BRANCH)), 8386 ready, this_insn); 8387 if (ip) 8388 { 8389 ultra_schedule_insn (ip, ready, this_insn, IEU1); 8390 this_insn--; 8391 } 8392 else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) | 8393 TMASK (TYPE_FPDIVD) | 8394 TMASK (TYPE_FPSQRTS) | 8395 TMASK (TYPE_FPSQRTD)), 8396 ready, this_insn)) != 0) 8397 { 8398 ultra_schedule_insn (ip, ready, this_insn, FPM); 8399 this_insn--; 8400 } 8401 } 8402 8403 /* Try to fill the integer pipeline. First, look for an IEU0 specific 8404 operation. We can't do more IEU operations if the first 3 slots are 8405 all full or we have dispatched two IEU insns already. */ 8406 if ((up->free_slot_mask & 0x7) != 0 8407 && up->num_ieu_insns < 2 8408 && up->contents[IEU0] == 0 8409 && up->contents[IEUN] == 0) 8410 { 8411 rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn); 8412 if (ip) 8413 { 8414 ultra_schedule_insn (ip, ready, this_insn, IEU0); 8415 this_insn--; 8416 } 8417 } 8418 8419 /* If we can, try to find an IEU1 specific or an unnamed 8420 IEU instruction. */ 8421 if ((up->free_slot_mask & 0x7) != 0 8422 && up->num_ieu_insns < 2) 8423 { 8424 rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | 8425 (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)), 8426 ready, this_insn); 8427 if (ip) 8428 { 8429 rtx insn = *ip; 8430 8431 ultra_schedule_insn (ip, ready, this_insn, 8432 (!up->contents[IEU1] 8433 && get_attr_type (insn) == TYPE_COMPARE) 8434 ? IEU1 : IEUN); 8435 this_insn--; 8436 } 8437 } 8438 8439 /* If only one IEU insn has been found, try to find another unnamed 8440 IEU operation or an IEU1 specific one. */ 8441 if ((up->free_slot_mask & 0x7) != 0 8442 && up->num_ieu_insns < 2) 8443 { 8444 rtx *ip; 8445 int tmask = TMASK (TYPE_IALU); 8446 8447 if (!up->contents[IEU1]) 8448 tmask |= TMASK (TYPE_COMPARE); 8449 ip = ultra_find_type (tmask, ready, this_insn); 8450 if (ip) 8451 { 8452 rtx insn = *ip; 8453 8454 ultra_schedule_insn (ip, ready, this_insn, 8455 (!up->contents[IEU1] 8456 && get_attr_type (insn) == TYPE_COMPARE) 8457 ? IEU1 : IEUN); 8458 this_insn--; 8459 } 8460 } 8461 8462 /* Try for a load or store, but such an insn can only be issued 8463 if it is within' one of the first 3 slots. */ 8464 if ((up->free_slot_mask & 0x7) != 0 8465 && up->contents[LSU] == 0) 8466 { 8467 rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | 8468 TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | 8469 TMASK (TYPE_FPSTORE)), ready, this_insn); 8470 if (ip) 8471 { 8472 ultra_schedule_insn (ip, ready, this_insn, LSU); 8473 this_insn--; 8474 } 8475 } 8476 8477 /* Now find FPU operations, first FPM class. But not divisions or 8478 square-roots because those will break the group up. Unlike all 8479 the previous types, these can go in any slot. */ 8480 if (up->free_slot_mask != 0 8481 && up->contents[FPM] == 0) 8482 { 8483 rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn); 8484 if (ip) 8485 { 8486 ultra_schedule_insn (ip, ready, this_insn, FPM); 8487 this_insn--; 8488 } 8489 } 8490 8491 /* Continue on with FPA class if we have not filled the group already. */ 8492 if (up->free_slot_mask != 0 8493 && up->contents[FPA] == 0) 8494 { 8495 rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | 8496 TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)), 8497 ready, this_insn); 8498 if (ip) 8499 { 8500 ultra_schedule_insn (ip, ready, this_insn, FPA); 8501 this_insn--; 8502 } 8503 } 8504 8505 /* Finally, maybe stick a branch in here. */ 8506 if (up->free_slot_mask != 0 8507 && up->contents[CTI] == 0) 8508 { 8509 rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn); 8510 8511 /* Try to slip in a branch only if it is one of the 8512 next 2 in the ready list. */ 8513 if (ip && ((&ready[this_insn] - ip) < 2)) 8514 { 8515 ultra_schedule_insn (ip, ready, this_insn, CTI); 8516 this_insn--; 8517 } 8518 } 8519 8520 up->group_size = 0; 8521 for (i = 0; i < 4; i++) 8522 if ((up->free_slot_mask & (1 << i)) == 0) 8523 up->group_size++; 8524 8525 /* See if we made any progress... */ 8526 if (old_group_size != up->group_size) 8527 break; 8528 8529 /* Clean out the (current cycle's) pipeline state 8530 and try once more. If we placed no instructions 8531 into the pipeline at all, it means a real hard 8532 conflict exists with some earlier issued instruction 8533 so we must advance to the next cycle to clear it up. */ 8534 if (up->group_size == 0) 8535 { 8536 ultra_flush_pipeline (); 8537 up = &ultra_pipe; 8538 } 8539 else 8540 { 8541 memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe); 8542 ultra_pipe.free_slot_mask = 0xf; 8543 } 8544 } 8545 8546 if (sched_verbose) 8547 { 8548 int n, gsize; 8549 8550 fprintf (dump, ";;\tUltraSPARC Launched ["); 8551 gsize = up->group_size; 8552 for (n = 0; n < 4; n++) 8553 { 8554 rtx insn = up->group[n]; 8555 8556 if (! insn) 8557 continue; 8558 8559 gsize -= 1; 8560 if (gsize != 0) 8561 fprintf (dump, "%s(%d) ", 8562 ultra_code_names[up->codes[n]], 8563 INSN_UID (insn)); 8564 else 8565 fprintf (dump, "%s(%d)", 8566 ultra_code_names[up->codes[n]], 8567 INSN_UID (insn)); 8568 } 8569 fprintf (dump, "]\n"); 8570 } 8571} 8572 8573static int 8574sparc_sched_reorder (dump, sched_verbose, ready, n_readyp, clock) 8575 FILE *dump; 8576 int sched_verbose; 8577 rtx *ready; 8578 int *n_readyp; 8579 int clock ATTRIBUTE_UNUSED; 8580{ 8581 if (sparc_cpu == PROCESSOR_ULTRASPARC) 8582 ultrasparc_sched_reorder (dump, sched_verbose, ready, *n_readyp); 8583 return sparc_issue_rate (); 8584} 8585 8586static int 8587sparc_issue_rate () 8588{ 8589 switch (sparc_cpu) 8590 { 8591 default: 8592 return 1; 8593 case PROCESSOR_V9: 8594 /* Assume V9 processors are capable of at least dual-issue. */ 8595 return 2; 8596 case PROCESSOR_SUPERSPARC: 8597 return 3; 8598 case PROCESSOR_HYPERSPARC: 8599 case PROCESSOR_SPARCLITE86X: 8600 return 2; 8601 case PROCESSOR_ULTRASPARC: 8602 return 4; 8603 } 8604} 8605 8606static int 8607set_extends (insn) 8608 rtx insn; 8609{ 8610 register rtx pat = PATTERN (insn); 8611 8612 switch (GET_CODE (SET_SRC (pat))) 8613 { 8614 /* Load and some shift instructions zero extend. */ 8615 case MEM: 8616 case ZERO_EXTEND: 8617 /* sethi clears the high bits */ 8618 case HIGH: 8619 /* LO_SUM is used with sethi. sethi cleared the high 8620 bits and the values used with lo_sum are positive */ 8621 case LO_SUM: 8622 /* Store flag stores 0 or 1 */ 8623 case LT: case LTU: 8624 case GT: case GTU: 8625 case LE: case LEU: 8626 case GE: case GEU: 8627 case EQ: 8628 case NE: 8629 return 1; 8630 case AND: 8631 { 8632 rtx op0 = XEXP (SET_SRC (pat), 0); 8633 rtx op1 = XEXP (SET_SRC (pat), 1); 8634 if (GET_CODE (op1) == CONST_INT) 8635 return INTVAL (op1) >= 0; 8636 if (GET_CODE (op0) != REG) 8637 return 0; 8638 if (sparc_check_64 (op0, insn) == 1) 8639 return 1; 8640 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 8641 } 8642 case IOR: 8643 case XOR: 8644 { 8645 rtx op0 = XEXP (SET_SRC (pat), 0); 8646 rtx op1 = XEXP (SET_SRC (pat), 1); 8647 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) 8648 return 0; 8649 if (GET_CODE (op1) == CONST_INT) 8650 return INTVAL (op1) >= 0; 8651 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 8652 } 8653 case ASHIFT: 8654 case LSHIFTRT: 8655 return GET_MODE (SET_SRC (pat)) == SImode; 8656 /* Positive integers leave the high bits zero. */ 8657 case CONST_DOUBLE: 8658 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); 8659 case CONST_INT: 8660 return ! (INTVAL (SET_SRC (pat)) & 0x80000000); 8661 case ASHIFTRT: 8662 case SIGN_EXTEND: 8663 return - (GET_MODE (SET_SRC (pat)) == SImode); 8664 case REG: 8665 return sparc_check_64 (SET_SRC (pat), insn); 8666 default: 8667 return 0; 8668 } 8669} 8670 8671/* We _ought_ to have only one kind per function, but... */ 8672static rtx sparc_addr_diff_list; 8673static rtx sparc_addr_list; 8674 8675void 8676sparc_defer_case_vector (lab, vec, diff) 8677 rtx lab, vec; 8678 int diff; 8679{ 8680 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); 8681 if (diff) 8682 sparc_addr_diff_list 8683 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); 8684 else 8685 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); 8686} 8687 8688static void 8689sparc_output_addr_vec (vec) 8690 rtx vec; 8691{ 8692 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 8693 int idx, vlen = XVECLEN (body, 0); 8694 8695#ifdef ASM_OUTPUT_ADDR_VEC_START 8696 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 8697#endif 8698 8699#ifdef ASM_OUTPUT_CASE_LABEL 8700 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 8701 NEXT_INSN (lab)); 8702#else 8703 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 8704#endif 8705 8706 for (idx = 0; idx < vlen; idx++) 8707 { 8708 ASM_OUTPUT_ADDR_VEC_ELT 8709 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); 8710 } 8711 8712#ifdef ASM_OUTPUT_ADDR_VEC_END 8713 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 8714#endif 8715} 8716 8717static void 8718sparc_output_addr_diff_vec (vec) 8719 rtx vec; 8720{ 8721 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 8722 rtx base = XEXP (XEXP (body, 0), 0); 8723 int idx, vlen = XVECLEN (body, 1); 8724 8725#ifdef ASM_OUTPUT_ADDR_VEC_START 8726 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 8727#endif 8728 8729#ifdef ASM_OUTPUT_CASE_LABEL 8730 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 8731 NEXT_INSN (lab)); 8732#else 8733 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 8734#endif 8735 8736 for (idx = 0; idx < vlen; idx++) 8737 { 8738 ASM_OUTPUT_ADDR_DIFF_ELT 8739 (asm_out_file, 8740 body, 8741 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), 8742 CODE_LABEL_NUMBER (base)); 8743 } 8744 8745#ifdef ASM_OUTPUT_ADDR_VEC_END 8746 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 8747#endif 8748} 8749 8750static void 8751sparc_output_deferred_case_vectors () 8752{ 8753 rtx t; 8754 int align; 8755 8756 if (sparc_addr_list == NULL_RTX 8757 && sparc_addr_diff_list == NULL_RTX) 8758 return; 8759 8760 /* Align to cache line in the function's code section. */ 8761 function_section (current_function_decl); 8762 8763 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 8764 if (align > 0) 8765 ASM_OUTPUT_ALIGN (asm_out_file, align); 8766 8767 for (t = sparc_addr_list; t ; t = XEXP (t, 1)) 8768 sparc_output_addr_vec (XEXP (t, 0)); 8769 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) 8770 sparc_output_addr_diff_vec (XEXP (t, 0)); 8771 8772 sparc_addr_list = sparc_addr_diff_list = NULL_RTX; 8773} 8774 8775/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are 8776 unknown. Return 1 if the high bits are zero, -1 if the register is 8777 sign extended. */ 8778int 8779sparc_check_64 (x, insn) 8780 rtx x, insn; 8781{ 8782 /* If a register is set only once it is safe to ignore insns this 8783 code does not know how to handle. The loop will either recognize 8784 the single set and return the correct value or fail to recognize 8785 it and return 0. */ 8786 int set_once = 0; 8787 rtx y = x; 8788 8789 if (GET_CODE (x) != REG) 8790 abort (); 8791 8792 if (GET_MODE (x) == DImode) 8793 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); 8794 8795 if (flag_expensive_optimizations 8796 && REG_N_SETS (REGNO (y)) == 1) 8797 set_once = 1; 8798 8799 if (insn == 0) 8800 { 8801 if (set_once) 8802 insn = get_last_insn_anywhere (); 8803 else 8804 return 0; 8805 } 8806 8807 while ((insn = PREV_INSN (insn))) 8808 { 8809 switch (GET_CODE (insn)) 8810 { 8811 case JUMP_INSN: 8812 case NOTE: 8813 break; 8814 case CODE_LABEL: 8815 case CALL_INSN: 8816 default: 8817 if (! set_once) 8818 return 0; 8819 break; 8820 case INSN: 8821 { 8822 rtx pat = PATTERN (insn); 8823 if (GET_CODE (pat) != SET) 8824 return 0; 8825 if (rtx_equal_p (x, SET_DEST (pat))) 8826 return set_extends (insn); 8827 if (y && rtx_equal_p (y, SET_DEST (pat))) 8828 return set_extends (insn); 8829 if (reg_overlap_mentioned_p (SET_DEST (pat), y)) 8830 return 0; 8831 } 8832 } 8833 } 8834 return 0; 8835} 8836 8837char * 8838sparc_v8plus_shift (operands, insn, opcode) 8839 rtx *operands; 8840 rtx insn; 8841 const char *opcode; 8842{ 8843 static char asm_code[60]; 8844 8845 if (GET_CODE (operands[3]) == SCRATCH) 8846 operands[3] = operands[0]; 8847 if (GET_CODE (operands[1]) == CONST_INT) 8848 { 8849 output_asm_insn ("mov\t%1, %3", operands); 8850 } 8851 else 8852 { 8853 output_asm_insn ("sllx\t%H1, 32, %3", operands); 8854 if (sparc_check_64 (operands[1], insn) <= 0) 8855 output_asm_insn ("srl\t%L1, 0, %L1", operands); 8856 output_asm_insn ("or\t%L1, %3, %3", operands); 8857 } 8858 8859 strcpy(asm_code, opcode); 8860 if (which_alternative != 2) 8861 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); 8862 else 8863 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); 8864} 8865 8866/* Output rtl to increment the profiler label LABELNO 8867 for profiling a function entry. */ 8868 8869void 8870sparc_profile_hook (labelno) 8871 int labelno; 8872{ 8873 char buf[32]; 8874 rtx lab, fun; 8875 8876 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 8877 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 8878 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); 8879 8880 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); 8881} 8882 8883/* Mark ARG, which is really a struct ultrasparc_pipline_state *, for 8884 GC. */ 8885 8886static void 8887mark_ultrasparc_pipeline_state (arg) 8888 void *arg; 8889{ 8890 struct ultrasparc_pipeline_state *ups; 8891 size_t i; 8892 8893 ups = (struct ultrasparc_pipeline_state *) arg; 8894 for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i) 8895 ggc_mark_rtx (ups->group[i]); 8896} 8897 8898/* Called to register all of our global variables with the garbage 8899 collector. */ 8900 8901static void 8902sparc_add_gc_roots () 8903{ 8904 ggc_add_rtx_root (&sparc_compare_op0, 1); 8905 ggc_add_rtx_root (&sparc_compare_op1, 1); 8906 ggc_add_rtx_root (&global_offset_table, 1); 8907 ggc_add_rtx_root (&get_pc_symbol, 1); 8908 ggc_add_rtx_root (&sparc_addr_diff_list, 1); 8909 ggc_add_rtx_root (&sparc_addr_list, 1); 8910 ggc_add_root (ultra_pipe_hist, ARRAY_SIZE (ultra_pipe_hist), 8911 sizeof (ultra_pipe_hist[0]), &mark_ultrasparc_pipeline_state); 8912} 8913 8914#ifdef OBJECT_FORMAT_ELF 8915static void 8916sparc_elf_asm_named_section (name, flags) 8917 const char *name; 8918 unsigned int flags; 8919{ 8920 if (flags & SECTION_MERGE) 8921 { 8922 /* entsize cannot be expressed in this section attributes 8923 encoding style. */ 8924 default_elf_asm_named_section (name, flags); 8925 return; 8926 } 8927 8928 fprintf (asm_out_file, "\t.section\t\"%s\"", name); 8929 8930 if (!(flags & SECTION_DEBUG)) 8931 fputs (",#alloc", asm_out_file); 8932 if (flags & SECTION_WRITE) 8933 fputs (",#write", asm_out_file); 8934 if (flags & SECTION_CODE) 8935 fputs (",#execinstr", asm_out_file); 8936 8937 /* ??? Handle SECTION_BSS. */ 8938 8939 fputc ('\n', asm_out_file); 8940} 8941#endif /* OBJECT_FORMAT_ELF */ 8942 8943int 8944sparc_extra_constraint_check (op, c, strict) 8945 rtx op; 8946 int c; 8947 int strict; 8948{ 8949 int reload_ok_mem; 8950 8951 if (TARGET_ARCH64 8952 && (c == 'T' || c == 'U')) 8953 return 0; 8954 8955 switch (c) 8956 { 8957 case 'Q': 8958 return fp_sethi_p (op); 8959 8960 case 'R': 8961 return fp_mov_p (op); 8962 8963 case 'S': 8964 return fp_high_losum_p (op); 8965 8966 case 'U': 8967 if (! strict 8968 || (GET_CODE (op) == REG 8969 && (REGNO (op) < FIRST_PSEUDO_REGISTER 8970 || reg_renumber[REGNO (op)] >= 0))) 8971 return register_ok_for_ldd (op); 8972 8973 return 0; 8974 8975 case 'W': 8976 case 'T': 8977 break; 8978 8979 default: 8980 return 0; 8981 } 8982 8983 /* Our memory extra constraints have to emulate the 8984 behavior of 'm' and 'o' in order for reload to work 8985 correctly. */ 8986 if (GET_CODE (op) == MEM) 8987 { 8988 reload_ok_mem = 0; 8989 if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) 8990 && (! strict 8991 || strict_memory_address_p (Pmode, XEXP (op, 0)))) 8992 reload_ok_mem = 1; 8993 } 8994 else 8995 { 8996 reload_ok_mem = (reload_in_progress 8997 && GET_CODE (op) == REG 8998 && REGNO (op) >= FIRST_PSEUDO_REGISTER 8999 && reg_renumber [REGNO (op)] < 0); 9000 } 9001 9002 return reload_ok_mem; 9003} 9004 9005/* Output code to add DELTA to the first argument, and then jump to FUNCTION. 9006 Used for C++ multiple inheritance. */ 9007 9008void 9009sparc_output_mi_thunk (file, thunk_fndecl, delta, function) 9010 FILE *file; 9011 tree thunk_fndecl ATTRIBUTE_UNUSED; 9012 HOST_WIDE_INT delta; 9013 tree function; 9014{ 9015 rtx this, insn, funexp, delta_rtx, tmp; 9016 9017 reload_completed = 1; 9018 no_new_pseudos = 1; 9019 current_function_uses_only_leaf_regs = 1; 9020 9021 emit_note (NULL, NOTE_INSN_PROLOGUE_END); 9022 9023 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function 9024 returns a structure, the structure return pointer is there instead. */ 9025 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)))) 9026 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1); 9027 else 9028 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST); 9029 9030 /* Add DELTA. When possible use a plain add, otherwise load it into 9031 a register first. */ 9032 delta_rtx = GEN_INT (delta); 9033 if (!SPARC_SIMM13_P (delta)) 9034 { 9035 rtx scratch = gen_rtx_REG (Pmode, 1); 9036 if (TARGET_ARCH64) 9037 sparc_emit_set_const64 (scratch, delta_rtx); 9038 else 9039 sparc_emit_set_const32 (scratch, delta_rtx); 9040 delta_rtx = scratch; 9041 } 9042 9043 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx); 9044 emit_insn (gen_rtx_SET (VOIDmode, this, tmp)); 9045 9046 /* Generate a tail call to the target function. */ 9047 if (! TREE_USED (function)) 9048 { 9049 assemble_external (function); 9050 TREE_USED (function) = 1; 9051 } 9052 funexp = XEXP (DECL_RTL (function), 0); 9053 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); 9054 insn = emit_call_insn (gen_sibcall (funexp)); 9055 SIBLING_CALL_P (insn) = 1; 9056 emit_barrier (); 9057 9058 /* Run just enough of rest_of_compilation to get the insns emitted. 9059 There's not really enough bulk here to make other passes such as 9060 instruction scheduling worth while. Note that use_thunk calls 9061 assemble_start_function and assemble_end_function. */ 9062 insn = get_insns (); 9063 shorten_branches (insn); 9064 final_start_function (insn, file, 1); 9065 final (insn, file, 1, 0); 9066 final_end_function (); 9067 9068 reload_completed = 0; 9069 no_new_pseudos = 0; 9070} 9071