spe.md revision 117395
1;; e500 SPE description 2;; Copyright (C) 2002 Free Software Foundation, Inc. 3;; Contributed by Aldy Hernandez (aldy@quesejoda.com) 4 5;; This file is part of GNU CC. 6 7;; GNU CC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 2, or (at your option) 10;; any later version. 11 12;; GNU CC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GNU CC; see the file COPYING. If not, write to 19;; the Free Software Foundation, 59 Temple Place - Suite 330, 20;; Boston, MA 02111-1307, USA. 21 22(define_constants 23 [(SPE_ACC_REGNO 111) 24 (SPEFSCR_REGNO 112)]) 25 26(define_insn "*negsf2_gpr" 27 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 28 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] 29 "TARGET_HARD_FLOAT && !TARGET_FPRS" 30 "efsneg %0,%1" 31 [(set_attr "type" "fp")]) 32 33(define_insn "*abssf2_gpr" 34 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 35 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] 36 "TARGET_HARD_FLOAT && !TARGET_FPRS" 37 "efsabs %0,%1" 38 [(set_attr "type" "fp")]) 39 40(define_insn "*addsf3_gpr" 41 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 42 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r") 43 (match_operand:SF 2 "gpc_reg_operand" "r")))] 44 "TARGET_HARD_FLOAT && !TARGET_FPRS" 45 "efsadd %0,%1,%2" 46 [(set_attr "type" "fp")]) 47 48(define_insn "*subsf3_gpr" 49 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 50 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r") 51 (match_operand:SF 2 "gpc_reg_operand" "r")))] 52 "TARGET_HARD_FLOAT && !TARGET_FPRS" 53 "efssub %0,%1,%2" 54 [(set_attr "type" "fp")]) 55 56(define_insn "*mulsf3_gpr" 57 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 58 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r") 59 (match_operand:SF 2 "gpc_reg_operand" "r")))] 60 "TARGET_HARD_FLOAT && !TARGET_FPRS" 61 "efsmul %0,%1,%2" 62 [(set_attr "type" "fp")]) 63 64(define_insn "*divsf3_gpr" 65 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 66 (div:SF (match_operand:SF 1 "gpc_reg_operand" "r") 67 (match_operand:SF 2 "gpc_reg_operand" "r")))] 68 "TARGET_HARD_FLOAT && !TARGET_FPRS" 69 "efsdiv %0,%1,%2" 70 [(set_attr "type" "fp")]) 71 72(define_insn "spe_efsctuiz" 73 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 74 (unspec:SI [(match_operand:SF 1 "gpc_reg_operand" "r")] 700))] 75 "TARGET_HARD_FLOAT && !TARGET_FPRS" 76 "efsctuiz %0,%1" 77 [(set_attr "type" "fp")]) 78 79(define_insn "spe_fixunssfsi2" 80 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 81 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))] 82 "TARGET_HARD_FLOAT && !TARGET_FPRS" 83 "efsctui %0,%1" 84 [(set_attr "type" "fp")]) 85 86(define_insn "spe_fix_truncsfsi2" 87 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 88 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] 89 "TARGET_HARD_FLOAT && !TARGET_FPRS" 90 "efsctsi %0,%1" 91 [(set_attr "type" "fp")]) 92 93(define_insn "spe_floatunssisf2" 94 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 95 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] 96 "TARGET_HARD_FLOAT && !TARGET_FPRS" 97 "efscfui %0,%1" 98 [(set_attr "type" "fp")]) 99 100(define_insn "spe_floatsisf2" 101 [(set (match_operand:SF 0 "gpc_reg_operand" "=r") 102 (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] 103 "TARGET_HARD_FLOAT && !TARGET_FPRS" 104 "efscfsi %0,%1" 105 [(set_attr "type" "fp")]) 106 107 108;; SPE SIMD instructions 109 110(define_insn "spe_evabs" 111 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 112 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] 113 "TARGET_SPE" 114 "evabs %0,%1" 115 [(set_attr "type" "vecsimple") 116 (set_attr "length" "4")]) 117 118(define_insn "spe_evandc" 119 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 120 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 121 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 122 "TARGET_SPE" 123 "evandc %0,%1,%2" 124 [(set_attr "type" "vecsimple") 125 (set_attr "length" "4")]) 126 127(define_insn "spe_evand" 128 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 129 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 130 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 131 "TARGET_SPE" 132 "evand %0,%1,%2" 133 [(set_attr "type" "vecsimple") 134 (set_attr "length" "4")]) 135 136;; Vector compare instructions 137 138(define_insn "spe_evcmpeq" 139 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 140 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 141 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))] 142 "TARGET_SPE" 143 "evcmpeq %0,%1,%2" 144 [(set_attr "type" "veccmp") 145 (set_attr "length" "4")]) 146 147(define_insn "spe_evcmpgts" 148 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 149 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 150 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))] 151 "TARGET_SPE" 152 "evcmpgts %0,%1,%2" 153 [(set_attr "type" "veccmp") 154 (set_attr "length" "4")]) 155 156(define_insn "spe_evcmpgtu" 157 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 158 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 159 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))] 160 "TARGET_SPE" 161 "evcmpgtu %0,%1,%2" 162 [(set_attr "type" "veccmp") 163 (set_attr "length" "4")]) 164 165(define_insn "spe_evcmplts" 166 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 167 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 168 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))] 169 "TARGET_SPE" 170 "evcmplts %0,%1,%2" 171 [(set_attr "type" "veccmp") 172 (set_attr "length" "4")]) 173 174(define_insn "spe_evcmpltu" 175 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 176 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") 177 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))] 178 "TARGET_SPE" 179 "evcmpltu %0,%1,%2" 180 [(set_attr "type" "veccmp") 181 (set_attr "length" "4")]) 182 183;; Floating point vector compare instructions 184 185(define_insn "spe_evfscmpeq" 186 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 187 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 188 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538)) 189 (clobber (reg:SI SPEFSCR_REGNO))] 190 "TARGET_SPE" 191 "evfscmpeq %0,%1,%2" 192 [(set_attr "type" "veccmp") 193 (set_attr "length" "4")]) 194 195(define_insn "spe_evfscmpgt" 196 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 197 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 198 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539)) 199 (clobber (reg:SI SPEFSCR_REGNO))] 200 "TARGET_SPE" 201 "evfscmpgt %0,%1,%2" 202 [(set_attr "type" "veccmp") 203 (set_attr "length" "4")]) 204 205(define_insn "spe_evfscmplt" 206 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 207 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 208 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540)) 209 (clobber (reg:SI SPEFSCR_REGNO))] 210 "TARGET_SPE" 211 "evfscmplt %0,%1,%2" 212 [(set_attr "type" "veccmp") 213 (set_attr "length" "4")]) 214 215(define_insn "spe_evfststeq" 216 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 217 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 218 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))] 219 "TARGET_SPE" 220 "evfststeq %0,%1,%2" 221 [(set_attr "type" "veccmp") 222 (set_attr "length" "4")]) 223 224(define_insn "spe_evfststgt" 225 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 226 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 227 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))] 228 "TARGET_SPE" 229 "evfststgt %0,%1,%2" 230 [(set_attr "type" "veccmp") 231 (set_attr "length" "4")]) 232 233(define_insn "spe_evfststlt" 234 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 235 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") 236 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))] 237 "TARGET_SPE" 238 "evfststlt %0,%1,%2" 239 [(set_attr "type" "veccmp") 240 (set_attr "length" "4")]) 241 242;; End of vector compare instructions 243 244(define_insn "spe_evcntlsw" 245 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 246 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))] 247 "TARGET_SPE" 248 "evcntlsw %0,%1" 249 [(set_attr "type" "vecsimple") 250 (set_attr "length" "4")]) 251 252(define_insn "spe_evcntlzw" 253 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 254 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))] 255 "TARGET_SPE" 256 "evcntlzw %0,%1" 257 [(set_attr "type" "vecsimple") 258 (set_attr "length" "4")]) 259 260(define_insn "spe_eveqv" 261 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 262 (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 263 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 264 "TARGET_SPE" 265 "eveqv %0,%1,%2" 266 [(set_attr "type" "vecsimple") 267 (set_attr "length" "4")]) 268 269(define_insn "spe_evextsb" 270 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 271 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))] 272 "TARGET_SPE" 273 "evextsb %0,%1" 274 [(set_attr "type" "vecsimple") 275 (set_attr "length" "4")]) 276 277(define_insn "spe_evextsh" 278 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 279 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))] 280 "TARGET_SPE" 281 "evextsh %0,%1" 282 [(set_attr "type" "vecsimple") 283 (set_attr "length" "4")]) 284 285(define_insn "spe_evlhhesplat" 286 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 287 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 288 (match_operand:QI 2 "immediate_operand" "i")))) 289 (unspec [(const_int 0)] 509)] 290 "TARGET_SPE" 291 "evlhhesplat %0,%1,%2" 292 [(set_attr "type" "vecload") 293 (set_attr "length" "4")]) 294 295(define_insn "spe_evlhhesplatx" 296 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 297 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 298 (match_operand:SI 2 "gpc_reg_operand" "r")))) 299 (unspec [(const_int 0)] 510)] 300 "TARGET_SPE" 301 "evlhhesplatx %0,%1,%2" 302 [(set_attr "type" "vecload") 303 (set_attr "length" "4")]) 304 305(define_insn "spe_evlhhossplat" 306 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 307 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 308 (match_operand:QI 2 "immediate_operand" "i")))) 309 (unspec [(const_int 0)] 511)] 310 "TARGET_SPE" 311 "evlhhossplat %0,%1,%2" 312 [(set_attr "type" "vecload") 313 (set_attr "length" "4")]) 314 315(define_insn "spe_evlhhossplatx" 316 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 317 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 318 (match_operand:SI 2 "gpc_reg_operand" "r")))) 319 (unspec [(const_int 0)] 512)] 320 "TARGET_SPE" 321 "evlhhossplatx %0,%1,%2" 322 [(set_attr "type" "vecload") 323 (set_attr "length" "4")]) 324 325(define_insn "spe_evlhhousplat" 326 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 327 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 328 (match_operand:QI 2 "immediate_operand" "i")))) 329 (unspec [(const_int 0)] 513)] 330 "TARGET_SPE" 331 "evlhhousplat %0,%1,%2" 332 [(set_attr "type" "vecload") 333 (set_attr "length" "4")]) 334 335(define_insn "spe_evlhhousplatx" 336 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 337 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 338 (match_operand:SI 2 "gpc_reg_operand" "r")))) 339 (unspec [(const_int 0)] 514)] 340 "TARGET_SPE" 341 "evlhhousplatx %0,%1,%2" 342 [(set_attr "type" "vecload") 343 (set_attr "length" "4")]) 344 345(define_insn "spe_evlwhsplat" 346 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 347 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 348 (match_operand:QI 2 "immediate_operand" "i")))) 349 (unspec [(const_int 0)] 515)] 350 "TARGET_SPE" 351 "evlwhsplat %0,%1,%2" 352 [(set_attr "type" "vecload") 353 (set_attr "length" "4")]) 354 355(define_insn "spe_evlwhsplatx" 356 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 357 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 358 (match_operand:SI 2 "gpc_reg_operand" "r")))) 359 (unspec [(const_int 0)] 516)] 360 "TARGET_SPE" 361 "evlwhsplatx %0,%1,%2" 362 [(set_attr "type" "vecload") 363 (set_attr "length" "4")]) 364 365(define_insn "spe_evlwwsplat" 366 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 367 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 368 (match_operand:QI 2 "immediate_operand" "i")))) 369 (unspec [(const_int 0)] 517)] 370 "TARGET_SPE" 371 "evlwwsplat %0,%1,%2" 372 [(set_attr "type" "vecload") 373 (set_attr "length" "4")]) 374 375(define_insn "spe_evlwwsplatx" 376 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 377 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 378 (match_operand:SI 2 "gpc_reg_operand" "r")))) 379 (unspec [(const_int 0)] 518)] 380 "TARGET_SPE" 381 "evlwwsplatx %0,%1,%2" 382 [(set_attr "type" "vecload") 383 (set_attr "length" "4")]) 384 385(define_insn "spe_evmergehi" 386 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 387 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 388 (vec_select:V2SI 389 (match_operand:V2SI 2 "gpc_reg_operand" "r") 390 (parallel [(const_int 1) 391 (const_int 0)])) 392 (const_int 2)))] 393 "TARGET_SPE" 394 "evmergehi %0,%1,%2" 395 [(set_attr "type" "vecsimple") 396 (set_attr "length" "4")]) 397 398(define_insn "spe_evmergehilo" 399 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 400 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 401 (match_operand:V2SI 2 "gpc_reg_operand" "r") 402 (const_int 2)))] 403 "TARGET_SPE" 404 "evmergehilo %0,%1,%2" 405 [(set_attr "type" "vecsimple") 406 (set_attr "length" "4")]) 407 408(define_insn "spe_evmergelo" 409 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 410 (vec_merge:V2SI (vec_select:V2SI 411 (match_operand:V2SI 1 "gpc_reg_operand" "r") 412 (parallel [(const_int 1) 413 (const_int 0)])) 414 (match_operand:V2SI 2 "gpc_reg_operand" "r") 415 (const_int 2)))] 416 "TARGET_SPE" 417 "evmergelo %0,%1,%2" 418 [(set_attr "type" "vecsimple") 419 (set_attr "length" "4")]) 420 421(define_insn "spe_evmergelohi" 422 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 423 (vec_merge:V2SI (vec_select:V2SI 424 (match_operand:V2SI 1 "gpc_reg_operand" "r") 425 (parallel [(const_int 1) 426 (const_int 0)])) 427 (vec_select:V2SI 428 (match_operand:V2SI 2 "gpc_reg_operand" "r") 429 (parallel [(const_int 1) 430 (const_int 0)])) 431 (const_int 2)))] 432 "TARGET_SPE" 433 "evmergelohi %0,%1,%2" 434 [(set_attr "type" "vecsimple") 435 (set_attr "length" "4")]) 436 437(define_insn "spe_evnand" 438 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 439 (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 440 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 441 "TARGET_SPE" 442 "evnand %0,%1,%2" 443 [(set_attr "type" "vecsimple") 444 (set_attr "length" "4")]) 445 446(define_insn "spe_evneg" 447 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 448 (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] 449 "TARGET_SPE" 450 "evneg %0,%1" 451 [(set_attr "type" "vecsimple") 452 (set_attr "length" "4")]) 453 454(define_insn "spe_evnor" 455 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 456 (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 457 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 458 "TARGET_SPE" 459 "evnor %0,%1,%2" 460 [(set_attr "type" "vecsimple") 461 (set_attr "length" "4")]) 462 463(define_insn "spe_evorc" 464 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 465 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 466 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] 467 "TARGET_SPE" 468 "evorc %0,%1,%2" 469 [(set_attr "type" "vecsimple") 470 (set_attr "length" "4")]) 471 472(define_insn "spe_evor" 473 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 474 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 475 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 476 "TARGET_SPE" 477 "evor %0,%1,%2" 478 [(set_attr "type" "vecsimple") 479 (set_attr "length" "4")]) 480 481(define_insn "spe_evrlwi" 482 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 483 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 484 (match_operand:QI 2 "immediate_operand" "i")] 519))] 485 "TARGET_SPE" 486 "evrlwi %0,%1,%2" 487 [(set_attr "type" "vecsimple") 488 (set_attr "length" "4")]) 489 490(define_insn "spe_evrlw" 491 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 492 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 493 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))] 494 "TARGET_SPE" 495 "evrlw %0,%1,%2" 496 [(set_attr "type" "veccomplex") 497 (set_attr "length" "4")]) 498 499(define_insn "spe_evrndw" 500 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 501 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))] 502 "TARGET_SPE" 503 "evrndw %0,%1" 504 [(set_attr "type" "vecsimple") 505 (set_attr "length" "4")]) 506 507(define_insn "spe_evsel" 508 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 509 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 510 (match_operand:V2SI 2 "gpc_reg_operand" "r") 511 (match_operand:CC 3 "cc_reg_operand" "y")] 522))] 512 "TARGET_SPE" 513 "evsel %0,%1,%2,%3" 514 [(set_attr "type" "veccmp") 515 (set_attr "length" "4")]) 516 517(define_insn "spe_evsel_fs" 518 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 519 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r") 520 (match_operand:V2SF 2 "gpc_reg_operand" "r") 521 (match_operand:CC 3 "cc_reg_operand" "y")] 725))] 522 "TARGET_SPE" 523 "evsel %0,%1,%2,%3" 524 [(set_attr "type" "veccmp") 525 (set_attr "length" "4")]) 526 527(define_insn "spe_evslwi" 528 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 529 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 530 (match_operand:QI 2 "immediate_operand" "i")] 531 523))] 532 "TARGET_SPE" 533 "evslwi %0,%1,%2" 534 [(set_attr "type" "vecsimple") 535 (set_attr "length" "4")]) 536 537(define_insn "spe_evslw" 538 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 539 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 540 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))] 541 "TARGET_SPE" 542 "evslw %0,%1,%2" 543 [(set_attr "type" "vecsimple") 544 (set_attr "length" "4")]) 545 546(define_insn "spe_evsrwis" 547 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 548 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 549 (match_operand:QI 2 "immediate_operand" "i")] 550 525))] 551 "TARGET_SPE" 552 "evsrwis %0,%1,%2" 553 [(set_attr "type" "vecsimple") 554 (set_attr "length" "4")]) 555 556(define_insn "spe_evsrwiu" 557 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 558 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 559 (match_operand:QI 2 "immediate_operand" "i")] 560 526))] 561 "TARGET_SPE" 562 "evsrwiu %0,%1,%2" 563 [(set_attr "type" "vecsimple") 564 (set_attr "length" "4")]) 565 566(define_insn "spe_evsrws" 567 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 568 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 569 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))] 570 "TARGET_SPE" 571 "evsrws %0,%1,%2" 572 [(set_attr "type" "vecsimple") 573 (set_attr "length" "4")]) 574 575(define_insn "spe_evsrwu" 576 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 577 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 578 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))] 579 "TARGET_SPE" 580 "evsrwu %0,%1,%2" 581 [(set_attr "type" "vecsimple") 582 (set_attr "length" "4")]) 583 584(define_insn "spe_evxor" 585 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 586 (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 587 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 588 "TARGET_SPE" 589 "evxor %0,%1,%2" 590 [(set_attr "type" "vecsimple") 591 (set_attr "length" "4")]) 592 593(define_insn "spe_evfsabs" 594 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 595 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] 596 "TARGET_SPE" 597 "evfsabs %0,%1" 598 [(set_attr "type" "vecfloat") 599 (set_attr "length" "4")]) 600 601(define_insn "spe_evfsadd" 602 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 603 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") 604 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) 605 (clobber (reg:SI SPEFSCR_REGNO))] 606 "TARGET_SPE" 607 "evfsadd %0,%1,%2" 608 [(set_attr "type" "vecfloat") 609 (set_attr "length" "4")]) 610 611(define_insn "spe_evfscfsf" 612 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 613 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))] 614 "TARGET_SPE" 615 "evfscfsf %0,%1" 616 [(set_attr "type" "vecfloat") 617 (set_attr "length" "4")]) 618 619(define_insn "spe_evfscfsi" 620 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 621 (fix:V2SI (match_operand:V2SF 1 "gpc_reg_operand" "r")))] 622 "TARGET_SPE" 623 "evfscfsi %0,%1" 624 [(set_attr "type" "vecfloat") 625 (set_attr "length" "4")]) 626 627(define_insn "spe_evfscfuf" 628 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 629 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))] 630 "TARGET_SPE" 631 "evfscfuf %0,%1" 632 [(set_attr "type" "vecfloat") 633 (set_attr "length" "4")]) 634 635(define_insn "spe_evfscfui" 636 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 637 (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))] 638 "TARGET_SPE" 639 "evfscfui %0,%1" 640 [(set_attr "type" "vecfloat") 641 (set_attr "length" "4")]) 642 643(define_insn "spe_evfsctsf" 644 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 645 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))] 646 "TARGET_SPE" 647 "evfsctsf %0,%1" 648 [(set_attr "type" "vecfloat") 649 (set_attr "length" "4")]) 650 651(define_insn "spe_evfsctsi" 652 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 653 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))] 654 "TARGET_SPE" 655 "evfsctsi %0,%1" 656 [(set_attr "type" "vecfloat") 657 (set_attr "length" "4")]) 658 659(define_insn "spe_evfsctsiz" 660 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 661 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))] 662 "TARGET_SPE" 663 "evfsctsiz %0,%1" 664 [(set_attr "type" "vecfloat") 665 (set_attr "length" "4")]) 666 667(define_insn "spe_evfsctuf" 668 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 669 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))] 670 "TARGET_SPE" 671 "evfsctuf %0,%1" 672 [(set_attr "type" "vecfloat") 673 (set_attr "length" "4")]) 674 675(define_insn "spe_evfsctui" 676 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 677 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))] 678 "TARGET_SPE" 679 "evfsctui %0,%1" 680 [(set_attr "type" "vecfloat") 681 (set_attr "length" "4")]) 682 683(define_insn "spe_evfsctuiz" 684 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 685 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))] 686 "TARGET_SPE" 687 "evfsctuiz %0,%1" 688 [(set_attr "type" "vecfloat") 689 (set_attr "length" "4")]) 690 691(define_insn "spe_evfsdiv" 692 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 693 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") 694 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) 695 (clobber (reg:SI SPEFSCR_REGNO))] 696 "TARGET_SPE" 697 "evfsdiv %0,%1,%2" 698 [(set_attr "type" "vecfloat") 699 (set_attr "length" "4")]) 700 701(define_insn "spe_evfsmul" 702 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 703 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") 704 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) 705 (clobber (reg:SI SPEFSCR_REGNO))] 706 "TARGET_SPE" 707 "evfsmul %0,%1,%2" 708 [(set_attr "type" "vecfloat") 709 (set_attr "length" "4")]) 710 711(define_insn "spe_evfsnabs" 712 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 713 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))] 714 "TARGET_SPE" 715 "evfsnabs %0,%1" 716 [(set_attr "type" "vecfloat") 717 (set_attr "length" "4")]) 718 719(define_insn "spe_evfsneg" 720 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 721 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] 722 "TARGET_SPE" 723 "evfsneg %0,%1" 724 [(set_attr "type" "vecfloat") 725 (set_attr "length" "4")]) 726 727(define_insn "spe_evfssub" 728 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 729 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") 730 (match_operand:V2SF 2 "gpc_reg_operand" "r"))) 731 (clobber (reg:SI SPEFSCR_REGNO))] 732 "TARGET_SPE" 733 "evfssub %0,%1,%2" 734 [(set_attr "type" "vecfloat") 735 (set_attr "length" "4")]) 736 737;; SPE SIMD load instructions. 738 739;; Only the hardware engineer who designed the SPE inderstands the 740;; plethora of load and store instructions ;-). We have no way of 741;; differentiating between them with RTL so use an unspec of const_int 0 742;; to avoid identical RTL. 743 744(define_insn "spe_evldd" 745 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 746 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 747 (match_operand:QI 2 "immediate_operand" "i")))) 748 (unspec [(const_int 0)] 544)] 749 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 750 "evldd %0,%1,%2" 751 [(set_attr "type" "vecload") 752 (set_attr "length" "4")]) 753 754(define_insn "spe_evlddx" 755 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 756 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 757 (match_operand:SI 2 "gpc_reg_operand" "r")))) 758 (unspec [(const_int 0)] 545)] 759 "TARGET_SPE" 760 "evlddx %0,%1,%2" 761 [(set_attr "type" "vecload") 762 (set_attr "length" "4")]) 763 764(define_insn "spe_evldh" 765 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 766 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 767 (match_operand:QI 2 "immediate_operand" "i")))) 768 (unspec [(const_int 0)] 546)] 769 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" 770 "evldh %0,%1,%2" 771 [(set_attr "type" "vecload") 772 (set_attr "length" "4")]) 773 774(define_insn "spe_evldhx" 775 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 776 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 777 (match_operand:SI 2 "gpc_reg_operand" "r")))) 778 (unspec [(const_int 0)] 547)] 779 "TARGET_SPE" 780 "evldhx %0,%1,%2" 781 [(set_attr "type" "vecload") 782 (set_attr "length" "4")]) 783 784(define_insn "spe_evldw" 785 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 786 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 787 (match_operand:QI 2 "immediate_operand" "i")))) 788 (unspec [(const_int 0)] 548)] 789 "TARGET_SPE" 790 "evldw %0,%1,%2" 791 [(set_attr "type" "vecload") 792 (set_attr "length" "4")]) 793 794(define_insn "spe_evldwx" 795 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 796 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 797 (match_operand:SI 2 "gpc_reg_operand" "r")))) 798 (unspec [(const_int 0)] 549)] 799 "TARGET_SPE" 800 "evldwx %0,%1,%2" 801 [(set_attr "type" "vecload") 802 (set_attr "length" "4")]) 803 804(define_insn "spe_evlwhe" 805 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 806 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 807 (match_operand:QI 2 "immediate_operand" "i")))) 808 (unspec [(const_int 0)] 550)] 809 "TARGET_SPE" 810 "evlwhe %0,%1,%2" 811 [(set_attr "type" "vecload") 812 (set_attr "length" "4")]) 813 814(define_insn "spe_evlwhex" 815 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 816 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 817 (match_operand:SI 2 "gpc_reg_operand" "r")))) 818 (unspec [(const_int 0)] 551)] 819 "TARGET_SPE" 820 "evlwhex %0,%1,%2" 821 [(set_attr "type" "vecload") 822 (set_attr "length" "4")]) 823 824(define_insn "spe_evlwhos" 825 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 826 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 827 (match_operand:QI 2 "immediate_operand" "i")))) 828 (unspec [(const_int 0)] 552)] 829 "TARGET_SPE" 830 "evlwhos %0,%1,%2" 831 [(set_attr "type" "vecload") 832 (set_attr "length" "4")]) 833 834(define_insn "spe_evlwhosx" 835 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 836 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 837 (match_operand:SI 2 "gpc_reg_operand" "r")))) 838 (unspec [(const_int 0)] 553)] 839 "TARGET_SPE" 840 "evlwhosx %0,%1,%2" 841 [(set_attr "type" "vecload") 842 (set_attr "length" "4")]) 843 844(define_insn "spe_evlwhou" 845 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 846 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 847 (match_operand:QI 2 "immediate_operand" "i")))) 848 (unspec [(const_int 0)] 554)] 849 "TARGET_SPE" 850 "evlwhou %0,%1,%2" 851 [(set_attr "type" "vecload") 852 (set_attr "length" "4")]) 853 854(define_insn "spe_evlwhoux" 855 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 856 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 857 (match_operand:SI 2 "gpc_reg_operand" "r")))) 858 (unspec [(const_int 0)] 555)] 859 "TARGET_SPE" 860 "evlwhoux %0,%1,%2" 861 [(set_attr "type" "vecload") 862 (set_attr "length" "4")]) 863 864(define_insn "spe_brinc" 865 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 866 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r") 867 (match_operand:SI 2 "gpc_reg_operand" "r")] 556))] 868 "TARGET_SPE" 869 "brinc %0,%1,%2" 870 [(set_attr "type" "veccomplex") 871 (set_attr "length" "4")]) 872 873(define_insn "spe_evmhegsmfaa" 874 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 875 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 876 (match_operand:V2SI 2 "gpc_reg_operand" "r") 877 (reg:V2SI SPE_ACC_REGNO)] 557)) 878 (clobber (reg:V2SI SPE_ACC_REGNO))] 879 "TARGET_SPE" 880 "evmhegsmfaa %0,%1,%2" 881 [(set_attr "type" "veccomplex") 882 (set_attr "length" "4")]) 883 884(define_insn "spe_evmhegsmfan" 885 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 886 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 887 (match_operand:V2SI 2 "gpc_reg_operand" "r") 888 (reg:V2SI SPE_ACC_REGNO)] 558)) 889 (clobber (reg:V2SI SPE_ACC_REGNO))] 890 "TARGET_SPE" 891 "evmhegsmfan %0,%1,%2" 892 [(set_attr "type" "veccomplex") 893 (set_attr "length" "4")]) 894 895(define_insn "spe_evmhegsmiaa" 896 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 897 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 898 (match_operand:V2SI 2 "gpc_reg_operand" "r") 899 (reg:V2SI SPE_ACC_REGNO)] 559)) 900 (clobber (reg:V2SI SPE_ACC_REGNO))] 901 "TARGET_SPE" 902 "evmhegsmiaa %0,%1,%2" 903 [(set_attr "type" "veccomplex") 904 (set_attr "length" "4")]) 905 906(define_insn "spe_evmhegsmian" 907 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 908 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 909 (match_operand:V2SI 2 "gpc_reg_operand" "r") 910 (reg:V2SI SPE_ACC_REGNO)] 560)) 911 (clobber (reg:V2SI SPE_ACC_REGNO))] 912 "TARGET_SPE" 913 "evmhegsmian %0,%1,%2" 914 [(set_attr "type" "veccomplex") 915 (set_attr "length" "4")]) 916 917(define_insn "spe_evmhegumiaa" 918 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 919 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 920 (match_operand:V2SI 2 "gpc_reg_operand" "r") 921 (reg:V2SI SPE_ACC_REGNO)] 561)) 922 (clobber (reg:V2SI SPE_ACC_REGNO))] 923 "TARGET_SPE" 924 "evmhegumiaa %0,%1,%2" 925 [(set_attr "type" "veccomplex") 926 (set_attr "length" "4")]) 927 928(define_insn "spe_evmhegumian" 929 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 930 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 931 (match_operand:V2SI 2 "gpc_reg_operand" "r") 932 (reg:V2SI SPE_ACC_REGNO)] 562)) 933 (clobber (reg:V2SI SPE_ACC_REGNO))] 934 "TARGET_SPE" 935 "evmhegumian %0,%1,%2" 936 [(set_attr "type" "veccomplex") 937 (set_attr "length" "4")]) 938 939(define_insn "spe_evmhesmfaaw" 940 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 941 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 942 (match_operand:V2SI 2 "gpc_reg_operand" "r") 943 (reg:V2SI SPE_ACC_REGNO)] 563)) 944 (clobber (reg:V2SI SPE_ACC_REGNO))] 945 "TARGET_SPE" 946 "evmhesmfaaw %0,%1,%2" 947 [(set_attr "type" "veccomplex") 948 (set_attr "length" "4")]) 949 950(define_insn "spe_evmhesmfanw" 951 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 952 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 953 (match_operand:V2SI 2 "gpc_reg_operand" "r") 954 (reg:V2SI SPE_ACC_REGNO)] 564)) 955 (clobber (reg:V2SI SPE_ACC_REGNO))] 956 "TARGET_SPE" 957 "evmhesmfanw %0,%1,%2" 958 [(set_attr "type" "veccomplex") 959 (set_attr "length" "4")]) 960 961(define_insn "spe_evmhesmfa" 962 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 963 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 964 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565)) 965 (clobber (reg:V2SI SPE_ACC_REGNO))] 966 "TARGET_SPE" 967 "evmhesmfa %0,%1,%2" 968 [(set_attr "type" "veccomplex") 969 (set_attr "length" "4")]) 970 971(define_insn "spe_evmhesmf" 972 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 973 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 974 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))] 975 "TARGET_SPE" 976 "evmhesmf %0,%1,%2" 977 [(set_attr "type" "veccomplex") 978 (set_attr "length" "4")]) 979 980(define_insn "spe_evmhesmiaaw" 981 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 982 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 983 (match_operand:V2SI 2 "gpc_reg_operand" "r") 984 (reg:V2SI SPE_ACC_REGNO)] 567)) 985 (clobber (reg:V2SI SPE_ACC_REGNO))] 986 "TARGET_SPE" 987 "evmhesmiaaw %0,%1,%2" 988 [(set_attr "type" "veccomplex") 989 (set_attr "length" "4")]) 990 991(define_insn "spe_evmhesmianw" 992 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 993 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 994 (match_operand:V2SI 2 "gpc_reg_operand" "r") 995 (reg:V2SI SPE_ACC_REGNO)] 568)) 996 (clobber (reg:V2SI SPE_ACC_REGNO))] 997 "TARGET_SPE" 998 "evmhesmianw %0,%1,%2" 999 [(set_attr "type" "veccomplex") 1000 (set_attr "length" "4")]) 1001 1002(define_insn "spe_evmhesmia" 1003 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1004 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1005 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569)) 1006 (clobber (reg:V2SI SPE_ACC_REGNO))] 1007 "TARGET_SPE" 1008 "evmhesmia %0,%1,%2" 1009 [(set_attr "type" "veccomplex") 1010 (set_attr "length" "4")]) 1011 1012(define_insn "spe_evmhesmi" 1013 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1014 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1015 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))] 1016 "TARGET_SPE" 1017 "evmhesmi %0,%1,%2" 1018 [(set_attr "type" "veccomplex") 1019 (set_attr "length" "4")]) 1020 1021(define_insn "spe_evmhessfaaw" 1022 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1023 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1024 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1025 (reg:V2SI SPE_ACC_REGNO)] 571)) 1026 (clobber (reg:SI SPEFSCR_REGNO)) 1027 (clobber (reg:V2SI SPE_ACC_REGNO))] 1028 "TARGET_SPE" 1029 "evmhessfaaw %0,%1,%2" 1030 [(set_attr "type" "veccomplex") 1031 (set_attr "length" "4")]) 1032 1033(define_insn "spe_evmhessfanw" 1034 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1035 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1036 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1037 (reg:V2SI SPE_ACC_REGNO)] 572)) 1038 (clobber (reg:SI SPEFSCR_REGNO)) 1039 (clobber (reg:V2SI SPE_ACC_REGNO))] 1040 "TARGET_SPE" 1041 "evmhessfanw %0,%1,%2" 1042 [(set_attr "type" "veccomplex") 1043 (set_attr "length" "4")]) 1044 1045(define_insn "spe_evmhessfa" 1046 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1047 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1048 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573)) 1049 (clobber (reg:SI SPEFSCR_REGNO)) 1050 (clobber (reg:V2SI SPE_ACC_REGNO))] 1051 "TARGET_SPE" 1052 "evmhessfa %0,%1,%2" 1053 [(set_attr "type" "veccomplex") 1054 (set_attr "length" "4")]) 1055 1056(define_insn "spe_evmhessf" 1057 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1058 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1059 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574)) 1060 (clobber (reg:SI SPEFSCR_REGNO))] 1061 "TARGET_SPE" 1062 "evmhessf %0,%1,%2" 1063 [(set_attr "type" "veccomplex") 1064 (set_attr "length" "4")]) 1065 1066(define_insn "spe_evmhessiaaw" 1067 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1068 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1069 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1070 (reg:V2SI SPE_ACC_REGNO)] 575)) 1071 (clobber (reg:SI SPEFSCR_REGNO)) 1072 (clobber (reg:V2SI SPE_ACC_REGNO))] 1073 "TARGET_SPE" 1074 "evmhessiaaw %0,%1,%2" 1075 [(set_attr "type" "veccomplex") 1076 (set_attr "length" "4")]) 1077 1078(define_insn "spe_evmhessianw" 1079 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1080 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1081 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1082 (reg:V2SI SPE_ACC_REGNO)] 576)) 1083 (clobber (reg:SI SPEFSCR_REGNO)) 1084 (clobber (reg:V2SI SPE_ACC_REGNO))] 1085 "TARGET_SPE" 1086 "evmhessianw %0,%1,%2" 1087 [(set_attr "type" "veccomplex") 1088 (set_attr "length" "4")]) 1089 1090(define_insn "spe_evmheumiaaw" 1091 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1092 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1093 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1094 (reg:V2SI SPE_ACC_REGNO)] 577)) 1095 (clobber (reg:V2SI SPE_ACC_REGNO))] 1096 "TARGET_SPE" 1097 "evmheumiaaw %0,%1,%2" 1098 [(set_attr "type" "veccomplex") 1099 (set_attr "length" "4")]) 1100 1101(define_insn "spe_evmheumianw" 1102 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1103 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1104 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1105 (reg:V2SI SPE_ACC_REGNO)] 578)) 1106 (clobber (reg:V2SI SPE_ACC_REGNO))] 1107 "TARGET_SPE" 1108 "evmheumianw %0,%1,%2" 1109 [(set_attr "type" "veccomplex") 1110 (set_attr "length" "4")]) 1111 1112(define_insn "spe_evmheumia" 1113 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1114 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1115 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579)) 1116 (clobber (reg:V2SI SPE_ACC_REGNO))] 1117 "TARGET_SPE" 1118 "evmheumia %0,%1,%2" 1119 [(set_attr "type" "veccomplex") 1120 (set_attr "length" "4")]) 1121 1122(define_insn "spe_evmheumi" 1123 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1124 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1125 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))] 1126 "TARGET_SPE" 1127 "evmheumi %0,%1,%2" 1128 [(set_attr "type" "veccomplex") 1129 (set_attr "length" "4")]) 1130 1131(define_insn "spe_evmheusiaaw" 1132 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1133 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1134 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1135 (reg:V2SI SPE_ACC_REGNO)] 581)) 1136 (clobber (reg:SI SPEFSCR_REGNO)) 1137 (clobber (reg:V2SI SPE_ACC_REGNO))] 1138 "TARGET_SPE" 1139 "evmheusiaaw %0,%1,%2" 1140 [(set_attr "type" "veccomplex") 1141 (set_attr "length" "4")]) 1142 1143(define_insn "spe_evmheusianw" 1144 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1145 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1146 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1147 (reg:V2SI SPE_ACC_REGNO)] 582)) 1148 (clobber (reg:SI SPEFSCR_REGNO)) 1149 (clobber (reg:V2SI SPE_ACC_REGNO))] 1150 "TARGET_SPE" 1151 "evmheusianw %0,%1,%2" 1152 [(set_attr "type" "veccomplex") 1153 (set_attr "length" "4")]) 1154 1155(define_insn "spe_evmhogsmfaa" 1156 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1157 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1158 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1159 (reg:V2SI SPE_ACC_REGNO)] 583)) 1160 (clobber (reg:V2SI SPE_ACC_REGNO))] 1161 "TARGET_SPE" 1162 "evmhogsmfaa %0,%1,%2" 1163 [(set_attr "type" "veccomplex") 1164 (set_attr "length" "4")]) 1165 1166(define_insn "spe_evmhogsmfan" 1167 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1168 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1169 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1170 (reg:V2SI SPE_ACC_REGNO)] 584)) 1171 (clobber (reg:V2SI SPE_ACC_REGNO))] 1172 "TARGET_SPE" 1173 "evmhogsmfan %0,%1,%2" 1174 [(set_attr "type" "veccomplex") 1175 (set_attr "length" "4")]) 1176 1177(define_insn "spe_evmhogsmiaa" 1178 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1179 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1180 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1181 (reg:V2SI SPE_ACC_REGNO)] 585)) 1182 (clobber (reg:V2SI SPE_ACC_REGNO))] 1183 "TARGET_SPE" 1184 "evmhogsmiaa %0,%1,%2" 1185 [(set_attr "type" "veccomplex") 1186 (set_attr "length" "4")]) 1187 1188(define_insn "spe_evmhogsmian" 1189 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1190 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1191 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1192 (reg:V2SI SPE_ACC_REGNO)] 586)) 1193 (clobber (reg:V2SI SPE_ACC_REGNO))] 1194 "TARGET_SPE" 1195 "evmhogsmian %0,%1,%2" 1196 [(set_attr "type" "veccomplex") 1197 (set_attr "length" "4")]) 1198 1199(define_insn "spe_evmhogumiaa" 1200 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1201 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1202 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1203 (reg:V2SI SPE_ACC_REGNO)] 587)) 1204 (clobber (reg:V2SI SPE_ACC_REGNO))] 1205 "TARGET_SPE" 1206 "evmhogumiaa %0,%1,%2" 1207 [(set_attr "type" "veccomplex") 1208 (set_attr "length" "4")]) 1209 1210(define_insn "spe_evmhogumian" 1211 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1212 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1213 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1214 (reg:V2SI SPE_ACC_REGNO)] 588)) 1215 (clobber (reg:V2SI SPE_ACC_REGNO))] 1216 "TARGET_SPE" 1217 "evmhogumian %0,%1,%2" 1218 [(set_attr "type" "veccomplex") 1219 (set_attr "length" "4")]) 1220 1221(define_insn "spe_evmhosmfaaw" 1222 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1223 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1224 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1225 (reg:V2SI SPE_ACC_REGNO)] 589)) 1226 (clobber (reg:V2SI SPE_ACC_REGNO))] 1227 "TARGET_SPE" 1228 "evmhosmfaaw %0,%1,%2" 1229 [(set_attr "type" "veccomplex") 1230 (set_attr "length" "4")]) 1231 1232(define_insn "spe_evmhosmfanw" 1233 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1234 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1235 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1236 (reg:V2SI SPE_ACC_REGNO)] 590)) 1237 (clobber (reg:V2SI SPE_ACC_REGNO))] 1238 "TARGET_SPE" 1239 "evmhosmfanw %0,%1,%2" 1240 [(set_attr "type" "veccomplex") 1241 (set_attr "length" "4")]) 1242 1243(define_insn "spe_evmhosmfa" 1244 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1245 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1246 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))] 1247 "TARGET_SPE" 1248 "evmhosmfa %0,%1,%2" 1249 [(set_attr "type" "veccomplex") 1250 (set_attr "length" "4")]) 1251 1252(define_insn "spe_evmhosmf" 1253 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1254 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1255 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592)) 1256 (clobber (reg:V2SI SPE_ACC_REGNO))] 1257 "TARGET_SPE" 1258 "evmhosmf %0,%1,%2" 1259 [(set_attr "type" "veccomplex") 1260 (set_attr "length" "4")]) 1261 1262(define_insn "spe_evmhosmiaaw" 1263 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1264 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1265 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1266 (reg:V2SI SPE_ACC_REGNO)] 593)) 1267 (clobber (reg:V2SI SPE_ACC_REGNO))] 1268 "TARGET_SPE" 1269 "evmhosmiaaw %0,%1,%2" 1270 [(set_attr "type" "veccomplex") 1271 (set_attr "length" "4")]) 1272 1273(define_insn "spe_evmhosmianw" 1274 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1275 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1276 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1277 (reg:V2SI SPE_ACC_REGNO)] 594)) 1278 (clobber (reg:V2SI SPE_ACC_REGNO))] 1279 "TARGET_SPE" 1280 "evmhosmianw %0,%1,%2" 1281 [(set_attr "type" "veccomplex") 1282 (set_attr "length" "4")]) 1283 1284(define_insn "spe_evmhosmia" 1285 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1286 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1287 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595)) 1288 (clobber (reg:V2SI SPE_ACC_REGNO))] 1289 "TARGET_SPE" 1290 "evmhosmia %0,%1,%2" 1291 [(set_attr "type" "veccomplex") 1292 (set_attr "length" "4")]) 1293 1294(define_insn "spe_evmhosmi" 1295 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1296 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1297 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))] 1298 "TARGET_SPE" 1299 "evmhosmi %0,%1,%2" 1300 [(set_attr "type" "veccomplex") 1301 (set_attr "length" "4")]) 1302 1303(define_insn "spe_evmhossfaaw" 1304 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1305 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1306 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1307 (reg:V2SI SPE_ACC_REGNO)] 597)) 1308 (clobber (reg:SI SPEFSCR_REGNO)) 1309 (clobber (reg:V2SI SPE_ACC_REGNO))] 1310 "TARGET_SPE" 1311 "evmhossfaaw %0,%1,%2" 1312 [(set_attr "type" "veccomplex") 1313 (set_attr "length" "4")]) 1314 1315(define_insn "spe_evmhossfanw" 1316 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1317 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1318 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1319 (reg:V2SI SPE_ACC_REGNO)] 598)) 1320 (clobber (reg:SI SPEFSCR_REGNO)) 1321 (clobber (reg:V2SI SPE_ACC_REGNO))] 1322 "TARGET_SPE" 1323 "evmhossfanw %0,%1,%2" 1324 [(set_attr "type" "veccomplex") 1325 (set_attr "length" "4")]) 1326 1327(define_insn "spe_evmhossfa" 1328 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1329 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1330 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1331 (reg:V2SI SPE_ACC_REGNO)] 599)) 1332 (clobber (reg:SI SPEFSCR_REGNO)) 1333 (clobber (reg:V2SI SPE_ACC_REGNO))] 1334 "TARGET_SPE" 1335 "evmhossfa %0,%1,%2" 1336 [(set_attr "type" "veccomplex") 1337 (set_attr "length" "4")]) 1338 1339(define_insn "spe_evmhossf" 1340 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1341 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1342 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600)) 1343 (clobber (reg:SI SPEFSCR_REGNO))] 1344 "TARGET_SPE" 1345 "evmhossf %0,%1,%2" 1346 [(set_attr "type" "veccomplex") 1347 (set_attr "length" "4")]) 1348 1349(define_insn "spe_evmhossiaaw" 1350 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1351 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1352 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1353 (reg:V2SI SPE_ACC_REGNO)] 601)) 1354 (clobber (reg:SI SPEFSCR_REGNO)) 1355 (clobber (reg:V2SI SPE_ACC_REGNO))] 1356 "TARGET_SPE" 1357 "evmhossiaaw %0,%1,%2" 1358 [(set_attr "type" "veccomplex") 1359 (set_attr "length" "4")]) 1360 1361(define_insn "spe_evmhossianw" 1362 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1363 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1364 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1365 (reg:V2SI SPE_ACC_REGNO)] 602)) 1366 (clobber (reg:SI SPEFSCR_REGNO)) 1367 (clobber (reg:V2SI SPE_ACC_REGNO))] 1368 "TARGET_SPE" 1369 "evmhossianw %0,%1,%2" 1370 [(set_attr "type" "veccomplex") 1371 (set_attr "length" "4")]) 1372 1373(define_insn "spe_evmhoumiaaw" 1374 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1375 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1376 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1377 (reg:V2SI SPE_ACC_REGNO)] 603)) 1378 (clobber (reg:V2SI SPE_ACC_REGNO))] 1379 "TARGET_SPE" 1380 "evmhoumiaaw %0,%1,%2" 1381 [(set_attr "type" "veccomplex") 1382 (set_attr "length" "4")]) 1383 1384(define_insn "spe_evmhoumianw" 1385 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1386 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1387 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1388 (reg:V2SI SPE_ACC_REGNO)] 604)) 1389 (clobber (reg:V2SI SPE_ACC_REGNO))] 1390 "TARGET_SPE" 1391 "evmhoumianw %0,%1,%2" 1392 [(set_attr "type" "veccomplex") 1393 (set_attr "length" "4")]) 1394 1395(define_insn "spe_evmhoumia" 1396 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1397 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1398 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605)) 1399 (clobber (reg:V2SI SPE_ACC_REGNO))] 1400 "TARGET_SPE" 1401 "evmhoumia %0,%1,%2" 1402 [(set_attr "type" "veccomplex") 1403 (set_attr "length" "4")]) 1404 1405(define_insn "spe_evmhoumi" 1406 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1407 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1408 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))] 1409 "TARGET_SPE" 1410 "evmhoumi %0,%1,%2" 1411 [(set_attr "type" "veccomplex") 1412 (set_attr "length" "4")]) 1413 1414(define_insn "spe_evmhousiaaw" 1415 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1416 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1417 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1418 (reg:V2SI SPE_ACC_REGNO)] 607)) 1419 (clobber (reg:SI SPEFSCR_REGNO)) 1420 (clobber (reg:V2SI SPE_ACC_REGNO))] 1421 "TARGET_SPE" 1422 "evmhousiaaw %0,%1,%2" 1423 [(set_attr "type" "veccomplex") 1424 (set_attr "length" "4")]) 1425 1426(define_insn "spe_evmhousianw" 1427 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1428 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1429 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1430 (reg:V2SI SPE_ACC_REGNO)] 608)) 1431 (clobber (reg:SI SPEFSCR_REGNO)) 1432 (clobber (reg:V2SI SPE_ACC_REGNO))] 1433 "TARGET_SPE" 1434 "evmhousianw %0,%1,%2" 1435 [(set_attr "type" "veccomplex") 1436 (set_attr "length" "4")]) 1437 1438(define_insn "spe_evmmlssfa" 1439 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1440 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1441 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))] 1442 "TARGET_SPE" 1443 "evmmlssfa %0,%1,%2" 1444 [(set_attr "type" "veccomplex") 1445 (set_attr "length" "4")]) 1446 1447(define_insn "spe_evmmlssf" 1448 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1449 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1450 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))] 1451 "TARGET_SPE" 1452 "evmmlssf %0,%1,%2" 1453 [(set_attr "type" "veccomplex") 1454 (set_attr "length" "4")]) 1455 1456(define_insn "spe_evmwhsmfa" 1457 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1458 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1459 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611)) 1460 (clobber (reg:V2SI SPE_ACC_REGNO))] 1461 "TARGET_SPE" 1462 "evmwhsmfa %0,%1,%2" 1463 [(set_attr "type" "veccomplex") 1464 (set_attr "length" "4")]) 1465 1466(define_insn "spe_evmwhsmf" 1467 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1468 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1469 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))] 1470 "TARGET_SPE" 1471 "evmwhsmf %0,%1,%2" 1472 [(set_attr "type" "veccomplex") 1473 (set_attr "length" "4")]) 1474 1475(define_insn "spe_evmwhsmia" 1476 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1477 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1478 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613)) 1479 (clobber (reg:V2SI SPE_ACC_REGNO))] 1480 "TARGET_SPE" 1481 "evmwhsmia %0,%1,%2" 1482 [(set_attr "type" "veccomplex") 1483 (set_attr "length" "4")]) 1484 1485(define_insn "spe_evmwhsmi" 1486 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1487 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1488 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))] 1489 "TARGET_SPE" 1490 "evmwhsmi %0,%1,%2" 1491 [(set_attr "type" "veccomplex") 1492 (set_attr "length" "4")]) 1493 1494(define_insn "spe_evmwhssfa" 1495 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1496 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1497 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615)) 1498 (clobber (reg:SI SPEFSCR_REGNO)) 1499 (clobber (reg:V2SI SPE_ACC_REGNO))] 1500 "TARGET_SPE" 1501 "evmwhssfa %0,%1,%2" 1502 [(set_attr "type" "veccomplex") 1503 (set_attr "length" "4")]) 1504 1505(define_insn "spe_evmwhusian" 1506 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1507 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1508 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))] 1509 "TARGET_SPE" 1510 "evmwhusian %0,%1,%2" 1511 [(set_attr "type" "veccomplex") 1512 (set_attr "length" "4")]) 1513 1514(define_insn "spe_evmwhssf" 1515 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1516 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1517 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628)) 1518 (clobber (reg:SI SPEFSCR_REGNO))] 1519 "TARGET_SPE" 1520 "evmwhssf %0,%1,%2" 1521 [(set_attr "type" "veccomplex") 1522 (set_attr "length" "4")]) 1523 1524(define_insn "spe_evmwhumia" 1525 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1526 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1527 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629)) 1528 (clobber (reg:V2SI SPE_ACC_REGNO))] 1529 "TARGET_SPE" 1530 "evmwhumia %0,%1,%2" 1531 [(set_attr "type" "veccomplex") 1532 (set_attr "length" "4")]) 1533 1534(define_insn "spe_evmwhumi" 1535 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1536 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1537 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))] 1538 "TARGET_SPE" 1539 "evmwhumi %0,%1,%2" 1540 [(set_attr "type" "veccomplex") 1541 (set_attr "length" "4")]) 1542 1543(define_insn "spe_evmwlsmiaaw" 1544 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1545 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1546 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1547 (reg:V2SI SPE_ACC_REGNO)] 635)) 1548 (clobber (reg:V2SI SPE_ACC_REGNO))] 1549 "TARGET_SPE" 1550 "evmwlsmiaaw %0,%1,%2" 1551 [(set_attr "type" "veccomplex") 1552 (set_attr "length" "4")]) 1553 1554(define_insn "spe_evmwlsmianw" 1555 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1556 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1557 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1558 (reg:V2SI SPE_ACC_REGNO)] 636)) 1559 (clobber (reg:V2SI SPE_ACC_REGNO))] 1560 "TARGET_SPE" 1561 "evmwlsmianw %0,%1,%2" 1562 [(set_attr "type" "veccomplex") 1563 (set_attr "length" "4")]) 1564 1565(define_insn "spe_evmwlssiaaw" 1566 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1567 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1568 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1569 (reg:V2SI SPE_ACC_REGNO)] 641)) 1570 (clobber (reg:SI SPEFSCR_REGNO)) 1571 (clobber (reg:V2SI SPE_ACC_REGNO))] 1572 "TARGET_SPE" 1573 "evmwlssiaaw %0,%1,%2" 1574 [(set_attr "type" "veccomplex") 1575 (set_attr "length" "4")]) 1576 1577(define_insn "spe_evmwlssianw" 1578 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1579 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1580 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1581 (reg:V2SI SPE_ACC_REGNO)] 642)) 1582 (clobber (reg:SI SPEFSCR_REGNO)) 1583 (clobber (reg:V2SI SPE_ACC_REGNO))] 1584 "TARGET_SPE" 1585 "evmwlssianw %0,%1,%2" 1586 [(set_attr "type" "veccomplex") 1587 (set_attr "length" "4")]) 1588 1589(define_insn "spe_evmwlumiaaw" 1590 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1591 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1592 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1593 (reg:V2SI SPE_ACC_REGNO)] 643)) 1594 (clobber (reg:V2SI SPE_ACC_REGNO))] 1595 "TARGET_SPE" 1596 "evmwlumiaaw %0,%1,%2" 1597 [(set_attr "type" "veccomplex") 1598 (set_attr "length" "4")]) 1599 1600(define_insn "spe_evmwlumianw" 1601 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1602 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1603 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1604 (reg:V2SI SPE_ACC_REGNO)] 644)) 1605 (clobber (reg:V2SI SPE_ACC_REGNO))] 1606 "TARGET_SPE" 1607 "evmwlumianw %0,%1,%2" 1608 [(set_attr "type" "veccomplex") 1609 (set_attr "length" "4")]) 1610 1611(define_insn "spe_evmwlumia" 1612 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1613 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1614 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645)) 1615 (clobber (reg:V2SI SPE_ACC_REGNO))] 1616 "TARGET_SPE" 1617 "evmwlumia %0,%1,%2" 1618 [(set_attr "type" "veccomplex") 1619 (set_attr "length" "4")]) 1620 1621(define_insn "spe_evmwlumi" 1622 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1623 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1624 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))] 1625 "TARGET_SPE" 1626 "evmwlumi %0,%1,%2" 1627 [(set_attr "type" "veccomplex") 1628 (set_attr "length" "4")]) 1629 1630(define_insn "spe_evmwlusiaaw" 1631 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1632 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1633 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1634 (reg:V2SI SPE_ACC_REGNO)] 647)) 1635 (clobber (reg:SI SPEFSCR_REGNO)) 1636 (clobber (reg:V2SI SPE_ACC_REGNO))] 1637 "TARGET_SPE" 1638 "evmwlusiaaw %0,%1,%2" 1639 [(set_attr "type" "veccomplex") 1640 (set_attr "length" "4")]) 1641 1642(define_insn "spe_evmwlusianw" 1643 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1644 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1645 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1646 (reg:V2SI SPE_ACC_REGNO)] 648)) 1647 (clobber (reg:SI SPEFSCR_REGNO)) 1648 (clobber (reg:V2SI SPE_ACC_REGNO))] 1649 "TARGET_SPE" 1650 "evmwlusianw %0,%1,%2" 1651 [(set_attr "type" "veccomplex") 1652 (set_attr "length" "4")]) 1653 1654(define_insn "spe_evmwsmfaa" 1655 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1656 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1657 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1658 (reg:V2SI SPE_ACC_REGNO)] 649)) 1659 (clobber (reg:V2SI SPE_ACC_REGNO))] 1660 "TARGET_SPE" 1661 "evmwsmfaa %0,%1,%2" 1662 [(set_attr "type" "veccomplex") 1663 (set_attr "length" "4")]) 1664 1665(define_insn "spe_evmwsmfan" 1666 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1667 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1668 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1669 (reg:V2SI SPE_ACC_REGNO)] 650)) 1670 (clobber (reg:V2SI SPE_ACC_REGNO))] 1671 "TARGET_SPE" 1672 "evmwsmfan %0,%1,%2" 1673 [(set_attr "type" "veccomplex") 1674 (set_attr "length" "4")]) 1675 1676(define_insn "spe_evmwsmfa" 1677 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1678 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1679 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651)) 1680 (clobber (reg:V2SI SPE_ACC_REGNO))] 1681 "TARGET_SPE" 1682 "evmwsmfa %0,%1,%2" 1683 [(set_attr "type" "veccomplex") 1684 (set_attr "length" "4")]) 1685 1686(define_insn "spe_evmwsmf" 1687 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1688 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1689 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))] 1690 "TARGET_SPE" 1691 "evmwsmf %0,%1,%2" 1692 [(set_attr "type" "veccomplex") 1693 (set_attr "length" "4")]) 1694 1695(define_insn "spe_evmwsmiaa" 1696 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1697 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1698 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1699 (reg:V2SI SPE_ACC_REGNO)] 653)) 1700 (clobber (reg:V2SI SPE_ACC_REGNO))] 1701 "TARGET_SPE" 1702 "evmwsmiaa %0,%1,%2" 1703 [(set_attr "type" "veccomplex") 1704 (set_attr "length" "4")]) 1705 1706(define_insn "spe_evmwsmian" 1707 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1708 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1709 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1710 (reg:V2SI SPE_ACC_REGNO)] 654)) 1711 (clobber (reg:V2SI SPE_ACC_REGNO))] 1712 "TARGET_SPE" 1713 "evmwsmian %0,%1,%2" 1714 [(set_attr "type" "veccomplex") 1715 (set_attr "length" "4")]) 1716 1717(define_insn "spe_evmwsmia" 1718 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1719 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1720 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655)) 1721 (clobber (reg:V2SI SPE_ACC_REGNO))] 1722 "TARGET_SPE" 1723 "evmwsmia %0,%1,%2" 1724 [(set_attr "type" "veccomplex") 1725 (set_attr "length" "4")]) 1726 1727(define_insn "spe_evmwsmi" 1728 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1729 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1730 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))] 1731 "TARGET_SPE" 1732 "evmwsmi %0,%1,%2" 1733 [(set_attr "type" "veccomplex") 1734 (set_attr "length" "4")]) 1735 1736(define_insn "spe_evmwssfaa" 1737 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1738 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1739 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1740 (reg:V2SI SPE_ACC_REGNO)] 657)) 1741 (clobber (reg:SI SPEFSCR_REGNO)) 1742 (clobber (reg:V2SI SPE_ACC_REGNO))] 1743 "TARGET_SPE" 1744 "evmwssfaa %0,%1,%2" 1745 [(set_attr "type" "veccomplex") 1746 (set_attr "length" "4")]) 1747 1748(define_insn "spe_evmwssfan" 1749 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1750 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1751 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1752 (reg:V2SI SPE_ACC_REGNO)] 658)) 1753 (clobber (reg:SI SPEFSCR_REGNO)) 1754 (clobber (reg:V2SI SPE_ACC_REGNO))] 1755 "TARGET_SPE" 1756 "evmwssfan %0,%1,%2" 1757 [(set_attr "type" "veccomplex") 1758 (set_attr "length" "4")]) 1759 1760(define_insn "spe_evmwssfa" 1761 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1762 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1763 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659)) 1764 (clobber (reg:SI SPEFSCR_REGNO)) 1765 (clobber (reg:V2SI SPE_ACC_REGNO))] 1766 "TARGET_SPE" 1767 "evmwssfa %0,%1,%2" 1768 [(set_attr "type" "veccomplex") 1769 (set_attr "length" "4")]) 1770 1771(define_insn "spe_evmwssf" 1772 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1773 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1774 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660)) 1775 (clobber (reg:SI SPEFSCR_REGNO))] 1776 "TARGET_SPE" 1777 "evmwssf %0,%1,%2" 1778 [(set_attr "type" "veccomplex") 1779 (set_attr "length" "4")]) 1780 1781(define_insn "spe_evmwumiaa" 1782 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1783 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1784 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1785 (reg:V2SI SPE_ACC_REGNO)] 661)) 1786 (clobber (reg:V2SI SPE_ACC_REGNO))] 1787 "TARGET_SPE" 1788 "evmwumiaa %0,%1,%2" 1789 [(set_attr "type" "veccomplex") 1790 (set_attr "length" "4")]) 1791 1792(define_insn "spe_evmwumian" 1793 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1794 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1795 (match_operand:V2SI 2 "gpc_reg_operand" "r") 1796 (reg:V2SI SPE_ACC_REGNO)] 662)) 1797 (clobber (reg:V2SI SPE_ACC_REGNO))] 1798 "TARGET_SPE" 1799 "evmwumian %0,%1,%2" 1800 [(set_attr "type" "veccomplex") 1801 (set_attr "length" "4")]) 1802 1803(define_insn "spe_evmwumia" 1804 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1805 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1806 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663)) 1807 (clobber (reg:V2SI SPE_ACC_REGNO))] 1808 "TARGET_SPE" 1809 "evmwumia %0,%1,%2" 1810 [(set_attr "type" "veccomplex") 1811 (set_attr "length" "4")]) 1812 1813(define_insn "spe_evmwumi" 1814 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1815 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1816 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))] 1817 "TARGET_SPE" 1818 "evmwumi %0,%1,%2" 1819 [(set_attr "type" "veccomplex") 1820 (set_attr "length" "4")]) 1821 1822(define_insn "spe_evaddw" 1823 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1824 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 1825 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 1826 "TARGET_SPE" 1827 "evaddw %0,%1,%2" 1828 [(set_attr "type" "veccomplex") 1829 (set_attr "length" "4")]) 1830 1831(define_insn "spe_evaddusiaaw" 1832 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1833 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1834 (reg:V2SI SPE_ACC_REGNO)] 673)) 1835 (clobber (reg:SI SPEFSCR_REGNO)) 1836 (clobber (reg:V2SI SPE_ACC_REGNO))] 1837 "TARGET_SPE" 1838 "evaddusiaaw %0,%1" 1839 [(set_attr "type" "veccomplex") 1840 (set_attr "length" "4")]) 1841 1842(define_insn "spe_evaddumiaaw" 1843 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1844 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1845 (reg:V2SI SPE_ACC_REGNO)] 674)) 1846 (clobber (reg:V2SI SPE_ACC_REGNO))] 1847 "TARGET_SPE" 1848 "evaddumiaaw %0,%1" 1849 [(set_attr "type" "veccomplex") 1850 (set_attr "length" "4")]) 1851 1852(define_insn "spe_evaddssiaaw" 1853 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1854 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1855 (reg:V2SI SPE_ACC_REGNO)] 675)) 1856 (clobber (reg:SI SPEFSCR_REGNO)) 1857 (clobber (reg:V2SI SPE_ACC_REGNO))] 1858 "TARGET_SPE" 1859 "evaddssiaaw %0,%1" 1860 [(set_attr "type" "veccomplex") 1861 (set_attr "length" "4")]) 1862 1863(define_insn "spe_evaddsmiaaw" 1864 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1865 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1866 (reg:V2SI SPE_ACC_REGNO)] 676)) 1867 (clobber (reg:V2SI SPE_ACC_REGNO))] 1868 "TARGET_SPE" 1869 "evaddsmiaaw %0,%1" 1870 [(set_attr "type" "veccomplex") 1871 (set_attr "length" "4")]) 1872 1873(define_insn "spe_evaddiw" 1874 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1875 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1876 (match_operand:QI 2 "immediate_operand" "i")] 677))] 1877 "TARGET_SPE" 1878 "evaddiw %0,%1,%2" 1879 [(set_attr "type" "veccomplex") 1880 (set_attr "length" "4")]) 1881 1882(define_insn "spe_evsubifw" 1883 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1884 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1885 (match_operand:QI 2 "immediate_operand" "i")] 678))] 1886 "TARGET_SPE" 1887 "evsubifw %0,%2,%1" 1888 [(set_attr "type" "veccomplex") 1889 (set_attr "length" "4")]) 1890 1891(define_insn "spe_evsubfw" 1892 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1893 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 1894 (match_operand:V2SI 2 "gpc_reg_operand" "r")))] 1895 "TARGET_SPE" 1896 "evsubfw %0,%1,%2" 1897 [(set_attr "type" "veccomplex") 1898 (set_attr "length" "4")]) 1899 1900(define_insn "spe_evsubfusiaaw" 1901 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1902 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1903 (reg:V2SI SPE_ACC_REGNO)] 679)) 1904 (clobber (reg:SI SPEFSCR_REGNO)) 1905 (clobber (reg:V2SI SPE_ACC_REGNO))] 1906 "TARGET_SPE" 1907 "evsubfusiaaw %0,%1" 1908 [(set_attr "type" "veccomplex") 1909 (set_attr "length" "4")]) 1910 1911(define_insn "spe_evsubfumiaaw" 1912 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1913 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1914 (reg:V2SI SPE_ACC_REGNO)] 680)) 1915 (clobber (reg:V2SI SPE_ACC_REGNO))] 1916 "TARGET_SPE" 1917 "evsubfumiaaw %0,%1" 1918 [(set_attr "type" "veccomplex") 1919 (set_attr "length" "4")]) 1920 1921(define_insn "spe_evsubfssiaaw" 1922 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1923 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1924 (reg:V2SI SPE_ACC_REGNO)] 681)) 1925 (clobber (reg:SI SPEFSCR_REGNO)) 1926 (clobber (reg:V2SI SPE_ACC_REGNO))] 1927 "TARGET_SPE" 1928 "evsubfssiaaw %0,%1" 1929 [(set_attr "type" "veccomplex") 1930 (set_attr "length" "4")]) 1931 1932(define_insn "spe_evsubfsmiaaw" 1933 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1934 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 1935 (reg:V2SI SPE_ACC_REGNO)] 682)) 1936 (clobber (reg:V2SI SPE_ACC_REGNO))] 1937 "TARGET_SPE" 1938 "evsubfsmiaaw %0,%1" 1939 [(set_attr "type" "veccomplex") 1940 (set_attr "length" "4")]) 1941 1942(define_insn "spe_evmra" 1943 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1944 (match_operand:V2SI 1 "gpc_reg_operand" "r")) 1945 (set (reg:V2SI SPE_ACC_REGNO) 1946 (unspec:V2SI [(match_dup 1)] 726))] 1947 "TARGET_SPE" 1948 "evmra %0,%1" 1949 [(set_attr "type" "veccomplex") 1950 (set_attr "length" "4")]) 1951 1952(define_insn "spe_evdivws" 1953 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1954 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 1955 (match_operand:V2SI 2 "gpc_reg_operand" "r"))) 1956 (clobber (reg:SI SPEFSCR_REGNO))] 1957 "TARGET_SPE" 1958 "evdivws %0,%1,%2" 1959 [(set_attr "type" "veccomplex") 1960 (set_attr "length" "4")]) 1961 1962(define_insn "spe_evdivwu" 1963 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1964 (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") 1965 (match_operand:V2SI 2 "gpc_reg_operand" "r"))) 1966 (clobber (reg:SI SPEFSCR_REGNO))] 1967 "TARGET_SPE" 1968 "evdivwu %0,%1,%2" 1969 [(set_attr "type" "veccomplex") 1970 (set_attr "length" "4")]) 1971 1972(define_insn "spe_evsplatfi" 1973 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1974 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))] 1975 "TARGET_SPE" 1976 "evsplatfi %0,%1" 1977 [(set_attr "type" "vecperm") 1978 (set_attr "length" "4")]) 1979 1980(define_insn "spe_evsplati" 1981 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 1982 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))] 1983 "TARGET_SPE" 1984 "evsplati %0,%1" 1985 [(set_attr "type" "vecperm") 1986 (set_attr "length" "4")]) 1987 1988(define_insn "spe_evstdd" 1989 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 1990 (match_operand:QI 1 "immediate_operand" "i"))) 1991 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 1992 (unspec [(const_int 0)] 686)] 1993 "TARGET_SPE" 1994 "evstdd %2,%0,%1" 1995 [(set_attr "type" "vecstore") 1996 (set_attr "length" "4")]) 1997 1998(define_insn "spe_evstddx" 1999 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2000 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2001 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2002 (unspec [(const_int 0)] 687)] 2003 "TARGET_SPE" 2004 "evstddx %2,%0,%1" 2005 [(set_attr "type" "vecstore") 2006 (set_attr "length" "4")]) 2007 2008(define_insn "spe_evstdh" 2009 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2010 (match_operand:QI 1 "immediate_operand" "i"))) 2011 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2012 (unspec [(const_int 0)] 688)] 2013 "TARGET_SPE" 2014 "evstdh %2,%0,%1" 2015 [(set_attr "type" "vecstore") 2016 (set_attr "length" "4")]) 2017 2018(define_insn "spe_evstdhx" 2019 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2020 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2021 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2022 (unspec [(const_int 0)] 689)] 2023 "TARGET_SPE" 2024 "evstdhx %2,%0,%1" 2025 [(set_attr "type" "vecstore") 2026 (set_attr "length" "4")]) 2027 2028(define_insn "spe_evstdw" 2029 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2030 (match_operand:QI 1 "immediate_operand" "i"))) 2031 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2032 (unspec [(const_int 0)] 690)] 2033 "TARGET_SPE" 2034 "evstdw %2,%0,%1" 2035 [(set_attr "type" "vecstore") 2036 (set_attr "length" "4")]) 2037 2038(define_insn "spe_evstdwx" 2039 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2040 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2041 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2042 (unspec [(const_int 0)] 691)] 2043 "TARGET_SPE" 2044 "evstdwx %2,%0,%1" 2045 [(set_attr "type" "vecstore") 2046 (set_attr "length" "4")]) 2047 2048(define_insn "spe_evstwhe" 2049 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2050 (match_operand:QI 1 "immediate_operand" "i"))) 2051 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2052 (unspec [(const_int 0)] 692)] 2053 "TARGET_SPE" 2054 "evstwhe %2,%0,%1" 2055 [(set_attr "type" "vecstore") 2056 (set_attr "length" "4")]) 2057 2058(define_insn "spe_evstwhex" 2059 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2060 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2061 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2062 (unspec [(const_int 0)] 693)] 2063 "TARGET_SPE" 2064 "evstwhex %2,%0,%1" 2065 [(set_attr "type" "vecstore") 2066 (set_attr "length" "4")]) 2067 2068(define_insn "spe_evstwho" 2069 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2070 (match_operand:QI 1 "immediate_operand" "i"))) 2071 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2072 (unspec [(const_int 0)] 694)] 2073 "TARGET_SPE" 2074 "evstwho %2,%0,%1" 2075 [(set_attr "type" "vecstore") 2076 (set_attr "length" "4")]) 2077 2078(define_insn "spe_evstwhox" 2079 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2080 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2081 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2082 (unspec [(const_int 0)] 695)] 2083 "TARGET_SPE" 2084 "evstwhox %2,%0,%1" 2085 [(set_attr "type" "vecstore") 2086 (set_attr "length" "4")]) 2087 2088(define_insn "spe_evstwwe" 2089 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2090 (match_operand:QI 1 "immediate_operand" "i"))) 2091 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2092 (unspec [(const_int 0)] 696)] 2093 "TARGET_SPE" 2094 "evstwwe %2,%0,%1" 2095 [(set_attr "type" "vecstore") 2096 (set_attr "length" "4")]) 2097 2098(define_insn "spe_evstwwex" 2099 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2100 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2101 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2102 (unspec [(const_int 0)] 697)] 2103 "TARGET_SPE" 2104 "evstwwex %2,%0,%1" 2105 [(set_attr "type" "vecstore") 2106 (set_attr "length" "4")]) 2107 2108(define_insn "spe_evstwwo" 2109 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2110 (match_operand:QI 1 "immediate_operand" "i"))) 2111 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2112 (unspec [(const_int 0)] 698)] 2113 "TARGET_SPE" 2114 "evstwwo %2,%0,%1" 2115 [(set_attr "type" "vecstore") 2116 (set_attr "length" "4")]) 2117 2118(define_insn "spe_evstwwox" 2119 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") 2120 (match_operand:SI 1 "gpc_reg_operand" "r"))) 2121 (match_operand:V2SI 2 "gpc_reg_operand" "r")) 2122 (unspec [(const_int 0)] 699)] 2123 "TARGET_SPE" 2124 "evstwwox %2,%0,%1" 2125 [(set_attr "type" "vecstore") 2126 (set_attr "length" "4")]) 2127 2128;; SPE vector clears 2129 2130(define_insn "*movv2si_const0" 2131 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2132 (match_operand:V2SI 1 "zero_constant" ""))] 2133 "TARGET_SPE" 2134 "evxor %0,%0,%0" 2135 [(set_attr "type" "vecsimple")]) 2136 2137(define_insn "*movv2sf_const0" 2138 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") 2139 (match_operand:V2SF 1 "zero_constant" ""))] 2140 "TARGET_SPE" 2141 "evxor %0,%0,%0" 2142 [(set_attr "type" "vecsimple")]) 2143 2144(define_insn "*movv4hi_const0" 2145 [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r") 2146 (match_operand:V4HI 1 "zero_constant" ""))] 2147 "TARGET_SPE" 2148 "evxor %0,%0,%0" 2149 [(set_attr "type" "vecsimple")]) 2150 2151(define_insn "*movv1di_const0" 2152 [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r") 2153 (match_operand:V1DI 1 "zero_constant" ""))] 2154 "TARGET_SPE" 2155 "evxor %0,%0,%0" 2156 [(set_attr "type" "vecsimple")]) 2157 2158;; Vector move instructions. 2159 2160(define_expand "movv2si" 2161 [(set (match_operand:V2SI 0 "nonimmediate_operand" "") 2162 (match_operand:V2SI 1 "any_operand" ""))] 2163 "TARGET_SPE" 2164 "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }") 2165 2166 2167(define_insn "*movv2si_internal" 2168 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r") 2169 (match_operand:V2SI 1 "input_operand" "r,m,r"))] 2170 "TARGET_SPE" 2171 "@ 2172 evstdd%X0 %1,%y0 2173 evldd%X1 %0,%y1 2174 evor %0,%1,%1" 2175 [(set_attr "type" "vecload")]) 2176 2177(define_expand "movv1di" 2178 [(set (match_operand:V1DI 0 "nonimmediate_operand" "") 2179 (match_operand:V1DI 1 "any_operand" ""))] 2180 "TARGET_SPE" 2181 "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }") 2182 2183(define_insn "*movv1di_internal" 2184 [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r") 2185 (match_operand:V1DI 1 "input_operand" "r,m,r"))] 2186 "TARGET_SPE" 2187 "@ 2188 evstdd%X0 %1,%y0 2189 evldd%X1 %0,%y1 2190 evor %0,%1,%1" 2191 [(set_attr "type" "vecload")]) 2192 2193(define_expand "movv4hi" 2194 [(set (match_operand:V4HI 0 "nonimmediate_operand" "") 2195 (match_operand:V4HI 1 "any_operand" ""))] 2196 "TARGET_SPE" 2197 "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }") 2198 2199(define_insn "*movv4hi_internal" 2200 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r") 2201 (match_operand:V4HI 1 "input_operand" "r,m,r"))] 2202 "TARGET_SPE" 2203 "@ 2204 evstdd%X0 %1,%y0 2205 evldd%X1 %0,%y1 2206 evor %0,%1,%1" 2207 [(set_attr "type" "vecload")]) 2208 2209(define_expand "movv2sf" 2210 [(set (match_operand:V2SF 0 "nonimmediate_operand" "") 2211 (match_operand:V2SF 1 "any_operand" ""))] 2212 "TARGET_SPE" 2213 "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }") 2214 2215(define_insn "*movv2sf_internal" 2216 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r") 2217 (match_operand:V2SF 1 "input_operand" "r,m,r"))] 2218 "TARGET_SPE" 2219 "@ 2220 evstdd%X0 %1,%y0 2221 evldd%X1 %0,%y1 2222 evor %0,%1,%1" 2223 [(set_attr "type" "vecload")]) 2224 2225(define_insn "spe_evmwhssfaa" 2226 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2227 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2228 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702)) 2229 (clobber (reg:SI SPEFSCR_REGNO)) 2230 (clobber (reg:V2SI SPE_ACC_REGNO))] 2231 "TARGET_SPE" 2232 "evmwhssfaa %0,%1,%2" 2233 [(set_attr "type" "veccomplex") 2234 (set_attr "length" "4")]) 2235 2236(define_insn "spe_evmwhssmaa" 2237 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2238 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2239 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703)) 2240 (clobber (reg:SI SPEFSCR_REGNO)) 2241 (clobber (reg:V2SI SPE_ACC_REGNO))] 2242 "TARGET_SPE" 2243 "evmwhssmaa %0,%1,%2" 2244 [(set_attr "type" "veccomplex") 2245 (set_attr "length" "4")]) 2246 2247(define_insn "spe_evmwhsmfaa" 2248 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2249 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2250 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704)) 2251 (clobber (reg:V2SI SPE_ACC_REGNO))] 2252 "TARGET_SPE" 2253 "evmwhsmfaa %0,%1,%2" 2254 [(set_attr "type" "veccomplex") 2255 (set_attr "length" "4")]) 2256 2257(define_insn "spe_evmwhsmiaa" 2258 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2259 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2260 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705)) 2261 (clobber (reg:V2SI SPE_ACC_REGNO))] 2262 "TARGET_SPE" 2263 "evmwhsmiaa %0,%1,%2" 2264 [(set_attr "type" "veccomplex") 2265 (set_attr "length" "4")]) 2266 2267(define_insn "spe_evmwhusiaa" 2268 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2269 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2270 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706)) 2271 (clobber (reg:SI SPEFSCR_REGNO)) 2272 (clobber (reg:V2SI SPE_ACC_REGNO))] 2273 "TARGET_SPE" 2274 "evmwhusiaa %0,%1,%2" 2275 [(set_attr "type" "veccomplex") 2276 (set_attr "length" "4")]) 2277 2278(define_insn "spe_evmwhumiaa" 2279 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2280 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2281 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707)) 2282 (clobber (reg:V2SI SPE_ACC_REGNO))] 2283 "TARGET_SPE" 2284 "evmwhumiaa %0,%1,%2" 2285 [(set_attr "type" "veccomplex") 2286 (set_attr "length" "4")]) 2287 2288(define_insn "spe_evmwhssfan" 2289 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2290 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2291 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708)) 2292 (clobber (reg:SI SPEFSCR_REGNO)) 2293 (clobber (reg:V2SI SPE_ACC_REGNO))] 2294 "TARGET_SPE" 2295 "evmwhssfan %0,%1,%2" 2296 [(set_attr "type" "veccomplex") 2297 (set_attr "length" "4")]) 2298 2299(define_insn "spe_evmwhssian" 2300 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2301 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2302 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709)) 2303 (clobber (reg:SI SPEFSCR_REGNO)) 2304 (clobber (reg:V2SI SPE_ACC_REGNO))] 2305 "TARGET_SPE" 2306 "evmwhssian %0,%1,%2" 2307 [(set_attr "type" "veccomplex") 2308 (set_attr "length" "4")]) 2309 2310(define_insn "spe_evmwhsmfan" 2311 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2312 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2313 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710)) 2314 (clobber (reg:V2SI SPE_ACC_REGNO))] 2315 "TARGET_SPE" 2316 "evmwhsmfan %0,%1,%2" 2317 [(set_attr "type" "veccomplex") 2318 (set_attr "length" "4")]) 2319 2320(define_insn "spe_evmwhsmian" 2321 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2322 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2323 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711)) 2324 (clobber (reg:V2SI SPE_ACC_REGNO))] 2325 "TARGET_SPE" 2326 "evmwhsmian %0,%1,%2" 2327 [(set_attr "type" "veccomplex") 2328 (set_attr "length" "4")]) 2329 2330(define_insn "spe_evmwhumian" 2331 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2332 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2333 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713)) 2334 (clobber (reg:V2SI SPE_ACC_REGNO))] 2335 "TARGET_SPE" 2336 "evmwhumian %0,%1,%2" 2337 [(set_attr "type" "veccomplex") 2338 (set_attr "length" "4")]) 2339 2340(define_insn "spe_evmwhgssfaa" 2341 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2342 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2343 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714)) 2344 (clobber (reg:SI SPEFSCR_REGNO)) 2345 (clobber (reg:V2SI SPE_ACC_REGNO))] 2346 "TARGET_SPE" 2347 "evmwhgssfaa %0,%1,%2" 2348 [(set_attr "type" "veccomplex") 2349 (set_attr "length" "4")]) 2350 2351(define_insn "spe_evmwhgsmfaa" 2352 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2353 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2354 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715)) 2355 (clobber (reg:V2SI SPE_ACC_REGNO))] 2356 "TARGET_SPE" 2357 "evmwhgsmfaa %0,%1,%2" 2358 [(set_attr "type" "veccomplex") 2359 (set_attr "length" "4")]) 2360 2361(define_insn "spe_evmwhgsmiaa" 2362 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2363 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2364 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716)) 2365 (clobber (reg:V2SI SPE_ACC_REGNO))] 2366 "TARGET_SPE" 2367 "evmwhgsmiaa %0,%1,%2" 2368 [(set_attr "type" "veccomplex") 2369 (set_attr "length" "4")]) 2370 2371(define_insn "spe_evmwhgumiaa" 2372 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2373 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2374 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717)) 2375 (clobber (reg:V2SI SPE_ACC_REGNO))] 2376 "TARGET_SPE" 2377 "evmwhgumiaa %0,%1,%2" 2378 [(set_attr "type" "veccomplex") 2379 (set_attr "length" "4")]) 2380 2381(define_insn "spe_evmwhgssfan" 2382 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2383 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2384 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718)) 2385 (clobber (reg:SI SPEFSCR_REGNO)) 2386 (clobber (reg:V2SI SPE_ACC_REGNO))] 2387 "TARGET_SPE" 2388 "evmwhgssfan %0,%1,%2" 2389 [(set_attr "type" "veccomplex") 2390 (set_attr "length" "4")]) 2391 2392(define_insn "spe_evmwhgsmfan" 2393 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2394 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2395 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719)) 2396 (clobber (reg:V2SI SPE_ACC_REGNO))] 2397 "TARGET_SPE" 2398 "evmwhgsmfan %0,%1,%2" 2399 [(set_attr "type" "veccomplex") 2400 (set_attr "length" "4")]) 2401 2402(define_insn "spe_evmwhgsmian" 2403 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2404 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2405 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720)) 2406 (clobber (reg:V2SI SPE_ACC_REGNO))] 2407 "TARGET_SPE" 2408 "evmwhgsmian %0,%1,%2" 2409 [(set_attr "type" "veccomplex") 2410 (set_attr "length" "4")]) 2411 2412(define_insn "spe_evmwhgumian" 2413 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") 2414 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") 2415 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721)) 2416 (clobber (reg:V2SI SPE_ACC_REGNO))] 2417 "TARGET_SPE" 2418 "evmwhgumian %0,%1,%2" 2419 [(set_attr "type" "veccomplex") 2420 (set_attr "length" "4")]) 2421 2422(define_insn "spe_mtspefscr" 2423 [(set (reg:SI SPEFSCR_REGNO) 2424 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] 2425 722))] 2426 "TARGET_SPE" 2427 "mtspefscr %0" 2428 [(set_attr "type" "vecsimple")]) 2429 2430(define_insn "spe_mfspefscr" 2431 [(set (match_operand:SI 0 "register_operand" "=r") 2432 (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))] 2433 "TARGET_SPE" 2434 "mfspefscr %0" 2435 [(set_attr "type" "vecsimple")]) 2436 2437;; MPC8540 single-precision FP instructions on GPRs. 2438;; We have 2 variants for each. One for IEEE compliant math and one 2439;; for non IEEE compliant math. 2440 2441(define_insn "cmpsfeq_gpr" 2442 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2443 (eq:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2444 (match_operand:SF 2 "gpc_reg_operand" "r")))] 2445 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" 2446 "efscmpeq %0,%1,%2" 2447 [(set_attr "type" "fpcompare")]) 2448 2449(define_insn "tstsfeq_gpr" 2450 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2451 (eq:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2452 (match_operand:SF 2 "gpc_reg_operand" "r")))] 2453 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" 2454 "efststeq %0,%1,%2" 2455 [(set_attr "type" "fpcompare")]) 2456 2457(define_insn "cmpsfgt_gpr" 2458 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2459 (gt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2460 (match_operand:SF 2 "gpc_reg_operand" "r")))] 2461 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" 2462 "efscmpgt %0,%1,%2" 2463 [(set_attr "type" "fpcompare")]) 2464 2465(define_insn "tstsfgt_gpr" 2466 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2467 (gt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2468 (match_operand:SF 2 "gpc_reg_operand" "r")))] 2469 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" 2470 "efststgt %0,%1,%2" 2471 [(set_attr "type" "fpcompare")]) 2472 2473(define_insn "cmpsflt_gpr" 2474 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2475 (lt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2476 (match_operand:SF 2 "gpc_reg_operand" "r")))] 2477 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" 2478 "efscmplt %0,%1,%2" 2479 [(set_attr "type" "fpcompare")]) 2480 2481(define_insn "tstsflt_gpr" 2482 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 2483 (lt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") 2484 (match_operand:SF 2 "gpc_reg_operand" "r")))] 2485 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" 2486 "efststlt %0,%1,%2" 2487 [(set_attr "type" "fpcompare")]) 2488 2489