rs6000.md revision 169689
1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 4;; Free Software Foundation, Inc. 5;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 6 7;; This file is part of GCC. 8 9;; GCC is free software; you can redistribute it and/or modify it 10;; under the terms of the GNU General Public License as published 11;; by the Free Software Foundation; either version 2, or (at your 12;; option) any later version. 13 14;; GCC is distributed in the hope that it will be useful, but WITHOUT 15;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17;; License for more details. 18 19;; You should have received a copy of the GNU General Public License 20;; along with GCC; see the file COPYING. If not, write to the 21;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 22;; MA 02110-1301, USA. 23 24;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 25 26;; 27;; UNSPEC usage 28;; 29 30(define_constants 31 [(UNSPEC_FRSP 0) ; frsp for POWER machines 32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer 33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC 34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less) 35 (UNSPEC_MOVSI_GOT 8) 36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit 37 (UNSPEC_FCTIWZ 10) 38 (UNSPEC_FRIM 11) 39 (UNSPEC_FRIN 12) 40 (UNSPEC_FRIP 13) 41 (UNSPEC_FRIZ 14) 42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase 43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic 44 (UNSPEC_TLSGD 17) 45 (UNSPEC_TLSLD 18) 46 (UNSPEC_MOVESI_FROM_CR 19) 47 (UNSPEC_MOVESI_TO_CR 20) 48 (UNSPEC_TLSDTPREL 21) 49 (UNSPEC_TLSDTPRELHA 22) 50 (UNSPEC_TLSDTPRELLO 23) 51 (UNSPEC_TLSGOTDTPREL 24) 52 (UNSPEC_TLSTPREL 25) 53 (UNSPEC_TLSTPRELHA 26) 54 (UNSPEC_TLSTPRELLO 27) 55 (UNSPEC_TLSGOTTPREL 28) 56 (UNSPEC_TLSTLS 29) 57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero 58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit 59 (UNSPEC_STFIWX 32) 60 (UNSPEC_POPCNTB 33) 61 (UNSPEC_FRES 34) 62 (UNSPEC_SP_SET 35) 63 (UNSPEC_SP_TEST 36) 64 (UNSPEC_SYNC 37) 65 (UNSPEC_LWSYNC 38) 66 (UNSPEC_ISYNC 39) 67 (UNSPEC_SYNC_OP 40) 68 (UNSPEC_ATOMIC 41) 69 (UNSPEC_CMPXCHG 42) 70 (UNSPEC_XCHG 43) 71 (UNSPEC_AND 44) 72 (UNSPEC_DLMZB 45) 73 (UNSPEC_DLMZB_CR 46) 74 (UNSPEC_DLMZB_STRLEN 47) 75 ]) 76 77;; 78;; UNSPEC_VOLATILE usage 79;; 80 81(define_constants 82 [(UNSPECV_BLOCK 0) 83 (UNSPECV_LL 1) ; load-locked 84 (UNSPECV_SC 2) ; store-conditional 85 (UNSPECV_EH_RR 9) ; eh_reg_restore 86 ]) 87 88;; Define an insn type attribute. This is used in function unit delay 89;; computations. 90(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c" 91 (const_string "integer")) 92 93;; Length (in bytes). 94; '(pc)' in the following doesn't include the instruction itself; it is 95; calculated as if the instruction had zero size. 96(define_attr "length" "" 97 (if_then_else (eq_attr "type" "branch") 98 (if_then_else (and (ge (minus (match_dup 0) (pc)) 99 (const_int -32768)) 100 (lt (minus (match_dup 0) (pc)) 101 (const_int 32764))) 102 (const_int 4) 103 (const_int 8)) 104 (const_int 4))) 105 106;; Processor type -- this attribute must exactly match the processor_type 107;; enumeration in rs6000.h. 108 109(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" 110 (const (symbol_ref "rs6000_cpu_attr"))) 111 112(automata_option "ndfa") 113 114(include "rios1.md") 115(include "rios2.md") 116(include "rs64.md") 117(include "mpc.md") 118(include "40x.md") 119(include "440.md") 120(include "603.md") 121(include "6xx.md") 122(include "7xx.md") 123(include "7450.md") 124(include "8540.md") 125(include "power4.md") 126(include "power5.md") 127 128(include "predicates.md") 129(include "constraints.md") 130 131(include "darwin.md") 132 133 134;; Mode macros 135 136; This mode macro allows :GPR to be used to indicate the allowable size 137; of whole values in GPRs. 138(define_mode_macro GPR [SI (DI "TARGET_POWERPC64")]) 139 140; Any supported integer mode. 141(define_mode_macro INT [QI HI SI DI TI]) 142 143; Any supported integer mode that fits in one register. 144(define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")]) 145 146; extend modes for DImode 147(define_mode_macro QHSI [QI HI SI]) 148 149; SImode or DImode, even if DImode doesn't fit in GPRs. 150(define_mode_macro SDI [SI DI]) 151 152; The size of a pointer. Also, the size of the value that a record-condition 153; (one with a '.') will compare. 154(define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) 155 156; Any hardware-supported floating-point mode 157(define_mode_macro FP [(SF "TARGET_HARD_FLOAT") 158 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)") 159 (TF "!TARGET_IEEEQUAD 160 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")]) 161 162; Various instructions that come in SI and DI forms. 163; A generic w/d attribute, for things like cmpw/cmpd. 164(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")]) 165 166; DImode bits 167(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) 168 169 170;; Start with fixed-point load and store insns. Here we put only the more 171;; complex forms. Basic data transfer is done later. 172 173(define_expand "zero_extend<mode>di2" 174 [(set (match_operand:DI 0 "gpc_reg_operand" "") 175 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))] 176 "TARGET_POWERPC64" 177 "") 178 179(define_insn "*zero_extend<mode>di2_internal1" 180 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 181 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))] 182 "TARGET_POWERPC64" 183 "@ 184 l<wd>z%U1%X1 %0,%1 185 rldicl %0,%1,0,<dbits>" 186 [(set_attr "type" "load,*")]) 187 188(define_insn "*zero_extend<mode>di2_internal2" 189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 190 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) 191 (const_int 0))) 192 (clobber (match_scratch:DI 2 "=r,r"))] 193 "TARGET_64BIT" 194 "@ 195 rldicl. %2,%1,0,<dbits> 196 #" 197 [(set_attr "type" "compare") 198 (set_attr "length" "4,8")]) 199 200(define_split 201 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 202 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) 203 (const_int 0))) 204 (clobber (match_scratch:DI 2 ""))] 205 "TARGET_POWERPC64 && reload_completed" 206 [(set (match_dup 2) 207 (zero_extend:DI (match_dup 1))) 208 (set (match_dup 0) 209 (compare:CC (match_dup 2) 210 (const_int 0)))] 211 "") 212 213(define_insn "*zero_extend<mode>di2_internal3" 214 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 215 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) 216 (const_int 0))) 217 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 218 (zero_extend:DI (match_dup 1)))] 219 "TARGET_64BIT" 220 "@ 221 rldicl. %0,%1,0,<dbits> 222 #" 223 [(set_attr "type" "compare") 224 (set_attr "length" "4,8")]) 225 226(define_split 227 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 228 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) 229 (const_int 0))) 230 (set (match_operand:DI 0 "gpc_reg_operand" "") 231 (zero_extend:DI (match_dup 1)))] 232 "TARGET_POWERPC64 && reload_completed" 233 [(set (match_dup 0) 234 (zero_extend:DI (match_dup 1))) 235 (set (match_dup 2) 236 (compare:CC (match_dup 0) 237 (const_int 0)))] 238 "") 239 240(define_insn "extendqidi2" 241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 242 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] 243 "TARGET_POWERPC64" 244 "extsb %0,%1") 245 246(define_insn "" 247 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 248 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 249 (const_int 0))) 250 (clobber (match_scratch:DI 2 "=r,r"))] 251 "TARGET_64BIT" 252 "@ 253 extsb. %2,%1 254 #" 255 [(set_attr "type" "compare") 256 (set_attr "length" "4,8")]) 257 258(define_split 259 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 260 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 261 (const_int 0))) 262 (clobber (match_scratch:DI 2 ""))] 263 "TARGET_POWERPC64 && reload_completed" 264 [(set (match_dup 2) 265 (sign_extend:DI (match_dup 1))) 266 (set (match_dup 0) 267 (compare:CC (match_dup 2) 268 (const_int 0)))] 269 "") 270 271(define_insn "" 272 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 273 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 274 (const_int 0))) 275 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 276 (sign_extend:DI (match_dup 1)))] 277 "TARGET_64BIT" 278 "@ 279 extsb. %0,%1 280 #" 281 [(set_attr "type" "compare") 282 (set_attr "length" "4,8")]) 283 284(define_split 285 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 286 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 287 (const_int 0))) 288 (set (match_operand:DI 0 "gpc_reg_operand" "") 289 (sign_extend:DI (match_dup 1)))] 290 "TARGET_POWERPC64 && reload_completed" 291 [(set (match_dup 0) 292 (sign_extend:DI (match_dup 1))) 293 (set (match_dup 2) 294 (compare:CC (match_dup 0) 295 (const_int 0)))] 296 "") 297 298(define_expand "extendhidi2" 299 [(set (match_operand:DI 0 "gpc_reg_operand" "") 300 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 301 "TARGET_POWERPC64" 302 "") 303 304(define_insn "" 305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 306 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 307 "TARGET_POWERPC64" 308 "@ 309 lha%U1%X1 %0,%1 310 extsh %0,%1" 311 [(set_attr "type" "load_ext,*")]) 312 313(define_insn "" 314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 315 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 316 (const_int 0))) 317 (clobber (match_scratch:DI 2 "=r,r"))] 318 "TARGET_64BIT" 319 "@ 320 extsh. %2,%1 321 #" 322 [(set_attr "type" "compare") 323 (set_attr "length" "4,8")]) 324 325(define_split 326 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 327 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 328 (const_int 0))) 329 (clobber (match_scratch:DI 2 ""))] 330 "TARGET_POWERPC64 && reload_completed" 331 [(set (match_dup 2) 332 (sign_extend:DI (match_dup 1))) 333 (set (match_dup 0) 334 (compare:CC (match_dup 2) 335 (const_int 0)))] 336 "") 337 338(define_insn "" 339 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 340 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 341 (const_int 0))) 342 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 343 (sign_extend:DI (match_dup 1)))] 344 "TARGET_64BIT" 345 "@ 346 extsh. %0,%1 347 #" 348 [(set_attr "type" "compare") 349 (set_attr "length" "4,8")]) 350 351(define_split 352 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 353 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 354 (const_int 0))) 355 (set (match_operand:DI 0 "gpc_reg_operand" "") 356 (sign_extend:DI (match_dup 1)))] 357 "TARGET_POWERPC64 && reload_completed" 358 [(set (match_dup 0) 359 (sign_extend:DI (match_dup 1))) 360 (set (match_dup 2) 361 (compare:CC (match_dup 0) 362 (const_int 0)))] 363 "") 364 365(define_expand "extendsidi2" 366 [(set (match_operand:DI 0 "gpc_reg_operand" "") 367 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 368 "TARGET_POWERPC64" 369 "") 370 371(define_insn "" 372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 373 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] 374 "TARGET_POWERPC64" 375 "@ 376 lwa%U1%X1 %0,%1 377 extsw %0,%1" 378 [(set_attr "type" "load_ext,*")]) 379 380(define_insn "" 381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 382 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 383 (const_int 0))) 384 (clobber (match_scratch:DI 2 "=r,r"))] 385 "TARGET_64BIT" 386 "@ 387 extsw. %2,%1 388 #" 389 [(set_attr "type" "compare") 390 (set_attr "length" "4,8")]) 391 392(define_split 393 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 394 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 395 (const_int 0))) 396 (clobber (match_scratch:DI 2 ""))] 397 "TARGET_POWERPC64 && reload_completed" 398 [(set (match_dup 2) 399 (sign_extend:DI (match_dup 1))) 400 (set (match_dup 0) 401 (compare:CC (match_dup 2) 402 (const_int 0)))] 403 "") 404 405(define_insn "" 406 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 407 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 408 (const_int 0))) 409 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 410 (sign_extend:DI (match_dup 1)))] 411 "TARGET_64BIT" 412 "@ 413 extsw. %0,%1 414 #" 415 [(set_attr "type" "compare") 416 (set_attr "length" "4,8")]) 417 418(define_split 419 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 420 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 421 (const_int 0))) 422 (set (match_operand:DI 0 "gpc_reg_operand" "") 423 (sign_extend:DI (match_dup 1)))] 424 "TARGET_POWERPC64 && reload_completed" 425 [(set (match_dup 0) 426 (sign_extend:DI (match_dup 1))) 427 (set (match_dup 2) 428 (compare:CC (match_dup 0) 429 (const_int 0)))] 430 "") 431 432(define_expand "zero_extendqisi2" 433 [(set (match_operand:SI 0 "gpc_reg_operand" "") 434 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] 435 "" 436 "") 437 438(define_insn "" 439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 440 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 441 "" 442 "@ 443 lbz%U1%X1 %0,%1 444 {rlinm|rlwinm} %0,%1,0,0xff" 445 [(set_attr "type" "load,*")]) 446 447(define_insn "" 448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 449 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 450 (const_int 0))) 451 (clobber (match_scratch:SI 2 "=r,r"))] 452 "" 453 "@ 454 {andil.|andi.} %2,%1,0xff 455 #" 456 [(set_attr "type" "compare") 457 (set_attr "length" "4,8")]) 458 459(define_split 460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 461 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 462 (const_int 0))) 463 (clobber (match_scratch:SI 2 ""))] 464 "reload_completed" 465 [(set (match_dup 2) 466 (zero_extend:SI (match_dup 1))) 467 (set (match_dup 0) 468 (compare:CC (match_dup 2) 469 (const_int 0)))] 470 "") 471 472(define_insn "" 473 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 474 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 475 (const_int 0))) 476 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 477 (zero_extend:SI (match_dup 1)))] 478 "" 479 "@ 480 {andil.|andi.} %0,%1,0xff 481 #" 482 [(set_attr "type" "compare") 483 (set_attr "length" "4,8")]) 484 485(define_split 486 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 487 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 488 (const_int 0))) 489 (set (match_operand:SI 0 "gpc_reg_operand" "") 490 (zero_extend:SI (match_dup 1)))] 491 "reload_completed" 492 [(set (match_dup 0) 493 (zero_extend:SI (match_dup 1))) 494 (set (match_dup 2) 495 (compare:CC (match_dup 0) 496 (const_int 0)))] 497 "") 498 499(define_expand "extendqisi2" 500 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 501 (use (match_operand:QI 1 "gpc_reg_operand" ""))] 502 "" 503 " 504{ 505 if (TARGET_POWERPC) 506 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); 507 else if (TARGET_POWER) 508 emit_insn (gen_extendqisi2_power (operands[0], operands[1])); 509 else 510 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); 511 DONE; 512}") 513 514(define_insn "extendqisi2_ppc" 515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 516 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] 517 "TARGET_POWERPC" 518 "extsb %0,%1") 519 520(define_insn "" 521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 522 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 523 (const_int 0))) 524 (clobber (match_scratch:SI 2 "=r,r"))] 525 "TARGET_POWERPC" 526 "@ 527 extsb. %2,%1 528 #" 529 [(set_attr "type" "compare") 530 (set_attr "length" "4,8")]) 531 532(define_split 533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 534 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 535 (const_int 0))) 536 (clobber (match_scratch:SI 2 ""))] 537 "TARGET_POWERPC && reload_completed" 538 [(set (match_dup 2) 539 (sign_extend:SI (match_dup 1))) 540 (set (match_dup 0) 541 (compare:CC (match_dup 2) 542 (const_int 0)))] 543 "") 544 545(define_insn "" 546 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 547 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 548 (const_int 0))) 549 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 550 (sign_extend:SI (match_dup 1)))] 551 "TARGET_POWERPC" 552 "@ 553 extsb. %0,%1 554 #" 555 [(set_attr "type" "compare") 556 (set_attr "length" "4,8")]) 557 558(define_split 559 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 560 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 561 (const_int 0))) 562 (set (match_operand:SI 0 "gpc_reg_operand" "") 563 (sign_extend:SI (match_dup 1)))] 564 "TARGET_POWERPC && reload_completed" 565 [(set (match_dup 0) 566 (sign_extend:SI (match_dup 1))) 567 (set (match_dup 2) 568 (compare:CC (match_dup 0) 569 (const_int 0)))] 570 "") 571 572(define_expand "extendqisi2_power" 573 [(parallel [(set (match_dup 2) 574 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 575 (const_int 24))) 576 (clobber (scratch:SI))]) 577 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 578 (ashiftrt:SI (match_dup 2) 579 (const_int 24))) 580 (clobber (scratch:SI))])] 581 "TARGET_POWER" 582 " 583{ operands[1] = gen_lowpart (SImode, operands[1]); 584 operands[2] = gen_reg_rtx (SImode); }") 585 586(define_expand "extendqisi2_no_power" 587 [(set (match_dup 2) 588 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 589 (const_int 24))) 590 (set (match_operand:SI 0 "gpc_reg_operand" "") 591 (ashiftrt:SI (match_dup 2) 592 (const_int 24)))] 593 "! TARGET_POWER && ! TARGET_POWERPC" 594 " 595{ operands[1] = gen_lowpart (SImode, operands[1]); 596 operands[2] = gen_reg_rtx (SImode); }") 597 598(define_expand "zero_extendqihi2" 599 [(set (match_operand:HI 0 "gpc_reg_operand" "") 600 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] 601 "" 602 "") 603 604(define_insn "" 605 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 606 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 607 "" 608 "@ 609 lbz%U1%X1 %0,%1 610 {rlinm|rlwinm} %0,%1,0,0xff" 611 [(set_attr "type" "load,*")]) 612 613(define_insn "" 614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 615 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 616 (const_int 0))) 617 (clobber (match_scratch:HI 2 "=r,r"))] 618 "" 619 "@ 620 {andil.|andi.} %2,%1,0xff 621 #" 622 [(set_attr "type" "compare") 623 (set_attr "length" "4,8")]) 624 625(define_split 626 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 627 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 628 (const_int 0))) 629 (clobber (match_scratch:HI 2 ""))] 630 "reload_completed" 631 [(set (match_dup 2) 632 (zero_extend:HI (match_dup 1))) 633 (set (match_dup 0) 634 (compare:CC (match_dup 2) 635 (const_int 0)))] 636 "") 637 638(define_insn "" 639 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 640 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 641 (const_int 0))) 642 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 643 (zero_extend:HI (match_dup 1)))] 644 "" 645 "@ 646 {andil.|andi.} %0,%1,0xff 647 #" 648 [(set_attr "type" "compare") 649 (set_attr "length" "4,8")]) 650 651(define_split 652 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 653 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 654 (const_int 0))) 655 (set (match_operand:HI 0 "gpc_reg_operand" "") 656 (zero_extend:HI (match_dup 1)))] 657 "reload_completed" 658 [(set (match_dup 0) 659 (zero_extend:HI (match_dup 1))) 660 (set (match_dup 2) 661 (compare:CC (match_dup 0) 662 (const_int 0)))] 663 "") 664 665(define_expand "extendqihi2" 666 [(use (match_operand:HI 0 "gpc_reg_operand" "")) 667 (use (match_operand:QI 1 "gpc_reg_operand" ""))] 668 "" 669 " 670{ 671 if (TARGET_POWERPC) 672 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); 673 else if (TARGET_POWER) 674 emit_insn (gen_extendqihi2_power (operands[0], operands[1])); 675 else 676 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); 677 DONE; 678}") 679 680(define_insn "extendqihi2_ppc" 681 [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 682 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] 683 "TARGET_POWERPC" 684 "extsb %0,%1") 685 686(define_insn "" 687 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 688 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 689 (const_int 0))) 690 (clobber (match_scratch:HI 2 "=r,r"))] 691 "TARGET_POWERPC" 692 "@ 693 extsb. %2,%1 694 #" 695 [(set_attr "type" "compare") 696 (set_attr "length" "4,8")]) 697 698(define_split 699 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 700 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 701 (const_int 0))) 702 (clobber (match_scratch:HI 2 ""))] 703 "TARGET_POWERPC && reload_completed" 704 [(set (match_dup 2) 705 (sign_extend:HI (match_dup 1))) 706 (set (match_dup 0) 707 (compare:CC (match_dup 2) 708 (const_int 0)))] 709 "") 710 711(define_insn "" 712 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 713 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 714 (const_int 0))) 715 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 716 (sign_extend:HI (match_dup 1)))] 717 "TARGET_POWERPC" 718 "@ 719 extsb. %0,%1 720 #" 721 [(set_attr "type" "compare") 722 (set_attr "length" "4,8")]) 723 724(define_split 725 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 726 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 727 (const_int 0))) 728 (set (match_operand:HI 0 "gpc_reg_operand" "") 729 (sign_extend:HI (match_dup 1)))] 730 "TARGET_POWERPC && reload_completed" 731 [(set (match_dup 0) 732 (sign_extend:HI (match_dup 1))) 733 (set (match_dup 2) 734 (compare:CC (match_dup 0) 735 (const_int 0)))] 736 "") 737 738(define_expand "extendqihi2_power" 739 [(parallel [(set (match_dup 2) 740 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 741 (const_int 24))) 742 (clobber (scratch:SI))]) 743 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") 744 (ashiftrt:SI (match_dup 2) 745 (const_int 24))) 746 (clobber (scratch:SI))])] 747 "TARGET_POWER" 748 " 749{ operands[0] = gen_lowpart (SImode, operands[0]); 750 operands[1] = gen_lowpart (SImode, operands[1]); 751 operands[2] = gen_reg_rtx (SImode); }") 752 753(define_expand "extendqihi2_no_power" 754 [(set (match_dup 2) 755 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 756 (const_int 24))) 757 (set (match_operand:HI 0 "gpc_reg_operand" "") 758 (ashiftrt:SI (match_dup 2) 759 (const_int 24)))] 760 "! TARGET_POWER && ! TARGET_POWERPC" 761 " 762{ operands[0] = gen_lowpart (SImode, operands[0]); 763 operands[1] = gen_lowpart (SImode, operands[1]); 764 operands[2] = gen_reg_rtx (SImode); }") 765 766(define_expand "zero_extendhisi2" 767 [(set (match_operand:SI 0 "gpc_reg_operand" "") 768 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 769 "" 770 "") 771 772(define_insn "" 773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 774 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 775 "" 776 "@ 777 lhz%U1%X1 %0,%1 778 {rlinm|rlwinm} %0,%1,0,0xffff" 779 [(set_attr "type" "load,*")]) 780 781(define_insn "" 782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 783 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 784 (const_int 0))) 785 (clobber (match_scratch:SI 2 "=r,r"))] 786 "" 787 "@ 788 {andil.|andi.} %2,%1,0xffff 789 #" 790 [(set_attr "type" "compare") 791 (set_attr "length" "4,8")]) 792 793(define_split 794 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 795 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 796 (const_int 0))) 797 (clobber (match_scratch:SI 2 ""))] 798 "reload_completed" 799 [(set (match_dup 2) 800 (zero_extend:SI (match_dup 1))) 801 (set (match_dup 0) 802 (compare:CC (match_dup 2) 803 (const_int 0)))] 804 "") 805 806(define_insn "" 807 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 808 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 809 (const_int 0))) 810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 811 (zero_extend:SI (match_dup 1)))] 812 "" 813 "@ 814 {andil.|andi.} %0,%1,0xffff 815 #" 816 [(set_attr "type" "compare") 817 (set_attr "length" "4,8")]) 818 819(define_split 820 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 821 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 822 (const_int 0))) 823 (set (match_operand:SI 0 "gpc_reg_operand" "") 824 (zero_extend:SI (match_dup 1)))] 825 "reload_completed" 826 [(set (match_dup 0) 827 (zero_extend:SI (match_dup 1))) 828 (set (match_dup 2) 829 (compare:CC (match_dup 0) 830 (const_int 0)))] 831 "") 832 833(define_expand "extendhisi2" 834 [(set (match_operand:SI 0 "gpc_reg_operand" "") 835 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 836 "" 837 "") 838 839(define_insn "" 840 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 841 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 842 "" 843 "@ 844 lha%U1%X1 %0,%1 845 {exts|extsh} %0,%1" 846 [(set_attr "type" "load_ext,*")]) 847 848(define_insn "" 849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 850 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 851 (const_int 0))) 852 (clobber (match_scratch:SI 2 "=r,r"))] 853 "" 854 "@ 855 {exts.|extsh.} %2,%1 856 #" 857 [(set_attr "type" "compare") 858 (set_attr "length" "4,8")]) 859 860(define_split 861 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 862 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 863 (const_int 0))) 864 (clobber (match_scratch:SI 2 ""))] 865 "reload_completed" 866 [(set (match_dup 2) 867 (sign_extend:SI (match_dup 1))) 868 (set (match_dup 0) 869 (compare:CC (match_dup 2) 870 (const_int 0)))] 871 "") 872 873(define_insn "" 874 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 875 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 876 (const_int 0))) 877 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 878 (sign_extend:SI (match_dup 1)))] 879 "" 880 "@ 881 {exts.|extsh.} %0,%1 882 #" 883 [(set_attr "type" "compare") 884 (set_attr "length" "4,8")]) 885 886;; IBM 405 and 440 half-word multiplication operations. 887 888(define_insn "*macchwc" 889 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 890 (compare:CC (plus:SI (mult:SI (ashiftrt:SI 891 (match_operand:SI 2 "gpc_reg_operand" "r") 892 (const_int 16)) 893 (sign_extend:SI 894 (match_operand:HI 1 "gpc_reg_operand" "r"))) 895 (match_operand:SI 4 "gpc_reg_operand" "0")) 896 (const_int 0))) 897 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 898 (plus:SI (mult:SI (ashiftrt:SI 899 (match_dup 2) 900 (const_int 16)) 901 (sign_extend:SI 902 (match_dup 1))) 903 (match_dup 4)))] 904 "TARGET_MULHW" 905 "macchw. %0, %1, %2" 906 [(set_attr "type" "imul3")]) 907 908(define_insn "*macchw" 909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 910 (plus:SI (mult:SI (ashiftrt:SI 911 (match_operand:SI 2 "gpc_reg_operand" "r") 912 (const_int 16)) 913 (sign_extend:SI 914 (match_operand:HI 1 "gpc_reg_operand" "r"))) 915 (match_operand:SI 3 "gpc_reg_operand" "0")))] 916 "TARGET_MULHW" 917 "macchw %0, %1, %2" 918 [(set_attr "type" "imul3")]) 919 920(define_insn "*macchwuc" 921 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 922 (compare:CC (plus:SI (mult:SI (lshiftrt:SI 923 (match_operand:SI 2 "gpc_reg_operand" "r") 924 (const_int 16)) 925 (zero_extend:SI 926 (match_operand:HI 1 "gpc_reg_operand" "r"))) 927 (match_operand:SI 4 "gpc_reg_operand" "0")) 928 (const_int 0))) 929 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 930 (plus:SI (mult:SI (lshiftrt:SI 931 (match_dup 2) 932 (const_int 16)) 933 (zero_extend:SI 934 (match_dup 1))) 935 (match_dup 4)))] 936 "TARGET_MULHW" 937 "macchwu. %0, %1, %2" 938 [(set_attr "type" "imul3")]) 939 940(define_insn "*macchwu" 941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 942 (plus:SI (mult:SI (lshiftrt:SI 943 (match_operand:SI 2 "gpc_reg_operand" "r") 944 (const_int 16)) 945 (zero_extend:SI 946 (match_operand:HI 1 "gpc_reg_operand" "r"))) 947 (match_operand:SI 3 "gpc_reg_operand" "0")))] 948 "TARGET_MULHW" 949 "macchwu %0, %1, %2" 950 [(set_attr "type" "imul3")]) 951 952(define_insn "*machhwc" 953 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 954 (compare:CC (plus:SI (mult:SI (ashiftrt:SI 955 (match_operand:SI 1 "gpc_reg_operand" "%r") 956 (const_int 16)) 957 (ashiftrt:SI 958 (match_operand:SI 2 "gpc_reg_operand" "r") 959 (const_int 16))) 960 (match_operand:SI 4 "gpc_reg_operand" "0")) 961 (const_int 0))) 962 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 963 (plus:SI (mult:SI (ashiftrt:SI 964 (match_dup 1) 965 (const_int 16)) 966 (ashiftrt:SI 967 (match_dup 2) 968 (const_int 16))) 969 (match_dup 4)))] 970 "TARGET_MULHW" 971 "machhw. %0, %1, %2" 972 [(set_attr "type" "imul3")]) 973 974(define_insn "*machhw" 975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 976 (plus:SI (mult:SI (ashiftrt:SI 977 (match_operand:SI 1 "gpc_reg_operand" "%r") 978 (const_int 16)) 979 (ashiftrt:SI 980 (match_operand:SI 2 "gpc_reg_operand" "r") 981 (const_int 16))) 982 (match_operand:SI 3 "gpc_reg_operand" "0")))] 983 "TARGET_MULHW" 984 "machhw %0, %1, %2" 985 [(set_attr "type" "imul3")]) 986 987(define_insn "*machhwuc" 988 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 989 (compare:CC (plus:SI (mult:SI (lshiftrt:SI 990 (match_operand:SI 1 "gpc_reg_operand" "%r") 991 (const_int 16)) 992 (lshiftrt:SI 993 (match_operand:SI 2 "gpc_reg_operand" "r") 994 (const_int 16))) 995 (match_operand:SI 4 "gpc_reg_operand" "0")) 996 (const_int 0))) 997 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 998 (plus:SI (mult:SI (lshiftrt:SI 999 (match_dup 1) 1000 (const_int 16)) 1001 (lshiftrt:SI 1002 (match_dup 2) 1003 (const_int 16))) 1004 (match_dup 4)))] 1005 "TARGET_MULHW" 1006 "machhwu. %0, %1, %2" 1007 [(set_attr "type" "imul3")]) 1008 1009(define_insn "*machhwu" 1010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1011 (plus:SI (mult:SI (lshiftrt:SI 1012 (match_operand:SI 1 "gpc_reg_operand" "%r") 1013 (const_int 16)) 1014 (lshiftrt:SI 1015 (match_operand:SI 2 "gpc_reg_operand" "r") 1016 (const_int 16))) 1017 (match_operand:SI 3 "gpc_reg_operand" "0")))] 1018 "TARGET_MULHW" 1019 "machhwu %0, %1, %2" 1020 [(set_attr "type" "imul3")]) 1021 1022(define_insn "*maclhwc" 1023 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1024 (compare:CC (plus:SI (mult:SI (sign_extend:SI 1025 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1026 (sign_extend:SI 1027 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1028 (match_operand:SI 4 "gpc_reg_operand" "0")) 1029 (const_int 0))) 1030 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1031 (plus:SI (mult:SI (sign_extend:SI 1032 (match_dup 1)) 1033 (sign_extend:SI 1034 (match_dup 2))) 1035 (match_dup 4)))] 1036 "TARGET_MULHW" 1037 "maclhw. %0, %1, %2" 1038 [(set_attr "type" "imul3")]) 1039 1040(define_insn "*maclhw" 1041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1042 (plus:SI (mult:SI (sign_extend:SI 1043 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1044 (sign_extend:SI 1045 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1046 (match_operand:SI 3 "gpc_reg_operand" "0")))] 1047 "TARGET_MULHW" 1048 "maclhw %0, %1, %2" 1049 [(set_attr "type" "imul3")]) 1050 1051(define_insn "*maclhwuc" 1052 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1053 (compare:CC (plus:SI (mult:SI (zero_extend:SI 1054 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1055 (zero_extend:SI 1056 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1057 (match_operand:SI 4 "gpc_reg_operand" "0")) 1058 (const_int 0))) 1059 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1060 (plus:SI (mult:SI (zero_extend:SI 1061 (match_dup 1)) 1062 (zero_extend:SI 1063 (match_dup 2))) 1064 (match_dup 4)))] 1065 "TARGET_MULHW" 1066 "maclhwu. %0, %1, %2" 1067 [(set_attr "type" "imul3")]) 1068 1069(define_insn "*maclhwu" 1070 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1071 (plus:SI (mult:SI (zero_extend:SI 1072 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1073 (zero_extend:SI 1074 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1075 (match_operand:SI 3 "gpc_reg_operand" "0")))] 1076 "TARGET_MULHW" 1077 "maclhwu %0, %1, %2" 1078 [(set_attr "type" "imul3")]) 1079 1080(define_insn "*nmacchwc" 1081 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1082 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") 1083 (mult:SI (ashiftrt:SI 1084 (match_operand:SI 2 "gpc_reg_operand" "r") 1085 (const_int 16)) 1086 (sign_extend:SI 1087 (match_operand:HI 1 "gpc_reg_operand" "r")))) 1088 (const_int 0))) 1089 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1090 (minus:SI (match_dup 4) 1091 (mult:SI (ashiftrt:SI 1092 (match_dup 2) 1093 (const_int 16)) 1094 (sign_extend:SI 1095 (match_dup 1)))))] 1096 "TARGET_MULHW" 1097 "nmacchw. %0, %1, %2" 1098 [(set_attr "type" "imul3")]) 1099 1100(define_insn "*nmacchw" 1101 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1102 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") 1103 (mult:SI (ashiftrt:SI 1104 (match_operand:SI 2 "gpc_reg_operand" "r") 1105 (const_int 16)) 1106 (sign_extend:SI 1107 (match_operand:HI 1 "gpc_reg_operand" "r")))))] 1108 "TARGET_MULHW" 1109 "nmacchw %0, %1, %2" 1110 [(set_attr "type" "imul3")]) 1111 1112(define_insn "*nmachhwc" 1113 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1114 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") 1115 (mult:SI (ashiftrt:SI 1116 (match_operand:SI 1 "gpc_reg_operand" "%r") 1117 (const_int 16)) 1118 (ashiftrt:SI 1119 (match_operand:SI 2 "gpc_reg_operand" "r") 1120 (const_int 16)))) 1121 (const_int 0))) 1122 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1123 (minus:SI (match_dup 4) 1124 (mult:SI (ashiftrt:SI 1125 (match_dup 1) 1126 (const_int 16)) 1127 (ashiftrt:SI 1128 (match_dup 2) 1129 (const_int 16)))))] 1130 "TARGET_MULHW" 1131 "nmachhw. %0, %1, %2" 1132 [(set_attr "type" "imul3")]) 1133 1134(define_insn "*nmachhw" 1135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1136 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") 1137 (mult:SI (ashiftrt:SI 1138 (match_operand:SI 1 "gpc_reg_operand" "%r") 1139 (const_int 16)) 1140 (ashiftrt:SI 1141 (match_operand:SI 2 "gpc_reg_operand" "r") 1142 (const_int 16)))))] 1143 "TARGET_MULHW" 1144 "nmachhw %0, %1, %2" 1145 [(set_attr "type" "imul3")]) 1146 1147(define_insn "*nmaclhwc" 1148 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1149 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") 1150 (mult:SI (sign_extend:SI 1151 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1152 (sign_extend:SI 1153 (match_operand:HI 2 "gpc_reg_operand" "r")))) 1154 (const_int 0))) 1155 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1156 (minus:SI (match_dup 4) 1157 (mult:SI (sign_extend:SI 1158 (match_dup 1)) 1159 (sign_extend:SI 1160 (match_dup 2)))))] 1161 "TARGET_MULHW" 1162 "nmaclhw. %0, %1, %2" 1163 [(set_attr "type" "imul3")]) 1164 1165(define_insn "*nmaclhw" 1166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1167 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") 1168 (mult:SI (sign_extend:SI 1169 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1170 (sign_extend:SI 1171 (match_operand:HI 2 "gpc_reg_operand" "r")))))] 1172 "TARGET_MULHW" 1173 "nmaclhw %0, %1, %2" 1174 [(set_attr "type" "imul3")]) 1175 1176(define_insn "*mulchwc" 1177 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1178 (compare:CC (mult:SI (ashiftrt:SI 1179 (match_operand:SI 2 "gpc_reg_operand" "r") 1180 (const_int 16)) 1181 (sign_extend:SI 1182 (match_operand:HI 1 "gpc_reg_operand" "r"))) 1183 (const_int 0))) 1184 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1185 (mult:SI (ashiftrt:SI 1186 (match_dup 2) 1187 (const_int 16)) 1188 (sign_extend:SI 1189 (match_dup 1))))] 1190 "TARGET_MULHW" 1191 "mulchw. %0, %1, %2" 1192 [(set_attr "type" "imul3")]) 1193 1194(define_insn "*mulchw" 1195 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1196 (mult:SI (ashiftrt:SI 1197 (match_operand:SI 2 "gpc_reg_operand" "r") 1198 (const_int 16)) 1199 (sign_extend:SI 1200 (match_operand:HI 1 "gpc_reg_operand" "r"))))] 1201 "TARGET_MULHW" 1202 "mulchw %0, %1, %2" 1203 [(set_attr "type" "imul3")]) 1204 1205(define_insn "*mulchwuc" 1206 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1207 (compare:CC (mult:SI (lshiftrt:SI 1208 (match_operand:SI 2 "gpc_reg_operand" "r") 1209 (const_int 16)) 1210 (zero_extend:SI 1211 (match_operand:HI 1 "gpc_reg_operand" "r"))) 1212 (const_int 0))) 1213 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1214 (mult:SI (lshiftrt:SI 1215 (match_dup 2) 1216 (const_int 16)) 1217 (zero_extend:SI 1218 (match_dup 1))))] 1219 "TARGET_MULHW" 1220 "mulchwu. %0, %1, %2" 1221 [(set_attr "type" "imul3")]) 1222 1223(define_insn "*mulchwu" 1224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1225 (mult:SI (lshiftrt:SI 1226 (match_operand:SI 2 "gpc_reg_operand" "r") 1227 (const_int 16)) 1228 (zero_extend:SI 1229 (match_operand:HI 1 "gpc_reg_operand" "r"))))] 1230 "TARGET_MULHW" 1231 "mulchwu %0, %1, %2" 1232 [(set_attr "type" "imul3")]) 1233 1234(define_insn "*mulhhwc" 1235 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1236 (compare:CC (mult:SI (ashiftrt:SI 1237 (match_operand:SI 1 "gpc_reg_operand" "%r") 1238 (const_int 16)) 1239 (ashiftrt:SI 1240 (match_operand:SI 2 "gpc_reg_operand" "r") 1241 (const_int 16))) 1242 (const_int 0))) 1243 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1244 (mult:SI (ashiftrt:SI 1245 (match_dup 1) 1246 (const_int 16)) 1247 (ashiftrt:SI 1248 (match_dup 2) 1249 (const_int 16))))] 1250 "TARGET_MULHW" 1251 "mulhhw. %0, %1, %2" 1252 [(set_attr "type" "imul3")]) 1253 1254(define_insn "*mulhhw" 1255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1256 (mult:SI (ashiftrt:SI 1257 (match_operand:SI 1 "gpc_reg_operand" "%r") 1258 (const_int 16)) 1259 (ashiftrt:SI 1260 (match_operand:SI 2 "gpc_reg_operand" "r") 1261 (const_int 16))))] 1262 "TARGET_MULHW" 1263 "mulhhw %0, %1, %2" 1264 [(set_attr "type" "imul3")]) 1265 1266(define_insn "*mulhhwuc" 1267 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1268 (compare:CC (mult:SI (lshiftrt:SI 1269 (match_operand:SI 1 "gpc_reg_operand" "%r") 1270 (const_int 16)) 1271 (lshiftrt:SI 1272 (match_operand:SI 2 "gpc_reg_operand" "r") 1273 (const_int 16))) 1274 (const_int 0))) 1275 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1276 (mult:SI (lshiftrt:SI 1277 (match_dup 1) 1278 (const_int 16)) 1279 (lshiftrt:SI 1280 (match_dup 2) 1281 (const_int 16))))] 1282 "TARGET_MULHW" 1283 "mulhhwu. %0, %1, %2" 1284 [(set_attr "type" "imul3")]) 1285 1286(define_insn "*mulhhwu" 1287 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1288 (mult:SI (lshiftrt:SI 1289 (match_operand:SI 1 "gpc_reg_operand" "%r") 1290 (const_int 16)) 1291 (lshiftrt:SI 1292 (match_operand:SI 2 "gpc_reg_operand" "r") 1293 (const_int 16))))] 1294 "TARGET_MULHW" 1295 "mulhhwu %0, %1, %2" 1296 [(set_attr "type" "imul3")]) 1297 1298(define_insn "*mullhwc" 1299 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1300 (compare:CC (mult:SI (sign_extend:SI 1301 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1302 (sign_extend:SI 1303 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1304 (const_int 0))) 1305 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1306 (mult:SI (sign_extend:SI 1307 (match_dup 1)) 1308 (sign_extend:SI 1309 (match_dup 2))))] 1310 "TARGET_MULHW" 1311 "mullhw. %0, %1, %2" 1312 [(set_attr "type" "imul3")]) 1313 1314(define_insn "*mullhw" 1315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1316 (mult:SI (sign_extend:SI 1317 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1318 (sign_extend:SI 1319 (match_operand:HI 2 "gpc_reg_operand" "r"))))] 1320 "TARGET_MULHW" 1321 "mullhw %0, %1, %2" 1322 [(set_attr "type" "imul3")]) 1323 1324(define_insn "*mullhwuc" 1325 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1326 (compare:CC (mult:SI (zero_extend:SI 1327 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1328 (zero_extend:SI 1329 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1330 (const_int 0))) 1331 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1332 (mult:SI (zero_extend:SI 1333 (match_dup 1)) 1334 (zero_extend:SI 1335 (match_dup 2))))] 1336 "TARGET_MULHW" 1337 "mullhwu. %0, %1, %2" 1338 [(set_attr "type" "imul3")]) 1339 1340(define_insn "*mullhwu" 1341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1342 (mult:SI (zero_extend:SI 1343 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1344 (zero_extend:SI 1345 (match_operand:HI 2 "gpc_reg_operand" "r"))))] 1346 "TARGET_MULHW" 1347 "mullhwu %0, %1, %2" 1348 [(set_attr "type" "imul3")]) 1349 1350;; IBM 405 and 440 string-search dlmzb instruction support. 1351(define_insn "dlmzb" 1352 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1353 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 1354 (match_operand:SI 2 "gpc_reg_operand" "r")] 1355 UNSPEC_DLMZB_CR)) 1356 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1357 (unspec:SI [(match_dup 1) 1358 (match_dup 2)] 1359 UNSPEC_DLMZB))] 1360 "TARGET_DLMZB" 1361 "dlmzb. %0, %1, %2") 1362 1363(define_expand "strlensi" 1364 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1365 (unspec:SI [(match_operand:BLK 1 "general_operand" "") 1366 (match_operand:QI 2 "const_int_operand" "") 1367 (match_operand 3 "const_int_operand" "")] 1368 UNSPEC_DLMZB_STRLEN)) 1369 (clobber (match_scratch:CC 4 "=x"))] 1370 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size" 1371{ 1372 rtx result = operands[0]; 1373 rtx src = operands[1]; 1374 rtx search_char = operands[2]; 1375 rtx align = operands[3]; 1376 rtx addr, scratch_string, word1, word2, scratch_dlmzb; 1377 rtx loop_label, end_label, mem, cr0, cond; 1378 if (search_char != const0_rtx 1379 || GET_CODE (align) != CONST_INT 1380 || INTVAL (align) < 8) 1381 FAIL; 1382 word1 = gen_reg_rtx (SImode); 1383 word2 = gen_reg_rtx (SImode); 1384 scratch_dlmzb = gen_reg_rtx (SImode); 1385 scratch_string = gen_reg_rtx (Pmode); 1386 loop_label = gen_label_rtx (); 1387 end_label = gen_label_rtx (); 1388 addr = force_reg (Pmode, XEXP (src, 0)); 1389 emit_move_insn (scratch_string, addr); 1390 emit_label (loop_label); 1391 mem = change_address (src, SImode, scratch_string); 1392 emit_move_insn (word1, mem); 1393 emit_move_insn (word2, adjust_address (mem, SImode, 4)); 1394 cr0 = gen_rtx_REG (CCmode, CR0_REGNO); 1395 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0)); 1396 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx); 1397 emit_jump_insn (gen_rtx_SET (VOIDmode, 1398 pc_rtx, 1399 gen_rtx_IF_THEN_ELSE (VOIDmode, 1400 cond, 1401 gen_rtx_LABEL_REF 1402 (VOIDmode, 1403 end_label), 1404 pc_rtx))); 1405 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8))); 1406 emit_jump_insn (gen_rtx_SET (VOIDmode, 1407 pc_rtx, 1408 gen_rtx_LABEL_REF (VOIDmode, loop_label))); 1409 emit_barrier (); 1410 emit_label (end_label); 1411 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb)); 1412 emit_insn (gen_subsi3 (result, scratch_string, addr)); 1413 emit_insn (gen_subsi3 (result, result, const1_rtx)); 1414 DONE; 1415}) 1416 1417(define_split 1418 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1419 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 1420 (const_int 0))) 1421 (set (match_operand:SI 0 "gpc_reg_operand" "") 1422 (sign_extend:SI (match_dup 1)))] 1423 "reload_completed" 1424 [(set (match_dup 0) 1425 (sign_extend:SI (match_dup 1))) 1426 (set (match_dup 2) 1427 (compare:CC (match_dup 0) 1428 (const_int 0)))] 1429 "") 1430 1431;; Fixed-point arithmetic insns. 1432 1433(define_expand "add<mode>3" 1434 [(set (match_operand:SDI 0 "gpc_reg_operand" "") 1435 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "") 1436 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))] 1437 "" 1438{ 1439 if (<MODE>mode == DImode && ! TARGET_POWERPC64) 1440 { 1441 if (non_short_cint_operand (operands[2], DImode)) 1442 FAIL; 1443 } 1444 else if (GET_CODE (operands[2]) == CONST_INT 1445 && ! add_operand (operands[2], <MODE>mode)) 1446 { 1447 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 1448 ? operands[0] : gen_reg_rtx (<MODE>mode)); 1449 1450 HOST_WIDE_INT val = INTVAL (operands[2]); 1451 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; 1452 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); 1453 1454 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest))) 1455 FAIL; 1456 1457 /* The ordering here is important for the prolog expander. 1458 When space is allocated from the stack, adding 'low' first may 1459 produce a temporary deallocation (which would be bad). */ 1460 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest))); 1461 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low))); 1462 DONE; 1463 } 1464}) 1465 1466;; Discourage ai/addic because of carry but provide it in an alternative 1467;; allowing register zero as source. 1468(define_insn "*add<mode>3_internal1" 1469 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r") 1470 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b") 1471 (match_operand:GPR 2 "add_operand" "r,I,I,L")))] 1472 "" 1473 "@ 1474 {cax|add} %0,%1,%2 1475 {cal %0,%2(%1)|addi %0,%1,%2} 1476 {ai|addic} %0,%1,%2 1477 {cau|addis} %0,%1,%v2" 1478 [(set_attr "length" "4,4,4,4")]) 1479 1480(define_insn "addsi3_high" 1481 [(set (match_operand:SI 0 "gpc_reg_operand" "=b") 1482 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 1483 (high:SI (match_operand 2 "" ""))))] 1484 "TARGET_MACHO && !TARGET_64BIT" 1485 "{cau|addis} %0,%1,ha16(%2)" 1486 [(set_attr "length" "4")]) 1487 1488(define_insn "*add<mode>3_internal2" 1489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 1490 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") 1491 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) 1492 (const_int 0))) 1493 (clobber (match_scratch:P 3 "=r,r,r,r"))] 1494 "" 1495 "@ 1496 {cax.|add.} %3,%1,%2 1497 {ai.|addic.} %3,%1,%2 1498 # 1499 #" 1500 [(set_attr "type" "fast_compare,compare,compare,compare") 1501 (set_attr "length" "4,4,8,8")]) 1502 1503(define_split 1504 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1505 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 1506 (match_operand:GPR 2 "reg_or_short_operand" "")) 1507 (const_int 0))) 1508 (clobber (match_scratch:GPR 3 ""))] 1509 "reload_completed" 1510 [(set (match_dup 3) 1511 (plus:GPR (match_dup 1) 1512 (match_dup 2))) 1513 (set (match_dup 0) 1514 (compare:CC (match_dup 3) 1515 (const_int 0)))] 1516 "") 1517 1518(define_insn "*add<mode>3_internal3" 1519 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 1520 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") 1521 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) 1522 (const_int 0))) 1523 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") 1524 (plus:P (match_dup 1) 1525 (match_dup 2)))] 1526 "" 1527 "@ 1528 {cax.|add.} %0,%1,%2 1529 {ai.|addic.} %0,%1,%2 1530 # 1531 #" 1532 [(set_attr "type" "fast_compare,compare,compare,compare") 1533 (set_attr "length" "4,4,8,8")]) 1534 1535(define_split 1536 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1537 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "") 1538 (match_operand:P 2 "reg_or_short_operand" "")) 1539 (const_int 0))) 1540 (set (match_operand:P 0 "gpc_reg_operand" "") 1541 (plus:P (match_dup 1) (match_dup 2)))] 1542 "reload_completed" 1543 [(set (match_dup 0) 1544 (plus:P (match_dup 1) 1545 (match_dup 2))) 1546 (set (match_dup 3) 1547 (compare:CC (match_dup 0) 1548 (const_int 0)))] 1549 "") 1550 1551;; Split an add that we can't do in one insn into two insns, each of which 1552;; does one 16-bit part. This is used by combine. Note that the low-order 1553;; add should be last in case the result gets used in an address. 1554 1555(define_split 1556 [(set (match_operand:GPR 0 "gpc_reg_operand" "") 1557 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 1558 (match_operand:GPR 2 "non_add_cint_operand" "")))] 1559 "" 1560 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3))) 1561 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] 1562{ 1563 HOST_WIDE_INT val = INTVAL (operands[2]); 1564 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; 1565 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); 1566 1567 operands[4] = GEN_INT (low); 1568 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest))) 1569 operands[3] = GEN_INT (rest); 1570 else if (! no_new_pseudos) 1571 { 1572 operands[3] = gen_reg_rtx (DImode); 1573 emit_move_insn (operands[3], operands[2]); 1574 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 1575 DONE; 1576 } 1577 else 1578 FAIL; 1579}) 1580 1581(define_insn "one_cmpl<mode>2" 1582 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 1583 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] 1584 "" 1585 "nor %0,%1,%1") 1586 1587(define_insn "" 1588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1589 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) 1590 (const_int 0))) 1591 (clobber (match_scratch:P 2 "=r,r"))] 1592 "" 1593 "@ 1594 nor. %2,%1,%1 1595 #" 1596 [(set_attr "type" "compare") 1597 (set_attr "length" "4,8")]) 1598 1599(define_split 1600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1601 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) 1602 (const_int 0))) 1603 (clobber (match_scratch:P 2 ""))] 1604 "reload_completed" 1605 [(set (match_dup 2) 1606 (not:P (match_dup 1))) 1607 (set (match_dup 0) 1608 (compare:CC (match_dup 2) 1609 (const_int 0)))] 1610 "") 1611 1612(define_insn "" 1613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1614 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) 1615 (const_int 0))) 1616 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 1617 (not:P (match_dup 1)))] 1618 "" 1619 "@ 1620 nor. %0,%1,%1 1621 #" 1622 [(set_attr "type" "compare") 1623 (set_attr "length" "4,8")]) 1624 1625(define_split 1626 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1627 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) 1628 (const_int 0))) 1629 (set (match_operand:P 0 "gpc_reg_operand" "") 1630 (not:P (match_dup 1)))] 1631 "reload_completed" 1632 [(set (match_dup 0) 1633 (not:P (match_dup 1))) 1634 (set (match_dup 2) 1635 (compare:CC (match_dup 0) 1636 (const_int 0)))] 1637 "") 1638 1639(define_insn "" 1640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1641 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") 1642 (match_operand:SI 2 "gpc_reg_operand" "r")))] 1643 "! TARGET_POWERPC" 1644 "{sf%I1|subf%I1c} %0,%2,%1") 1645 1646(define_insn "" 1647 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") 1648 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I") 1649 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))] 1650 "TARGET_POWERPC" 1651 "@ 1652 subf %0,%2,%1 1653 subfic %0,%2,%1") 1654 1655(define_insn "" 1656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1657 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1658 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1659 (const_int 0))) 1660 (clobber (match_scratch:SI 3 "=r,r"))] 1661 "! TARGET_POWERPC" 1662 "@ 1663 {sf.|subfc.} %3,%2,%1 1664 #" 1665 [(set_attr "type" "compare") 1666 (set_attr "length" "4,8")]) 1667 1668(define_insn "" 1669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1670 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") 1671 (match_operand:P 2 "gpc_reg_operand" "r,r")) 1672 (const_int 0))) 1673 (clobber (match_scratch:P 3 "=r,r"))] 1674 "TARGET_POWERPC" 1675 "@ 1676 subf. %3,%2,%1 1677 #" 1678 [(set_attr "type" "fast_compare") 1679 (set_attr "length" "4,8")]) 1680 1681(define_split 1682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1683 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") 1684 (match_operand:P 2 "gpc_reg_operand" "")) 1685 (const_int 0))) 1686 (clobber (match_scratch:P 3 ""))] 1687 "reload_completed" 1688 [(set (match_dup 3) 1689 (minus:P (match_dup 1) 1690 (match_dup 2))) 1691 (set (match_dup 0) 1692 (compare:CC (match_dup 3) 1693 (const_int 0)))] 1694 "") 1695 1696(define_insn "" 1697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1698 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1699 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1700 (const_int 0))) 1701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1702 (minus:SI (match_dup 1) (match_dup 2)))] 1703 "! TARGET_POWERPC" 1704 "@ 1705 {sf.|subfc.} %0,%2,%1 1706 #" 1707 [(set_attr "type" "compare") 1708 (set_attr "length" "4,8")]) 1709 1710(define_insn "" 1711 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1712 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") 1713 (match_operand:P 2 "gpc_reg_operand" "r,r")) 1714 (const_int 0))) 1715 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 1716 (minus:P (match_dup 1) 1717 (match_dup 2)))] 1718 "TARGET_POWERPC" 1719 "@ 1720 subf. %0,%2,%1 1721 #" 1722 [(set_attr "type" "fast_compare") 1723 (set_attr "length" "4,8")]) 1724 1725(define_split 1726 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1727 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") 1728 (match_operand:P 2 "gpc_reg_operand" "")) 1729 (const_int 0))) 1730 (set (match_operand:P 0 "gpc_reg_operand" "") 1731 (minus:P (match_dup 1) 1732 (match_dup 2)))] 1733 "reload_completed" 1734 [(set (match_dup 0) 1735 (minus:P (match_dup 1) 1736 (match_dup 2))) 1737 (set (match_dup 3) 1738 (compare:CC (match_dup 0) 1739 (const_int 0)))] 1740 "") 1741 1742(define_expand "sub<mode>3" 1743 [(set (match_operand:SDI 0 "gpc_reg_operand" "") 1744 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "") 1745 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))] 1746 "" 1747 " 1748{ 1749 if (GET_CODE (operands[2]) == CONST_INT) 1750 { 1751 emit_insn (gen_add<mode>3 (operands[0], operands[1], 1752 negate_rtx (<MODE>mode, operands[2]))); 1753 DONE; 1754 } 1755}") 1756 1757;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] 1758;; instruction and some auxiliary computations. Then we just have a single 1759;; DEFINE_INSN for doz[i] and the define_splits to make them if made by 1760;; combine. 1761 1762(define_expand "sminsi3" 1763 [(set (match_dup 3) 1764 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 1765 (match_operand:SI 2 "reg_or_short_operand" "")) 1766 (const_int 0) 1767 (minus:SI (match_dup 2) (match_dup 1)))) 1768 (set (match_operand:SI 0 "gpc_reg_operand" "") 1769 (minus:SI (match_dup 2) (match_dup 3)))] 1770 "TARGET_POWER || TARGET_ISEL" 1771 " 1772{ 1773 if (TARGET_ISEL) 1774 { 1775 operands[2] = force_reg (SImode, operands[2]); 1776 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); 1777 DONE; 1778 } 1779 1780 operands[3] = gen_reg_rtx (SImode); 1781}") 1782 1783(define_split 1784 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1785 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") 1786 (match_operand:SI 2 "reg_or_short_operand" ""))) 1787 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1788 "TARGET_POWER" 1789 [(set (match_dup 3) 1790 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 1791 (const_int 0) 1792 (minus:SI (match_dup 2) (match_dup 1)))) 1793 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] 1794 "") 1795 1796(define_expand "smaxsi3" 1797 [(set (match_dup 3) 1798 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 1799 (match_operand:SI 2 "reg_or_short_operand" "")) 1800 (const_int 0) 1801 (minus:SI (match_dup 2) (match_dup 1)))) 1802 (set (match_operand:SI 0 "gpc_reg_operand" "") 1803 (plus:SI (match_dup 3) (match_dup 1)))] 1804 "TARGET_POWER || TARGET_ISEL" 1805 " 1806{ 1807 if (TARGET_ISEL) 1808 { 1809 operands[2] = force_reg (SImode, operands[2]); 1810 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); 1811 DONE; 1812 } 1813 operands[3] = gen_reg_rtx (SImode); 1814}") 1815 1816(define_split 1817 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1818 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") 1819 (match_operand:SI 2 "reg_or_short_operand" ""))) 1820 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1821 "TARGET_POWER" 1822 [(set (match_dup 3) 1823 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 1824 (const_int 0) 1825 (minus:SI (match_dup 2) (match_dup 1)))) 1826 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] 1827 "") 1828 1829(define_expand "uminsi3" 1830 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1831 (match_dup 5))) 1832 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 1833 (match_dup 5))) 1834 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 1835 (const_int 0) 1836 (minus:SI (match_dup 4) (match_dup 3)))) 1837 (set (match_operand:SI 0 "gpc_reg_operand" "") 1838 (minus:SI (match_dup 2) (match_dup 3)))] 1839 "TARGET_POWER || TARGET_ISEL" 1840 " 1841{ 1842 if (TARGET_ISEL) 1843 { 1844 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); 1845 DONE; 1846 } 1847 operands[3] = gen_reg_rtx (SImode); 1848 operands[4] = gen_reg_rtx (SImode); 1849 operands[5] = GEN_INT (-2147483647 - 1); 1850}") 1851 1852(define_expand "umaxsi3" 1853 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1854 (match_dup 5))) 1855 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 1856 (match_dup 5))) 1857 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 1858 (const_int 0) 1859 (minus:SI (match_dup 4) (match_dup 3)))) 1860 (set (match_operand:SI 0 "gpc_reg_operand" "") 1861 (plus:SI (match_dup 3) (match_dup 1)))] 1862 "TARGET_POWER || TARGET_ISEL" 1863 " 1864{ 1865 if (TARGET_ISEL) 1866 { 1867 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); 1868 DONE; 1869 } 1870 operands[3] = gen_reg_rtx (SImode); 1871 operands[4] = gen_reg_rtx (SImode); 1872 operands[5] = GEN_INT (-2147483647 - 1); 1873}") 1874 1875(define_insn "" 1876 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1877 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 1878 (match_operand:SI 2 "reg_or_short_operand" "rI")) 1879 (const_int 0) 1880 (minus:SI (match_dup 2) (match_dup 1))))] 1881 "TARGET_POWER" 1882 "doz%I2 %0,%1,%2") 1883 1884(define_insn "" 1885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1886 (compare:CC 1887 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") 1888 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 1889 (const_int 0) 1890 (minus:SI (match_dup 2) (match_dup 1))) 1891 (const_int 0))) 1892 (clobber (match_scratch:SI 3 "=r,r"))] 1893 "TARGET_POWER" 1894 "@ 1895 doz%I2. %3,%1,%2 1896 #" 1897 [(set_attr "type" "delayed_compare") 1898 (set_attr "length" "4,8")]) 1899 1900(define_split 1901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1902 (compare:CC 1903 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") 1904 (match_operand:SI 2 "reg_or_short_operand" "")) 1905 (const_int 0) 1906 (minus:SI (match_dup 2) (match_dup 1))) 1907 (const_int 0))) 1908 (clobber (match_scratch:SI 3 ""))] 1909 "TARGET_POWER && reload_completed" 1910 [(set (match_dup 3) 1911 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1912 (const_int 0) 1913 (minus:SI (match_dup 2) (match_dup 1)))) 1914 (set (match_dup 0) 1915 (compare:CC (match_dup 3) 1916 (const_int 0)))] 1917 "") 1918 1919(define_insn "" 1920 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1921 (compare:CC 1922 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") 1923 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 1924 (const_int 0) 1925 (minus:SI (match_dup 2) (match_dup 1))) 1926 (const_int 0))) 1927 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1928 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1929 (const_int 0) 1930 (minus:SI (match_dup 2) (match_dup 1))))] 1931 "TARGET_POWER" 1932 "@ 1933 doz%I2. %0,%1,%2 1934 #" 1935 [(set_attr "type" "delayed_compare") 1936 (set_attr "length" "4,8")]) 1937 1938(define_split 1939 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1940 (compare:CC 1941 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") 1942 (match_operand:SI 2 "reg_or_short_operand" "")) 1943 (const_int 0) 1944 (minus:SI (match_dup 2) (match_dup 1))) 1945 (const_int 0))) 1946 (set (match_operand:SI 0 "gpc_reg_operand" "") 1947 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1948 (const_int 0) 1949 (minus:SI (match_dup 2) (match_dup 1))))] 1950 "TARGET_POWER && reload_completed" 1951 [(set (match_dup 0) 1952 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1953 (const_int 0) 1954 (minus:SI (match_dup 2) (match_dup 1)))) 1955 (set (match_dup 3) 1956 (compare:CC (match_dup 0) 1957 (const_int 0)))] 1958 "") 1959 1960;; We don't need abs with condition code because such comparisons should 1961;; never be done. 1962(define_expand "abssi2" 1963 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1964 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] 1965 "" 1966 " 1967{ 1968 if (TARGET_ISEL) 1969 { 1970 emit_insn (gen_abssi2_isel (operands[0], operands[1])); 1971 DONE; 1972 } 1973 else if (! TARGET_POWER) 1974 { 1975 emit_insn (gen_abssi2_nopower (operands[0], operands[1])); 1976 DONE; 1977 } 1978}") 1979 1980(define_insn "*abssi2_power" 1981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1982 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1983 "TARGET_POWER" 1984 "abs %0,%1") 1985 1986(define_insn_and_split "abssi2_isel" 1987 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1988 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 1989 (clobber (match_scratch:SI 2 "=&b")) 1990 (clobber (match_scratch:CC 3 "=y"))] 1991 "TARGET_ISEL" 1992 "#" 1993 "&& reload_completed" 1994 [(set (match_dup 2) (neg:SI (match_dup 1))) 1995 (set (match_dup 3) 1996 (compare:CC (match_dup 1) 1997 (const_int 0))) 1998 (set (match_dup 0) 1999 (if_then_else:SI (ge (match_dup 3) 2000 (const_int 0)) 2001 (match_dup 1) 2002 (match_dup 2)))] 2003 "") 2004 2005(define_insn_and_split "abssi2_nopower" 2006 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 2007 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) 2008 (clobber (match_scratch:SI 2 "=&r,&r"))] 2009 "! TARGET_POWER && ! TARGET_ISEL" 2010 "#" 2011 "&& reload_completed" 2012 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 2013 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) 2014 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] 2015 "") 2016 2017(define_insn "*nabs_power" 2018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2019 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] 2020 "TARGET_POWER" 2021 "nabs %0,%1") 2022 2023(define_insn_and_split "*nabs_nopower" 2024 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 2025 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) 2026 (clobber (match_scratch:SI 2 "=&r,&r"))] 2027 "! TARGET_POWER" 2028 "#" 2029 "&& reload_completed" 2030 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 2031 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) 2032 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] 2033 "") 2034 2035(define_expand "neg<mode>2" 2036 [(set (match_operand:SDI 0 "gpc_reg_operand" "") 2037 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] 2038 "" 2039 "") 2040 2041(define_insn "*neg<mode>2_internal" 2042 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2043 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] 2044 "" 2045 "neg %0,%1") 2046 2047(define_insn "" 2048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2049 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) 2050 (const_int 0))) 2051 (clobber (match_scratch:P 2 "=r,r"))] 2052 "" 2053 "@ 2054 neg. %2,%1 2055 #" 2056 [(set_attr "type" "fast_compare") 2057 (set_attr "length" "4,8")]) 2058 2059(define_split 2060 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2061 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) 2062 (const_int 0))) 2063 (clobber (match_scratch:P 2 ""))] 2064 "reload_completed" 2065 [(set (match_dup 2) 2066 (neg:P (match_dup 1))) 2067 (set (match_dup 0) 2068 (compare:CC (match_dup 2) 2069 (const_int 0)))] 2070 "") 2071 2072(define_insn "" 2073 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 2074 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) 2075 (const_int 0))) 2076 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 2077 (neg:P (match_dup 1)))] 2078 "" 2079 "@ 2080 neg. %0,%1 2081 #" 2082 [(set_attr "type" "fast_compare") 2083 (set_attr "length" "4,8")]) 2084 2085(define_split 2086 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 2087 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) 2088 (const_int 0))) 2089 (set (match_operand:P 0 "gpc_reg_operand" "") 2090 (neg:P (match_dup 1)))] 2091 "reload_completed" 2092 [(set (match_dup 0) 2093 (neg:P (match_dup 1))) 2094 (set (match_dup 2) 2095 (compare:CC (match_dup 0) 2096 (const_int 0)))] 2097 "") 2098 2099(define_insn "clz<mode>2" 2100 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2101 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] 2102 "" 2103 "{cntlz|cntlz<wd>} %0,%1") 2104 2105(define_expand "ctz<mode>2" 2106 [(set (match_dup 2) 2107 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) 2108 (parallel [(set (match_dup 3) (and:GPR (match_dup 1) 2109 (match_dup 2))) 2110 (clobber (scratch:CC))]) 2111 (set (match_dup 4) (clz:GPR (match_dup 3))) 2112 (set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2113 (minus:GPR (match_dup 5) (match_dup 4)))] 2114 "" 2115 { 2116 operands[2] = gen_reg_rtx (<MODE>mode); 2117 operands[3] = gen_reg_rtx (<MODE>mode); 2118 operands[4] = gen_reg_rtx (<MODE>mode); 2119 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1); 2120 }) 2121 2122(define_expand "ffs<mode>2" 2123 [(set (match_dup 2) 2124 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) 2125 (parallel [(set (match_dup 3) (and:GPR (match_dup 1) 2126 (match_dup 2))) 2127 (clobber (scratch:CC))]) 2128 (set (match_dup 4) (clz:GPR (match_dup 3))) 2129 (set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2130 (minus:GPR (match_dup 5) (match_dup 4)))] 2131 "" 2132 { 2133 operands[2] = gen_reg_rtx (<MODE>mode); 2134 operands[3] = gen_reg_rtx (<MODE>mode); 2135 operands[4] = gen_reg_rtx (<MODE>mode); 2136 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)); 2137 }) 2138 2139(define_expand "popcount<mode>2" 2140 [(set (match_dup 2) 2141 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] 2142 UNSPEC_POPCNTB)) 2143 (set (match_dup 3) 2144 (mult:GPR (match_dup 2) (match_dup 4))) 2145 (set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2146 (lshiftrt:GPR (match_dup 3) (match_dup 5)))] 2147 "TARGET_POPCNTB" 2148 { 2149 operands[2] = gen_reg_rtx (<MODE>mode); 2150 operands[3] = gen_reg_rtx (<MODE>mode); 2151 operands[4] = force_reg (<MODE>mode, 2152 <MODE>mode == SImode 2153 ? GEN_INT (0x01010101) 2154 : GEN_INT ((HOST_WIDE_INT) 2155 0x01010101 << 32 | 0x01010101)); 2156 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8); 2157 }) 2158 2159(define_insn "popcntb<mode>2" 2160 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2161 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] 2162 UNSPEC_POPCNTB))] 2163 "TARGET_POPCNTB" 2164 "popcntb %0,%1") 2165 2166(define_expand "mulsi3" 2167 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2168 (use (match_operand:SI 1 "gpc_reg_operand" "")) 2169 (use (match_operand:SI 2 "reg_or_short_operand" ""))] 2170 "" 2171 " 2172{ 2173 if (TARGET_POWER) 2174 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); 2175 else 2176 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); 2177 DONE; 2178}") 2179 2180(define_insn "mulsi3_mq" 2181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2182 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2183 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 2184 (clobber (match_scratch:SI 3 "=q,q"))] 2185 "TARGET_POWER" 2186 "@ 2187 {muls|mullw} %0,%1,%2 2188 {muli|mulli} %0,%1,%2" 2189 [(set (attr "type") 2190 (cond [(match_operand:SI 2 "s8bit_cint_operand" "") 2191 (const_string "imul3") 2192 (match_operand:SI 2 "short_cint_operand" "") 2193 (const_string "imul2")] 2194 (const_string "imul")))]) 2195 2196(define_insn "mulsi3_no_mq" 2197 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2198 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2199 (match_operand:SI 2 "reg_or_short_operand" "r,I")))] 2200 "! TARGET_POWER" 2201 "@ 2202 {muls|mullw} %0,%1,%2 2203 {muli|mulli} %0,%1,%2" 2204 [(set (attr "type") 2205 (cond [(match_operand:SI 2 "s8bit_cint_operand" "") 2206 (const_string "imul3") 2207 (match_operand:SI 2 "short_cint_operand" "") 2208 (const_string "imul2")] 2209 (const_string "imul")))]) 2210 2211(define_insn "*mulsi3_mq_internal1" 2212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2213 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2214 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2215 (const_int 0))) 2216 (clobber (match_scratch:SI 3 "=r,r")) 2217 (clobber (match_scratch:SI 4 "=q,q"))] 2218 "TARGET_POWER" 2219 "@ 2220 {muls.|mullw.} %3,%1,%2 2221 #" 2222 [(set_attr "type" "imul_compare") 2223 (set_attr "length" "4,8")]) 2224 2225(define_split 2226 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2227 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2228 (match_operand:SI 2 "gpc_reg_operand" "")) 2229 (const_int 0))) 2230 (clobber (match_scratch:SI 3 "")) 2231 (clobber (match_scratch:SI 4 ""))] 2232 "TARGET_POWER && reload_completed" 2233 [(parallel [(set (match_dup 3) 2234 (mult:SI (match_dup 1) (match_dup 2))) 2235 (clobber (match_dup 4))]) 2236 (set (match_dup 0) 2237 (compare:CC (match_dup 3) 2238 (const_int 0)))] 2239 "") 2240 2241(define_insn "*mulsi3_no_mq_internal1" 2242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2243 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2244 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2245 (const_int 0))) 2246 (clobber (match_scratch:SI 3 "=r,r"))] 2247 "! TARGET_POWER" 2248 "@ 2249 {muls.|mullw.} %3,%1,%2 2250 #" 2251 [(set_attr "type" "imul_compare") 2252 (set_attr "length" "4,8")]) 2253 2254(define_split 2255 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2256 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2257 (match_operand:SI 2 "gpc_reg_operand" "")) 2258 (const_int 0))) 2259 (clobber (match_scratch:SI 3 ""))] 2260 "! TARGET_POWER && reload_completed" 2261 [(set (match_dup 3) 2262 (mult:SI (match_dup 1) (match_dup 2))) 2263 (set (match_dup 0) 2264 (compare:CC (match_dup 3) 2265 (const_int 0)))] 2266 "") 2267 2268(define_insn "*mulsi3_mq_internal2" 2269 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2270 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2271 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2272 (const_int 0))) 2273 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2274 (mult:SI (match_dup 1) (match_dup 2))) 2275 (clobber (match_scratch:SI 4 "=q,q"))] 2276 "TARGET_POWER" 2277 "@ 2278 {muls.|mullw.} %0,%1,%2 2279 #" 2280 [(set_attr "type" "imul_compare") 2281 (set_attr "length" "4,8")]) 2282 2283(define_split 2284 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2285 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2286 (match_operand:SI 2 "gpc_reg_operand" "")) 2287 (const_int 0))) 2288 (set (match_operand:SI 0 "gpc_reg_operand" "") 2289 (mult:SI (match_dup 1) (match_dup 2))) 2290 (clobber (match_scratch:SI 4 ""))] 2291 "TARGET_POWER && reload_completed" 2292 [(parallel [(set (match_dup 0) 2293 (mult:SI (match_dup 1) (match_dup 2))) 2294 (clobber (match_dup 4))]) 2295 (set (match_dup 3) 2296 (compare:CC (match_dup 0) 2297 (const_int 0)))] 2298 "") 2299 2300(define_insn "*mulsi3_no_mq_internal2" 2301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2302 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2303 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2304 (const_int 0))) 2305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2306 (mult:SI (match_dup 1) (match_dup 2)))] 2307 "! TARGET_POWER" 2308 "@ 2309 {muls.|mullw.} %0,%1,%2 2310 #" 2311 [(set_attr "type" "imul_compare") 2312 (set_attr "length" "4,8")]) 2313 2314(define_split 2315 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2316 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2317 (match_operand:SI 2 "gpc_reg_operand" "")) 2318 (const_int 0))) 2319 (set (match_operand:SI 0 "gpc_reg_operand" "") 2320 (mult:SI (match_dup 1) (match_dup 2)))] 2321 "! TARGET_POWER && reload_completed" 2322 [(set (match_dup 0) 2323 (mult:SI (match_dup 1) (match_dup 2))) 2324 (set (match_dup 3) 2325 (compare:CC (match_dup 0) 2326 (const_int 0)))] 2327 "") 2328 2329;; Operand 1 is divided by operand 2; quotient goes to operand 2330;; 0 and remainder to operand 3. 2331;; ??? At some point, see what, if anything, we can do about if (x % y == 0). 2332 2333(define_expand "divmodsi4" 2334 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 2335 (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 2336 (match_operand:SI 2 "gpc_reg_operand" ""))) 2337 (set (match_operand:SI 3 "register_operand" "") 2338 (mod:SI (match_dup 1) (match_dup 2)))])] 2339 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" 2340 " 2341{ 2342 if (! TARGET_POWER && ! TARGET_POWERPC) 2343 { 2344 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 2345 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 2346 emit_insn (gen_divss_call ()); 2347 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 2348 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); 2349 DONE; 2350 } 2351}") 2352 2353(define_insn "*divmodsi4_internal" 2354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2355 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2356 (match_operand:SI 2 "gpc_reg_operand" "r"))) 2357 (set (match_operand:SI 3 "register_operand" "=q") 2358 (mod:SI (match_dup 1) (match_dup 2)))] 2359 "TARGET_POWER" 2360 "divs %0,%1,%2" 2361 [(set_attr "type" "idiv")]) 2362 2363(define_expand "udiv<mode>3" 2364 [(set (match_operand:GPR 0 "gpc_reg_operand" "") 2365 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 2366 (match_operand:GPR 2 "gpc_reg_operand" "")))] 2367 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" 2368 " 2369{ 2370 if (! TARGET_POWER && ! TARGET_POWERPC) 2371 { 2372 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 2373 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 2374 emit_insn (gen_quous_call ()); 2375 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 2376 DONE; 2377 } 2378 else if (TARGET_POWER) 2379 { 2380 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); 2381 DONE; 2382 } 2383}") 2384 2385(define_insn "udivsi3_mq" 2386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2387 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2388 (match_operand:SI 2 "gpc_reg_operand" "r"))) 2389 (clobber (match_scratch:SI 3 "=q"))] 2390 "TARGET_POWERPC && TARGET_POWER" 2391 "divwu %0,%1,%2" 2392 [(set_attr "type" "idiv")]) 2393 2394(define_insn "*udivsi3_no_mq" 2395 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2396 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") 2397 (match_operand:GPR 2 "gpc_reg_operand" "r")))] 2398 "TARGET_POWERPC && ! TARGET_POWER" 2399 "div<wd>u %0,%1,%2" 2400 [(set_attr "type" "idiv")]) 2401 2402;; For powers of two we can do srai/aze for divide and then adjust for 2403;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be 2404;; used; for PowerPC, force operands into register and do a normal divide; 2405;; for AIX common-mode, use quoss call on register operands. 2406(define_expand "div<mode>3" 2407 [(set (match_operand:GPR 0 "gpc_reg_operand" "") 2408 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 2409 (match_operand:GPR 2 "reg_or_cint_operand" "")))] 2410 "" 2411 " 2412{ 2413 if (GET_CODE (operands[2]) == CONST_INT 2414 && INTVAL (operands[2]) > 0 2415 && exact_log2 (INTVAL (operands[2])) >= 0) 2416 ; 2417 else if (TARGET_POWERPC) 2418 { 2419 operands[2] = force_reg (<MODE>mode, operands[2]); 2420 if (TARGET_POWER) 2421 { 2422 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); 2423 DONE; 2424 } 2425 } 2426 else if (TARGET_POWER) 2427 FAIL; 2428 else 2429 { 2430 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 2431 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 2432 emit_insn (gen_quoss_call ()); 2433 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 2434 DONE; 2435 } 2436}") 2437 2438(define_insn "divsi3_mq" 2439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2440 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2441 (match_operand:SI 2 "gpc_reg_operand" "r"))) 2442 (clobber (match_scratch:SI 3 "=q"))] 2443 "TARGET_POWERPC && TARGET_POWER" 2444 "divw %0,%1,%2" 2445 [(set_attr "type" "idiv")]) 2446 2447(define_insn "*div<mode>3_no_mq" 2448 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2449 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") 2450 (match_operand:GPR 2 "gpc_reg_operand" "r")))] 2451 "TARGET_POWERPC && ! TARGET_POWER" 2452 "div<wd> %0,%1,%2" 2453 [(set_attr "type" "idiv")]) 2454 2455(define_expand "mod<mode>3" 2456 [(use (match_operand:GPR 0 "gpc_reg_operand" "")) 2457 (use (match_operand:GPR 1 "gpc_reg_operand" "")) 2458 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))] 2459 "" 2460 " 2461{ 2462 int i; 2463 rtx temp1; 2464 rtx temp2; 2465 2466 if (GET_CODE (operands[2]) != CONST_INT 2467 || INTVAL (operands[2]) <= 0 2468 || (i = exact_log2 (INTVAL (operands[2]))) < 0) 2469 FAIL; 2470 2471 temp1 = gen_reg_rtx (<MODE>mode); 2472 temp2 = gen_reg_rtx (<MODE>mode); 2473 2474 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2])); 2475 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i))); 2476 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2)); 2477 DONE; 2478}") 2479 2480(define_insn "" 2481 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2482 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") 2483 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))] 2484 "" 2485 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0" 2486 [(set_attr "type" "two") 2487 (set_attr "length" "8")]) 2488 2489(define_insn "" 2490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2491 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") 2492 (match_operand:P 2 "exact_log2_cint_operand" "N,N")) 2493 (const_int 0))) 2494 (clobber (match_scratch:P 3 "=r,r"))] 2495 "" 2496 "@ 2497 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3 2498 #" 2499 [(set_attr "type" "compare") 2500 (set_attr "length" "8,12")]) 2501 2502(define_split 2503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2504 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 2505 (match_operand:GPR 2 "exact_log2_cint_operand" 2506 "")) 2507 (const_int 0))) 2508 (clobber (match_scratch:GPR 3 ""))] 2509 "reload_completed" 2510 [(set (match_dup 3) 2511 (div:<MODE> (match_dup 1) (match_dup 2))) 2512 (set (match_dup 0) 2513 (compare:CC (match_dup 3) 2514 (const_int 0)))] 2515 "") 2516 2517(define_insn "" 2518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2519 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") 2520 (match_operand:P 2 "exact_log2_cint_operand" "N,N")) 2521 (const_int 0))) 2522 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 2523 (div:P (match_dup 1) (match_dup 2)))] 2524 "" 2525 "@ 2526 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0 2527 #" 2528 [(set_attr "type" "compare") 2529 (set_attr "length" "8,12")]) 2530 2531(define_split 2532 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2533 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 2534 (match_operand:GPR 2 "exact_log2_cint_operand" 2535 "")) 2536 (const_int 0))) 2537 (set (match_operand:GPR 0 "gpc_reg_operand" "") 2538 (div:GPR (match_dup 1) (match_dup 2)))] 2539 "reload_completed" 2540 [(set (match_dup 0) 2541 (div:<MODE> (match_dup 1) (match_dup 2))) 2542 (set (match_dup 3) 2543 (compare:CC (match_dup 0) 2544 (const_int 0)))] 2545 "") 2546 2547(define_insn "" 2548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2549 (udiv:SI 2550 (plus:DI (ashift:DI 2551 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 2552 (const_int 32)) 2553 (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) 2554 (match_operand:SI 3 "gpc_reg_operand" "r"))) 2555 (set (match_operand:SI 2 "register_operand" "=*q") 2556 (umod:SI 2557 (plus:DI (ashift:DI 2558 (zero_extend:DI (match_dup 1)) (const_int 32)) 2559 (zero_extend:DI (match_dup 4))) 2560 (match_dup 3)))] 2561 "TARGET_POWER" 2562 "div %0,%1,%3" 2563 [(set_attr "type" "idiv")]) 2564 2565;; To do unsigned divide we handle the cases of the divisor looking like a 2566;; negative number. If it is a constant that is less than 2**31, we don't 2567;; have to worry about the branches. So make a few subroutines here. 2568;; 2569;; First comes the normal case. 2570(define_expand "udivmodsi4_normal" 2571 [(set (match_dup 4) (const_int 0)) 2572 (parallel [(set (match_operand:SI 0 "" "") 2573 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 2574 (const_int 32)) 2575 (zero_extend:DI (match_operand:SI 1 "" ""))) 2576 (match_operand:SI 2 "" ""))) 2577 (set (match_operand:SI 3 "" "") 2578 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 2579 (const_int 32)) 2580 (zero_extend:DI (match_dup 1))) 2581 (match_dup 2)))])] 2582 "TARGET_POWER" 2583 " 2584{ operands[4] = gen_reg_rtx (SImode); }") 2585 2586;; This handles the branches. 2587(define_expand "udivmodsi4_tests" 2588 [(set (match_operand:SI 0 "" "") (const_int 0)) 2589 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) 2590 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) 2591 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) 2592 (label_ref (match_operand:SI 4 "" "")) (pc))) 2593 (set (match_dup 0) (const_int 1)) 2594 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) 2595 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) 2596 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) 2597 (label_ref (match_dup 4)) (pc)))] 2598 "TARGET_POWER" 2599 " 2600{ operands[5] = gen_reg_rtx (CCUNSmode); 2601 operands[6] = gen_reg_rtx (CCmode); 2602}") 2603 2604(define_expand "udivmodsi4" 2605 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 2606 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 2607 (match_operand:SI 2 "reg_or_cint_operand" ""))) 2608 (set (match_operand:SI 3 "gpc_reg_operand" "") 2609 (umod:SI (match_dup 1) (match_dup 2)))])] 2610 "" 2611 " 2612{ 2613 rtx label = 0; 2614 2615 if (! TARGET_POWER) 2616 { 2617 if (! TARGET_POWERPC) 2618 { 2619 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 2620 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 2621 emit_insn (gen_divus_call ()); 2622 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 2623 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); 2624 DONE; 2625 } 2626 else 2627 FAIL; 2628 } 2629 2630 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) 2631 { 2632 operands[2] = force_reg (SImode, operands[2]); 2633 label = gen_label_rtx (); 2634 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], 2635 operands[3], label)); 2636 } 2637 else 2638 operands[2] = force_reg (SImode, operands[2]); 2639 2640 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], 2641 operands[3])); 2642 if (label) 2643 emit_label (label); 2644 2645 DONE; 2646}") 2647 2648;; AIX architecture-independent common-mode multiply (DImode), 2649;; divide/modulus, and quotient subroutine calls. Input operands in R3 and 2650;; R4; results in R3 and sometimes R4; link register always clobbered by bla 2651;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but 2652;; assumed unused if generating common-mode, so ignore. 2653(define_insn "mulh_call" 2654 [(set (reg:SI 3) 2655 (truncate:SI 2656 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) 2657 (sign_extend:DI (reg:SI 4))) 2658 (const_int 32)))) 2659 (clobber (match_scratch:SI 0 "=l"))] 2660 "! TARGET_POWER && ! TARGET_POWERPC" 2661 "bla __mulh" 2662 [(set_attr "type" "imul")]) 2663 2664(define_insn "mull_call" 2665 [(set (reg:DI 3) 2666 (mult:DI (sign_extend:DI (reg:SI 3)) 2667 (sign_extend:DI (reg:SI 4)))) 2668 (clobber (match_scratch:SI 0 "=l")) 2669 (clobber (reg:SI 0))] 2670 "! TARGET_POWER && ! TARGET_POWERPC" 2671 "bla __mull" 2672 [(set_attr "type" "imul")]) 2673 2674(define_insn "divss_call" 2675 [(set (reg:SI 3) 2676 (div:SI (reg:SI 3) (reg:SI 4))) 2677 (set (reg:SI 4) 2678 (mod:SI (reg:SI 3) (reg:SI 4))) 2679 (clobber (match_scratch:SI 0 "=l")) 2680 (clobber (reg:SI 0))] 2681 "! TARGET_POWER && ! TARGET_POWERPC" 2682 "bla __divss" 2683 [(set_attr "type" "idiv")]) 2684 2685(define_insn "divus_call" 2686 [(set (reg:SI 3) 2687 (udiv:SI (reg:SI 3) (reg:SI 4))) 2688 (set (reg:SI 4) 2689 (umod:SI (reg:SI 3) (reg:SI 4))) 2690 (clobber (match_scratch:SI 0 "=l")) 2691 (clobber (reg:SI 0)) 2692 (clobber (match_scratch:CC 1 "=x")) 2693 (clobber (reg:CC 69))] 2694 "! TARGET_POWER && ! TARGET_POWERPC" 2695 "bla __divus" 2696 [(set_attr "type" "idiv")]) 2697 2698(define_insn "quoss_call" 2699 [(set (reg:SI 3) 2700 (div:SI (reg:SI 3) (reg:SI 4))) 2701 (clobber (match_scratch:SI 0 "=l"))] 2702 "! TARGET_POWER && ! TARGET_POWERPC" 2703 "bla __quoss" 2704 [(set_attr "type" "idiv")]) 2705 2706(define_insn "quous_call" 2707 [(set (reg:SI 3) 2708 (udiv:SI (reg:SI 3) (reg:SI 4))) 2709 (clobber (match_scratch:SI 0 "=l")) 2710 (clobber (reg:SI 0)) 2711 (clobber (match_scratch:CC 1 "=x")) 2712 (clobber (reg:CC 69))] 2713 "! TARGET_POWER && ! TARGET_POWERPC" 2714 "bla __quous" 2715 [(set_attr "type" "idiv")]) 2716 2717;; Logical instructions 2718;; The logical instructions are mostly combined by using match_operator, 2719;; but the plain AND insns are somewhat different because there is no 2720;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all 2721;; those rotate-and-mask operations. Thus, the AND insns come first. 2722 2723(define_insn "andsi3" 2724 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 2725 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 2726 (match_operand:SI 2 "and_operand" "?r,T,K,L"))) 2727 (clobber (match_scratch:CC 3 "=X,X,x,x"))] 2728 "" 2729 "@ 2730 and %0,%1,%2 2731 {rlinm|rlwinm} %0,%1,0,%m2,%M2 2732 {andil.|andi.} %0,%1,%b2 2733 {andiu.|andis.} %0,%1,%u2" 2734 [(set_attr "type" "*,*,compare,compare")]) 2735 2736;; Note to set cr's other than cr0 we do the and immediate and then 2737;; the test again -- this avoids a mfcr which on the higher end 2738;; machines causes an execution serialization 2739 2740(define_insn "*andsi3_internal2" 2741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2742 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2743 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2744 (const_int 0))) 2745 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) 2746 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2747 "TARGET_32BIT" 2748 "@ 2749 and. %3,%1,%2 2750 {andil.|andi.} %3,%1,%b2 2751 {andiu.|andis.} %3,%1,%u2 2752 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 2753 # 2754 # 2755 # 2756 #" 2757 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2758 (set_attr "length" "4,4,4,4,8,8,8,8")]) 2759 2760(define_insn "*andsi3_internal3" 2761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2762 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2763 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2764 (const_int 0))) 2765 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) 2766 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2767 "TARGET_64BIT" 2768 "@ 2769 # 2770 {andil.|andi.} %3,%1,%b2 2771 {andiu.|andis.} %3,%1,%u2 2772 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 2773 # 2774 # 2775 # 2776 #" 2777 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2778 (set_attr "length" "8,4,4,4,8,8,8,8")]) 2779 2780(define_split 2781 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2782 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 2783 (match_operand:GPR 2 "and_operand" "")) 2784 (const_int 0))) 2785 (clobber (match_scratch:GPR 3 "")) 2786 (clobber (match_scratch:CC 4 ""))] 2787 "reload_completed" 2788 [(parallel [(set (match_dup 3) 2789 (and:<MODE> (match_dup 1) 2790 (match_dup 2))) 2791 (clobber (match_dup 4))]) 2792 (set (match_dup 0) 2793 (compare:CC (match_dup 3) 2794 (const_int 0)))] 2795 "") 2796 2797;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the 2798;; whole 64 bit reg, and we don't know what is in the high 32 bits. 2799 2800(define_split 2801 [(set (match_operand:CC 0 "cc_reg_operand" "") 2802 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2803 (match_operand:SI 2 "gpc_reg_operand" "")) 2804 (const_int 0))) 2805 (clobber (match_scratch:SI 3 "")) 2806 (clobber (match_scratch:CC 4 ""))] 2807 "TARGET_POWERPC64 && reload_completed" 2808 [(parallel [(set (match_dup 3) 2809 (and:SI (match_dup 1) 2810 (match_dup 2))) 2811 (clobber (match_dup 4))]) 2812 (set (match_dup 0) 2813 (compare:CC (match_dup 3) 2814 (const_int 0)))] 2815 "") 2816 2817(define_insn "*andsi3_internal4" 2818 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2819 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2820 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2821 (const_int 0))) 2822 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") 2823 (and:SI (match_dup 1) 2824 (match_dup 2))) 2825 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2826 "TARGET_32BIT" 2827 "@ 2828 and. %0,%1,%2 2829 {andil.|andi.} %0,%1,%b2 2830 {andiu.|andis.} %0,%1,%u2 2831 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 2832 # 2833 # 2834 # 2835 #" 2836 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2837 (set_attr "length" "4,4,4,4,8,8,8,8")]) 2838 2839(define_insn "*andsi3_internal5" 2840 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2841 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2842 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2843 (const_int 0))) 2844 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") 2845 (and:SI (match_dup 1) 2846 (match_dup 2))) 2847 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2848 "TARGET_64BIT" 2849 "@ 2850 # 2851 {andil.|andi.} %0,%1,%b2 2852 {andiu.|andis.} %0,%1,%u2 2853 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 2854 # 2855 # 2856 # 2857 #" 2858 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2859 (set_attr "length" "8,4,4,4,8,8,8,8")]) 2860 2861(define_split 2862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2863 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2864 (match_operand:SI 2 "and_operand" "")) 2865 (const_int 0))) 2866 (set (match_operand:SI 0 "gpc_reg_operand" "") 2867 (and:SI (match_dup 1) 2868 (match_dup 2))) 2869 (clobber (match_scratch:CC 4 ""))] 2870 "reload_completed" 2871 [(parallel [(set (match_dup 0) 2872 (and:SI (match_dup 1) 2873 (match_dup 2))) 2874 (clobber (match_dup 4))]) 2875 (set (match_dup 3) 2876 (compare:CC (match_dup 0) 2877 (const_int 0)))] 2878 "") 2879 2880(define_split 2881 [(set (match_operand:CC 3 "cc_reg_operand" "") 2882 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2883 (match_operand:SI 2 "gpc_reg_operand" "")) 2884 (const_int 0))) 2885 (set (match_operand:SI 0 "gpc_reg_operand" "") 2886 (and:SI (match_dup 1) 2887 (match_dup 2))) 2888 (clobber (match_scratch:CC 4 ""))] 2889 "TARGET_POWERPC64 && reload_completed" 2890 [(parallel [(set (match_dup 0) 2891 (and:SI (match_dup 1) 2892 (match_dup 2))) 2893 (clobber (match_dup 4))]) 2894 (set (match_dup 3) 2895 (compare:CC (match_dup 0) 2896 (const_int 0)))] 2897 "") 2898 2899;; Handle the PowerPC64 rlwinm corner case 2900 2901(define_insn_and_split "*andsi3_internal6" 2902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2903 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2904 (match_operand:SI 2 "mask_operand_wrap" "i")))] 2905 "TARGET_POWERPC64" 2906 "#" 2907 "TARGET_POWERPC64" 2908 [(set (match_dup 0) 2909 (and:SI (rotate:SI (match_dup 1) (match_dup 3)) 2910 (match_dup 4))) 2911 (set (match_dup 0) 2912 (rotate:SI (match_dup 0) (match_dup 5)))] 2913 " 2914{ 2915 int mb = extract_MB (operands[2]); 2916 int me = extract_ME (operands[2]); 2917 operands[3] = GEN_INT (me + 1); 2918 operands[5] = GEN_INT (32 - (me + 1)); 2919 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); 2920}" 2921 [(set_attr "length" "8")]) 2922 2923(define_expand "iorsi3" 2924 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2925 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") 2926 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] 2927 "" 2928 " 2929{ 2930 if (GET_CODE (operands[2]) == CONST_INT 2931 && ! logical_operand (operands[2], SImode)) 2932 { 2933 HOST_WIDE_INT value = INTVAL (operands[2]); 2934 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 2935 ? operands[0] : gen_reg_rtx (SImode)); 2936 2937 emit_insn (gen_iorsi3 (tmp, operands[1], 2938 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 2939 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 2940 DONE; 2941 } 2942}") 2943 2944(define_expand "xorsi3" 2945 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2946 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 2947 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] 2948 "" 2949 " 2950{ 2951 if (GET_CODE (operands[2]) == CONST_INT 2952 && ! logical_operand (operands[2], SImode)) 2953 { 2954 HOST_WIDE_INT value = INTVAL (operands[2]); 2955 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 2956 ? operands[0] : gen_reg_rtx (SImode)); 2957 2958 emit_insn (gen_xorsi3 (tmp, operands[1], 2959 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 2960 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 2961 DONE; 2962 } 2963}") 2964 2965(define_insn "*boolsi3_internal1" 2966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 2967 (match_operator:SI 3 "boolean_or_operator" 2968 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 2969 (match_operand:SI 2 "logical_operand" "r,K,L")]))] 2970 "" 2971 "@ 2972 %q3 %0,%1,%2 2973 {%q3il|%q3i} %0,%1,%b2 2974 {%q3iu|%q3is} %0,%1,%u2") 2975 2976(define_insn "*boolsi3_internal2" 2977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2978 (compare:CC (match_operator:SI 4 "boolean_or_operator" 2979 [(match_operand:SI 1 "gpc_reg_operand" "%r,r") 2980 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 2981 (const_int 0))) 2982 (clobber (match_scratch:SI 3 "=r,r"))] 2983 "TARGET_32BIT" 2984 "@ 2985 %q4. %3,%1,%2 2986 #" 2987 [(set_attr "type" "compare") 2988 (set_attr "length" "4,8")]) 2989 2990(define_split 2991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2992 (compare:CC (match_operator:SI 4 "boolean_operator" 2993 [(match_operand:SI 1 "gpc_reg_operand" "") 2994 (match_operand:SI 2 "gpc_reg_operand" "")]) 2995 (const_int 0))) 2996 (clobber (match_scratch:SI 3 ""))] 2997 "TARGET_32BIT && reload_completed" 2998 [(set (match_dup 3) (match_dup 4)) 2999 (set (match_dup 0) 3000 (compare:CC (match_dup 3) 3001 (const_int 0)))] 3002 "") 3003 3004(define_insn "*boolsi3_internal3" 3005 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3006 (compare:CC (match_operator:SI 4 "boolean_operator" 3007 [(match_operand:SI 1 "gpc_reg_operand" "%r,r") 3008 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 3009 (const_int 0))) 3010 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3011 (match_dup 4))] 3012 "TARGET_32BIT" 3013 "@ 3014 %q4. %0,%1,%2 3015 #" 3016 [(set_attr "type" "compare") 3017 (set_attr "length" "4,8")]) 3018 3019(define_split 3020 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3021 (compare:CC (match_operator:SI 4 "boolean_operator" 3022 [(match_operand:SI 1 "gpc_reg_operand" "") 3023 (match_operand:SI 2 "gpc_reg_operand" "")]) 3024 (const_int 0))) 3025 (set (match_operand:SI 0 "gpc_reg_operand" "") 3026 (match_dup 4))] 3027 "TARGET_32BIT && reload_completed" 3028 [(set (match_dup 0) (match_dup 4)) 3029 (set (match_dup 3) 3030 (compare:CC (match_dup 0) 3031 (const_int 0)))] 3032 "") 3033 3034;; Split a logical operation that we can't do in one insn into two insns, 3035;; each of which does one 16-bit part. This is used by combine. 3036 3037(define_split 3038 [(set (match_operand:SI 0 "gpc_reg_operand" "") 3039 (match_operator:SI 3 "boolean_or_operator" 3040 [(match_operand:SI 1 "gpc_reg_operand" "") 3041 (match_operand:SI 2 "non_logical_cint_operand" "")]))] 3042 "" 3043 [(set (match_dup 0) (match_dup 4)) 3044 (set (match_dup 0) (match_dup 5))] 3045" 3046{ 3047 rtx i; 3048 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); 3049 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 3050 operands[1], i); 3051 i = GEN_INT (INTVAL (operands[2]) & 0xffff); 3052 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 3053 operands[0], i); 3054}") 3055 3056(define_insn "*boolcsi3_internal1" 3057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3058 (match_operator:SI 3 "boolean_operator" 3059 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 3060 (match_operand:SI 2 "gpc_reg_operand" "r")]))] 3061 "" 3062 "%q3 %0,%2,%1") 3063 3064(define_insn "*boolcsi3_internal2" 3065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3066 (compare:CC (match_operator:SI 4 "boolean_operator" 3067 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 3068 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 3069 (const_int 0))) 3070 (clobber (match_scratch:SI 3 "=r,r"))] 3071 "TARGET_32BIT" 3072 "@ 3073 %q4. %3,%2,%1 3074 #" 3075 [(set_attr "type" "compare") 3076 (set_attr "length" "4,8")]) 3077 3078(define_split 3079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3080 (compare:CC (match_operator:SI 4 "boolean_operator" 3081 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3082 (match_operand:SI 2 "gpc_reg_operand" "")]) 3083 (const_int 0))) 3084 (clobber (match_scratch:SI 3 ""))] 3085 "TARGET_32BIT && reload_completed" 3086 [(set (match_dup 3) (match_dup 4)) 3087 (set (match_dup 0) 3088 (compare:CC (match_dup 3) 3089 (const_int 0)))] 3090 "") 3091 3092(define_insn "*boolcsi3_internal3" 3093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3094 (compare:CC (match_operator:SI 4 "boolean_operator" 3095 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) 3096 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 3097 (const_int 0))) 3098 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3099 (match_dup 4))] 3100 "TARGET_32BIT" 3101 "@ 3102 %q4. %0,%2,%1 3103 #" 3104 [(set_attr "type" "compare") 3105 (set_attr "length" "4,8")]) 3106 3107(define_split 3108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3109 (compare:CC (match_operator:SI 4 "boolean_operator" 3110 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3111 (match_operand:SI 2 "gpc_reg_operand" "")]) 3112 (const_int 0))) 3113 (set (match_operand:SI 0 "gpc_reg_operand" "") 3114 (match_dup 4))] 3115 "TARGET_32BIT && reload_completed" 3116 [(set (match_dup 0) (match_dup 4)) 3117 (set (match_dup 3) 3118 (compare:CC (match_dup 0) 3119 (const_int 0)))] 3120 "") 3121 3122(define_insn "*boolccsi3_internal1" 3123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3124 (match_operator:SI 3 "boolean_operator" 3125 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 3126 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] 3127 "" 3128 "%q3 %0,%1,%2") 3129 3130(define_insn "*boolccsi3_internal2" 3131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3132 (compare:CC (match_operator:SI 4 "boolean_operator" 3133 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 3134 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) 3135 (const_int 0))) 3136 (clobber (match_scratch:SI 3 "=r,r"))] 3137 "TARGET_32BIT" 3138 "@ 3139 %q4. %3,%1,%2 3140 #" 3141 [(set_attr "type" "compare") 3142 (set_attr "length" "4,8")]) 3143 3144(define_split 3145 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3146 (compare:CC (match_operator:SI 4 "boolean_operator" 3147 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3148 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) 3149 (const_int 0))) 3150 (clobber (match_scratch:SI 3 ""))] 3151 "TARGET_32BIT && reload_completed" 3152 [(set (match_dup 3) (match_dup 4)) 3153 (set (match_dup 0) 3154 (compare:CC (match_dup 3) 3155 (const_int 0)))] 3156 "") 3157 3158(define_insn "*boolccsi3_internal3" 3159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3160 (compare:CC (match_operator:SI 4 "boolean_operator" 3161 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) 3162 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) 3163 (const_int 0))) 3164 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3165 (match_dup 4))] 3166 "TARGET_32BIT" 3167 "@ 3168 %q4. %0,%1,%2 3169 #" 3170 [(set_attr "type" "compare") 3171 (set_attr "length" "4,8")]) 3172 3173(define_split 3174 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3175 (compare:CC (match_operator:SI 4 "boolean_operator" 3176 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3177 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) 3178 (const_int 0))) 3179 (set (match_operand:SI 0 "gpc_reg_operand" "") 3180 (match_dup 4))] 3181 "TARGET_32BIT && reload_completed" 3182 [(set (match_dup 0) (match_dup 4)) 3183 (set (match_dup 3) 3184 (compare:CC (match_dup 0) 3185 (const_int 0)))] 3186 "") 3187 3188;; maskir insn. We need four forms because things might be in arbitrary 3189;; orders. Don't define forms that only set CR fields because these 3190;; would modify an input register. 3191 3192(define_insn "*maskir_internal1" 3193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3194 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 3195 (match_operand:SI 1 "gpc_reg_operand" "0")) 3196 (and:SI (match_dup 2) 3197 (match_operand:SI 3 "gpc_reg_operand" "r"))))] 3198 "TARGET_POWER" 3199 "maskir %0,%3,%2") 3200 3201(define_insn "*maskir_internal2" 3202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3203 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 3204 (match_operand:SI 1 "gpc_reg_operand" "0")) 3205 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3206 (match_dup 2))))] 3207 "TARGET_POWER" 3208 "maskir %0,%3,%2") 3209 3210(define_insn "*maskir_internal3" 3211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3212 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") 3213 (match_operand:SI 3 "gpc_reg_operand" "r")) 3214 (and:SI (not:SI (match_dup 2)) 3215 (match_operand:SI 1 "gpc_reg_operand" "0"))))] 3216 "TARGET_POWER" 3217 "maskir %0,%3,%2") 3218 3219(define_insn "*maskir_internal4" 3220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3221 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3222 (match_operand:SI 2 "gpc_reg_operand" "r")) 3223 (and:SI (not:SI (match_dup 2)) 3224 (match_operand:SI 1 "gpc_reg_operand" "0"))))] 3225 "TARGET_POWER" 3226 "maskir %0,%3,%2") 3227 3228(define_insn "*maskir_internal5" 3229 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3230 (compare:CC 3231 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) 3232 (match_operand:SI 1 "gpc_reg_operand" "0,0")) 3233 (and:SI (match_dup 2) 3234 (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 3235 (const_int 0))) 3236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3237 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3238 (and:SI (match_dup 2) (match_dup 3))))] 3239 "TARGET_POWER" 3240 "@ 3241 maskir. %0,%3,%2 3242 #" 3243 [(set_attr "type" "compare") 3244 (set_attr "length" "4,8")]) 3245 3246(define_split 3247 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3248 (compare:CC 3249 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) 3250 (match_operand:SI 1 "gpc_reg_operand" "")) 3251 (and:SI (match_dup 2) 3252 (match_operand:SI 3 "gpc_reg_operand" ""))) 3253 (const_int 0))) 3254 (set (match_operand:SI 0 "gpc_reg_operand" "") 3255 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3256 (and:SI (match_dup 2) (match_dup 3))))] 3257 "TARGET_POWER && reload_completed" 3258 [(set (match_dup 0) 3259 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3260 (and:SI (match_dup 2) (match_dup 3)))) 3261 (set (match_dup 4) 3262 (compare:CC (match_dup 0) 3263 (const_int 0)))] 3264 "") 3265 3266(define_insn "*maskir_internal6" 3267 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3268 (compare:CC 3269 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) 3270 (match_operand:SI 1 "gpc_reg_operand" "0,0")) 3271 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") 3272 (match_dup 2))) 3273 (const_int 0))) 3274 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3275 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3276 (and:SI (match_dup 3) (match_dup 2))))] 3277 "TARGET_POWER" 3278 "@ 3279 maskir. %0,%3,%2 3280 #" 3281 [(set_attr "type" "compare") 3282 (set_attr "length" "4,8")]) 3283 3284(define_split 3285 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3286 (compare:CC 3287 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) 3288 (match_operand:SI 1 "gpc_reg_operand" "")) 3289 (and:SI (match_operand:SI 3 "gpc_reg_operand" "") 3290 (match_dup 2))) 3291 (const_int 0))) 3292 (set (match_operand:SI 0 "gpc_reg_operand" "") 3293 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3294 (and:SI (match_dup 3) (match_dup 2))))] 3295 "TARGET_POWER && reload_completed" 3296 [(set (match_dup 0) 3297 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3298 (and:SI (match_dup 3) (match_dup 2)))) 3299 (set (match_dup 4) 3300 (compare:CC (match_dup 0) 3301 (const_int 0)))] 3302 "") 3303 3304(define_insn "*maskir_internal7" 3305 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3306 (compare:CC 3307 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") 3308 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 3309 (and:SI (not:SI (match_dup 2)) 3310 (match_operand:SI 1 "gpc_reg_operand" "0,0"))) 3311 (const_int 0))) 3312 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3313 (ior:SI (and:SI (match_dup 2) (match_dup 3)) 3314 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 3315 "TARGET_POWER" 3316 "@ 3317 maskir. %0,%3,%2 3318 #" 3319 [(set_attr "type" "compare") 3320 (set_attr "length" "4,8")]) 3321 3322(define_split 3323 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3324 (compare:CC 3325 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") 3326 (match_operand:SI 3 "gpc_reg_operand" "")) 3327 (and:SI (not:SI (match_dup 2)) 3328 (match_operand:SI 1 "gpc_reg_operand" ""))) 3329 (const_int 0))) 3330 (set (match_operand:SI 0 "gpc_reg_operand" "") 3331 (ior:SI (and:SI (match_dup 2) (match_dup 3)) 3332 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 3333 "TARGET_POWER && reload_completed" 3334 [(set (match_dup 0) 3335 (ior:SI (and:SI (match_dup 2) (match_dup 3)) 3336 (and:SI (not:SI (match_dup 2)) (match_dup 1)))) 3337 (set (match_dup 4) 3338 (compare:CC (match_dup 0) 3339 (const_int 0)))] 3340 "") 3341 3342(define_insn "*maskir_internal8" 3343 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3344 (compare:CC 3345 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") 3346 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 3347 (and:SI (not:SI (match_dup 2)) 3348 (match_operand:SI 1 "gpc_reg_operand" "0,0"))) 3349 (const_int 0))) 3350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3351 (ior:SI (and:SI (match_dup 3) (match_dup 2)) 3352 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 3353 "TARGET_POWER" 3354 "@ 3355 maskir. %0,%3,%2 3356 #" 3357 [(set_attr "type" "compare") 3358 (set_attr "length" "4,8")]) 3359 3360(define_split 3361 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3362 (compare:CC 3363 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") 3364 (match_operand:SI 2 "gpc_reg_operand" "")) 3365 (and:SI (not:SI (match_dup 2)) 3366 (match_operand:SI 1 "gpc_reg_operand" ""))) 3367 (const_int 0))) 3368 (set (match_operand:SI 0 "gpc_reg_operand" "") 3369 (ior:SI (and:SI (match_dup 3) (match_dup 2)) 3370 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 3371 "TARGET_POWER && reload_completed" 3372 [(set (match_dup 0) 3373 (ior:SI (and:SI (match_dup 3) (match_dup 2)) 3374 (and:SI (not:SI (match_dup 2)) (match_dup 1)))) 3375 (set (match_dup 4) 3376 (compare:CC (match_dup 0) 3377 (const_int 0)))] 3378 "") 3379 3380;; Rotate and shift insns, in all their variants. These support shifts, 3381;; field inserts and extracts, and various combinations thereof. 3382(define_expand "insv" 3383 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") 3384 (match_operand:SI 1 "const_int_operand" "") 3385 (match_operand:SI 2 "const_int_operand" "")) 3386 (match_operand 3 "gpc_reg_operand" ""))] 3387 "" 3388 " 3389{ 3390 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 3391 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 3392 compiler if the address of the structure is taken later. Likewise, do 3393 not handle invalid E500 subregs. */ 3394 if (GET_CODE (operands[0]) == SUBREG 3395 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD 3396 || ((TARGET_E500_DOUBLE || TARGET_SPE) 3397 && invalid_e500_subreg (operands[0], GET_MODE (operands[0]))))) 3398 FAIL; 3399 3400 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) 3401 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); 3402 else 3403 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); 3404 DONE; 3405}") 3406 3407(define_insn "insvsi" 3408 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3409 (match_operand:SI 1 "const_int_operand" "i") 3410 (match_operand:SI 2 "const_int_operand" "i")) 3411 (match_operand:SI 3 "gpc_reg_operand" "r"))] 3412 "" 3413 "* 3414{ 3415 int start = INTVAL (operands[2]) & 31; 3416 int size = INTVAL (operands[1]) & 31; 3417 3418 operands[4] = GEN_INT (32 - start - size); 3419 operands[1] = GEN_INT (start + size - 1); 3420 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3421}" 3422 [(set_attr "type" "insert_word")]) 3423 3424(define_insn "*insvsi_internal1" 3425 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3426 (match_operand:SI 1 "const_int_operand" "i") 3427 (match_operand:SI 2 "const_int_operand" "i")) 3428 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3429 (match_operand:SI 4 "const_int_operand" "i")))] 3430 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 3431 "* 3432{ 3433 int shift = INTVAL (operands[4]) & 31; 3434 int start = INTVAL (operands[2]) & 31; 3435 int size = INTVAL (operands[1]) & 31; 3436 3437 operands[4] = GEN_INT (shift - start - size); 3438 operands[1] = GEN_INT (start + size - 1); 3439 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3440}" 3441 [(set_attr "type" "insert_word")]) 3442 3443(define_insn "*insvsi_internal2" 3444 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3445 (match_operand:SI 1 "const_int_operand" "i") 3446 (match_operand:SI 2 "const_int_operand" "i")) 3447 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3448 (match_operand:SI 4 "const_int_operand" "i")))] 3449 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 3450 "* 3451{ 3452 int shift = INTVAL (operands[4]) & 31; 3453 int start = INTVAL (operands[2]) & 31; 3454 int size = INTVAL (operands[1]) & 31; 3455 3456 operands[4] = GEN_INT (32 - shift - start - size); 3457 operands[1] = GEN_INT (start + size - 1); 3458 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3459}" 3460 [(set_attr "type" "insert_word")]) 3461 3462(define_insn "*insvsi_internal3" 3463 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3464 (match_operand:SI 1 "const_int_operand" "i") 3465 (match_operand:SI 2 "const_int_operand" "i")) 3466 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3467 (match_operand:SI 4 "const_int_operand" "i")))] 3468 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 3469 "* 3470{ 3471 int shift = INTVAL (operands[4]) & 31; 3472 int start = INTVAL (operands[2]) & 31; 3473 int size = INTVAL (operands[1]) & 31; 3474 3475 operands[4] = GEN_INT (32 - shift - start - size); 3476 operands[1] = GEN_INT (start + size - 1); 3477 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3478}" 3479 [(set_attr "type" "insert_word")]) 3480 3481(define_insn "*insvsi_internal4" 3482 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3483 (match_operand:SI 1 "const_int_operand" "i") 3484 (match_operand:SI 2 "const_int_operand" "i")) 3485 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3486 (match_operand:SI 4 "const_int_operand" "i") 3487 (match_operand:SI 5 "const_int_operand" "i")))] 3488 "INTVAL (operands[4]) >= INTVAL (operands[1])" 3489 "* 3490{ 3491 int extract_start = INTVAL (operands[5]) & 31; 3492 int extract_size = INTVAL (operands[4]) & 31; 3493 int insert_start = INTVAL (operands[2]) & 31; 3494 int insert_size = INTVAL (operands[1]) & 31; 3495 3496/* Align extract field with insert field */ 3497 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); 3498 operands[1] = GEN_INT (insert_start + insert_size - 1); 3499 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; 3500}" 3501 [(set_attr "type" "insert_word")]) 3502 3503;; combine patterns for rlwimi 3504(define_insn "*insvsi_internal5" 3505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3506 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") 3507 (match_operand:SI 1 "mask_operand" "i")) 3508 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3509 (match_operand:SI 2 "const_int_operand" "i")) 3510 (match_operand:SI 5 "mask_operand" "i"))))] 3511 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" 3512 "* 3513{ 3514 int me = extract_ME(operands[5]); 3515 int mb = extract_MB(operands[5]); 3516 operands[4] = GEN_INT(32 - INTVAL(operands[2])); 3517 operands[2] = GEN_INT(mb); 3518 operands[1] = GEN_INT(me); 3519 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3520}" 3521 [(set_attr "type" "insert_word")]) 3522 3523(define_insn "*insvsi_internal6" 3524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3525 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3526 (match_operand:SI 2 "const_int_operand" "i")) 3527 (match_operand:SI 5 "mask_operand" "i")) 3528 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") 3529 (match_operand:SI 1 "mask_operand" "i"))))] 3530 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" 3531 "* 3532{ 3533 int me = extract_ME(operands[5]); 3534 int mb = extract_MB(operands[5]); 3535 operands[4] = GEN_INT(32 - INTVAL(operands[2])); 3536 operands[2] = GEN_INT(mb); 3537 operands[1] = GEN_INT(me); 3538 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3539}" 3540 [(set_attr "type" "insert_word")]) 3541 3542(define_insn "insvdi" 3543 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") 3544 (match_operand:SI 1 "const_int_operand" "i") 3545 (match_operand:SI 2 "const_int_operand" "i")) 3546 (match_operand:DI 3 "gpc_reg_operand" "r"))] 3547 "TARGET_POWERPC64" 3548 "* 3549{ 3550 int start = INTVAL (operands[2]) & 63; 3551 int size = INTVAL (operands[1]) & 63; 3552 3553 operands[1] = GEN_INT (64 - start - size); 3554 return \"rldimi %0,%3,%H1,%H2\"; 3555}") 3556 3557(define_insn "*insvdi_internal2" 3558 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") 3559 (match_operand:SI 1 "const_int_operand" "i") 3560 (match_operand:SI 2 "const_int_operand" "i")) 3561 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") 3562 (match_operand:SI 4 "const_int_operand" "i")))] 3563 "TARGET_POWERPC64 3564 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" 3565 "* 3566{ 3567 int shift = INTVAL (operands[4]) & 63; 3568 int start = (INTVAL (operands[2]) & 63) - 32; 3569 int size = INTVAL (operands[1]) & 63; 3570 3571 operands[4] = GEN_INT (64 - shift - start - size); 3572 operands[2] = GEN_INT (start); 3573 operands[1] = GEN_INT (start + size - 1); 3574 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3575}") 3576 3577(define_insn "*insvdi_internal3" 3578 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") 3579 (match_operand:SI 1 "const_int_operand" "i") 3580 (match_operand:SI 2 "const_int_operand" "i")) 3581 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") 3582 (match_operand:SI 4 "const_int_operand" "i")))] 3583 "TARGET_POWERPC64 3584 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" 3585 "* 3586{ 3587 int shift = INTVAL (operands[4]) & 63; 3588 int start = (INTVAL (operands[2]) & 63) - 32; 3589 int size = INTVAL (operands[1]) & 63; 3590 3591 operands[4] = GEN_INT (64 - shift - start - size); 3592 operands[2] = GEN_INT (start); 3593 operands[1] = GEN_INT (start + size - 1); 3594 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3595}") 3596 3597(define_expand "extzv" 3598 [(set (match_operand 0 "gpc_reg_operand" "") 3599 (zero_extract (match_operand 1 "gpc_reg_operand" "") 3600 (match_operand:SI 2 "const_int_operand" "") 3601 (match_operand:SI 3 "const_int_operand" "")))] 3602 "" 3603 " 3604{ 3605 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 3606 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 3607 compiler if the address of the structure is taken later. */ 3608 if (GET_CODE (operands[0]) == SUBREG 3609 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) 3610 FAIL; 3611 3612 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) 3613 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); 3614 else 3615 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); 3616 DONE; 3617}") 3618 3619(define_insn "extzvsi" 3620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3621 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3622 (match_operand:SI 2 "const_int_operand" "i") 3623 (match_operand:SI 3 "const_int_operand" "i")))] 3624 "" 3625 "* 3626{ 3627 int start = INTVAL (operands[3]) & 31; 3628 int size = INTVAL (operands[2]) & 31; 3629 3630 if (start + size >= 32) 3631 operands[3] = const0_rtx; 3632 else 3633 operands[3] = GEN_INT (start + size); 3634 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; 3635}") 3636 3637(define_insn "*extzvsi_internal1" 3638 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3639 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3640 (match_operand:SI 2 "const_int_operand" "i,i") 3641 (match_operand:SI 3 "const_int_operand" "i,i")) 3642 (const_int 0))) 3643 (clobber (match_scratch:SI 4 "=r,r"))] 3644 "" 3645 "* 3646{ 3647 int start = INTVAL (operands[3]) & 31; 3648 int size = INTVAL (operands[2]) & 31; 3649 3650 /* Force split for non-cc0 compare. */ 3651 if (which_alternative == 1) 3652 return \"#\"; 3653 3654 /* If the bit-field being tested fits in the upper or lower half of a 3655 word, it is possible to use andiu. or andil. to test it. This is 3656 useful because the condition register set-use delay is smaller for 3657 andi[ul]. than for rlinm. This doesn't work when the starting bit 3658 position is 0 because the LT and GT bits may be set wrong. */ 3659 3660 if ((start > 0 && start + size <= 16) || start >= 16) 3661 { 3662 operands[3] = GEN_INT (((1 << (16 - (start & 15))) 3663 - (1 << (16 - (start & 15) - size)))); 3664 if (start < 16) 3665 return \"{andiu.|andis.} %4,%1,%3\"; 3666 else 3667 return \"{andil.|andi.} %4,%1,%3\"; 3668 } 3669 3670 if (start + size >= 32) 3671 operands[3] = const0_rtx; 3672 else 3673 operands[3] = GEN_INT (start + size); 3674 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; 3675}" 3676 [(set_attr "type" "compare") 3677 (set_attr "length" "4,8")]) 3678 3679(define_split 3680 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3681 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 3682 (match_operand:SI 2 "const_int_operand" "") 3683 (match_operand:SI 3 "const_int_operand" "")) 3684 (const_int 0))) 3685 (clobber (match_scratch:SI 4 ""))] 3686 "reload_completed" 3687 [(set (match_dup 4) 3688 (zero_extract:SI (match_dup 1) (match_dup 2) 3689 (match_dup 3))) 3690 (set (match_dup 0) 3691 (compare:CC (match_dup 4) 3692 (const_int 0)))] 3693 "") 3694 3695(define_insn "*extzvsi_internal2" 3696 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3697 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3698 (match_operand:SI 2 "const_int_operand" "i,i") 3699 (match_operand:SI 3 "const_int_operand" "i,i")) 3700 (const_int 0))) 3701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3702 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 3703 "" 3704 "* 3705{ 3706 int start = INTVAL (operands[3]) & 31; 3707 int size = INTVAL (operands[2]) & 31; 3708 3709 /* Force split for non-cc0 compare. */ 3710 if (which_alternative == 1) 3711 return \"#\"; 3712 3713 /* Since we are using the output value, we can't ignore any need for 3714 a shift. The bit-field must end at the LSB. */ 3715 if (start >= 16 && start + size == 32) 3716 { 3717 operands[3] = GEN_INT ((1 << size) - 1); 3718 return \"{andil.|andi.} %0,%1,%3\"; 3719 } 3720 3721 if (start + size >= 32) 3722 operands[3] = const0_rtx; 3723 else 3724 operands[3] = GEN_INT (start + size); 3725 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; 3726}" 3727 [(set_attr "type" "compare") 3728 (set_attr "length" "4,8")]) 3729 3730(define_split 3731 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3732 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 3733 (match_operand:SI 2 "const_int_operand" "") 3734 (match_operand:SI 3 "const_int_operand" "")) 3735 (const_int 0))) 3736 (set (match_operand:SI 0 "gpc_reg_operand" "") 3737 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 3738 "reload_completed" 3739 [(set (match_dup 0) 3740 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) 3741 (set (match_dup 4) 3742 (compare:CC (match_dup 0) 3743 (const_int 0)))] 3744 "") 3745 3746(define_insn "extzvdi" 3747 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3748 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3749 (match_operand:SI 2 "const_int_operand" "i") 3750 (match_operand:SI 3 "const_int_operand" "i")))] 3751 "TARGET_POWERPC64" 3752 "* 3753{ 3754 int start = INTVAL (operands[3]) & 63; 3755 int size = INTVAL (operands[2]) & 63; 3756 3757 if (start + size >= 64) 3758 operands[3] = const0_rtx; 3759 else 3760 operands[3] = GEN_INT (start + size); 3761 operands[2] = GEN_INT (64 - size); 3762 return \"rldicl %0,%1,%3,%2\"; 3763}") 3764 3765(define_insn "*extzvdi_internal1" 3766 [(set (match_operand:CC 0 "gpc_reg_operand" "=x") 3767 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3768 (match_operand:SI 2 "const_int_operand" "i") 3769 (match_operand:SI 3 "const_int_operand" "i")) 3770 (const_int 0))) 3771 (clobber (match_scratch:DI 4 "=r"))] 3772 "TARGET_64BIT" 3773 "* 3774{ 3775 int start = INTVAL (operands[3]) & 63; 3776 int size = INTVAL (operands[2]) & 63; 3777 3778 if (start + size >= 64) 3779 operands[3] = const0_rtx; 3780 else 3781 operands[3] = GEN_INT (start + size); 3782 operands[2] = GEN_INT (64 - size); 3783 return \"rldicl. %4,%1,%3,%2\"; 3784}" 3785 [(set_attr "type" "compare")]) 3786 3787(define_insn "*extzvdi_internal2" 3788 [(set (match_operand:CC 4 "gpc_reg_operand" "=x") 3789 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3790 (match_operand:SI 2 "const_int_operand" "i") 3791 (match_operand:SI 3 "const_int_operand" "i")) 3792 (const_int 0))) 3793 (set (match_operand:DI 0 "gpc_reg_operand" "=r") 3794 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] 3795 "TARGET_64BIT" 3796 "* 3797{ 3798 int start = INTVAL (operands[3]) & 63; 3799 int size = INTVAL (operands[2]) & 63; 3800 3801 if (start + size >= 64) 3802 operands[3] = const0_rtx; 3803 else 3804 operands[3] = GEN_INT (start + size); 3805 operands[2] = GEN_INT (64 - size); 3806 return \"rldicl. %0,%1,%3,%2\"; 3807}" 3808 [(set_attr "type" "compare")]) 3809 3810(define_insn "rotlsi3" 3811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3812 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3813 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 3814 "" 3815 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") 3816 3817(define_insn "*rotlsi3_internal2" 3818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3819 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3820 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3821 (const_int 0))) 3822 (clobber (match_scratch:SI 3 "=r,r"))] 3823 "" 3824 "@ 3825 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff 3826 #" 3827 [(set_attr "type" "delayed_compare") 3828 (set_attr "length" "4,8")]) 3829 3830(define_split 3831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3832 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3833 (match_operand:SI 2 "reg_or_cint_operand" "")) 3834 (const_int 0))) 3835 (clobber (match_scratch:SI 3 ""))] 3836 "reload_completed" 3837 [(set (match_dup 3) 3838 (rotate:SI (match_dup 1) (match_dup 2))) 3839 (set (match_dup 0) 3840 (compare:CC (match_dup 3) 3841 (const_int 0)))] 3842 "") 3843 3844(define_insn "*rotlsi3_internal3" 3845 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3846 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3847 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3848 (const_int 0))) 3849 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3850 (rotate:SI (match_dup 1) (match_dup 2)))] 3851 "" 3852 "@ 3853 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff 3854 #" 3855 [(set_attr "type" "delayed_compare") 3856 (set_attr "length" "4,8")]) 3857 3858(define_split 3859 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3860 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3861 (match_operand:SI 2 "reg_or_cint_operand" "")) 3862 (const_int 0))) 3863 (set (match_operand:SI 0 "gpc_reg_operand" "") 3864 (rotate:SI (match_dup 1) (match_dup 2)))] 3865 "reload_completed" 3866 [(set (match_dup 0) 3867 (rotate:SI (match_dup 1) (match_dup 2))) 3868 (set (match_dup 3) 3869 (compare:CC (match_dup 0) 3870 (const_int 0)))] 3871 "") 3872 3873(define_insn "*rotlsi3_internal4" 3874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3875 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3876 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3877 (match_operand:SI 3 "mask_operand" "n")))] 3878 "" 3879 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") 3880 3881(define_insn "*rotlsi3_internal5" 3882 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3883 (compare:CC (and:SI 3884 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3885 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3886 (match_operand:SI 3 "mask_operand" "n,n")) 3887 (const_int 0))) 3888 (clobber (match_scratch:SI 4 "=r,r"))] 3889 "" 3890 "@ 3891 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 3892 #" 3893 [(set_attr "type" "delayed_compare") 3894 (set_attr "length" "4,8")]) 3895 3896(define_split 3897 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3898 (compare:CC (and:SI 3899 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3900 (match_operand:SI 2 "reg_or_cint_operand" "")) 3901 (match_operand:SI 3 "mask_operand" "")) 3902 (const_int 0))) 3903 (clobber (match_scratch:SI 4 ""))] 3904 "reload_completed" 3905 [(set (match_dup 4) 3906 (and:SI (rotate:SI (match_dup 1) 3907 (match_dup 2)) 3908 (match_dup 3))) 3909 (set (match_dup 0) 3910 (compare:CC (match_dup 4) 3911 (const_int 0)))] 3912 "") 3913 3914(define_insn "*rotlsi3_internal6" 3915 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3916 (compare:CC (and:SI 3917 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3918 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3919 (match_operand:SI 3 "mask_operand" "n,n")) 3920 (const_int 0))) 3921 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3922 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3923 "" 3924 "@ 3925 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 3926 #" 3927 [(set_attr "type" "delayed_compare") 3928 (set_attr "length" "4,8")]) 3929 3930(define_split 3931 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3932 (compare:CC (and:SI 3933 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3934 (match_operand:SI 2 "reg_or_cint_operand" "")) 3935 (match_operand:SI 3 "mask_operand" "")) 3936 (const_int 0))) 3937 (set (match_operand:SI 0 "gpc_reg_operand" "") 3938 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3939 "reload_completed" 3940 [(set (match_dup 0) 3941 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 3942 (set (match_dup 4) 3943 (compare:CC (match_dup 0) 3944 (const_int 0)))] 3945 "") 3946 3947(define_insn "*rotlsi3_internal7" 3948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3949 (zero_extend:SI 3950 (subreg:QI 3951 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3952 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 3953 "" 3954 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") 3955 3956(define_insn "*rotlsi3_internal8" 3957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3958 (compare:CC (zero_extend:SI 3959 (subreg:QI 3960 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3961 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3962 (const_int 0))) 3963 (clobber (match_scratch:SI 3 "=r,r"))] 3964 "" 3965 "@ 3966 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff 3967 #" 3968 [(set_attr "type" "delayed_compare") 3969 (set_attr "length" "4,8")]) 3970 3971(define_split 3972 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3973 (compare:CC (zero_extend:SI 3974 (subreg:QI 3975 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3976 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 3977 (const_int 0))) 3978 (clobber (match_scratch:SI 3 ""))] 3979 "reload_completed" 3980 [(set (match_dup 3) 3981 (zero_extend:SI (subreg:QI 3982 (rotate:SI (match_dup 1) 3983 (match_dup 2)) 0))) 3984 (set (match_dup 0) 3985 (compare:CC (match_dup 3) 3986 (const_int 0)))] 3987 "") 3988 3989(define_insn "*rotlsi3_internal9" 3990 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3991 (compare:CC (zero_extend:SI 3992 (subreg:QI 3993 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3994 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3995 (const_int 0))) 3996 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3997 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 3998 "" 3999 "@ 4000 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff 4001 #" 4002 [(set_attr "type" "delayed_compare") 4003 (set_attr "length" "4,8")]) 4004 4005(define_split 4006 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4007 (compare:CC (zero_extend:SI 4008 (subreg:QI 4009 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4010 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 4011 (const_int 0))) 4012 (set (match_operand:SI 0 "gpc_reg_operand" "") 4013 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 4014 "reload_completed" 4015 [(set (match_dup 0) 4016 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) 4017 (set (match_dup 3) 4018 (compare:CC (match_dup 0) 4019 (const_int 0)))] 4020 "") 4021 4022(define_insn "*rotlsi3_internal10" 4023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4024 (zero_extend:SI 4025 (subreg:HI 4026 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4027 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 4028 "" 4029 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") 4030 4031(define_insn "*rotlsi3_internal11" 4032 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4033 (compare:CC (zero_extend:SI 4034 (subreg:HI 4035 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4036 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 4037 (const_int 0))) 4038 (clobber (match_scratch:SI 3 "=r,r"))] 4039 "" 4040 "@ 4041 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff 4042 #" 4043 [(set_attr "type" "delayed_compare") 4044 (set_attr "length" "4,8")]) 4045 4046(define_split 4047 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4048 (compare:CC (zero_extend:SI 4049 (subreg:HI 4050 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4051 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 4052 (const_int 0))) 4053 (clobber (match_scratch:SI 3 ""))] 4054 "reload_completed" 4055 [(set (match_dup 3) 4056 (zero_extend:SI (subreg:HI 4057 (rotate:SI (match_dup 1) 4058 (match_dup 2)) 0))) 4059 (set (match_dup 0) 4060 (compare:CC (match_dup 3) 4061 (const_int 0)))] 4062 "") 4063 4064(define_insn "*rotlsi3_internal12" 4065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4066 (compare:CC (zero_extend:SI 4067 (subreg:HI 4068 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4069 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 4070 (const_int 0))) 4071 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4072 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 4073 "" 4074 "@ 4075 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff 4076 #" 4077 [(set_attr "type" "delayed_compare") 4078 (set_attr "length" "4,8")]) 4079 4080(define_split 4081 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4082 (compare:CC (zero_extend:SI 4083 (subreg:HI 4084 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4085 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 4086 (const_int 0))) 4087 (set (match_operand:SI 0 "gpc_reg_operand" "") 4088 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 4089 "reload_completed" 4090 [(set (match_dup 0) 4091 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) 4092 (set (match_dup 3) 4093 (compare:CC (match_dup 0) 4094 (const_int 0)))] 4095 "") 4096 4097;; Note that we use "sle." instead of "sl." so that we can set 4098;; SHIFT_COUNT_TRUNCATED. 4099 4100(define_expand "ashlsi3" 4101 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 4102 (use (match_operand:SI 1 "gpc_reg_operand" "")) 4103 (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 4104 "" 4105 " 4106{ 4107 if (TARGET_POWER) 4108 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); 4109 else 4110 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); 4111 DONE; 4112}") 4113 4114(define_insn "ashlsi3_power" 4115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4116 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4117 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 4118 (clobber (match_scratch:SI 3 "=q,X"))] 4119 "TARGET_POWER" 4120 "@ 4121 sle %0,%1,%2 4122 {sli|slwi} %0,%1,%h2") 4123 4124(define_insn "ashlsi3_no_power" 4125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4126 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4127 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 4128 "! TARGET_POWER" 4129 "{sl|slw}%I2 %0,%1,%h2") 4130 4131(define_insn "" 4132 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4133 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4134 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4135 (const_int 0))) 4136 (clobber (match_scratch:SI 3 "=r,r,r,r")) 4137 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4138 "TARGET_POWER" 4139 "@ 4140 sle. %3,%1,%2 4141 {sli.|slwi.} %3,%1,%h2 4142 # 4143 #" 4144 [(set_attr "type" "delayed_compare") 4145 (set_attr "length" "4,4,8,8")]) 4146 4147(define_split 4148 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4149 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4150 (match_operand:SI 2 "reg_or_cint_operand" "")) 4151 (const_int 0))) 4152 (clobber (match_scratch:SI 3 "")) 4153 (clobber (match_scratch:SI 4 ""))] 4154 "TARGET_POWER && reload_completed" 4155 [(parallel [(set (match_dup 3) 4156 (ashift:SI (match_dup 1) (match_dup 2))) 4157 (clobber (match_dup 4))]) 4158 (set (match_dup 0) 4159 (compare:CC (match_dup 3) 4160 (const_int 0)))] 4161 "") 4162 4163(define_insn "" 4164 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4165 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4166 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4167 (const_int 0))) 4168 (clobber (match_scratch:SI 3 "=r,r"))] 4169 "! TARGET_POWER && TARGET_32BIT" 4170 "@ 4171 {sl|slw}%I2. %3,%1,%h2 4172 #" 4173 [(set_attr "type" "delayed_compare") 4174 (set_attr "length" "4,8")]) 4175 4176(define_split 4177 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4178 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4179 (match_operand:SI 2 "reg_or_cint_operand" "")) 4180 (const_int 0))) 4181 (clobber (match_scratch:SI 3 ""))] 4182 "! TARGET_POWER && TARGET_32BIT && reload_completed" 4183 [(set (match_dup 3) 4184 (ashift:SI (match_dup 1) (match_dup 2))) 4185 (set (match_dup 0) 4186 (compare:CC (match_dup 3) 4187 (const_int 0)))] 4188 "") 4189 4190(define_insn "" 4191 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4192 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4193 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4194 (const_int 0))) 4195 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4196 (ashift:SI (match_dup 1) (match_dup 2))) 4197 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4198 "TARGET_POWER" 4199 "@ 4200 sle. %0,%1,%2 4201 {sli.|slwi.} %0,%1,%h2 4202 # 4203 #" 4204 [(set_attr "type" "delayed_compare") 4205 (set_attr "length" "4,4,8,8")]) 4206 4207(define_split 4208 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4209 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4210 (match_operand:SI 2 "reg_or_cint_operand" "")) 4211 (const_int 0))) 4212 (set (match_operand:SI 0 "gpc_reg_operand" "") 4213 (ashift:SI (match_dup 1) (match_dup 2))) 4214 (clobber (match_scratch:SI 4 ""))] 4215 "TARGET_POWER && reload_completed" 4216 [(parallel [(set (match_dup 0) 4217 (ashift:SI (match_dup 1) (match_dup 2))) 4218 (clobber (match_dup 4))]) 4219 (set (match_dup 3) 4220 (compare:CC (match_dup 0) 4221 (const_int 0)))] 4222 "") 4223 4224(define_insn "" 4225 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4226 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4227 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4228 (const_int 0))) 4229 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4230 (ashift:SI (match_dup 1) (match_dup 2)))] 4231 "! TARGET_POWER && TARGET_32BIT" 4232 "@ 4233 {sl|slw}%I2. %0,%1,%h2 4234 #" 4235 [(set_attr "type" "delayed_compare") 4236 (set_attr "length" "4,8")]) 4237 4238(define_split 4239 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4240 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4241 (match_operand:SI 2 "reg_or_cint_operand" "")) 4242 (const_int 0))) 4243 (set (match_operand:SI 0 "gpc_reg_operand" "") 4244 (ashift:SI (match_dup 1) (match_dup 2)))] 4245 "! TARGET_POWER && TARGET_32BIT && reload_completed" 4246 [(set (match_dup 0) 4247 (ashift:SI (match_dup 1) (match_dup 2))) 4248 (set (match_dup 3) 4249 (compare:CC (match_dup 0) 4250 (const_int 0)))] 4251 "") 4252 4253(define_insn "rlwinm" 4254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4255 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4256 (match_operand:SI 2 "const_int_operand" "i")) 4257 (match_operand:SI 3 "mask_operand" "n")))] 4258 "includes_lshift_p (operands[2], operands[3])" 4259 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") 4260 4261(define_insn "" 4262 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4263 (compare:CC 4264 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4265 (match_operand:SI 2 "const_int_operand" "i,i")) 4266 (match_operand:SI 3 "mask_operand" "n,n")) 4267 (const_int 0))) 4268 (clobber (match_scratch:SI 4 "=r,r"))] 4269 "includes_lshift_p (operands[2], operands[3])" 4270 "@ 4271 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 4272 #" 4273 [(set_attr "type" "delayed_compare") 4274 (set_attr "length" "4,8")]) 4275 4276(define_split 4277 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4278 (compare:CC 4279 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4280 (match_operand:SI 2 "const_int_operand" "")) 4281 (match_operand:SI 3 "mask_operand" "")) 4282 (const_int 0))) 4283 (clobber (match_scratch:SI 4 ""))] 4284 "includes_lshift_p (operands[2], operands[3]) && reload_completed" 4285 [(set (match_dup 4) 4286 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) 4287 (match_dup 3))) 4288 (set (match_dup 0) 4289 (compare:CC (match_dup 4) 4290 (const_int 0)))] 4291 "") 4292 4293(define_insn "" 4294 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 4295 (compare:CC 4296 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4297 (match_operand:SI 2 "const_int_operand" "i,i")) 4298 (match_operand:SI 3 "mask_operand" "n,n")) 4299 (const_int 0))) 4300 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4301 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4302 "includes_lshift_p (operands[2], operands[3])" 4303 "@ 4304 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 4305 #" 4306 [(set_attr "type" "delayed_compare") 4307 (set_attr "length" "4,8")]) 4308 4309(define_split 4310 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 4311 (compare:CC 4312 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4313 (match_operand:SI 2 "const_int_operand" "")) 4314 (match_operand:SI 3 "mask_operand" "")) 4315 (const_int 0))) 4316 (set (match_operand:SI 0 "gpc_reg_operand" "") 4317 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4318 "includes_lshift_p (operands[2], operands[3]) && reload_completed" 4319 [(set (match_dup 0) 4320 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 4321 (set (match_dup 4) 4322 (compare:CC (match_dup 0) 4323 (const_int 0)))] 4324 "") 4325 4326;; The AIX assembler mis-handles "sri x,x,0", so write that case as 4327;; "sli x,x,0". 4328(define_expand "lshrsi3" 4329 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 4330 (use (match_operand:SI 1 "gpc_reg_operand" "")) 4331 (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 4332 "" 4333 " 4334{ 4335 if (TARGET_POWER) 4336 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); 4337 else 4338 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); 4339 DONE; 4340}") 4341 4342(define_insn "lshrsi3_power" 4343 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 4344 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") 4345 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) 4346 (clobber (match_scratch:SI 3 "=q,X,X"))] 4347 "TARGET_POWER" 4348 "@ 4349 sre %0,%1,%2 4350 mr %0,%1 4351 {s%A2i|s%A2wi} %0,%1,%h2") 4352 4353(define_insn "lshrsi3_no_power" 4354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4355 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4356 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] 4357 "! TARGET_POWER" 4358 "@ 4359 mr %0,%1 4360 {sr|srw}%I2 %0,%1,%h2") 4361 4362(define_insn "" 4363 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") 4364 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") 4365 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) 4366 (const_int 0))) 4367 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) 4368 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] 4369 "TARGET_POWER" 4370 "@ 4371 sre. %3,%1,%2 4372 mr. %1,%1 4373 {s%A2i.|s%A2wi.} %3,%1,%h2 4374 # 4375 # 4376 #" 4377 [(set_attr "type" "delayed_compare") 4378 (set_attr "length" "4,4,4,8,8,8")]) 4379 4380(define_split 4381 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4382 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4383 (match_operand:SI 2 "reg_or_cint_operand" "")) 4384 (const_int 0))) 4385 (clobber (match_scratch:SI 3 "")) 4386 (clobber (match_scratch:SI 4 ""))] 4387 "TARGET_POWER && reload_completed" 4388 [(parallel [(set (match_dup 3) 4389 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4390 (clobber (match_dup 4))]) 4391 (set (match_dup 0) 4392 (compare:CC (match_dup 3) 4393 (const_int 0)))] 4394 "") 4395 4396(define_insn "" 4397 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4398 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4399 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) 4400 (const_int 0))) 4401 (clobber (match_scratch:SI 3 "=X,r,X,r"))] 4402 "! TARGET_POWER && TARGET_32BIT" 4403 "@ 4404 mr. %1,%1 4405 {sr|srw}%I2. %3,%1,%h2 4406 # 4407 #" 4408 [(set_attr "type" "delayed_compare") 4409 (set_attr "length" "4,4,8,8")]) 4410 4411(define_split 4412 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4413 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4414 (match_operand:SI 2 "reg_or_cint_operand" "")) 4415 (const_int 0))) 4416 (clobber (match_scratch:SI 3 ""))] 4417 "! TARGET_POWER && TARGET_32BIT && reload_completed" 4418 [(set (match_dup 3) 4419 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4420 (set (match_dup 0) 4421 (compare:CC (match_dup 3) 4422 (const_int 0)))] 4423 "") 4424 4425(define_insn "" 4426 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") 4427 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") 4428 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) 4429 (const_int 0))) 4430 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") 4431 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4432 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] 4433 "TARGET_POWER" 4434 "@ 4435 sre. %0,%1,%2 4436 mr. %0,%1 4437 {s%A2i.|s%A2wi.} %0,%1,%h2 4438 # 4439 # 4440 #" 4441 [(set_attr "type" "delayed_compare") 4442 (set_attr "length" "4,4,4,8,8,8")]) 4443 4444(define_split 4445 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4446 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4447 (match_operand:SI 2 "reg_or_cint_operand" "")) 4448 (const_int 0))) 4449 (set (match_operand:SI 0 "gpc_reg_operand" "") 4450 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4451 (clobber (match_scratch:SI 4 ""))] 4452 "TARGET_POWER && reload_completed" 4453 [(parallel [(set (match_dup 0) 4454 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4455 (clobber (match_dup 4))]) 4456 (set (match_dup 3) 4457 (compare:CC (match_dup 0) 4458 (const_int 0)))] 4459 "") 4460 4461(define_insn "" 4462 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4463 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4464 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) 4465 (const_int 0))) 4466 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4467 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 4468 "! TARGET_POWER && TARGET_32BIT" 4469 "@ 4470 mr. %0,%1 4471 {sr|srw}%I2. %0,%1,%h2 4472 # 4473 #" 4474 [(set_attr "type" "delayed_compare") 4475 (set_attr "length" "4,4,8,8")]) 4476 4477(define_split 4478 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4479 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4480 (match_operand:SI 2 "reg_or_cint_operand" "")) 4481 (const_int 0))) 4482 (set (match_operand:SI 0 "gpc_reg_operand" "") 4483 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 4484 "! TARGET_POWER && TARGET_32BIT && reload_completed" 4485 [(set (match_dup 0) 4486 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4487 (set (match_dup 3) 4488 (compare:CC (match_dup 0) 4489 (const_int 0)))] 4490 "") 4491 4492(define_insn "" 4493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4494 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4495 (match_operand:SI 2 "const_int_operand" "i")) 4496 (match_operand:SI 3 "mask_operand" "n")))] 4497 "includes_rshift_p (operands[2], operands[3])" 4498 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") 4499 4500(define_insn "" 4501 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4502 (compare:CC 4503 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4504 (match_operand:SI 2 "const_int_operand" "i,i")) 4505 (match_operand:SI 3 "mask_operand" "n,n")) 4506 (const_int 0))) 4507 (clobber (match_scratch:SI 4 "=r,r"))] 4508 "includes_rshift_p (operands[2], operands[3])" 4509 "@ 4510 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 4511 #" 4512 [(set_attr "type" "delayed_compare") 4513 (set_attr "length" "4,8")]) 4514 4515(define_split 4516 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4517 (compare:CC 4518 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4519 (match_operand:SI 2 "const_int_operand" "")) 4520 (match_operand:SI 3 "mask_operand" "")) 4521 (const_int 0))) 4522 (clobber (match_scratch:SI 4 ""))] 4523 "includes_rshift_p (operands[2], operands[3]) && reload_completed" 4524 [(set (match_dup 4) 4525 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) 4526 (match_dup 3))) 4527 (set (match_dup 0) 4528 (compare:CC (match_dup 4) 4529 (const_int 0)))] 4530 "") 4531 4532(define_insn "" 4533 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 4534 (compare:CC 4535 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4536 (match_operand:SI 2 "const_int_operand" "i,i")) 4537 (match_operand:SI 3 "mask_operand" "n,n")) 4538 (const_int 0))) 4539 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4540 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4541 "includes_rshift_p (operands[2], operands[3])" 4542 "@ 4543 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 4544 #" 4545 [(set_attr "type" "delayed_compare") 4546 (set_attr "length" "4,8")]) 4547 4548(define_split 4549 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 4550 (compare:CC 4551 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4552 (match_operand:SI 2 "const_int_operand" "")) 4553 (match_operand:SI 3 "mask_operand" "")) 4554 (const_int 0))) 4555 (set (match_operand:SI 0 "gpc_reg_operand" "") 4556 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4557 "includes_rshift_p (operands[2], operands[3]) && reload_completed" 4558 [(set (match_dup 0) 4559 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 4560 (set (match_dup 4) 4561 (compare:CC (match_dup 0) 4562 (const_int 0)))] 4563 "") 4564 4565(define_insn "" 4566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4567 (zero_extend:SI 4568 (subreg:QI 4569 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4570 (match_operand:SI 2 "const_int_operand" "i")) 0)))] 4571 "includes_rshift_p (operands[2], GEN_INT (255))" 4572 "{rlinm|rlwinm} %0,%1,%s2,0xff") 4573 4574(define_insn "" 4575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4576 (compare:CC 4577 (zero_extend:SI 4578 (subreg:QI 4579 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4580 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4581 (const_int 0))) 4582 (clobber (match_scratch:SI 3 "=r,r"))] 4583 "includes_rshift_p (operands[2], GEN_INT (255))" 4584 "@ 4585 {rlinm.|rlwinm.} %3,%1,%s2,0xff 4586 #" 4587 [(set_attr "type" "delayed_compare") 4588 (set_attr "length" "4,8")]) 4589 4590(define_split 4591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4592 (compare:CC 4593 (zero_extend:SI 4594 (subreg:QI 4595 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4596 (match_operand:SI 2 "const_int_operand" "")) 0)) 4597 (const_int 0))) 4598 (clobber (match_scratch:SI 3 ""))] 4599 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4600 [(set (match_dup 3) 4601 (zero_extend:SI (subreg:QI 4602 (lshiftrt:SI (match_dup 1) 4603 (match_dup 2)) 0))) 4604 (set (match_dup 0) 4605 (compare:CC (match_dup 3) 4606 (const_int 0)))] 4607 "") 4608 4609(define_insn "" 4610 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4611 (compare:CC 4612 (zero_extend:SI 4613 (subreg:QI 4614 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4615 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4616 (const_int 0))) 4617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4618 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4619 "includes_rshift_p (operands[2], GEN_INT (255))" 4620 "@ 4621 {rlinm.|rlwinm.} %0,%1,%s2,0xff 4622 #" 4623 [(set_attr "type" "delayed_compare") 4624 (set_attr "length" "4,8")]) 4625 4626(define_split 4627 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4628 (compare:CC 4629 (zero_extend:SI 4630 (subreg:QI 4631 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4632 (match_operand:SI 2 "const_int_operand" "")) 0)) 4633 (const_int 0))) 4634 (set (match_operand:SI 0 "gpc_reg_operand" "") 4635 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4636 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4637 [(set (match_dup 0) 4638 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) 4639 (set (match_dup 3) 4640 (compare:CC (match_dup 0) 4641 (const_int 0)))] 4642 "") 4643 4644(define_insn "" 4645 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4646 (zero_extend:SI 4647 (subreg:HI 4648 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4649 (match_operand:SI 2 "const_int_operand" "i")) 0)))] 4650 "includes_rshift_p (operands[2], GEN_INT (65535))" 4651 "{rlinm|rlwinm} %0,%1,%s2,0xffff") 4652 4653(define_insn "" 4654 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4655 (compare:CC 4656 (zero_extend:SI 4657 (subreg:HI 4658 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4659 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4660 (const_int 0))) 4661 (clobber (match_scratch:SI 3 "=r,r"))] 4662 "includes_rshift_p (operands[2], GEN_INT (65535))" 4663 "@ 4664 {rlinm.|rlwinm.} %3,%1,%s2,0xffff 4665 #" 4666 [(set_attr "type" "delayed_compare") 4667 (set_attr "length" "4,8")]) 4668 4669(define_split 4670 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4671 (compare:CC 4672 (zero_extend:SI 4673 (subreg:HI 4674 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4675 (match_operand:SI 2 "const_int_operand" "")) 0)) 4676 (const_int 0))) 4677 (clobber (match_scratch:SI 3 ""))] 4678 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4679 [(set (match_dup 3) 4680 (zero_extend:SI (subreg:HI 4681 (lshiftrt:SI (match_dup 1) 4682 (match_dup 2)) 0))) 4683 (set (match_dup 0) 4684 (compare:CC (match_dup 3) 4685 (const_int 0)))] 4686 "") 4687 4688(define_insn "" 4689 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4690 (compare:CC 4691 (zero_extend:SI 4692 (subreg:HI 4693 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4694 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4695 (const_int 0))) 4696 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4697 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4698 "includes_rshift_p (operands[2], GEN_INT (65535))" 4699 "@ 4700 {rlinm.|rlwinm.} %0,%1,%s2,0xffff 4701 #" 4702 [(set_attr "type" "delayed_compare") 4703 (set_attr "length" "4,8")]) 4704 4705(define_split 4706 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4707 (compare:CC 4708 (zero_extend:SI 4709 (subreg:HI 4710 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4711 (match_operand:SI 2 "const_int_operand" "")) 0)) 4712 (const_int 0))) 4713 (set (match_operand:SI 0 "gpc_reg_operand" "") 4714 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4715 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4716 [(set (match_dup 0) 4717 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) 4718 (set (match_dup 3) 4719 (compare:CC (match_dup 0) 4720 (const_int 0)))] 4721 "") 4722 4723(define_insn "" 4724 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 4725 (const_int 1) 4726 (match_operand:SI 1 "gpc_reg_operand" "r")) 4727 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 4728 (const_int 31)))] 4729 "TARGET_POWER" 4730 "rrib %0,%1,%2") 4731 4732(define_insn "" 4733 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 4734 (const_int 1) 4735 (match_operand:SI 1 "gpc_reg_operand" "r")) 4736 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 4737 (const_int 31)))] 4738 "TARGET_POWER" 4739 "rrib %0,%1,%2") 4740 4741(define_insn "" 4742 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 4743 (const_int 1) 4744 (match_operand:SI 1 "gpc_reg_operand" "r")) 4745 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 4746 (const_int 1) 4747 (const_int 0)))] 4748 "TARGET_POWER" 4749 "rrib %0,%1,%2") 4750 4751(define_expand "ashrsi3" 4752 [(set (match_operand:SI 0 "gpc_reg_operand" "") 4753 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4754 (match_operand:SI 2 "reg_or_cint_operand" "")))] 4755 "" 4756 " 4757{ 4758 if (TARGET_POWER) 4759 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); 4760 else 4761 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); 4762 DONE; 4763}") 4764 4765(define_insn "ashrsi3_power" 4766 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4767 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4768 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 4769 (clobber (match_scratch:SI 3 "=q,X"))] 4770 "TARGET_POWER" 4771 "@ 4772 srea %0,%1,%2 4773 {srai|srawi} %0,%1,%h2") 4774 4775(define_insn "ashrsi3_no_power" 4776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4777 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4778 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 4779 "! TARGET_POWER" 4780 "{sra|sraw}%I2 %0,%1,%h2") 4781 4782(define_insn "" 4783 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4784 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4785 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4786 (const_int 0))) 4787 (clobber (match_scratch:SI 3 "=r,r,r,r")) 4788 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4789 "TARGET_POWER" 4790 "@ 4791 srea. %3,%1,%2 4792 {srai.|srawi.} %3,%1,%h2 4793 # 4794 #" 4795 [(set_attr "type" "delayed_compare") 4796 (set_attr "length" "4,4,8,8")]) 4797 4798(define_split 4799 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4800 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4801 (match_operand:SI 2 "reg_or_cint_operand" "")) 4802 (const_int 0))) 4803 (clobber (match_scratch:SI 3 "")) 4804 (clobber (match_scratch:SI 4 ""))] 4805 "TARGET_POWER && reload_completed" 4806 [(parallel [(set (match_dup 3) 4807 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4808 (clobber (match_dup 4))]) 4809 (set (match_dup 0) 4810 (compare:CC (match_dup 3) 4811 (const_int 0)))] 4812 "") 4813 4814(define_insn "" 4815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4816 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4817 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4818 (const_int 0))) 4819 (clobber (match_scratch:SI 3 "=r,r"))] 4820 "! TARGET_POWER" 4821 "@ 4822 {sra|sraw}%I2. %3,%1,%h2 4823 #" 4824 [(set_attr "type" "delayed_compare") 4825 (set_attr "length" "4,8")]) 4826 4827(define_split 4828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4829 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4830 (match_operand:SI 2 "reg_or_cint_operand" "")) 4831 (const_int 0))) 4832 (clobber (match_scratch:SI 3 ""))] 4833 "! TARGET_POWER && reload_completed" 4834 [(set (match_dup 3) 4835 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4836 (set (match_dup 0) 4837 (compare:CC (match_dup 3) 4838 (const_int 0)))] 4839 "") 4840 4841(define_insn "" 4842 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4843 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4844 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4845 (const_int 0))) 4846 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4847 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4848 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4849 "TARGET_POWER" 4850 "@ 4851 srea. %0,%1,%2 4852 {srai.|srawi.} %0,%1,%h2 4853 # 4854 #" 4855 [(set_attr "type" "delayed_compare") 4856 (set_attr "length" "4,4,8,8")]) 4857 4858(define_split 4859 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4860 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4861 (match_operand:SI 2 "reg_or_cint_operand" "")) 4862 (const_int 0))) 4863 (set (match_operand:SI 0 "gpc_reg_operand" "") 4864 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4865 (clobber (match_scratch:SI 4 ""))] 4866 "TARGET_POWER && reload_completed" 4867 [(parallel [(set (match_dup 0) 4868 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4869 (clobber (match_dup 4))]) 4870 (set (match_dup 3) 4871 (compare:CC (match_dup 0) 4872 (const_int 0)))] 4873 "") 4874 4875(define_insn "" 4876 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4877 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4878 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4879 (const_int 0))) 4880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4881 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 4882 "! TARGET_POWER" 4883 "@ 4884 {sra|sraw}%I2. %0,%1,%h2 4885 #" 4886 [(set_attr "type" "delayed_compare") 4887 (set_attr "length" "4,8")]) 4888 4889(define_split 4890 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4891 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4892 (match_operand:SI 2 "reg_or_cint_operand" "")) 4893 (const_int 0))) 4894 (set (match_operand:SI 0 "gpc_reg_operand" "") 4895 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 4896 "! TARGET_POWER && reload_completed" 4897 [(set (match_dup 0) 4898 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4899 (set (match_dup 3) 4900 (compare:CC (match_dup 0) 4901 (const_int 0)))] 4902 "") 4903 4904;; Floating-point insns, excluding normal data motion. 4905;; 4906;; PowerPC has a full set of single-precision floating point instructions. 4907;; 4908;; For the POWER architecture, we pretend that we have both SFmode and 4909;; DFmode insns, while, in fact, all fp insns are actually done in double. 4910;; The only conversions we will do will be when storing to memory. In that 4911;; case, we will use the "frsp" instruction before storing. 4912;; 4913;; Note that when we store into a single-precision memory location, we need to 4914;; use the frsp insn first. If the register being stored isn't dead, we 4915;; need a scratch register for the frsp. But this is difficult when the store 4916;; is done by reload. It is not incorrect to do the frsp on the register in 4917;; this case, we just lose precision that we would have otherwise gotten but 4918;; is not guaranteed. Perhaps this should be tightened up at some point. 4919 4920(define_expand "extendsfdf2" 4921 [(set (match_operand:DF 0 "gpc_reg_operand" "") 4922 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))] 4923 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 4924 "") 4925 4926(define_insn_and_split "*extendsfdf2_fpr" 4927 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f") 4928 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))] 4929 "TARGET_HARD_FLOAT && TARGET_FPRS" 4930 "@ 4931 # 4932 fmr %0,%1 4933 lfs%U1%X1 %0,%1" 4934 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])" 4935 [(const_int 0)] 4936{ 4937 emit_note (NOTE_INSN_DELETED); 4938 DONE; 4939} 4940 [(set_attr "type" "fp,fp,fpload")]) 4941 4942(define_expand "truncdfsf2" 4943 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4944 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] 4945 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 4946 "") 4947 4948(define_insn "*truncdfsf2_fpr" 4949 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4950 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] 4951 "TARGET_HARD_FLOAT && TARGET_FPRS" 4952 "frsp %0,%1" 4953 [(set_attr "type" "fp")]) 4954 4955(define_insn "aux_truncdfsf2" 4956 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4957 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] 4958 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4959 "frsp %0,%1" 4960 [(set_attr "type" "fp")]) 4961 4962(define_expand "negsf2" 4963 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4964 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 4965 "TARGET_HARD_FLOAT" 4966 "") 4967 4968(define_insn "*negsf2" 4969 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4970 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4971 "TARGET_HARD_FLOAT && TARGET_FPRS" 4972 "fneg %0,%1" 4973 [(set_attr "type" "fp")]) 4974 4975(define_expand "abssf2" 4976 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4977 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 4978 "TARGET_HARD_FLOAT" 4979 "") 4980 4981(define_insn "*abssf2" 4982 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4983 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4984 "TARGET_HARD_FLOAT && TARGET_FPRS" 4985 "fabs %0,%1" 4986 [(set_attr "type" "fp")]) 4987 4988(define_insn "" 4989 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4990 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] 4991 "TARGET_HARD_FLOAT && TARGET_FPRS" 4992 "fnabs %0,%1" 4993 [(set_attr "type" "fp")]) 4994 4995(define_expand "addsf3" 4996 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4997 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") 4998 (match_operand:SF 2 "gpc_reg_operand" "")))] 4999 "TARGET_HARD_FLOAT" 5000 "") 5001 5002(define_insn "" 5003 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5004 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5005 (match_operand:SF 2 "gpc_reg_operand" "f")))] 5006 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 5007 "fadds %0,%1,%2" 5008 [(set_attr "type" "fp")]) 5009 5010(define_insn "" 5011 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5012 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5013 (match_operand:SF 2 "gpc_reg_operand" "f")))] 5014 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 5015 "{fa|fadd} %0,%1,%2" 5016 [(set_attr "type" "fp")]) 5017 5018(define_expand "subsf3" 5019 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5020 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") 5021 (match_operand:SF 2 "gpc_reg_operand" "")))] 5022 "TARGET_HARD_FLOAT" 5023 "") 5024 5025(define_insn "" 5026 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5027 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 5028 (match_operand:SF 2 "gpc_reg_operand" "f")))] 5029 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 5030 "fsubs %0,%1,%2" 5031 [(set_attr "type" "fp")]) 5032 5033(define_insn "" 5034 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5035 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 5036 (match_operand:SF 2 "gpc_reg_operand" "f")))] 5037 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 5038 "{fs|fsub} %0,%1,%2" 5039 [(set_attr "type" "fp")]) 5040 5041(define_expand "mulsf3" 5042 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5043 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") 5044 (match_operand:SF 2 "gpc_reg_operand" "")))] 5045 "TARGET_HARD_FLOAT" 5046 "") 5047 5048(define_insn "" 5049 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5050 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5051 (match_operand:SF 2 "gpc_reg_operand" "f")))] 5052 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 5053 "fmuls %0,%1,%2" 5054 [(set_attr "type" "fp")]) 5055 5056(define_insn "" 5057 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5058 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5059 (match_operand:SF 2 "gpc_reg_operand" "f")))] 5060 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 5061 "{fm|fmul} %0,%1,%2" 5062 [(set_attr "type" "dmul")]) 5063 5064(define_insn "fres" 5065 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5066 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] 5067 "TARGET_PPC_GFXOPT && flag_finite_math_only" 5068 "fres %0,%1" 5069 [(set_attr "type" "fp")]) 5070 5071(define_expand "divsf3" 5072 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5073 (div:SF (match_operand:SF 1 "gpc_reg_operand" "") 5074 (match_operand:SF 2 "gpc_reg_operand" "")))] 5075 "TARGET_HARD_FLOAT" 5076{ 5077 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT 5078 && flag_finite_math_only && !flag_trapping_math) 5079 { 5080 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]); 5081 DONE; 5082 } 5083}) 5084 5085(define_insn "" 5086 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5087 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 5088 (match_operand:SF 2 "gpc_reg_operand" "f")))] 5089 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 5090 "fdivs %0,%1,%2" 5091 [(set_attr "type" "sdiv")]) 5092 5093(define_insn "" 5094 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5095 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 5096 (match_operand:SF 2 "gpc_reg_operand" "f")))] 5097 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 5098 "{fd|fdiv} %0,%1,%2" 5099 [(set_attr "type" "ddiv")]) 5100 5101(define_insn "" 5102 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5103 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5104 (match_operand:SF 2 "gpc_reg_operand" "f")) 5105 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5106 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5107 "fmadds %0,%1,%2,%3" 5108 [(set_attr "type" "fp")]) 5109 5110(define_insn "" 5111 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5112 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5113 (match_operand:SF 2 "gpc_reg_operand" "f")) 5114 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5115 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5116 "{fma|fmadd} %0,%1,%2,%3" 5117 [(set_attr "type" "dmul")]) 5118 5119(define_insn "" 5120 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5121 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5122 (match_operand:SF 2 "gpc_reg_operand" "f")) 5123 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5124 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5125 "fmsubs %0,%1,%2,%3" 5126 [(set_attr "type" "fp")]) 5127 5128(define_insn "" 5129 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5130 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5131 (match_operand:SF 2 "gpc_reg_operand" "f")) 5132 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5133 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5134 "{fms|fmsub} %0,%1,%2,%3" 5135 [(set_attr "type" "dmul")]) 5136 5137(define_insn "" 5138 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5139 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5140 (match_operand:SF 2 "gpc_reg_operand" "f")) 5141 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 5142 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5143 && HONOR_SIGNED_ZEROS (SFmode)" 5144 "fnmadds %0,%1,%2,%3" 5145 [(set_attr "type" "fp")]) 5146 5147(define_insn "" 5148 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5149 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) 5150 (match_operand:SF 2 "gpc_reg_operand" "f")) 5151 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5152 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5153 && ! HONOR_SIGNED_ZEROS (SFmode)" 5154 "fnmadds %0,%1,%2,%3" 5155 [(set_attr "type" "fp")]) 5156 5157(define_insn "" 5158 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5159 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5160 (match_operand:SF 2 "gpc_reg_operand" "f")) 5161 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 5162 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5163 "{fnma|fnmadd} %0,%1,%2,%3" 5164 [(set_attr "type" "dmul")]) 5165 5166(define_insn "" 5167 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5168 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) 5169 (match_operand:SF 2 "gpc_reg_operand" "f")) 5170 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5171 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5172 && ! HONOR_SIGNED_ZEROS (SFmode)" 5173 "{fnma|fnmadd} %0,%1,%2,%3" 5174 [(set_attr "type" "dmul")]) 5175 5176(define_insn "" 5177 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5178 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5179 (match_operand:SF 2 "gpc_reg_operand" "f")) 5180 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 5181 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5182 && HONOR_SIGNED_ZEROS (SFmode)" 5183 "fnmsubs %0,%1,%2,%3" 5184 [(set_attr "type" "fp")]) 5185 5186(define_insn "" 5187 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5188 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") 5189 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5190 (match_operand:SF 2 "gpc_reg_operand" "f"))))] 5191 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5192 && ! HONOR_SIGNED_ZEROS (SFmode)" 5193 "fnmsubs %0,%1,%2,%3" 5194 [(set_attr "type" "fp")]) 5195 5196(define_insn "" 5197 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5198 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5199 (match_operand:SF 2 "gpc_reg_operand" "f")) 5200 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 5201 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5202 "{fnms|fnmsub} %0,%1,%2,%3" 5203 [(set_attr "type" "dmul")]) 5204 5205(define_insn "" 5206 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5207 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") 5208 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5209 (match_operand:SF 2 "gpc_reg_operand" "f"))))] 5210 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5211 && ! HONOR_SIGNED_ZEROS (SFmode)" 5212 "{fnms|fnmsub} %0,%1,%2,%3" 5213 [(set_attr "type" "dmul")]) 5214 5215(define_expand "sqrtsf2" 5216 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5217 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 5218 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" 5219 "") 5220 5221(define_insn "" 5222 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5223 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 5224 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 5225 "fsqrts %0,%1" 5226 [(set_attr "type" "ssqrt")]) 5227 5228(define_insn "" 5229 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5230 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 5231 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" 5232 "fsqrt %0,%1" 5233 [(set_attr "type" "dsqrt")]) 5234 5235(define_expand "copysignsf3" 5236 [(set (match_dup 3) 5237 (abs:SF (match_operand:SF 1 "gpc_reg_operand" ""))) 5238 (set (match_dup 4) 5239 (neg:SF (abs:SF (match_dup 1)))) 5240 (set (match_operand:SF 0 "gpc_reg_operand" "") 5241 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "") 5242 (match_dup 5)) 5243 (match_dup 3) 5244 (match_dup 4)))] 5245 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS 5246 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)" 5247 { 5248 operands[3] = gen_reg_rtx (SFmode); 5249 operands[4] = gen_reg_rtx (SFmode); 5250 operands[5] = CONST0_RTX (SFmode); 5251 }) 5252 5253(define_expand "copysigndf3" 5254 [(set (match_dup 3) 5255 (abs:DF (match_operand:DF 1 "gpc_reg_operand" ""))) 5256 (set (match_dup 4) 5257 (neg:DF (abs:DF (match_dup 1)))) 5258 (set (match_operand:DF 0 "gpc_reg_operand" "") 5259 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "") 5260 (match_dup 5)) 5261 (match_dup 3) 5262 (match_dup 4)))] 5263 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS 5264 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)" 5265 { 5266 operands[3] = gen_reg_rtx (DFmode); 5267 operands[4] = gen_reg_rtx (DFmode); 5268 operands[5] = CONST0_RTX (DFmode); 5269 }) 5270 5271;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a 5272;; fsel instruction and some auxiliary computations. Then we just have a 5273;; single DEFINE_INSN for fsel and the define_splits to make them if made by 5274;; combine. 5275(define_expand "smaxsf3" 5276 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5277 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") 5278 (match_operand:SF 2 "gpc_reg_operand" "")) 5279 (match_dup 1) 5280 (match_dup 2)))] 5281 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" 5282 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") 5283 5284(define_expand "sminsf3" 5285 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5286 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") 5287 (match_operand:SF 2 "gpc_reg_operand" "")) 5288 (match_dup 2) 5289 (match_dup 1)))] 5290 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" 5291 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") 5292 5293(define_split 5294 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5295 (match_operator:SF 3 "min_max_operator" 5296 [(match_operand:SF 1 "gpc_reg_operand" "") 5297 (match_operand:SF 2 "gpc_reg_operand" "")]))] 5298 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" 5299 [(const_int 0)] 5300 " 5301{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), 5302 operands[1], operands[2]); 5303 DONE; 5304}") 5305 5306(define_expand "movsicc" 5307 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5308 (if_then_else:SI (match_operand 1 "comparison_operator" "") 5309 (match_operand:SI 2 "gpc_reg_operand" "") 5310 (match_operand:SI 3 "gpc_reg_operand" "")))] 5311 "TARGET_ISEL" 5312 " 5313{ 5314 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 5315 DONE; 5316 else 5317 FAIL; 5318}") 5319 5320;; We use the BASE_REGS for the isel input operands because, if rA is 5321;; 0, the value of 0 is placed in rD upon truth. Similarly for rB 5322;; because we may switch the operands and rB may end up being rA. 5323;; 5324;; We need 2 patterns: an unsigned and a signed pattern. We could 5325;; leave out the mode in operand 4 and use one pattern, but reload can 5326;; change the mode underneath our feet and then gets confused trying 5327;; to reload the value. 5328(define_insn "isel_signed" 5329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5330 (if_then_else:SI 5331 (match_operator 1 "comparison_operator" 5332 [(match_operand:CC 4 "cc_reg_operand" "y") 5333 (const_int 0)]) 5334 (match_operand:SI 2 "gpc_reg_operand" "b") 5335 (match_operand:SI 3 "gpc_reg_operand" "b")))] 5336 "TARGET_ISEL" 5337 "* 5338{ return output_isel (operands); }" 5339 [(set_attr "length" "4")]) 5340 5341(define_insn "isel_unsigned" 5342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5343 (if_then_else:SI 5344 (match_operator 1 "comparison_operator" 5345 [(match_operand:CCUNS 4 "cc_reg_operand" "y") 5346 (const_int 0)]) 5347 (match_operand:SI 2 "gpc_reg_operand" "b") 5348 (match_operand:SI 3 "gpc_reg_operand" "b")))] 5349 "TARGET_ISEL" 5350 "* 5351{ return output_isel (operands); }" 5352 [(set_attr "length" "4")]) 5353 5354(define_expand "movsfcc" 5355 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5356 (if_then_else:SF (match_operand 1 "comparison_operator" "") 5357 (match_operand:SF 2 "gpc_reg_operand" "") 5358 (match_operand:SF 3 "gpc_reg_operand" "")))] 5359 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 5360 " 5361{ 5362 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 5363 DONE; 5364 else 5365 FAIL; 5366}") 5367 5368(define_insn "*fselsfsf4" 5369 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5370 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 5371 (match_operand:SF 4 "zero_fp_constant" "F")) 5372 (match_operand:SF 2 "gpc_reg_operand" "f") 5373 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5374 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 5375 "fsel %0,%1,%2,%3" 5376 [(set_attr "type" "fp")]) 5377 5378(define_insn "*fseldfsf4" 5379 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5380 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 5381 (match_operand:DF 4 "zero_fp_constant" "F")) 5382 (match_operand:SF 2 "gpc_reg_operand" "f") 5383 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5384 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 5385 "fsel %0,%1,%2,%3" 5386 [(set_attr "type" "fp")]) 5387 5388(define_expand "negdf2" 5389 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5390 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] 5391 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 5392 "") 5393 5394(define_insn "*negdf2_fpr" 5395 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5396 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 5397 "TARGET_HARD_FLOAT && TARGET_FPRS" 5398 "fneg %0,%1" 5399 [(set_attr "type" "fp")]) 5400 5401(define_expand "absdf2" 5402 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5403 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] 5404 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 5405 "") 5406 5407(define_insn "*absdf2_fpr" 5408 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5409 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 5410 "TARGET_HARD_FLOAT && TARGET_FPRS" 5411 "fabs %0,%1" 5412 [(set_attr "type" "fp")]) 5413 5414(define_insn "*nabsdf2_fpr" 5415 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5416 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] 5417 "TARGET_HARD_FLOAT && TARGET_FPRS" 5418 "fnabs %0,%1" 5419 [(set_attr "type" "fp")]) 5420 5421(define_expand "adddf3" 5422 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5423 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "") 5424 (match_operand:DF 2 "gpc_reg_operand" "")))] 5425 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 5426 "") 5427 5428(define_insn "*adddf3_fpr" 5429 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5430 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5431 (match_operand:DF 2 "gpc_reg_operand" "f")))] 5432 "TARGET_HARD_FLOAT && TARGET_FPRS" 5433 "{fa|fadd} %0,%1,%2" 5434 [(set_attr "type" "fp")]) 5435 5436(define_expand "subdf3" 5437 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5438 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") 5439 (match_operand:DF 2 "gpc_reg_operand" "")))] 5440 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 5441 "") 5442 5443(define_insn "*subdf3_fpr" 5444 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5445 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") 5446 (match_operand:DF 2 "gpc_reg_operand" "f")))] 5447 "TARGET_HARD_FLOAT && TARGET_FPRS" 5448 "{fs|fsub} %0,%1,%2" 5449 [(set_attr "type" "fp")]) 5450 5451(define_expand "muldf3" 5452 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5453 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "") 5454 (match_operand:DF 2 "gpc_reg_operand" "")))] 5455 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 5456 "") 5457 5458(define_insn "*muldf3_fpr" 5459 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5460 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5461 (match_operand:DF 2 "gpc_reg_operand" "f")))] 5462 "TARGET_HARD_FLOAT && TARGET_FPRS" 5463 "{fm|fmul} %0,%1,%2" 5464 [(set_attr "type" "dmul")]) 5465 5466(define_insn "fred" 5467 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5468 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] 5469 "TARGET_POPCNTB && flag_finite_math_only" 5470 "fre %0,%1" 5471 [(set_attr "type" "fp")]) 5472 5473(define_expand "divdf3" 5474 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5475 (div:DF (match_operand:DF 1 "gpc_reg_operand" "") 5476 (match_operand:DF 2 "gpc_reg_operand" "")))] 5477 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 5478{ 5479 if (swdiv && !optimize_size && TARGET_POPCNTB 5480 && flag_finite_math_only && !flag_trapping_math) 5481 { 5482 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]); 5483 DONE; 5484 } 5485}) 5486 5487(define_insn "*divdf3_fpr" 5488 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5489 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") 5490 (match_operand:DF 2 "gpc_reg_operand" "f")))] 5491 "TARGET_HARD_FLOAT && TARGET_FPRS" 5492 "{fd|fdiv} %0,%1,%2" 5493 [(set_attr "type" "ddiv")]) 5494 5495(define_insn "" 5496 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5497 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5498 (match_operand:DF 2 "gpc_reg_operand" "f")) 5499 (match_operand:DF 3 "gpc_reg_operand" "f")))] 5500 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5501 "{fma|fmadd} %0,%1,%2,%3" 5502 [(set_attr "type" "dmul")]) 5503 5504(define_insn "" 5505 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5506 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5507 (match_operand:DF 2 "gpc_reg_operand" "f")) 5508 (match_operand:DF 3 "gpc_reg_operand" "f")))] 5509 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5510 "{fms|fmsub} %0,%1,%2,%3" 5511 [(set_attr "type" "dmul")]) 5512 5513(define_insn "" 5514 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5515 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5516 (match_operand:DF 2 "gpc_reg_operand" "f")) 5517 (match_operand:DF 3 "gpc_reg_operand" "f"))))] 5518 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5519 && HONOR_SIGNED_ZEROS (DFmode)" 5520 "{fnma|fnmadd} %0,%1,%2,%3" 5521 [(set_attr "type" "dmul")]) 5522 5523(define_insn "" 5524 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5525 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) 5526 (match_operand:DF 2 "gpc_reg_operand" "f")) 5527 (match_operand:DF 3 "gpc_reg_operand" "f")))] 5528 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5529 && ! HONOR_SIGNED_ZEROS (DFmode)" 5530 "{fnma|fnmadd} %0,%1,%2,%3" 5531 [(set_attr "type" "dmul")]) 5532 5533(define_insn "" 5534 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5535 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5536 (match_operand:DF 2 "gpc_reg_operand" "f")) 5537 (match_operand:DF 3 "gpc_reg_operand" "f"))))] 5538 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5539 && HONOR_SIGNED_ZEROS (DFmode)" 5540 "{fnms|fnmsub} %0,%1,%2,%3" 5541 [(set_attr "type" "dmul")]) 5542 5543(define_insn "" 5544 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5545 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") 5546 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5547 (match_operand:DF 2 "gpc_reg_operand" "f"))))] 5548 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5549 && ! HONOR_SIGNED_ZEROS (DFmode)" 5550 "{fnms|fnmsub} %0,%1,%2,%3" 5551 [(set_attr "type" "dmul")]) 5552 5553(define_insn "sqrtdf2" 5554 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5555 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 5556 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" 5557 "fsqrt %0,%1" 5558 [(set_attr "type" "dsqrt")]) 5559 5560;; The conditional move instructions allow us to perform max and min 5561;; operations even when 5562 5563(define_expand "smaxdf3" 5564 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5565 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") 5566 (match_operand:DF 2 "gpc_reg_operand" "")) 5567 (match_dup 1) 5568 (match_dup 2)))] 5569 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" 5570 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") 5571 5572(define_expand "smindf3" 5573 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5574 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") 5575 (match_operand:DF 2 "gpc_reg_operand" "")) 5576 (match_dup 2) 5577 (match_dup 1)))] 5578 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" 5579 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") 5580 5581(define_split 5582 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5583 (match_operator:DF 3 "min_max_operator" 5584 [(match_operand:DF 1 "gpc_reg_operand" "") 5585 (match_operand:DF 2 "gpc_reg_operand" "")]))] 5586 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" 5587 [(const_int 0)] 5588 " 5589{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), 5590 operands[1], operands[2]); 5591 DONE; 5592}") 5593 5594(define_expand "movdfcc" 5595 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5596 (if_then_else:DF (match_operand 1 "comparison_operator" "") 5597 (match_operand:DF 2 "gpc_reg_operand" "") 5598 (match_operand:DF 3 "gpc_reg_operand" "")))] 5599 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 5600 " 5601{ 5602 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 5603 DONE; 5604 else 5605 FAIL; 5606}") 5607 5608(define_insn "*fseldfdf4" 5609 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5610 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 5611 (match_operand:DF 4 "zero_fp_constant" "F")) 5612 (match_operand:DF 2 "gpc_reg_operand" "f") 5613 (match_operand:DF 3 "gpc_reg_operand" "f")))] 5614 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 5615 "fsel %0,%1,%2,%3" 5616 [(set_attr "type" "fp")]) 5617 5618(define_insn "*fselsfdf4" 5619 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5620 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 5621 (match_operand:SF 4 "zero_fp_constant" "F")) 5622 (match_operand:DF 2 "gpc_reg_operand" "f") 5623 (match_operand:DF 3 "gpc_reg_operand" "f")))] 5624 "TARGET_PPC_GFXOPT" 5625 "fsel %0,%1,%2,%3" 5626 [(set_attr "type" "fp")]) 5627 5628;; Conversions to and from floating-point. 5629 5630(define_expand "fixuns_truncsfsi2" 5631 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5632 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] 5633 "TARGET_HARD_FLOAT && !TARGET_FPRS" 5634 "") 5635 5636(define_expand "fix_truncsfsi2" 5637 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5638 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] 5639 "TARGET_HARD_FLOAT && !TARGET_FPRS" 5640 "") 5641 5642; For each of these conversions, there is a define_expand, a define_insn 5643; with a '#' template, and a define_split (with C code). The idea is 5644; to allow constant folding with the template of the define_insn, 5645; then to have the insns split later (between sched1 and final). 5646 5647(define_expand "floatsidf2" 5648 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") 5649 (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5650 (use (match_dup 2)) 5651 (use (match_dup 3)) 5652 (clobber (match_dup 4)) 5653 (clobber (match_dup 5)) 5654 (clobber (match_dup 6))])] 5655 "TARGET_HARD_FLOAT && TARGET_FPRS" 5656 " 5657{ 5658 if (TARGET_E500_DOUBLE) 5659 { 5660 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1])); 5661 DONE; 5662 } 5663 if (TARGET_POWERPC64) 5664 { 5665 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 5666 rtx t1 = gen_reg_rtx (DImode); 5667 rtx t2 = gen_reg_rtx (DImode); 5668 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); 5669 DONE; 5670 } 5671 5672 operands[2] = force_reg (SImode, GEN_INT (0x43300000)); 5673 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); 5674 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); 5675 operands[5] = gen_reg_rtx (DFmode); 5676 operands[6] = gen_reg_rtx (SImode); 5677}") 5678 5679(define_insn_and_split "*floatsidf2_internal" 5680 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") 5681 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5682 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 5683 (use (match_operand:DF 3 "gpc_reg_operand" "f")) 5684 (clobber (match_operand:DF 4 "memory_operand" "=o")) 5685 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) 5686 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] 5687 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5688 "#" 5689 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))" 5690 [(pc)] 5691 " 5692{ 5693 rtx lowword, highword; 5694 gcc_assert (MEM_P (operands[4])); 5695 highword = adjust_address (operands[4], SImode, 0); 5696 lowword = adjust_address (operands[4], SImode, 4); 5697 if (! WORDS_BIG_ENDIAN) 5698 { 5699 rtx tmp; 5700 tmp = highword; highword = lowword; lowword = tmp; 5701 } 5702 5703 emit_insn (gen_xorsi3 (operands[6], operands[1], 5704 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); 5705 emit_move_insn (lowword, operands[6]); 5706 emit_move_insn (highword, operands[2]); 5707 emit_move_insn (operands[5], operands[4]); 5708 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); 5709 DONE; 5710}" 5711 [(set_attr "length" "24")]) 5712 5713(define_expand "floatunssisf2" 5714 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5715 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] 5716 "TARGET_HARD_FLOAT && !TARGET_FPRS" 5717 "") 5718 5719(define_expand "floatunssidf2" 5720 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") 5721 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5722 (use (match_dup 2)) 5723 (use (match_dup 3)) 5724 (clobber (match_dup 4)) 5725 (clobber (match_dup 5))])] 5726 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 5727 " 5728{ 5729 if (TARGET_E500_DOUBLE) 5730 { 5731 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1])); 5732 DONE; 5733 } 5734 if (TARGET_POWERPC64) 5735 { 5736 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 5737 rtx t1 = gen_reg_rtx (DImode); 5738 rtx t2 = gen_reg_rtx (DImode); 5739 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, 5740 t1, t2)); 5741 DONE; 5742 } 5743 5744 operands[2] = force_reg (SImode, GEN_INT (0x43300000)); 5745 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); 5746 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); 5747 operands[5] = gen_reg_rtx (DFmode); 5748}") 5749 5750(define_insn_and_split "*floatunssidf2_internal" 5751 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") 5752 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5753 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 5754 (use (match_operand:DF 3 "gpc_reg_operand" "f")) 5755 (clobber (match_operand:DF 4 "memory_operand" "=o")) 5756 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] 5757 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5758 "#" 5759 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))" 5760 [(pc)] 5761 " 5762{ 5763 rtx lowword, highword; 5764 gcc_assert (MEM_P (operands[4])); 5765 highword = adjust_address (operands[4], SImode, 0); 5766 lowword = adjust_address (operands[4], SImode, 4); 5767 if (! WORDS_BIG_ENDIAN) 5768 { 5769 rtx tmp; 5770 tmp = highword; highword = lowword; lowword = tmp; 5771 } 5772 5773 emit_move_insn (lowword, operands[1]); 5774 emit_move_insn (highword, operands[2]); 5775 emit_move_insn (operands[5], operands[4]); 5776 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); 5777 DONE; 5778}" 5779 [(set_attr "length" "20")]) 5780 5781(define_expand "fix_truncdfsi2" 5782 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "") 5783 (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) 5784 (clobber (match_dup 2)) 5785 (clobber (match_dup 3))])] 5786 "(TARGET_POWER2 || TARGET_POWERPC) 5787 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" 5788 " 5789{ 5790 if (TARGET_E500_DOUBLE) 5791 { 5792 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1])); 5793 DONE; 5794 } 5795 operands[2] = gen_reg_rtx (DImode); 5796 if (TARGET_PPC_GFXOPT) 5797 { 5798 rtx orig_dest = operands[0]; 5799 if (! memory_operand (orig_dest, GET_MODE (orig_dest))) 5800 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0); 5801 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1], 5802 operands[2])); 5803 if (operands[0] != orig_dest) 5804 emit_move_insn (orig_dest, operands[0]); 5805 DONE; 5806 } 5807 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 5808}") 5809 5810(define_insn_and_split "*fix_truncdfsi2_internal" 5811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5812 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) 5813 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) 5814 (clobber (match_operand:DI 3 "memory_operand" "=o"))] 5815 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" 5816 "#" 5817 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))" 5818 [(pc)] 5819 " 5820{ 5821 rtx lowword; 5822 gcc_assert (MEM_P (operands[3])); 5823 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0); 5824 5825 emit_insn (gen_fctiwz (operands[2], operands[1])); 5826 emit_move_insn (operands[3], operands[2]); 5827 emit_move_insn (operands[0], lowword); 5828 DONE; 5829}" 5830 [(set_attr "length" "16")]) 5831 5832(define_insn_and_split "fix_truncdfsi2_internal_gfxopt" 5833 [(set (match_operand:SI 0 "memory_operand" "=Z") 5834 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) 5835 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))] 5836 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS 5837 && TARGET_PPC_GFXOPT" 5838 "#" 5839 "&& 1" 5840 [(pc)] 5841 " 5842{ 5843 emit_insn (gen_fctiwz (operands[2], operands[1])); 5844 emit_insn (gen_stfiwx (operands[0], operands[2])); 5845 DONE; 5846}" 5847 [(set_attr "length" "16")]) 5848 5849; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) 5850; rather than (set (subreg:SI (reg)) (fix:SI ...)) 5851; because the first makes it clear that operand 0 is not live 5852; before the instruction. 5853(define_insn "fctiwz" 5854 [(set (match_operand:DI 0 "gpc_reg_operand" "=f") 5855 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 5856 UNSPEC_FCTIWZ))] 5857 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" 5858 "{fcirz|fctiwz} %0,%1" 5859 [(set_attr "type" "fp")]) 5860 5861(define_insn "btruncdf2" 5862 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5863 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))] 5864 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" 5865 "friz %0,%1" 5866 [(set_attr "type" "fp")]) 5867 5868(define_insn "btruncsf2" 5869 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5870 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))] 5871 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" 5872 "friz %0,%1" 5873 [(set_attr "type" "fp")]) 5874 5875(define_insn "ceildf2" 5876 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5877 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))] 5878 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" 5879 "frip %0,%1" 5880 [(set_attr "type" "fp")]) 5881 5882(define_insn "ceilsf2" 5883 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5884 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))] 5885 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" 5886 "frip %0,%1" 5887 [(set_attr "type" "fp")]) 5888 5889(define_insn "floordf2" 5890 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5891 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))] 5892 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" 5893 "frim %0,%1" 5894 [(set_attr "type" "fp")]) 5895 5896(define_insn "floorsf2" 5897 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5898 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))] 5899 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" 5900 "frim %0,%1" 5901 [(set_attr "type" "fp")]) 5902 5903(define_insn "rounddf2" 5904 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5905 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))] 5906 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" 5907 "frin %0,%1" 5908 [(set_attr "type" "fp")]) 5909 5910(define_insn "roundsf2" 5911 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5912 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))] 5913 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS" 5914 "frin %0,%1" 5915 [(set_attr "type" "fp")]) 5916 5917; An UNSPEC is used so we don't have to support SImode in FP registers. 5918(define_insn "stfiwx" 5919 [(set (match_operand:SI 0 "memory_operand" "=Z") 5920 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")] 5921 UNSPEC_STFIWX))] 5922 "TARGET_PPC_GFXOPT" 5923 "stfiwx %1,%y0" 5924 [(set_attr "type" "fpstore")]) 5925 5926(define_expand "floatsisf2" 5927 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5928 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] 5929 "TARGET_HARD_FLOAT && !TARGET_FPRS" 5930 "") 5931 5932(define_insn "floatdidf2" 5933 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5934 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] 5935 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5936 "fcfid %0,%1" 5937 [(set_attr "type" "fp")]) 5938 5939(define_insn_and_split "floatsidf_ppc64" 5940 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5941 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5942 (clobber (match_operand:DI 2 "memory_operand" "=o")) 5943 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) 5944 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] 5945 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5946 "#" 5947 "&& 1" 5948 [(set (match_dup 3) (sign_extend:DI (match_dup 1))) 5949 (set (match_dup 2) (match_dup 3)) 5950 (set (match_dup 4) (match_dup 2)) 5951 (set (match_dup 0) (float:DF (match_dup 4)))] 5952 "") 5953 5954(define_insn_and_split "floatunssidf_ppc64" 5955 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5956 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5957 (clobber (match_operand:DI 2 "memory_operand" "=o")) 5958 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) 5959 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] 5960 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5961 "#" 5962 "&& 1" 5963 [(set (match_dup 3) (zero_extend:DI (match_dup 1))) 5964 (set (match_dup 2) (match_dup 3)) 5965 (set (match_dup 4) (match_dup 2)) 5966 (set (match_dup 0) (float:DF (match_dup 4)))] 5967 "") 5968 5969(define_insn "fix_truncdfdi2" 5970 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") 5971 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] 5972 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5973 "fctidz %0,%1" 5974 [(set_attr "type" "fp")]) 5975 5976(define_expand "floatdisf2" 5977 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5978 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] 5979 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5980 " 5981{ 5982 rtx val = operands[1]; 5983 if (!flag_unsafe_math_optimizations) 5984 { 5985 rtx label = gen_label_rtx (); 5986 val = gen_reg_rtx (DImode); 5987 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label)); 5988 emit_label (label); 5989 } 5990 emit_insn (gen_floatdisf2_internal1 (operands[0], val)); 5991 DONE; 5992}") 5993 5994;; This is not IEEE compliant if rounding mode is "round to nearest". 5995;; If the DI->DF conversion is inexact, then it's possible to suffer 5996;; from double rounding. 5997(define_insn_and_split "floatdisf2_internal1" 5998 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5999 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) 6000 (clobber (match_scratch:DF 2 "=f"))] 6001 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 6002 "#" 6003 "&& reload_completed" 6004 [(set (match_dup 2) 6005 (float:DF (match_dup 1))) 6006 (set (match_dup 0) 6007 (float_truncate:SF (match_dup 2)))] 6008 "") 6009 6010;; Twiddles bits to avoid double rounding. 6011;; Bits that might be truncated when converting to DFmode are replaced 6012;; by a bit that won't be lost at that stage, but is below the SFmode 6013;; rounding position. 6014(define_expand "floatdisf2_internal2" 6015 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") 6016 (const_int 53))) 6017 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1) 6018 (const_int 2047))) 6019 (clobber (scratch:CC))]) 6020 (set (match_dup 3) (plus:DI (match_dup 3) 6021 (const_int 1))) 6022 (set (match_dup 0) (plus:DI (match_dup 0) 6023 (const_int 2047))) 6024 (set (match_dup 4) (compare:CCUNS (match_dup 3) 6025 (const_int 2))) 6026 (set (match_dup 0) (ior:DI (match_dup 0) 6027 (match_dup 1))) 6028 (parallel [(set (match_dup 0) (and:DI (match_dup 0) 6029 (const_int -2048))) 6030 (clobber (scratch:CC))]) 6031 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) 6032 (label_ref (match_operand:DI 2 "" "")) 6033 (pc))) 6034 (set (match_dup 0) (match_dup 1))] 6035 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 6036 " 6037{ 6038 operands[3] = gen_reg_rtx (DImode); 6039 operands[4] = gen_reg_rtx (CCUNSmode); 6040}") 6041 6042;; Define the DImode operations that can be done in a small number 6043;; of instructions. The & constraints are to prevent the register 6044;; allocator from allocating registers that overlap with the inputs 6045;; (for example, having an input in 7,8 and an output in 6,7). We 6046;; also allow for the output being the same as one of the inputs. 6047 6048(define_insn "*adddi3_noppc64" 6049 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") 6050 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") 6051 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] 6052 "! TARGET_POWERPC64" 6053 "* 6054{ 6055 if (WORDS_BIG_ENDIAN) 6056 return (GET_CODE (operands[2])) != CONST_INT 6057 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" 6058 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; 6059 else 6060 return (GET_CODE (operands[2])) != CONST_INT 6061 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" 6062 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; 6063}" 6064 [(set_attr "type" "two") 6065 (set_attr "length" "8")]) 6066 6067(define_insn "*subdi3_noppc64" 6068 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") 6069 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") 6070 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] 6071 "! TARGET_POWERPC64" 6072 "* 6073{ 6074 if (WORDS_BIG_ENDIAN) 6075 return (GET_CODE (operands[1]) != CONST_INT) 6076 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" 6077 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; 6078 else 6079 return (GET_CODE (operands[1]) != CONST_INT) 6080 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" 6081 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; 6082}" 6083 [(set_attr "type" "two") 6084 (set_attr "length" "8")]) 6085 6086(define_insn "*negdi2_noppc64" 6087 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 6088 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] 6089 "! TARGET_POWERPC64" 6090 "* 6091{ 6092 return (WORDS_BIG_ENDIAN) 6093 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" 6094 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; 6095}" 6096 [(set_attr "type" "two") 6097 (set_attr "length" "8")]) 6098 6099(define_expand "mulsidi3" 6100 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6101 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 6102 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 6103 "! TARGET_POWERPC64" 6104 " 6105{ 6106 if (! TARGET_POWER && ! TARGET_POWERPC) 6107 { 6108 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 6109 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 6110 emit_insn (gen_mull_call ()); 6111 if (WORDS_BIG_ENDIAN) 6112 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); 6113 else 6114 { 6115 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), 6116 gen_rtx_REG (SImode, 3)); 6117 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), 6118 gen_rtx_REG (SImode, 4)); 6119 } 6120 DONE; 6121 } 6122 else if (TARGET_POWER) 6123 { 6124 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); 6125 DONE; 6126 } 6127}") 6128 6129(define_insn "mulsidi3_mq" 6130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6131 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 6132 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 6133 (clobber (match_scratch:SI 3 "=q"))] 6134 "TARGET_POWER" 6135 "mul %0,%1,%2\;mfmq %L0" 6136 [(set_attr "type" "imul") 6137 (set_attr "length" "8")]) 6138 6139(define_insn "*mulsidi3_no_mq" 6140 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 6141 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 6142 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 6143 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" 6144 "* 6145{ 6146 return (WORDS_BIG_ENDIAN) 6147 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" 6148 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; 6149}" 6150 [(set_attr "type" "imul") 6151 (set_attr "length" "8")]) 6152 6153(define_split 6154 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6155 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 6156 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 6157 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" 6158 [(set (match_dup 3) 6159 (truncate:SI 6160 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 6161 (sign_extend:DI (match_dup 2))) 6162 (const_int 32)))) 6163 (set (match_dup 4) 6164 (mult:SI (match_dup 1) 6165 (match_dup 2)))] 6166 " 6167{ 6168 int endian = (WORDS_BIG_ENDIAN == 0); 6169 operands[3] = operand_subword (operands[0], endian, 0, DImode); 6170 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); 6171}") 6172 6173(define_expand "umulsidi3" 6174 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6175 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 6176 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 6177 "TARGET_POWERPC && ! TARGET_POWERPC64" 6178 " 6179{ 6180 if (TARGET_POWER) 6181 { 6182 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); 6183 DONE; 6184 } 6185}") 6186 6187(define_insn "umulsidi3_mq" 6188 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 6189 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 6190 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 6191 (clobber (match_scratch:SI 3 "=q"))] 6192 "TARGET_POWERPC && TARGET_POWER" 6193 "* 6194{ 6195 return (WORDS_BIG_ENDIAN) 6196 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" 6197 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; 6198}" 6199 [(set_attr "type" "imul") 6200 (set_attr "length" "8")]) 6201 6202(define_insn "*umulsidi3_no_mq" 6203 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 6204 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 6205 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 6206 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" 6207 "* 6208{ 6209 return (WORDS_BIG_ENDIAN) 6210 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" 6211 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; 6212}" 6213 [(set_attr "type" "imul") 6214 (set_attr "length" "8")]) 6215 6216(define_split 6217 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6218 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 6219 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 6220 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" 6221 [(set (match_dup 3) 6222 (truncate:SI 6223 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 6224 (zero_extend:DI (match_dup 2))) 6225 (const_int 32)))) 6226 (set (match_dup 4) 6227 (mult:SI (match_dup 1) 6228 (match_dup 2)))] 6229 " 6230{ 6231 int endian = (WORDS_BIG_ENDIAN == 0); 6232 operands[3] = operand_subword (operands[0], endian, 0, DImode); 6233 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); 6234}") 6235 6236(define_expand "smulsi3_highpart" 6237 [(set (match_operand:SI 0 "gpc_reg_operand" "") 6238 (truncate:SI 6239 (lshiftrt:DI (mult:DI (sign_extend:DI 6240 (match_operand:SI 1 "gpc_reg_operand" "%r")) 6241 (sign_extend:DI 6242 (match_operand:SI 2 "gpc_reg_operand" "r"))) 6243 (const_int 32))))] 6244 "" 6245 " 6246{ 6247 if (! TARGET_POWER && ! TARGET_POWERPC) 6248 { 6249 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 6250 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 6251 emit_insn (gen_mulh_call ()); 6252 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 6253 DONE; 6254 } 6255 else if (TARGET_POWER) 6256 { 6257 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); 6258 DONE; 6259 } 6260}") 6261 6262(define_insn "smulsi3_highpart_mq" 6263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6264 (truncate:SI 6265 (lshiftrt:DI (mult:DI (sign_extend:DI 6266 (match_operand:SI 1 "gpc_reg_operand" "%r")) 6267 (sign_extend:DI 6268 (match_operand:SI 2 "gpc_reg_operand" "r"))) 6269 (const_int 32)))) 6270 (clobber (match_scratch:SI 3 "=q"))] 6271 "TARGET_POWER" 6272 "mul %0,%1,%2" 6273 [(set_attr "type" "imul")]) 6274 6275(define_insn "*smulsi3_highpart_no_mq" 6276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6277 (truncate:SI 6278 (lshiftrt:DI (mult:DI (sign_extend:DI 6279 (match_operand:SI 1 "gpc_reg_operand" "%r")) 6280 (sign_extend:DI 6281 (match_operand:SI 2 "gpc_reg_operand" "r"))) 6282 (const_int 32))))] 6283 "TARGET_POWERPC && ! TARGET_POWER" 6284 "mulhw %0,%1,%2" 6285 [(set_attr "type" "imul")]) 6286 6287(define_expand "umulsi3_highpart" 6288 [(set (match_operand:SI 0 "gpc_reg_operand" "") 6289 (truncate:SI 6290 (lshiftrt:DI (mult:DI (zero_extend:DI 6291 (match_operand:SI 1 "gpc_reg_operand" "")) 6292 (zero_extend:DI 6293 (match_operand:SI 2 "gpc_reg_operand" ""))) 6294 (const_int 32))))] 6295 "TARGET_POWERPC" 6296 " 6297{ 6298 if (TARGET_POWER) 6299 { 6300 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); 6301 DONE; 6302 } 6303}") 6304 6305(define_insn "umulsi3_highpart_mq" 6306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6307 (truncate:SI 6308 (lshiftrt:DI (mult:DI (zero_extend:DI 6309 (match_operand:SI 1 "gpc_reg_operand" "%r")) 6310 (zero_extend:DI 6311 (match_operand:SI 2 "gpc_reg_operand" "r"))) 6312 (const_int 32)))) 6313 (clobber (match_scratch:SI 3 "=q"))] 6314 "TARGET_POWERPC && TARGET_POWER" 6315 "mulhwu %0,%1,%2" 6316 [(set_attr "type" "imul")]) 6317 6318(define_insn "*umulsi3_highpart_no_mq" 6319 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6320 (truncate:SI 6321 (lshiftrt:DI (mult:DI (zero_extend:DI 6322 (match_operand:SI 1 "gpc_reg_operand" "%r")) 6323 (zero_extend:DI 6324 (match_operand:SI 2 "gpc_reg_operand" "r"))) 6325 (const_int 32))))] 6326 "TARGET_POWERPC && ! TARGET_POWER" 6327 "mulhwu %0,%1,%2" 6328 [(set_attr "type" "imul")]) 6329 6330;; If operands 0 and 2 are in the same register, we have a problem. But 6331;; operands 0 and 1 (the usual case) can be in the same register. That's 6332;; why we have the strange constraints below. 6333(define_insn "ashldi3_power" 6334 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") 6335 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 6336 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 6337 (clobber (match_scratch:SI 3 "=X,q,q,q"))] 6338 "TARGET_POWER" 6339 "@ 6340 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} 6341 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 6342 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 6343 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" 6344 [(set_attr "length" "8")]) 6345 6346(define_insn "lshrdi3_power" 6347 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") 6348 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 6349 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 6350 (clobber (match_scratch:SI 3 "=X,q,q,q"))] 6351 "TARGET_POWER" 6352 "@ 6353 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} 6354 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 6355 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 6356 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" 6357 [(set_attr "length" "8")]) 6358 6359;; Shift by a variable amount is too complex to be worth open-coding. We 6360;; just handle shifts by constants. 6361(define_insn "ashrdi3_power" 6362 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 6363 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6364 (match_operand:SI 2 "const_int_operand" "M,i"))) 6365 (clobber (match_scratch:SI 3 "=X,q"))] 6366 "TARGET_POWER" 6367 "@ 6368 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 6369 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" 6370 [(set_attr "length" "8")]) 6371 6372(define_insn "ashrdi3_no_power" 6373 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") 6374 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6375 (match_operand:SI 2 "const_int_operand" "M,i")))] 6376 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" 6377 "@ 6378 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 6379 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" 6380 [(set_attr "type" "two,three") 6381 (set_attr "length" "8,12")]) 6382 6383(define_insn "*ashrdisi3_noppc64" 6384 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6385 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6386 (const_int 32)) 4))] 6387 "TARGET_32BIT && !TARGET_POWERPC64" 6388 "* 6389{ 6390 if (REGNO (operands[0]) == REGNO (operands[1])) 6391 return \"\"; 6392 else 6393 return \"mr %0,%1\"; 6394}" 6395 [(set_attr "length" "4")]) 6396 6397 6398;; PowerPC64 DImode operations. 6399 6400(define_insn_and_split "absdi2" 6401 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 6402 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) 6403 (clobber (match_scratch:DI 2 "=&r,&r"))] 6404 "TARGET_POWERPC64" 6405 "#" 6406 "&& reload_completed" 6407 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) 6408 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) 6409 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] 6410 "") 6411 6412(define_insn_and_split "*nabsdi2" 6413 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 6414 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) 6415 (clobber (match_scratch:DI 2 "=&r,&r"))] 6416 "TARGET_POWERPC64" 6417 "#" 6418 "&& reload_completed" 6419 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) 6420 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) 6421 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] 6422 "") 6423 6424(define_insn "muldi3" 6425 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6426 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") 6427 (match_operand:DI 2 "reg_or_short_operand" "r,I")))] 6428 "TARGET_POWERPC64" 6429 "@ 6430 mulld %0,%1,%2 6431 mulli %0,%1,%2" 6432 [(set (attr "type") 6433 (cond [(match_operand:SI 2 "s8bit_cint_operand" "") 6434 (const_string "imul3") 6435 (match_operand:SI 2 "short_cint_operand" "") 6436 (const_string "imul2")] 6437 (const_string "lmul")))]) 6438 6439(define_insn "*muldi3_internal1" 6440 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6441 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") 6442 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 6443 (const_int 0))) 6444 (clobber (match_scratch:DI 3 "=r,r"))] 6445 "TARGET_POWERPC64" 6446 "@ 6447 mulld. %3,%1,%2 6448 #" 6449 [(set_attr "type" "lmul_compare") 6450 (set_attr "length" "4,8")]) 6451 6452(define_split 6453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6454 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") 6455 (match_operand:DI 2 "gpc_reg_operand" "")) 6456 (const_int 0))) 6457 (clobber (match_scratch:DI 3 ""))] 6458 "TARGET_POWERPC64 && reload_completed" 6459 [(set (match_dup 3) 6460 (mult:DI (match_dup 1) (match_dup 2))) 6461 (set (match_dup 0) 6462 (compare:CC (match_dup 3) 6463 (const_int 0)))] 6464 "") 6465 6466(define_insn "*muldi3_internal2" 6467 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6468 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") 6469 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 6470 (const_int 0))) 6471 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6472 (mult:DI (match_dup 1) (match_dup 2)))] 6473 "TARGET_POWERPC64" 6474 "@ 6475 mulld. %0,%1,%2 6476 #" 6477 [(set_attr "type" "lmul_compare") 6478 (set_attr "length" "4,8")]) 6479 6480(define_split 6481 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6482 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") 6483 (match_operand:DI 2 "gpc_reg_operand" "")) 6484 (const_int 0))) 6485 (set (match_operand:DI 0 "gpc_reg_operand" "") 6486 (mult:DI (match_dup 1) (match_dup 2)))] 6487 "TARGET_POWERPC64 && reload_completed" 6488 [(set (match_dup 0) 6489 (mult:DI (match_dup 1) (match_dup 2))) 6490 (set (match_dup 3) 6491 (compare:CC (match_dup 0) 6492 (const_int 0)))] 6493 "") 6494 6495(define_insn "smuldi3_highpart" 6496 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6497 (truncate:DI 6498 (lshiftrt:TI (mult:TI (sign_extend:TI 6499 (match_operand:DI 1 "gpc_reg_operand" "%r")) 6500 (sign_extend:TI 6501 (match_operand:DI 2 "gpc_reg_operand" "r"))) 6502 (const_int 64))))] 6503 "TARGET_POWERPC64" 6504 "mulhd %0,%1,%2" 6505 [(set_attr "type" "lmul")]) 6506 6507(define_insn "umuldi3_highpart" 6508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6509 (truncate:DI 6510 (lshiftrt:TI (mult:TI (zero_extend:TI 6511 (match_operand:DI 1 "gpc_reg_operand" "%r")) 6512 (zero_extend:TI 6513 (match_operand:DI 2 "gpc_reg_operand" "r"))) 6514 (const_int 64))))] 6515 "TARGET_POWERPC64" 6516 "mulhdu %0,%1,%2" 6517 [(set_attr "type" "lmul")]) 6518 6519(define_insn "rotldi3" 6520 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6521 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6522 (match_operand:DI 2 "reg_or_cint_operand" "ri")))] 6523 "TARGET_POWERPC64" 6524 "rld%I2cl %0,%1,%H2,0") 6525 6526(define_insn "*rotldi3_internal2" 6527 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6528 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6529 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6530 (const_int 0))) 6531 (clobber (match_scratch:DI 3 "=r,r"))] 6532 "TARGET_64BIT" 6533 "@ 6534 rld%I2cl. %3,%1,%H2,0 6535 #" 6536 [(set_attr "type" "delayed_compare") 6537 (set_attr "length" "4,8")]) 6538 6539(define_split 6540 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6541 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6542 (match_operand:DI 2 "reg_or_cint_operand" "")) 6543 (const_int 0))) 6544 (clobber (match_scratch:DI 3 ""))] 6545 "TARGET_POWERPC64 && reload_completed" 6546 [(set (match_dup 3) 6547 (rotate:DI (match_dup 1) (match_dup 2))) 6548 (set (match_dup 0) 6549 (compare:CC (match_dup 3) 6550 (const_int 0)))] 6551 "") 6552 6553(define_insn "*rotldi3_internal3" 6554 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6555 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6556 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6557 (const_int 0))) 6558 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6559 (rotate:DI (match_dup 1) (match_dup 2)))] 6560 "TARGET_64BIT" 6561 "@ 6562 rld%I2cl. %0,%1,%H2,0 6563 #" 6564 [(set_attr "type" "delayed_compare") 6565 (set_attr "length" "4,8")]) 6566 6567(define_split 6568 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6569 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6570 (match_operand:DI 2 "reg_or_cint_operand" "")) 6571 (const_int 0))) 6572 (set (match_operand:DI 0 "gpc_reg_operand" "") 6573 (rotate:DI (match_dup 1) (match_dup 2)))] 6574 "TARGET_POWERPC64 && reload_completed" 6575 [(set (match_dup 0) 6576 (rotate:DI (match_dup 1) (match_dup 2))) 6577 (set (match_dup 3) 6578 (compare:CC (match_dup 0) 6579 (const_int 0)))] 6580 "") 6581 6582(define_insn "*rotldi3_internal4" 6583 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6584 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6585 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 6586 (match_operand:DI 3 "mask64_operand" "n")))] 6587 "TARGET_POWERPC64" 6588 "rld%I2c%B3 %0,%1,%H2,%S3") 6589 6590(define_insn "*rotldi3_internal5" 6591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6592 (compare:CC (and:DI 6593 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6594 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6595 (match_operand:DI 3 "mask64_operand" "n,n")) 6596 (const_int 0))) 6597 (clobber (match_scratch:DI 4 "=r,r"))] 6598 "TARGET_64BIT" 6599 "@ 6600 rld%I2c%B3. %4,%1,%H2,%S3 6601 #" 6602 [(set_attr "type" "delayed_compare") 6603 (set_attr "length" "4,8")]) 6604 6605(define_split 6606 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6607 (compare:CC (and:DI 6608 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6609 (match_operand:DI 2 "reg_or_cint_operand" "")) 6610 (match_operand:DI 3 "mask64_operand" "")) 6611 (const_int 0))) 6612 (clobber (match_scratch:DI 4 ""))] 6613 "TARGET_POWERPC64 && reload_completed" 6614 [(set (match_dup 4) 6615 (and:DI (rotate:DI (match_dup 1) 6616 (match_dup 2)) 6617 (match_dup 3))) 6618 (set (match_dup 0) 6619 (compare:CC (match_dup 4) 6620 (const_int 0)))] 6621 "") 6622 6623(define_insn "*rotldi3_internal6" 6624 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 6625 (compare:CC (and:DI 6626 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6627 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6628 (match_operand:DI 3 "mask64_operand" "n,n")) 6629 (const_int 0))) 6630 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6631 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6632 "TARGET_64BIT" 6633 "@ 6634 rld%I2c%B3. %0,%1,%H2,%S3 6635 #" 6636 [(set_attr "type" "delayed_compare") 6637 (set_attr "length" "4,8")]) 6638 6639(define_split 6640 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 6641 (compare:CC (and:DI 6642 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6643 (match_operand:DI 2 "reg_or_cint_operand" "")) 6644 (match_operand:DI 3 "mask64_operand" "")) 6645 (const_int 0))) 6646 (set (match_operand:DI 0 "gpc_reg_operand" "") 6647 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6648 "TARGET_POWERPC64 && reload_completed" 6649 [(set (match_dup 0) 6650 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) 6651 (set (match_dup 4) 6652 (compare:CC (match_dup 0) 6653 (const_int 0)))] 6654 "") 6655 6656(define_insn "*rotldi3_internal7" 6657 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6658 (zero_extend:DI 6659 (subreg:QI 6660 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6661 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] 6662 "TARGET_POWERPC64" 6663 "rld%I2cl %0,%1,%H2,56") 6664 6665(define_insn "*rotldi3_internal8" 6666 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6667 (compare:CC (zero_extend:DI 6668 (subreg:QI 6669 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6670 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6671 (const_int 0))) 6672 (clobber (match_scratch:DI 3 "=r,r"))] 6673 "TARGET_64BIT" 6674 "@ 6675 rld%I2cl. %3,%1,%H2,56 6676 #" 6677 [(set_attr "type" "delayed_compare") 6678 (set_attr "length" "4,8")]) 6679 6680(define_split 6681 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6682 (compare:CC (zero_extend:DI 6683 (subreg:QI 6684 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6685 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6686 (const_int 0))) 6687 (clobber (match_scratch:DI 3 ""))] 6688 "TARGET_POWERPC64 && reload_completed" 6689 [(set (match_dup 3) 6690 (zero_extend:DI (subreg:QI 6691 (rotate:DI (match_dup 1) 6692 (match_dup 2)) 0))) 6693 (set (match_dup 0) 6694 (compare:CC (match_dup 3) 6695 (const_int 0)))] 6696 "") 6697 6698(define_insn "*rotldi3_internal9" 6699 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6700 (compare:CC (zero_extend:DI 6701 (subreg:QI 6702 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6703 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6704 (const_int 0))) 6705 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6706 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6707 "TARGET_64BIT" 6708 "@ 6709 rld%I2cl. %0,%1,%H2,56 6710 #" 6711 [(set_attr "type" "delayed_compare") 6712 (set_attr "length" "4,8")]) 6713 6714(define_split 6715 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6716 (compare:CC (zero_extend:DI 6717 (subreg:QI 6718 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6719 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6720 (const_int 0))) 6721 (set (match_operand:DI 0 "gpc_reg_operand" "") 6722 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6723 "TARGET_POWERPC64 && reload_completed" 6724 [(set (match_dup 0) 6725 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 6726 (set (match_dup 3) 6727 (compare:CC (match_dup 0) 6728 (const_int 0)))] 6729 "") 6730 6731(define_insn "*rotldi3_internal10" 6732 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6733 (zero_extend:DI 6734 (subreg:HI 6735 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6736 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] 6737 "TARGET_POWERPC64" 6738 "rld%I2cl %0,%1,%H2,48") 6739 6740(define_insn "*rotldi3_internal11" 6741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6742 (compare:CC (zero_extend:DI 6743 (subreg:HI 6744 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6745 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6746 (const_int 0))) 6747 (clobber (match_scratch:DI 3 "=r,r"))] 6748 "TARGET_64BIT" 6749 "@ 6750 rld%I2cl. %3,%1,%H2,48 6751 #" 6752 [(set_attr "type" "delayed_compare") 6753 (set_attr "length" "4,8")]) 6754 6755(define_split 6756 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6757 (compare:CC (zero_extend:DI 6758 (subreg:HI 6759 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6760 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6761 (const_int 0))) 6762 (clobber (match_scratch:DI 3 ""))] 6763 "TARGET_POWERPC64 && reload_completed" 6764 [(set (match_dup 3) 6765 (zero_extend:DI (subreg:HI 6766 (rotate:DI (match_dup 1) 6767 (match_dup 2)) 0))) 6768 (set (match_dup 0) 6769 (compare:CC (match_dup 3) 6770 (const_int 0)))] 6771 "") 6772 6773(define_insn "*rotldi3_internal12" 6774 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6775 (compare:CC (zero_extend:DI 6776 (subreg:HI 6777 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6778 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6779 (const_int 0))) 6780 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6781 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6782 "TARGET_64BIT" 6783 "@ 6784 rld%I2cl. %0,%1,%H2,48 6785 #" 6786 [(set_attr "type" "delayed_compare") 6787 (set_attr "length" "4,8")]) 6788 6789(define_split 6790 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6791 (compare:CC (zero_extend:DI 6792 (subreg:HI 6793 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6794 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6795 (const_int 0))) 6796 (set (match_operand:DI 0 "gpc_reg_operand" "") 6797 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6798 "TARGET_POWERPC64 && reload_completed" 6799 [(set (match_dup 0) 6800 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 6801 (set (match_dup 3) 6802 (compare:CC (match_dup 0) 6803 (const_int 0)))] 6804 "") 6805 6806(define_insn "*rotldi3_internal13" 6807 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6808 (zero_extend:DI 6809 (subreg:SI 6810 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6811 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] 6812 "TARGET_POWERPC64" 6813 "rld%I2cl %0,%1,%H2,32") 6814 6815(define_insn "*rotldi3_internal14" 6816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6817 (compare:CC (zero_extend:DI 6818 (subreg:SI 6819 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6820 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6821 (const_int 0))) 6822 (clobber (match_scratch:DI 3 "=r,r"))] 6823 "TARGET_64BIT" 6824 "@ 6825 rld%I2cl. %3,%1,%H2,32 6826 #" 6827 [(set_attr "type" "delayed_compare") 6828 (set_attr "length" "4,8")]) 6829 6830(define_split 6831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6832 (compare:CC (zero_extend:DI 6833 (subreg:SI 6834 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6835 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6836 (const_int 0))) 6837 (clobber (match_scratch:DI 3 ""))] 6838 "TARGET_POWERPC64 && reload_completed" 6839 [(set (match_dup 3) 6840 (zero_extend:DI (subreg:SI 6841 (rotate:DI (match_dup 1) 6842 (match_dup 2)) 0))) 6843 (set (match_dup 0) 6844 (compare:CC (match_dup 3) 6845 (const_int 0)))] 6846 "") 6847 6848(define_insn "*rotldi3_internal15" 6849 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6850 (compare:CC (zero_extend:DI 6851 (subreg:SI 6852 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6853 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6854 (const_int 0))) 6855 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6856 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6857 "TARGET_64BIT" 6858 "@ 6859 rld%I2cl. %0,%1,%H2,32 6860 #" 6861 [(set_attr "type" "delayed_compare") 6862 (set_attr "length" "4,8")]) 6863 6864(define_split 6865 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6866 (compare:CC (zero_extend:DI 6867 (subreg:SI 6868 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6869 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6870 (const_int 0))) 6871 (set (match_operand:DI 0 "gpc_reg_operand" "") 6872 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6873 "TARGET_POWERPC64 && reload_completed" 6874 [(set (match_dup 0) 6875 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 6876 (set (match_dup 3) 6877 (compare:CC (match_dup 0) 6878 (const_int 0)))] 6879 "") 6880 6881(define_expand "ashldi3" 6882 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6883 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6884 (match_operand:SI 2 "reg_or_cint_operand" "")))] 6885 "TARGET_POWERPC64 || TARGET_POWER" 6886 " 6887{ 6888 if (TARGET_POWERPC64) 6889 ; 6890 else if (TARGET_POWER) 6891 { 6892 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); 6893 DONE; 6894 } 6895 else 6896 FAIL; 6897}") 6898 6899(define_insn "*ashldi3_internal1" 6900 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6901 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6902 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 6903 "TARGET_POWERPC64" 6904 "sld%I2 %0,%1,%H2") 6905 6906(define_insn "*ashldi3_internal2" 6907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6908 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6909 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6910 (const_int 0))) 6911 (clobber (match_scratch:DI 3 "=r,r"))] 6912 "TARGET_64BIT" 6913 "@ 6914 sld%I2. %3,%1,%H2 6915 #" 6916 [(set_attr "type" "delayed_compare") 6917 (set_attr "length" "4,8")]) 6918 6919(define_split 6920 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6921 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6922 (match_operand:SI 2 "reg_or_cint_operand" "")) 6923 (const_int 0))) 6924 (clobber (match_scratch:DI 3 ""))] 6925 "TARGET_POWERPC64 && reload_completed" 6926 [(set (match_dup 3) 6927 (ashift:DI (match_dup 1) (match_dup 2))) 6928 (set (match_dup 0) 6929 (compare:CC (match_dup 3) 6930 (const_int 0)))] 6931 "") 6932 6933(define_insn "*ashldi3_internal3" 6934 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6935 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6936 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6937 (const_int 0))) 6938 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6939 (ashift:DI (match_dup 1) (match_dup 2)))] 6940 "TARGET_64BIT" 6941 "@ 6942 sld%I2. %0,%1,%H2 6943 #" 6944 [(set_attr "type" "delayed_compare") 6945 (set_attr "length" "4,8")]) 6946 6947(define_split 6948 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6949 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6950 (match_operand:SI 2 "reg_or_cint_operand" "")) 6951 (const_int 0))) 6952 (set (match_operand:DI 0 "gpc_reg_operand" "") 6953 (ashift:DI (match_dup 1) (match_dup 2)))] 6954 "TARGET_POWERPC64 && reload_completed" 6955 [(set (match_dup 0) 6956 (ashift:DI (match_dup 1) (match_dup 2))) 6957 (set (match_dup 3) 6958 (compare:CC (match_dup 0) 6959 (const_int 0)))] 6960 "") 6961 6962(define_insn "*ashldi3_internal4" 6963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6964 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6965 (match_operand:SI 2 "const_int_operand" "i")) 6966 (match_operand:DI 3 "const_int_operand" "n")))] 6967 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" 6968 "rldic %0,%1,%H2,%W3") 6969 6970(define_insn "ashldi3_internal5" 6971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6972 (compare:CC 6973 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6974 (match_operand:SI 2 "const_int_operand" "i,i")) 6975 (match_operand:DI 3 "const_int_operand" "n,n")) 6976 (const_int 0))) 6977 (clobber (match_scratch:DI 4 "=r,r"))] 6978 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" 6979 "@ 6980 rldic. %4,%1,%H2,%W3 6981 #" 6982 [(set_attr "type" "compare") 6983 (set_attr "length" "4,8")]) 6984 6985(define_split 6986 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6987 (compare:CC 6988 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6989 (match_operand:SI 2 "const_int_operand" "")) 6990 (match_operand:DI 3 "const_int_operand" "")) 6991 (const_int 0))) 6992 (clobber (match_scratch:DI 4 ""))] 6993 "TARGET_POWERPC64 && reload_completed 6994 && includes_rldic_lshift_p (operands[2], operands[3])" 6995 [(set (match_dup 4) 6996 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 6997 (match_dup 3))) 6998 (set (match_dup 0) 6999 (compare:CC (match_dup 4) 7000 (const_int 0)))] 7001 "") 7002 7003(define_insn "*ashldi3_internal6" 7004 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 7005 (compare:CC 7006 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7007 (match_operand:SI 2 "const_int_operand" "i,i")) 7008 (match_operand:DI 3 "const_int_operand" "n,n")) 7009 (const_int 0))) 7010 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7011 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7012 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" 7013 "@ 7014 rldic. %0,%1,%H2,%W3 7015 #" 7016 [(set_attr "type" "compare") 7017 (set_attr "length" "4,8")]) 7018 7019(define_split 7020 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 7021 (compare:CC 7022 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7023 (match_operand:SI 2 "const_int_operand" "")) 7024 (match_operand:DI 3 "const_int_operand" "")) 7025 (const_int 0))) 7026 (set (match_operand:DI 0 "gpc_reg_operand" "") 7027 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7028 "TARGET_POWERPC64 && reload_completed 7029 && includes_rldic_lshift_p (operands[2], operands[3])" 7030 [(set (match_dup 0) 7031 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 7032 (match_dup 3))) 7033 (set (match_dup 4) 7034 (compare:CC (match_dup 0) 7035 (const_int 0)))] 7036 "") 7037 7038(define_insn "*ashldi3_internal7" 7039 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7040 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 7041 (match_operand:SI 2 "const_int_operand" "i")) 7042 (match_operand:DI 3 "mask64_operand" "n")))] 7043 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" 7044 "rldicr %0,%1,%H2,%S3") 7045 7046(define_insn "ashldi3_internal8" 7047 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7048 (compare:CC 7049 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7050 (match_operand:SI 2 "const_int_operand" "i,i")) 7051 (match_operand:DI 3 "mask64_operand" "n,n")) 7052 (const_int 0))) 7053 (clobber (match_scratch:DI 4 "=r,r"))] 7054 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" 7055 "@ 7056 rldicr. %4,%1,%H2,%S3 7057 #" 7058 [(set_attr "type" "compare") 7059 (set_attr "length" "4,8")]) 7060 7061(define_split 7062 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7063 (compare:CC 7064 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7065 (match_operand:SI 2 "const_int_operand" "")) 7066 (match_operand:DI 3 "mask64_operand" "")) 7067 (const_int 0))) 7068 (clobber (match_scratch:DI 4 ""))] 7069 "TARGET_POWERPC64 && reload_completed 7070 && includes_rldicr_lshift_p (operands[2], operands[3])" 7071 [(set (match_dup 4) 7072 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 7073 (match_dup 3))) 7074 (set (match_dup 0) 7075 (compare:CC (match_dup 4) 7076 (const_int 0)))] 7077 "") 7078 7079(define_insn "*ashldi3_internal9" 7080 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 7081 (compare:CC 7082 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7083 (match_operand:SI 2 "const_int_operand" "i,i")) 7084 (match_operand:DI 3 "mask64_operand" "n,n")) 7085 (const_int 0))) 7086 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7087 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7088 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" 7089 "@ 7090 rldicr. %0,%1,%H2,%S3 7091 #" 7092 [(set_attr "type" "compare") 7093 (set_attr "length" "4,8")]) 7094 7095(define_split 7096 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 7097 (compare:CC 7098 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7099 (match_operand:SI 2 "const_int_operand" "")) 7100 (match_operand:DI 3 "mask64_operand" "")) 7101 (const_int 0))) 7102 (set (match_operand:DI 0 "gpc_reg_operand" "") 7103 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7104 "TARGET_POWERPC64 && reload_completed 7105 && includes_rldicr_lshift_p (operands[2], operands[3])" 7106 [(set (match_dup 0) 7107 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 7108 (match_dup 3))) 7109 (set (match_dup 4) 7110 (compare:CC (match_dup 0) 7111 (const_int 0)))] 7112 "") 7113 7114(define_expand "lshrdi3" 7115 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7116 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7117 (match_operand:SI 2 "reg_or_cint_operand" "")))] 7118 "TARGET_POWERPC64 || TARGET_POWER" 7119 " 7120{ 7121 if (TARGET_POWERPC64) 7122 ; 7123 else if (TARGET_POWER) 7124 { 7125 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); 7126 DONE; 7127 } 7128 else 7129 FAIL; 7130}") 7131 7132(define_insn "*lshrdi3_internal1" 7133 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7134 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 7135 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 7136 "TARGET_POWERPC64" 7137 "srd%I2 %0,%1,%H2") 7138 7139(define_insn "*lshrdi3_internal2" 7140 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7141 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7142 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 7143 (const_int 0))) 7144 (clobber (match_scratch:DI 3 "=r,r"))] 7145 "TARGET_64BIT " 7146 "@ 7147 srd%I2. %3,%1,%H2 7148 #" 7149 [(set_attr "type" "delayed_compare") 7150 (set_attr "length" "4,8")]) 7151 7152(define_split 7153 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7154 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7155 (match_operand:SI 2 "reg_or_cint_operand" "")) 7156 (const_int 0))) 7157 (clobber (match_scratch:DI 3 ""))] 7158 "TARGET_POWERPC64 && reload_completed" 7159 [(set (match_dup 3) 7160 (lshiftrt:DI (match_dup 1) (match_dup 2))) 7161 (set (match_dup 0) 7162 (compare:CC (match_dup 3) 7163 (const_int 0)))] 7164 "") 7165 7166(define_insn "*lshrdi3_internal3" 7167 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7168 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7169 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 7170 (const_int 0))) 7171 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7172 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 7173 "TARGET_64BIT" 7174 "@ 7175 srd%I2. %0,%1,%H2 7176 #" 7177 [(set_attr "type" "delayed_compare") 7178 (set_attr "length" "4,8")]) 7179 7180(define_split 7181 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7182 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7183 (match_operand:SI 2 "reg_or_cint_operand" "")) 7184 (const_int 0))) 7185 (set (match_operand:DI 0 "gpc_reg_operand" "") 7186 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 7187 "TARGET_POWERPC64 && reload_completed" 7188 [(set (match_dup 0) 7189 (lshiftrt:DI (match_dup 1) (match_dup 2))) 7190 (set (match_dup 3) 7191 (compare:CC (match_dup 0) 7192 (const_int 0)))] 7193 "") 7194 7195(define_expand "ashrdi3" 7196 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7197 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7198 (match_operand:SI 2 "reg_or_cint_operand" "")))] 7199 "WORDS_BIG_ENDIAN" 7200 " 7201{ 7202 if (TARGET_POWERPC64) 7203 ; 7204 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) 7205 { 7206 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); 7207 DONE; 7208 } 7209 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT 7210 && WORDS_BIG_ENDIAN) 7211 { 7212 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); 7213 DONE; 7214 } 7215 else 7216 FAIL; 7217}") 7218 7219(define_insn "*ashrdi3_internal1" 7220 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7221 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 7222 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 7223 "TARGET_POWERPC64" 7224 "srad%I2 %0,%1,%H2") 7225 7226(define_insn "*ashrdi3_internal2" 7227 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7228 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7229 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 7230 (const_int 0))) 7231 (clobber (match_scratch:DI 3 "=r,r"))] 7232 "TARGET_64BIT" 7233 "@ 7234 srad%I2. %3,%1,%H2 7235 #" 7236 [(set_attr "type" "delayed_compare") 7237 (set_attr "length" "4,8")]) 7238 7239(define_split 7240 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7241 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7242 (match_operand:SI 2 "reg_or_cint_operand" "")) 7243 (const_int 0))) 7244 (clobber (match_scratch:DI 3 ""))] 7245 "TARGET_POWERPC64 && reload_completed" 7246 [(set (match_dup 3) 7247 (ashiftrt:DI (match_dup 1) (match_dup 2))) 7248 (set (match_dup 0) 7249 (compare:CC (match_dup 3) 7250 (const_int 0)))] 7251 "") 7252 7253(define_insn "*ashrdi3_internal3" 7254 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7255 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7256 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 7257 (const_int 0))) 7258 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7259 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 7260 "TARGET_64BIT" 7261 "@ 7262 srad%I2. %0,%1,%H2 7263 #" 7264 [(set_attr "type" "delayed_compare") 7265 (set_attr "length" "4,8")]) 7266 7267(define_split 7268 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7269 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7270 (match_operand:SI 2 "reg_or_cint_operand" "")) 7271 (const_int 0))) 7272 (set (match_operand:DI 0 "gpc_reg_operand" "") 7273 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 7274 "TARGET_POWERPC64 && reload_completed" 7275 [(set (match_dup 0) 7276 (ashiftrt:DI (match_dup 1) (match_dup 2))) 7277 (set (match_dup 3) 7278 (compare:CC (match_dup 0) 7279 (const_int 0)))] 7280 "") 7281 7282(define_insn "anddi3" 7283 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") 7284 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") 7285 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) 7286 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] 7287 "TARGET_POWERPC64" 7288 "@ 7289 and %0,%1,%2 7290 rldic%B2 %0,%1,0,%S2 7291 rlwinm %0,%1,0,%m2,%M2 7292 andi. %0,%1,%b2 7293 andis. %0,%1,%u2 7294 #" 7295 [(set_attr "type" "*,*,*,compare,compare,*") 7296 (set_attr "length" "4,4,4,4,4,8")]) 7297 7298(define_split 7299 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7300 (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7301 (match_operand:DI 2 "mask64_2_operand" ""))) 7302 (clobber (match_scratch:CC 3 ""))] 7303 "TARGET_POWERPC64 7304 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) 7305 && !mask_operand (operands[2], DImode) 7306 && !mask64_operand (operands[2], DImode)" 7307 [(set (match_dup 0) 7308 (and:DI (rotate:DI (match_dup 1) 7309 (match_dup 4)) 7310 (match_dup 5))) 7311 (set (match_dup 0) 7312 (and:DI (rotate:DI (match_dup 0) 7313 (match_dup 6)) 7314 (match_dup 7)))] 7315{ 7316 build_mask64_2_operands (operands[2], &operands[4]); 7317}) 7318 7319(define_insn "*anddi3_internal2" 7320 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") 7321 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") 7322 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) 7323 (const_int 0))) 7324 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r")) 7325 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] 7326 "TARGET_64BIT" 7327 "@ 7328 and. %3,%1,%2 7329 rldic%B2. %3,%1,0,%S2 7330 rlwinm. %3,%1,0,%m2,%M2 7331 andi. %3,%1,%b2 7332 andis. %3,%1,%u2 7333 # 7334 # 7335 # 7336 # 7337 # 7338 # 7339 #" 7340 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare") 7341 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) 7342 7343(define_split 7344 [(set (match_operand:CC 0 "cc_reg_operand" "") 7345 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7346 (match_operand:DI 2 "mask64_2_operand" "")) 7347 (const_int 0))) 7348 (clobber (match_scratch:DI 3 "")) 7349 (clobber (match_scratch:CC 4 ""))] 7350 "TARGET_64BIT && reload_completed 7351 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) 7352 && !mask_operand (operands[2], DImode) 7353 && !mask64_operand (operands[2], DImode)" 7354 [(set (match_dup 3) 7355 (and:DI (rotate:DI (match_dup 1) 7356 (match_dup 5)) 7357 (match_dup 6))) 7358 (parallel [(set (match_dup 0) 7359 (compare:CC (and:DI (rotate:DI (match_dup 3) 7360 (match_dup 7)) 7361 (match_dup 8)) 7362 (const_int 0))) 7363 (clobber (match_dup 3))])] 7364 " 7365{ 7366 build_mask64_2_operands (operands[2], &operands[5]); 7367}") 7368 7369(define_insn "*anddi3_internal3" 7370 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") 7371 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") 7372 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) 7373 (const_int 0))) 7374 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r") 7375 (and:DI (match_dup 1) (match_dup 2))) 7376 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] 7377 "TARGET_64BIT" 7378 "@ 7379 and. %0,%1,%2 7380 rldic%B2. %0,%1,0,%S2 7381 rlwinm. %0,%1,0,%m2,%M2 7382 andi. %0,%1,%b2 7383 andis. %0,%1,%u2 7384 # 7385 # 7386 # 7387 # 7388 # 7389 # 7390 #" 7391 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare") 7392 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) 7393 7394(define_split 7395 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7396 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7397 (match_operand:DI 2 "and64_2_operand" "")) 7398 (const_int 0))) 7399 (set (match_operand:DI 0 "gpc_reg_operand" "") 7400 (and:DI (match_dup 1) (match_dup 2))) 7401 (clobber (match_scratch:CC 4 ""))] 7402 "TARGET_64BIT && reload_completed" 7403 [(parallel [(set (match_dup 0) 7404 (and:DI (match_dup 1) (match_dup 2))) 7405 (clobber (match_dup 4))]) 7406 (set (match_dup 3) 7407 (compare:CC (match_dup 0) 7408 (const_int 0)))] 7409 "") 7410 7411(define_split 7412 [(set (match_operand:CC 3 "cc_reg_operand" "") 7413 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7414 (match_operand:DI 2 "mask64_2_operand" "")) 7415 (const_int 0))) 7416 (set (match_operand:DI 0 "gpc_reg_operand" "") 7417 (and:DI (match_dup 1) (match_dup 2))) 7418 (clobber (match_scratch:CC 4 ""))] 7419 "TARGET_64BIT && reload_completed 7420 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) 7421 && !mask_operand (operands[2], DImode) 7422 && !mask64_operand (operands[2], DImode)" 7423 [(set (match_dup 0) 7424 (and:DI (rotate:DI (match_dup 1) 7425 (match_dup 5)) 7426 (match_dup 6))) 7427 (parallel [(set (match_dup 3) 7428 (compare:CC (and:DI (rotate:DI (match_dup 0) 7429 (match_dup 7)) 7430 (match_dup 8)) 7431 (const_int 0))) 7432 (set (match_dup 0) 7433 (and:DI (rotate:DI (match_dup 0) 7434 (match_dup 7)) 7435 (match_dup 8)))])] 7436 " 7437{ 7438 build_mask64_2_operands (operands[2], &operands[5]); 7439}") 7440 7441(define_expand "iordi3" 7442 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7443 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") 7444 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] 7445 "TARGET_POWERPC64" 7446 " 7447{ 7448 if (non_logical_cint_operand (operands[2], DImode)) 7449 { 7450 HOST_WIDE_INT value; 7451 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 7452 ? operands[0] : gen_reg_rtx (DImode)); 7453 7454 if (GET_CODE (operands[2]) == CONST_INT) 7455 { 7456 value = INTVAL (operands[2]); 7457 emit_insn (gen_iordi3 (tmp, operands[1], 7458 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 7459 } 7460 else 7461 { 7462 value = CONST_DOUBLE_LOW (operands[2]); 7463 emit_insn (gen_iordi3 (tmp, operands[1], 7464 immed_double_const (value 7465 & (~ (HOST_WIDE_INT) 0xffff), 7466 0, DImode))); 7467 } 7468 7469 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 7470 DONE; 7471 } 7472}") 7473 7474(define_expand "xordi3" 7475 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7476 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") 7477 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] 7478 "TARGET_POWERPC64" 7479 " 7480{ 7481 if (non_logical_cint_operand (operands[2], DImode)) 7482 { 7483 HOST_WIDE_INT value; 7484 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 7485 ? operands[0] : gen_reg_rtx (DImode)); 7486 7487 if (GET_CODE (operands[2]) == CONST_INT) 7488 { 7489 value = INTVAL (operands[2]); 7490 emit_insn (gen_xordi3 (tmp, operands[1], 7491 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 7492 } 7493 else 7494 { 7495 value = CONST_DOUBLE_LOW (operands[2]); 7496 emit_insn (gen_xordi3 (tmp, operands[1], 7497 immed_double_const (value 7498 & (~ (HOST_WIDE_INT) 0xffff), 7499 0, DImode))); 7500 } 7501 7502 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 7503 DONE; 7504 } 7505}") 7506 7507(define_insn "*booldi3_internal1" 7508 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") 7509 (match_operator:DI 3 "boolean_or_operator" 7510 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") 7511 (match_operand:DI 2 "logical_operand" "r,K,JF")]))] 7512 "TARGET_POWERPC64" 7513 "@ 7514 %q3 %0,%1,%2 7515 %q3i %0,%1,%b2 7516 %q3is %0,%1,%u2") 7517 7518(define_insn "*booldi3_internal2" 7519 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7520 (compare:CC (match_operator:DI 4 "boolean_or_operator" 7521 [(match_operand:DI 1 "gpc_reg_operand" "%r,r") 7522 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7523 (const_int 0))) 7524 (clobber (match_scratch:DI 3 "=r,r"))] 7525 "TARGET_64BIT" 7526 "@ 7527 %q4. %3,%1,%2 7528 #" 7529 [(set_attr "type" "compare") 7530 (set_attr "length" "4,8")]) 7531 7532(define_split 7533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7534 (compare:CC (match_operator:DI 4 "boolean_operator" 7535 [(match_operand:DI 1 "gpc_reg_operand" "") 7536 (match_operand:DI 2 "gpc_reg_operand" "")]) 7537 (const_int 0))) 7538 (clobber (match_scratch:DI 3 ""))] 7539 "TARGET_POWERPC64 && reload_completed" 7540 [(set (match_dup 3) (match_dup 4)) 7541 (set (match_dup 0) 7542 (compare:CC (match_dup 3) 7543 (const_int 0)))] 7544 "") 7545 7546(define_insn "*booldi3_internal3" 7547 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7548 (compare:CC (match_operator:DI 4 "boolean_operator" 7549 [(match_operand:DI 1 "gpc_reg_operand" "%r,r") 7550 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7551 (const_int 0))) 7552 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7553 (match_dup 4))] 7554 "TARGET_64BIT" 7555 "@ 7556 %q4. %0,%1,%2 7557 #" 7558 [(set_attr "type" "compare") 7559 (set_attr "length" "4,8")]) 7560 7561(define_split 7562 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7563 (compare:CC (match_operator:DI 4 "boolean_operator" 7564 [(match_operand:DI 1 "gpc_reg_operand" "") 7565 (match_operand:DI 2 "gpc_reg_operand" "")]) 7566 (const_int 0))) 7567 (set (match_operand:DI 0 "gpc_reg_operand" "") 7568 (match_dup 4))] 7569 "TARGET_POWERPC64 && reload_completed" 7570 [(set (match_dup 0) (match_dup 4)) 7571 (set (match_dup 3) 7572 (compare:CC (match_dup 0) 7573 (const_int 0)))] 7574 "") 7575 7576;; Split a logical operation that we can't do in one insn into two insns, 7577;; each of which does one 16-bit part. This is used by combine. 7578 7579(define_split 7580 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7581 (match_operator:DI 3 "boolean_or_operator" 7582 [(match_operand:DI 1 "gpc_reg_operand" "") 7583 (match_operand:DI 2 "non_logical_cint_operand" "")]))] 7584 "TARGET_POWERPC64" 7585 [(set (match_dup 0) (match_dup 4)) 7586 (set (match_dup 0) (match_dup 5))] 7587" 7588{ 7589 rtx i3,i4; 7590 7591 if (GET_CODE (operands[2]) == CONST_DOUBLE) 7592 { 7593 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); 7594 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), 7595 0, DImode); 7596 i4 = GEN_INT (value & 0xffff); 7597 } 7598 else 7599 { 7600 i3 = GEN_INT (INTVAL (operands[2]) 7601 & (~ (HOST_WIDE_INT) 0xffff)); 7602 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); 7603 } 7604 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, 7605 operands[1], i3); 7606 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, 7607 operands[0], i4); 7608}") 7609 7610(define_insn "*boolcdi3_internal1" 7611 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7612 (match_operator:DI 3 "boolean_operator" 7613 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) 7614 (match_operand:DI 2 "gpc_reg_operand" "r")]))] 7615 "TARGET_POWERPC64" 7616 "%q3 %0,%2,%1") 7617 7618(define_insn "*boolcdi3_internal2" 7619 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7620 (compare:CC (match_operator:DI 4 "boolean_operator" 7621 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 7622 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7623 (const_int 0))) 7624 (clobber (match_scratch:DI 3 "=r,r"))] 7625 "TARGET_64BIT" 7626 "@ 7627 %q4. %3,%2,%1 7628 #" 7629 [(set_attr "type" "compare") 7630 (set_attr "length" "4,8")]) 7631 7632(define_split 7633 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7634 (compare:CC (match_operator:DI 4 "boolean_operator" 7635 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7636 (match_operand:DI 2 "gpc_reg_operand" "")]) 7637 (const_int 0))) 7638 (clobber (match_scratch:DI 3 ""))] 7639 "TARGET_POWERPC64 && reload_completed" 7640 [(set (match_dup 3) (match_dup 4)) 7641 (set (match_dup 0) 7642 (compare:CC (match_dup 3) 7643 (const_int 0)))] 7644 "") 7645 7646(define_insn "*boolcdi3_internal3" 7647 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7648 (compare:CC (match_operator:DI 4 "boolean_operator" 7649 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) 7650 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7651 (const_int 0))) 7652 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7653 (match_dup 4))] 7654 "TARGET_64BIT" 7655 "@ 7656 %q4. %0,%2,%1 7657 #" 7658 [(set_attr "type" "compare") 7659 (set_attr "length" "4,8")]) 7660 7661(define_split 7662 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7663 (compare:CC (match_operator:DI 4 "boolean_operator" 7664 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7665 (match_operand:DI 2 "gpc_reg_operand" "")]) 7666 (const_int 0))) 7667 (set (match_operand:DI 0 "gpc_reg_operand" "") 7668 (match_dup 4))] 7669 "TARGET_POWERPC64 && reload_completed" 7670 [(set (match_dup 0) (match_dup 4)) 7671 (set (match_dup 3) 7672 (compare:CC (match_dup 0) 7673 (const_int 0)))] 7674 "") 7675 7676(define_insn "*boolccdi3_internal1" 7677 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7678 (match_operator:DI 3 "boolean_operator" 7679 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) 7680 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] 7681 "TARGET_POWERPC64" 7682 "%q3 %0,%1,%2") 7683 7684(define_insn "*boolccdi3_internal2" 7685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7686 (compare:CC (match_operator:DI 4 "boolean_operator" 7687 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 7688 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) 7689 (const_int 0))) 7690 (clobber (match_scratch:DI 3 "=r,r"))] 7691 "TARGET_64BIT" 7692 "@ 7693 %q4. %3,%1,%2 7694 #" 7695 [(set_attr "type" "compare") 7696 (set_attr "length" "4,8")]) 7697 7698(define_split 7699 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7700 (compare:CC (match_operator:DI 4 "boolean_operator" 7701 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7702 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) 7703 (const_int 0))) 7704 (clobber (match_scratch:DI 3 ""))] 7705 "TARGET_POWERPC64 && reload_completed" 7706 [(set (match_dup 3) (match_dup 4)) 7707 (set (match_dup 0) 7708 (compare:CC (match_dup 3) 7709 (const_int 0)))] 7710 "") 7711 7712(define_insn "*boolccdi3_internal3" 7713 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7714 (compare:CC (match_operator:DI 4 "boolean_operator" 7715 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) 7716 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) 7717 (const_int 0))) 7718 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7719 (match_dup 4))] 7720 "TARGET_64BIT" 7721 "@ 7722 %q4. %0,%1,%2 7723 #" 7724 [(set_attr "type" "compare") 7725 (set_attr "length" "4,8")]) 7726 7727(define_split 7728 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7729 (compare:CC (match_operator:DI 4 "boolean_operator" 7730 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7731 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) 7732 (const_int 0))) 7733 (set (match_operand:DI 0 "gpc_reg_operand" "") 7734 (match_dup 4))] 7735 "TARGET_POWERPC64 && reload_completed" 7736 [(set (match_dup 0) (match_dup 4)) 7737 (set (match_dup 3) 7738 (compare:CC (match_dup 0) 7739 (const_int 0)))] 7740 "") 7741 7742;; Now define ways of moving data around. 7743 7744;; Set up a register with a value from the GOT table 7745 7746(define_expand "movsi_got" 7747 [(set (match_operand:SI 0 "gpc_reg_operand" "") 7748 (unspec:SI [(match_operand:SI 1 "got_operand" "") 7749 (match_dup 2)] UNSPEC_MOVSI_GOT))] 7750 "DEFAULT_ABI == ABI_V4 && flag_pic == 1" 7751 " 7752{ 7753 if (GET_CODE (operands[1]) == CONST) 7754 { 7755 rtx offset = const0_rtx; 7756 HOST_WIDE_INT value; 7757 7758 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); 7759 value = INTVAL (offset); 7760 if (value != 0) 7761 { 7762 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); 7763 emit_insn (gen_movsi_got (tmp, operands[1])); 7764 emit_insn (gen_addsi3 (operands[0], tmp, offset)); 7765 DONE; 7766 } 7767 } 7768 7769 operands[2] = rs6000_got_register (operands[1]); 7770}") 7771 7772(define_insn "*movsi_got_internal" 7773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7774 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") 7775 (match_operand:SI 2 "gpc_reg_operand" "b")] 7776 UNSPEC_MOVSI_GOT))] 7777 "DEFAULT_ABI == ABI_V4 && flag_pic == 1" 7778 "{l|lwz} %0,%a1@got(%2)" 7779 [(set_attr "type" "load")]) 7780 7781;; Used by sched, shorten_branches and final when the GOT pseudo reg 7782;; didn't get allocated to a hard register. 7783(define_split 7784 [(set (match_operand:SI 0 "gpc_reg_operand" "") 7785 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") 7786 (match_operand:SI 2 "memory_operand" "")] 7787 UNSPEC_MOVSI_GOT))] 7788 "DEFAULT_ABI == ABI_V4 7789 && flag_pic == 1 7790 && (reload_in_progress || reload_completed)" 7791 [(set (match_dup 0) (match_dup 2)) 7792 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 7793 UNSPEC_MOVSI_GOT))] 7794 "") 7795 7796;; For SI, we special-case integers that can't be loaded in one insn. We 7797;; do the load 16-bits at a time. We could do this by loading from memory, 7798;; and this is even supposed to be faster, but it is simpler not to get 7799;; integers in the TOC. 7800(define_insn "movsi_low" 7801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7802 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") 7803 (match_operand 2 "" ""))))] 7804 "TARGET_MACHO && ! TARGET_64BIT" 7805 "{l|lwz} %0,lo16(%2)(%1)" 7806 [(set_attr "type" "load") 7807 (set_attr "length" "4")]) 7808 7809(define_insn "*movsi_internal1" 7810 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") 7811 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] 7812 "gpc_reg_operand (operands[0], SImode) 7813 || gpc_reg_operand (operands[1], SImode)" 7814 "@ 7815 mr %0,%1 7816 {cal|la} %0,%a1 7817 {l%U1%X1|lwz%U1%X1} %0,%1 7818 {st%U0%X0|stw%U0%X0} %1,%0 7819 {lil|li} %0,%1 7820 {liu|lis} %0,%v1 7821 # 7822 {cal|la} %0,%a1 7823 mf%1 %0 7824 mt%0 %1 7825 mt%0 %1 7826 mt%0 %1 7827 {cror 0,0,0|nop}" 7828 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") 7829 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) 7830 7831;; Split a load of a large constant into the appropriate two-insn 7832;; sequence. 7833 7834(define_split 7835 [(set (match_operand:SI 0 "gpc_reg_operand" "") 7836 (match_operand:SI 1 "const_int_operand" ""))] 7837 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 7838 && (INTVAL (operands[1]) & 0xffff) != 0" 7839 [(set (match_dup 0) 7840 (match_dup 2)) 7841 (set (match_dup 0) 7842 (ior:SI (match_dup 0) 7843 (match_dup 3)))] 7844 " 7845{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); 7846 7847 if (tem == operands[0]) 7848 DONE; 7849 else 7850 FAIL; 7851}") 7852 7853(define_insn "*mov<mode>_internal2" 7854 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") 7855 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r") 7856 (const_int 0))) 7857 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] 7858 "" 7859 "@ 7860 {cmpi|cmp<wd>i} %2,%0,0 7861 mr. %0,%1 7862 #" 7863 [(set_attr "type" "cmp,compare,cmp") 7864 (set_attr "length" "4,4,8")]) 7865 7866(define_split 7867 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 7868 (compare:CC (match_operand:P 1 "gpc_reg_operand" "") 7869 (const_int 0))) 7870 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))] 7871 "reload_completed" 7872 [(set (match_dup 0) (match_dup 1)) 7873 (set (match_dup 2) 7874 (compare:CC (match_dup 0) 7875 (const_int 0)))] 7876 "") 7877 7878(define_insn "*movhi_internal" 7879 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 7880 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 7881 "gpc_reg_operand (operands[0], HImode) 7882 || gpc_reg_operand (operands[1], HImode)" 7883 "@ 7884 mr %0,%1 7885 lhz%U1%X1 %0,%1 7886 sth%U0%X0 %1,%0 7887 {lil|li} %0,%w1 7888 mf%1 %0 7889 mt%0 %1 7890 mt%0 %1 7891 {cror 0,0,0|nop}" 7892 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) 7893 7894(define_expand "mov<mode>" 7895 [(set (match_operand:INT 0 "general_operand" "") 7896 (match_operand:INT 1 "any_operand" ""))] 7897 "" 7898 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") 7899 7900(define_insn "*movqi_internal" 7901 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 7902 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 7903 "gpc_reg_operand (operands[0], QImode) 7904 || gpc_reg_operand (operands[1], QImode)" 7905 "@ 7906 mr %0,%1 7907 lbz%U1%X1 %0,%1 7908 stb%U0%X0 %1,%0 7909 {lil|li} %0,%1 7910 mf%1 %0 7911 mt%0 %1 7912 mt%0 %1 7913 {cror 0,0,0|nop}" 7914 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) 7915 7916;; Here is how to move condition codes around. When we store CC data in 7917;; an integer register or memory, we store just the high-order 4 bits. 7918;; This lets us not shift in the most common case of CR0. 7919(define_expand "movcc" 7920 [(set (match_operand:CC 0 "nonimmediate_operand" "") 7921 (match_operand:CC 1 "nonimmediate_operand" ""))] 7922 "" 7923 "") 7924 7925(define_insn "*movcc_internal1" 7926 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m") 7927 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))] 7928 "register_operand (operands[0], CCmode) 7929 || register_operand (operands[1], CCmode)" 7930 "@ 7931 mcrf %0,%1 7932 mtcrf 128,%1 7933 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff 7934 crxor %0,%0,%0 7935 mfcr %0%Q1 7936 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 7937 mr %0,%1 7938 {lil|li} %0,%1 7939 mf%1 %0 7940 mt%0 %1 7941 mt%0 %1 7942 {l%U1%X1|lwz%U1%X1} %0,%1 7943 {st%U0%U1|stw%U0%U1} %1,%0" 7944 [(set (attr "type") 7945 (cond [(eq_attr "alternative" "0,3") 7946 (const_string "cr_logical") 7947 (eq_attr "alternative" "1,2") 7948 (const_string "mtcr") 7949 (eq_attr "alternative" "6,7,9") 7950 (const_string "integer") 7951 (eq_attr "alternative" "8") 7952 (const_string "mfjmpr") 7953 (eq_attr "alternative" "10") 7954 (const_string "mtjmpr") 7955 (eq_attr "alternative" "11") 7956 (const_string "load") 7957 (eq_attr "alternative" "12") 7958 (const_string "store") 7959 (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) 7960 (const_string "mfcrf") 7961 ] 7962 (const_string "mfcr"))) 7963 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")]) 7964 7965;; For floating-point, we normally deal with the floating-point registers 7966;; unless -msoft-float is used. The sole exception is that parameter passing 7967;; can produce floating-point values in fixed-point registers. Unless the 7968;; value is a simple constant or already in memory, we deal with this by 7969;; allocating memory and copying the value explicitly via that memory location. 7970(define_expand "movsf" 7971 [(set (match_operand:SF 0 "nonimmediate_operand" "") 7972 (match_operand:SF 1 "any_operand" ""))] 7973 "" 7974 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") 7975 7976(define_split 7977 [(set (match_operand:SF 0 "gpc_reg_operand" "") 7978 (match_operand:SF 1 "const_double_operand" ""))] 7979 "reload_completed 7980 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 7981 || (GET_CODE (operands[0]) == SUBREG 7982 && GET_CODE (SUBREG_REG (operands[0])) == REG 7983 && REGNO (SUBREG_REG (operands[0])) <= 31))" 7984 [(set (match_dup 2) (match_dup 3))] 7985 " 7986{ 7987 long l; 7988 REAL_VALUE_TYPE rv; 7989 7990 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 7991 REAL_VALUE_TO_TARGET_SINGLE (rv, l); 7992 7993 if (! TARGET_POWERPC64) 7994 operands[2] = operand_subword (operands[0], 0, 0, SFmode); 7995 else 7996 operands[2] = gen_lowpart (SImode, operands[0]); 7997 7998 operands[3] = gen_int_mode (l, SImode); 7999}") 8000 8001(define_insn "*movsf_hardfloat" 8002 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r") 8003 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] 8004 "(gpc_reg_operand (operands[0], SFmode) 8005 || gpc_reg_operand (operands[1], SFmode)) 8006 && (TARGET_HARD_FLOAT && TARGET_FPRS)" 8007 "@ 8008 mr %0,%1 8009 {l%U1%X1|lwz%U1%X1} %0,%1 8010 {st%U0%X0|stw%U0%X0} %1,%0 8011 fmr %0,%1 8012 lfs%U1%X1 %0,%1 8013 stfs%U0%X0 %1,%0 8014 mt%0 %1 8015 mt%0 %1 8016 mf%1 %0 8017 {cror 0,0,0|nop} 8018 # 8019 #" 8020 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*") 8021 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) 8022 8023(define_insn "*movsf_softfloat" 8024 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") 8025 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] 8026 "(gpc_reg_operand (operands[0], SFmode) 8027 || gpc_reg_operand (operands[1], SFmode)) 8028 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" 8029 "@ 8030 mr %0,%1 8031 mt%0 %1 8032 mt%0 %1 8033 mf%1 %0 8034 {l%U1%X1|lwz%U1%X1} %0,%1 8035 {st%U0%X0|stw%U0%X0} %1,%0 8036 {lil|li} %0,%1 8037 {liu|lis} %0,%v1 8038 {cal|la} %0,%a1 8039 # 8040 # 8041 {cror 0,0,0|nop}" 8042 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*") 8043 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) 8044 8045 8046(define_expand "movdf" 8047 [(set (match_operand:DF 0 "nonimmediate_operand" "") 8048 (match_operand:DF 1 "any_operand" ""))] 8049 "" 8050 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") 8051 8052(define_split 8053 [(set (match_operand:DF 0 "gpc_reg_operand" "") 8054 (match_operand:DF 1 "const_int_operand" ""))] 8055 "! TARGET_POWERPC64 && reload_completed 8056 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 8057 || (GET_CODE (operands[0]) == SUBREG 8058 && GET_CODE (SUBREG_REG (operands[0])) == REG 8059 && REGNO (SUBREG_REG (operands[0])) <= 31))" 8060 [(set (match_dup 2) (match_dup 4)) 8061 (set (match_dup 3) (match_dup 1))] 8062 " 8063{ 8064 int endian = (WORDS_BIG_ENDIAN == 0); 8065 HOST_WIDE_INT value = INTVAL (operands[1]); 8066 8067 operands[2] = operand_subword (operands[0], endian, 0, DFmode); 8068 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); 8069#if HOST_BITS_PER_WIDE_INT == 32 8070 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; 8071#else 8072 operands[4] = GEN_INT (value >> 32); 8073 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); 8074#endif 8075}") 8076 8077(define_split 8078 [(set (match_operand:DF 0 "gpc_reg_operand" "") 8079 (match_operand:DF 1 "const_double_operand" ""))] 8080 "! TARGET_POWERPC64 && reload_completed 8081 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 8082 || (GET_CODE (operands[0]) == SUBREG 8083 && GET_CODE (SUBREG_REG (operands[0])) == REG 8084 && REGNO (SUBREG_REG (operands[0])) <= 31))" 8085 [(set (match_dup 2) (match_dup 4)) 8086 (set (match_dup 3) (match_dup 5))] 8087 " 8088{ 8089 int endian = (WORDS_BIG_ENDIAN == 0); 8090 long l[2]; 8091 REAL_VALUE_TYPE rv; 8092 8093 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 8094 REAL_VALUE_TO_TARGET_DOUBLE (rv, l); 8095 8096 operands[2] = operand_subword (operands[0], endian, 0, DFmode); 8097 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); 8098 operands[4] = gen_int_mode (l[endian], SImode); 8099 operands[5] = gen_int_mode (l[1 - endian], SImode); 8100}") 8101 8102(define_split 8103 [(set (match_operand:DF 0 "gpc_reg_operand" "") 8104 (match_operand:DF 1 "const_double_operand" ""))] 8105 "TARGET_POWERPC64 && reload_completed 8106 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 8107 || (GET_CODE (operands[0]) == SUBREG 8108 && GET_CODE (SUBREG_REG (operands[0])) == REG 8109 && REGNO (SUBREG_REG (operands[0])) <= 31))" 8110 [(set (match_dup 2) (match_dup 3))] 8111 " 8112{ 8113 int endian = (WORDS_BIG_ENDIAN == 0); 8114 long l[2]; 8115 REAL_VALUE_TYPE rv; 8116#if HOST_BITS_PER_WIDE_INT >= 64 8117 HOST_WIDE_INT val; 8118#endif 8119 8120 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 8121 REAL_VALUE_TO_TARGET_DOUBLE (rv, l); 8122 8123 operands[2] = gen_lowpart (DImode, operands[0]); 8124 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ 8125#if HOST_BITS_PER_WIDE_INT >= 64 8126 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 8127 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); 8128 8129 operands[3] = gen_int_mode (val, DImode); 8130#else 8131 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); 8132#endif 8133}") 8134 8135;; Don't have reload use general registers to load a constant. First, 8136;; it might not work if the output operand is the equivalent of 8137;; a non-offsettable memref, but also it is less efficient than loading 8138;; the constant into an FP register, since it will probably be used there. 8139;; The "??" is a kludge until we can figure out a more reasonable way 8140;; of handling these non-offsettable values. 8141(define_insn "*movdf_hardfloat32" 8142 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") 8143 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] 8144 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS 8145 && (gpc_reg_operand (operands[0], DFmode) 8146 || gpc_reg_operand (operands[1], DFmode))" 8147 "* 8148{ 8149 switch (which_alternative) 8150 { 8151 default: 8152 gcc_unreachable (); 8153 case 0: 8154 /* We normally copy the low-numbered register first. However, if 8155 the first register operand 0 is the same as the second register 8156 of operand 1, we must copy in the opposite order. */ 8157 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8158 return \"mr %L0,%L1\;mr %0,%1\"; 8159 else 8160 return \"mr %0,%1\;mr %L0,%L1\"; 8161 case 1: 8162 if (rs6000_offsettable_memref_p (operands[1]) 8163 || (GET_CODE (operands[1]) == MEM 8164 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM 8165 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC 8166 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) 8167 { 8168 /* If the low-address word is used in the address, we must load 8169 it last. Otherwise, load it first. Note that we cannot have 8170 auto-increment in that case since the address register is 8171 known to be dead. */ 8172 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8173 operands[1], 0)) 8174 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 8175 else 8176 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 8177 } 8178 else 8179 { 8180 rtx addreg; 8181 8182 addreg = find_addr_reg (XEXP (operands[1], 0)); 8183 if (refers_to_regno_p (REGNO (operands[0]), 8184 REGNO (operands[0]) + 1, 8185 operands[1], 0)) 8186 { 8187 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); 8188 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); 8189 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 8190 return \"{lx|lwzx} %0,%1\"; 8191 } 8192 else 8193 { 8194 output_asm_insn (\"{lx|lwzx} %0,%1\", operands); 8195 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); 8196 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); 8197 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 8198 return \"\"; 8199 } 8200 } 8201 case 2: 8202 if (rs6000_offsettable_memref_p (operands[0]) 8203 || (GET_CODE (operands[0]) == MEM 8204 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM 8205 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC 8206 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) 8207 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 8208 else 8209 { 8210 rtx addreg; 8211 8212 addreg = find_addr_reg (XEXP (operands[0], 0)); 8213 output_asm_insn (\"{stx|stwx} %1,%0\", operands); 8214 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); 8215 output_asm_insn (\"{stx|stwx} %L1,%0\", operands); 8216 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 8217 return \"\"; 8218 } 8219 case 3: 8220 return \"fmr %0,%1\"; 8221 case 4: 8222 return \"lfd%U1%X1 %0,%1\"; 8223 case 5: 8224 return \"stfd%U0%X0 %1,%0\"; 8225 case 6: 8226 case 7: 8227 case 8: 8228 return \"#\"; 8229 } 8230}" 8231 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") 8232 (set_attr "length" "8,16,16,4,4,4,8,12,16")]) 8233 8234(define_insn "*movdf_softfloat32" 8235 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") 8236 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] 8237 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) 8238 && (gpc_reg_operand (operands[0], DFmode) 8239 || gpc_reg_operand (operands[1], DFmode))" 8240 "* 8241{ 8242 switch (which_alternative) 8243 { 8244 default: 8245 gcc_unreachable (); 8246 case 0: 8247 /* We normally copy the low-numbered register first. However, if 8248 the first register operand 0 is the same as the second register of 8249 operand 1, we must copy in the opposite order. */ 8250 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8251 return \"mr %L0,%L1\;mr %0,%1\"; 8252 else 8253 return \"mr %0,%1\;mr %L0,%L1\"; 8254 case 1: 8255 /* If the low-address word is used in the address, we must load 8256 it last. Otherwise, load it first. Note that we cannot have 8257 auto-increment in that case since the address register is 8258 known to be dead. */ 8259 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8260 operands[1], 0)) 8261 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 8262 else 8263 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 8264 case 2: 8265 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 8266 case 3: 8267 case 4: 8268 case 5: 8269 return \"#\"; 8270 } 8271}" 8272 [(set_attr "type" "two,load,store,*,*,*") 8273 (set_attr "length" "8,8,8,8,12,16")]) 8274 8275; ld/std require word-aligned displacements -> 'Y' constraint. 8276; List Y->r and r->Y before r->r for reload. 8277(define_insn "*movdf_hardfloat64" 8278 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r") 8279 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] 8280 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS 8281 && (gpc_reg_operand (operands[0], DFmode) 8282 || gpc_reg_operand (operands[1], DFmode))" 8283 "@ 8284 std%U0%X0 %1,%0 8285 ld%U1%X1 %0,%1 8286 mr %0,%1 8287 fmr %0,%1 8288 lfd%U1%X1 %0,%1 8289 stfd%U0%X0 %1,%0 8290 mt%0 %1 8291 mf%1 %0 8292 {cror 0,0,0|nop} 8293 # 8294 # 8295 #" 8296 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*") 8297 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) 8298 8299(define_insn "*movdf_softfloat64" 8300 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") 8301 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] 8302 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) 8303 && (gpc_reg_operand (operands[0], DFmode) 8304 || gpc_reg_operand (operands[1], DFmode))" 8305 "@ 8306 ld%U1%X1 %0,%1 8307 std%U0%X0 %1,%0 8308 mr %0,%1 8309 mt%0 %1 8310 mf%1 %0 8311 # 8312 # 8313 # 8314 {cror 0,0,0|nop}" 8315 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*") 8316 (set_attr "length" "4,4,4,4,4,8,12,16,4")]) 8317 8318(define_expand "movtf" 8319 [(set (match_operand:TF 0 "general_operand" "") 8320 (match_operand:TF 1 "any_operand" ""))] 8321 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128" 8322 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") 8323 8324; It's important to list the o->f and f->o moves before f->f because 8325; otherwise reload, given m->f, will try to pick f->f and reload it, 8326; which doesn't make progress. Likewise r->Y must be before r->r. 8327(define_insn_and_split "*movtf_internal" 8328 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r") 8329 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))] 8330 "!TARGET_IEEEQUAD 8331 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 8332 && (gpc_reg_operand (operands[0], TFmode) 8333 || gpc_reg_operand (operands[1], TFmode))" 8334 "#" 8335 "&& reload_completed" 8336 [(pc)] 8337{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } 8338 [(set_attr "length" "8,8,8,20,20,16")]) 8339 8340(define_insn_and_split "*movtf_softfloat" 8341 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,Y,r") 8342 (match_operand:TF 1 "input_operand" "YGHF,r,r"))] 8343 "!TARGET_IEEEQUAD 8344 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128 8345 && (gpc_reg_operand (operands[0], TFmode) 8346 || gpc_reg_operand (operands[1], TFmode))" 8347 "#" 8348 "&& reload_completed" 8349 [(pc)] 8350{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } 8351 [(set_attr "length" "20,20,16")]) 8352 8353(define_expand "extenddftf2" 8354 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") 8355 (float_extend:TF (match_operand:DF 1 "input_operand" ""))) 8356 (use (match_dup 2))])] 8357 "!TARGET_IEEEQUAD 8358 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8359{ 8360 operands[2] = CONST0_RTX (DFmode); 8361 /* Generate GOT reference early for SVR4 PIC. */ 8362 if (DEFAULT_ABI == ABI_V4 && flag_pic) 8363 operands[2] = validize_mem (force_const_mem (DFmode, operands[2])); 8364}) 8365 8366(define_insn_and_split "*extenddftf2_internal" 8367 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") 8368 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) 8369 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))] 8370 "!TARGET_IEEEQUAD 8371 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8372 "#" 8373 "&& reload_completed" 8374 [(pc)] 8375{ 8376 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; 8377 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); 8378 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), 8379 operands[1]); 8380 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), 8381 operands[2]); 8382 DONE; 8383}) 8384 8385(define_expand "extendsftf2" 8386 [(set (match_operand:TF 0 "nonimmediate_operand" "") 8387 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] 8388 "!TARGET_IEEEQUAD 8389 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8390{ 8391 rtx tmp = gen_reg_rtx (DFmode); 8392 emit_insn (gen_extendsfdf2 (tmp, operands[1])); 8393 emit_insn (gen_extenddftf2 (operands[0], tmp)); 8394 DONE; 8395}) 8396 8397(define_expand "trunctfdf2" 8398 [(set (match_operand:DF 0 "gpc_reg_operand" "") 8399 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))] 8400 "!TARGET_IEEEQUAD 8401 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8402 "") 8403 8404(define_insn_and_split "trunctfdf2_internal1" 8405 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") 8406 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))] 8407 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT 8408 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8409 "@ 8410 # 8411 fmr %0,%1" 8412 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" 8413 [(const_int 0)] 8414{ 8415 emit_note (NOTE_INSN_DELETED); 8416 DONE; 8417} 8418 [(set_attr "type" "fp")]) 8419 8420(define_insn "trunctfdf2_internal2" 8421 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 8422 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8423 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT 8424 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8425 "fadd %0,%1,%L1" 8426 [(set_attr "type" "fp")]) 8427 8428(define_insn_and_split "trunctfsf2" 8429 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 8430 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) 8431 (clobber (match_scratch:DF 2 "=f"))] 8432 "!TARGET_IEEEQUAD 8433 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8434 "#" 8435 "&& reload_completed" 8436 [(set (match_dup 2) 8437 (float_truncate:DF (match_dup 1))) 8438 (set (match_dup 0) 8439 (float_truncate:SF (match_dup 2)))] 8440 "") 8441 8442(define_expand "floatsitf2" 8443 [(set (match_operand:TF 0 "gpc_reg_operand" "") 8444 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))] 8445 "!TARGET_IEEEQUAD 8446 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8447{ 8448 rtx tmp = gen_reg_rtx (DFmode); 8449 expand_float (tmp, operands[1], false); 8450 emit_insn (gen_extenddftf2 (operands[0], tmp)); 8451 DONE; 8452}) 8453 8454; fadd, but rounding towards zero. 8455; This is probably not the optimal code sequence. 8456(define_insn "fix_trunc_helper" 8457 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 8458 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] 8459 UNSPEC_FIX_TRUNC_TF)) 8460 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] 8461 "TARGET_HARD_FLOAT && TARGET_FPRS" 8462 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" 8463 [(set_attr "type" "fp") 8464 (set_attr "length" "20")]) 8465 8466(define_expand "fix_trunctfsi2" 8467 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 8468 (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) 8469 (clobber (match_dup 2)) 8470 (clobber (match_dup 3)) 8471 (clobber (match_dup 4)) 8472 (clobber (match_dup 5))])] 8473 "!TARGET_IEEEQUAD 8474 && (TARGET_POWER2 || TARGET_POWERPC) 8475 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8476{ 8477 operands[2] = gen_reg_rtx (DFmode); 8478 operands[3] = gen_reg_rtx (DFmode); 8479 operands[4] = gen_reg_rtx (DImode); 8480 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 8481}) 8482 8483(define_insn_and_split "*fix_trunctfsi2_internal" 8484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 8485 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) 8486 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) 8487 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) 8488 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) 8489 (clobber (match_operand:DI 5 "memory_operand" "=o"))] 8490 "!TARGET_IEEEQUAD 8491 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8492 "#" 8493 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))" 8494 [(pc)] 8495{ 8496 rtx lowword; 8497 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); 8498 8499 gcc_assert (MEM_P (operands[5])); 8500 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0); 8501 8502 emit_insn (gen_fctiwz (operands[4], operands[2])); 8503 emit_move_insn (operands[5], operands[4]); 8504 emit_move_insn (operands[0], lowword); 8505 DONE; 8506}) 8507 8508(define_insn "negtf2" 8509 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8510 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8511 "!TARGET_IEEEQUAD 8512 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8513 "* 8514{ 8515 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8516 return \"fneg %L0,%L1\;fneg %0,%1\"; 8517 else 8518 return \"fneg %0,%1\;fneg %L0,%L1\"; 8519}" 8520 [(set_attr "type" "fp") 8521 (set_attr "length" "8")]) 8522 8523(define_expand "abstf2" 8524 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8525 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8526 "!TARGET_IEEEQUAD 8527 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8528 " 8529{ 8530 rtx label = gen_label_rtx (); 8531 emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); 8532 emit_label (label); 8533 DONE; 8534}") 8535 8536(define_expand "abstf2_internal" 8537 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8538 (match_operand:TF 1 "gpc_reg_operand" "f")) 8539 (set (match_dup 3) (match_dup 5)) 8540 (set (match_dup 5) (abs:DF (match_dup 5))) 8541 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) 8542 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) 8543 (label_ref (match_operand 2 "" "")) 8544 (pc))) 8545 (set (match_dup 6) (neg:DF (match_dup 6)))] 8546 "!TARGET_IEEEQUAD 8547 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8548 " 8549{ 8550 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); 8551 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; 8552 operands[3] = gen_reg_rtx (DFmode); 8553 operands[4] = gen_reg_rtx (CCFPmode); 8554 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); 8555 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); 8556}") 8557 8558;; Next come the multi-word integer load and store and the load and store 8559;; multiple insns. 8560 8561; List r->r after r->"o<>", otherwise reload will try to reload a 8562; non-offsettable address by using r->r which won't make progress. 8563(define_insn "*movdi_internal32" 8564 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r") 8565 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] 8566 "! TARGET_POWERPC64 8567 && (gpc_reg_operand (operands[0], DImode) 8568 || gpc_reg_operand (operands[1], DImode))" 8569 "@ 8570 # 8571 # 8572 # 8573 fmr %0,%1 8574 lfd%U1%X1 %0,%1 8575 stfd%U0%X0 %1,%0 8576 #" 8577 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")]) 8578 8579(define_split 8580 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8581 (match_operand:DI 1 "const_int_operand" ""))] 8582 "! TARGET_POWERPC64 && reload_completed" 8583 [(set (match_dup 2) (match_dup 4)) 8584 (set (match_dup 3) (match_dup 1))] 8585 " 8586{ 8587 HOST_WIDE_INT value = INTVAL (operands[1]); 8588 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, 8589 DImode); 8590 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, 8591 DImode); 8592#if HOST_BITS_PER_WIDE_INT == 32 8593 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; 8594#else 8595 operands[4] = GEN_INT (value >> 32); 8596 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); 8597#endif 8598}") 8599 8600(define_split 8601 [(set (match_operand:DI 0 "nonimmediate_operand" "") 8602 (match_operand:DI 1 "input_operand" ""))] 8603 "reload_completed && !TARGET_POWERPC64 8604 && gpr_or_gpr_p (operands[0], operands[1])" 8605 [(pc)] 8606{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 8607 8608(define_insn "*movdi_internal64" 8609 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h") 8610 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] 8611 "TARGET_POWERPC64 8612 && (gpc_reg_operand (operands[0], DImode) 8613 || gpc_reg_operand (operands[1], DImode))" 8614 "@ 8615 mr %0,%1 8616 ld%U1%X1 %0,%1 8617 std%U0%X0 %1,%0 8618 li %0,%1 8619 lis %0,%v1 8620 # 8621 {cal|la} %0,%a1 8622 fmr %0,%1 8623 lfd%U1%X1 %0,%1 8624 stfd%U0%X0 %1,%0 8625 mf%1 %0 8626 mt%0 %1 8627 {cror 0,0,0|nop}" 8628 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") 8629 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) 8630 8631;; immediate value valid for a single instruction hiding in a const_double 8632(define_insn "" 8633 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 8634 (match_operand:DI 1 "const_double_operand" "F"))] 8635 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 8636 && GET_CODE (operands[1]) == CONST_DOUBLE 8637 && num_insns_constant (operands[1], DImode) == 1" 8638 "* 8639{ 8640 return ((unsigned HOST_WIDE_INT) 8641 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) 8642 ? \"li %0,%1\" : \"lis %0,%v1\"; 8643}") 8644 8645;; Generate all one-bits and clear left or right. 8646;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. 8647(define_split 8648 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8649 (match_operand:DI 1 "mask64_operand" ""))] 8650 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 8651 [(set (match_dup 0) (const_int -1)) 8652 (set (match_dup 0) 8653 (and:DI (rotate:DI (match_dup 0) 8654 (const_int 0)) 8655 (match_dup 1)))] 8656 "") 8657 8658;; Split a load of a large constant into the appropriate five-instruction 8659;; sequence. Handle anything in a constant number of insns. 8660;; When non-easy constants can go in the TOC, this should use 8661;; easy_fp_constant predicate. 8662(define_split 8663 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8664 (match_operand:DI 1 "const_int_operand" ""))] 8665 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 8666 [(set (match_dup 0) (match_dup 2)) 8667 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 8668 " 8669{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); 8670 8671 if (tem == operands[0]) 8672 DONE; 8673 else 8674 FAIL; 8675}") 8676 8677(define_split 8678 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8679 (match_operand:DI 1 "const_double_operand" ""))] 8680 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 8681 [(set (match_dup 0) (match_dup 2)) 8682 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 8683 " 8684{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); 8685 8686 if (tem == operands[0]) 8687 DONE; 8688 else 8689 FAIL; 8690}") 8691 8692;; TImode is similar, except that we usually want to compute the address into 8693;; a register and use lsi/stsi (the exception is during reload). MQ is also 8694;; clobbered in stsi for POWER, so we need a SCRATCH for it. 8695 8696;; We say that MQ is clobbered in the last alternative because the first 8697;; alternative would never get used otherwise since it would need a reload 8698;; while the 2nd alternative would not. We put memory cases first so they 8699;; are preferred. Otherwise, we'd try to reload the output instead of 8700;; giving the SCRATCH mq. 8701 8702(define_insn "*movti_power" 8703 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r") 8704 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n")) 8705 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))] 8706 "TARGET_POWER && ! TARGET_POWERPC64 8707 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" 8708 "* 8709{ 8710 switch (which_alternative) 8711 { 8712 default: 8713 gcc_unreachable (); 8714 8715 case 0: 8716 if (TARGET_STRING) 8717 return \"{stsi|stswi} %1,%P0,16\"; 8718 case 1: 8719 case 2: 8720 return \"#\"; 8721 case 3: 8722 /* If the address is not used in the output, we can use lsi. Otherwise, 8723 fall through to generating four loads. */ 8724 if (TARGET_STRING 8725 && ! reg_overlap_mentioned_p (operands[0], operands[1])) 8726 return \"{lsi|lswi} %0,%P1,16\"; 8727 /* ... fall through ... */ 8728 case 4: 8729 case 5: 8730 return \"#\"; 8731 } 8732}" 8733 [(set_attr "type" "store,store,*,load,load,*")]) 8734 8735(define_insn "*movti_string" 8736 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r") 8737 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))] 8738 "! TARGET_POWER && ! TARGET_POWERPC64 8739 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" 8740 "* 8741{ 8742 switch (which_alternative) 8743 { 8744 default: 8745 gcc_unreachable (); 8746 case 0: 8747 if (TARGET_STRING) 8748 return \"{stsi|stswi} %1,%P0,16\"; 8749 case 1: 8750 case 2: 8751 return \"#\"; 8752 case 3: 8753 /* If the address is not used in the output, we can use lsi. Otherwise, 8754 fall through to generating four loads. */ 8755 if (TARGET_STRING 8756 && ! reg_overlap_mentioned_p (operands[0], operands[1])) 8757 return \"{lsi|lswi} %0,%P1,16\"; 8758 /* ... fall through ... */ 8759 case 4: 8760 case 5: 8761 return \"#\"; 8762 } 8763}" 8764 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")]) 8765 8766(define_insn "*movti_ppc64" 8767 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") 8768 (match_operand:TI 1 "input_operand" "r,r,m"))] 8769 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) 8770 || gpc_reg_operand (operands[1], TImode))" 8771 "#" 8772 [(set_attr "type" "*,load,store")]) 8773 8774(define_split 8775 [(set (match_operand:TI 0 "gpc_reg_operand" "") 8776 (match_operand:TI 1 "const_double_operand" ""))] 8777 "TARGET_POWERPC64" 8778 [(set (match_dup 2) (match_dup 4)) 8779 (set (match_dup 3) (match_dup 5))] 8780 " 8781{ 8782 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, 8783 TImode); 8784 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, 8785 TImode); 8786 if (GET_CODE (operands[1]) == CONST_DOUBLE) 8787 { 8788 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); 8789 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); 8790 } 8791 else if (GET_CODE (operands[1]) == CONST_INT) 8792 { 8793 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); 8794 operands[5] = operands[1]; 8795 } 8796 else 8797 FAIL; 8798}") 8799 8800(define_split 8801 [(set (match_operand:TI 0 "nonimmediate_operand" "") 8802 (match_operand:TI 1 "input_operand" ""))] 8803 "reload_completed 8804 && gpr_or_gpr_p (operands[0], operands[1])" 8805 [(pc)] 8806{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 8807 8808(define_expand "load_multiple" 8809 [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 8810 (match_operand:SI 1 "" "")) 8811 (use (match_operand:SI 2 "" ""))])] 8812 "TARGET_STRING && !TARGET_POWERPC64" 8813 " 8814{ 8815 int regno; 8816 int count; 8817 rtx op1; 8818 int i; 8819 8820 /* Support only loading a constant number of fixed-point registers from 8821 memory and only bother with this if more than two; the machine 8822 doesn't support more than eight. */ 8823 if (GET_CODE (operands[2]) != CONST_INT 8824 || INTVAL (operands[2]) <= 2 8825 || INTVAL (operands[2]) > 8 8826 || GET_CODE (operands[1]) != MEM 8827 || GET_CODE (operands[0]) != REG 8828 || REGNO (operands[0]) >= 32) 8829 FAIL; 8830 8831 count = INTVAL (operands[2]); 8832 regno = REGNO (operands[0]); 8833 8834 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 8835 op1 = replace_equiv_address (operands[1], 8836 force_reg (SImode, XEXP (operands[1], 0))); 8837 8838 for (i = 0; i < count; i++) 8839 XVECEXP (operands[3], 0, i) 8840 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), 8841 adjust_address_nv (op1, SImode, i * 4)); 8842}") 8843 8844(define_insn "*ldmsi8" 8845 [(match_parallel 0 "load_multiple_operation" 8846 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8847 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8848 (set (match_operand:SI 3 "gpc_reg_operand" "") 8849 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8850 (set (match_operand:SI 4 "gpc_reg_operand" "") 8851 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8852 (set (match_operand:SI 5 "gpc_reg_operand" "") 8853 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 8854 (set (match_operand:SI 6 "gpc_reg_operand" "") 8855 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) 8856 (set (match_operand:SI 7 "gpc_reg_operand" "") 8857 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) 8858 (set (match_operand:SI 8 "gpc_reg_operand" "") 8859 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) 8860 (set (match_operand:SI 9 "gpc_reg_operand" "") 8861 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] 8862 "TARGET_STRING && XVECLEN (operands[0], 0) == 8" 8863 "* 8864{ return rs6000_output_load_multiple (operands); }" 8865 [(set_attr "type" "load_ux") 8866 (set_attr "length" "32")]) 8867 8868(define_insn "*ldmsi7" 8869 [(match_parallel 0 "load_multiple_operation" 8870 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8871 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8872 (set (match_operand:SI 3 "gpc_reg_operand" "") 8873 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8874 (set (match_operand:SI 4 "gpc_reg_operand" "") 8875 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8876 (set (match_operand:SI 5 "gpc_reg_operand" "") 8877 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 8878 (set (match_operand:SI 6 "gpc_reg_operand" "") 8879 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) 8880 (set (match_operand:SI 7 "gpc_reg_operand" "") 8881 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) 8882 (set (match_operand:SI 8 "gpc_reg_operand" "") 8883 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] 8884 "TARGET_STRING && XVECLEN (operands[0], 0) == 7" 8885 "* 8886{ return rs6000_output_load_multiple (operands); }" 8887 [(set_attr "type" "load_ux") 8888 (set_attr "length" "32")]) 8889 8890(define_insn "*ldmsi6" 8891 [(match_parallel 0 "load_multiple_operation" 8892 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8893 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8894 (set (match_operand:SI 3 "gpc_reg_operand" "") 8895 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8896 (set (match_operand:SI 4 "gpc_reg_operand" "") 8897 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8898 (set (match_operand:SI 5 "gpc_reg_operand" "") 8899 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 8900 (set (match_operand:SI 6 "gpc_reg_operand" "") 8901 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) 8902 (set (match_operand:SI 7 "gpc_reg_operand" "") 8903 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] 8904 "TARGET_STRING && XVECLEN (operands[0], 0) == 6" 8905 "* 8906{ return rs6000_output_load_multiple (operands); }" 8907 [(set_attr "type" "load_ux") 8908 (set_attr "length" "32")]) 8909 8910(define_insn "*ldmsi5" 8911 [(match_parallel 0 "load_multiple_operation" 8912 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8913 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8914 (set (match_operand:SI 3 "gpc_reg_operand" "") 8915 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8916 (set (match_operand:SI 4 "gpc_reg_operand" "") 8917 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8918 (set (match_operand:SI 5 "gpc_reg_operand" "") 8919 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 8920 (set (match_operand:SI 6 "gpc_reg_operand" "") 8921 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] 8922 "TARGET_STRING && XVECLEN (operands[0], 0) == 5" 8923 "* 8924{ return rs6000_output_load_multiple (operands); }" 8925 [(set_attr "type" "load_ux") 8926 (set_attr "length" "32")]) 8927 8928(define_insn "*ldmsi4" 8929 [(match_parallel 0 "load_multiple_operation" 8930 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8931 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8932 (set (match_operand:SI 3 "gpc_reg_operand" "") 8933 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8934 (set (match_operand:SI 4 "gpc_reg_operand" "") 8935 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8936 (set (match_operand:SI 5 "gpc_reg_operand" "") 8937 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] 8938 "TARGET_STRING && XVECLEN (operands[0], 0) == 4" 8939 "* 8940{ return rs6000_output_load_multiple (operands); }" 8941 [(set_attr "type" "load_ux") 8942 (set_attr "length" "32")]) 8943 8944(define_insn "*ldmsi3" 8945 [(match_parallel 0 "load_multiple_operation" 8946 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8947 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8948 (set (match_operand:SI 3 "gpc_reg_operand" "") 8949 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8950 (set (match_operand:SI 4 "gpc_reg_operand" "") 8951 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] 8952 "TARGET_STRING && XVECLEN (operands[0], 0) == 3" 8953 "* 8954{ return rs6000_output_load_multiple (operands); }" 8955 [(set_attr "type" "load_ux") 8956 (set_attr "length" "32")]) 8957 8958(define_expand "store_multiple" 8959 [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 8960 (match_operand:SI 1 "" "")) 8961 (clobber (scratch:SI)) 8962 (use (match_operand:SI 2 "" ""))])] 8963 "TARGET_STRING && !TARGET_POWERPC64" 8964 " 8965{ 8966 int regno; 8967 int count; 8968 rtx to; 8969 rtx op0; 8970 int i; 8971 8972 /* Support only storing a constant number of fixed-point registers to 8973 memory and only bother with this if more than two; the machine 8974 doesn't support more than eight. */ 8975 if (GET_CODE (operands[2]) != CONST_INT 8976 || INTVAL (operands[2]) <= 2 8977 || INTVAL (operands[2]) > 8 8978 || GET_CODE (operands[0]) != MEM 8979 || GET_CODE (operands[1]) != REG 8980 || REGNO (operands[1]) >= 32) 8981 FAIL; 8982 8983 count = INTVAL (operands[2]); 8984 regno = REGNO (operands[1]); 8985 8986 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); 8987 to = force_reg (SImode, XEXP (operands[0], 0)); 8988 op0 = replace_equiv_address (operands[0], to); 8989 8990 XVECEXP (operands[3], 0, 0) 8991 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); 8992 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, 8993 gen_rtx_SCRATCH (SImode)); 8994 8995 for (i = 1; i < count; i++) 8996 XVECEXP (operands[3], 0, i + 1) 8997 = gen_rtx_SET (VOIDmode, 8998 adjust_address_nv (op0, SImode, i * 4), 8999 gen_rtx_REG (SImode, regno + i)); 9000}") 9001 9002(define_insn "*stmsi8" 9003 [(match_parallel 0 "store_multiple_operation" 9004 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9005 (match_operand:SI 2 "gpc_reg_operand" "r")) 9006 (clobber (match_scratch:SI 3 "=X")) 9007 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9008 (match_operand:SI 4 "gpc_reg_operand" "r")) 9009 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9010 (match_operand:SI 5 "gpc_reg_operand" "r")) 9011 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9012 (match_operand:SI 6 "gpc_reg_operand" "r")) 9013 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 9014 (match_operand:SI 7 "gpc_reg_operand" "r")) 9015 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 9016 (match_operand:SI 8 "gpc_reg_operand" "r")) 9017 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) 9018 (match_operand:SI 9 "gpc_reg_operand" "r")) 9019 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) 9020 (match_operand:SI 10 "gpc_reg_operand" "r"))])] 9021 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" 9022 "{stsi|stswi} %2,%1,%O0" 9023 [(set_attr "type" "store_ux")]) 9024 9025(define_insn "*stmsi7" 9026 [(match_parallel 0 "store_multiple_operation" 9027 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9028 (match_operand:SI 2 "gpc_reg_operand" "r")) 9029 (clobber (match_scratch:SI 3 "=X")) 9030 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9031 (match_operand:SI 4 "gpc_reg_operand" "r")) 9032 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9033 (match_operand:SI 5 "gpc_reg_operand" "r")) 9034 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9035 (match_operand:SI 6 "gpc_reg_operand" "r")) 9036 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 9037 (match_operand:SI 7 "gpc_reg_operand" "r")) 9038 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 9039 (match_operand:SI 8 "gpc_reg_operand" "r")) 9040 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) 9041 (match_operand:SI 9 "gpc_reg_operand" "r"))])] 9042 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" 9043 "{stsi|stswi} %2,%1,%O0" 9044 [(set_attr "type" "store_ux")]) 9045 9046(define_insn "*stmsi6" 9047 [(match_parallel 0 "store_multiple_operation" 9048 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9049 (match_operand:SI 2 "gpc_reg_operand" "r")) 9050 (clobber (match_scratch:SI 3 "=X")) 9051 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9052 (match_operand:SI 4 "gpc_reg_operand" "r")) 9053 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9054 (match_operand:SI 5 "gpc_reg_operand" "r")) 9055 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9056 (match_operand:SI 6 "gpc_reg_operand" "r")) 9057 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 9058 (match_operand:SI 7 "gpc_reg_operand" "r")) 9059 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 9060 (match_operand:SI 8 "gpc_reg_operand" "r"))])] 9061 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" 9062 "{stsi|stswi} %2,%1,%O0" 9063 [(set_attr "type" "store_ux")]) 9064 9065(define_insn "*stmsi5" 9066 [(match_parallel 0 "store_multiple_operation" 9067 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9068 (match_operand:SI 2 "gpc_reg_operand" "r")) 9069 (clobber (match_scratch:SI 3 "=X")) 9070 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9071 (match_operand:SI 4 "gpc_reg_operand" "r")) 9072 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9073 (match_operand:SI 5 "gpc_reg_operand" "r")) 9074 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9075 (match_operand:SI 6 "gpc_reg_operand" "r")) 9076 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 9077 (match_operand:SI 7 "gpc_reg_operand" "r"))])] 9078 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" 9079 "{stsi|stswi} %2,%1,%O0" 9080 [(set_attr "type" "store_ux")]) 9081 9082(define_insn "*stmsi4" 9083 [(match_parallel 0 "store_multiple_operation" 9084 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9085 (match_operand:SI 2 "gpc_reg_operand" "r")) 9086 (clobber (match_scratch:SI 3 "=X")) 9087 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9088 (match_operand:SI 4 "gpc_reg_operand" "r")) 9089 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9090 (match_operand:SI 5 "gpc_reg_operand" "r")) 9091 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9092 (match_operand:SI 6 "gpc_reg_operand" "r"))])] 9093 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" 9094 "{stsi|stswi} %2,%1,%O0" 9095 [(set_attr "type" "store_ux")]) 9096 9097(define_insn "*stmsi3" 9098 [(match_parallel 0 "store_multiple_operation" 9099 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9100 (match_operand:SI 2 "gpc_reg_operand" "r")) 9101 (clobber (match_scratch:SI 3 "=X")) 9102 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9103 (match_operand:SI 4 "gpc_reg_operand" "r")) 9104 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9105 (match_operand:SI 5 "gpc_reg_operand" "r"))])] 9106 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" 9107 "{stsi|stswi} %2,%1,%O0" 9108 [(set_attr "type" "store_ux")]) 9109 9110(define_insn "*stmsi8_power" 9111 [(match_parallel 0 "store_multiple_operation" 9112 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9113 (match_operand:SI 2 "gpc_reg_operand" "r")) 9114 (clobber (match_scratch:SI 3 "=q")) 9115 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9116 (match_operand:SI 4 "gpc_reg_operand" "r")) 9117 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9118 (match_operand:SI 5 "gpc_reg_operand" "r")) 9119 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9120 (match_operand:SI 6 "gpc_reg_operand" "r")) 9121 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 9122 (match_operand:SI 7 "gpc_reg_operand" "r")) 9123 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 9124 (match_operand:SI 8 "gpc_reg_operand" "r")) 9125 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) 9126 (match_operand:SI 9 "gpc_reg_operand" "r")) 9127 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) 9128 (match_operand:SI 10 "gpc_reg_operand" "r"))])] 9129 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9" 9130 "{stsi|stswi} %2,%1,%O0" 9131 [(set_attr "type" "store_ux")]) 9132 9133(define_insn "*stmsi7_power" 9134 [(match_parallel 0 "store_multiple_operation" 9135 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9136 (match_operand:SI 2 "gpc_reg_operand" "r")) 9137 (clobber (match_scratch:SI 3 "=q")) 9138 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9139 (match_operand:SI 4 "gpc_reg_operand" "r")) 9140 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9141 (match_operand:SI 5 "gpc_reg_operand" "r")) 9142 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9143 (match_operand:SI 6 "gpc_reg_operand" "r")) 9144 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 9145 (match_operand:SI 7 "gpc_reg_operand" "r")) 9146 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 9147 (match_operand:SI 8 "gpc_reg_operand" "r")) 9148 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) 9149 (match_operand:SI 9 "gpc_reg_operand" "r"))])] 9150 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8" 9151 "{stsi|stswi} %2,%1,%O0" 9152 [(set_attr "type" "store_ux")]) 9153 9154(define_insn "*stmsi6_power" 9155 [(match_parallel 0 "store_multiple_operation" 9156 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9157 (match_operand:SI 2 "gpc_reg_operand" "r")) 9158 (clobber (match_scratch:SI 3 "=q")) 9159 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9160 (match_operand:SI 4 "gpc_reg_operand" "r")) 9161 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9162 (match_operand:SI 5 "gpc_reg_operand" "r")) 9163 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9164 (match_operand:SI 6 "gpc_reg_operand" "r")) 9165 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 9166 (match_operand:SI 7 "gpc_reg_operand" "r")) 9167 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 9168 (match_operand:SI 8 "gpc_reg_operand" "r"))])] 9169 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7" 9170 "{stsi|stswi} %2,%1,%O0" 9171 [(set_attr "type" "store_ux")]) 9172 9173(define_insn "*stmsi5_power" 9174 [(match_parallel 0 "store_multiple_operation" 9175 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9176 (match_operand:SI 2 "gpc_reg_operand" "r")) 9177 (clobber (match_scratch:SI 3 "=q")) 9178 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9179 (match_operand:SI 4 "gpc_reg_operand" "r")) 9180 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9181 (match_operand:SI 5 "gpc_reg_operand" "r")) 9182 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9183 (match_operand:SI 6 "gpc_reg_operand" "r")) 9184 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 9185 (match_operand:SI 7 "gpc_reg_operand" "r"))])] 9186 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6" 9187 "{stsi|stswi} %2,%1,%O0" 9188 [(set_attr "type" "store_ux")]) 9189 9190(define_insn "*stmsi4_power" 9191 [(match_parallel 0 "store_multiple_operation" 9192 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9193 (match_operand:SI 2 "gpc_reg_operand" "r")) 9194 (clobber (match_scratch:SI 3 "=q")) 9195 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9196 (match_operand:SI 4 "gpc_reg_operand" "r")) 9197 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9198 (match_operand:SI 5 "gpc_reg_operand" "r")) 9199 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 9200 (match_operand:SI 6 "gpc_reg_operand" "r"))])] 9201 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5" 9202 "{stsi|stswi} %2,%1,%O0" 9203 [(set_attr "type" "store_ux")]) 9204 9205(define_insn "*stmsi3_power" 9206 [(match_parallel 0 "store_multiple_operation" 9207 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 9208 (match_operand:SI 2 "gpc_reg_operand" "r")) 9209 (clobber (match_scratch:SI 3 "=q")) 9210 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 9211 (match_operand:SI 4 "gpc_reg_operand" "r")) 9212 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 9213 (match_operand:SI 5 "gpc_reg_operand" "r"))])] 9214 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4" 9215 "{stsi|stswi} %2,%1,%O0" 9216 [(set_attr "type" "store_ux")]) 9217 9218(define_expand "setmemsi" 9219 [(parallel [(set (match_operand:BLK 0 "" "") 9220 (match_operand 2 "const_int_operand" "")) 9221 (use (match_operand:SI 1 "" "")) 9222 (use (match_operand:SI 3 "" ""))])] 9223 "" 9224 " 9225{ 9226 /* If value to set is not zero, use the library routine. */ 9227 if (operands[2] != const0_rtx) 9228 FAIL; 9229 9230 if (expand_block_clear (operands)) 9231 DONE; 9232 else 9233 FAIL; 9234}") 9235 9236;; String/block move insn. 9237;; Argument 0 is the destination 9238;; Argument 1 is the source 9239;; Argument 2 is the length 9240;; Argument 3 is the alignment 9241 9242(define_expand "movmemsi" 9243 [(parallel [(set (match_operand:BLK 0 "" "") 9244 (match_operand:BLK 1 "" "")) 9245 (use (match_operand:SI 2 "" "")) 9246 (use (match_operand:SI 3 "" ""))])] 9247 "" 9248 " 9249{ 9250 if (expand_block_move (operands)) 9251 DONE; 9252 else 9253 FAIL; 9254}") 9255 9256;; Move up to 32 bytes at a time. The fixed registers are needed because the 9257;; register allocator doesn't have a clue about allocating 8 word registers. 9258;; rD/rS = r5 is preferred, efficient form. 9259(define_expand "movmemsi_8reg" 9260 [(parallel [(set (match_operand 0 "" "") 9261 (match_operand 1 "" "")) 9262 (use (match_operand 2 "" "")) 9263 (use (match_operand 3 "" "")) 9264 (clobber (reg:SI 5)) 9265 (clobber (reg:SI 6)) 9266 (clobber (reg:SI 7)) 9267 (clobber (reg:SI 8)) 9268 (clobber (reg:SI 9)) 9269 (clobber (reg:SI 10)) 9270 (clobber (reg:SI 11)) 9271 (clobber (reg:SI 12)) 9272 (clobber (match_scratch:SI 4 ""))])] 9273 "TARGET_STRING" 9274 "") 9275 9276(define_insn "" 9277 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9278 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9279 (use (match_operand:SI 2 "immediate_operand" "i")) 9280 (use (match_operand:SI 3 "immediate_operand" "i")) 9281 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9282 (clobber (reg:SI 6)) 9283 (clobber (reg:SI 7)) 9284 (clobber (reg:SI 8)) 9285 (clobber (reg:SI 9)) 9286 (clobber (reg:SI 10)) 9287 (clobber (reg:SI 11)) 9288 (clobber (reg:SI 12)) 9289 (clobber (match_scratch:SI 5 "=q"))] 9290 "TARGET_STRING && TARGET_POWER 9291 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) 9292 || INTVAL (operands[2]) == 0) 9293 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 9294 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 9295 && REGNO (operands[4]) == 5" 9296 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9297 [(set_attr "type" "store_ux") 9298 (set_attr "length" "8")]) 9299 9300(define_insn "" 9301 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) 9302 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) 9303 (use (match_operand:SI 2 "immediate_operand" "i")) 9304 (use (match_operand:SI 3 "immediate_operand" "i")) 9305 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9306 (clobber (reg:SI 6)) 9307 (clobber (reg:SI 7)) 9308 (clobber (reg:SI 8)) 9309 (clobber (reg:SI 9)) 9310 (clobber (reg:SI 10)) 9311 (clobber (reg:SI 11)) 9312 (clobber (reg:SI 12)) 9313 (clobber (match_scratch:SI 5 "=X"))] 9314 "TARGET_STRING && ! TARGET_POWER 9315 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) 9316 || INTVAL (operands[2]) == 0) 9317 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 9318 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 9319 && REGNO (operands[4]) == 5" 9320 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9321 [(set_attr "type" "store_ux") 9322 (set_attr "length" "8")]) 9323 9324;; Move up to 24 bytes at a time. The fixed registers are needed because the 9325;; register allocator doesn't have a clue about allocating 6 word registers. 9326;; rD/rS = r5 is preferred, efficient form. 9327(define_expand "movmemsi_6reg" 9328 [(parallel [(set (match_operand 0 "" "") 9329 (match_operand 1 "" "")) 9330 (use (match_operand 2 "" "")) 9331 (use (match_operand 3 "" "")) 9332 (clobber (reg:SI 5)) 9333 (clobber (reg:SI 6)) 9334 (clobber (reg:SI 7)) 9335 (clobber (reg:SI 8)) 9336 (clobber (reg:SI 9)) 9337 (clobber (reg:SI 10)) 9338 (clobber (match_scratch:SI 4 ""))])] 9339 "TARGET_STRING" 9340 "") 9341 9342(define_insn "" 9343 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9344 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9345 (use (match_operand:SI 2 "immediate_operand" "i")) 9346 (use (match_operand:SI 3 "immediate_operand" "i")) 9347 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9348 (clobber (reg:SI 6)) 9349 (clobber (reg:SI 7)) 9350 (clobber (reg:SI 8)) 9351 (clobber (reg:SI 9)) 9352 (clobber (reg:SI 10)) 9353 (clobber (match_scratch:SI 5 "=q"))] 9354 "TARGET_STRING && TARGET_POWER 9355 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 9356 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) 9357 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) 9358 && REGNO (operands[4]) == 5" 9359 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9360 [(set_attr "type" "store_ux") 9361 (set_attr "length" "8")]) 9362 9363(define_insn "" 9364 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) 9365 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) 9366 (use (match_operand:SI 2 "immediate_operand" "i")) 9367 (use (match_operand:SI 3 "immediate_operand" "i")) 9368 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9369 (clobber (reg:SI 6)) 9370 (clobber (reg:SI 7)) 9371 (clobber (reg:SI 8)) 9372 (clobber (reg:SI 9)) 9373 (clobber (reg:SI 10)) 9374 (clobber (match_scratch:SI 5 "=X"))] 9375 "TARGET_STRING && ! TARGET_POWER 9376 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 9377 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) 9378 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) 9379 && REGNO (operands[4]) == 5" 9380 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9381 [(set_attr "type" "store_ux") 9382 (set_attr "length" "8")]) 9383 9384;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill 9385;; problems with TImode. 9386;; rD/rS = r5 is preferred, efficient form. 9387(define_expand "movmemsi_4reg" 9388 [(parallel [(set (match_operand 0 "" "") 9389 (match_operand 1 "" "")) 9390 (use (match_operand 2 "" "")) 9391 (use (match_operand 3 "" "")) 9392 (clobber (reg:SI 5)) 9393 (clobber (reg:SI 6)) 9394 (clobber (reg:SI 7)) 9395 (clobber (reg:SI 8)) 9396 (clobber (match_scratch:SI 4 ""))])] 9397 "TARGET_STRING" 9398 "") 9399 9400(define_insn "" 9401 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9402 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9403 (use (match_operand:SI 2 "immediate_operand" "i")) 9404 (use (match_operand:SI 3 "immediate_operand" "i")) 9405 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9406 (clobber (reg:SI 6)) 9407 (clobber (reg:SI 7)) 9408 (clobber (reg:SI 8)) 9409 (clobber (match_scratch:SI 5 "=q"))] 9410 "TARGET_STRING && TARGET_POWER 9411 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 9412 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) 9413 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) 9414 && REGNO (operands[4]) == 5" 9415 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9416 [(set_attr "type" "store_ux") 9417 (set_attr "length" "8")]) 9418 9419(define_insn "" 9420 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) 9421 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) 9422 (use (match_operand:SI 2 "immediate_operand" "i")) 9423 (use (match_operand:SI 3 "immediate_operand" "i")) 9424 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9425 (clobber (reg:SI 6)) 9426 (clobber (reg:SI 7)) 9427 (clobber (reg:SI 8)) 9428 (clobber (match_scratch:SI 5 "=X"))] 9429 "TARGET_STRING && ! TARGET_POWER 9430 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 9431 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) 9432 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) 9433 && REGNO (operands[4]) == 5" 9434 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9435 [(set_attr "type" "store_ux") 9436 (set_attr "length" "8")]) 9437 9438;; Move up to 8 bytes at a time. 9439(define_expand "movmemsi_2reg" 9440 [(parallel [(set (match_operand 0 "" "") 9441 (match_operand 1 "" "")) 9442 (use (match_operand 2 "" "")) 9443 (use (match_operand 3 "" "")) 9444 (clobber (match_scratch:DI 4 "")) 9445 (clobber (match_scratch:SI 5 ""))])] 9446 "TARGET_STRING && ! TARGET_POWERPC64" 9447 "") 9448 9449(define_insn "" 9450 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9451 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9452 (use (match_operand:SI 2 "immediate_operand" "i")) 9453 (use (match_operand:SI 3 "immediate_operand" "i")) 9454 (clobber (match_scratch:DI 4 "=&r")) 9455 (clobber (match_scratch:SI 5 "=q"))] 9456 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 9457 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" 9458 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9459 [(set_attr "type" "store_ux") 9460 (set_attr "length" "8")]) 9461 9462(define_insn "" 9463 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9464 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9465 (use (match_operand:SI 2 "immediate_operand" "i")) 9466 (use (match_operand:SI 3 "immediate_operand" "i")) 9467 (clobber (match_scratch:DI 4 "=&r")) 9468 (clobber (match_scratch:SI 5 "=X"))] 9469 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 9470 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" 9471 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9472 [(set_attr "type" "store_ux") 9473 (set_attr "length" "8")]) 9474 9475;; Move up to 4 bytes at a time. 9476(define_expand "movmemsi_1reg" 9477 [(parallel [(set (match_operand 0 "" "") 9478 (match_operand 1 "" "")) 9479 (use (match_operand 2 "" "")) 9480 (use (match_operand 3 "" "")) 9481 (clobber (match_scratch:SI 4 "")) 9482 (clobber (match_scratch:SI 5 ""))])] 9483 "TARGET_STRING" 9484 "") 9485 9486(define_insn "" 9487 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9488 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9489 (use (match_operand:SI 2 "immediate_operand" "i")) 9490 (use (match_operand:SI 3 "immediate_operand" "i")) 9491 (clobber (match_scratch:SI 4 "=&r")) 9492 (clobber (match_scratch:SI 5 "=q"))] 9493 "TARGET_STRING && TARGET_POWER 9494 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 9495 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9496 [(set_attr "type" "store_ux") 9497 (set_attr "length" "8")]) 9498 9499(define_insn "" 9500 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) 9501 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) 9502 (use (match_operand:SI 2 "immediate_operand" "i")) 9503 (use (match_operand:SI 3 "immediate_operand" "i")) 9504 (clobber (match_scratch:SI 4 "=&r")) 9505 (clobber (match_scratch:SI 5 "=X"))] 9506 "TARGET_STRING && ! TARGET_POWER 9507 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 9508 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9509 [(set_attr "type" "store_ux") 9510 (set_attr "length" "8")]) 9511 9512;; Define insns that do load or store with update. Some of these we can 9513;; get by using pre-decrement or pre-increment, but the hardware can also 9514;; do cases where the increment is not the size of the object. 9515;; 9516;; In all these cases, we use operands 0 and 1 for the register being 9517;; incremented because those are the operands that local-alloc will 9518;; tie and these are the pair most likely to be tieable (and the ones 9519;; that will benefit the most). 9520 9521(define_insn "*movdi_update1" 9522 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") 9523 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 9524 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) 9525 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 9526 (plus:DI (match_dup 1) (match_dup 2)))] 9527 "TARGET_POWERPC64 && TARGET_UPDATE" 9528 "@ 9529 ldux %3,%0,%2 9530 ldu %3,%2(%0)" 9531 [(set_attr "type" "load_ux,load_u")]) 9532 9533(define_insn "movdi_<mode>_update" 9534 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") 9535 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) 9536 (match_operand:DI 3 "gpc_reg_operand" "r,r")) 9537 (set (match_operand:P 0 "gpc_reg_operand" "=b,b") 9538 (plus:P (match_dup 1) (match_dup 2)))] 9539 "TARGET_POWERPC64 && TARGET_UPDATE" 9540 "@ 9541 stdux %3,%0,%2 9542 stdu %3,%2(%0)" 9543 [(set_attr "type" "store_ux,store_u")]) 9544 9545(define_insn "*movsi_update1" 9546 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9547 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9548 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9549 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9550 (plus:SI (match_dup 1) (match_dup 2)))] 9551 "TARGET_UPDATE" 9552 "@ 9553 {lux|lwzux} %3,%0,%2 9554 {lu|lwzu} %3,%2(%0)" 9555 [(set_attr "type" "load_ux,load_u")]) 9556 9557(define_insn "*movsi_update2" 9558 [(set (match_operand:DI 3 "gpc_reg_operand" "=r") 9559 (sign_extend:DI 9560 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") 9561 (match_operand:DI 2 "gpc_reg_operand" "r"))))) 9562 (set (match_operand:DI 0 "gpc_reg_operand" "=b") 9563 (plus:DI (match_dup 1) (match_dup 2)))] 9564 "TARGET_POWERPC64" 9565 "lwaux %3,%0,%2" 9566 [(set_attr "type" "load_ext_ux")]) 9567 9568(define_insn "movsi_update" 9569 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9570 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9571 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 9572 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9573 (plus:SI (match_dup 1) (match_dup 2)))] 9574 "TARGET_UPDATE" 9575 "@ 9576 {stux|stwux} %3,%0,%2 9577 {stu|stwu} %3,%2(%0)" 9578 [(set_attr "type" "store_ux,store_u")]) 9579 9580(define_insn "*movhi_update1" 9581 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") 9582 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9583 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9584 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9585 (plus:SI (match_dup 1) (match_dup 2)))] 9586 "TARGET_UPDATE" 9587 "@ 9588 lhzux %3,%0,%2 9589 lhzu %3,%2(%0)" 9590 [(set_attr "type" "load_ux,load_u")]) 9591 9592(define_insn "*movhi_update2" 9593 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9594 (zero_extend:SI 9595 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9596 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 9597 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9598 (plus:SI (match_dup 1) (match_dup 2)))] 9599 "TARGET_UPDATE" 9600 "@ 9601 lhzux %3,%0,%2 9602 lhzu %3,%2(%0)" 9603 [(set_attr "type" "load_ux,load_u")]) 9604 9605(define_insn "*movhi_update3" 9606 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9607 (sign_extend:SI 9608 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9609 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 9610 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9611 (plus:SI (match_dup 1) (match_dup 2)))] 9612 "TARGET_UPDATE" 9613 "@ 9614 lhaux %3,%0,%2 9615 lhau %3,%2(%0)" 9616 [(set_attr "type" "load_ext_ux,load_ext_u")]) 9617 9618(define_insn "*movhi_update4" 9619 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9620 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9621 (match_operand:HI 3 "gpc_reg_operand" "r,r")) 9622 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9623 (plus:SI (match_dup 1) (match_dup 2)))] 9624 "TARGET_UPDATE" 9625 "@ 9626 sthux %3,%0,%2 9627 sthu %3,%2(%0)" 9628 [(set_attr "type" "store_ux,store_u")]) 9629 9630(define_insn "*movqi_update1" 9631 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") 9632 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9633 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9634 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9635 (plus:SI (match_dup 1) (match_dup 2)))] 9636 "TARGET_UPDATE" 9637 "@ 9638 lbzux %3,%0,%2 9639 lbzu %3,%2(%0)" 9640 [(set_attr "type" "load_ux,load_u")]) 9641 9642(define_insn "*movqi_update2" 9643 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9644 (zero_extend:SI 9645 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9646 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 9647 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9648 (plus:SI (match_dup 1) (match_dup 2)))] 9649 "TARGET_UPDATE" 9650 "@ 9651 lbzux %3,%0,%2 9652 lbzu %3,%2(%0)" 9653 [(set_attr "type" "load_ux,load_u")]) 9654 9655(define_insn "*movqi_update3" 9656 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9657 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9658 (match_operand:QI 3 "gpc_reg_operand" "r,r")) 9659 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9660 (plus:SI (match_dup 1) (match_dup 2)))] 9661 "TARGET_UPDATE" 9662 "@ 9663 stbux %3,%0,%2 9664 stbu %3,%2(%0)" 9665 [(set_attr "type" "store_ux,store_u")]) 9666 9667(define_insn "*movsf_update1" 9668 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") 9669 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9670 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9671 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9672 (plus:SI (match_dup 1) (match_dup 2)))] 9673 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" 9674 "@ 9675 lfsux %3,%0,%2 9676 lfsu %3,%2(%0)" 9677 [(set_attr "type" "fpload_ux,fpload_u")]) 9678 9679(define_insn "*movsf_update2" 9680 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9681 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9682 (match_operand:SF 3 "gpc_reg_operand" "f,f")) 9683 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9684 (plus:SI (match_dup 1) (match_dup 2)))] 9685 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" 9686 "@ 9687 stfsux %3,%0,%2 9688 stfsu %3,%2(%0)" 9689 [(set_attr "type" "fpstore_ux,fpstore_u")]) 9690 9691(define_insn "*movsf_update3" 9692 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") 9693 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9694 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9695 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9696 (plus:SI (match_dup 1) (match_dup 2)))] 9697 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" 9698 "@ 9699 {lux|lwzux} %3,%0,%2 9700 {lu|lwzu} %3,%2(%0)" 9701 [(set_attr "type" "load_ux,load_u")]) 9702 9703(define_insn "*movsf_update4" 9704 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9705 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9706 (match_operand:SF 3 "gpc_reg_operand" "r,r")) 9707 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9708 (plus:SI (match_dup 1) (match_dup 2)))] 9709 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" 9710 "@ 9711 {stux|stwux} %3,%0,%2 9712 {stu|stwu} %3,%2(%0)" 9713 [(set_attr "type" "store_ux,store_u")]) 9714 9715(define_insn "*movdf_update1" 9716 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") 9717 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9718 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9719 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9720 (plus:SI (match_dup 1) (match_dup 2)))] 9721 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" 9722 "@ 9723 lfdux %3,%0,%2 9724 lfdu %3,%2(%0)" 9725 [(set_attr "type" "fpload_ux,fpload_u")]) 9726 9727(define_insn "*movdf_update2" 9728 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9729 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9730 (match_operand:DF 3 "gpc_reg_operand" "f,f")) 9731 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9732 (plus:SI (match_dup 1) (match_dup 2)))] 9733 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" 9734 "@ 9735 stfdux %3,%0,%2 9736 stfdu %3,%2(%0)" 9737 [(set_attr "type" "fpstore_ux,fpstore_u")]) 9738 9739;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. 9740 9741(define_insn "*lfq_power2" 9742 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f") 9743 (match_operand:V2DF 1 "memory_operand" ""))] 9744 "TARGET_POWER2 9745 && TARGET_HARD_FLOAT && TARGET_FPRS" 9746 "lfq%U1%X1 %0,%1") 9747 9748(define_peephole2 9749 [(set (match_operand:DF 0 "gpc_reg_operand" "") 9750 (match_operand:DF 1 "memory_operand" "")) 9751 (set (match_operand:DF 2 "gpc_reg_operand" "") 9752 (match_operand:DF 3 "memory_operand" ""))] 9753 "TARGET_POWER2 9754 && TARGET_HARD_FLOAT && TARGET_FPRS 9755 && registers_ok_for_quad_peep (operands[0], operands[2]) 9756 && mems_ok_for_quad_peep (operands[1], operands[3])" 9757 [(set (match_dup 0) 9758 (match_dup 1))] 9759 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0); 9760 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));") 9761 9762(define_insn "*stfq_power2" 9763 [(set (match_operand:V2DF 0 "memory_operand" "") 9764 (match_operand:V2DF 1 "gpc_reg_operand" "f"))] 9765 "TARGET_POWER2 9766 && TARGET_HARD_FLOAT && TARGET_FPRS" 9767 "stfq%U0%X0 %1,%0") 9768 9769 9770(define_peephole2 9771 [(set (match_operand:DF 0 "memory_operand" "") 9772 (match_operand:DF 1 "gpc_reg_operand" "")) 9773 (set (match_operand:DF 2 "memory_operand" "") 9774 (match_operand:DF 3 "gpc_reg_operand" ""))] 9775 "TARGET_POWER2 9776 && TARGET_HARD_FLOAT && TARGET_FPRS 9777 && registers_ok_for_quad_peep (operands[1], operands[3]) 9778 && mems_ok_for_quad_peep (operands[0], operands[2])" 9779 [(set (match_dup 0) 9780 (match_dup 1))] 9781 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0); 9782 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));") 9783 9784;; After inserting conditional returns we can sometimes have 9785;; unnecessary register moves. Unfortunately we cannot have a 9786;; modeless peephole here, because some single SImode sets have early 9787;; clobber outputs. Although those sets expand to multi-ppc-insn 9788;; sequences, using get_attr_length here will smash the operands 9789;; array. Neither is there an early_cobbler_p predicate. 9790;; Disallow subregs for E500 so we don't munge frob_di_df_2. 9791(define_peephole2 9792 [(set (match_operand:DF 0 "gpc_reg_operand" "") 9793 (match_operand:DF 1 "any_operand" "")) 9794 (set (match_operand:DF 2 "gpc_reg_operand" "") 9795 (match_dup 0))] 9796 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG) 9797 && peep2_reg_dead_p (2, operands[0])" 9798 [(set (match_dup 2) (match_dup 1))]) 9799 9800(define_peephole2 9801 [(set (match_operand:SF 0 "gpc_reg_operand" "") 9802 (match_operand:SF 1 "any_operand" "")) 9803 (set (match_operand:SF 2 "gpc_reg_operand" "") 9804 (match_dup 0))] 9805 "peep2_reg_dead_p (2, operands[0])" 9806 [(set (match_dup 2) (match_dup 1))]) 9807 9808 9809;; TLS support. 9810 9811;; "b" output constraint here and on tls_ld to support tls linker optimization. 9812(define_insn "tls_gd_32" 9813 [(set (match_operand:SI 0 "gpc_reg_operand" "=b") 9814 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9815 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9816 UNSPEC_TLSGD))] 9817 "HAVE_AS_TLS && !TARGET_64BIT" 9818 "addi %0,%1,%2@got@tlsgd") 9819 9820(define_insn "tls_gd_64" 9821 [(set (match_operand:DI 0 "gpc_reg_operand" "=b") 9822 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9823 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9824 UNSPEC_TLSGD))] 9825 "HAVE_AS_TLS && TARGET_64BIT" 9826 "addi %0,%1,%2@got@tlsgd") 9827 9828(define_insn "tls_ld_32" 9829 [(set (match_operand:SI 0 "gpc_reg_operand" "=b") 9830 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")] 9831 UNSPEC_TLSLD))] 9832 "HAVE_AS_TLS && !TARGET_64BIT" 9833 "addi %0,%1,%&@got@tlsld") 9834 9835(define_insn "tls_ld_64" 9836 [(set (match_operand:DI 0 "gpc_reg_operand" "=b") 9837 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")] 9838 UNSPEC_TLSLD))] 9839 "HAVE_AS_TLS && TARGET_64BIT" 9840 "addi %0,%1,%&@got@tlsld") 9841 9842(define_insn "tls_dtprel_32" 9843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9844 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9845 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9846 UNSPEC_TLSDTPREL))] 9847 "HAVE_AS_TLS && !TARGET_64BIT" 9848 "addi %0,%1,%2@dtprel") 9849 9850(define_insn "tls_dtprel_64" 9851 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9852 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9853 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9854 UNSPEC_TLSDTPREL))] 9855 "HAVE_AS_TLS && TARGET_64BIT" 9856 "addi %0,%1,%2@dtprel") 9857 9858(define_insn "tls_dtprel_ha_32" 9859 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9860 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9861 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9862 UNSPEC_TLSDTPRELHA))] 9863 "HAVE_AS_TLS && !TARGET_64BIT" 9864 "addis %0,%1,%2@dtprel@ha") 9865 9866(define_insn "tls_dtprel_ha_64" 9867 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9868 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9869 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9870 UNSPEC_TLSDTPRELHA))] 9871 "HAVE_AS_TLS && TARGET_64BIT" 9872 "addis %0,%1,%2@dtprel@ha") 9873 9874(define_insn "tls_dtprel_lo_32" 9875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9876 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9877 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9878 UNSPEC_TLSDTPRELLO))] 9879 "HAVE_AS_TLS && !TARGET_64BIT" 9880 "addi %0,%1,%2@dtprel@l") 9881 9882(define_insn "tls_dtprel_lo_64" 9883 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9884 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9885 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9886 UNSPEC_TLSDTPRELLO))] 9887 "HAVE_AS_TLS && TARGET_64BIT" 9888 "addi %0,%1,%2@dtprel@l") 9889 9890(define_insn "tls_got_dtprel_32" 9891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9892 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9893 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9894 UNSPEC_TLSGOTDTPREL))] 9895 "HAVE_AS_TLS && !TARGET_64BIT" 9896 "lwz %0,%2@got@dtprel(%1)") 9897 9898(define_insn "tls_got_dtprel_64" 9899 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9900 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9901 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9902 UNSPEC_TLSGOTDTPREL))] 9903 "HAVE_AS_TLS && TARGET_64BIT" 9904 "ld %0,%2@got@dtprel(%1)") 9905 9906(define_insn "tls_tprel_32" 9907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9908 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9909 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9910 UNSPEC_TLSTPREL))] 9911 "HAVE_AS_TLS && !TARGET_64BIT" 9912 "addi %0,%1,%2@tprel") 9913 9914(define_insn "tls_tprel_64" 9915 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9916 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9917 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9918 UNSPEC_TLSTPREL))] 9919 "HAVE_AS_TLS && TARGET_64BIT" 9920 "addi %0,%1,%2@tprel") 9921 9922(define_insn "tls_tprel_ha_32" 9923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9924 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9925 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9926 UNSPEC_TLSTPRELHA))] 9927 "HAVE_AS_TLS && !TARGET_64BIT" 9928 "addis %0,%1,%2@tprel@ha") 9929 9930(define_insn "tls_tprel_ha_64" 9931 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9932 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9933 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9934 UNSPEC_TLSTPRELHA))] 9935 "HAVE_AS_TLS && TARGET_64BIT" 9936 "addis %0,%1,%2@tprel@ha") 9937 9938(define_insn "tls_tprel_lo_32" 9939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9940 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9941 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9942 UNSPEC_TLSTPRELLO))] 9943 "HAVE_AS_TLS && !TARGET_64BIT" 9944 "addi %0,%1,%2@tprel@l") 9945 9946(define_insn "tls_tprel_lo_64" 9947 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9948 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9949 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9950 UNSPEC_TLSTPRELLO))] 9951 "HAVE_AS_TLS && TARGET_64BIT" 9952 "addi %0,%1,%2@tprel@l") 9953 9954;; "b" output constraint here and on tls_tls input to support linker tls 9955;; optimization. The linker may edit the instructions emitted by a 9956;; tls_got_tprel/tls_tls pair to addis,addi. 9957(define_insn "tls_got_tprel_32" 9958 [(set (match_operand:SI 0 "gpc_reg_operand" "=b") 9959 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9960 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9961 UNSPEC_TLSGOTTPREL))] 9962 "HAVE_AS_TLS && !TARGET_64BIT" 9963 "lwz %0,%2@got@tprel(%1)") 9964 9965(define_insn "tls_got_tprel_64" 9966 [(set (match_operand:DI 0 "gpc_reg_operand" "=b") 9967 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9968 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9969 UNSPEC_TLSGOTTPREL))] 9970 "HAVE_AS_TLS && TARGET_64BIT" 9971 "ld %0,%2@got@tprel(%1)") 9972 9973(define_insn "tls_tls_32" 9974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9975 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") 9976 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9977 UNSPEC_TLSTLS))] 9978 "HAVE_AS_TLS && !TARGET_64BIT" 9979 "add %0,%1,%2@tls") 9980 9981(define_insn "tls_tls_64" 9982 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9983 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") 9984 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9985 UNSPEC_TLSTLS))] 9986 "HAVE_AS_TLS && TARGET_64BIT" 9987 "add %0,%1,%2@tls") 9988 9989;; Next come insns related to the calling sequence. 9990;; 9991;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). 9992;; We move the back-chain and decrement the stack pointer. 9993 9994(define_expand "allocate_stack" 9995 [(set (match_operand 0 "gpc_reg_operand" "=r") 9996 (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) 9997 (set (reg 1) 9998 (minus (reg 1) (match_dup 1)))] 9999 "" 10000 " 10001{ rtx chain = gen_reg_rtx (Pmode); 10002 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); 10003 rtx neg_op0; 10004 10005 emit_move_insn (chain, stack_bot); 10006 10007 /* Check stack bounds if necessary. */ 10008 if (current_function_limit_stack) 10009 { 10010 rtx available; 10011 available = expand_binop (Pmode, sub_optab, 10012 stack_pointer_rtx, stack_limit_rtx, 10013 NULL_RTX, 1, OPTAB_WIDEN); 10014 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); 10015 } 10016 10017 if (GET_CODE (operands[1]) != CONST_INT 10018 || INTVAL (operands[1]) < -32767 10019 || INTVAL (operands[1]) > 32768) 10020 { 10021 neg_op0 = gen_reg_rtx (Pmode); 10022 if (TARGET_32BIT) 10023 emit_insn (gen_negsi2 (neg_op0, operands[1])); 10024 else 10025 emit_insn (gen_negdi2 (neg_op0, operands[1])); 10026 } 10027 else 10028 neg_op0 = GEN_INT (- INTVAL (operands[1])); 10029 10030 if (TARGET_UPDATE) 10031 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update)) 10032 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); 10033 10034 else 10035 { 10036 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) 10037 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); 10038 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); 10039 } 10040 10041 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 10042 DONE; 10043}") 10044 10045;; These patterns say how to save and restore the stack pointer. We need not 10046;; save the stack pointer at function level since we are careful to 10047;; preserve the backchain. At block level, we have to restore the backchain 10048;; when we restore the stack pointer. 10049;; 10050;; For nonlocal gotos, we must save both the stack pointer and its 10051;; backchain and restore both. Note that in the nonlocal case, the 10052;; save area is a memory location. 10053 10054(define_expand "save_stack_function" 10055 [(match_operand 0 "any_operand" "") 10056 (match_operand 1 "any_operand" "")] 10057 "" 10058 "DONE;") 10059 10060(define_expand "restore_stack_function" 10061 [(match_operand 0 "any_operand" "") 10062 (match_operand 1 "any_operand" "")] 10063 "" 10064 "DONE;") 10065 10066;; Adjust stack pointer (op0) to a new value (op1). 10067;; First copy old stack backchain to new location, and ensure that the 10068;; scheduler won't reorder the sp assignment before the backchain write. 10069(define_expand "restore_stack_block" 10070 [(set (match_dup 2) (match_dup 3)) 10071 (set (match_dup 4) (match_dup 2)) 10072 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE)) 10073 (set (match_operand 0 "register_operand" "") 10074 (match_operand 1 "register_operand" ""))] 10075 "" 10076 " 10077{ 10078 operands[2] = gen_reg_rtx (Pmode); 10079 operands[3] = gen_frame_mem (Pmode, operands[0]); 10080 operands[4] = gen_frame_mem (Pmode, operands[1]); 10081 operands[5] = gen_frame_mem (BLKmode, operands[0]); 10082}") 10083 10084(define_expand "save_stack_nonlocal" 10085 [(set (match_dup 3) (match_dup 4)) 10086 (set (match_operand 0 "memory_operand" "") (match_dup 3)) 10087 (set (match_dup 2) (match_operand 1 "register_operand" ""))] 10088 "" 10089 " 10090{ 10091 int units_per_word = (TARGET_32BIT) ? 4 : 8; 10092 10093 /* Copy the backchain to the first word, sp to the second. */ 10094 operands[0] = adjust_address_nv (operands[0], Pmode, 0); 10095 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word); 10096 operands[3] = gen_reg_rtx (Pmode); 10097 operands[4] = gen_frame_mem (Pmode, operands[1]); 10098}") 10099 10100(define_expand "restore_stack_nonlocal" 10101 [(set (match_dup 2) (match_operand 1 "memory_operand" "")) 10102 (set (match_dup 3) (match_dup 4)) 10103 (set (match_dup 5) (match_dup 2)) 10104 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE)) 10105 (set (match_operand 0 "register_operand" "") (match_dup 3))] 10106 "" 10107 " 10108{ 10109 int units_per_word = (TARGET_32BIT) ? 4 : 8; 10110 10111 /* Restore the backchain from the first word, sp from the second. */ 10112 operands[2] = gen_reg_rtx (Pmode); 10113 operands[3] = gen_reg_rtx (Pmode); 10114 operands[1] = adjust_address_nv (operands[1], Pmode, 0); 10115 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word); 10116 operands[5] = gen_frame_mem (Pmode, operands[3]); 10117 operands[6] = gen_frame_mem (BLKmode, operands[0]); 10118}") 10119 10120;; TOC register handling. 10121 10122;; Code to initialize the TOC register... 10123 10124(define_insn "load_toc_aix_si" 10125 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 10126 (unspec:SI [(const_int 0)] UNSPEC_TOC)) 10127 (use (reg:SI 2))])] 10128 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" 10129 "* 10130{ 10131 char buf[30]; 10132 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); 10133 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 10134 operands[2] = gen_rtx_REG (Pmode, 2); 10135 return \"{l|lwz} %0,%1(%2)\"; 10136}" 10137 [(set_attr "type" "load")]) 10138 10139(define_insn "load_toc_aix_di" 10140 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 10141 (unspec:DI [(const_int 0)] UNSPEC_TOC)) 10142 (use (reg:DI 2))])] 10143 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" 10144 "* 10145{ 10146 char buf[30]; 10147#ifdef TARGET_RELOCATABLE 10148 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 10149 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); 10150#else 10151 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); 10152#endif 10153 if (TARGET_ELF) 10154 strcat (buf, \"@toc\"); 10155 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 10156 operands[2] = gen_rtx_REG (Pmode, 2); 10157 return \"ld %0,%1(%2)\"; 10158}" 10159 [(set_attr "type" "load")]) 10160 10161(define_insn "load_toc_v4_pic_si" 10162 [(set (match_operand:SI 0 "register_operand" "=l") 10163 (unspec:SI [(const_int 0)] UNSPEC_TOC))] 10164 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" 10165 "bl _GLOBAL_OFFSET_TABLE_@local-4" 10166 [(set_attr "type" "branch") 10167 (set_attr "length" "4")]) 10168 10169(define_insn "load_toc_v4_PIC_1" 10170 [(set (match_operand:SI 0 "register_operand" "=l") 10171 (match_operand:SI 1 "immediate_operand" "s")) 10172 (use (unspec [(match_dup 1)] UNSPEC_TOC))] 10173 "TARGET_ELF && DEFAULT_ABI != ABI_AIX 10174 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" 10175 "bcl 20,31,%1\\n%1:" 10176 [(set_attr "type" "branch") 10177 (set_attr "length" "4")]) 10178 10179(define_insn "load_toc_v4_PIC_1b" 10180 [(set (match_operand:SI 0 "register_operand" "=l") 10181 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 10182 UNSPEC_TOCPTR))] 10183 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" 10184 "bcl 20,31,$+8\\n\\t.long %1-$" 10185 [(set_attr "type" "branch") 10186 (set_attr "length" "8")]) 10187 10188(define_insn "load_toc_v4_PIC_2" 10189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 10190 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 10191 (minus:SI (match_operand:SI 2 "immediate_operand" "s") 10192 (match_operand:SI 3 "immediate_operand" "s")))))] 10193 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" 10194 "{l|lwz} %0,%2-%3(%1)" 10195 [(set_attr "type" "load")]) 10196 10197(define_insn "load_toc_v4_PIC_3b" 10198 [(set (match_operand:SI 0 "gpc_reg_operand" "=b") 10199 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 10200 (high:SI 10201 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") 10202 (match_operand:SI 3 "symbol_ref_operand" "s")))))] 10203 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" 10204 "{cau|addis} %0,%1,%2-%3@ha") 10205 10206(define_insn "load_toc_v4_PIC_3c" 10207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 10208 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") 10209 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") 10210 (match_operand:SI 3 "symbol_ref_operand" "s"))))] 10211 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" 10212 "{cal|addi} %0,%1,%2-%3@l") 10213 10214;; If the TOC is shared over a translation unit, as happens with all 10215;; the kinds of PIC that we support, we need to restore the TOC 10216;; pointer only when jumping over units of translation. 10217;; On Darwin, we need to reload the picbase. 10218 10219(define_expand "builtin_setjmp_receiver" 10220 [(use (label_ref (match_operand 0 "" "")))] 10221 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) 10222 || (TARGET_TOC && TARGET_MINIMAL_TOC) 10223 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" 10224 " 10225{ 10226#if TARGET_MACHO 10227 if (DEFAULT_ABI == ABI_DARWIN) 10228 { 10229 const char *picbase = machopic_function_base_name (); 10230 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); 10231 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); 10232 rtx tmplabrtx; 10233 char tmplab[20]; 10234 10235 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", 10236 CODE_LABEL_NUMBER (operands[0])); 10237 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); 10238 10239 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); 10240 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); 10241 } 10242 else 10243#endif 10244 rs6000_emit_load_toc_table (FALSE); 10245 DONE; 10246}") 10247 10248;; Elf specific ways of loading addresses for non-PIC code. 10249;; The output of this could be r0, but we make a very strong 10250;; preference for a base register because it will usually 10251;; be needed there. 10252(define_insn "elf_high" 10253 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") 10254 (high:SI (match_operand 1 "" "")))] 10255 "TARGET_ELF && ! TARGET_64BIT" 10256 "{liu|lis} %0,%1@ha") 10257 10258(define_insn "elf_low" 10259 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 10260 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") 10261 (match_operand 2 "" "")))] 10262 "TARGET_ELF && ! TARGET_64BIT" 10263 "@ 10264 {cal|la} %0,%2@l(%1) 10265 {ai|addic} %0,%1,%K2") 10266 10267;; A function pointer under AIX is a pointer to a data area whose first word 10268;; contains the actual address of the function, whose second word contains a 10269;; pointer to its TOC, and whose third word contains a value to place in the 10270;; static chain register (r11). Note that if we load the static chain, our 10271;; "trampoline" need not have any executable code. 10272 10273(define_expand "call_indirect_aix32" 10274 [(set (match_dup 2) 10275 (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) 10276 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) 10277 (reg:SI 2)) 10278 (set (reg:SI 2) 10279 (mem:SI (plus:SI (match_dup 0) 10280 (const_int 4)))) 10281 (set (reg:SI 11) 10282 (mem:SI (plus:SI (match_dup 0) 10283 (const_int 8)))) 10284 (parallel [(call (mem:SI (match_dup 2)) 10285 (match_operand 1 "" "")) 10286 (use (reg:SI 2)) 10287 (use (reg:SI 11)) 10288 (set (reg:SI 2) 10289 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 10290 (clobber (scratch:SI))])] 10291 "TARGET_32BIT" 10292 " 10293{ operands[2] = gen_reg_rtx (SImode); }") 10294 10295(define_expand "call_indirect_aix64" 10296 [(set (match_dup 2) 10297 (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) 10298 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) 10299 (reg:DI 2)) 10300 (set (reg:DI 2) 10301 (mem:DI (plus:DI (match_dup 0) 10302 (const_int 8)))) 10303 (set (reg:DI 11) 10304 (mem:DI (plus:DI (match_dup 0) 10305 (const_int 16)))) 10306 (parallel [(call (mem:SI (match_dup 2)) 10307 (match_operand 1 "" "")) 10308 (use (reg:DI 2)) 10309 (use (reg:DI 11)) 10310 (set (reg:DI 2) 10311 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10312 (clobber (scratch:SI))])] 10313 "TARGET_64BIT" 10314 " 10315{ operands[2] = gen_reg_rtx (DImode); }") 10316 10317(define_expand "call_value_indirect_aix32" 10318 [(set (match_dup 3) 10319 (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 10320 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) 10321 (reg:SI 2)) 10322 (set (reg:SI 2) 10323 (mem:SI (plus:SI (match_dup 1) 10324 (const_int 4)))) 10325 (set (reg:SI 11) 10326 (mem:SI (plus:SI (match_dup 1) 10327 (const_int 8)))) 10328 (parallel [(set (match_operand 0 "" "") 10329 (call (mem:SI (match_dup 3)) 10330 (match_operand 2 "" ""))) 10331 (use (reg:SI 2)) 10332 (use (reg:SI 11)) 10333 (set (reg:SI 2) 10334 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 10335 (clobber (scratch:SI))])] 10336 "TARGET_32BIT" 10337 " 10338{ operands[3] = gen_reg_rtx (SImode); }") 10339 10340(define_expand "call_value_indirect_aix64" 10341 [(set (match_dup 3) 10342 (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 10343 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) 10344 (reg:DI 2)) 10345 (set (reg:DI 2) 10346 (mem:DI (plus:DI (match_dup 1) 10347 (const_int 8)))) 10348 (set (reg:DI 11) 10349 (mem:DI (plus:DI (match_dup 1) 10350 (const_int 16)))) 10351 (parallel [(set (match_operand 0 "" "") 10352 (call (mem:SI (match_dup 3)) 10353 (match_operand 2 "" ""))) 10354 (use (reg:DI 2)) 10355 (use (reg:DI 11)) 10356 (set (reg:DI 2) 10357 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10358 (clobber (scratch:SI))])] 10359 "TARGET_64BIT" 10360 " 10361{ operands[3] = gen_reg_rtx (DImode); }") 10362 10363;; Now the definitions for the call and call_value insns 10364(define_expand "call" 10365 [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) 10366 (match_operand 1 "" "")) 10367 (use (match_operand 2 "" "")) 10368 (clobber (scratch:SI))])] 10369 "" 10370 " 10371{ 10372#if TARGET_MACHO 10373 if (MACHOPIC_INDIRECT) 10374 operands[0] = machopic_indirect_call_target (operands[0]); 10375#endif 10376 10377 gcc_assert (GET_CODE (operands[0]) == MEM); 10378 gcc_assert (GET_CODE (operands[1]) == CONST_INT); 10379 10380 operands[0] = XEXP (operands[0], 0); 10381 10382 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT 10383 && flag_pic 10384 && GET_CODE (operands[0]) == SYMBOL_REF 10385 && !SYMBOL_REF_LOCAL_P (operands[0])) 10386 { 10387 rtx call; 10388 rtvec tmp; 10389 10390 tmp = gen_rtvec (3, 10391 gen_rtx_CALL (VOIDmode, 10392 gen_rtx_MEM (SImode, operands[0]), 10393 operands[1]), 10394 gen_rtx_USE (VOIDmode, operands[2]), 10395 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); 10396 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp)); 10397 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx); 10398 DONE; 10399 } 10400 10401 if (GET_CODE (operands[0]) != SYMBOL_REF 10402 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) 10403 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) 10404 { 10405 if (INTVAL (operands[2]) & CALL_LONG) 10406 operands[0] = rs6000_longcall_ref (operands[0]); 10407 10408 switch (DEFAULT_ABI) 10409 { 10410 case ABI_V4: 10411 case ABI_DARWIN: 10412 operands[0] = force_reg (Pmode, operands[0]); 10413 break; 10414 10415 case ABI_AIX: 10416 /* AIX function pointers are really pointers to a three word 10417 area. */ 10418 emit_call_insn (TARGET_32BIT 10419 ? gen_call_indirect_aix32 (force_reg (SImode, 10420 operands[0]), 10421 operands[1]) 10422 : gen_call_indirect_aix64 (force_reg (DImode, 10423 operands[0]), 10424 operands[1])); 10425 DONE; 10426 10427 default: 10428 gcc_unreachable (); 10429 } 10430 } 10431}") 10432 10433(define_expand "call_value" 10434 [(parallel [(set (match_operand 0 "" "") 10435 (call (mem:SI (match_operand 1 "address_operand" "")) 10436 (match_operand 2 "" ""))) 10437 (use (match_operand 3 "" "")) 10438 (clobber (scratch:SI))])] 10439 "" 10440 " 10441{ 10442#if TARGET_MACHO 10443 if (MACHOPIC_INDIRECT) 10444 operands[1] = machopic_indirect_call_target (operands[1]); 10445#endif 10446 10447 gcc_assert (GET_CODE (operands[1]) == MEM); 10448 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 10449 10450 operands[1] = XEXP (operands[1], 0); 10451 10452 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT 10453 && flag_pic 10454 && GET_CODE (operands[1]) == SYMBOL_REF 10455 && !SYMBOL_REF_LOCAL_P (operands[1])) 10456 { 10457 rtx call; 10458 rtvec tmp; 10459 10460 tmp = gen_rtvec (3, 10461 gen_rtx_SET (VOIDmode, 10462 operands[0], 10463 gen_rtx_CALL (VOIDmode, 10464 gen_rtx_MEM (SImode, 10465 operands[1]), 10466 operands[2])), 10467 gen_rtx_USE (VOIDmode, operands[3]), 10468 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); 10469 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp)); 10470 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx); 10471 DONE; 10472 } 10473 10474 if (GET_CODE (operands[1]) != SYMBOL_REF 10475 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) 10476 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) 10477 { 10478 if (INTVAL (operands[3]) & CALL_LONG) 10479 operands[1] = rs6000_longcall_ref (operands[1]); 10480 10481 switch (DEFAULT_ABI) 10482 { 10483 case ABI_V4: 10484 case ABI_DARWIN: 10485 operands[1] = force_reg (Pmode, operands[1]); 10486 break; 10487 10488 case ABI_AIX: 10489 /* AIX function pointers are really pointers to a three word 10490 area. */ 10491 emit_call_insn (TARGET_32BIT 10492 ? gen_call_value_indirect_aix32 (operands[0], 10493 force_reg (SImode, 10494 operands[1]), 10495 operands[2]) 10496 : gen_call_value_indirect_aix64 (operands[0], 10497 force_reg (DImode, 10498 operands[1]), 10499 operands[2])); 10500 DONE; 10501 10502 default: 10503 gcc_unreachable (); 10504 } 10505 } 10506}") 10507 10508;; Call to function in current module. No TOC pointer reload needed. 10509;; Operand2 is nonzero if we are using the V.4 calling sequence and 10510;; either the function was not prototyped, or it was prototyped as a 10511;; variable argument function. It is > 0 if FP registers were passed 10512;; and < 0 if they were not. 10513 10514(define_insn "*call_local32" 10515 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) 10516 (match_operand 1 "" "g,g")) 10517 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10518 (clobber (match_scratch:SI 3 "=l,l"))] 10519 "(INTVAL (operands[2]) & CALL_LONG) == 0" 10520 "* 10521{ 10522 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10523 output_asm_insn (\"crxor 6,6,6\", operands); 10524 10525 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10526 output_asm_insn (\"creqv 6,6,6\", operands); 10527 10528 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; 10529}" 10530 [(set_attr "type" "branch") 10531 (set_attr "length" "4,8")]) 10532 10533(define_insn "*call_local64" 10534 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) 10535 (match_operand 1 "" "g,g")) 10536 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10537 (clobber (match_scratch:SI 3 "=l,l"))] 10538 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" 10539 "* 10540{ 10541 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10542 output_asm_insn (\"crxor 6,6,6\", operands); 10543 10544 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10545 output_asm_insn (\"creqv 6,6,6\", operands); 10546 10547 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; 10548}" 10549 [(set_attr "type" "branch") 10550 (set_attr "length" "4,8")]) 10551 10552(define_insn "*call_value_local32" 10553 [(set (match_operand 0 "" "") 10554 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) 10555 (match_operand 2 "" "g,g"))) 10556 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10557 (clobber (match_scratch:SI 4 "=l,l"))] 10558 "(INTVAL (operands[3]) & CALL_LONG) == 0" 10559 "* 10560{ 10561 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10562 output_asm_insn (\"crxor 6,6,6\", operands); 10563 10564 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10565 output_asm_insn (\"creqv 6,6,6\", operands); 10566 10567 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; 10568}" 10569 [(set_attr "type" "branch") 10570 (set_attr "length" "4,8")]) 10571 10572 10573(define_insn "*call_value_local64" 10574 [(set (match_operand 0 "" "") 10575 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) 10576 (match_operand 2 "" "g,g"))) 10577 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10578 (clobber (match_scratch:SI 4 "=l,l"))] 10579 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" 10580 "* 10581{ 10582 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10583 output_asm_insn (\"crxor 6,6,6\", operands); 10584 10585 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10586 output_asm_insn (\"creqv 6,6,6\", operands); 10587 10588 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; 10589}" 10590 [(set_attr "type" "branch") 10591 (set_attr "length" "4,8")]) 10592 10593;; Call to function which may be in another module. Restore the TOC 10594;; pointer (r2) after the call unless this is System V. 10595;; Operand2 is nonzero if we are using the V.4 calling sequence and 10596;; either the function was not prototyped, or it was prototyped as a 10597;; variable argument function. It is > 0 if FP registers were passed 10598;; and < 0 if they were not. 10599 10600(define_insn "*call_indirect_nonlocal_aix32" 10601 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l")) 10602 (match_operand 1 "" "g,g")) 10603 (use (reg:SI 2)) 10604 (use (reg:SI 11)) 10605 (set (reg:SI 2) 10606 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 10607 (clobber (match_scratch:SI 2 "=l,l"))] 10608 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" 10609 "b%T0l\;{l|lwz} 2,20(1)" 10610 [(set_attr "type" "jmpreg") 10611 (set_attr "length" "8")]) 10612 10613(define_insn "*call_nonlocal_aix32" 10614 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) 10615 (match_operand 1 "" "g")) 10616 (use (match_operand:SI 2 "immediate_operand" "O")) 10617 (clobber (match_scratch:SI 3 "=l"))] 10618 "TARGET_32BIT 10619 && DEFAULT_ABI == ABI_AIX 10620 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10621 "bl %z0\;%." 10622 [(set_attr "type" "branch") 10623 (set_attr "length" "8")]) 10624 10625(define_insn "*call_indirect_nonlocal_aix64" 10626 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l")) 10627 (match_operand 1 "" "g,g")) 10628 (use (reg:DI 2)) 10629 (use (reg:DI 11)) 10630 (set (reg:DI 2) 10631 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10632 (clobber (match_scratch:SI 2 "=l,l"))] 10633 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" 10634 "b%T0l\;ld 2,40(1)" 10635 [(set_attr "type" "jmpreg") 10636 (set_attr "length" "8")]) 10637 10638(define_insn "*call_nonlocal_aix64" 10639 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) 10640 (match_operand 1 "" "g")) 10641 (use (match_operand:SI 2 "immediate_operand" "O")) 10642 (clobber (match_scratch:SI 3 "=l"))] 10643 "TARGET_64BIT 10644 && DEFAULT_ABI == ABI_AIX 10645 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10646 "bl %z0\;%." 10647 [(set_attr "type" "branch") 10648 (set_attr "length" "8")]) 10649 10650(define_insn "*call_value_indirect_nonlocal_aix32" 10651 [(set (match_operand 0 "" "") 10652 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l")) 10653 (match_operand 2 "" "g,g"))) 10654 (use (reg:SI 2)) 10655 (use (reg:SI 11)) 10656 (set (reg:SI 2) 10657 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 10658 (clobber (match_scratch:SI 3 "=l,l"))] 10659 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" 10660 "b%T1l\;{l|lwz} 2,20(1)" 10661 [(set_attr "type" "jmpreg") 10662 (set_attr "length" "8")]) 10663 10664(define_insn "*call_value_nonlocal_aix32" 10665 [(set (match_operand 0 "" "") 10666 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) 10667 (match_operand 2 "" "g"))) 10668 (use (match_operand:SI 3 "immediate_operand" "O")) 10669 (clobber (match_scratch:SI 4 "=l"))] 10670 "TARGET_32BIT 10671 && DEFAULT_ABI == ABI_AIX 10672 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10673 "bl %z1\;%." 10674 [(set_attr "type" "branch") 10675 (set_attr "length" "8")]) 10676 10677(define_insn "*call_value_indirect_nonlocal_aix64" 10678 [(set (match_operand 0 "" "") 10679 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l")) 10680 (match_operand 2 "" "g,g"))) 10681 (use (reg:DI 2)) 10682 (use (reg:DI 11)) 10683 (set (reg:DI 2) 10684 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10685 (clobber (match_scratch:SI 3 "=l,l"))] 10686 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" 10687 "b%T1l\;ld 2,40(1)" 10688 [(set_attr "type" "jmpreg") 10689 (set_attr "length" "8")]) 10690 10691(define_insn "*call_value_nonlocal_aix64" 10692 [(set (match_operand 0 "" "") 10693 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) 10694 (match_operand 2 "" "g"))) 10695 (use (match_operand:SI 3 "immediate_operand" "O")) 10696 (clobber (match_scratch:SI 4 "=l"))] 10697 "TARGET_64BIT 10698 && DEFAULT_ABI == ABI_AIX 10699 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10700 "bl %z1\;%." 10701 [(set_attr "type" "branch") 10702 (set_attr "length" "8")]) 10703 10704;; A function pointer under System V is just a normal pointer 10705;; operands[0] is the function pointer 10706;; operands[1] is the stack size to clean up 10707;; operands[2] is the value FUNCTION_ARG returns for the VOID argument 10708;; which indicates how to set cr1 10709 10710(define_insn "*call_indirect_nonlocal_sysv<mode>" 10711 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l")) 10712 (match_operand 1 "" "g,g,g,g")) 10713 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) 10714 (clobber (match_scratch:SI 3 "=l,l,l,l"))] 10715 "DEFAULT_ABI == ABI_V4 10716 || DEFAULT_ABI == ABI_DARWIN" 10717{ 10718 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10719 output_asm_insn ("crxor 6,6,6", operands); 10720 10721 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10722 output_asm_insn ("creqv 6,6,6", operands); 10723 10724 return "b%T0l"; 10725} 10726 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") 10727 (set_attr "length" "4,4,8,8")]) 10728 10729(define_insn "*call_nonlocal_sysv<mode>" 10730 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s")) 10731 (match_operand 1 "" "g,g")) 10732 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10733 (clobber (match_scratch:SI 3 "=l,l"))] 10734 "(DEFAULT_ABI == ABI_DARWIN 10735 || (DEFAULT_ABI == ABI_V4 10736 && (INTVAL (operands[2]) & CALL_LONG) == 0))" 10737{ 10738 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10739 output_asm_insn ("crxor 6,6,6", operands); 10740 10741 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10742 output_asm_insn ("creqv 6,6,6", operands); 10743 10744#if TARGET_MACHO 10745 return output_call(insn, operands, 0, 2); 10746#else 10747 if (DEFAULT_ABI == ABI_V4 && flag_pic) 10748 { 10749 if (TARGET_SECURE_PLT && flag_pic == 2) 10750 /* The magic 32768 offset here and in the other sysv call insns 10751 corresponds to the offset of r30 in .got2, as given by LCTOC1. 10752 See sysv4.h:toc_section. */ 10753 return "bl %z0+32768@plt"; 10754 else 10755 return "bl %z0@plt"; 10756 } 10757 else 10758 return "bl %z0"; 10759#endif 10760} 10761 [(set_attr "type" "branch,branch") 10762 (set_attr "length" "4,8")]) 10763 10764(define_insn "*call_value_indirect_nonlocal_sysv<mode>" 10765 [(set (match_operand 0 "" "") 10766 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l")) 10767 (match_operand 2 "" "g,g,g,g"))) 10768 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) 10769 (clobber (match_scratch:SI 4 "=l,l,l,l"))] 10770 "DEFAULT_ABI == ABI_V4 10771 || DEFAULT_ABI == ABI_DARWIN" 10772{ 10773 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10774 output_asm_insn ("crxor 6,6,6", operands); 10775 10776 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10777 output_asm_insn ("creqv 6,6,6", operands); 10778 10779 return "b%T1l"; 10780} 10781 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") 10782 (set_attr "length" "4,4,8,8")]) 10783 10784(define_insn "*call_value_nonlocal_sysv<mode>" 10785 [(set (match_operand 0 "" "") 10786 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s")) 10787 (match_operand 2 "" "g,g"))) 10788 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10789 (clobber (match_scratch:SI 4 "=l,l"))] 10790 "(DEFAULT_ABI == ABI_DARWIN 10791 || (DEFAULT_ABI == ABI_V4 10792 && (INTVAL (operands[3]) & CALL_LONG) == 0))" 10793{ 10794 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10795 output_asm_insn ("crxor 6,6,6", operands); 10796 10797 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10798 output_asm_insn ("creqv 6,6,6", operands); 10799 10800#if TARGET_MACHO 10801 return output_call(insn, operands, 1, 3); 10802#else 10803 if (DEFAULT_ABI == ABI_V4 && flag_pic) 10804 { 10805 if (TARGET_SECURE_PLT && flag_pic == 2) 10806 return "bl %z1+32768@plt"; 10807 else 10808 return "bl %z1@plt"; 10809 } 10810 else 10811 return "bl %z1"; 10812#endif 10813} 10814 [(set_attr "type" "branch,branch") 10815 (set_attr "length" "4,8")]) 10816 10817;; Call subroutine returning any type. 10818(define_expand "untyped_call" 10819 [(parallel [(call (match_operand 0 "" "") 10820 (const_int 0)) 10821 (match_operand 1 "" "") 10822 (match_operand 2 "" "")])] 10823 "" 10824 " 10825{ 10826 int i; 10827 10828 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); 10829 10830 for (i = 0; i < XVECLEN (operands[2], 0); i++) 10831 { 10832 rtx set = XVECEXP (operands[2], 0, i); 10833 emit_move_insn (SET_DEST (set), SET_SRC (set)); 10834 } 10835 10836 /* The optimizer does not know that the call sets the function value 10837 registers we stored in the result block. We avoid problems by 10838 claiming that all hard registers are used and clobbered at this 10839 point. */ 10840 emit_insn (gen_blockage ()); 10841 10842 DONE; 10843}") 10844 10845;; sibling call patterns 10846(define_expand "sibcall" 10847 [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) 10848 (match_operand 1 "" "")) 10849 (use (match_operand 2 "" "")) 10850 (use (match_operand 3 "" "")) 10851 (return)])] 10852 "" 10853 " 10854{ 10855#if TARGET_MACHO 10856 if (MACHOPIC_INDIRECT) 10857 operands[0] = machopic_indirect_call_target (operands[0]); 10858#endif 10859 10860 gcc_assert (GET_CODE (operands[0]) == MEM); 10861 gcc_assert (GET_CODE (operands[1]) == CONST_INT); 10862 10863 operands[0] = XEXP (operands[0], 0); 10864 operands[3] = gen_reg_rtx (SImode); 10865 10866}") 10867 10868;; this and similar patterns must be marked as using LR, otherwise 10869;; dataflow will try to delete the store into it. This is true 10870;; even when the actual reg to jump to is in CTR, when LR was 10871;; saved and restored around the PIC-setting BCL. 10872(define_insn "*sibcall_local32" 10873 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) 10874 (match_operand 1 "" "g,g")) 10875 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10876 (use (match_operand:SI 3 "register_operand" "l,l")) 10877 (return)] 10878 "(INTVAL (operands[2]) & CALL_LONG) == 0" 10879 "* 10880{ 10881 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10882 output_asm_insn (\"crxor 6,6,6\", operands); 10883 10884 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10885 output_asm_insn (\"creqv 6,6,6\", operands); 10886 10887 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; 10888}" 10889 [(set_attr "type" "branch") 10890 (set_attr "length" "4,8")]) 10891 10892(define_insn "*sibcall_local64" 10893 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) 10894 (match_operand 1 "" "g,g")) 10895 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10896 (use (match_operand:SI 3 "register_operand" "l,l")) 10897 (return)] 10898 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" 10899 "* 10900{ 10901 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10902 output_asm_insn (\"crxor 6,6,6\", operands); 10903 10904 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10905 output_asm_insn (\"creqv 6,6,6\", operands); 10906 10907 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; 10908}" 10909 [(set_attr "type" "branch") 10910 (set_attr "length" "4,8")]) 10911 10912(define_insn "*sibcall_value_local32" 10913 [(set (match_operand 0 "" "") 10914 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) 10915 (match_operand 2 "" "g,g"))) 10916 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10917 (use (match_operand:SI 4 "register_operand" "l,l")) 10918 (return)] 10919 "(INTVAL (operands[3]) & CALL_LONG) == 0" 10920 "* 10921{ 10922 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10923 output_asm_insn (\"crxor 6,6,6\", operands); 10924 10925 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10926 output_asm_insn (\"creqv 6,6,6\", operands); 10927 10928 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; 10929}" 10930 [(set_attr "type" "branch") 10931 (set_attr "length" "4,8")]) 10932 10933 10934(define_insn "*sibcall_value_local64" 10935 [(set (match_operand 0 "" "") 10936 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) 10937 (match_operand 2 "" "g,g"))) 10938 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10939 (use (match_operand:SI 4 "register_operand" "l,l")) 10940 (return)] 10941 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" 10942 "* 10943{ 10944 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10945 output_asm_insn (\"crxor 6,6,6\", operands); 10946 10947 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10948 output_asm_insn (\"creqv 6,6,6\", operands); 10949 10950 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; 10951}" 10952 [(set_attr "type" "branch") 10953 (set_attr "length" "4,8")]) 10954 10955(define_insn "*sibcall_nonlocal_aix32" 10956 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) 10957 (match_operand 1 "" "g")) 10958 (use (match_operand:SI 2 "immediate_operand" "O")) 10959 (use (match_operand:SI 3 "register_operand" "l")) 10960 (return)] 10961 "TARGET_32BIT 10962 && DEFAULT_ABI == ABI_AIX 10963 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10964 "b %z0" 10965 [(set_attr "type" "branch") 10966 (set_attr "length" "4")]) 10967 10968(define_insn "*sibcall_nonlocal_aix64" 10969 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) 10970 (match_operand 1 "" "g")) 10971 (use (match_operand:SI 2 "immediate_operand" "O")) 10972 (use (match_operand:SI 3 "register_operand" "l")) 10973 (return)] 10974 "TARGET_64BIT 10975 && DEFAULT_ABI == ABI_AIX 10976 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10977 "b %z0" 10978 [(set_attr "type" "branch") 10979 (set_attr "length" "4")]) 10980 10981(define_insn "*sibcall_value_nonlocal_aix32" 10982 [(set (match_operand 0 "" "") 10983 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) 10984 (match_operand 2 "" "g"))) 10985 (use (match_operand:SI 3 "immediate_operand" "O")) 10986 (use (match_operand:SI 4 "register_operand" "l")) 10987 (return)] 10988 "TARGET_32BIT 10989 && DEFAULT_ABI == ABI_AIX 10990 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10991 "b %z1" 10992 [(set_attr "type" "branch") 10993 (set_attr "length" "4")]) 10994 10995(define_insn "*sibcall_value_nonlocal_aix64" 10996 [(set (match_operand 0 "" "") 10997 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) 10998 (match_operand 2 "" "g"))) 10999 (use (match_operand:SI 3 "immediate_operand" "O")) 11000 (use (match_operand:SI 4 "register_operand" "l")) 11001 (return)] 11002 "TARGET_64BIT 11003 && DEFAULT_ABI == ABI_AIX 11004 && (INTVAL (operands[3]) & CALL_LONG) == 0" 11005 "b %z1" 11006 [(set_attr "type" "branch") 11007 (set_attr "length" "4")]) 11008 11009(define_insn "*sibcall_nonlocal_sysv<mode>" 11010 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s")) 11011 (match_operand 1 "" "")) 11012 (use (match_operand 2 "immediate_operand" "O,n")) 11013 (use (match_operand:SI 3 "register_operand" "l,l")) 11014 (return)] 11015 "(DEFAULT_ABI == ABI_DARWIN 11016 || DEFAULT_ABI == ABI_V4) 11017 && (INTVAL (operands[2]) & CALL_LONG) == 0" 11018 "* 11019{ 11020 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 11021 output_asm_insn (\"crxor 6,6,6\", operands); 11022 11023 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 11024 output_asm_insn (\"creqv 6,6,6\", operands); 11025 11026 if (DEFAULT_ABI == ABI_V4 && flag_pic) 11027 { 11028 if (TARGET_SECURE_PLT && flag_pic == 2) 11029 return \"b %z0+32768@plt\"; 11030 else 11031 return \"b %z0@plt\"; 11032 } 11033 else 11034 return \"b %z0\"; 11035}" 11036 [(set_attr "type" "branch,branch") 11037 (set_attr "length" "4,8")]) 11038 11039(define_expand "sibcall_value" 11040 [(parallel [(set (match_operand 0 "register_operand" "") 11041 (call (mem:SI (match_operand 1 "address_operand" "")) 11042 (match_operand 2 "" ""))) 11043 (use (match_operand 3 "" "")) 11044 (use (match_operand 4 "" "")) 11045 (return)])] 11046 "" 11047 " 11048{ 11049#if TARGET_MACHO 11050 if (MACHOPIC_INDIRECT) 11051 operands[1] = machopic_indirect_call_target (operands[1]); 11052#endif 11053 11054 gcc_assert (GET_CODE (operands[1]) == MEM); 11055 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 11056 11057 operands[1] = XEXP (operands[1], 0); 11058 operands[4] = gen_reg_rtx (SImode); 11059 11060}") 11061 11062(define_insn "*sibcall_value_nonlocal_sysv<mode>" 11063 [(set (match_operand 0 "" "") 11064 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s")) 11065 (match_operand 2 "" ""))) 11066 (use (match_operand:SI 3 "immediate_operand" "O,n")) 11067 (use (match_operand:SI 4 "register_operand" "l,l")) 11068 (return)] 11069 "(DEFAULT_ABI == ABI_DARWIN 11070 || DEFAULT_ABI == ABI_V4) 11071 && (INTVAL (operands[3]) & CALL_LONG) == 0" 11072 "* 11073{ 11074 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 11075 output_asm_insn (\"crxor 6,6,6\", operands); 11076 11077 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 11078 output_asm_insn (\"creqv 6,6,6\", operands); 11079 11080 if (DEFAULT_ABI == ABI_V4 && flag_pic) 11081 { 11082 if (TARGET_SECURE_PLT && flag_pic == 2) 11083 return \"b %z1+32768@plt\"; 11084 else 11085 return \"b %z1@plt\"; 11086 } 11087 else 11088 return \"b %z1\"; 11089}" 11090 [(set_attr "type" "branch,branch") 11091 (set_attr "length" "4,8")]) 11092 11093(define_expand "sibcall_epilogue" 11094 [(use (const_int 0))] 11095 "TARGET_SCHED_PROLOG" 11096 " 11097{ 11098 rs6000_emit_epilogue (TRUE); 11099 DONE; 11100}") 11101 11102;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 11103;; all of memory. This blocks insns from being moved across this point. 11104 11105(define_insn "blockage" 11106 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] 11107 "" 11108 "") 11109 11110;; Compare insns are next. Note that the RS/6000 has two types of compares, 11111;; signed & unsigned, and one type of branch. 11112;; 11113;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc 11114;; insns, and branches. We store the operands of compares until we see 11115;; how it is used. 11116(define_expand "cmp<mode>" 11117 [(set (cc0) 11118 (compare (match_operand:GPR 0 "gpc_reg_operand" "") 11119 (match_operand:GPR 1 "reg_or_short_operand" "")))] 11120 "" 11121 " 11122{ 11123 /* Take care of the possibility that operands[1] might be negative but 11124 this might be a logical operation. That insn doesn't exist. */ 11125 if (GET_CODE (operands[1]) == CONST_INT 11126 && INTVAL (operands[1]) < 0) 11127 operands[1] = force_reg (<MODE>mode, operands[1]); 11128 11129 rs6000_compare_op0 = operands[0]; 11130 rs6000_compare_op1 = operands[1]; 11131 rs6000_compare_fp_p = 0; 11132 DONE; 11133}") 11134 11135(define_expand "cmp<mode>" 11136 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "") 11137 (match_operand:FP 1 "gpc_reg_operand" "")))] 11138 "" 11139 " 11140{ 11141 rs6000_compare_op0 = operands[0]; 11142 rs6000_compare_op1 = operands[1]; 11143 rs6000_compare_fp_p = 1; 11144 DONE; 11145}") 11146 11147(define_expand "beq" 11148 [(use (match_operand 0 "" ""))] 11149 "" 11150 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") 11151 11152(define_expand "bne" 11153 [(use (match_operand 0 "" ""))] 11154 "" 11155 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") 11156 11157(define_expand "bge" 11158 [(use (match_operand 0 "" ""))] 11159 "" 11160 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") 11161 11162(define_expand "bgt" 11163 [(use (match_operand 0 "" ""))] 11164 "" 11165 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") 11166 11167(define_expand "ble" 11168 [(use (match_operand 0 "" ""))] 11169 "" 11170 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") 11171 11172(define_expand "blt" 11173 [(use (match_operand 0 "" ""))] 11174 "" 11175 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") 11176 11177(define_expand "bgeu" 11178 [(use (match_operand 0 "" ""))] 11179 "" 11180 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") 11181 11182(define_expand "bgtu" 11183 [(use (match_operand 0 "" ""))] 11184 "" 11185 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") 11186 11187(define_expand "bleu" 11188 [(use (match_operand 0 "" ""))] 11189 "" 11190 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") 11191 11192(define_expand "bltu" 11193 [(use (match_operand 0 "" ""))] 11194 "" 11195 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") 11196 11197(define_expand "bunordered" 11198 [(use (match_operand 0 "" ""))] 11199 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" 11200 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") 11201 11202(define_expand "bordered" 11203 [(use (match_operand 0 "" ""))] 11204 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" 11205 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") 11206 11207(define_expand "buneq" 11208 [(use (match_operand 0 "" ""))] 11209 "" 11210 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") 11211 11212(define_expand "bunge" 11213 [(use (match_operand 0 "" ""))] 11214 "" 11215 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") 11216 11217(define_expand "bungt" 11218 [(use (match_operand 0 "" ""))] 11219 "" 11220 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") 11221 11222(define_expand "bunle" 11223 [(use (match_operand 0 "" ""))] 11224 "" 11225 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") 11226 11227(define_expand "bunlt" 11228 [(use (match_operand 0 "" ""))] 11229 "" 11230 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") 11231 11232(define_expand "bltgt" 11233 [(use (match_operand 0 "" ""))] 11234 "" 11235 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") 11236 11237;; For SNE, we would prefer that the xor/abs sequence be used for integers. 11238;; For SEQ, likewise, except that comparisons with zero should be done 11239;; with an scc insns. However, due to the order that combine see the 11240;; resulting insns, we must, in fact, allow SEQ for integers. Fail in 11241;; the cases we don't want to handle. 11242(define_expand "seq" 11243 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11244 "" 11245 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") 11246 11247(define_expand "sne" 11248 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11249 "" 11250 " 11251{ 11252 if (! rs6000_compare_fp_p) 11253 FAIL; 11254 11255 rs6000_emit_sCOND (NE, operands[0]); 11256 DONE; 11257}") 11258 11259;; A >= 0 is best done the portable way for A an integer. 11260(define_expand "sge" 11261 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11262 "" 11263 " 11264{ 11265 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 11266 FAIL; 11267 11268 rs6000_emit_sCOND (GE, operands[0]); 11269 DONE; 11270}") 11271 11272;; A > 0 is best done using the portable sequence, so fail in that case. 11273(define_expand "sgt" 11274 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11275 "" 11276 " 11277{ 11278 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 11279 FAIL; 11280 11281 rs6000_emit_sCOND (GT, operands[0]); 11282 DONE; 11283}") 11284 11285;; A <= 0 is best done the portable way for A an integer. 11286(define_expand "sle" 11287 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11288 "" 11289 " 11290{ 11291 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 11292 FAIL; 11293 11294 rs6000_emit_sCOND (LE, operands[0]); 11295 DONE; 11296}") 11297 11298;; A < 0 is best done in the portable way for A an integer. 11299(define_expand "slt" 11300 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11301 "" 11302 " 11303{ 11304 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 11305 FAIL; 11306 11307 rs6000_emit_sCOND (LT, operands[0]); 11308 DONE; 11309}") 11310 11311(define_expand "sgeu" 11312 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11313 "" 11314 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") 11315 11316(define_expand "sgtu" 11317 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11318 "" 11319 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") 11320 11321(define_expand "sleu" 11322 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11323 "" 11324 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") 11325 11326(define_expand "sltu" 11327 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11328 "" 11329 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") 11330 11331(define_expand "sunordered" 11332 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11333 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" 11334 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") 11335 11336(define_expand "sordered" 11337 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11338 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" 11339 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") 11340 11341(define_expand "suneq" 11342 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11343 "" 11344 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") 11345 11346(define_expand "sunge" 11347 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11348 "" 11349 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") 11350 11351(define_expand "sungt" 11352 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11353 "" 11354 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") 11355 11356(define_expand "sunle" 11357 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11358 "" 11359 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") 11360 11361(define_expand "sunlt" 11362 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11363 "" 11364 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") 11365 11366(define_expand "sltgt" 11367 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11368 "" 11369 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") 11370 11371(define_expand "stack_protect_set" 11372 [(match_operand 0 "memory_operand" "") 11373 (match_operand 1 "memory_operand" "")] 11374 "" 11375{ 11376#ifdef TARGET_THREAD_SSP_OFFSET 11377 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2); 11378 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET)); 11379 operands[1] = gen_rtx_MEM (Pmode, addr); 11380#endif 11381 if (TARGET_64BIT) 11382 emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); 11383 else 11384 emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); 11385 DONE; 11386}) 11387 11388(define_insn "stack_protect_setsi" 11389 [(set (match_operand:SI 0 "memory_operand" "=m") 11390 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) 11391 (set (match_scratch:SI 2 "=&r") (const_int 0))] 11392 "TARGET_32BIT" 11393 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0" 11394 [(set_attr "type" "three") 11395 (set_attr "length" "12")]) 11396 11397(define_insn "stack_protect_setdi" 11398 [(set (match_operand:DI 0 "memory_operand" "=m") 11399 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET)) 11400 (set (match_scratch:DI 2 "=&r") (const_int 0))] 11401 "TARGET_64BIT" 11402 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0" 11403 [(set_attr "type" "three") 11404 (set_attr "length" "12")]) 11405 11406(define_expand "stack_protect_test" 11407 [(match_operand 0 "memory_operand" "") 11408 (match_operand 1 "memory_operand" "") 11409 (match_operand 2 "" "")] 11410 "" 11411{ 11412#ifdef TARGET_THREAD_SSP_OFFSET 11413 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2); 11414 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET)); 11415 operands[1] = gen_rtx_MEM (Pmode, addr); 11416#endif 11417 rs6000_compare_op0 = operands[0]; 11418 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), 11419 UNSPEC_SP_TEST); 11420 rs6000_compare_fp_p = 0; 11421 emit_jump_insn (gen_beq (operands[2])); 11422 DONE; 11423}) 11424 11425(define_insn "stack_protect_testsi" 11426 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") 11427 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m") 11428 (match_operand:SI 2 "memory_operand" "m,m")] 11429 UNSPEC_SP_TEST)) 11430 (set (match_scratch:SI 4 "=r,r") (const_int 0)) 11431 (clobber (match_scratch:SI 3 "=&r,&r"))] 11432 "TARGET_32BIT" 11433 "@ 11434 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0 11435 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0" 11436 [(set_attr "length" "16,20")]) 11437 11438(define_insn "stack_protect_testdi" 11439 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") 11440 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m") 11441 (match_operand:DI 2 "memory_operand" "m,m")] 11442 UNSPEC_SP_TEST)) 11443 (set (match_scratch:DI 4 "=r,r") (const_int 0)) 11444 (clobber (match_scratch:DI 3 "=&r,&r"))] 11445 "TARGET_64BIT" 11446 "@ 11447 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0 11448 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0" 11449 [(set_attr "length" "16,20")]) 11450 11451 11452;; Here are the actual compare insns. 11453(define_insn "*cmp<mode>_internal1" 11454 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 11455 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r") 11456 (match_operand:GPR 2 "reg_or_short_operand" "rI")))] 11457 "" 11458 "{cmp%I2|cmp<wd>%I2} %0,%1,%2" 11459 [(set_attr "type" "cmp")]) 11460 11461;; If we are comparing a register for equality with a large constant, 11462;; we can do this with an XOR followed by a compare. But this is profitable 11463;; only if the large constant is only used for the comparison (and in this 11464;; case we already have a register to reuse as scratch). 11465;; 11466;; For 64-bit registers, we could only do so if the constant's bit 15 is clear: 11467;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available. 11468 11469(define_peephole2 11470 [(set (match_operand:SI 0 "register_operand") 11471 (match_operand:SI 1 "logical_const_operand" "")) 11472 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator" 11473 [(match_dup 0) 11474 (match_operand:SI 2 "logical_const_operand" "")])) 11475 (set (match_operand:CC 4 "cc_reg_operand" "") 11476 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "") 11477 (match_dup 0))) 11478 (set (pc) 11479 (if_then_else (match_operator 6 "equality_operator" 11480 [(match_dup 4) (const_int 0)]) 11481 (match_operand 7 "" "") 11482 (match_operand 8 "" "")))] 11483 "peep2_reg_dead_p (3, operands[0]) 11484 && peep2_reg_dead_p (4, operands[4])" 11485 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9))) 11486 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10))) 11487 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))] 11488 11489{ 11490 /* Get the constant we are comparing against, and see what it looks like 11491 when sign-extended from 16 to 32 bits. Then see what constant we could 11492 XOR with SEXTC to get the sign-extended value. */ 11493 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]), 11494 SImode, 11495 operands[1], operands[2]); 11496 HOST_WIDE_INT c = INTVAL (cnst); 11497 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; 11498 HOST_WIDE_INT xorv = c ^ sextc; 11499 11500 operands[9] = GEN_INT (xorv); 11501 operands[10] = GEN_INT (sextc); 11502}) 11503 11504(define_insn "*cmpsi_internal2" 11505 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 11506 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 11507 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] 11508 "" 11509 "{cmpl%I2|cmplw%I2} %0,%1,%b2" 11510 [(set_attr "type" "cmp")]) 11511 11512(define_insn "*cmpdi_internal2" 11513 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 11514 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") 11515 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] 11516 "" 11517 "cmpld%I2 %0,%1,%b2" 11518 [(set_attr "type" "cmp")]) 11519 11520;; The following two insns don't exist as single insns, but if we provide 11521;; them, we can swap an add and compare, which will enable us to overlap more 11522;; of the required delay between a compare and branch. We generate code for 11523;; them by splitting. 11524 11525(define_insn "" 11526 [(set (match_operand:CC 3 "cc_reg_operand" "=y") 11527 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 11528 (match_operand:SI 2 "short_cint_operand" "i"))) 11529 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 11530 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 11531 "" 11532 "#" 11533 [(set_attr "length" "8")]) 11534 11535(define_insn "" 11536 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") 11537 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 11538 (match_operand:SI 2 "u_short_cint_operand" "i"))) 11539 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 11540 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 11541 "" 11542 "#" 11543 [(set_attr "length" "8")]) 11544 11545(define_split 11546 [(set (match_operand:CC 3 "cc_reg_operand" "") 11547 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 11548 (match_operand:SI 2 "short_cint_operand" ""))) 11549 (set (match_operand:SI 0 "gpc_reg_operand" "") 11550 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 11551 "" 11552 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) 11553 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 11554 11555(define_split 11556 [(set (match_operand:CCUNS 3 "cc_reg_operand" "") 11557 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") 11558 (match_operand:SI 2 "u_short_cint_operand" ""))) 11559 (set (match_operand:SI 0 "gpc_reg_operand" "") 11560 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 11561 "" 11562 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) 11563 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 11564 11565(define_insn "*cmpsf_internal1" 11566 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 11567 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") 11568 (match_operand:SF 2 "gpc_reg_operand" "f")))] 11569 "TARGET_HARD_FLOAT && TARGET_FPRS" 11570 "fcmpu %0,%1,%2" 11571 [(set_attr "type" "fpcompare")]) 11572 11573(define_insn "*cmpdf_internal1" 11574 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 11575 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") 11576 (match_operand:DF 2 "gpc_reg_operand" "f")))] 11577 "TARGET_HARD_FLOAT && TARGET_FPRS" 11578 "fcmpu %0,%1,%2" 11579 [(set_attr "type" "fpcompare")]) 11580 11581;; Only need to compare second words if first words equal 11582(define_insn "*cmptf_internal1" 11583 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 11584 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") 11585 (match_operand:TF 2 "gpc_reg_operand" "f")))] 11586 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT 11587 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 11588 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" 11589 [(set_attr "type" "fpcompare") 11590 (set_attr "length" "12")]) 11591 11592(define_insn_and_split "*cmptf_internal2" 11593 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 11594 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") 11595 (match_operand:TF 2 "gpc_reg_operand" "f"))) 11596 (clobber (match_scratch:DF 3 "=f")) 11597 (clobber (match_scratch:DF 4 "=f")) 11598 (clobber (match_scratch:DF 5 "=f")) 11599 (clobber (match_scratch:DF 6 "=f")) 11600 (clobber (match_scratch:DF 7 "=f")) 11601 (clobber (match_scratch:DF 8 "=f")) 11602 (clobber (match_scratch:DF 9 "=f")) 11603 (clobber (match_scratch:DF 10 "=f"))] 11604 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT 11605 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 11606 "#" 11607 "&& reload_completed" 11608 [(set (match_dup 3) (match_dup 13)) 11609 (set (match_dup 4) (match_dup 14)) 11610 (set (match_dup 9) (abs:DF (match_dup 5))) 11611 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3))) 11612 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0)) 11613 (label_ref (match_dup 11)) 11614 (pc))) 11615 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7))) 11616 (set (pc) (label_ref (match_dup 12))) 11617 (match_dup 11) 11618 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7))) 11619 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8))) 11620 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9))) 11621 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4))) 11622 (match_dup 12)] 11623{ 11624 REAL_VALUE_TYPE rv; 11625 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; 11626 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); 11627 11628 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word); 11629 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word); 11630 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word); 11631 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word); 11632 operands[11] = gen_label_rtx (); 11633 operands[12] = gen_label_rtx (); 11634 real_inf (&rv); 11635 operands[13] = force_const_mem (DFmode, 11636 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode)); 11637 operands[14] = force_const_mem (DFmode, 11638 CONST_DOUBLE_FROM_REAL_VALUE (dconst0, 11639 DFmode)); 11640 if (TARGET_TOC) 11641 { 11642 operands[13] = gen_const_mem (DFmode, 11643 create_TOC_reference (XEXP (operands[13], 0))); 11644 operands[14] = gen_const_mem (DFmode, 11645 create_TOC_reference (XEXP (operands[14], 0))); 11646 set_mem_alias_set (operands[13], get_TOC_alias_set ()); 11647 set_mem_alias_set (operands[14], get_TOC_alias_set ()); 11648 } 11649}) 11650 11651;; Now we have the scc insns. We can do some combinations because of the 11652;; way the machine works. 11653;; 11654;; Note that this is probably faster if we can put an insn between the 11655;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most 11656;; cases the insns below which don't use an intermediate CR field will 11657;; be used instead. 11658(define_insn "" 11659 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11660 (match_operator:SI 1 "scc_comparison_operator" 11661 [(match_operand 2 "cc_reg_operand" "y") 11662 (const_int 0)]))] 11663 "" 11664 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" 11665 [(set (attr "type") 11666 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) 11667 (const_string "mfcrf") 11668 ] 11669 (const_string "mfcr"))) 11670 (set_attr "length" "8")]) 11671 11672;; Same as above, but get the GT bit. 11673(define_insn "move_from_CR_gt_bit" 11674 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11675 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))] 11676 "TARGET_E500" 11677 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31" 11678 [(set_attr "type" "mfcr") 11679 (set_attr "length" "8")]) 11680 11681;; Same as above, but get the OV/ORDERED bit. 11682(define_insn "move_from_CR_ov_bit" 11683 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11684 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] 11685 "TARGET_ISEL" 11686 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" 11687 [(set_attr "type" "mfcr") 11688 (set_attr "length" "8")]) 11689 11690(define_insn "" 11691 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11692 (match_operator:DI 1 "scc_comparison_operator" 11693 [(match_operand 2 "cc_reg_operand" "y") 11694 (const_int 0)]))] 11695 "TARGET_POWERPC64" 11696 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" 11697 [(set (attr "type") 11698 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) 11699 (const_string "mfcrf") 11700 ] 11701 (const_string "mfcr"))) 11702 (set_attr "length" "8")]) 11703 11704(define_insn "" 11705 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11706 (compare:CC (match_operator:SI 1 "scc_comparison_operator" 11707 [(match_operand 2 "cc_reg_operand" "y,y") 11708 (const_int 0)]) 11709 (const_int 0))) 11710 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 11711 (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 11712 "TARGET_32BIT" 11713 "@ 11714 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 11715 #" 11716 [(set_attr "type" "delayed_compare") 11717 (set_attr "length" "8,16")]) 11718 11719(define_split 11720 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11721 (compare:CC (match_operator:SI 1 "scc_comparison_operator" 11722 [(match_operand 2 "cc_reg_operand" "") 11723 (const_int 0)]) 11724 (const_int 0))) 11725 (set (match_operand:SI 3 "gpc_reg_operand" "") 11726 (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 11727 "TARGET_32BIT && reload_completed" 11728 [(set (match_dup 3) 11729 (match_op_dup 1 [(match_dup 2) (const_int 0)])) 11730 (set (match_dup 0) 11731 (compare:CC (match_dup 3) 11732 (const_int 0)))] 11733 "") 11734 11735(define_insn "" 11736 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11737 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 11738 [(match_operand 2 "cc_reg_operand" "y") 11739 (const_int 0)]) 11740 (match_operand:SI 3 "const_int_operand" "n")))] 11741 "" 11742 "* 11743{ 11744 int is_bit = ccr_bit (operands[1], 1); 11745 int put_bit = 31 - (INTVAL (operands[3]) & 31); 11746 int count; 11747 11748 if (is_bit >= put_bit) 11749 count = is_bit - put_bit; 11750 else 11751 count = 32 - (put_bit - is_bit); 11752 11753 operands[4] = GEN_INT (count); 11754 operands[5] = GEN_INT (put_bit); 11755 11756 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; 11757}" 11758 [(set (attr "type") 11759 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) 11760 (const_string "mfcrf") 11761 ] 11762 (const_string "mfcr"))) 11763 (set_attr "length" "8")]) 11764 11765(define_insn "" 11766 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11767 (compare:CC 11768 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 11769 [(match_operand 2 "cc_reg_operand" "y,y") 11770 (const_int 0)]) 11771 (match_operand:SI 3 "const_int_operand" "n,n")) 11772 (const_int 0))) 11773 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") 11774 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 11775 (match_dup 3)))] 11776 "" 11777 "* 11778{ 11779 int is_bit = ccr_bit (operands[1], 1); 11780 int put_bit = 31 - (INTVAL (operands[3]) & 31); 11781 int count; 11782 11783 /* Force split for non-cc0 compare. */ 11784 if (which_alternative == 1) 11785 return \"#\"; 11786 11787 if (is_bit >= put_bit) 11788 count = is_bit - put_bit; 11789 else 11790 count = 32 - (put_bit - is_bit); 11791 11792 operands[5] = GEN_INT (count); 11793 operands[6] = GEN_INT (put_bit); 11794 11795 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; 11796}" 11797 [(set_attr "type" "delayed_compare") 11798 (set_attr "length" "8,16")]) 11799 11800(define_split 11801 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11802 (compare:CC 11803 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 11804 [(match_operand 2 "cc_reg_operand" "") 11805 (const_int 0)]) 11806 (match_operand:SI 3 "const_int_operand" "")) 11807 (const_int 0))) 11808 (set (match_operand:SI 4 "gpc_reg_operand" "") 11809 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 11810 (match_dup 3)))] 11811 "reload_completed" 11812 [(set (match_dup 4) 11813 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 11814 (match_dup 3))) 11815 (set (match_dup 0) 11816 (compare:CC (match_dup 4) 11817 (const_int 0)))] 11818 "") 11819 11820;; There is a 3 cycle delay between consecutive mfcr instructions 11821;; so it is useful to combine 2 scc instructions to use only one mfcr. 11822 11823(define_peephole 11824 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11825 (match_operator:SI 1 "scc_comparison_operator" 11826 [(match_operand 2 "cc_reg_operand" "y") 11827 (const_int 0)])) 11828 (set (match_operand:SI 3 "gpc_reg_operand" "=r") 11829 (match_operator:SI 4 "scc_comparison_operator" 11830 [(match_operand 5 "cc_reg_operand" "y") 11831 (const_int 0)]))] 11832 "REGNO (operands[2]) != REGNO (operands[5])" 11833 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" 11834 [(set_attr "type" "mfcr") 11835 (set_attr "length" "12")]) 11836 11837(define_peephole 11838 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11839 (match_operator:DI 1 "scc_comparison_operator" 11840 [(match_operand 2 "cc_reg_operand" "y") 11841 (const_int 0)])) 11842 (set (match_operand:DI 3 "gpc_reg_operand" "=r") 11843 (match_operator:DI 4 "scc_comparison_operator" 11844 [(match_operand 5 "cc_reg_operand" "y") 11845 (const_int 0)]))] 11846 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" 11847 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" 11848 [(set_attr "type" "mfcr") 11849 (set_attr "length" "12")]) 11850 11851;; There are some scc insns that can be done directly, without a compare. 11852;; These are faster because they don't involve the communications between 11853;; the FXU and branch units. In fact, we will be replacing all of the 11854;; integer scc insns here or in the portable methods in emit_store_flag. 11855;; 11856;; Also support (neg (scc ..)) since that construct is used to replace 11857;; branches, (plus (scc ..) ..) since that construct is common and 11858;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the 11859;; cases where it is no more expensive than (neg (scc ..)). 11860 11861;; Have reload force a constant into a register for the simple insns that 11862;; otherwise won't accept constants. We do this because it is faster than 11863;; the cmp/mfcr sequence we would otherwise generate. 11864 11865(define_mode_attr scc_eq_op2 [(SI "rKLI") 11866 (DI "rKJI")]) 11867 11868(define_insn_and_split "*eq<mode>" 11869 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 11870 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") 11871 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))] 11872 "!TARGET_POWER" 11873 "#" 11874 "!TARGET_POWER" 11875 [(set (match_dup 0) 11876 (clz:GPR (match_dup 3))) 11877 (set (match_dup 0) 11878 (lshiftrt:GPR (match_dup 0) (match_dup 4)))] 11879 { 11880 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) 11881 { 11882 /* Use output operand as intermediate. */ 11883 operands[3] = operands[0]; 11884 11885 if (logical_operand (operands[2], <MODE>mode)) 11886 emit_insn (gen_rtx_SET (VOIDmode, operands[3], 11887 gen_rtx_XOR (<MODE>mode, 11888 operands[1], operands[2]))); 11889 else 11890 emit_insn (gen_rtx_SET (VOIDmode, operands[3], 11891 gen_rtx_PLUS (<MODE>mode, operands[1], 11892 negate_rtx (<MODE>mode, 11893 operands[2])))); 11894 } 11895 else 11896 operands[3] = operands[1]; 11897 11898 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode))); 11899 }) 11900 11901(define_insn_and_split "*eq<mode>_compare" 11902 [(set (match_operand:CC 3 "cc_reg_operand" "=y") 11903 (compare:CC 11904 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r") 11905 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>")) 11906 (const_int 0))) 11907 (set (match_operand:P 0 "gpc_reg_operand" "=r") 11908 (eq:P (match_dup 1) (match_dup 2)))] 11909 "!TARGET_POWER && optimize_size" 11910 "#" 11911 "!TARGET_POWER && optimize_size" 11912 [(set (match_dup 0) 11913 (clz:P (match_dup 4))) 11914 (parallel [(set (match_dup 3) 11915 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5)) 11916 (const_int 0))) 11917 (set (match_dup 0) 11918 (lshiftrt:P (match_dup 0) (match_dup 5)))])] 11919 { 11920 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) 11921 { 11922 /* Use output operand as intermediate. */ 11923 operands[4] = operands[0]; 11924 11925 if (logical_operand (operands[2], <MODE>mode)) 11926 emit_insn (gen_rtx_SET (VOIDmode, operands[4], 11927 gen_rtx_XOR (<MODE>mode, 11928 operands[1], operands[2]))); 11929 else 11930 emit_insn (gen_rtx_SET (VOIDmode, operands[4], 11931 gen_rtx_PLUS (<MODE>mode, operands[1], 11932 negate_rtx (<MODE>mode, 11933 operands[2])))); 11934 } 11935 else 11936 operands[4] = operands[1]; 11937 11938 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode))); 11939 }) 11940 11941(define_insn "*eqsi_power" 11942 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 11943 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 11944 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) 11945 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] 11946 "TARGET_POWER" 11947 "@ 11948 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 11949 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 11950 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 11951 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 11952 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" 11953 [(set_attr "type" "three,two,three,three,three") 11954 (set_attr "length" "12,8,12,12,12")]) 11955 11956;; We have insns of the form shown by the first define_insn below. If 11957;; there is something inside the comparison operation, we must split it. 11958(define_split 11959 [(set (match_operand:SI 0 "gpc_reg_operand" "") 11960 (plus:SI (match_operator 1 "comparison_operator" 11961 [(match_operand:SI 2 "" "") 11962 (match_operand:SI 3 11963 "reg_or_cint_operand" "")]) 11964 (match_operand:SI 4 "gpc_reg_operand" ""))) 11965 (clobber (match_operand:SI 5 "register_operand" ""))] 11966 "! gpc_reg_operand (operands[2], SImode)" 11967 [(set (match_dup 5) (match_dup 2)) 11968 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) 11969 (match_dup 4)))]) 11970 11971(define_insn "*plus_eqsi" 11972 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") 11973 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 11974 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I")) 11975 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] 11976 "TARGET_32BIT" 11977 "@ 11978 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 11979 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 11980 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 11981 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 11982 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" 11983 [(set_attr "type" "three,two,three,three,three") 11984 (set_attr "length" "12,8,12,12,12")]) 11985 11986(define_insn "*compare_plus_eqsi" 11987 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 11988 (compare:CC 11989 (plus:SI 11990 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 11991 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) 11992 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) 11993 (const_int 0))) 11994 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] 11995 "TARGET_32BIT && optimize_size" 11996 "@ 11997 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 11998 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 11999 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 12000 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 12001 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 12002 # 12003 # 12004 # 12005 # 12006 #" 12007 [(set_attr "type" "compare") 12008 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 12009 12010(define_split 12011 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12012 (compare:CC 12013 (plus:SI 12014 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 12015 (match_operand:SI 2 "scc_eq_operand" "")) 12016 (match_operand:SI 3 "gpc_reg_operand" "")) 12017 (const_int 0))) 12018 (clobber (match_scratch:SI 4 ""))] 12019 "TARGET_32BIT && optimize_size && reload_completed" 12020 [(set (match_dup 4) 12021 (plus:SI (eq:SI (match_dup 1) 12022 (match_dup 2)) 12023 (match_dup 3))) 12024 (set (match_dup 0) 12025 (compare:CC (match_dup 4) 12026 (const_int 0)))] 12027 "") 12028 12029(define_insn "*plus_eqsi_compare" 12030 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 12031 (compare:CC 12032 (plus:SI 12033 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 12034 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) 12035 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) 12036 (const_int 0))) 12037 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") 12038 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12039 "TARGET_32BIT && optimize_size" 12040 "@ 12041 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 12042 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 12043 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 12044 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 12045 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 12046 # 12047 # 12048 # 12049 # 12050 #" 12051 [(set_attr "type" "compare") 12052 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 12053 12054(define_split 12055 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12056 (compare:CC 12057 (plus:SI 12058 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 12059 (match_operand:SI 2 "scc_eq_operand" "")) 12060 (match_operand:SI 3 "gpc_reg_operand" "")) 12061 (const_int 0))) 12062 (set (match_operand:SI 0 "gpc_reg_operand" "") 12063 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12064 "TARGET_32BIT && optimize_size && reload_completed" 12065 [(set (match_dup 0) 12066 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12067 (set (match_dup 4) 12068 (compare:CC (match_dup 0) 12069 (const_int 0)))] 12070 "") 12071 12072(define_insn "*neg_eq0<mode>" 12073 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 12074 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r") 12075 (const_int 0))))] 12076 "" 12077 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0" 12078 [(set_attr "type" "two") 12079 (set_attr "length" "8")]) 12080 12081(define_insn_and_split "*neg_eq<mode>" 12082 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 12083 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r") 12084 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))] 12085 "" 12086 "#" 12087 "" 12088 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))] 12089 { 12090 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) 12091 { 12092 /* Use output operand as intermediate. */ 12093 operands[3] = operands[0]; 12094 12095 if (logical_operand (operands[2], <MODE>mode)) 12096 emit_insn (gen_rtx_SET (VOIDmode, operands[3], 12097 gen_rtx_XOR (<MODE>mode, 12098 operands[1], operands[2]))); 12099 else 12100 emit_insn (gen_rtx_SET (VOIDmode, operands[3], 12101 gen_rtx_PLUS (<MODE>mode, operands[1], 12102 negate_rtx (<MODE>mode, 12103 operands[2])))); 12104 } 12105 else 12106 operands[3] = operands[1]; 12107 }) 12108 12109;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, 12110;; since it nabs/sr is just as fast. 12111(define_insn "*ne0si" 12112 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 12113 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 12114 (const_int 31))) 12115 (clobber (match_scratch:SI 2 "=&r"))] 12116 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" 12117 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" 12118 [(set_attr "type" "two") 12119 (set_attr "length" "8")]) 12120 12121(define_insn "*ne0di" 12122 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 12123 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) 12124 (const_int 63))) 12125 (clobber (match_scratch:DI 2 "=&r"))] 12126 "TARGET_64BIT" 12127 "addic %2,%1,-1\;subfe %0,%2,%1" 12128 [(set_attr "type" "two") 12129 (set_attr "length" "8")]) 12130 12131;; This is what (plus (ne X (const_int 0)) Y) looks like. 12132(define_insn "*plus_ne0si" 12133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12134 (plus:SI (lshiftrt:SI 12135 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 12136 (const_int 31)) 12137 (match_operand:SI 2 "gpc_reg_operand" "r"))) 12138 (clobber (match_scratch:SI 3 "=&r"))] 12139 "TARGET_32BIT" 12140 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" 12141 [(set_attr "type" "two") 12142 (set_attr "length" "8")]) 12143 12144(define_insn "*plus_ne0di" 12145 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 12146 (plus:DI (lshiftrt:DI 12147 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) 12148 (const_int 63)) 12149 (match_operand:DI 2 "gpc_reg_operand" "r"))) 12150 (clobber (match_scratch:DI 3 "=&r"))] 12151 "TARGET_64BIT" 12152 "addic %3,%1,-1\;addze %0,%2" 12153 [(set_attr "type" "two") 12154 (set_attr "length" "8")]) 12155 12156(define_insn "*compare_plus_ne0si" 12157 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12158 (compare:CC 12159 (plus:SI (lshiftrt:SI 12160 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) 12161 (const_int 31)) 12162 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 12163 (const_int 0))) 12164 (clobber (match_scratch:SI 3 "=&r,&r")) 12165 (clobber (match_scratch:SI 4 "=X,&r"))] 12166 "TARGET_32BIT" 12167 "@ 12168 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 12169 #" 12170 [(set_attr "type" "compare") 12171 (set_attr "length" "8,12")]) 12172 12173(define_split 12174 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12175 (compare:CC 12176 (plus:SI (lshiftrt:SI 12177 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 12178 (const_int 31)) 12179 (match_operand:SI 2 "gpc_reg_operand" "")) 12180 (const_int 0))) 12181 (clobber (match_scratch:SI 3 "")) 12182 (clobber (match_scratch:SI 4 ""))] 12183 "TARGET_32BIT && reload_completed" 12184 [(parallel [(set (match_dup 3) 12185 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) 12186 (const_int 31)) 12187 (match_dup 2))) 12188 (clobber (match_dup 4))]) 12189 (set (match_dup 0) 12190 (compare:CC (match_dup 3) 12191 (const_int 0)))] 12192 "") 12193 12194(define_insn "*compare_plus_ne0di" 12195 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12196 (compare:CC 12197 (plus:DI (lshiftrt:DI 12198 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) 12199 (const_int 63)) 12200 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 12201 (const_int 0))) 12202 (clobber (match_scratch:DI 3 "=&r,&r"))] 12203 "TARGET_64BIT" 12204 "@ 12205 addic %3,%1,-1\;addze. %3,%2 12206 #" 12207 [(set_attr "type" "compare") 12208 (set_attr "length" "8,12")]) 12209 12210(define_split 12211 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12212 (compare:CC 12213 (plus:DI (lshiftrt:DI 12214 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 12215 (const_int 63)) 12216 (match_operand:DI 2 "gpc_reg_operand" "")) 12217 (const_int 0))) 12218 (clobber (match_scratch:DI 3 ""))] 12219 "TARGET_64BIT && reload_completed" 12220 [(set (match_dup 3) 12221 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) 12222 (const_int 63)) 12223 (match_dup 2))) 12224 (set (match_dup 0) 12225 (compare:CC (match_dup 3) 12226 (const_int 0)))] 12227 "") 12228 12229(define_insn "*plus_ne0si_compare" 12230 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12231 (compare:CC 12232 (plus:SI (lshiftrt:SI 12233 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) 12234 (const_int 31)) 12235 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 12236 (const_int 0))) 12237 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12238 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 12239 (match_dup 2))) 12240 (clobber (match_scratch:SI 3 "=&r,&r"))] 12241 "TARGET_32BIT" 12242 "@ 12243 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 12244 #" 12245 [(set_attr "type" "compare") 12246 (set_attr "length" "8,12")]) 12247 12248(define_split 12249 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12250 (compare:CC 12251 (plus:SI (lshiftrt:SI 12252 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 12253 (const_int 31)) 12254 (match_operand:SI 2 "gpc_reg_operand" "")) 12255 (const_int 0))) 12256 (set (match_operand:SI 0 "gpc_reg_operand" "") 12257 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 12258 (match_dup 2))) 12259 (clobber (match_scratch:SI 3 ""))] 12260 "TARGET_32BIT && reload_completed" 12261 [(parallel [(set (match_dup 0) 12262 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 12263 (match_dup 2))) 12264 (clobber (match_dup 3))]) 12265 (set (match_dup 4) 12266 (compare:CC (match_dup 0) 12267 (const_int 0)))] 12268 "") 12269 12270(define_insn "*plus_ne0di_compare" 12271 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12272 (compare:CC 12273 (plus:DI (lshiftrt:DI 12274 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) 12275 (const_int 63)) 12276 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 12277 (const_int 0))) 12278 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 12279 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) 12280 (match_dup 2))) 12281 (clobber (match_scratch:DI 3 "=&r,&r"))] 12282 "TARGET_64BIT" 12283 "@ 12284 addic %3,%1,-1\;addze. %0,%2 12285 #" 12286 [(set_attr "type" "compare") 12287 (set_attr "length" "8,12")]) 12288 12289(define_split 12290 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12291 (compare:CC 12292 (plus:DI (lshiftrt:DI 12293 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 12294 (const_int 63)) 12295 (match_operand:DI 2 "gpc_reg_operand" "")) 12296 (const_int 0))) 12297 (set (match_operand:DI 0 "gpc_reg_operand" "") 12298 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) 12299 (match_dup 2))) 12300 (clobber (match_scratch:DI 3 ""))] 12301 "TARGET_64BIT && reload_completed" 12302 [(parallel [(set (match_dup 0) 12303 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) 12304 (match_dup 2))) 12305 (clobber (match_dup 3))]) 12306 (set (match_dup 4) 12307 (compare:CC (match_dup 0) 12308 (const_int 0)))] 12309 "") 12310 12311(define_insn "" 12312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12313 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12314 (match_operand:SI 2 "reg_or_short_operand" "r,O"))) 12315 (clobber (match_scratch:SI 3 "=r,X"))] 12316 "TARGET_POWER" 12317 "@ 12318 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 12319 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" 12320 [(set_attr "length" "12")]) 12321 12322(define_insn "" 12323 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12324 (compare:CC 12325 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12326 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) 12327 (const_int 0))) 12328 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 12329 (le:SI (match_dup 1) (match_dup 2))) 12330 (clobber (match_scratch:SI 3 "=r,X,r,X"))] 12331 "TARGET_POWER" 12332 "@ 12333 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 12334 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 12335 # 12336 #" 12337 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") 12338 (set_attr "length" "12,12,16,16")]) 12339 12340(define_split 12341 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12342 (compare:CC 12343 (le:SI (match_operand:SI 1 "gpc_reg_operand" "") 12344 (match_operand:SI 2 "reg_or_short_operand" "")) 12345 (const_int 0))) 12346 (set (match_operand:SI 0 "gpc_reg_operand" "") 12347 (le:SI (match_dup 1) (match_dup 2))) 12348 (clobber (match_scratch:SI 3 ""))] 12349 "TARGET_POWER && reload_completed" 12350 [(parallel [(set (match_dup 0) 12351 (le:SI (match_dup 1) (match_dup 2))) 12352 (clobber (match_dup 3))]) 12353 (set (match_dup 4) 12354 (compare:CC (match_dup 0) 12355 (const_int 0)))] 12356 "") 12357 12358(define_insn "" 12359 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12360 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12361 (match_operand:SI 2 "reg_or_short_operand" "r,O")) 12362 (match_operand:SI 3 "gpc_reg_operand" "r,r")))] 12363 "TARGET_POWER" 12364 "@ 12365 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 12366 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" 12367 [(set_attr "length" "12")]) 12368 12369(define_insn "" 12370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 12371 (compare:CC 12372 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12373 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) 12374 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12375 (const_int 0))) 12376 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 12377 "TARGET_POWER" 12378 "@ 12379 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 12380 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 12381 # 12382 #" 12383 [(set_attr "type" "compare") 12384 (set_attr "length" "12,12,16,16")]) 12385 12386(define_split 12387 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12388 (compare:CC 12389 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") 12390 (match_operand:SI 2 "reg_or_short_operand" "")) 12391 (match_operand:SI 3 "gpc_reg_operand" "")) 12392 (const_int 0))) 12393 (clobber (match_scratch:SI 4 ""))] 12394 "TARGET_POWER && reload_completed" 12395 [(set (match_dup 4) 12396 (plus:SI (le:SI (match_dup 1) (match_dup 2)) 12397 (match_dup 3))) 12398 (set (match_dup 0) 12399 (compare:CC (match_dup 4) 12400 (const_int 0)))] 12401 "") 12402 12403(define_insn "" 12404 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12405 (compare:CC 12406 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12407 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) 12408 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12409 (const_int 0))) 12410 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12411 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12412 "TARGET_POWER" 12413 "@ 12414 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 12415 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 12416 # 12417 #" 12418 [(set_attr "type" "compare") 12419 (set_attr "length" "12,12,16,16")]) 12420 12421(define_split 12422 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12423 (compare:CC 12424 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") 12425 (match_operand:SI 2 "reg_or_short_operand" "")) 12426 (match_operand:SI 3 "gpc_reg_operand" "")) 12427 (const_int 0))) 12428 (set (match_operand:SI 0 "gpc_reg_operand" "") 12429 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12430 "TARGET_POWER && reload_completed" 12431 [(set (match_dup 0) 12432 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12433 (set (match_dup 4) 12434 (compare:CC (match_dup 0) 12435 (const_int 0)))] 12436 "") 12437 12438(define_insn "" 12439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12440 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12441 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] 12442 "TARGET_POWER" 12443 "@ 12444 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 12445 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" 12446 [(set_attr "length" "12")]) 12447 12448(define_insn "*leu<mode>" 12449 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 12450 (leu:P (match_operand:P 1 "gpc_reg_operand" "r") 12451 (match_operand:P 2 "reg_or_short_operand" "rI")))] 12452 "" 12453 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 12454 [(set_attr "type" "three") 12455 (set_attr "length" "12")]) 12456 12457(define_insn "*leu<mode>_compare" 12458 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12459 (compare:CC 12460 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 12461 (match_operand:P 2 "reg_or_short_operand" "rI,rI")) 12462 (const_int 0))) 12463 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 12464 (leu:P (match_dup 1) (match_dup 2)))] 12465 "" 12466 "@ 12467 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 12468 #" 12469 [(set_attr "type" "compare") 12470 (set_attr "length" "12,16")]) 12471 12472(define_split 12473 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12474 (compare:CC 12475 (leu:P (match_operand:P 1 "gpc_reg_operand" "") 12476 (match_operand:P 2 "reg_or_short_operand" "")) 12477 (const_int 0))) 12478 (set (match_operand:P 0 "gpc_reg_operand" "") 12479 (leu:P (match_dup 1) (match_dup 2)))] 12480 "reload_completed" 12481 [(set (match_dup 0) 12482 (leu:P (match_dup 1) (match_dup 2))) 12483 (set (match_dup 3) 12484 (compare:CC (match_dup 0) 12485 (const_int 0)))] 12486 "") 12487 12488(define_insn "*plus_leu<mode>" 12489 [(set (match_operand:P 0 "gpc_reg_operand" "=&r") 12490 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") 12491 (match_operand:P 2 "reg_or_short_operand" "rI")) 12492 (match_operand:P 3 "gpc_reg_operand" "r")))] 12493 "" 12494 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" 12495 [(set_attr "type" "two") 12496 (set_attr "length" "8")]) 12497 12498(define_insn "" 12499 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12500 (compare:CC 12501 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12502 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12503 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12504 (const_int 0))) 12505 (clobber (match_scratch:SI 4 "=&r,&r"))] 12506 "TARGET_32BIT" 12507 "@ 12508 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 12509 #" 12510 [(set_attr "type" "compare") 12511 (set_attr "length" "8,12")]) 12512 12513(define_split 12514 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12515 (compare:CC 12516 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12517 (match_operand:SI 2 "reg_or_short_operand" "")) 12518 (match_operand:SI 3 "gpc_reg_operand" "")) 12519 (const_int 0))) 12520 (clobber (match_scratch:SI 4 ""))] 12521 "TARGET_32BIT && reload_completed" 12522 [(set (match_dup 4) 12523 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) 12524 (match_dup 3))) 12525 (set (match_dup 0) 12526 (compare:CC (match_dup 4) 12527 (const_int 0)))] 12528 "") 12529 12530(define_insn "" 12531 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12532 (compare:CC 12533 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12534 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12535 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12536 (const_int 0))) 12537 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12538 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12539 "TARGET_32BIT" 12540 "@ 12541 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 12542 #" 12543 [(set_attr "type" "compare") 12544 (set_attr "length" "8,12")]) 12545 12546(define_split 12547 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12548 (compare:CC 12549 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12550 (match_operand:SI 2 "reg_or_short_operand" "")) 12551 (match_operand:SI 3 "gpc_reg_operand" "")) 12552 (const_int 0))) 12553 (set (match_operand:SI 0 "gpc_reg_operand" "") 12554 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12555 "TARGET_32BIT && reload_completed" 12556 [(set (match_dup 0) 12557 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12558 (set (match_dup 4) 12559 (compare:CC (match_dup 0) 12560 (const_int 0)))] 12561 "") 12562 12563(define_insn "*neg_leu<mode>" 12564 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 12565 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") 12566 (match_operand:P 2 "reg_or_short_operand" "rI"))))] 12567 "" 12568 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" 12569 [(set_attr "type" "three") 12570 (set_attr "length" "12")]) 12571 12572(define_insn "*and_neg_leu<mode>" 12573 [(set (match_operand:P 0 "gpc_reg_operand" "=&r") 12574 (and:P (neg:P 12575 (leu:P (match_operand:P 1 "gpc_reg_operand" "r") 12576 (match_operand:P 2 "reg_or_short_operand" "rI"))) 12577 (match_operand:P 3 "gpc_reg_operand" "r")))] 12578 "" 12579 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" 12580 [(set_attr "type" "three") 12581 (set_attr "length" "12")]) 12582 12583(define_insn "" 12584 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12585 (compare:CC 12586 (and:SI (neg:SI 12587 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12588 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) 12589 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12590 (const_int 0))) 12591 (clobber (match_scratch:SI 4 "=&r,&r"))] 12592 "TARGET_32BIT" 12593 "@ 12594 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 12595 #" 12596 [(set_attr "type" "compare") 12597 (set_attr "length" "12,16")]) 12598 12599(define_split 12600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12601 (compare:CC 12602 (and:SI (neg:SI 12603 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12604 (match_operand:SI 2 "reg_or_short_operand" ""))) 12605 (match_operand:SI 3 "gpc_reg_operand" "")) 12606 (const_int 0))) 12607 (clobber (match_scratch:SI 4 ""))] 12608 "TARGET_32BIT && reload_completed" 12609 [(set (match_dup 4) 12610 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) 12611 (match_dup 3))) 12612 (set (match_dup 0) 12613 (compare:CC (match_dup 4) 12614 (const_int 0)))] 12615 "") 12616 12617(define_insn "" 12618 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12619 (compare:CC 12620 (and:SI (neg:SI 12621 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12622 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) 12623 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12624 (const_int 0))) 12625 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12626 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 12627 "TARGET_32BIT" 12628 "@ 12629 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 12630 #" 12631 [(set_attr "type" "compare") 12632 (set_attr "length" "12,16")]) 12633 12634(define_split 12635 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12636 (compare:CC 12637 (and:SI (neg:SI 12638 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12639 (match_operand:SI 2 "reg_or_short_operand" ""))) 12640 (match_operand:SI 3 "gpc_reg_operand" "")) 12641 (const_int 0))) 12642 (set (match_operand:SI 0 "gpc_reg_operand" "") 12643 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 12644 "TARGET_32BIT && reload_completed" 12645 [(set (match_dup 0) 12646 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) 12647 (match_dup 3))) 12648 (set (match_dup 4) 12649 (compare:CC (match_dup 0) 12650 (const_int 0)))] 12651 "") 12652 12653(define_insn "" 12654 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12655 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12656 (match_operand:SI 2 "reg_or_short_operand" "rI")))] 12657 "TARGET_POWER" 12658 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" 12659 [(set_attr "length" "12")]) 12660 12661(define_insn "" 12662 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12663 (compare:CC 12664 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12665 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12666 (const_int 0))) 12667 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12668 (lt:SI (match_dup 1) (match_dup 2)))] 12669 "TARGET_POWER" 12670 "@ 12671 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 12672 #" 12673 [(set_attr "type" "delayed_compare") 12674 (set_attr "length" "12,16")]) 12675 12676(define_split 12677 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12678 (compare:CC 12679 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12680 (match_operand:SI 2 "reg_or_short_operand" "")) 12681 (const_int 0))) 12682 (set (match_operand:SI 0 "gpc_reg_operand" "") 12683 (lt:SI (match_dup 1) (match_dup 2)))] 12684 "TARGET_POWER && reload_completed" 12685 [(set (match_dup 0) 12686 (lt:SI (match_dup 1) (match_dup 2))) 12687 (set (match_dup 3) 12688 (compare:CC (match_dup 0) 12689 (const_int 0)))] 12690 "") 12691 12692(define_insn "" 12693 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 12694 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12695 (match_operand:SI 2 "reg_or_short_operand" "rI")) 12696 (match_operand:SI 3 "gpc_reg_operand" "r")))] 12697 "TARGET_POWER" 12698 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" 12699 [(set_attr "length" "12")]) 12700 12701(define_insn "" 12702 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12703 (compare:CC 12704 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12705 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12706 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12707 (const_int 0))) 12708 (clobber (match_scratch:SI 4 "=&r,&r"))] 12709 "TARGET_POWER" 12710 "@ 12711 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 12712 #" 12713 [(set_attr "type" "compare") 12714 (set_attr "length" "12,16")]) 12715 12716(define_split 12717 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12718 (compare:CC 12719 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12720 (match_operand:SI 2 "reg_or_short_operand" "")) 12721 (match_operand:SI 3 "gpc_reg_operand" "")) 12722 (const_int 0))) 12723 (clobber (match_scratch:SI 4 ""))] 12724 "TARGET_POWER && reload_completed" 12725 [(set (match_dup 4) 12726 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) 12727 (match_dup 3))) 12728 (set (match_dup 0) 12729 (compare:CC (match_dup 4) 12730 (const_int 0)))] 12731 "") 12732 12733(define_insn "" 12734 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12735 (compare:CC 12736 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12737 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12738 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12739 (const_int 0))) 12740 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12741 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12742 "TARGET_POWER" 12743 "@ 12744 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 12745 #" 12746 [(set_attr "type" "compare") 12747 (set_attr "length" "12,16")]) 12748 12749(define_split 12750 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12751 (compare:CC 12752 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12753 (match_operand:SI 2 "reg_or_short_operand" "")) 12754 (match_operand:SI 3 "gpc_reg_operand" "")) 12755 (const_int 0))) 12756 (set (match_operand:SI 0 "gpc_reg_operand" "") 12757 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12758 "TARGET_POWER && reload_completed" 12759 [(set (match_dup 0) 12760 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12761 (set (match_dup 4) 12762 (compare:CC (match_dup 0) 12763 (const_int 0)))] 12764 "") 12765 12766(define_insn "" 12767 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12768 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12769 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 12770 "TARGET_POWER" 12771 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" 12772 [(set_attr "length" "12")]) 12773 12774(define_insn_and_split "*ltu<mode>" 12775 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") 12776 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 12777 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))] 12778 "" 12779 "#" 12780 "" 12781 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) 12782 (set (match_dup 0) (neg:P (match_dup 0)))] 12783 "") 12784 12785(define_insn_and_split "*ltu<mode>_compare" 12786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 12787 (compare:CC 12788 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") 12789 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) 12790 (const_int 0))) 12791 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") 12792 (ltu:P (match_dup 1) (match_dup 2)))] 12793 "" 12794 "#" 12795 "" 12796 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) 12797 (parallel [(set (match_dup 3) 12798 (compare:CC (neg:P (match_dup 0)) (const_int 0))) 12799 (set (match_dup 0) (neg:P (match_dup 0)))])] 12800 "") 12801 12802(define_insn_and_split "*plus_ltu<mode>" 12803 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r") 12804 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 12805 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")) 12806 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))] 12807 "" 12808 "#" 12809 "&& !reg_overlap_mentioned_p (operands[0], operands[3])" 12810 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) 12811 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] 12812 "") 12813 12814(define_insn_and_split "*plus_ltu<mode>_compare" 12815 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12816 (compare:CC 12817 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") 12818 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) 12819 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r")) 12820 (const_int 0))) 12821 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12822 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))] 12823 "" 12824 "#" 12825 "&& !reg_overlap_mentioned_p (operands[0], operands[3])" 12826 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) 12827 (parallel [(set (match_dup 4) 12828 (compare:CC (minus:P (match_dup 3) (match_dup 0)) 12829 (const_int 0))) 12830 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])] 12831 "") 12832 12833(define_insn "*neg_ltu<mode>" 12834 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") 12835 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 12836 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))] 12837 "" 12838 "@ 12839 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 12840 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" 12841 [(set_attr "type" "two") 12842 (set_attr "length" "8")]) 12843 12844(define_insn "" 12845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12846 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12847 (match_operand:SI 2 "reg_or_short_operand" "rI"))) 12848 (clobber (match_scratch:SI 3 "=r"))] 12849 "TARGET_POWER" 12850 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" 12851 [(set_attr "length" "12")]) 12852 12853(define_insn "" 12854 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12855 (compare:CC 12856 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12857 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12858 (const_int 0))) 12859 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12860 (ge:SI (match_dup 1) (match_dup 2))) 12861 (clobber (match_scratch:SI 3 "=r,r"))] 12862 "TARGET_POWER" 12863 "@ 12864 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 12865 #" 12866 [(set_attr "type" "compare") 12867 (set_attr "length" "12,16")]) 12868 12869(define_split 12870 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12871 (compare:CC 12872 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") 12873 (match_operand:SI 2 "reg_or_short_operand" "")) 12874 (const_int 0))) 12875 (set (match_operand:SI 0 "gpc_reg_operand" "") 12876 (ge:SI (match_dup 1) (match_dup 2))) 12877 (clobber (match_scratch:SI 3 ""))] 12878 "TARGET_POWER && reload_completed" 12879 [(parallel [(set (match_dup 0) 12880 (ge:SI (match_dup 1) (match_dup 2))) 12881 (clobber (match_dup 3))]) 12882 (set (match_dup 4) 12883 (compare:CC (match_dup 0) 12884 (const_int 0)))] 12885 "") 12886 12887(define_insn "" 12888 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 12889 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12890 (match_operand:SI 2 "reg_or_short_operand" "rI")) 12891 (match_operand:SI 3 "gpc_reg_operand" "r")))] 12892 "TARGET_POWER" 12893 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" 12894 [(set_attr "length" "12")]) 12895 12896(define_insn "" 12897 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12898 (compare:CC 12899 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12900 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12901 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12902 (const_int 0))) 12903 (clobber (match_scratch:SI 4 "=&r,&r"))] 12904 "TARGET_POWER" 12905 "@ 12906 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 12907 #" 12908 [(set_attr "type" "compare") 12909 (set_attr "length" "12,16")]) 12910 12911(define_split 12912 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12913 (compare:CC 12914 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") 12915 (match_operand:SI 2 "reg_or_short_operand" "")) 12916 (match_operand:SI 3 "gpc_reg_operand" "")) 12917 (const_int 0))) 12918 (clobber (match_scratch:SI 4 ""))] 12919 "TARGET_POWER && reload_completed" 12920 [(set (match_dup 4) 12921 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) 12922 (match_dup 3))) 12923 (set (match_dup 0) 12924 (compare:CC (match_dup 4) 12925 (const_int 0)))] 12926 "") 12927 12928(define_insn "" 12929 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12930 (compare:CC 12931 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12932 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12933 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12934 (const_int 0))) 12935 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12936 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12937 "TARGET_POWER" 12938 "@ 12939 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 12940 #" 12941 [(set_attr "type" "compare") 12942 (set_attr "length" "12,16")]) 12943 12944(define_split 12945 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12946 (compare:CC 12947 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") 12948 (match_operand:SI 2 "reg_or_short_operand" "")) 12949 (match_operand:SI 3 "gpc_reg_operand" "")) 12950 (const_int 0))) 12951 (set (match_operand:SI 0 "gpc_reg_operand" "") 12952 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12953 "TARGET_POWER && reload_completed" 12954 [(set (match_dup 0) 12955 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12956 (set (match_dup 4) 12957 (compare:CC (match_dup 0) 12958 (const_int 0)))] 12959 "") 12960 12961(define_insn "" 12962 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12963 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12964 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 12965 "TARGET_POWER" 12966 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 12967 [(set_attr "length" "12")]) 12968 12969(define_insn "*geu<mode>" 12970 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") 12971 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 12972 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))] 12973 "" 12974 "@ 12975 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 12976 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 12977 [(set_attr "type" "three") 12978 (set_attr "length" "12")]) 12979 12980(define_insn "*geu<mode>_compare" 12981 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 12982 (compare:CC 12983 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") 12984 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) 12985 (const_int 0))) 12986 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") 12987 (geu:P (match_dup 1) (match_dup 2)))] 12988 "" 12989 "@ 12990 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 12991 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 12992 # 12993 #" 12994 [(set_attr "type" "compare") 12995 (set_attr "length" "12,12,16,16")]) 12996 12997(define_split 12998 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12999 (compare:CC 13000 (geu:P (match_operand:P 1 "gpc_reg_operand" "") 13001 (match_operand:P 2 "reg_or_neg_short_operand" "")) 13002 (const_int 0))) 13003 (set (match_operand:P 0 "gpc_reg_operand" "") 13004 (geu:P (match_dup 1) (match_dup 2)))] 13005 "reload_completed" 13006 [(set (match_dup 0) 13007 (geu:P (match_dup 1) (match_dup 2))) 13008 (set (match_dup 3) 13009 (compare:CC (match_dup 0) 13010 (const_int 0)))] 13011 "") 13012 13013(define_insn "*plus_geu<mode>" 13014 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r") 13015 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 13016 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")) 13017 (match_operand:P 3 "gpc_reg_operand" "r,r")))] 13018 "" 13019 "@ 13020 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 13021 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" 13022 [(set_attr "type" "two") 13023 (set_attr "length" "8")]) 13024 13025(define_insn "" 13026 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 13027 (compare:CC 13028 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 13029 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 13030 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 13031 (const_int 0))) 13032 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 13033 "TARGET_32BIT" 13034 "@ 13035 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 13036 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 13037 # 13038 #" 13039 [(set_attr "type" "compare") 13040 (set_attr "length" "8,8,12,12")]) 13041 13042(define_split 13043 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13044 (compare:CC 13045 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 13046 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 13047 (match_operand:SI 3 "gpc_reg_operand" "")) 13048 (const_int 0))) 13049 (clobber (match_scratch:SI 4 ""))] 13050 "TARGET_32BIT && reload_completed" 13051 [(set (match_dup 4) 13052 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) 13053 (match_dup 3))) 13054 (set (match_dup 0) 13055 (compare:CC (match_dup 4) 13056 (const_int 0)))] 13057 "") 13058 13059(define_insn "" 13060 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 13061 (compare:CC 13062 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 13063 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 13064 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 13065 (const_int 0))) 13066 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 13067 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13068 "TARGET_32BIT" 13069 "@ 13070 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 13071 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 13072 # 13073 #" 13074 [(set_attr "type" "compare") 13075 (set_attr "length" "8,8,12,12")]) 13076 13077(define_split 13078 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 13079 (compare:CC 13080 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 13081 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 13082 (match_operand:SI 3 "gpc_reg_operand" "")) 13083 (const_int 0))) 13084 (set (match_operand:SI 0 "gpc_reg_operand" "") 13085 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13086 "TARGET_32BIT && reload_completed" 13087 [(set (match_dup 0) 13088 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 13089 (set (match_dup 4) 13090 (compare:CC (match_dup 0) 13091 (const_int 0)))] 13092 "") 13093 13094(define_insn "*neg_geu<mode>" 13095 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") 13096 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 13097 (match_operand:P 2 "reg_or_short_operand" "r,I"))))] 13098 "" 13099 "@ 13100 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 13101 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" 13102 [(set_attr "type" "three") 13103 (set_attr "length" "12")]) 13104 13105(define_insn "*and_neg_geu<mode>" 13106 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r") 13107 (and:P (neg:P 13108 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 13109 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))) 13110 (match_operand:P 3 "gpc_reg_operand" "r,r")))] 13111 "" 13112 "@ 13113 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 13114 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" 13115 [(set_attr "type" "three") 13116 (set_attr "length" "12")]) 13117 13118(define_insn "" 13119 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 13120 (compare:CC 13121 (and:SI (neg:SI 13122 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 13123 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) 13124 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 13125 (const_int 0))) 13126 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 13127 "TARGET_32BIT" 13128 "@ 13129 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 13130 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 13131 # 13132 #" 13133 [(set_attr "type" "compare") 13134 (set_attr "length" "12,12,16,16")]) 13135 13136(define_split 13137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13138 (compare:CC 13139 (and:SI (neg:SI 13140 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 13141 (match_operand:SI 2 "reg_or_neg_short_operand" ""))) 13142 (match_operand:SI 3 "gpc_reg_operand" "")) 13143 (const_int 0))) 13144 (clobber (match_scratch:SI 4 ""))] 13145 "TARGET_32BIT && reload_completed" 13146 [(set (match_dup 4) 13147 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) 13148 (match_dup 3))) 13149 (set (match_dup 0) 13150 (compare:CC (match_dup 4) 13151 (const_int 0)))] 13152 "") 13153 13154(define_insn "" 13155 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 13156 (compare:CC 13157 (and:SI (neg:SI 13158 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 13159 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) 13160 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 13161 (const_int 0))) 13162 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 13163 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 13164 "TARGET_32BIT" 13165 "@ 13166 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 13167 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 13168 # 13169 #" 13170 [(set_attr "type" "compare") 13171 (set_attr "length" "12,12,16,16")]) 13172 13173(define_split 13174 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 13175 (compare:CC 13176 (and:SI (neg:SI 13177 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 13178 (match_operand:SI 2 "reg_or_neg_short_operand" ""))) 13179 (match_operand:SI 3 "gpc_reg_operand" "")) 13180 (const_int 0))) 13181 (set (match_operand:SI 0 "gpc_reg_operand" "") 13182 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 13183 "TARGET_32BIT && reload_completed" 13184 [(set (match_dup 0) 13185 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 13186 (set (match_dup 4) 13187 (compare:CC (match_dup 0) 13188 (const_int 0)))] 13189 "") 13190 13191(define_insn "" 13192 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13193 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13194 (match_operand:SI 2 "reg_or_short_operand" "r")))] 13195 "TARGET_POWER" 13196 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" 13197 [(set_attr "length" "12")]) 13198 13199(define_insn "" 13200 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13201 (compare:CC 13202 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13203 (match_operand:SI 2 "reg_or_short_operand" "r,r")) 13204 (const_int 0))) 13205 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 13206 (gt:SI (match_dup 1) (match_dup 2)))] 13207 "TARGET_POWER" 13208 "@ 13209 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 13210 #" 13211 [(set_attr "type" "delayed_compare") 13212 (set_attr "length" "12,16")]) 13213 13214(define_split 13215 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 13216 (compare:CC 13217 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13218 (match_operand:SI 2 "reg_or_short_operand" "")) 13219 (const_int 0))) 13220 (set (match_operand:SI 0 "gpc_reg_operand" "") 13221 (gt:SI (match_dup 1) (match_dup 2)))] 13222 "TARGET_POWER && reload_completed" 13223 [(set (match_dup 0) 13224 (gt:SI (match_dup 1) (match_dup 2))) 13225 (set (match_dup 3) 13226 (compare:CC (match_dup 0) 13227 (const_int 0)))] 13228 "") 13229 13230(define_insn "*plus_gt0<mode>" 13231 [(set (match_operand:P 0 "gpc_reg_operand" "=&r") 13232 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r") 13233 (const_int 0)) 13234 (match_operand:P 2 "gpc_reg_operand" "r")))] 13235 "" 13236 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" 13237 [(set_attr "type" "three") 13238 (set_attr "length" "12")]) 13239 13240(define_insn "" 13241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13242 (compare:CC 13243 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13244 (const_int 0)) 13245 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 13246 (const_int 0))) 13247 (clobber (match_scratch:SI 3 "=&r,&r"))] 13248 "TARGET_32BIT" 13249 "@ 13250 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 13251 #" 13252 [(set_attr "type" "compare") 13253 (set_attr "length" "12,16")]) 13254 13255(define_split 13256 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13257 (compare:CC 13258 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13259 (const_int 0)) 13260 (match_operand:SI 2 "gpc_reg_operand" "")) 13261 (const_int 0))) 13262 (clobber (match_scratch:SI 3 ""))] 13263 "TARGET_32BIT && reload_completed" 13264 [(set (match_dup 3) 13265 (plus:SI (gt:SI (match_dup 1) (const_int 0)) 13266 (match_dup 2))) 13267 (set (match_dup 0) 13268 (compare:CC (match_dup 3) 13269 (const_int 0)))] 13270 "") 13271 13272(define_insn "" 13273 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13274 (compare:CC 13275 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 13276 (const_int 0)) 13277 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 13278 (const_int 0))) 13279 (clobber (match_scratch:DI 3 "=&r,&r"))] 13280 "TARGET_64BIT" 13281 "@ 13282 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 13283 #" 13284 [(set_attr "type" "compare") 13285 (set_attr "length" "12,16")]) 13286 13287(define_split 13288 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13289 (compare:CC 13290 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 13291 (const_int 0)) 13292 (match_operand:DI 2 "gpc_reg_operand" "")) 13293 (const_int 0))) 13294 (clobber (match_scratch:DI 3 ""))] 13295 "TARGET_64BIT && reload_completed" 13296 [(set (match_dup 3) 13297 (plus:DI (gt:DI (match_dup 1) (const_int 0)) 13298 (match_dup 2))) 13299 (set (match_dup 0) 13300 (compare:CC (match_dup 3) 13301 (const_int 0)))] 13302 "") 13303 13304(define_insn "" 13305 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13306 (compare:CC 13307 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13308 (const_int 0)) 13309 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 13310 (const_int 0))) 13311 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 13312 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] 13313 "TARGET_32BIT" 13314 "@ 13315 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 13316 #" 13317 [(set_attr "type" "compare") 13318 (set_attr "length" "12,16")]) 13319 13320(define_split 13321 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 13322 (compare:CC 13323 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13324 (const_int 0)) 13325 (match_operand:SI 2 "gpc_reg_operand" "")) 13326 (const_int 0))) 13327 (set (match_operand:SI 0 "gpc_reg_operand" "") 13328 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] 13329 "TARGET_32BIT && reload_completed" 13330 [(set (match_dup 0) 13331 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) 13332 (set (match_dup 3) 13333 (compare:CC (match_dup 0) 13334 (const_int 0)))] 13335 "") 13336 13337(define_insn "" 13338 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13339 (compare:CC 13340 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 13341 (const_int 0)) 13342 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 13343 (const_int 0))) 13344 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") 13345 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] 13346 "TARGET_64BIT" 13347 "@ 13348 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 13349 #" 13350 [(set_attr "type" "compare") 13351 (set_attr "length" "12,16")]) 13352 13353(define_split 13354 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 13355 (compare:CC 13356 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 13357 (const_int 0)) 13358 (match_operand:DI 2 "gpc_reg_operand" "")) 13359 (const_int 0))) 13360 (set (match_operand:DI 0 "gpc_reg_operand" "") 13361 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] 13362 "TARGET_64BIT && reload_completed" 13363 [(set (match_dup 0) 13364 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) 13365 (set (match_dup 3) 13366 (compare:CC (match_dup 0) 13367 (const_int 0)))] 13368 "") 13369 13370(define_insn "" 13371 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 13372 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13373 (match_operand:SI 2 "reg_or_short_operand" "r")) 13374 (match_operand:SI 3 "gpc_reg_operand" "r")))] 13375 "TARGET_POWER" 13376 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" 13377 [(set_attr "length" "12")]) 13378 13379(define_insn "" 13380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13381 (compare:CC 13382 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13383 (match_operand:SI 2 "reg_or_short_operand" "r,r")) 13384 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 13385 (const_int 0))) 13386 (clobber (match_scratch:SI 4 "=&r,&r"))] 13387 "TARGET_POWER" 13388 "@ 13389 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 13390 #" 13391 [(set_attr "type" "compare") 13392 (set_attr "length" "12,16")]) 13393 13394(define_split 13395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13396 (compare:CC 13397 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13398 (match_operand:SI 2 "reg_or_short_operand" "")) 13399 (match_operand:SI 3 "gpc_reg_operand" "")) 13400 (const_int 0))) 13401 (clobber (match_scratch:SI 4 ""))] 13402 "TARGET_POWER && reload_completed" 13403 [(set (match_dup 4) 13404 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 13405 (set (match_dup 0) 13406 (compare:CC (match_dup 4) 13407 (const_int 0)))] 13408 "") 13409 13410(define_insn "" 13411 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 13412 (compare:CC 13413 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13414 (match_operand:SI 2 "reg_or_short_operand" "r,r")) 13415 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 13416 (const_int 0))) 13417 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 13418 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13419 "TARGET_POWER" 13420 "@ 13421 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 13422 #" 13423 [(set_attr "type" "compare") 13424 (set_attr "length" "12,16")]) 13425 13426(define_split 13427 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 13428 (compare:CC 13429 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13430 (match_operand:SI 2 "reg_or_short_operand" "")) 13431 (match_operand:SI 3 "gpc_reg_operand" "")) 13432 (const_int 0))) 13433 (set (match_operand:SI 0 "gpc_reg_operand" "") 13434 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13435 "TARGET_POWER && reload_completed" 13436 [(set (match_dup 0) 13437 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 13438 (set (match_dup 4) 13439 (compare:CC (match_dup 0) 13440 (const_int 0)))] 13441 "") 13442 13443(define_insn "" 13444 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13445 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13446 (match_operand:SI 2 "reg_or_short_operand" "r"))))] 13447 "TARGET_POWER" 13448 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" 13449 [(set_attr "length" "12")]) 13450 13451(define_insn_and_split "*gtu<mode>" 13452 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 13453 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") 13454 (match_operand:P 2 "reg_or_short_operand" "rI")))] 13455 "" 13456 "#" 13457 "" 13458 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) 13459 (set (match_dup 0) (neg:P (match_dup 0)))] 13460 "") 13461 13462(define_insn_and_split "*gtu<mode>_compare" 13463 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13464 (compare:CC 13465 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 13466 (match_operand:P 2 "reg_or_short_operand" "rI,rI")) 13467 (const_int 0))) 13468 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 13469 (gtu:P (match_dup 1) (match_dup 2)))] 13470 "" 13471 "#" 13472 "" 13473 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) 13474 (parallel [(set (match_dup 3) 13475 (compare:CC (neg:P (match_dup 0)) (const_int 0))) 13476 (set (match_dup 0) (neg:P (match_dup 0)))])] 13477 "") 13478 13479(define_insn_and_split "*plus_gtu<mode>" 13480 [(set (match_operand:P 0 "gpc_reg_operand" "=&r") 13481 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") 13482 (match_operand:P 2 "reg_or_short_operand" "rI")) 13483 (match_operand:P 3 "reg_or_short_operand" "rI")))] 13484 "" 13485 "#" 13486 "&& !reg_overlap_mentioned_p (operands[0], operands[3])" 13487 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) 13488 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] 13489 "") 13490 13491(define_insn_and_split "*plus_gtu<mode>_compare" 13492 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 13493 (compare:CC 13494 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") 13495 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r")) 13496 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r")) 13497 (const_int 0))) 13498 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r") 13499 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))] 13500 "" 13501 "#" 13502 "&& !reg_overlap_mentioned_p (operands[0], operands[3])" 13503 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) 13504 (parallel [(set (match_dup 4) 13505 (compare:CC (minus:P (match_dup 3) (match_dup 0)) 13506 (const_int 0))) 13507 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])] 13508 "") 13509 13510(define_insn "*neg_gtu<mode>" 13511 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 13512 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") 13513 (match_operand:P 2 "reg_or_short_operand" "rI"))))] 13514 "" 13515 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" 13516 [(set_attr "type" "two") 13517 (set_attr "length" "8")]) 13518 13519 13520;; Define both directions of branch and return. If we need a reload 13521;; register, we'd rather use CR0 since it is much easier to copy a 13522;; register CC value to there. 13523 13524(define_insn "" 13525 [(set (pc) 13526 (if_then_else (match_operator 1 "branch_comparison_operator" 13527 [(match_operand 2 13528 "cc_reg_operand" "y") 13529 (const_int 0)]) 13530 (label_ref (match_operand 0 "" "")) 13531 (pc)))] 13532 "" 13533 "* 13534{ 13535 return output_cbranch (operands[1], \"%l0\", 0, insn); 13536}" 13537 [(set_attr "type" "branch")]) 13538 13539(define_insn "" 13540 [(set (pc) 13541 (if_then_else (match_operator 0 "branch_comparison_operator" 13542 [(match_operand 1 13543 "cc_reg_operand" "y") 13544 (const_int 0)]) 13545 (return) 13546 (pc)))] 13547 "direct_return ()" 13548 "* 13549{ 13550 return output_cbranch (operands[0], NULL, 0, insn); 13551}" 13552 [(set_attr "type" "jmpreg") 13553 (set_attr "length" "4")]) 13554 13555(define_insn "" 13556 [(set (pc) 13557 (if_then_else (match_operator 1 "branch_comparison_operator" 13558 [(match_operand 2 13559 "cc_reg_operand" "y") 13560 (const_int 0)]) 13561 (pc) 13562 (label_ref (match_operand 0 "" ""))))] 13563 "" 13564 "* 13565{ 13566 return output_cbranch (operands[1], \"%l0\", 1, insn); 13567}" 13568 [(set_attr "type" "branch")]) 13569 13570(define_insn "" 13571 [(set (pc) 13572 (if_then_else (match_operator 0 "branch_comparison_operator" 13573 [(match_operand 1 13574 "cc_reg_operand" "y") 13575 (const_int 0)]) 13576 (pc) 13577 (return)))] 13578 "direct_return ()" 13579 "* 13580{ 13581 return output_cbranch (operands[0], NULL, 1, insn); 13582}" 13583 [(set_attr "type" "jmpreg") 13584 (set_attr "length" "4")]) 13585 13586;; Logic on condition register values. 13587 13588; This pattern matches things like 13589; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) 13590; (eq:SI (reg:CCFP 68) (const_int 0))) 13591; (const_int 1))) 13592; which are generated by the branch logic. 13593; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) 13594 13595(define_insn "*cceq_ior_compare" 13596 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") 13597 (compare:CCEQ (match_operator:SI 1 "boolean_operator" 13598 [(match_operator:SI 2 13599 "branch_positive_comparison_operator" 13600 [(match_operand 3 13601 "cc_reg_operand" "y,y") 13602 (const_int 0)]) 13603 (match_operator:SI 4 13604 "branch_positive_comparison_operator" 13605 [(match_operand 5 13606 "cc_reg_operand" "0,y") 13607 (const_int 0)])]) 13608 (const_int 1)))] 13609 "" 13610 "cr%q1 %E0,%j2,%j4" 13611 [(set_attr "type" "cr_logical,delayed_cr")]) 13612 13613; Why is the constant -1 here, but 1 in the previous pattern? 13614; Because ~1 has all but the low bit set. 13615(define_insn "" 13616 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") 13617 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" 13618 [(not:SI (match_operator:SI 2 13619 "branch_positive_comparison_operator" 13620 [(match_operand 3 13621 "cc_reg_operand" "y,y") 13622 (const_int 0)])) 13623 (match_operator:SI 4 13624 "branch_positive_comparison_operator" 13625 [(match_operand 5 13626 "cc_reg_operand" "0,y") 13627 (const_int 0)])]) 13628 (const_int -1)))] 13629 "" 13630 "cr%q1 %E0,%j2,%j4" 13631 [(set_attr "type" "cr_logical,delayed_cr")]) 13632 13633(define_insn "*cceq_rev_compare" 13634 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") 13635 (compare:CCEQ (match_operator:SI 1 13636 "branch_positive_comparison_operator" 13637 [(match_operand 2 13638 "cc_reg_operand" "0,y") 13639 (const_int 0)]) 13640 (const_int 0)))] 13641 "" 13642 "{crnor %E0,%j1,%j1|crnot %E0,%j1}" 13643 [(set_attr "type" "cr_logical,delayed_cr")]) 13644 13645;; If we are comparing the result of two comparisons, this can be done 13646;; using creqv or crxor. 13647 13648(define_insn_and_split "" 13649 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 13650 (compare:CCEQ (match_operator 1 "branch_comparison_operator" 13651 [(match_operand 2 "cc_reg_operand" "y") 13652 (const_int 0)]) 13653 (match_operator 3 "branch_comparison_operator" 13654 [(match_operand 4 "cc_reg_operand" "y") 13655 (const_int 0)])))] 13656 "" 13657 "#" 13658 "" 13659 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) 13660 (match_dup 5)))] 13661 " 13662{ 13663 int positive_1, positive_2; 13664 13665 positive_1 = branch_positive_comparison_operator (operands[1], 13666 GET_MODE (operands[1])); 13667 positive_2 = branch_positive_comparison_operator (operands[3], 13668 GET_MODE (operands[3])); 13669 13670 if (! positive_1) 13671 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), 13672 GET_CODE (operands[1])), 13673 SImode, 13674 operands[2], const0_rtx); 13675 else if (GET_MODE (operands[1]) != SImode) 13676 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, 13677 operands[2], const0_rtx); 13678 13679 if (! positive_2) 13680 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), 13681 GET_CODE (operands[3])), 13682 SImode, 13683 operands[4], const0_rtx); 13684 else if (GET_MODE (operands[3]) != SImode) 13685 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 13686 operands[4], const0_rtx); 13687 13688 if (positive_1 == positive_2) 13689 { 13690 operands[1] = gen_rtx_NOT (SImode, operands[1]); 13691 operands[5] = constm1_rtx; 13692 } 13693 else 13694 { 13695 operands[5] = const1_rtx; 13696 } 13697}") 13698 13699;; Unconditional branch and return. 13700 13701(define_insn "jump" 13702 [(set (pc) 13703 (label_ref (match_operand 0 "" "")))] 13704 "" 13705 "b %l0" 13706 [(set_attr "type" "branch")]) 13707 13708(define_insn "return" 13709 [(return)] 13710 "direct_return ()" 13711 "{br|blr}" 13712 [(set_attr "type" "jmpreg")]) 13713 13714(define_expand "indirect_jump" 13715 [(set (pc) (match_operand 0 "register_operand" ""))]) 13716 13717(define_insn "*indirect_jump<mode>" 13718 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))] 13719 "" 13720 "@ 13721 bctr 13722 {br|blr}" 13723 [(set_attr "type" "jmpreg")]) 13724 13725;; Table jump for switch statements: 13726(define_expand "tablejump" 13727 [(use (match_operand 0 "" "")) 13728 (use (label_ref (match_operand 1 "" "")))] 13729 "" 13730 " 13731{ 13732 if (TARGET_32BIT) 13733 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); 13734 else 13735 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); 13736 DONE; 13737}") 13738 13739(define_expand "tablejumpsi" 13740 [(set (match_dup 3) 13741 (plus:SI (match_operand:SI 0 "" "") 13742 (match_dup 2))) 13743 (parallel [(set (pc) (match_dup 3)) 13744 (use (label_ref (match_operand 1 "" "")))])] 13745 "TARGET_32BIT" 13746 " 13747{ operands[0] = force_reg (SImode, operands[0]); 13748 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); 13749 operands[3] = gen_reg_rtx (SImode); 13750}") 13751 13752(define_expand "tablejumpdi" 13753 [(set (match_dup 4) 13754 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) 13755 (set (match_dup 3) 13756 (plus:DI (match_dup 4) 13757 (match_dup 2))) 13758 (parallel [(set (pc) (match_dup 3)) 13759 (use (label_ref (match_operand 1 "" "")))])] 13760 "TARGET_64BIT" 13761 " 13762{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); 13763 operands[3] = gen_reg_rtx (DImode); 13764 operands[4] = gen_reg_rtx (DImode); 13765}") 13766 13767(define_insn "*tablejump<mode>_internal1" 13768 [(set (pc) 13769 (match_operand:P 0 "register_operand" "c,*l")) 13770 (use (label_ref (match_operand 1 "" "")))] 13771 "" 13772 "@ 13773 bctr 13774 {br|blr}" 13775 [(set_attr "type" "jmpreg")]) 13776 13777(define_insn "nop" 13778 [(const_int 0)] 13779 "" 13780 "{cror 0,0,0|nop}") 13781 13782;; Define the subtract-one-and-jump insns, starting with the template 13783;; so loop.c knows what to generate. 13784 13785(define_expand "doloop_end" 13786 [(use (match_operand 0 "" "")) ; loop pseudo 13787 (use (match_operand 1 "" "")) ; iterations; zero if unknown 13788 (use (match_operand 2 "" "")) ; max iterations 13789 (use (match_operand 3 "" "")) ; loop level 13790 (use (match_operand 4 "" ""))] ; label 13791 "" 13792 " 13793{ 13794 /* Only use this on innermost loops. */ 13795 if (INTVAL (operands[3]) > 1) 13796 FAIL; 13797 if (TARGET_64BIT) 13798 { 13799 if (GET_MODE (operands[0]) != DImode) 13800 FAIL; 13801 emit_jump_insn (gen_ctrdi (operands[0], operands[4])); 13802 } 13803 else 13804 { 13805 if (GET_MODE (operands[0]) != SImode) 13806 FAIL; 13807 emit_jump_insn (gen_ctrsi (operands[0], operands[4])); 13808 } 13809 DONE; 13810}") 13811 13812(define_expand "ctr<mode>" 13813 [(parallel [(set (pc) 13814 (if_then_else (ne (match_operand:P 0 "register_operand" "") 13815 (const_int 1)) 13816 (label_ref (match_operand 1 "" "")) 13817 (pc))) 13818 (set (match_dup 0) 13819 (plus:P (match_dup 0) 13820 (const_int -1))) 13821 (clobber (match_scratch:CC 2 "")) 13822 (clobber (match_scratch:P 3 ""))])] 13823 "" 13824 "") 13825 13826;; We need to be able to do this for any operand, including MEM, or we 13827;; will cause reload to blow up since we don't allow output reloads on 13828;; JUMP_INSNs. 13829;; For the length attribute to be calculated correctly, the 13830;; label MUST be operand 0. 13831 13832(define_insn "*ctr<mode>_internal1" 13833 [(set (pc) 13834 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r") 13835 (const_int 1)) 13836 (label_ref (match_operand 0 "" "")) 13837 (pc))) 13838 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") 13839 (plus:P (match_dup 1) 13840 (const_int -1))) 13841 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 13842 (clobber (match_scratch:P 4 "=X,X,&r,r"))] 13843 "" 13844 "* 13845{ 13846 if (which_alternative != 0) 13847 return \"#\"; 13848 else if (get_attr_length (insn) == 4) 13849 return \"{bdn|bdnz} %l0\"; 13850 else 13851 return \"bdz $+8\;b %l0\"; 13852}" 13853 [(set_attr "type" "branch") 13854 (set_attr "length" "*,12,16,16")]) 13855 13856(define_insn "*ctr<mode>_internal2" 13857 [(set (pc) 13858 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r") 13859 (const_int 1)) 13860 (pc) 13861 (label_ref (match_operand 0 "" "")))) 13862 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") 13863 (plus:P (match_dup 1) 13864 (const_int -1))) 13865 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 13866 (clobber (match_scratch:P 4 "=X,X,&r,r"))] 13867 "" 13868 "* 13869{ 13870 if (which_alternative != 0) 13871 return \"#\"; 13872 else if (get_attr_length (insn) == 4) 13873 return \"bdz %l0\"; 13874 else 13875 return \"{bdn|bdnz} $+8\;b %l0\"; 13876}" 13877 [(set_attr "type" "branch") 13878 (set_attr "length" "*,12,16,16")]) 13879 13880;; Similar but use EQ 13881 13882(define_insn "*ctr<mode>_internal5" 13883 [(set (pc) 13884 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r") 13885 (const_int 1)) 13886 (label_ref (match_operand 0 "" "")) 13887 (pc))) 13888 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") 13889 (plus:P (match_dup 1) 13890 (const_int -1))) 13891 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 13892 (clobber (match_scratch:P 4 "=X,X,&r,r"))] 13893 "" 13894 "* 13895{ 13896 if (which_alternative != 0) 13897 return \"#\"; 13898 else if (get_attr_length (insn) == 4) 13899 return \"bdz %l0\"; 13900 else 13901 return \"{bdn|bdnz} $+8\;b %l0\"; 13902}" 13903 [(set_attr "type" "branch") 13904 (set_attr "length" "*,12,16,16")]) 13905 13906(define_insn "*ctr<mode>_internal6" 13907 [(set (pc) 13908 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r") 13909 (const_int 1)) 13910 (pc) 13911 (label_ref (match_operand 0 "" "")))) 13912 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") 13913 (plus:P (match_dup 1) 13914 (const_int -1))) 13915 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 13916 (clobber (match_scratch:P 4 "=X,X,&r,r"))] 13917 "" 13918 "* 13919{ 13920 if (which_alternative != 0) 13921 return \"#\"; 13922 else if (get_attr_length (insn) == 4) 13923 return \"{bdn|bdnz} %l0\"; 13924 else 13925 return \"bdz $+8\;b %l0\"; 13926}" 13927 [(set_attr "type" "branch") 13928 (set_attr "length" "*,12,16,16")]) 13929 13930;; Now the splitters if we could not allocate the CTR register 13931 13932(define_split 13933 [(set (pc) 13934 (if_then_else (match_operator 2 "comparison_operator" 13935 [(match_operand:P 1 "gpc_reg_operand" "") 13936 (const_int 1)]) 13937 (match_operand 5 "" "") 13938 (match_operand 6 "" ""))) 13939 (set (match_operand:P 0 "gpc_reg_operand" "") 13940 (plus:P (match_dup 1) (const_int -1))) 13941 (clobber (match_scratch:CC 3 "")) 13942 (clobber (match_scratch:P 4 ""))] 13943 "reload_completed" 13944 [(parallel [(set (match_dup 3) 13945 (compare:CC (plus:P (match_dup 1) 13946 (const_int -1)) 13947 (const_int 0))) 13948 (set (match_dup 0) 13949 (plus:P (match_dup 1) 13950 (const_int -1)))]) 13951 (set (pc) (if_then_else (match_dup 7) 13952 (match_dup 5) 13953 (match_dup 6)))] 13954 " 13955{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, 13956 operands[3], const0_rtx); }") 13957 13958(define_split 13959 [(set (pc) 13960 (if_then_else (match_operator 2 "comparison_operator" 13961 [(match_operand:P 1 "gpc_reg_operand" "") 13962 (const_int 1)]) 13963 (match_operand 5 "" "") 13964 (match_operand 6 "" ""))) 13965 (set (match_operand:P 0 "nonimmediate_operand" "") 13966 (plus:P (match_dup 1) (const_int -1))) 13967 (clobber (match_scratch:CC 3 "")) 13968 (clobber (match_scratch:P 4 ""))] 13969 "reload_completed && ! gpc_reg_operand (operands[0], SImode)" 13970 [(parallel [(set (match_dup 3) 13971 (compare:CC (plus:P (match_dup 1) 13972 (const_int -1)) 13973 (const_int 0))) 13974 (set (match_dup 4) 13975 (plus:P (match_dup 1) 13976 (const_int -1)))]) 13977 (set (match_dup 0) 13978 (match_dup 4)) 13979 (set (pc) (if_then_else (match_dup 7) 13980 (match_dup 5) 13981 (match_dup 6)))] 13982 " 13983{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, 13984 operands[3], const0_rtx); }") 13985 13986(define_insn "trap" 13987 [(trap_if (const_int 1) (const_int 0))] 13988 "" 13989 "{t 31,0,0|trap}") 13990 13991(define_expand "conditional_trap" 13992 [(trap_if (match_operator 0 "trap_comparison_operator" 13993 [(match_dup 2) (match_dup 3)]) 13994 (match_operand 1 "const_int_operand" ""))] 13995 "" 13996 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; 13997 operands[2] = rs6000_compare_op0; 13998 operands[3] = rs6000_compare_op1;") 13999 14000(define_insn "" 14001 [(trap_if (match_operator 0 "trap_comparison_operator" 14002 [(match_operand:GPR 1 "register_operand" "r") 14003 (match_operand:GPR 2 "reg_or_short_operand" "rI")]) 14004 (const_int 0))] 14005 "" 14006 "{t|t<wd>}%V0%I2 %1,%2") 14007 14008;; Insns related to generating the function prologue and epilogue. 14009 14010(define_expand "prologue" 14011 [(use (const_int 0))] 14012 "TARGET_SCHED_PROLOG" 14013 " 14014{ 14015 rs6000_emit_prologue (); 14016 DONE; 14017}") 14018 14019(define_insn "*movesi_from_cr_one" 14020 [(match_parallel 0 "mfcr_operation" 14021 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 14022 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") 14023 (match_operand 3 "immediate_operand" "n")] 14024 UNSPEC_MOVESI_FROM_CR))])] 14025 "TARGET_MFCRF" 14026 "* 14027{ 14028 int mask = 0; 14029 int i; 14030 for (i = 0; i < XVECLEN (operands[0], 0); i++) 14031 { 14032 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); 14033 operands[4] = GEN_INT (mask); 14034 output_asm_insn (\"mfcr %1,%4\", operands); 14035 } 14036 return \"\"; 14037}" 14038 [(set_attr "type" "mfcrf")]) 14039 14040(define_insn "movesi_from_cr" 14041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 14042 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) 14043 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 14044 UNSPEC_MOVESI_FROM_CR))] 14045 "" 14046 "mfcr %0" 14047 [(set_attr "type" "mfcr")]) 14048 14049(define_insn "*stmw" 14050 [(match_parallel 0 "stmw_operation" 14051 [(set (match_operand:SI 1 "memory_operand" "=m") 14052 (match_operand:SI 2 "gpc_reg_operand" "r"))])] 14053 "TARGET_MULTIPLE" 14054 "{stm|stmw} %2,%1" 14055 [(set_attr "type" "store_ux")]) 14056 14057(define_insn "*save_fpregs_<mode>" 14058 [(match_parallel 0 "any_parallel_operand" 14059 [(clobber (match_operand:P 1 "register_operand" "=l")) 14060 (use (match_operand:P 2 "call_operand" "s")) 14061 (set (match_operand:DF 3 "memory_operand" "=m") 14062 (match_operand:DF 4 "gpc_reg_operand" "f"))])] 14063 "" 14064 "bl %z2" 14065 [(set_attr "type" "branch") 14066 (set_attr "length" "4")]) 14067 14068; These are to explain that changes to the stack pointer should 14069; not be moved over stores to stack memory. 14070(define_insn "stack_tie" 14071 [(set (match_operand:BLK 0 "memory_operand" "+m") 14072 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] 14073 "" 14074 "" 14075 [(set_attr "length" "0")]) 14076 14077 14078(define_expand "epilogue" 14079 [(use (const_int 0))] 14080 "TARGET_SCHED_PROLOG" 14081 " 14082{ 14083 rs6000_emit_epilogue (FALSE); 14084 DONE; 14085}") 14086 14087; On some processors, doing the mtcrf one CC register at a time is 14088; faster (like on the 604e). On others, doing them all at once is 14089; faster; for instance, on the 601 and 750. 14090 14091(define_expand "movsi_to_cr_one" 14092 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 14093 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 14094 (match_dup 2)] UNSPEC_MOVESI_TO_CR))] 14095 "" 14096 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") 14097 14098(define_insn "*movsi_to_cr" 14099 [(match_parallel 0 "mtcrf_operation" 14100 [(set (match_operand:CC 1 "cc_reg_operand" "=y") 14101 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") 14102 (match_operand 3 "immediate_operand" "n")] 14103 UNSPEC_MOVESI_TO_CR))])] 14104 "" 14105 "* 14106{ 14107 int mask = 0; 14108 int i; 14109 for (i = 0; i < XVECLEN (operands[0], 0); i++) 14110 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); 14111 operands[4] = GEN_INT (mask); 14112 return \"mtcrf %4,%2\"; 14113}" 14114 [(set_attr "type" "mtcr")]) 14115 14116(define_insn "*mtcrfsi" 14117 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 14118 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 14119 (match_operand 2 "immediate_operand" "n")] 14120 UNSPEC_MOVESI_TO_CR))] 14121 "GET_CODE (operands[0]) == REG 14122 && CR_REGNO_P (REGNO (operands[0])) 14123 && GET_CODE (operands[2]) == CONST_INT 14124 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" 14125 "mtcrf %R0,%1" 14126 [(set_attr "type" "mtcr")]) 14127 14128; The load-multiple instructions have similar properties. 14129; Note that "load_multiple" is a name known to the machine-independent 14130; code that actually corresponds to the PowerPC load-string. 14131 14132(define_insn "*lmw" 14133 [(match_parallel 0 "lmw_operation" 14134 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 14135 (match_operand:SI 2 "memory_operand" "m"))])] 14136 "TARGET_MULTIPLE" 14137 "{lm|lmw} %1,%2" 14138 [(set_attr "type" "load_ux")]) 14139 14140(define_insn "*return_internal_<mode>" 14141 [(return) 14142 (use (match_operand:P 0 "register_operand" "lc"))] 14143 "" 14144 "b%T0" 14145 [(set_attr "type" "jmpreg")]) 14146 14147; FIXME: This would probably be somewhat simpler if the Cygnus sibcall 14148; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible... 14149 14150(define_insn "*return_and_restore_fpregs_<mode>" 14151 [(match_parallel 0 "any_parallel_operand" 14152 [(return) 14153 (use (match_operand:P 1 "register_operand" "l")) 14154 (use (match_operand:P 2 "call_operand" "s")) 14155 (set (match_operand:DF 3 "gpc_reg_operand" "=f") 14156 (match_operand:DF 4 "memory_operand" "m"))])] 14157 "" 14158 "b %z2") 14159 14160; This is used in compiling the unwind routines. 14161(define_expand "eh_return" 14162 [(use (match_operand 0 "general_operand" ""))] 14163 "" 14164 " 14165{ 14166 if (TARGET_32BIT) 14167 emit_insn (gen_eh_set_lr_si (operands[0])); 14168 else 14169 emit_insn (gen_eh_set_lr_di (operands[0])); 14170 DONE; 14171}") 14172 14173; We can't expand this before we know where the link register is stored. 14174(define_insn "eh_set_lr_<mode>" 14175 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")] 14176 UNSPECV_EH_RR) 14177 (clobber (match_scratch:P 1 "=&b"))] 14178 "" 14179 "#") 14180 14181(define_split 14182 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) 14183 (clobber (match_scratch 1 ""))] 14184 "reload_completed" 14185 [(const_int 0)] 14186 " 14187{ 14188 rs6000_emit_eh_reg_restore (operands[0], operands[1]); 14189 DONE; 14190}") 14191 14192(define_insn "prefetch" 14193 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a") 14194 (match_operand:SI 1 "const_int_operand" "n") 14195 (match_operand:SI 2 "const_int_operand" "n"))] 14196 "TARGET_POWERPC" 14197 "* 14198{ 14199 if (GET_CODE (operands[0]) == REG) 14200 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; 14201 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; 14202}" 14203 [(set_attr "type" "load")]) 14204 14205 14206(include "sync.md") 14207(include "altivec.md") 14208(include "spe.md") 14209