rs6000.md revision 161651
1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify it 9;; under the terms of the GNU General Public License as published 10;; by the Free Software Foundation; either version 2, or (at your 11;; option) any later version. 12 13;; GCC is distributed in the hope that it will be useful, but WITHOUT 14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16;; License for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING. If not, write to the 20;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, 21;; MA 02111-1307, USA. 22 23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 24 25;; 26;; UNSPEC usage 27;; 28 29(define_constants 30 [(UNSPEC_FRSP 0) ; frsp for POWER machines 31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer 32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC 33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less) 34 (UNSPEC_MOVSI_GOT 8) 35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit 36 (UNSPEC_FCTIWZ 10) 37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase 38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic 39 (UNSPEC_TLSGD 17) 40 (UNSPEC_TLSLD 18) 41 (UNSPEC_MOVESI_FROM_CR 19) 42 (UNSPEC_MOVESI_TO_CR 20) 43 (UNSPEC_TLSDTPREL 21) 44 (UNSPEC_TLSDTPRELHA 22) 45 (UNSPEC_TLSDTPRELLO 23) 46 (UNSPEC_TLSGOTDTPREL 24) 47 (UNSPEC_TLSTPREL 25) 48 (UNSPEC_TLSTPRELHA 26) 49 (UNSPEC_TLSTPRELLO 27) 50 (UNSPEC_TLSGOTTPREL 28) 51 (UNSPEC_TLSTLS 29) 52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero 53 (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit 54 ]) 55 56;; 57;; UNSPEC_VOLATILE usage 58;; 59 60(define_constants 61 [(UNSPECV_BLOCK 0) 62 (UNSPECV_EH_RR 9) ; eh_reg_restore 63 ]) 64 65;; Define an insn type attribute. This is used in function unit delay 66;; computations. 67(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" 68 (const_string "integer")) 69 70;; Length (in bytes). 71; '(pc)' in the following doesn't include the instruction itself; it is 72; calculated as if the instruction had zero size. 73(define_attr "length" "" 74 (if_then_else (eq_attr "type" "branch") 75 (if_then_else (and (ge (minus (match_dup 0) (pc)) 76 (const_int -32768)) 77 (lt (minus (match_dup 0) (pc)) 78 (const_int 32764))) 79 (const_int 4) 80 (const_int 8)) 81 (const_int 4))) 82 83;; Processor type -- this attribute must exactly match the processor_type 84;; enumeration in rs6000.h. 85 86(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" 87 (const (symbol_ref "rs6000_cpu_attr"))) 88 89(automata_option "ndfa") 90 91(include "rios1.md") 92(include "rios2.md") 93(include "rs64.md") 94(include "mpc.md") 95(include "40x.md") 96(include "440.md") 97(include "603.md") 98(include "6xx.md") 99(include "7xx.md") 100(include "7450.md") 101(include "8540.md") 102(include "power4.md") 103(include "power5.md") 104 105 106;; Start with fixed-point load and store insns. Here we put only the more 107;; complex forms. Basic data transfer is done later. 108 109(define_expand "zero_extendqidi2" 110 [(set (match_operand:DI 0 "gpc_reg_operand" "") 111 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] 112 "TARGET_POWERPC64" 113 "") 114 115(define_insn "" 116 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 117 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 118 "TARGET_POWERPC64" 119 "@ 120 lbz%U1%X1 %0,%1 121 rldicl %0,%1,0,56" 122 [(set_attr "type" "load,*")]) 123 124(define_insn "" 125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 126 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 127 (const_int 0))) 128 (clobber (match_scratch:DI 2 "=r,r"))] 129 "TARGET_64BIT" 130 "@ 131 rldicl. %2,%1,0,56 132 #" 133 [(set_attr "type" "compare") 134 (set_attr "length" "4,8")]) 135 136(define_split 137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 138 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 139 (const_int 0))) 140 (clobber (match_scratch:DI 2 ""))] 141 "TARGET_POWERPC64 && reload_completed" 142 [(set (match_dup 2) 143 (zero_extend:DI (match_dup 1))) 144 (set (match_dup 0) 145 (compare:CC (match_dup 2) 146 (const_int 0)))] 147 "") 148 149(define_insn "" 150 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 151 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 152 (const_int 0))) 153 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 154 (zero_extend:DI (match_dup 1)))] 155 "TARGET_64BIT" 156 "@ 157 rldicl. %0,%1,0,56 158 #" 159 [(set_attr "type" "compare") 160 (set_attr "length" "4,8")]) 161 162(define_split 163 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 164 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 165 (const_int 0))) 166 (set (match_operand:DI 0 "gpc_reg_operand" "") 167 (zero_extend:DI (match_dup 1)))] 168 "TARGET_POWERPC64 && reload_completed" 169 [(set (match_dup 0) 170 (zero_extend:DI (match_dup 1))) 171 (set (match_dup 2) 172 (compare:CC (match_dup 0) 173 (const_int 0)))] 174 "") 175 176(define_insn "extendqidi2" 177 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 178 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] 179 "TARGET_POWERPC64" 180 "extsb %0,%1") 181 182(define_insn "" 183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 184 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 185 (const_int 0))) 186 (clobber (match_scratch:DI 2 "=r,r"))] 187 "TARGET_64BIT" 188 "@ 189 extsb. %2,%1 190 #" 191 [(set_attr "type" "compare") 192 (set_attr "length" "4,8")]) 193 194(define_split 195 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 196 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 197 (const_int 0))) 198 (clobber (match_scratch:DI 2 ""))] 199 "TARGET_POWERPC64 && reload_completed" 200 [(set (match_dup 2) 201 (sign_extend:DI (match_dup 1))) 202 (set (match_dup 0) 203 (compare:CC (match_dup 2) 204 (const_int 0)))] 205 "") 206 207(define_insn "" 208 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 209 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 210 (const_int 0))) 211 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 212 (sign_extend:DI (match_dup 1)))] 213 "TARGET_64BIT" 214 "@ 215 extsb. %0,%1 216 #" 217 [(set_attr "type" "compare") 218 (set_attr "length" "4,8")]) 219 220(define_split 221 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 222 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 223 (const_int 0))) 224 (set (match_operand:DI 0 "gpc_reg_operand" "") 225 (sign_extend:DI (match_dup 1)))] 226 "TARGET_POWERPC64 && reload_completed" 227 [(set (match_dup 0) 228 (sign_extend:DI (match_dup 1))) 229 (set (match_dup 2) 230 (compare:CC (match_dup 0) 231 (const_int 0)))] 232 "") 233 234(define_expand "zero_extendhidi2" 235 [(set (match_operand:DI 0 "gpc_reg_operand" "") 236 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 237 "TARGET_POWERPC64" 238 "") 239 240(define_insn "" 241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 242 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 243 "TARGET_POWERPC64" 244 "@ 245 lhz%U1%X1 %0,%1 246 rldicl %0,%1,0,48" 247 [(set_attr "type" "load,*")]) 248 249(define_insn "" 250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 251 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 252 (const_int 0))) 253 (clobber (match_scratch:DI 2 "=r,r"))] 254 "TARGET_64BIT" 255 "@ 256 rldicl. %2,%1,0,48 257 #" 258 [(set_attr "type" "compare") 259 (set_attr "length" "4,8")]) 260 261(define_split 262 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 263 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 264 (const_int 0))) 265 (clobber (match_scratch:DI 2 ""))] 266 "TARGET_POWERPC64 && reload_completed" 267 [(set (match_dup 2) 268 (zero_extend:DI (match_dup 1))) 269 (set (match_dup 0) 270 (compare:CC (match_dup 2) 271 (const_int 0)))] 272 "") 273 274(define_insn "" 275 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 276 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 277 (const_int 0))) 278 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 279 (zero_extend:DI (match_dup 1)))] 280 "TARGET_64BIT" 281 "@ 282 rldicl. %0,%1,0,48 283 #" 284 [(set_attr "type" "compare") 285 (set_attr "length" "4,8")]) 286 287(define_split 288 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 289 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 290 (const_int 0))) 291 (set (match_operand:DI 0 "gpc_reg_operand" "") 292 (zero_extend:DI (match_dup 1)))] 293 "TARGET_POWERPC64 && reload_completed" 294 [(set (match_dup 0) 295 (zero_extend:DI (match_dup 1))) 296 (set (match_dup 2) 297 (compare:CC (match_dup 0) 298 (const_int 0)))] 299 "") 300 301(define_expand "extendhidi2" 302 [(set (match_operand:DI 0 "gpc_reg_operand" "") 303 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 304 "TARGET_POWERPC64" 305 "") 306 307(define_insn "" 308 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 309 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 310 "TARGET_POWERPC64" 311 "@ 312 lha%U1%X1 %0,%1 313 extsh %0,%1" 314 [(set_attr "type" "load_ext,*")]) 315 316(define_insn "" 317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 318 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 319 (const_int 0))) 320 (clobber (match_scratch:DI 2 "=r,r"))] 321 "TARGET_64BIT" 322 "@ 323 extsh. %2,%1 324 #" 325 [(set_attr "type" "compare") 326 (set_attr "length" "4,8")]) 327 328(define_split 329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 330 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 331 (const_int 0))) 332 (clobber (match_scratch:DI 2 ""))] 333 "TARGET_POWERPC64 && reload_completed" 334 [(set (match_dup 2) 335 (sign_extend:DI (match_dup 1))) 336 (set (match_dup 0) 337 (compare:CC (match_dup 2) 338 (const_int 0)))] 339 "") 340 341(define_insn "" 342 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 343 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 344 (const_int 0))) 345 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 346 (sign_extend:DI (match_dup 1)))] 347 "TARGET_64BIT" 348 "@ 349 extsh. %0,%1 350 #" 351 [(set_attr "type" "compare") 352 (set_attr "length" "4,8")]) 353 354(define_split 355 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 356 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 357 (const_int 0))) 358 (set (match_operand:DI 0 "gpc_reg_operand" "") 359 (sign_extend:DI (match_dup 1)))] 360 "TARGET_POWERPC64 && reload_completed" 361 [(set (match_dup 0) 362 (sign_extend:DI (match_dup 1))) 363 (set (match_dup 2) 364 (compare:CC (match_dup 0) 365 (const_int 0)))] 366 "") 367 368(define_expand "zero_extendsidi2" 369 [(set (match_operand:DI 0 "gpc_reg_operand" "") 370 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 371 "TARGET_POWERPC64" 372 "") 373 374(define_insn "" 375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 376 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] 377 "TARGET_POWERPC64" 378 "@ 379 lwz%U1%X1 %0,%1 380 rldicl %0,%1,0,32" 381 [(set_attr "type" "load,*")]) 382 383(define_insn "" 384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 385 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 386 (const_int 0))) 387 (clobber (match_scratch:DI 2 "=r,r"))] 388 "TARGET_64BIT" 389 "@ 390 rldicl. %2,%1,0,32 391 #" 392 [(set_attr "type" "compare") 393 (set_attr "length" "4,8")]) 394 395(define_split 396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 397 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 398 (const_int 0))) 399 (clobber (match_scratch:DI 2 ""))] 400 "TARGET_POWERPC64 && reload_completed" 401 [(set (match_dup 2) 402 (zero_extend:DI (match_dup 1))) 403 (set (match_dup 0) 404 (compare:CC (match_dup 2) 405 (const_int 0)))] 406 "") 407 408(define_insn "" 409 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 410 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 411 (const_int 0))) 412 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 413 (zero_extend:DI (match_dup 1)))] 414 "TARGET_64BIT" 415 "@ 416 rldicl. %0,%1,0,32 417 #" 418 [(set_attr "type" "compare") 419 (set_attr "length" "4,8")]) 420 421(define_split 422 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 423 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 424 (const_int 0))) 425 (set (match_operand:DI 0 "gpc_reg_operand" "") 426 (zero_extend:DI (match_dup 1)))] 427 "TARGET_POWERPC64 && reload_completed" 428 [(set (match_dup 0) 429 (zero_extend:DI (match_dup 1))) 430 (set (match_dup 2) 431 (compare:CC (match_dup 0) 432 (const_int 0)))] 433 "") 434 435(define_expand "extendsidi2" 436 [(set (match_operand:DI 0 "gpc_reg_operand" "") 437 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 438 "TARGET_POWERPC64" 439 "") 440 441(define_insn "" 442 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 443 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] 444 "TARGET_POWERPC64" 445 "@ 446 lwa%U1%X1 %0,%1 447 extsw %0,%1" 448 [(set_attr "type" "load_ext,*")]) 449 450(define_insn "" 451 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 452 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 453 (const_int 0))) 454 (clobber (match_scratch:DI 2 "=r,r"))] 455 "TARGET_64BIT" 456 "@ 457 extsw. %2,%1 458 #" 459 [(set_attr "type" "compare") 460 (set_attr "length" "4,8")]) 461 462(define_split 463 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 464 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 465 (const_int 0))) 466 (clobber (match_scratch:DI 2 ""))] 467 "TARGET_POWERPC64 && reload_completed" 468 [(set (match_dup 2) 469 (sign_extend:DI (match_dup 1))) 470 (set (match_dup 0) 471 (compare:CC (match_dup 2) 472 (const_int 0)))] 473 "") 474 475(define_insn "" 476 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 477 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 478 (const_int 0))) 479 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 480 (sign_extend:DI (match_dup 1)))] 481 "TARGET_64BIT" 482 "@ 483 extsw. %0,%1 484 #" 485 [(set_attr "type" "compare") 486 (set_attr "length" "4,8")]) 487 488(define_split 489 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 490 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 491 (const_int 0))) 492 (set (match_operand:DI 0 "gpc_reg_operand" "") 493 (sign_extend:DI (match_dup 1)))] 494 "TARGET_POWERPC64 && reload_completed" 495 [(set (match_dup 0) 496 (sign_extend:DI (match_dup 1))) 497 (set (match_dup 2) 498 (compare:CC (match_dup 0) 499 (const_int 0)))] 500 "") 501 502(define_expand "zero_extendqisi2" 503 [(set (match_operand:SI 0 "gpc_reg_operand" "") 504 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] 505 "" 506 "") 507 508(define_insn "" 509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 510 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 511 "" 512 "@ 513 lbz%U1%X1 %0,%1 514 {rlinm|rlwinm} %0,%1,0,0xff" 515 [(set_attr "type" "load,*")]) 516 517(define_insn "" 518 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 519 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 520 (const_int 0))) 521 (clobber (match_scratch:SI 2 "=r,r"))] 522 "" 523 "@ 524 {andil.|andi.} %2,%1,0xff 525 #" 526 [(set_attr "type" "compare") 527 (set_attr "length" "4,8")]) 528 529(define_split 530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 531 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 532 (const_int 0))) 533 (clobber (match_scratch:SI 2 ""))] 534 "reload_completed" 535 [(set (match_dup 2) 536 (zero_extend:SI (match_dup 1))) 537 (set (match_dup 0) 538 (compare:CC (match_dup 2) 539 (const_int 0)))] 540 "") 541 542(define_insn "" 543 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 544 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 545 (const_int 0))) 546 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 547 (zero_extend:SI (match_dup 1)))] 548 "" 549 "@ 550 {andil.|andi.} %0,%1,0xff 551 #" 552 [(set_attr "type" "compare") 553 (set_attr "length" "4,8")]) 554 555(define_split 556 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 557 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 558 (const_int 0))) 559 (set (match_operand:SI 0 "gpc_reg_operand" "") 560 (zero_extend:SI (match_dup 1)))] 561 "reload_completed" 562 [(set (match_dup 0) 563 (zero_extend:SI (match_dup 1))) 564 (set (match_dup 2) 565 (compare:CC (match_dup 0) 566 (const_int 0)))] 567 "") 568 569(define_expand "extendqisi2" 570 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 571 (use (match_operand:QI 1 "gpc_reg_operand" ""))] 572 "" 573 " 574{ 575 if (TARGET_POWERPC) 576 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); 577 else if (TARGET_POWER) 578 emit_insn (gen_extendqisi2_power (operands[0], operands[1])); 579 else 580 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); 581 DONE; 582}") 583 584(define_insn "extendqisi2_ppc" 585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 586 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] 587 "TARGET_POWERPC" 588 "extsb %0,%1") 589 590(define_insn "" 591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 592 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 593 (const_int 0))) 594 (clobber (match_scratch:SI 2 "=r,r"))] 595 "TARGET_POWERPC" 596 "@ 597 extsb. %2,%1 598 #" 599 [(set_attr "type" "compare") 600 (set_attr "length" "4,8")]) 601 602(define_split 603 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 604 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 605 (const_int 0))) 606 (clobber (match_scratch:SI 2 ""))] 607 "TARGET_POWERPC && reload_completed" 608 [(set (match_dup 2) 609 (sign_extend:SI (match_dup 1))) 610 (set (match_dup 0) 611 (compare:CC (match_dup 2) 612 (const_int 0)))] 613 "") 614 615(define_insn "" 616 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 617 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 618 (const_int 0))) 619 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 620 (sign_extend:SI (match_dup 1)))] 621 "TARGET_POWERPC" 622 "@ 623 extsb. %0,%1 624 #" 625 [(set_attr "type" "compare") 626 (set_attr "length" "4,8")]) 627 628(define_split 629 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 630 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 631 (const_int 0))) 632 (set (match_operand:SI 0 "gpc_reg_operand" "") 633 (sign_extend:SI (match_dup 1)))] 634 "TARGET_POWERPC && reload_completed" 635 [(set (match_dup 0) 636 (sign_extend:SI (match_dup 1))) 637 (set (match_dup 2) 638 (compare:CC (match_dup 0) 639 (const_int 0)))] 640 "") 641 642(define_expand "extendqisi2_power" 643 [(parallel [(set (match_dup 2) 644 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 645 (const_int 24))) 646 (clobber (scratch:SI))]) 647 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 648 (ashiftrt:SI (match_dup 2) 649 (const_int 24))) 650 (clobber (scratch:SI))])] 651 "TARGET_POWER" 652 " 653{ operands[1] = gen_lowpart (SImode, operands[1]); 654 operands[2] = gen_reg_rtx (SImode); }") 655 656(define_expand "extendqisi2_no_power" 657 [(set (match_dup 2) 658 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 659 (const_int 24))) 660 (set (match_operand:SI 0 "gpc_reg_operand" "") 661 (ashiftrt:SI (match_dup 2) 662 (const_int 24)))] 663 "! TARGET_POWER && ! TARGET_POWERPC" 664 " 665{ operands[1] = gen_lowpart (SImode, operands[1]); 666 operands[2] = gen_reg_rtx (SImode); }") 667 668(define_expand "zero_extendqihi2" 669 [(set (match_operand:HI 0 "gpc_reg_operand" "") 670 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] 671 "" 672 "") 673 674(define_insn "" 675 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 676 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 677 "" 678 "@ 679 lbz%U1%X1 %0,%1 680 {rlinm|rlwinm} %0,%1,0,0xff" 681 [(set_attr "type" "load,*")]) 682 683(define_insn "" 684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 685 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 686 (const_int 0))) 687 (clobber (match_scratch:HI 2 "=r,r"))] 688 "" 689 "@ 690 {andil.|andi.} %2,%1,0xff 691 #" 692 [(set_attr "type" "compare") 693 (set_attr "length" "4,8")]) 694 695(define_split 696 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 697 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 698 (const_int 0))) 699 (clobber (match_scratch:HI 2 ""))] 700 "reload_completed" 701 [(set (match_dup 2) 702 (zero_extend:HI (match_dup 1))) 703 (set (match_dup 0) 704 (compare:CC (match_dup 2) 705 (const_int 0)))] 706 "") 707 708(define_insn "" 709 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 710 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 711 (const_int 0))) 712 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 713 (zero_extend:HI (match_dup 1)))] 714 "" 715 "@ 716 {andil.|andi.} %0,%1,0xff 717 #" 718 [(set_attr "type" "compare") 719 (set_attr "length" "4,8")]) 720 721(define_split 722 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 723 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 724 (const_int 0))) 725 (set (match_operand:HI 0 "gpc_reg_operand" "") 726 (zero_extend:HI (match_dup 1)))] 727 "reload_completed" 728 [(set (match_dup 0) 729 (zero_extend:HI (match_dup 1))) 730 (set (match_dup 2) 731 (compare:CC (match_dup 0) 732 (const_int 0)))] 733 "") 734 735(define_expand "extendqihi2" 736 [(use (match_operand:HI 0 "gpc_reg_operand" "")) 737 (use (match_operand:QI 1 "gpc_reg_operand" ""))] 738 "" 739 " 740{ 741 if (TARGET_POWERPC) 742 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); 743 else if (TARGET_POWER) 744 emit_insn (gen_extendqihi2_power (operands[0], operands[1])); 745 else 746 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); 747 DONE; 748}") 749 750(define_insn "extendqihi2_ppc" 751 [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 752 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] 753 "TARGET_POWERPC" 754 "extsb %0,%1") 755 756(define_insn "" 757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 758 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 759 (const_int 0))) 760 (clobber (match_scratch:HI 2 "=r,r"))] 761 "TARGET_POWERPC" 762 "@ 763 extsb. %2,%1 764 #" 765 [(set_attr "type" "compare") 766 (set_attr "length" "4,8")]) 767 768(define_split 769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 770 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 771 (const_int 0))) 772 (clobber (match_scratch:HI 2 ""))] 773 "TARGET_POWERPC && reload_completed" 774 [(set (match_dup 2) 775 (sign_extend:HI (match_dup 1))) 776 (set (match_dup 0) 777 (compare:CC (match_dup 2) 778 (const_int 0)))] 779 "") 780 781(define_insn "" 782 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 783 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 784 (const_int 0))) 785 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 786 (sign_extend:HI (match_dup 1)))] 787 "TARGET_POWERPC" 788 "@ 789 extsb. %0,%1 790 #" 791 [(set_attr "type" "compare") 792 (set_attr "length" "4,8")]) 793 794(define_split 795 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 796 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 797 (const_int 0))) 798 (set (match_operand:HI 0 "gpc_reg_operand" "") 799 (sign_extend:HI (match_dup 1)))] 800 "TARGET_POWERPC && reload_completed" 801 [(set (match_dup 0) 802 (sign_extend:HI (match_dup 1))) 803 (set (match_dup 2) 804 (compare:CC (match_dup 0) 805 (const_int 0)))] 806 "") 807 808(define_expand "extendqihi2_power" 809 [(parallel [(set (match_dup 2) 810 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 811 (const_int 24))) 812 (clobber (scratch:SI))]) 813 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") 814 (ashiftrt:SI (match_dup 2) 815 (const_int 24))) 816 (clobber (scratch:SI))])] 817 "TARGET_POWER" 818 " 819{ operands[0] = gen_lowpart (SImode, operands[0]); 820 operands[1] = gen_lowpart (SImode, operands[1]); 821 operands[2] = gen_reg_rtx (SImode); }") 822 823(define_expand "extendqihi2_no_power" 824 [(set (match_dup 2) 825 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 826 (const_int 24))) 827 (set (match_operand:HI 0 "gpc_reg_operand" "") 828 (ashiftrt:SI (match_dup 2) 829 (const_int 24)))] 830 "! TARGET_POWER && ! TARGET_POWERPC" 831 " 832{ operands[0] = gen_lowpart (SImode, operands[0]); 833 operands[1] = gen_lowpart (SImode, operands[1]); 834 operands[2] = gen_reg_rtx (SImode); }") 835 836(define_expand "zero_extendhisi2" 837 [(set (match_operand:SI 0 "gpc_reg_operand" "") 838 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 839 "" 840 "") 841 842(define_insn "" 843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 844 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 845 "" 846 "@ 847 lhz%U1%X1 %0,%1 848 {rlinm|rlwinm} %0,%1,0,0xffff" 849 [(set_attr "type" "load,*")]) 850 851(define_insn "" 852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 853 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 854 (const_int 0))) 855 (clobber (match_scratch:SI 2 "=r,r"))] 856 "" 857 "@ 858 {andil.|andi.} %2,%1,0xffff 859 #" 860 [(set_attr "type" "compare") 861 (set_attr "length" "4,8")]) 862 863(define_split 864 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 865 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 866 (const_int 0))) 867 (clobber (match_scratch:SI 2 ""))] 868 "reload_completed" 869 [(set (match_dup 2) 870 (zero_extend:SI (match_dup 1))) 871 (set (match_dup 0) 872 (compare:CC (match_dup 2) 873 (const_int 0)))] 874 "") 875 876(define_insn "" 877 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 878 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 879 (const_int 0))) 880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 881 (zero_extend:SI (match_dup 1)))] 882 "" 883 "@ 884 {andil.|andi.} %0,%1,0xffff 885 #" 886 [(set_attr "type" "compare") 887 (set_attr "length" "4,8")]) 888 889(define_split 890 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 891 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 892 (const_int 0))) 893 (set (match_operand:SI 0 "gpc_reg_operand" "") 894 (zero_extend:SI (match_dup 1)))] 895 "reload_completed" 896 [(set (match_dup 0) 897 (zero_extend:SI (match_dup 1))) 898 (set (match_dup 2) 899 (compare:CC (match_dup 0) 900 (const_int 0)))] 901 "") 902 903(define_expand "extendhisi2" 904 [(set (match_operand:SI 0 "gpc_reg_operand" "") 905 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 906 "" 907 "") 908 909(define_insn "" 910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 911 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 912 "" 913 "@ 914 lha%U1%X1 %0,%1 915 {exts|extsh} %0,%1" 916 [(set_attr "type" "load_ext,*")]) 917 918(define_insn "" 919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 920 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 921 (const_int 0))) 922 (clobber (match_scratch:SI 2 "=r,r"))] 923 "" 924 "@ 925 {exts.|extsh.} %2,%1 926 #" 927 [(set_attr "type" "compare") 928 (set_attr "length" "4,8")]) 929 930(define_split 931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 932 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 933 (const_int 0))) 934 (clobber (match_scratch:SI 2 ""))] 935 "reload_completed" 936 [(set (match_dup 2) 937 (sign_extend:SI (match_dup 1))) 938 (set (match_dup 0) 939 (compare:CC (match_dup 2) 940 (const_int 0)))] 941 "") 942 943(define_insn "" 944 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 945 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 946 (const_int 0))) 947 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 948 (sign_extend:SI (match_dup 1)))] 949 "" 950 "@ 951 {exts.|extsh.} %0,%1 952 #" 953 [(set_attr "type" "compare") 954 (set_attr "length" "4,8")]) 955 956(define_split 957 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 958 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 959 (const_int 0))) 960 (set (match_operand:SI 0 "gpc_reg_operand" "") 961 (sign_extend:SI (match_dup 1)))] 962 "reload_completed" 963 [(set (match_dup 0) 964 (sign_extend:SI (match_dup 1))) 965 (set (match_dup 2) 966 (compare:CC (match_dup 0) 967 (const_int 0)))] 968 "") 969 970;; Fixed-point arithmetic insns. 971 972;; Discourage ai/addic because of carry but provide it in an alternative 973;; allowing register zero as source. 974(define_expand "addsi3" 975 [(set (match_operand:SI 0 "gpc_reg_operand" "") 976 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 977 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] 978 "" 979 " 980{ 981 if (GET_CODE (operands[2]) == CONST_INT 982 && ! add_operand (operands[2], SImode)) 983 { 984 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 985 ? operands[0] : gen_reg_rtx (SImode)); 986 987 HOST_WIDE_INT val = INTVAL (operands[2]); 988 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; 989 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); 990 991 /* The ordering here is important for the prolog expander. 992 When space is allocated from the stack, adding 'low' first may 993 produce a temporary deallocation (which would be bad). */ 994 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); 995 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); 996 DONE; 997 } 998}") 999 1000(define_insn "*addsi3_internal1" 1001 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") 1002 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") 1003 (match_operand:SI 2 "add_operand" "r,I,I,L")))] 1004 "" 1005 "@ 1006 {cax|add} %0,%1,%2 1007 {cal %0,%2(%1)|addi %0,%1,%2} 1008 {ai|addic} %0,%1,%2 1009 {cau|addis} %0,%1,%v2" 1010 [(set_attr "length" "4,4,4,4")]) 1011 1012(define_insn "addsi3_high" 1013 [(set (match_operand:SI 0 "gpc_reg_operand" "=b") 1014 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 1015 (high:SI (match_operand 2 "" ""))))] 1016 "TARGET_MACHO && !TARGET_64BIT" 1017 "{cau|addis} %0,%1,ha16(%2)" 1018 [(set_attr "length" "4")]) 1019 1020(define_insn "*addsi3_internal2" 1021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 1022 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1023 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) 1024 (const_int 0))) 1025 (clobber (match_scratch:SI 3 "=r,r,r,r"))] 1026 "TARGET_32BIT" 1027 "@ 1028 {cax.|add.} %3,%1,%2 1029 {ai.|addic.} %3,%1,%2 1030 # 1031 #" 1032 [(set_attr "type" "fast_compare,compare,compare,compare") 1033 (set_attr "length" "4,4,8,8")]) 1034 1035(define_split 1036 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1037 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1038 (match_operand:SI 2 "reg_or_short_operand" "")) 1039 (const_int 0))) 1040 (clobber (match_scratch:SI 3 ""))] 1041 "TARGET_32BIT && reload_completed" 1042 [(set (match_dup 3) 1043 (plus:SI (match_dup 1) 1044 (match_dup 2))) 1045 (set (match_dup 0) 1046 (compare:CC (match_dup 3) 1047 (const_int 0)))] 1048 "") 1049 1050(define_insn "*addsi3_internal3" 1051 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 1052 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1053 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) 1054 (const_int 0))) 1055 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 1056 (plus:SI (match_dup 1) 1057 (match_dup 2)))] 1058 "TARGET_32BIT" 1059 "@ 1060 {cax.|add.} %0,%1,%2 1061 {ai.|addic.} %0,%1,%2 1062 # 1063 #" 1064 [(set_attr "type" "fast_compare,compare,compare,compare") 1065 (set_attr "length" "4,4,8,8")]) 1066 1067(define_split 1068 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1069 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1070 (match_operand:SI 2 "reg_or_short_operand" "")) 1071 (const_int 0))) 1072 (set (match_operand:SI 0 "gpc_reg_operand" "") 1073 (plus:SI (match_dup 1) (match_dup 2)))] 1074 "TARGET_32BIT && reload_completed" 1075 [(set (match_dup 0) 1076 (plus:SI (match_dup 1) 1077 (match_dup 2))) 1078 (set (match_dup 3) 1079 (compare:CC (match_dup 0) 1080 (const_int 0)))] 1081 "") 1082 1083;; Split an add that we can't do in one insn into two insns, each of which 1084;; does one 16-bit part. This is used by combine. Note that the low-order 1085;; add should be last in case the result gets used in an address. 1086 1087(define_split 1088 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1089 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1090 (match_operand:SI 2 "non_add_cint_operand" "")))] 1091 "" 1092 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 1093 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 1094" 1095{ 1096 HOST_WIDE_INT val = INTVAL (operands[2]); 1097 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; 1098 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); 1099 1100 operands[3] = GEN_INT (rest); 1101 operands[4] = GEN_INT (low); 1102}") 1103 1104(define_insn "one_cmplsi2" 1105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1106 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1107 "" 1108 "nor %0,%1,%1") 1109 1110(define_insn "" 1111 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1112 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1113 (const_int 0))) 1114 (clobber (match_scratch:SI 2 "=r,r"))] 1115 "TARGET_32BIT" 1116 "@ 1117 nor. %2,%1,%1 1118 #" 1119 [(set_attr "type" "compare") 1120 (set_attr "length" "4,8")]) 1121 1122(define_split 1123 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1124 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 1125 (const_int 0))) 1126 (clobber (match_scratch:SI 2 ""))] 1127 "TARGET_32BIT && reload_completed" 1128 [(set (match_dup 2) 1129 (not:SI (match_dup 1))) 1130 (set (match_dup 0) 1131 (compare:CC (match_dup 2) 1132 (const_int 0)))] 1133 "") 1134 1135(define_insn "" 1136 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1137 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1138 (const_int 0))) 1139 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1140 (not:SI (match_dup 1)))] 1141 "TARGET_32BIT" 1142 "@ 1143 nor. %0,%1,%1 1144 #" 1145 [(set_attr "type" "compare") 1146 (set_attr "length" "4,8")]) 1147 1148(define_split 1149 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1150 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 1151 (const_int 0))) 1152 (set (match_operand:SI 0 "gpc_reg_operand" "") 1153 (not:SI (match_dup 1)))] 1154 "TARGET_32BIT && reload_completed" 1155 [(set (match_dup 0) 1156 (not:SI (match_dup 1))) 1157 (set (match_dup 2) 1158 (compare:CC (match_dup 0) 1159 (const_int 0)))] 1160 "") 1161 1162(define_insn "" 1163 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1164 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") 1165 (match_operand:SI 2 "gpc_reg_operand" "r")))] 1166 "! TARGET_POWERPC" 1167 "{sf%I1|subf%I1c} %0,%2,%1") 1168 1169(define_insn "" 1170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1171 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") 1172 (match_operand:SI 2 "gpc_reg_operand" "r,r")))] 1173 "TARGET_POWERPC" 1174 "@ 1175 subf %0,%2,%1 1176 subfic %0,%2,%1") 1177 1178(define_insn "" 1179 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1180 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1181 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1182 (const_int 0))) 1183 (clobber (match_scratch:SI 3 "=r,r"))] 1184 "! TARGET_POWERPC" 1185 "@ 1186 {sf.|subfc.} %3,%2,%1 1187 #" 1188 [(set_attr "type" "compare") 1189 (set_attr "length" "4,8")]) 1190 1191(define_insn "" 1192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1193 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1194 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1195 (const_int 0))) 1196 (clobber (match_scratch:SI 3 "=r,r"))] 1197 "TARGET_POWERPC && TARGET_32BIT" 1198 "@ 1199 subf. %3,%2,%1 1200 #" 1201 [(set_attr "type" "fast_compare") 1202 (set_attr "length" "4,8")]) 1203 1204(define_split 1205 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1206 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1207 (match_operand:SI 2 "gpc_reg_operand" "")) 1208 (const_int 0))) 1209 (clobber (match_scratch:SI 3 ""))] 1210 "TARGET_32BIT && reload_completed" 1211 [(set (match_dup 3) 1212 (minus:SI (match_dup 1) 1213 (match_dup 2))) 1214 (set (match_dup 0) 1215 (compare:CC (match_dup 3) 1216 (const_int 0)))] 1217 "") 1218 1219(define_insn "" 1220 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1221 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1222 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1223 (const_int 0))) 1224 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1225 (minus:SI (match_dup 1) (match_dup 2)))] 1226 "! TARGET_POWERPC" 1227 "@ 1228 {sf.|subfc.} %0,%2,%1 1229 #" 1230 [(set_attr "type" "compare") 1231 (set_attr "length" "4,8")]) 1232 1233(define_insn "" 1234 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1235 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1236 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1237 (const_int 0))) 1238 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1239 (minus:SI (match_dup 1) 1240 (match_dup 2)))] 1241 "TARGET_POWERPC && TARGET_32BIT" 1242 "@ 1243 subf. %0,%2,%1 1244 #" 1245 [(set_attr "type" "fast_compare") 1246 (set_attr "length" "4,8")]) 1247 1248(define_split 1249 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1250 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1251 (match_operand:SI 2 "gpc_reg_operand" "")) 1252 (const_int 0))) 1253 (set (match_operand:SI 0 "gpc_reg_operand" "") 1254 (minus:SI (match_dup 1) 1255 (match_dup 2)))] 1256 "TARGET_32BIT && reload_completed" 1257 [(set (match_dup 0) 1258 (minus:SI (match_dup 1) 1259 (match_dup 2))) 1260 (set (match_dup 3) 1261 (compare:CC (match_dup 0) 1262 (const_int 0)))] 1263 "") 1264 1265(define_expand "subsi3" 1266 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1267 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") 1268 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] 1269 "" 1270 " 1271{ 1272 if (GET_CODE (operands[2]) == CONST_INT) 1273 { 1274 emit_insn (gen_addsi3 (operands[0], operands[1], 1275 negate_rtx (SImode, operands[2]))); 1276 DONE; 1277 } 1278}") 1279 1280;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] 1281;; instruction and some auxiliary computations. Then we just have a single 1282;; DEFINE_INSN for doz[i] and the define_splits to make them if made by 1283;; combine. 1284 1285(define_expand "sminsi3" 1286 [(set (match_dup 3) 1287 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 1288 (match_operand:SI 2 "reg_or_short_operand" "")) 1289 (const_int 0) 1290 (minus:SI (match_dup 2) (match_dup 1)))) 1291 (set (match_operand:SI 0 "gpc_reg_operand" "") 1292 (minus:SI (match_dup 2) (match_dup 3)))] 1293 "TARGET_POWER || TARGET_ISEL" 1294 " 1295{ 1296 if (TARGET_ISEL) 1297 { 1298 operands[2] = force_reg (SImode, operands[2]); 1299 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); 1300 DONE; 1301 } 1302 1303 operands[3] = gen_reg_rtx (SImode); 1304}") 1305 1306(define_split 1307 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1308 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") 1309 (match_operand:SI 2 "reg_or_short_operand" ""))) 1310 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1311 "TARGET_POWER" 1312 [(set (match_dup 3) 1313 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 1314 (const_int 0) 1315 (minus:SI (match_dup 2) (match_dup 1)))) 1316 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] 1317 "") 1318 1319(define_expand "smaxsi3" 1320 [(set (match_dup 3) 1321 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 1322 (match_operand:SI 2 "reg_or_short_operand" "")) 1323 (const_int 0) 1324 (minus:SI (match_dup 2) (match_dup 1)))) 1325 (set (match_operand:SI 0 "gpc_reg_operand" "") 1326 (plus:SI (match_dup 3) (match_dup 1)))] 1327 "TARGET_POWER || TARGET_ISEL" 1328 " 1329{ 1330 if (TARGET_ISEL) 1331 { 1332 operands[2] = force_reg (SImode, operands[2]); 1333 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); 1334 DONE; 1335 } 1336 operands[3] = gen_reg_rtx (SImode); 1337}") 1338 1339(define_split 1340 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1341 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") 1342 (match_operand:SI 2 "reg_or_short_operand" ""))) 1343 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1344 "TARGET_POWER" 1345 [(set (match_dup 3) 1346 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 1347 (const_int 0) 1348 (minus:SI (match_dup 2) (match_dup 1)))) 1349 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] 1350 "") 1351 1352(define_expand "uminsi3" 1353 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1354 (match_dup 5))) 1355 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 1356 (match_dup 5))) 1357 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 1358 (const_int 0) 1359 (minus:SI (match_dup 4) (match_dup 3)))) 1360 (set (match_operand:SI 0 "gpc_reg_operand" "") 1361 (minus:SI (match_dup 2) (match_dup 3)))] 1362 "TARGET_POWER || TARGET_ISEL" 1363 " 1364{ 1365 if (TARGET_ISEL) 1366 { 1367 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); 1368 DONE; 1369 } 1370 operands[3] = gen_reg_rtx (SImode); 1371 operands[4] = gen_reg_rtx (SImode); 1372 operands[5] = GEN_INT (-2147483647 - 1); 1373}") 1374 1375(define_expand "umaxsi3" 1376 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1377 (match_dup 5))) 1378 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 1379 (match_dup 5))) 1380 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 1381 (const_int 0) 1382 (minus:SI (match_dup 4) (match_dup 3)))) 1383 (set (match_operand:SI 0 "gpc_reg_operand" "") 1384 (plus:SI (match_dup 3) (match_dup 1)))] 1385 "TARGET_POWER || TARGET_ISEL" 1386 " 1387{ 1388 if (TARGET_ISEL) 1389 { 1390 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); 1391 DONE; 1392 } 1393 operands[3] = gen_reg_rtx (SImode); 1394 operands[4] = gen_reg_rtx (SImode); 1395 operands[5] = GEN_INT (-2147483647 - 1); 1396}") 1397 1398(define_insn "" 1399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1400 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 1401 (match_operand:SI 2 "reg_or_short_operand" "rI")) 1402 (const_int 0) 1403 (minus:SI (match_dup 2) (match_dup 1))))] 1404 "TARGET_POWER" 1405 "doz%I2 %0,%1,%2") 1406 1407(define_insn "" 1408 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1409 (compare:CC 1410 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") 1411 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 1412 (const_int 0) 1413 (minus:SI (match_dup 2) (match_dup 1))) 1414 (const_int 0))) 1415 (clobber (match_scratch:SI 3 "=r,r"))] 1416 "TARGET_POWER" 1417 "@ 1418 doz%I2. %3,%1,%2 1419 #" 1420 [(set_attr "type" "delayed_compare") 1421 (set_attr "length" "4,8")]) 1422 1423(define_split 1424 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1425 (compare:CC 1426 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") 1427 (match_operand:SI 2 "reg_or_short_operand" "")) 1428 (const_int 0) 1429 (minus:SI (match_dup 2) (match_dup 1))) 1430 (const_int 0))) 1431 (clobber (match_scratch:SI 3 ""))] 1432 "TARGET_POWER && reload_completed" 1433 [(set (match_dup 3) 1434 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1435 (const_int 0) 1436 (minus:SI (match_dup 2) (match_dup 1)))) 1437 (set (match_dup 0) 1438 (compare:CC (match_dup 3) 1439 (const_int 0)))] 1440 "") 1441 1442(define_insn "" 1443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1444 (compare:CC 1445 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") 1446 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 1447 (const_int 0) 1448 (minus:SI (match_dup 2) (match_dup 1))) 1449 (const_int 0))) 1450 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1451 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1452 (const_int 0) 1453 (minus:SI (match_dup 2) (match_dup 1))))] 1454 "TARGET_POWER" 1455 "@ 1456 doz%I2. %0,%1,%2 1457 #" 1458 [(set_attr "type" "delayed_compare") 1459 (set_attr "length" "4,8")]) 1460 1461(define_split 1462 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1463 (compare:CC 1464 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") 1465 (match_operand:SI 2 "reg_or_short_operand" "")) 1466 (const_int 0) 1467 (minus:SI (match_dup 2) (match_dup 1))) 1468 (const_int 0))) 1469 (set (match_operand:SI 0 "gpc_reg_operand" "") 1470 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1471 (const_int 0) 1472 (minus:SI (match_dup 2) (match_dup 1))))] 1473 "TARGET_POWER && reload_completed" 1474 [(set (match_dup 0) 1475 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 1476 (const_int 0) 1477 (minus:SI (match_dup 2) (match_dup 1)))) 1478 (set (match_dup 3) 1479 (compare:CC (match_dup 0) 1480 (const_int 0)))] 1481 "") 1482 1483;; We don't need abs with condition code because such comparisons should 1484;; never be done. 1485(define_expand "abssi2" 1486 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1487 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] 1488 "" 1489 " 1490{ 1491 if (TARGET_ISEL) 1492 { 1493 emit_insn (gen_abssi2_isel (operands[0], operands[1])); 1494 DONE; 1495 } 1496 else if (! TARGET_POWER) 1497 { 1498 emit_insn (gen_abssi2_nopower (operands[0], operands[1])); 1499 DONE; 1500 } 1501}") 1502 1503(define_insn "*abssi2_power" 1504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1505 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1506 "TARGET_POWER" 1507 "abs %0,%1") 1508 1509(define_insn_and_split "abssi2_isel" 1510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1511 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 1512 (clobber (match_scratch:SI 2 "=&b")) 1513 (clobber (match_scratch:CC 3 "=y"))] 1514 "TARGET_ISEL" 1515 "#" 1516 "&& reload_completed" 1517 [(set (match_dup 2) (neg:SI (match_dup 1))) 1518 (set (match_dup 3) 1519 (compare:CC (match_dup 1) 1520 (const_int 0))) 1521 (set (match_dup 0) 1522 (if_then_else:SI (ge (match_dup 3) 1523 (const_int 0)) 1524 (match_dup 1) 1525 (match_dup 2)))] 1526 "") 1527 1528(define_insn_and_split "abssi2_nopower" 1529 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 1530 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) 1531 (clobber (match_scratch:SI 2 "=&r,&r"))] 1532 "! TARGET_POWER && ! TARGET_ISEL" 1533 "#" 1534 "&& reload_completed" 1535 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 1536 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) 1537 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] 1538 "") 1539 1540(define_insn "*nabs_power" 1541 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1542 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] 1543 "TARGET_POWER" 1544 "nabs %0,%1") 1545 1546(define_insn_and_split "*nabs_nopower" 1547 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 1548 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) 1549 (clobber (match_scratch:SI 2 "=&r,&r"))] 1550 "! TARGET_POWER" 1551 "#" 1552 "&& reload_completed" 1553 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 1554 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) 1555 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] 1556 "") 1557 1558(define_insn "negsi2" 1559 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1560 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1561 "" 1562 "neg %0,%1") 1563 1564(define_insn "" 1565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1566 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1567 (const_int 0))) 1568 (clobber (match_scratch:SI 2 "=r,r"))] 1569 "TARGET_32BIT" 1570 "@ 1571 neg. %2,%1 1572 #" 1573 [(set_attr "type" "fast_compare") 1574 (set_attr "length" "4,8")]) 1575 1576(define_split 1577 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1578 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) 1579 (const_int 0))) 1580 (clobber (match_scratch:SI 2 ""))] 1581 "TARGET_32BIT && reload_completed" 1582 [(set (match_dup 2) 1583 (neg:SI (match_dup 1))) 1584 (set (match_dup 0) 1585 (compare:CC (match_dup 2) 1586 (const_int 0)))] 1587 "") 1588 1589(define_insn "" 1590 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1591 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1592 (const_int 0))) 1593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1594 (neg:SI (match_dup 1)))] 1595 "TARGET_32BIT" 1596 "@ 1597 neg. %0,%1 1598 #" 1599 [(set_attr "type" "fast_compare") 1600 (set_attr "length" "4,8")]) 1601 1602(define_split 1603 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1604 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) 1605 (const_int 0))) 1606 (set (match_operand:SI 0 "gpc_reg_operand" "") 1607 (neg:SI (match_dup 1)))] 1608 "TARGET_32BIT && reload_completed" 1609 [(set (match_dup 0) 1610 (neg:SI (match_dup 1))) 1611 (set (match_dup 2) 1612 (compare:CC (match_dup 0) 1613 (const_int 0)))] 1614 "") 1615 1616(define_insn "clzsi2" 1617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1618 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1619 "" 1620 "{cntlz|cntlzw} %0,%1") 1621 1622(define_expand "ctzsi2" 1623 [(set (match_dup 2) 1624 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 1625 (parallel [(set (match_dup 3) (and:SI (match_dup 1) 1626 (match_dup 2))) 1627 (clobber (scratch:CC))]) 1628 (set (match_dup 4) (clz:SI (match_dup 3))) 1629 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1630 (minus:SI (const_int 31) (match_dup 4)))] 1631 "" 1632 { 1633 operands[2] = gen_reg_rtx (SImode); 1634 operands[3] = gen_reg_rtx (SImode); 1635 operands[4] = gen_reg_rtx (SImode); 1636 }) 1637 1638(define_expand "ffssi2" 1639 [(set (match_dup 2) 1640 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 1641 (parallel [(set (match_dup 3) (and:SI (match_dup 1) 1642 (match_dup 2))) 1643 (clobber (scratch:CC))]) 1644 (set (match_dup 4) (clz:SI (match_dup 3))) 1645 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1646 (minus:SI (const_int 32) (match_dup 4)))] 1647 "" 1648 { 1649 operands[2] = gen_reg_rtx (SImode); 1650 operands[3] = gen_reg_rtx (SImode); 1651 operands[4] = gen_reg_rtx (SImode); 1652 }) 1653 1654(define_expand "mulsi3" 1655 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 1656 (use (match_operand:SI 1 "gpc_reg_operand" "")) 1657 (use (match_operand:SI 2 "reg_or_short_operand" ""))] 1658 "" 1659 " 1660{ 1661 if (TARGET_POWER) 1662 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); 1663 else 1664 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); 1665 DONE; 1666}") 1667 1668(define_insn "mulsi3_mq" 1669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1670 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1671 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 1672 (clobber (match_scratch:SI 3 "=q,q"))] 1673 "TARGET_POWER" 1674 "@ 1675 {muls|mullw} %0,%1,%2 1676 {muli|mulli} %0,%1,%2" 1677 [(set (attr "type") 1678 (cond [(match_operand:SI 2 "s8bit_cint_operand" "") 1679 (const_string "imul3") 1680 (match_operand:SI 2 "short_cint_operand" "") 1681 (const_string "imul2")] 1682 (const_string "imul")))]) 1683 1684(define_insn "mulsi3_no_mq" 1685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1686 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1687 (match_operand:SI 2 "reg_or_short_operand" "r,I")))] 1688 "! TARGET_POWER" 1689 "@ 1690 {muls|mullw} %0,%1,%2 1691 {muli|mulli} %0,%1,%2" 1692 [(set (attr "type") 1693 (cond [(match_operand:SI 2 "s8bit_cint_operand" "") 1694 (const_string "imul3") 1695 (match_operand:SI 2 "short_cint_operand" "") 1696 (const_string "imul2")] 1697 (const_string "imul")))]) 1698 1699(define_insn "*mulsi3_mq_internal1" 1700 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1701 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1702 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1703 (const_int 0))) 1704 (clobber (match_scratch:SI 3 "=r,r")) 1705 (clobber (match_scratch:SI 4 "=q,q"))] 1706 "TARGET_POWER" 1707 "@ 1708 {muls.|mullw.} %3,%1,%2 1709 #" 1710 [(set_attr "type" "imul_compare") 1711 (set_attr "length" "4,8")]) 1712 1713(define_split 1714 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1715 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 1716 (match_operand:SI 2 "gpc_reg_operand" "")) 1717 (const_int 0))) 1718 (clobber (match_scratch:SI 3 "")) 1719 (clobber (match_scratch:SI 4 ""))] 1720 "TARGET_POWER && reload_completed" 1721 [(parallel [(set (match_dup 3) 1722 (mult:SI (match_dup 1) (match_dup 2))) 1723 (clobber (match_dup 4))]) 1724 (set (match_dup 0) 1725 (compare:CC (match_dup 3) 1726 (const_int 0)))] 1727 "") 1728 1729(define_insn "*mulsi3_no_mq_internal1" 1730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1731 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1732 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1733 (const_int 0))) 1734 (clobber (match_scratch:SI 3 "=r,r"))] 1735 "! TARGET_POWER" 1736 "@ 1737 {muls.|mullw.} %3,%1,%2 1738 #" 1739 [(set_attr "type" "imul_compare") 1740 (set_attr "length" "4,8")]) 1741 1742(define_split 1743 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1744 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 1745 (match_operand:SI 2 "gpc_reg_operand" "")) 1746 (const_int 0))) 1747 (clobber (match_scratch:SI 3 ""))] 1748 "! TARGET_POWER && reload_completed" 1749 [(set (match_dup 3) 1750 (mult:SI (match_dup 1) (match_dup 2))) 1751 (set (match_dup 0) 1752 (compare:CC (match_dup 3) 1753 (const_int 0)))] 1754 "") 1755 1756(define_insn "*mulsi3_mq_internal2" 1757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1758 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1759 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1760 (const_int 0))) 1761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1762 (mult:SI (match_dup 1) (match_dup 2))) 1763 (clobber (match_scratch:SI 4 "=q,q"))] 1764 "TARGET_POWER" 1765 "@ 1766 {muls.|mullw.} %0,%1,%2 1767 #" 1768 [(set_attr "type" "imul_compare") 1769 (set_attr "length" "4,8")]) 1770 1771(define_split 1772 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1773 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 1774 (match_operand:SI 2 "gpc_reg_operand" "")) 1775 (const_int 0))) 1776 (set (match_operand:SI 0 "gpc_reg_operand" "") 1777 (mult:SI (match_dup 1) (match_dup 2))) 1778 (clobber (match_scratch:SI 4 ""))] 1779 "TARGET_POWER && reload_completed" 1780 [(parallel [(set (match_dup 0) 1781 (mult:SI (match_dup 1) (match_dup 2))) 1782 (clobber (match_dup 4))]) 1783 (set (match_dup 3) 1784 (compare:CC (match_dup 0) 1785 (const_int 0)))] 1786 "") 1787 1788(define_insn "*mulsi3_no_mq_internal2" 1789 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1790 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 1791 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1792 (const_int 0))) 1793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1794 (mult:SI (match_dup 1) (match_dup 2)))] 1795 "! TARGET_POWER" 1796 "@ 1797 {muls.|mullw.} %0,%1,%2 1798 #" 1799 [(set_attr "type" "imul_compare") 1800 (set_attr "length" "4,8")]) 1801 1802(define_split 1803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1804 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 1805 (match_operand:SI 2 "gpc_reg_operand" "")) 1806 (const_int 0))) 1807 (set (match_operand:SI 0 "gpc_reg_operand" "") 1808 (mult:SI (match_dup 1) (match_dup 2)))] 1809 "! TARGET_POWER && reload_completed" 1810 [(set (match_dup 0) 1811 (mult:SI (match_dup 1) (match_dup 2))) 1812 (set (match_dup 3) 1813 (compare:CC (match_dup 0) 1814 (const_int 0)))] 1815 "") 1816 1817;; Operand 1 is divided by operand 2; quotient goes to operand 1818;; 0 and remainder to operand 3. 1819;; ??? At some point, see what, if anything, we can do about if (x % y == 0). 1820 1821(define_expand "divmodsi4" 1822 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 1823 (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 1824 (match_operand:SI 2 "gpc_reg_operand" ""))) 1825 (set (match_operand:SI 3 "register_operand" "") 1826 (mod:SI (match_dup 1) (match_dup 2)))])] 1827 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" 1828 " 1829{ 1830 if (! TARGET_POWER && ! TARGET_POWERPC) 1831 { 1832 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 1833 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 1834 emit_insn (gen_divss_call ()); 1835 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 1836 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); 1837 DONE; 1838 } 1839}") 1840 1841(define_insn "*divmodsi4_internal" 1842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1843 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1844 (match_operand:SI 2 "gpc_reg_operand" "r"))) 1845 (set (match_operand:SI 3 "register_operand" "=q") 1846 (mod:SI (match_dup 1) (match_dup 2)))] 1847 "TARGET_POWER" 1848 "divs %0,%1,%2" 1849 [(set_attr "type" "idiv")]) 1850 1851(define_expand "udivsi3" 1852 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1853 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 1854 (match_operand:SI 2 "gpc_reg_operand" "")))] 1855 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" 1856 " 1857{ 1858 if (! TARGET_POWER && ! TARGET_POWERPC) 1859 { 1860 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 1861 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 1862 emit_insn (gen_quous_call ()); 1863 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 1864 DONE; 1865 } 1866 else if (TARGET_POWER) 1867 { 1868 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); 1869 DONE; 1870 } 1871}") 1872 1873(define_insn "udivsi3_mq" 1874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1875 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1876 (match_operand:SI 2 "gpc_reg_operand" "r"))) 1877 (clobber (match_scratch:SI 3 "=q"))] 1878 "TARGET_POWERPC && TARGET_POWER" 1879 "divwu %0,%1,%2" 1880 [(set_attr "type" "idiv")]) 1881 1882(define_insn "*udivsi3_no_mq" 1883 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1884 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1885 (match_operand:SI 2 "gpc_reg_operand" "r")))] 1886 "TARGET_POWERPC && ! TARGET_POWER" 1887 "divwu %0,%1,%2" 1888 [(set_attr "type" "idiv")]) 1889 1890;; For powers of two we can do srai/aze for divide and then adjust for 1891;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be 1892;; used; for PowerPC, force operands into register and do a normal divide; 1893;; for AIX common-mode, use quoss call on register operands. 1894(define_expand "divsi3" 1895 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1896 (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 1897 (match_operand:SI 2 "reg_or_cint_operand" "")))] 1898 "" 1899 " 1900{ 1901 if (GET_CODE (operands[2]) == CONST_INT 1902 && INTVAL (operands[2]) > 0 1903 && exact_log2 (INTVAL (operands[2])) >= 0) 1904 ; 1905 else if (TARGET_POWERPC) 1906 { 1907 operands[2] = force_reg (SImode, operands[2]); 1908 if (TARGET_POWER) 1909 { 1910 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); 1911 DONE; 1912 } 1913 } 1914 else if (TARGET_POWER) 1915 FAIL; 1916 else 1917 { 1918 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 1919 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 1920 emit_insn (gen_quoss_call ()); 1921 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 1922 DONE; 1923 } 1924}") 1925 1926(define_insn "divsi3_mq" 1927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1928 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1929 (match_operand:SI 2 "gpc_reg_operand" "r"))) 1930 (clobber (match_scratch:SI 3 "=q"))] 1931 "TARGET_POWERPC && TARGET_POWER" 1932 "divw %0,%1,%2" 1933 [(set_attr "type" "idiv")]) 1934 1935(define_insn "*divsi3_no_mq" 1936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1937 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1938 (match_operand:SI 2 "gpc_reg_operand" "r")))] 1939 "TARGET_POWERPC && ! TARGET_POWER" 1940 "divw %0,%1,%2" 1941 [(set_attr "type" "idiv")]) 1942 1943(define_expand "modsi3" 1944 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 1945 (use (match_operand:SI 1 "gpc_reg_operand" "")) 1946 (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 1947 "" 1948 " 1949{ 1950 int i; 1951 rtx temp1; 1952 rtx temp2; 1953 1954 if (GET_CODE (operands[2]) != CONST_INT 1955 || INTVAL (operands[2]) <= 0 1956 || (i = exact_log2 (INTVAL (operands[2]))) < 0) 1957 FAIL; 1958 1959 temp1 = gen_reg_rtx (SImode); 1960 temp2 = gen_reg_rtx (SImode); 1961 1962 emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); 1963 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); 1964 emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); 1965 DONE; 1966}") 1967 1968(define_insn "" 1969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1970 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 1971 (match_operand:SI 2 "exact_log2_cint_operand" "N")))] 1972 "" 1973 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" 1974 [(set_attr "length" "8")]) 1975 1976(define_insn "" 1977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1978 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1979 (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) 1980 (const_int 0))) 1981 (clobber (match_scratch:SI 3 "=r,r"))] 1982 "" 1983 "@ 1984 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 1985 #" 1986 [(set_attr "type" "compare") 1987 (set_attr "length" "8,12")]) 1988 1989(define_split 1990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1991 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 1992 (match_operand:SI 2 "exact_log2_cint_operand" "")) 1993 (const_int 0))) 1994 (clobber (match_scratch:SI 3 ""))] 1995 "reload_completed" 1996 [(set (match_dup 3) 1997 (div:SI (match_dup 1) (match_dup 2))) 1998 (set (match_dup 0) 1999 (compare:CC (match_dup 3) 2000 (const_int 0)))] 2001 "") 2002 2003(define_insn "" 2004 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2005 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2006 (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) 2007 (const_int 0))) 2008 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2009 (div:SI (match_dup 1) (match_dup 2)))] 2010 "" 2011 "@ 2012 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 2013 #" 2014 [(set_attr "type" "compare") 2015 (set_attr "length" "8,12")]) 2016 2017(define_split 2018 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2019 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 2020 (match_operand:SI 2 "exact_log2_cint_operand" "")) 2021 (const_int 0))) 2022 (set (match_operand:SI 0 "gpc_reg_operand" "") 2023 (div:SI (match_dup 1) (match_dup 2)))] 2024 "reload_completed" 2025 [(set (match_dup 0) 2026 (div:SI (match_dup 1) (match_dup 2))) 2027 (set (match_dup 3) 2028 (compare:CC (match_dup 0) 2029 (const_int 0)))] 2030 "") 2031 2032(define_insn "" 2033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2034 (udiv:SI 2035 (plus:DI (ashift:DI 2036 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 2037 (const_int 32)) 2038 (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) 2039 (match_operand:SI 3 "gpc_reg_operand" "r"))) 2040 (set (match_operand:SI 2 "register_operand" "=*q") 2041 (umod:SI 2042 (plus:DI (ashift:DI 2043 (zero_extend:DI (match_dup 1)) (const_int 32)) 2044 (zero_extend:DI (match_dup 4))) 2045 (match_dup 3)))] 2046 "TARGET_POWER" 2047 "div %0,%1,%3" 2048 [(set_attr "type" "idiv")]) 2049 2050;; To do unsigned divide we handle the cases of the divisor looking like a 2051;; negative number. If it is a constant that is less than 2**31, we don't 2052;; have to worry about the branches. So make a few subroutines here. 2053;; 2054;; First comes the normal case. 2055(define_expand "udivmodsi4_normal" 2056 [(set (match_dup 4) (const_int 0)) 2057 (parallel [(set (match_operand:SI 0 "" "") 2058 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 2059 (const_int 32)) 2060 (zero_extend:DI (match_operand:SI 1 "" ""))) 2061 (match_operand:SI 2 "" ""))) 2062 (set (match_operand:SI 3 "" "") 2063 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 2064 (const_int 32)) 2065 (zero_extend:DI (match_dup 1))) 2066 (match_dup 2)))])] 2067 "TARGET_POWER" 2068 " 2069{ operands[4] = gen_reg_rtx (SImode); }") 2070 2071;; This handles the branches. 2072(define_expand "udivmodsi4_tests" 2073 [(set (match_operand:SI 0 "" "") (const_int 0)) 2074 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) 2075 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) 2076 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) 2077 (label_ref (match_operand:SI 4 "" "")) (pc))) 2078 (set (match_dup 0) (const_int 1)) 2079 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) 2080 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) 2081 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) 2082 (label_ref (match_dup 4)) (pc)))] 2083 "TARGET_POWER" 2084 " 2085{ operands[5] = gen_reg_rtx (CCUNSmode); 2086 operands[6] = gen_reg_rtx (CCmode); 2087}") 2088 2089(define_expand "udivmodsi4" 2090 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 2091 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 2092 (match_operand:SI 2 "reg_or_cint_operand" ""))) 2093 (set (match_operand:SI 3 "gpc_reg_operand" "") 2094 (umod:SI (match_dup 1) (match_dup 2)))])] 2095 "" 2096 " 2097{ 2098 rtx label = 0; 2099 2100 if (! TARGET_POWER) 2101 { 2102 if (! TARGET_POWERPC) 2103 { 2104 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 2105 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 2106 emit_insn (gen_divus_call ()); 2107 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 2108 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); 2109 DONE; 2110 } 2111 else 2112 FAIL; 2113 } 2114 2115 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) 2116 { 2117 operands[2] = force_reg (SImode, operands[2]); 2118 label = gen_label_rtx (); 2119 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], 2120 operands[3], label)); 2121 } 2122 else 2123 operands[2] = force_reg (SImode, operands[2]); 2124 2125 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], 2126 operands[3])); 2127 if (label) 2128 emit_label (label); 2129 2130 DONE; 2131}") 2132 2133;; AIX architecture-independent common-mode multiply (DImode), 2134;; divide/modulus, and quotient subroutine calls. Input operands in R3 and 2135;; R4; results in R3 and sometimes R4; link register always clobbered by bla 2136;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but 2137;; assumed unused if generating common-mode, so ignore. 2138(define_insn "mulh_call" 2139 [(set (reg:SI 3) 2140 (truncate:SI 2141 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) 2142 (sign_extend:DI (reg:SI 4))) 2143 (const_int 32)))) 2144 (clobber (match_scratch:SI 0 "=l"))] 2145 "! TARGET_POWER && ! TARGET_POWERPC" 2146 "bla __mulh" 2147 [(set_attr "type" "imul")]) 2148 2149(define_insn "mull_call" 2150 [(set (reg:DI 3) 2151 (mult:DI (sign_extend:DI (reg:SI 3)) 2152 (sign_extend:DI (reg:SI 4)))) 2153 (clobber (match_scratch:SI 0 "=l")) 2154 (clobber (reg:SI 0))] 2155 "! TARGET_POWER && ! TARGET_POWERPC" 2156 "bla __mull" 2157 [(set_attr "type" "imul")]) 2158 2159(define_insn "divss_call" 2160 [(set (reg:SI 3) 2161 (div:SI (reg:SI 3) (reg:SI 4))) 2162 (set (reg:SI 4) 2163 (mod:SI (reg:SI 3) (reg:SI 4))) 2164 (clobber (match_scratch:SI 0 "=l")) 2165 (clobber (reg:SI 0))] 2166 "! TARGET_POWER && ! TARGET_POWERPC" 2167 "bla __divss" 2168 [(set_attr "type" "idiv")]) 2169 2170(define_insn "divus_call" 2171 [(set (reg:SI 3) 2172 (udiv:SI (reg:SI 3) (reg:SI 4))) 2173 (set (reg:SI 4) 2174 (umod:SI (reg:SI 3) (reg:SI 4))) 2175 (clobber (match_scratch:SI 0 "=l")) 2176 (clobber (reg:SI 0)) 2177 (clobber (match_scratch:CC 1 "=x")) 2178 (clobber (reg:CC 69))] 2179 "! TARGET_POWER && ! TARGET_POWERPC" 2180 "bla __divus" 2181 [(set_attr "type" "idiv")]) 2182 2183(define_insn "quoss_call" 2184 [(set (reg:SI 3) 2185 (div:SI (reg:SI 3) (reg:SI 4))) 2186 (clobber (match_scratch:SI 0 "=l"))] 2187 "! TARGET_POWER && ! TARGET_POWERPC" 2188 "bla __quoss" 2189 [(set_attr "type" "idiv")]) 2190 2191(define_insn "quous_call" 2192 [(set (reg:SI 3) 2193 (udiv:SI (reg:SI 3) (reg:SI 4))) 2194 (clobber (match_scratch:SI 0 "=l")) 2195 (clobber (reg:SI 0)) 2196 (clobber (match_scratch:CC 1 "=x")) 2197 (clobber (reg:CC 69))] 2198 "! TARGET_POWER && ! TARGET_POWERPC" 2199 "bla __quous" 2200 [(set_attr "type" "idiv")]) 2201 2202;; Logical instructions 2203;; The logical instructions are mostly combined by using match_operator, 2204;; but the plain AND insns are somewhat different because there is no 2205;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all 2206;; those rotate-and-mask operations. Thus, the AND insns come first. 2207 2208(define_insn "andsi3" 2209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 2210 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 2211 (match_operand:SI 2 "and_operand" "?r,T,K,L"))) 2212 (clobber (match_scratch:CC 3 "=X,X,x,x"))] 2213 "" 2214 "@ 2215 and %0,%1,%2 2216 {rlinm|rlwinm} %0,%1,0,%m2,%M2 2217 {andil.|andi.} %0,%1,%b2 2218 {andiu.|andis.} %0,%1,%u2") 2219 2220;; Note to set cr's other than cr0 we do the and immediate and then 2221;; the test again -- this avoids a mfcr which on the higher end 2222;; machines causes an execution serialization 2223 2224(define_insn "*andsi3_internal2" 2225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2226 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2227 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2228 (const_int 0))) 2229 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) 2230 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2231 "TARGET_32BIT" 2232 "@ 2233 and. %3,%1,%2 2234 {andil.|andi.} %3,%1,%b2 2235 {andiu.|andis.} %3,%1,%u2 2236 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 2237 # 2238 # 2239 # 2240 #" 2241 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2242 (set_attr "length" "4,4,4,4,8,8,8,8")]) 2243 2244(define_insn "*andsi3_internal3" 2245 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2246 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2247 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2248 (const_int 0))) 2249 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) 2250 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2251 "TARGET_64BIT" 2252 "@ 2253 # 2254 {andil.|andi.} %3,%1,%b2 2255 {andiu.|andis.} %3,%1,%u2 2256 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 2257 # 2258 # 2259 # 2260 #" 2261 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2262 (set_attr "length" "8,4,4,4,8,8,8,8")]) 2263 2264(define_split 2265 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2266 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2267 (match_operand:SI 2 "and_operand" "")) 2268 (const_int 0))) 2269 (clobber (match_scratch:SI 3 "")) 2270 (clobber (match_scratch:CC 4 ""))] 2271 "reload_completed" 2272 [(parallel [(set (match_dup 3) 2273 (and:SI (match_dup 1) 2274 (match_dup 2))) 2275 (clobber (match_dup 4))]) 2276 (set (match_dup 0) 2277 (compare:CC (match_dup 3) 2278 (const_int 0)))] 2279 "") 2280 2281;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the 2282;; whole 64 bit reg, and we don't know what is in the high 32 bits. 2283 2284(define_split 2285 [(set (match_operand:CC 0 "cc_reg_operand" "") 2286 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2287 (match_operand:SI 2 "gpc_reg_operand" "")) 2288 (const_int 0))) 2289 (clobber (match_scratch:SI 3 "")) 2290 (clobber (match_scratch:CC 4 ""))] 2291 "TARGET_POWERPC64 && reload_completed" 2292 [(parallel [(set (match_dup 3) 2293 (and:SI (match_dup 1) 2294 (match_dup 2))) 2295 (clobber (match_dup 4))]) 2296 (set (match_dup 0) 2297 (compare:CC (match_dup 3) 2298 (const_int 0)))] 2299 "") 2300 2301(define_insn "*andsi3_internal4" 2302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2303 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2304 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2305 (const_int 0))) 2306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") 2307 (and:SI (match_dup 1) 2308 (match_dup 2))) 2309 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2310 "TARGET_32BIT" 2311 "@ 2312 and. %0,%1,%2 2313 {andil.|andi.} %0,%1,%b2 2314 {andiu.|andis.} %0,%1,%u2 2315 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 2316 # 2317 # 2318 # 2319 #" 2320 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2321 (set_attr "length" "4,4,4,4,8,8,8,8")]) 2322 2323(define_insn "*andsi3_internal5" 2324 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2326 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2327 (const_int 0))) 2328 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") 2329 (and:SI (match_dup 1) 2330 (match_dup 2))) 2331 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2332 "TARGET_64BIT" 2333 "@ 2334 # 2335 {andil.|andi.} %0,%1,%b2 2336 {andiu.|andis.} %0,%1,%u2 2337 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 2338 # 2339 # 2340 # 2341 #" 2342 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2343 (set_attr "length" "8,4,4,4,8,8,8,8")]) 2344 2345(define_split 2346 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2347 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2348 (match_operand:SI 2 "and_operand" "")) 2349 (const_int 0))) 2350 (set (match_operand:SI 0 "gpc_reg_operand" "") 2351 (and:SI (match_dup 1) 2352 (match_dup 2))) 2353 (clobber (match_scratch:CC 4 ""))] 2354 "reload_completed" 2355 [(parallel [(set (match_dup 0) 2356 (and:SI (match_dup 1) 2357 (match_dup 2))) 2358 (clobber (match_dup 4))]) 2359 (set (match_dup 3) 2360 (compare:CC (match_dup 0) 2361 (const_int 0)))] 2362 "") 2363 2364(define_split 2365 [(set (match_operand:CC 3 "cc_reg_operand" "") 2366 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2367 (match_operand:SI 2 "gpc_reg_operand" "")) 2368 (const_int 0))) 2369 (set (match_operand:SI 0 "gpc_reg_operand" "") 2370 (and:SI (match_dup 1) 2371 (match_dup 2))) 2372 (clobber (match_scratch:CC 4 ""))] 2373 "TARGET_POWERPC64 && reload_completed" 2374 [(parallel [(set (match_dup 0) 2375 (and:SI (match_dup 1) 2376 (match_dup 2))) 2377 (clobber (match_dup 4))]) 2378 (set (match_dup 3) 2379 (compare:CC (match_dup 0) 2380 (const_int 0)))] 2381 "") 2382 2383;; Handle the PowerPC64 rlwinm corner case 2384 2385(define_insn_and_split "*andsi3_internal6" 2386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2387 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2388 (match_operand:SI 2 "mask_operand_wrap" "i")))] 2389 "TARGET_POWERPC64" 2390 "#" 2391 "TARGET_POWERPC64" 2392 [(set (match_dup 0) 2393 (and:SI (rotate:SI (match_dup 1) (match_dup 3)) 2394 (match_dup 4))) 2395 (set (match_dup 0) 2396 (rotate:SI (match_dup 0) (match_dup 5)))] 2397 " 2398{ 2399 int mb = extract_MB (operands[2]); 2400 int me = extract_ME (operands[2]); 2401 operands[3] = GEN_INT (me + 1); 2402 operands[5] = GEN_INT (32 - (me + 1)); 2403 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); 2404}" 2405 [(set_attr "length" "8")]) 2406 2407(define_expand "iorsi3" 2408 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2409 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") 2410 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] 2411 "" 2412 " 2413{ 2414 if (GET_CODE (operands[2]) == CONST_INT 2415 && ! logical_operand (operands[2], SImode)) 2416 { 2417 HOST_WIDE_INT value = INTVAL (operands[2]); 2418 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 2419 ? operands[0] : gen_reg_rtx (SImode)); 2420 2421 emit_insn (gen_iorsi3 (tmp, operands[1], 2422 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 2423 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 2424 DONE; 2425 } 2426}") 2427 2428(define_expand "xorsi3" 2429 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2430 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 2431 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] 2432 "" 2433 " 2434{ 2435 if (GET_CODE (operands[2]) == CONST_INT 2436 && ! logical_operand (operands[2], SImode)) 2437 { 2438 HOST_WIDE_INT value = INTVAL (operands[2]); 2439 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 2440 ? operands[0] : gen_reg_rtx (SImode)); 2441 2442 emit_insn (gen_xorsi3 (tmp, operands[1], 2443 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 2444 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 2445 DONE; 2446 } 2447}") 2448 2449(define_insn "*boolsi3_internal1" 2450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 2451 (match_operator:SI 3 "boolean_or_operator" 2452 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 2453 (match_operand:SI 2 "logical_operand" "r,K,L")]))] 2454 "" 2455 "@ 2456 %q3 %0,%1,%2 2457 {%q3il|%q3i} %0,%1,%b2 2458 {%q3iu|%q3is} %0,%1,%u2") 2459 2460(define_insn "*boolsi3_internal2" 2461 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2462 (compare:CC (match_operator:SI 4 "boolean_or_operator" 2463 [(match_operand:SI 1 "gpc_reg_operand" "%r,r") 2464 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 2465 (const_int 0))) 2466 (clobber (match_scratch:SI 3 "=r,r"))] 2467 "TARGET_32BIT" 2468 "@ 2469 %q4. %3,%1,%2 2470 #" 2471 [(set_attr "type" "compare") 2472 (set_attr "length" "4,8")]) 2473 2474(define_split 2475 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2476 (compare:CC (match_operator:SI 4 "boolean_operator" 2477 [(match_operand:SI 1 "gpc_reg_operand" "") 2478 (match_operand:SI 2 "gpc_reg_operand" "")]) 2479 (const_int 0))) 2480 (clobber (match_scratch:SI 3 ""))] 2481 "TARGET_32BIT && reload_completed" 2482 [(set (match_dup 3) (match_dup 4)) 2483 (set (match_dup 0) 2484 (compare:CC (match_dup 3) 2485 (const_int 0)))] 2486 "") 2487 2488(define_insn "*boolsi3_internal3" 2489 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2490 (compare:CC (match_operator:SI 4 "boolean_operator" 2491 [(match_operand:SI 1 "gpc_reg_operand" "%r,r") 2492 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 2493 (const_int 0))) 2494 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2495 (match_dup 4))] 2496 "TARGET_32BIT" 2497 "@ 2498 %q4. %0,%1,%2 2499 #" 2500 [(set_attr "type" "compare") 2501 (set_attr "length" "4,8")]) 2502 2503(define_split 2504 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2505 (compare:CC (match_operator:SI 4 "boolean_operator" 2506 [(match_operand:SI 1 "gpc_reg_operand" "") 2507 (match_operand:SI 2 "gpc_reg_operand" "")]) 2508 (const_int 0))) 2509 (set (match_operand:SI 0 "gpc_reg_operand" "") 2510 (match_dup 4))] 2511 "TARGET_32BIT && reload_completed" 2512 [(set (match_dup 0) (match_dup 4)) 2513 (set (match_dup 3) 2514 (compare:CC (match_dup 0) 2515 (const_int 0)))] 2516 "") 2517 2518;; Split a logical operation that we can't do in one insn into two insns, 2519;; each of which does one 16-bit part. This is used by combine. 2520 2521(define_split 2522 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2523 (match_operator:SI 3 "boolean_or_operator" 2524 [(match_operand:SI 1 "gpc_reg_operand" "") 2525 (match_operand:SI 2 "non_logical_cint_operand" "")]))] 2526 "" 2527 [(set (match_dup 0) (match_dup 4)) 2528 (set (match_dup 0) (match_dup 5))] 2529" 2530{ 2531 rtx i; 2532 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); 2533 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, 2534 operands[1], i); 2535 i = GEN_INT (INTVAL (operands[2]) & 0xffff); 2536 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, 2537 operands[0], i); 2538}") 2539 2540(define_insn "*boolcsi3_internal1" 2541 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2542 (match_operator:SI 3 "boolean_operator" 2543 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 2544 (match_operand:SI 2 "gpc_reg_operand" "r")]))] 2545 "" 2546 "%q3 %0,%2,%1") 2547 2548(define_insn "*boolcsi3_internal2" 2549 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2550 (compare:CC (match_operator:SI 4 "boolean_operator" 2551 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 2552 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 2553 (const_int 0))) 2554 (clobber (match_scratch:SI 3 "=r,r"))] 2555 "TARGET_32BIT" 2556 "@ 2557 %q4. %3,%2,%1 2558 #" 2559 [(set_attr "type" "compare") 2560 (set_attr "length" "4,8")]) 2561 2562(define_split 2563 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2564 (compare:CC (match_operator:SI 4 "boolean_operator" 2565 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 2566 (match_operand:SI 2 "gpc_reg_operand" "")]) 2567 (const_int 0))) 2568 (clobber (match_scratch:SI 3 ""))] 2569 "TARGET_32BIT && reload_completed" 2570 [(set (match_dup 3) (match_dup 4)) 2571 (set (match_dup 0) 2572 (compare:CC (match_dup 3) 2573 (const_int 0)))] 2574 "") 2575 2576(define_insn "*boolcsi3_internal3" 2577 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2578 (compare:CC (match_operator:SI 4 "boolean_operator" 2579 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) 2580 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 2581 (const_int 0))) 2582 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2583 (match_dup 4))] 2584 "TARGET_32BIT" 2585 "@ 2586 %q4. %0,%2,%1 2587 #" 2588 [(set_attr "type" "compare") 2589 (set_attr "length" "4,8")]) 2590 2591(define_split 2592 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2593 (compare:CC (match_operator:SI 4 "boolean_operator" 2594 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 2595 (match_operand:SI 2 "gpc_reg_operand" "")]) 2596 (const_int 0))) 2597 (set (match_operand:SI 0 "gpc_reg_operand" "") 2598 (match_dup 4))] 2599 "TARGET_32BIT && reload_completed" 2600 [(set (match_dup 0) (match_dup 4)) 2601 (set (match_dup 3) 2602 (compare:CC (match_dup 0) 2603 (const_int 0)))] 2604 "") 2605 2606(define_insn "*boolccsi3_internal1" 2607 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2608 (match_operator:SI 3 "boolean_operator" 2609 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 2610 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] 2611 "" 2612 "%q3 %0,%1,%2") 2613 2614(define_insn "*boolccsi3_internal2" 2615 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2616 (compare:CC (match_operator:SI 4 "boolean_operator" 2617 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 2618 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) 2619 (const_int 0))) 2620 (clobber (match_scratch:SI 3 "=r,r"))] 2621 "TARGET_32BIT" 2622 "@ 2623 %q4. %3,%1,%2 2624 #" 2625 [(set_attr "type" "compare") 2626 (set_attr "length" "4,8")]) 2627 2628(define_split 2629 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2630 (compare:CC (match_operator:SI 4 "boolean_operator" 2631 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 2632 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) 2633 (const_int 0))) 2634 (clobber (match_scratch:SI 3 ""))] 2635 "TARGET_32BIT && reload_completed" 2636 [(set (match_dup 3) (match_dup 4)) 2637 (set (match_dup 0) 2638 (compare:CC (match_dup 3) 2639 (const_int 0)))] 2640 "") 2641 2642(define_insn "*boolccsi3_internal3" 2643 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2644 (compare:CC (match_operator:SI 4 "boolean_operator" 2645 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) 2646 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) 2647 (const_int 0))) 2648 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2649 (match_dup 4))] 2650 "TARGET_32BIT" 2651 "@ 2652 %q4. %0,%1,%2 2653 #" 2654 [(set_attr "type" "compare") 2655 (set_attr "length" "4,8")]) 2656 2657(define_split 2658 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2659 (compare:CC (match_operator:SI 4 "boolean_operator" 2660 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 2661 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) 2662 (const_int 0))) 2663 (set (match_operand:SI 0 "gpc_reg_operand" "") 2664 (match_dup 4))] 2665 "TARGET_32BIT && reload_completed" 2666 [(set (match_dup 0) (match_dup 4)) 2667 (set (match_dup 3) 2668 (compare:CC (match_dup 0) 2669 (const_int 0)))] 2670 "") 2671 2672;; maskir insn. We need four forms because things might be in arbitrary 2673;; orders. Don't define forms that only set CR fields because these 2674;; would modify an input register. 2675 2676(define_insn "*maskir_internal1" 2677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2678 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 2679 (match_operand:SI 1 "gpc_reg_operand" "0")) 2680 (and:SI (match_dup 2) 2681 (match_operand:SI 3 "gpc_reg_operand" "r"))))] 2682 "TARGET_POWER" 2683 "maskir %0,%3,%2") 2684 2685(define_insn "*maskir_internal2" 2686 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2687 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 2688 (match_operand:SI 1 "gpc_reg_operand" "0")) 2689 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 2690 (match_dup 2))))] 2691 "TARGET_POWER" 2692 "maskir %0,%3,%2") 2693 2694(define_insn "*maskir_internal3" 2695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2696 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") 2697 (match_operand:SI 3 "gpc_reg_operand" "r")) 2698 (and:SI (not:SI (match_dup 2)) 2699 (match_operand:SI 1 "gpc_reg_operand" "0"))))] 2700 "TARGET_POWER" 2701 "maskir %0,%3,%2") 2702 2703(define_insn "*maskir_internal4" 2704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2705 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 2706 (match_operand:SI 2 "gpc_reg_operand" "r")) 2707 (and:SI (not:SI (match_dup 2)) 2708 (match_operand:SI 1 "gpc_reg_operand" "0"))))] 2709 "TARGET_POWER" 2710 "maskir %0,%3,%2") 2711 2712(define_insn "*maskir_internal5" 2713 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 2714 (compare:CC 2715 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2716 (match_operand:SI 1 "gpc_reg_operand" "0,0")) 2717 (and:SI (match_dup 2) 2718 (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 2719 (const_int 0))) 2720 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2721 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 2722 (and:SI (match_dup 2) (match_dup 3))))] 2723 "TARGET_POWER" 2724 "@ 2725 maskir. %0,%3,%2 2726 #" 2727 [(set_attr "type" "compare") 2728 (set_attr "length" "4,8")]) 2729 2730(define_split 2731 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 2732 (compare:CC 2733 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) 2734 (match_operand:SI 1 "gpc_reg_operand" "")) 2735 (and:SI (match_dup 2) 2736 (match_operand:SI 3 "gpc_reg_operand" ""))) 2737 (const_int 0))) 2738 (set (match_operand:SI 0 "gpc_reg_operand" "") 2739 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 2740 (and:SI (match_dup 2) (match_dup 3))))] 2741 "TARGET_POWER && reload_completed" 2742 [(set (match_dup 0) 2743 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 2744 (and:SI (match_dup 2) (match_dup 3)))) 2745 (set (match_dup 4) 2746 (compare:CC (match_dup 0) 2747 (const_int 0)))] 2748 "") 2749 2750(define_insn "*maskir_internal6" 2751 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 2752 (compare:CC 2753 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2754 (match_operand:SI 1 "gpc_reg_operand" "0,0")) 2755 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") 2756 (match_dup 2))) 2757 (const_int 0))) 2758 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2759 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 2760 (and:SI (match_dup 3) (match_dup 2))))] 2761 "TARGET_POWER" 2762 "@ 2763 maskir. %0,%3,%2 2764 #" 2765 [(set_attr "type" "compare") 2766 (set_attr "length" "4,8")]) 2767 2768(define_split 2769 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 2770 (compare:CC 2771 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) 2772 (match_operand:SI 1 "gpc_reg_operand" "")) 2773 (and:SI (match_operand:SI 3 "gpc_reg_operand" "") 2774 (match_dup 2))) 2775 (const_int 0))) 2776 (set (match_operand:SI 0 "gpc_reg_operand" "") 2777 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 2778 (and:SI (match_dup 3) (match_dup 2))))] 2779 "TARGET_POWER && reload_completed" 2780 [(set (match_dup 0) 2781 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 2782 (and:SI (match_dup 3) (match_dup 2)))) 2783 (set (match_dup 4) 2784 (compare:CC (match_dup 0) 2785 (const_int 0)))] 2786 "") 2787 2788(define_insn "*maskir_internal7" 2789 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 2790 (compare:CC 2791 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") 2792 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 2793 (and:SI (not:SI (match_dup 2)) 2794 (match_operand:SI 1 "gpc_reg_operand" "0,0"))) 2795 (const_int 0))) 2796 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2797 (ior:SI (and:SI (match_dup 2) (match_dup 3)) 2798 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 2799 "TARGET_POWER" 2800 "@ 2801 maskir. %0,%3,%2 2802 #" 2803 [(set_attr "type" "compare") 2804 (set_attr "length" "4,8")]) 2805 2806(define_split 2807 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 2808 (compare:CC 2809 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") 2810 (match_operand:SI 3 "gpc_reg_operand" "")) 2811 (and:SI (not:SI (match_dup 2)) 2812 (match_operand:SI 1 "gpc_reg_operand" ""))) 2813 (const_int 0))) 2814 (set (match_operand:SI 0 "gpc_reg_operand" "") 2815 (ior:SI (and:SI (match_dup 2) (match_dup 3)) 2816 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 2817 "TARGET_POWER && reload_completed" 2818 [(set (match_dup 0) 2819 (ior:SI (and:SI (match_dup 2) (match_dup 3)) 2820 (and:SI (not:SI (match_dup 2)) (match_dup 1)))) 2821 (set (match_dup 4) 2822 (compare:CC (match_dup 0) 2823 (const_int 0)))] 2824 "") 2825 2826(define_insn "*maskir_internal8" 2827 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 2828 (compare:CC 2829 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") 2830 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2831 (and:SI (not:SI (match_dup 2)) 2832 (match_operand:SI 1 "gpc_reg_operand" "0,0"))) 2833 (const_int 0))) 2834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2835 (ior:SI (and:SI (match_dup 3) (match_dup 2)) 2836 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 2837 "TARGET_POWER" 2838 "@ 2839 maskir. %0,%3,%2 2840 #" 2841 [(set_attr "type" "compare") 2842 (set_attr "length" "4,8")]) 2843 2844(define_split 2845 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 2846 (compare:CC 2847 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") 2848 (match_operand:SI 2 "gpc_reg_operand" "")) 2849 (and:SI (not:SI (match_dup 2)) 2850 (match_operand:SI 1 "gpc_reg_operand" ""))) 2851 (const_int 0))) 2852 (set (match_operand:SI 0 "gpc_reg_operand" "") 2853 (ior:SI (and:SI (match_dup 3) (match_dup 2)) 2854 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 2855 "TARGET_POWER && reload_completed" 2856 [(set (match_dup 0) 2857 (ior:SI (and:SI (match_dup 3) (match_dup 2)) 2858 (and:SI (not:SI (match_dup 2)) (match_dup 1)))) 2859 (set (match_dup 4) 2860 (compare:CC (match_dup 0) 2861 (const_int 0)))] 2862 "") 2863 2864;; Rotate and shift insns, in all their variants. These support shifts, 2865;; field inserts and extracts, and various combinations thereof. 2866(define_expand "insv" 2867 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") 2868 (match_operand:SI 1 "const_int_operand" "") 2869 (match_operand:SI 2 "const_int_operand" "")) 2870 (match_operand 3 "gpc_reg_operand" ""))] 2871 "" 2872 " 2873{ 2874 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 2875 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 2876 compiler if the address of the structure is taken later. */ 2877 if (GET_CODE (operands[0]) == SUBREG 2878 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) 2879 FAIL; 2880 2881 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) 2882 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); 2883 else 2884 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); 2885 DONE; 2886}") 2887 2888(define_insn "insvsi" 2889 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2890 (match_operand:SI 1 "const_int_operand" "i") 2891 (match_operand:SI 2 "const_int_operand" "i")) 2892 (match_operand:SI 3 "gpc_reg_operand" "r"))] 2893 "" 2894 "* 2895{ 2896 int start = INTVAL (operands[2]) & 31; 2897 int size = INTVAL (operands[1]) & 31; 2898 2899 operands[4] = GEN_INT (32 - start - size); 2900 operands[1] = GEN_INT (start + size - 1); 2901 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 2902}" 2903 [(set_attr "type" "insert_word")]) 2904 2905(define_insn "*insvsi_internal1" 2906 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2907 (match_operand:SI 1 "const_int_operand" "i") 2908 (match_operand:SI 2 "const_int_operand" "i")) 2909 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") 2910 (match_operand:SI 4 "const_int_operand" "i")))] 2911 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 2912 "* 2913{ 2914 int shift = INTVAL (operands[4]) & 31; 2915 int start = INTVAL (operands[2]) & 31; 2916 int size = INTVAL (operands[1]) & 31; 2917 2918 operands[4] = GEN_INT (shift - start - size); 2919 operands[1] = GEN_INT (start + size - 1); 2920 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 2921}" 2922 [(set_attr "type" "insert_word")]) 2923 2924(define_insn "*insvsi_internal2" 2925 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2926 (match_operand:SI 1 "const_int_operand" "i") 2927 (match_operand:SI 2 "const_int_operand" "i")) 2928 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 2929 (match_operand:SI 4 "const_int_operand" "i")))] 2930 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 2931 "* 2932{ 2933 int shift = INTVAL (operands[4]) & 31; 2934 int start = INTVAL (operands[2]) & 31; 2935 int size = INTVAL (operands[1]) & 31; 2936 2937 operands[4] = GEN_INT (32 - shift - start - size); 2938 operands[1] = GEN_INT (start + size - 1); 2939 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 2940}" 2941 [(set_attr "type" "insert_word")]) 2942 2943(define_insn "*insvsi_internal3" 2944 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2945 (match_operand:SI 1 "const_int_operand" "i") 2946 (match_operand:SI 2 "const_int_operand" "i")) 2947 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 2948 (match_operand:SI 4 "const_int_operand" "i")))] 2949 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 2950 "* 2951{ 2952 int shift = INTVAL (operands[4]) & 31; 2953 int start = INTVAL (operands[2]) & 31; 2954 int size = INTVAL (operands[1]) & 31; 2955 2956 operands[4] = GEN_INT (32 - shift - start - size); 2957 operands[1] = GEN_INT (start + size - 1); 2958 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 2959}" 2960 [(set_attr "type" "insert_word")]) 2961 2962(define_insn "*insvsi_internal4" 2963 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 2964 (match_operand:SI 1 "const_int_operand" "i") 2965 (match_operand:SI 2 "const_int_operand" "i")) 2966 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") 2967 (match_operand:SI 4 "const_int_operand" "i") 2968 (match_operand:SI 5 "const_int_operand" "i")))] 2969 "INTVAL (operands[4]) >= INTVAL (operands[1])" 2970 "* 2971{ 2972 int extract_start = INTVAL (operands[5]) & 31; 2973 int extract_size = INTVAL (operands[4]) & 31; 2974 int insert_start = INTVAL (operands[2]) & 31; 2975 int insert_size = INTVAL (operands[1]) & 31; 2976 2977/* Align extract field with insert field */ 2978 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); 2979 operands[1] = GEN_INT (insert_start + insert_size - 1); 2980 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; 2981}" 2982 [(set_attr "type" "insert_word")]) 2983 2984(define_insn "insvdi" 2985 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") 2986 (match_operand:SI 1 "const_int_operand" "i") 2987 (match_operand:SI 2 "const_int_operand" "i")) 2988 (match_operand:DI 3 "gpc_reg_operand" "r"))] 2989 "TARGET_POWERPC64" 2990 "* 2991{ 2992 int start = INTVAL (operands[2]) & 63; 2993 int size = INTVAL (operands[1]) & 63; 2994 2995 operands[1] = GEN_INT (64 - start - size); 2996 return \"rldimi %0,%3,%H1,%H2\"; 2997}") 2998 2999(define_expand "extzv" 3000 [(set (match_operand 0 "gpc_reg_operand" "") 3001 (zero_extract (match_operand 1 "gpc_reg_operand" "") 3002 (match_operand:SI 2 "const_int_operand" "") 3003 (match_operand:SI 3 "const_int_operand" "")))] 3004 "" 3005 " 3006{ 3007 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 3008 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 3009 compiler if the address of the structure is taken later. */ 3010 if (GET_CODE (operands[0]) == SUBREG 3011 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) 3012 FAIL; 3013 3014 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) 3015 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); 3016 else 3017 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); 3018 DONE; 3019}") 3020 3021(define_insn "extzvsi" 3022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3023 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3024 (match_operand:SI 2 "const_int_operand" "i") 3025 (match_operand:SI 3 "const_int_operand" "i")))] 3026 "" 3027 "* 3028{ 3029 int start = INTVAL (operands[3]) & 31; 3030 int size = INTVAL (operands[2]) & 31; 3031 3032 if (start + size >= 32) 3033 operands[3] = const0_rtx; 3034 else 3035 operands[3] = GEN_INT (start + size); 3036 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; 3037}") 3038 3039(define_insn "*extzvsi_internal1" 3040 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3041 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3042 (match_operand:SI 2 "const_int_operand" "i,i") 3043 (match_operand:SI 3 "const_int_operand" "i,i")) 3044 (const_int 0))) 3045 (clobber (match_scratch:SI 4 "=r,r"))] 3046 "" 3047 "* 3048{ 3049 int start = INTVAL (operands[3]) & 31; 3050 int size = INTVAL (operands[2]) & 31; 3051 3052 /* Force split for non-cc0 compare. */ 3053 if (which_alternative == 1) 3054 return \"#\"; 3055 3056 /* If the bit-field being tested fits in the upper or lower half of a 3057 word, it is possible to use andiu. or andil. to test it. This is 3058 useful because the condition register set-use delay is smaller for 3059 andi[ul]. than for rlinm. This doesn't work when the starting bit 3060 position is 0 because the LT and GT bits may be set wrong. */ 3061 3062 if ((start > 0 && start + size <= 16) || start >= 16) 3063 { 3064 operands[3] = GEN_INT (((1 << (16 - (start & 15))) 3065 - (1 << (16 - (start & 15) - size)))); 3066 if (start < 16) 3067 return \"{andiu.|andis.} %4,%1,%3\"; 3068 else 3069 return \"{andil.|andi.} %4,%1,%3\"; 3070 } 3071 3072 if (start + size >= 32) 3073 operands[3] = const0_rtx; 3074 else 3075 operands[3] = GEN_INT (start + size); 3076 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; 3077}" 3078 [(set_attr "type" "compare") 3079 (set_attr "length" "4,8")]) 3080 3081(define_split 3082 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3083 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 3084 (match_operand:SI 2 "const_int_operand" "") 3085 (match_operand:SI 3 "const_int_operand" "")) 3086 (const_int 0))) 3087 (clobber (match_scratch:SI 4 ""))] 3088 "reload_completed" 3089 [(set (match_dup 4) 3090 (zero_extract:SI (match_dup 1) (match_dup 2) 3091 (match_dup 3))) 3092 (set (match_dup 0) 3093 (compare:CC (match_dup 4) 3094 (const_int 0)))] 3095 "") 3096 3097(define_insn "*extzvsi_internal2" 3098 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3099 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3100 (match_operand:SI 2 "const_int_operand" "i,i") 3101 (match_operand:SI 3 "const_int_operand" "i,i")) 3102 (const_int 0))) 3103 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3104 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 3105 "" 3106 "* 3107{ 3108 int start = INTVAL (operands[3]) & 31; 3109 int size = INTVAL (operands[2]) & 31; 3110 3111 /* Force split for non-cc0 compare. */ 3112 if (which_alternative == 1) 3113 return \"#\"; 3114 3115 /* Since we are using the output value, we can't ignore any need for 3116 a shift. The bit-field must end at the LSB. */ 3117 if (start >= 16 && start + size == 32) 3118 { 3119 operands[3] = GEN_INT ((1 << size) - 1); 3120 return \"{andil.|andi.} %0,%1,%3\"; 3121 } 3122 3123 if (start + size >= 32) 3124 operands[3] = const0_rtx; 3125 else 3126 operands[3] = GEN_INT (start + size); 3127 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; 3128}" 3129 [(set_attr "type" "compare") 3130 (set_attr "length" "4,8")]) 3131 3132(define_split 3133 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3134 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 3135 (match_operand:SI 2 "const_int_operand" "") 3136 (match_operand:SI 3 "const_int_operand" "")) 3137 (const_int 0))) 3138 (set (match_operand:SI 0 "gpc_reg_operand" "") 3139 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 3140 "reload_completed" 3141 [(set (match_dup 0) 3142 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) 3143 (set (match_dup 4) 3144 (compare:CC (match_dup 0) 3145 (const_int 0)))] 3146 "") 3147 3148(define_insn "extzvdi" 3149 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3150 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3151 (match_operand:SI 2 "const_int_operand" "i") 3152 (match_operand:SI 3 "const_int_operand" "i")))] 3153 "TARGET_POWERPC64" 3154 "* 3155{ 3156 int start = INTVAL (operands[3]) & 63; 3157 int size = INTVAL (operands[2]) & 63; 3158 3159 if (start + size >= 64) 3160 operands[3] = const0_rtx; 3161 else 3162 operands[3] = GEN_INT (start + size); 3163 operands[2] = GEN_INT (64 - size); 3164 return \"rldicl %0,%1,%3,%2\"; 3165}") 3166 3167(define_insn "*extzvdi_internal1" 3168 [(set (match_operand:CC 0 "gpc_reg_operand" "=x") 3169 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3170 (match_operand:SI 2 "const_int_operand" "i") 3171 (match_operand:SI 3 "const_int_operand" "i")) 3172 (const_int 0))) 3173 (clobber (match_scratch:DI 4 "=r"))] 3174 "TARGET_64BIT" 3175 "* 3176{ 3177 int start = INTVAL (operands[3]) & 63; 3178 int size = INTVAL (operands[2]) & 63; 3179 3180 if (start + size >= 64) 3181 operands[3] = const0_rtx; 3182 else 3183 operands[3] = GEN_INT (start + size); 3184 operands[2] = GEN_INT (64 - size); 3185 return \"rldicl. %4,%1,%3,%2\"; 3186}") 3187 3188(define_insn "*extzvdi_internal2" 3189 [(set (match_operand:CC 4 "gpc_reg_operand" "=x") 3190 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3191 (match_operand:SI 2 "const_int_operand" "i") 3192 (match_operand:SI 3 "const_int_operand" "i")) 3193 (const_int 0))) 3194 (set (match_operand:DI 0 "gpc_reg_operand" "=r") 3195 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] 3196 "TARGET_64BIT" 3197 "* 3198{ 3199 int start = INTVAL (operands[3]) & 63; 3200 int size = INTVAL (operands[2]) & 63; 3201 3202 if (start + size >= 64) 3203 operands[3] = const0_rtx; 3204 else 3205 operands[3] = GEN_INT (start + size); 3206 operands[2] = GEN_INT (64 - size); 3207 return \"rldicl. %0,%1,%3,%2\"; 3208}") 3209 3210(define_insn "rotlsi3" 3211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3212 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3213 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 3214 "" 3215 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") 3216 3217(define_insn "*rotlsi3_internal2" 3218 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3219 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3220 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3221 (const_int 0))) 3222 (clobber (match_scratch:SI 3 "=r,r"))] 3223 "" 3224 "@ 3225 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff 3226 #" 3227 [(set_attr "type" "delayed_compare") 3228 (set_attr "length" "4,8")]) 3229 3230(define_split 3231 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3232 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3233 (match_operand:SI 2 "reg_or_cint_operand" "")) 3234 (const_int 0))) 3235 (clobber (match_scratch:SI 3 ""))] 3236 "reload_completed" 3237 [(set (match_dup 3) 3238 (rotate:SI (match_dup 1) (match_dup 2))) 3239 (set (match_dup 0) 3240 (compare:CC (match_dup 3) 3241 (const_int 0)))] 3242 "") 3243 3244(define_insn "*rotlsi3_internal3" 3245 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3246 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3247 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3248 (const_int 0))) 3249 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3250 (rotate:SI (match_dup 1) (match_dup 2)))] 3251 "" 3252 "@ 3253 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff 3254 #" 3255 [(set_attr "type" "delayed_compare") 3256 (set_attr "length" "4,8")]) 3257 3258(define_split 3259 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3260 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3261 (match_operand:SI 2 "reg_or_cint_operand" "")) 3262 (const_int 0))) 3263 (set (match_operand:SI 0 "gpc_reg_operand" "") 3264 (rotate:SI (match_dup 1) (match_dup 2)))] 3265 "reload_completed" 3266 [(set (match_dup 0) 3267 (rotate:SI (match_dup 1) (match_dup 2))) 3268 (set (match_dup 3) 3269 (compare:CC (match_dup 0) 3270 (const_int 0)))] 3271 "") 3272 3273(define_insn "*rotlsi3_internal4" 3274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3275 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3276 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3277 (match_operand:SI 3 "mask_operand" "n")))] 3278 "" 3279 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") 3280 3281(define_insn "*rotlsi3_internal5" 3282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3283 (compare:CC (and:SI 3284 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3285 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3286 (match_operand:SI 3 "mask_operand" "n,n")) 3287 (const_int 0))) 3288 (clobber (match_scratch:SI 4 "=r,r"))] 3289 "" 3290 "@ 3291 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 3292 #" 3293 [(set_attr "type" "delayed_compare") 3294 (set_attr "length" "4,8")]) 3295 3296(define_split 3297 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3298 (compare:CC (and:SI 3299 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3300 (match_operand:SI 2 "reg_or_cint_operand" "")) 3301 (match_operand:SI 3 "mask_operand" "")) 3302 (const_int 0))) 3303 (clobber (match_scratch:SI 4 ""))] 3304 "reload_completed" 3305 [(set (match_dup 4) 3306 (and:SI (rotate:SI (match_dup 1) 3307 (match_dup 2)) 3308 (match_dup 3))) 3309 (set (match_dup 0) 3310 (compare:CC (match_dup 4) 3311 (const_int 0)))] 3312 "") 3313 3314(define_insn "*rotlsi3_internal6" 3315 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3316 (compare:CC (and:SI 3317 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3318 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3319 (match_operand:SI 3 "mask_operand" "n,n")) 3320 (const_int 0))) 3321 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3322 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3323 "" 3324 "@ 3325 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 3326 #" 3327 [(set_attr "type" "delayed_compare") 3328 (set_attr "length" "4,8")]) 3329 3330(define_split 3331 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3332 (compare:CC (and:SI 3333 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3334 (match_operand:SI 2 "reg_or_cint_operand" "")) 3335 (match_operand:SI 3 "mask_operand" "")) 3336 (const_int 0))) 3337 (set (match_operand:SI 0 "gpc_reg_operand" "") 3338 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3339 "reload_completed" 3340 [(set (match_dup 0) 3341 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 3342 (set (match_dup 4) 3343 (compare:CC (match_dup 0) 3344 (const_int 0)))] 3345 "") 3346 3347(define_insn "*rotlsi3_internal7" 3348 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3349 (zero_extend:SI 3350 (subreg:QI 3351 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3352 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 3353 "" 3354 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") 3355 3356(define_insn "*rotlsi3_internal8" 3357 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3358 (compare:CC (zero_extend:SI 3359 (subreg:QI 3360 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3361 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3362 (const_int 0))) 3363 (clobber (match_scratch:SI 3 "=r,r"))] 3364 "" 3365 "@ 3366 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff 3367 #" 3368 [(set_attr "type" "delayed_compare") 3369 (set_attr "length" "4,8")]) 3370 3371(define_split 3372 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3373 (compare:CC (zero_extend:SI 3374 (subreg:QI 3375 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3376 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 3377 (const_int 0))) 3378 (clobber (match_scratch:SI 3 ""))] 3379 "reload_completed" 3380 [(set (match_dup 3) 3381 (zero_extend:SI (subreg:QI 3382 (rotate:SI (match_dup 1) 3383 (match_dup 2)) 0))) 3384 (set (match_dup 0) 3385 (compare:CC (match_dup 3) 3386 (const_int 0)))] 3387 "") 3388 3389(define_insn "*rotlsi3_internal9" 3390 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3391 (compare:CC (zero_extend:SI 3392 (subreg:QI 3393 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3394 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3395 (const_int 0))) 3396 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3397 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 3398 "" 3399 "@ 3400 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff 3401 #" 3402 [(set_attr "type" "delayed_compare") 3403 (set_attr "length" "4,8")]) 3404 3405(define_split 3406 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3407 (compare:CC (zero_extend:SI 3408 (subreg:QI 3409 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3410 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 3411 (const_int 0))) 3412 (set (match_operand:SI 0 "gpc_reg_operand" "") 3413 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 3414 "reload_completed" 3415 [(set (match_dup 0) 3416 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) 3417 (set (match_dup 3) 3418 (compare:CC (match_dup 0) 3419 (const_int 0)))] 3420 "") 3421 3422(define_insn "*rotlsi3_internal10" 3423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3424 (zero_extend:SI 3425 (subreg:HI 3426 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3427 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 3428 "" 3429 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") 3430 3431(define_insn "*rotlsi3_internal11" 3432 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3433 (compare:CC (zero_extend:SI 3434 (subreg:HI 3435 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3436 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3437 (const_int 0))) 3438 (clobber (match_scratch:SI 3 "=r,r"))] 3439 "" 3440 "@ 3441 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff 3442 #" 3443 [(set_attr "type" "delayed_compare") 3444 (set_attr "length" "4,8")]) 3445 3446(define_split 3447 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3448 (compare:CC (zero_extend:SI 3449 (subreg:HI 3450 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3451 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 3452 (const_int 0))) 3453 (clobber (match_scratch:SI 3 ""))] 3454 "reload_completed" 3455 [(set (match_dup 3) 3456 (zero_extend:SI (subreg:HI 3457 (rotate:SI (match_dup 1) 3458 (match_dup 2)) 0))) 3459 (set (match_dup 0) 3460 (compare:CC (match_dup 3) 3461 (const_int 0)))] 3462 "") 3463 3464(define_insn "*rotlsi3_internal12" 3465 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3466 (compare:CC (zero_extend:SI 3467 (subreg:HI 3468 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3469 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3470 (const_int 0))) 3471 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3472 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 3473 "" 3474 "@ 3475 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff 3476 #" 3477 [(set_attr "type" "delayed_compare") 3478 (set_attr "length" "4,8")]) 3479 3480(define_split 3481 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3482 (compare:CC (zero_extend:SI 3483 (subreg:HI 3484 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3485 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 3486 (const_int 0))) 3487 (set (match_operand:SI 0 "gpc_reg_operand" "") 3488 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 3489 "reload_completed" 3490 [(set (match_dup 0) 3491 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) 3492 (set (match_dup 3) 3493 (compare:CC (match_dup 0) 3494 (const_int 0)))] 3495 "") 3496 3497;; Note that we use "sle." instead of "sl." so that we can set 3498;; SHIFT_COUNT_TRUNCATED. 3499 3500(define_expand "ashlsi3" 3501 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 3502 (use (match_operand:SI 1 "gpc_reg_operand" "")) 3503 (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 3504 "" 3505 " 3506{ 3507 if (TARGET_POWER) 3508 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); 3509 else 3510 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); 3511 DONE; 3512}") 3513 3514(define_insn "ashlsi3_power" 3515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3516 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3517 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 3518 (clobber (match_scratch:SI 3 "=q,X"))] 3519 "TARGET_POWER" 3520 "@ 3521 sle %0,%1,%2 3522 {sli|slwi} %0,%1,%h2") 3523 3524(define_insn "ashlsi3_no_power" 3525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3526 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3527 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 3528 "! TARGET_POWER" 3529 "{sl|slw}%I2 %0,%1,%h2") 3530 3531(define_insn "" 3532 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 3533 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 3534 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3535 (const_int 0))) 3536 (clobber (match_scratch:SI 3 "=r,r,r,r")) 3537 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 3538 "TARGET_POWER" 3539 "@ 3540 sle. %3,%1,%2 3541 {sli.|slwi.} %3,%1,%h2 3542 # 3543 #" 3544 [(set_attr "type" "delayed_compare") 3545 (set_attr "length" "4,4,8,8")]) 3546 3547(define_split 3548 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3549 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 3550 (match_operand:SI 2 "reg_or_cint_operand" "")) 3551 (const_int 0))) 3552 (clobber (match_scratch:SI 3 "")) 3553 (clobber (match_scratch:SI 4 ""))] 3554 "TARGET_POWER && reload_completed" 3555 [(parallel [(set (match_dup 3) 3556 (ashift:SI (match_dup 1) (match_dup 2))) 3557 (clobber (match_dup 4))]) 3558 (set (match_dup 0) 3559 (compare:CC (match_dup 3) 3560 (const_int 0)))] 3561 "") 3562 3563(define_insn "" 3564 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3565 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3566 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3567 (const_int 0))) 3568 (clobber (match_scratch:SI 3 "=r,r"))] 3569 "! TARGET_POWER && TARGET_32BIT" 3570 "@ 3571 {sl|slw}%I2. %3,%1,%h2 3572 #" 3573 [(set_attr "type" "delayed_compare") 3574 (set_attr "length" "4,8")]) 3575 3576(define_split 3577 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3578 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 3579 (match_operand:SI 2 "reg_or_cint_operand" "")) 3580 (const_int 0))) 3581 (clobber (match_scratch:SI 3 ""))] 3582 "! TARGET_POWER && TARGET_32BIT && reload_completed" 3583 [(set (match_dup 3) 3584 (ashift:SI (match_dup 1) (match_dup 2))) 3585 (set (match_dup 0) 3586 (compare:CC (match_dup 3) 3587 (const_int 0)))] 3588 "") 3589 3590(define_insn "" 3591 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 3592 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 3593 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3594 (const_int 0))) 3595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 3596 (ashift:SI (match_dup 1) (match_dup 2))) 3597 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 3598 "TARGET_POWER" 3599 "@ 3600 sle. %0,%1,%2 3601 {sli.|slwi.} %0,%1,%h2 3602 # 3603 #" 3604 [(set_attr "type" "delayed_compare") 3605 (set_attr "length" "4,4,8,8")]) 3606 3607(define_split 3608 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3609 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 3610 (match_operand:SI 2 "reg_or_cint_operand" "")) 3611 (const_int 0))) 3612 (set (match_operand:SI 0 "gpc_reg_operand" "") 3613 (ashift:SI (match_dup 1) (match_dup 2))) 3614 (clobber (match_scratch:SI 4 ""))] 3615 "TARGET_POWER && reload_completed" 3616 [(parallel [(set (match_dup 0) 3617 (ashift:SI (match_dup 1) (match_dup 2))) 3618 (clobber (match_dup 4))]) 3619 (set (match_dup 3) 3620 (compare:CC (match_dup 0) 3621 (const_int 0)))] 3622 "") 3623 3624(define_insn "" 3625 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3626 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3627 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3628 (const_int 0))) 3629 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3630 (ashift:SI (match_dup 1) (match_dup 2)))] 3631 "! TARGET_POWER && TARGET_32BIT" 3632 "@ 3633 {sl|slw}%I2. %0,%1,%h2 3634 #" 3635 [(set_attr "type" "delayed_compare") 3636 (set_attr "length" "4,8")]) 3637 3638(define_split 3639 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3640 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 3641 (match_operand:SI 2 "reg_or_cint_operand" "")) 3642 (const_int 0))) 3643 (set (match_operand:SI 0 "gpc_reg_operand" "") 3644 (ashift:SI (match_dup 1) (match_dup 2)))] 3645 "! TARGET_POWER && TARGET_32BIT && reload_completed" 3646 [(set (match_dup 0) 3647 (ashift:SI (match_dup 1) (match_dup 2))) 3648 (set (match_dup 3) 3649 (compare:CC (match_dup 0) 3650 (const_int 0)))] 3651 "") 3652 3653(define_insn "" 3654 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3655 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3656 (match_operand:SI 2 "const_int_operand" "i")) 3657 (match_operand:SI 3 "mask_operand" "n")))] 3658 "includes_lshift_p (operands[2], operands[3])" 3659 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") 3660 3661(define_insn "" 3662 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3663 (compare:CC 3664 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3665 (match_operand:SI 2 "const_int_operand" "i,i")) 3666 (match_operand:SI 3 "mask_operand" "n,n")) 3667 (const_int 0))) 3668 (clobber (match_scratch:SI 4 "=r,r"))] 3669 "includes_lshift_p (operands[2], operands[3])" 3670 "@ 3671 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 3672 #" 3673 [(set_attr "type" "delayed_compare") 3674 (set_attr "length" "4,8")]) 3675 3676(define_split 3677 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3678 (compare:CC 3679 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 3680 (match_operand:SI 2 "const_int_operand" "")) 3681 (match_operand:SI 3 "mask_operand" "")) 3682 (const_int 0))) 3683 (clobber (match_scratch:SI 4 ""))] 3684 "includes_lshift_p (operands[2], operands[3]) && reload_completed" 3685 [(set (match_dup 4) 3686 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) 3687 (match_dup 3))) 3688 (set (match_dup 0) 3689 (compare:CC (match_dup 4) 3690 (const_int 0)))] 3691 "") 3692 3693(define_insn "" 3694 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3695 (compare:CC 3696 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3697 (match_operand:SI 2 "const_int_operand" "i,i")) 3698 (match_operand:SI 3 "mask_operand" "n,n")) 3699 (const_int 0))) 3700 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3701 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3702 "includes_lshift_p (operands[2], operands[3])" 3703 "@ 3704 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 3705 #" 3706 [(set_attr "type" "delayed_compare") 3707 (set_attr "length" "4,8")]) 3708 3709(define_split 3710 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3711 (compare:CC 3712 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 3713 (match_operand:SI 2 "const_int_operand" "")) 3714 (match_operand:SI 3 "mask_operand" "")) 3715 (const_int 0))) 3716 (set (match_operand:SI 0 "gpc_reg_operand" "") 3717 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3718 "includes_lshift_p (operands[2], operands[3]) && reload_completed" 3719 [(set (match_dup 0) 3720 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 3721 (set (match_dup 4) 3722 (compare:CC (match_dup 0) 3723 (const_int 0)))] 3724 "") 3725 3726;; The AIX assembler mis-handles "sri x,x,0", so write that case as 3727;; "sli x,x,0". 3728(define_expand "lshrsi3" 3729 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 3730 (use (match_operand:SI 1 "gpc_reg_operand" "")) 3731 (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 3732 "" 3733 " 3734{ 3735 if (TARGET_POWER) 3736 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); 3737 else 3738 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); 3739 DONE; 3740}") 3741 3742(define_insn "lshrsi3_power" 3743 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 3744 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") 3745 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) 3746 (clobber (match_scratch:SI 3 "=q,X,X"))] 3747 "TARGET_POWER" 3748 "@ 3749 sre %0,%1,%2 3750 mr %0,%1 3751 {s%A2i|s%A2wi} %0,%1,%h2") 3752 3753(define_insn "lshrsi3_no_power" 3754 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3755 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3756 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] 3757 "! TARGET_POWER" 3758 "@ 3759 mr %0,%1 3760 {sr|srw}%I2 %0,%1,%h2") 3761 3762(define_insn "" 3763 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") 3764 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") 3765 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) 3766 (const_int 0))) 3767 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) 3768 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] 3769 "TARGET_POWER" 3770 "@ 3771 sre. %3,%1,%2 3772 mr. %1,%1 3773 {s%A2i.|s%A2wi.} %3,%1,%h2 3774 # 3775 # 3776 #" 3777 [(set_attr "type" "delayed_compare") 3778 (set_attr "length" "4,4,4,8,8,8")]) 3779 3780(define_split 3781 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3782 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 3783 (match_operand:SI 2 "reg_or_cint_operand" "")) 3784 (const_int 0))) 3785 (clobber (match_scratch:SI 3 "")) 3786 (clobber (match_scratch:SI 4 ""))] 3787 "TARGET_POWER && reload_completed" 3788 [(parallel [(set (match_dup 3) 3789 (lshiftrt:SI (match_dup 1) (match_dup 2))) 3790 (clobber (match_dup 4))]) 3791 (set (match_dup 0) 3792 (compare:CC (match_dup 3) 3793 (const_int 0)))] 3794 "") 3795 3796(define_insn "" 3797 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 3798 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 3799 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) 3800 (const_int 0))) 3801 (clobber (match_scratch:SI 3 "=X,r,X,r"))] 3802 "! TARGET_POWER && TARGET_32BIT" 3803 "@ 3804 mr. %1,%1 3805 {sr|srw}%I2. %3,%1,%h2 3806 # 3807 #" 3808 [(set_attr "type" "delayed_compare") 3809 (set_attr "length" "4,4,8,8")]) 3810 3811(define_split 3812 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3813 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 3814 (match_operand:SI 2 "reg_or_cint_operand" "")) 3815 (const_int 0))) 3816 (clobber (match_scratch:SI 3 ""))] 3817 "! TARGET_POWER && TARGET_32BIT && reload_completed" 3818 [(set (match_dup 3) 3819 (lshiftrt:SI (match_dup 1) (match_dup 2))) 3820 (set (match_dup 0) 3821 (compare:CC (match_dup 3) 3822 (const_int 0)))] 3823 "") 3824 3825(define_insn "" 3826 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") 3827 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") 3828 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) 3829 (const_int 0))) 3830 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") 3831 (lshiftrt:SI (match_dup 1) (match_dup 2))) 3832 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] 3833 "TARGET_POWER" 3834 "@ 3835 sre. %0,%1,%2 3836 mr. %0,%1 3837 {s%A2i.|s%A2wi.} %0,%1,%h2 3838 # 3839 # 3840 #" 3841 [(set_attr "type" "delayed_compare") 3842 (set_attr "length" "4,4,4,8,8,8")]) 3843 3844(define_split 3845 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3846 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 3847 (match_operand:SI 2 "reg_or_cint_operand" "")) 3848 (const_int 0))) 3849 (set (match_operand:SI 0 "gpc_reg_operand" "") 3850 (lshiftrt:SI (match_dup 1) (match_dup 2))) 3851 (clobber (match_scratch:SI 4 ""))] 3852 "TARGET_POWER && reload_completed" 3853 [(parallel [(set (match_dup 0) 3854 (lshiftrt:SI (match_dup 1) (match_dup 2))) 3855 (clobber (match_dup 4))]) 3856 (set (match_dup 3) 3857 (compare:CC (match_dup 0) 3858 (const_int 0)))] 3859 "") 3860 3861(define_insn "" 3862 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 3863 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 3864 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) 3865 (const_int 0))) 3866 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 3867 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 3868 "! TARGET_POWER && TARGET_32BIT" 3869 "@ 3870 mr. %0,%1 3871 {sr|srw}%I2. %0,%1,%h2 3872 # 3873 #" 3874 [(set_attr "type" "delayed_compare") 3875 (set_attr "length" "4,4,8,8")]) 3876 3877(define_split 3878 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3879 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 3880 (match_operand:SI 2 "reg_or_cint_operand" "")) 3881 (const_int 0))) 3882 (set (match_operand:SI 0 "gpc_reg_operand" "") 3883 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 3884 "! TARGET_POWER && TARGET_32BIT && reload_completed" 3885 [(set (match_dup 0) 3886 (lshiftrt:SI (match_dup 1) (match_dup 2))) 3887 (set (match_dup 3) 3888 (compare:CC (match_dup 0) 3889 (const_int 0)))] 3890 "") 3891 3892(define_insn "" 3893 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3894 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3895 (match_operand:SI 2 "const_int_operand" "i")) 3896 (match_operand:SI 3 "mask_operand" "n")))] 3897 "includes_rshift_p (operands[2], operands[3])" 3898 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") 3899 3900(define_insn "" 3901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3902 (compare:CC 3903 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3904 (match_operand:SI 2 "const_int_operand" "i,i")) 3905 (match_operand:SI 3 "mask_operand" "n,n")) 3906 (const_int 0))) 3907 (clobber (match_scratch:SI 4 "=r,r"))] 3908 "includes_rshift_p (operands[2], operands[3])" 3909 "@ 3910 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 3911 #" 3912 [(set_attr "type" "delayed_compare") 3913 (set_attr "length" "4,8")]) 3914 3915(define_split 3916 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3917 (compare:CC 3918 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 3919 (match_operand:SI 2 "const_int_operand" "")) 3920 (match_operand:SI 3 "mask_operand" "")) 3921 (const_int 0))) 3922 (clobber (match_scratch:SI 4 ""))] 3923 "includes_rshift_p (operands[2], operands[3]) && reload_completed" 3924 [(set (match_dup 4) 3925 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3926 (match_dup 3))) 3927 (set (match_dup 0) 3928 (compare:CC (match_dup 4) 3929 (const_int 0)))] 3930 "") 3931 3932(define_insn "" 3933 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3934 (compare:CC 3935 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3936 (match_operand:SI 2 "const_int_operand" "i,i")) 3937 (match_operand:SI 3 "mask_operand" "n,n")) 3938 (const_int 0))) 3939 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3940 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3941 "includes_rshift_p (operands[2], operands[3])" 3942 "@ 3943 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 3944 #" 3945 [(set_attr "type" "delayed_compare") 3946 (set_attr "length" "4,8")]) 3947 3948(define_split 3949 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3950 (compare:CC 3951 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 3952 (match_operand:SI 2 "const_int_operand" "")) 3953 (match_operand:SI 3 "mask_operand" "")) 3954 (const_int 0))) 3955 (set (match_operand:SI 0 "gpc_reg_operand" "") 3956 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3957 "includes_rshift_p (operands[2], operands[3]) && reload_completed" 3958 [(set (match_dup 0) 3959 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 3960 (set (match_dup 4) 3961 (compare:CC (match_dup 0) 3962 (const_int 0)))] 3963 "") 3964 3965(define_insn "" 3966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3967 (zero_extend:SI 3968 (subreg:QI 3969 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3970 (match_operand:SI 2 "const_int_operand" "i")) 0)))] 3971 "includes_rshift_p (operands[2], GEN_INT (255))" 3972 "{rlinm|rlwinm} %0,%1,%s2,0xff") 3973 3974(define_insn "" 3975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3976 (compare:CC 3977 (zero_extend:SI 3978 (subreg:QI 3979 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3980 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 3981 (const_int 0))) 3982 (clobber (match_scratch:SI 3 "=r,r"))] 3983 "includes_rshift_p (operands[2], GEN_INT (255))" 3984 "@ 3985 {rlinm.|rlwinm.} %3,%1,%s2,0xff 3986 #" 3987 [(set_attr "type" "delayed_compare") 3988 (set_attr "length" "4,8")]) 3989 3990(define_split 3991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3992 (compare:CC 3993 (zero_extend:SI 3994 (subreg:QI 3995 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 3996 (match_operand:SI 2 "const_int_operand" "")) 0)) 3997 (const_int 0))) 3998 (clobber (match_scratch:SI 3 ""))] 3999 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4000 [(set (match_dup 3) 4001 (zero_extend:SI (subreg:QI 4002 (lshiftrt:SI (match_dup 1) 4003 (match_dup 2)) 0))) 4004 (set (match_dup 0) 4005 (compare:CC (match_dup 3) 4006 (const_int 0)))] 4007 "") 4008 4009(define_insn "" 4010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4011 (compare:CC 4012 (zero_extend:SI 4013 (subreg:QI 4014 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4015 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4016 (const_int 0))) 4017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4018 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4019 "includes_rshift_p (operands[2], GEN_INT (255))" 4020 "@ 4021 {rlinm.|rlwinm.} %0,%1,%s2,0xff 4022 #" 4023 [(set_attr "type" "delayed_compare") 4024 (set_attr "length" "4,8")]) 4025 4026(define_split 4027 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4028 (compare:CC 4029 (zero_extend:SI 4030 (subreg:QI 4031 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4032 (match_operand:SI 2 "const_int_operand" "")) 0)) 4033 (const_int 0))) 4034 (set (match_operand:SI 0 "gpc_reg_operand" "") 4035 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4036 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4037 [(set (match_dup 0) 4038 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) 4039 (set (match_dup 3) 4040 (compare:CC (match_dup 0) 4041 (const_int 0)))] 4042 "") 4043 4044(define_insn "" 4045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4046 (zero_extend:SI 4047 (subreg:HI 4048 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4049 (match_operand:SI 2 "const_int_operand" "i")) 0)))] 4050 "includes_rshift_p (operands[2], GEN_INT (65535))" 4051 "{rlinm|rlwinm} %0,%1,%s2,0xffff") 4052 4053(define_insn "" 4054 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4055 (compare:CC 4056 (zero_extend:SI 4057 (subreg:HI 4058 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4059 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4060 (const_int 0))) 4061 (clobber (match_scratch:SI 3 "=r,r"))] 4062 "includes_rshift_p (operands[2], GEN_INT (65535))" 4063 "@ 4064 {rlinm.|rlwinm.} %3,%1,%s2,0xffff 4065 #" 4066 [(set_attr "type" "delayed_compare") 4067 (set_attr "length" "4,8")]) 4068 4069(define_split 4070 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4071 (compare:CC 4072 (zero_extend:SI 4073 (subreg:HI 4074 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4075 (match_operand:SI 2 "const_int_operand" "")) 0)) 4076 (const_int 0))) 4077 (clobber (match_scratch:SI 3 ""))] 4078 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4079 [(set (match_dup 3) 4080 (zero_extend:SI (subreg:HI 4081 (lshiftrt:SI (match_dup 1) 4082 (match_dup 2)) 0))) 4083 (set (match_dup 0) 4084 (compare:CC (match_dup 3) 4085 (const_int 0)))] 4086 "") 4087 4088(define_insn "" 4089 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4090 (compare:CC 4091 (zero_extend:SI 4092 (subreg:HI 4093 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4094 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4095 (const_int 0))) 4096 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4097 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4098 "includes_rshift_p (operands[2], GEN_INT (65535))" 4099 "@ 4100 {rlinm.|rlwinm.} %0,%1,%s2,0xffff 4101 #" 4102 [(set_attr "type" "delayed_compare") 4103 (set_attr "length" "4,8")]) 4104 4105(define_split 4106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4107 (compare:CC 4108 (zero_extend:SI 4109 (subreg:HI 4110 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4111 (match_operand:SI 2 "const_int_operand" "")) 0)) 4112 (const_int 0))) 4113 (set (match_operand:SI 0 "gpc_reg_operand" "") 4114 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4115 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4116 [(set (match_dup 0) 4117 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) 4118 (set (match_dup 3) 4119 (compare:CC (match_dup 0) 4120 (const_int 0)))] 4121 "") 4122 4123(define_insn "" 4124 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 4125 (const_int 1) 4126 (match_operand:SI 1 "gpc_reg_operand" "r")) 4127 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 4128 (const_int 31)))] 4129 "TARGET_POWER" 4130 "rrib %0,%1,%2") 4131 4132(define_insn "" 4133 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 4134 (const_int 1) 4135 (match_operand:SI 1 "gpc_reg_operand" "r")) 4136 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 4137 (const_int 31)))] 4138 "TARGET_POWER" 4139 "rrib %0,%1,%2") 4140 4141(define_insn "" 4142 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 4143 (const_int 1) 4144 (match_operand:SI 1 "gpc_reg_operand" "r")) 4145 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 4146 (const_int 1) 4147 (const_int 0)))] 4148 "TARGET_POWER" 4149 "rrib %0,%1,%2") 4150 4151(define_expand "ashrsi3" 4152 [(set (match_operand:SI 0 "gpc_reg_operand" "") 4153 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4154 (match_operand:SI 2 "reg_or_cint_operand" "")))] 4155 "" 4156 " 4157{ 4158 if (TARGET_POWER) 4159 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); 4160 else 4161 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); 4162 DONE; 4163}") 4164 4165(define_insn "ashrsi3_power" 4166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4167 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4168 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 4169 (clobber (match_scratch:SI 3 "=q,X"))] 4170 "TARGET_POWER" 4171 "@ 4172 srea %0,%1,%2 4173 {srai|srawi} %0,%1,%h2") 4174 4175(define_insn "ashrsi3_no_power" 4176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4177 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4178 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 4179 "! TARGET_POWER" 4180 "{sra|sraw}%I2 %0,%1,%h2") 4181 4182(define_insn "" 4183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4184 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4185 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4186 (const_int 0))) 4187 (clobber (match_scratch:SI 3 "=r,r,r,r")) 4188 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4189 "TARGET_POWER" 4190 "@ 4191 srea. %3,%1,%2 4192 {srai.|srawi.} %3,%1,%h2 4193 # 4194 #" 4195 [(set_attr "type" "delayed_compare") 4196 (set_attr "length" "4,4,8,8")]) 4197 4198(define_split 4199 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4200 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4201 (match_operand:SI 2 "reg_or_cint_operand" "")) 4202 (const_int 0))) 4203 (clobber (match_scratch:SI 3 "")) 4204 (clobber (match_scratch:SI 4 ""))] 4205 "TARGET_POWER && reload_completed" 4206 [(parallel [(set (match_dup 3) 4207 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4208 (clobber (match_dup 4))]) 4209 (set (match_dup 0) 4210 (compare:CC (match_dup 3) 4211 (const_int 0)))] 4212 "") 4213 4214(define_insn "" 4215 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4216 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4217 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4218 (const_int 0))) 4219 (clobber (match_scratch:SI 3 "=r,r"))] 4220 "! TARGET_POWER" 4221 "@ 4222 {sra|sraw}%I2. %3,%1,%h2 4223 #" 4224 [(set_attr "type" "delayed_compare") 4225 (set_attr "length" "4,8")]) 4226 4227(define_split 4228 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4229 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4230 (match_operand:SI 2 "reg_or_cint_operand" "")) 4231 (const_int 0))) 4232 (clobber (match_scratch:SI 3 ""))] 4233 "! TARGET_POWER && reload_completed" 4234 [(set (match_dup 3) 4235 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4236 (set (match_dup 0) 4237 (compare:CC (match_dup 3) 4238 (const_int 0)))] 4239 "") 4240 4241(define_insn "" 4242 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4243 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4244 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4245 (const_int 0))) 4246 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4247 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4248 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4249 "TARGET_POWER" 4250 "@ 4251 srea. %0,%1,%2 4252 {srai.|srawi.} %0,%1,%h2 4253 # 4254 #" 4255 [(set_attr "type" "delayed_compare") 4256 (set_attr "length" "4,4,8,8")]) 4257 4258(define_split 4259 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4260 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4261 (match_operand:SI 2 "reg_or_cint_operand" "")) 4262 (const_int 0))) 4263 (set (match_operand:SI 0 "gpc_reg_operand" "") 4264 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4265 (clobber (match_scratch:SI 4 ""))] 4266 "TARGET_POWER && reload_completed" 4267 [(parallel [(set (match_dup 0) 4268 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4269 (clobber (match_dup 4))]) 4270 (set (match_dup 3) 4271 (compare:CC (match_dup 0) 4272 (const_int 0)))] 4273 "") 4274 4275(define_insn "" 4276 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4277 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4278 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4279 (const_int 0))) 4280 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4281 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 4282 "! TARGET_POWER" 4283 "@ 4284 {sra|sraw}%I2. %0,%1,%h2 4285 #" 4286 [(set_attr "type" "delayed_compare") 4287 (set_attr "length" "4,8")]) 4288 4289(define_split 4290 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4291 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4292 (match_operand:SI 2 "reg_or_cint_operand" "")) 4293 (const_int 0))) 4294 (set (match_operand:SI 0 "gpc_reg_operand" "") 4295 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 4296 "! TARGET_POWER && reload_completed" 4297 [(set (match_dup 0) 4298 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4299 (set (match_dup 3) 4300 (compare:CC (match_dup 0) 4301 (const_int 0)))] 4302 "") 4303 4304;; Floating-point insns, excluding normal data motion. 4305;; 4306;; PowerPC has a full set of single-precision floating point instructions. 4307;; 4308;; For the POWER architecture, we pretend that we have both SFmode and 4309;; DFmode insns, while, in fact, all fp insns are actually done in double. 4310;; The only conversions we will do will be when storing to memory. In that 4311;; case, we will use the "frsp" instruction before storing. 4312;; 4313;; Note that when we store into a single-precision memory location, we need to 4314;; use the frsp insn first. If the register being stored isn't dead, we 4315;; need a scratch register for the frsp. But this is difficult when the store 4316;; is done by reload. It is not incorrect to do the frsp on the register in 4317;; this case, we just lose precision that we would have otherwise gotten but 4318;; is not guaranteed. Perhaps this should be tightened up at some point. 4319 4320(define_insn "extendsfdf2" 4321 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4322 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4323 "TARGET_HARD_FLOAT && TARGET_FPRS" 4324 "* 4325{ 4326 if (REGNO (operands[0]) == REGNO (operands[1])) 4327 return \"\"; 4328 else 4329 return \"fmr %0,%1\"; 4330}" 4331 [(set_attr "type" "fp")]) 4332 4333(define_insn "truncdfsf2" 4334 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4335 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] 4336 "TARGET_HARD_FLOAT && TARGET_FPRS" 4337 "frsp %0,%1" 4338 [(set_attr "type" "fp")]) 4339 4340(define_insn "aux_truncdfsf2" 4341 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4342 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] 4343 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4344 "frsp %0,%1" 4345 [(set_attr "type" "fp")]) 4346 4347(define_expand "negsf2" 4348 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4349 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 4350 "TARGET_HARD_FLOAT" 4351 "") 4352 4353(define_insn "*negsf2" 4354 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4355 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4356 "TARGET_HARD_FLOAT && TARGET_FPRS" 4357 "fneg %0,%1" 4358 [(set_attr "type" "fp")]) 4359 4360(define_expand "abssf2" 4361 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4362 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 4363 "TARGET_HARD_FLOAT" 4364 "") 4365 4366(define_insn "*abssf2" 4367 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4368 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4369 "TARGET_HARD_FLOAT && TARGET_FPRS" 4370 "fabs %0,%1" 4371 [(set_attr "type" "fp")]) 4372 4373(define_insn "" 4374 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4375 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] 4376 "TARGET_HARD_FLOAT && TARGET_FPRS" 4377 "fnabs %0,%1" 4378 [(set_attr "type" "fp")]) 4379 4380(define_expand "addsf3" 4381 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4382 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") 4383 (match_operand:SF 2 "gpc_reg_operand" "")))] 4384 "TARGET_HARD_FLOAT" 4385 "") 4386 4387(define_insn "" 4388 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4389 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4390 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4391 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4392 "fadds %0,%1,%2" 4393 [(set_attr "type" "fp")]) 4394 4395(define_insn "" 4396 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4397 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4398 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4399 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4400 "{fa|fadd} %0,%1,%2" 4401 [(set_attr "type" "fp")]) 4402 4403(define_expand "subsf3" 4404 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4405 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") 4406 (match_operand:SF 2 "gpc_reg_operand" "")))] 4407 "TARGET_HARD_FLOAT" 4408 "") 4409 4410(define_insn "" 4411 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4412 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 4413 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4414 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4415 "fsubs %0,%1,%2" 4416 [(set_attr "type" "fp")]) 4417 4418(define_insn "" 4419 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4420 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 4421 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4422 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4423 "{fs|fsub} %0,%1,%2" 4424 [(set_attr "type" "fp")]) 4425 4426(define_expand "mulsf3" 4427 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4428 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") 4429 (match_operand:SF 2 "gpc_reg_operand" "")))] 4430 "TARGET_HARD_FLOAT" 4431 "") 4432 4433(define_insn "" 4434 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4435 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4436 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4437 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4438 "fmuls %0,%1,%2" 4439 [(set_attr "type" "fp")]) 4440 4441(define_insn "" 4442 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4443 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4444 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4445 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4446 "{fm|fmul} %0,%1,%2" 4447 [(set_attr "type" "dmul")]) 4448 4449(define_expand "divsf3" 4450 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4451 (div:SF (match_operand:SF 1 "gpc_reg_operand" "") 4452 (match_operand:SF 2 "gpc_reg_operand" "")))] 4453 "TARGET_HARD_FLOAT" 4454 "") 4455 4456(define_insn "" 4457 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4458 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 4459 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4460 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4461 "fdivs %0,%1,%2" 4462 [(set_attr "type" "sdiv")]) 4463 4464(define_insn "" 4465 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4466 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 4467 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4468 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" 4469 "{fd|fdiv} %0,%1,%2" 4470 [(set_attr "type" "ddiv")]) 4471 4472(define_insn "" 4473 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4474 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4475 (match_operand:SF 2 "gpc_reg_operand" "f")) 4476 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4477 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 4478 "fmadds %0,%1,%2,%3" 4479 [(set_attr "type" "fp")]) 4480 4481(define_insn "" 4482 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4483 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4484 (match_operand:SF 2 "gpc_reg_operand" "f")) 4485 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4486 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 4487 "{fma|fmadd} %0,%1,%2,%3" 4488 [(set_attr "type" "dmul")]) 4489 4490(define_insn "" 4491 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4492 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4493 (match_operand:SF 2 "gpc_reg_operand" "f")) 4494 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4495 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 4496 "fmsubs %0,%1,%2,%3" 4497 [(set_attr "type" "fp")]) 4498 4499(define_insn "" 4500 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4501 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4502 (match_operand:SF 2 "gpc_reg_operand" "f")) 4503 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4504 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 4505 "{fms|fmsub} %0,%1,%2,%3" 4506 [(set_attr "type" "dmul")]) 4507 4508(define_insn "" 4509 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4510 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4511 (match_operand:SF 2 "gpc_reg_operand" "f")) 4512 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 4513 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4514 && HONOR_SIGNED_ZEROS (SFmode)" 4515 "fnmadds %0,%1,%2,%3" 4516 [(set_attr "type" "fp")]) 4517 4518(define_insn "" 4519 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4520 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) 4521 (match_operand:SF 2 "gpc_reg_operand" "f")) 4522 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4523 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4524 && ! HONOR_SIGNED_ZEROS (SFmode)" 4525 "fnmadds %0,%1,%2,%3" 4526 [(set_attr "type" "fp")]) 4527 4528(define_insn "" 4529 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4530 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4531 (match_operand:SF 2 "gpc_reg_operand" "f")) 4532 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 4533 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 4534 "{fnma|fnmadd} %0,%1,%2,%3" 4535 [(set_attr "type" "dmul")]) 4536 4537(define_insn "" 4538 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4539 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) 4540 (match_operand:SF 2 "gpc_reg_operand" "f")) 4541 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4542 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4543 && ! HONOR_SIGNED_ZEROS (SFmode)" 4544 "{fnma|fnmadd} %0,%1,%2,%3" 4545 [(set_attr "type" "dmul")]) 4546 4547(define_insn "" 4548 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4549 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4550 (match_operand:SF 2 "gpc_reg_operand" "f")) 4551 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 4552 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4553 && HONOR_SIGNED_ZEROS (SFmode)" 4554 "fnmsubs %0,%1,%2,%3" 4555 [(set_attr "type" "fp")]) 4556 4557(define_insn "" 4558 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4559 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") 4560 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4561 (match_operand:SF 2 "gpc_reg_operand" "f"))))] 4562 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4563 && ! HONOR_SIGNED_ZEROS (SFmode)" 4564 "fnmsubs %0,%1,%2,%3" 4565 [(set_attr "type" "fp")]) 4566 4567(define_insn "" 4568 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4569 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4570 (match_operand:SF 2 "gpc_reg_operand" "f")) 4571 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 4572 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 4573 "{fnms|fnmsub} %0,%1,%2,%3" 4574 [(set_attr "type" "dmul")]) 4575 4576(define_insn "" 4577 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4578 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") 4579 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4580 (match_operand:SF 2 "gpc_reg_operand" "f"))))] 4581 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4582 && ! HONOR_SIGNED_ZEROS (SFmode)" 4583 "{fnms|fnmsub} %0,%1,%2,%3" 4584 [(set_attr "type" "fp")]) 4585 4586(define_expand "sqrtsf2" 4587 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4588 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 4589 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" 4590 "") 4591 4592(define_insn "" 4593 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4594 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4595 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4596 "fsqrts %0,%1" 4597 [(set_attr "type" "ssqrt")]) 4598 4599(define_insn "" 4600 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4601 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4602 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" 4603 "fsqrt %0,%1" 4604 [(set_attr "type" "dsqrt")]) 4605 4606;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a 4607;; fsel instruction and some auxiliary computations. Then we just have a 4608;; single DEFINE_INSN for fsel and the define_splits to make them if made by 4609;; combine. 4610(define_expand "maxsf3" 4611 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4612 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") 4613 (match_operand:SF 2 "gpc_reg_operand" "")) 4614 (match_dup 1) 4615 (match_dup 2)))] 4616 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4617 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") 4618 4619(define_expand "minsf3" 4620 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4621 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") 4622 (match_operand:SF 2 "gpc_reg_operand" "")) 4623 (match_dup 2) 4624 (match_dup 1)))] 4625 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4626 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") 4627 4628(define_split 4629 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4630 (match_operator:SF 3 "min_max_operator" 4631 [(match_operand:SF 1 "gpc_reg_operand" "") 4632 (match_operand:SF 2 "gpc_reg_operand" "")]))] 4633 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4634 [(const_int 0)] 4635 " 4636{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), 4637 operands[1], operands[2]); 4638 DONE; 4639}") 4640 4641(define_expand "movsicc" 4642 [(set (match_operand:SI 0 "gpc_reg_operand" "") 4643 (if_then_else:SI (match_operand 1 "comparison_operator" "") 4644 (match_operand:SI 2 "gpc_reg_operand" "") 4645 (match_operand:SI 3 "gpc_reg_operand" "")))] 4646 "TARGET_ISEL" 4647 " 4648{ 4649 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 4650 DONE; 4651 else 4652 FAIL; 4653}") 4654 4655;; We use the BASE_REGS for the isel input operands because, if rA is 4656;; 0, the value of 0 is placed in rD upon truth. Similarly for rB 4657;; because we may switch the operands and rB may end up being rA. 4658;; 4659;; We need 2 patterns: an unsigned and a signed pattern. We could 4660;; leave out the mode in operand 4 and use one pattern, but reload can 4661;; change the mode underneath our feet and then gets confused trying 4662;; to reload the value. 4663(define_insn "isel_signed" 4664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4665 (if_then_else:SI 4666 (match_operator 1 "comparison_operator" 4667 [(match_operand:CC 4 "cc_reg_operand" "y") 4668 (const_int 0)]) 4669 (match_operand:SI 2 "gpc_reg_operand" "b") 4670 (match_operand:SI 3 "gpc_reg_operand" "b")))] 4671 "TARGET_ISEL" 4672 "* 4673{ return output_isel (operands); }" 4674 [(set_attr "length" "4")]) 4675 4676(define_insn "isel_unsigned" 4677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4678 (if_then_else:SI 4679 (match_operator 1 "comparison_operator" 4680 [(match_operand:CCUNS 4 "cc_reg_operand" "y") 4681 (const_int 0)]) 4682 (match_operand:SI 2 "gpc_reg_operand" "b") 4683 (match_operand:SI 3 "gpc_reg_operand" "b")))] 4684 "TARGET_ISEL" 4685 "* 4686{ return output_isel (operands); }" 4687 [(set_attr "length" "4")]) 4688 4689(define_expand "movsfcc" 4690 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4691 (if_then_else:SF (match_operand 1 "comparison_operator" "") 4692 (match_operand:SF 2 "gpc_reg_operand" "") 4693 (match_operand:SF 3 "gpc_reg_operand" "")))] 4694 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4695 " 4696{ 4697 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 4698 DONE; 4699 else 4700 FAIL; 4701}") 4702 4703(define_insn "*fselsfsf4" 4704 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4705 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 4706 (match_operand:SF 4 "zero_fp_constant" "F")) 4707 (match_operand:SF 2 "gpc_reg_operand" "f") 4708 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4709 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4710 "fsel %0,%1,%2,%3" 4711 [(set_attr "type" "fp")]) 4712 4713(define_insn "*fseldfsf4" 4714 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4715 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 4716 (match_operand:DF 4 "zero_fp_constant" "F")) 4717 (match_operand:SF 2 "gpc_reg_operand" "f") 4718 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4719 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4720 "fsel %0,%1,%2,%3" 4721 [(set_attr "type" "fp")]) 4722 4723(define_insn "negdf2" 4724 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4725 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 4726 "TARGET_HARD_FLOAT && TARGET_FPRS" 4727 "fneg %0,%1" 4728 [(set_attr "type" "fp")]) 4729 4730(define_insn "absdf2" 4731 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4732 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 4733 "TARGET_HARD_FLOAT && TARGET_FPRS" 4734 "fabs %0,%1" 4735 [(set_attr "type" "fp")]) 4736 4737(define_insn "" 4738 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4739 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] 4740 "TARGET_HARD_FLOAT && TARGET_FPRS" 4741 "fnabs %0,%1" 4742 [(set_attr "type" "fp")]) 4743 4744(define_insn "adddf3" 4745 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4746 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 4747 (match_operand:DF 2 "gpc_reg_operand" "f")))] 4748 "TARGET_HARD_FLOAT && TARGET_FPRS" 4749 "{fa|fadd} %0,%1,%2" 4750 [(set_attr "type" "fp")]) 4751 4752(define_insn "subdf3" 4753 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4754 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") 4755 (match_operand:DF 2 "gpc_reg_operand" "f")))] 4756 "TARGET_HARD_FLOAT && TARGET_FPRS" 4757 "{fs|fsub} %0,%1,%2" 4758 [(set_attr "type" "fp")]) 4759 4760(define_insn "muldf3" 4761 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4762 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 4763 (match_operand:DF 2 "gpc_reg_operand" "f")))] 4764 "TARGET_HARD_FLOAT && TARGET_FPRS" 4765 "{fm|fmul} %0,%1,%2" 4766 [(set_attr "type" "dmul")]) 4767 4768(define_insn "divdf3" 4769 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4770 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") 4771 (match_operand:DF 2 "gpc_reg_operand" "f")))] 4772 "TARGET_HARD_FLOAT && TARGET_FPRS" 4773 "{fd|fdiv} %0,%1,%2" 4774 [(set_attr "type" "ddiv")]) 4775 4776(define_insn "" 4777 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4778 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 4779 (match_operand:DF 2 "gpc_reg_operand" "f")) 4780 (match_operand:DF 3 "gpc_reg_operand" "f")))] 4781 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 4782 "{fma|fmadd} %0,%1,%2,%3" 4783 [(set_attr "type" "dmul")]) 4784 4785(define_insn "" 4786 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4787 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 4788 (match_operand:DF 2 "gpc_reg_operand" "f")) 4789 (match_operand:DF 3 "gpc_reg_operand" "f")))] 4790 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 4791 "{fms|fmsub} %0,%1,%2,%3" 4792 [(set_attr "type" "dmul")]) 4793 4794(define_insn "" 4795 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4796 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 4797 (match_operand:DF 2 "gpc_reg_operand" "f")) 4798 (match_operand:DF 3 "gpc_reg_operand" "f"))))] 4799 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4800 && HONOR_SIGNED_ZEROS (DFmode)" 4801 "{fnma|fnmadd} %0,%1,%2,%3" 4802 [(set_attr "type" "dmul")]) 4803 4804(define_insn "" 4805 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4806 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) 4807 (match_operand:DF 2 "gpc_reg_operand" "f")) 4808 (match_operand:DF 3 "gpc_reg_operand" "f")))] 4809 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4810 && ! HONOR_SIGNED_ZEROS (DFmode)" 4811 "{fnma|fnmadd} %0,%1,%2,%3" 4812 [(set_attr "type" "dmul")]) 4813 4814(define_insn "" 4815 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4816 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 4817 (match_operand:DF 2 "gpc_reg_operand" "f")) 4818 (match_operand:DF 3 "gpc_reg_operand" "f"))))] 4819 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4820 && HONOR_SIGNED_ZEROS (DFmode)" 4821 "{fnms|fnmsub} %0,%1,%2,%3" 4822 [(set_attr "type" "dmul")]) 4823 4824(define_insn "" 4825 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4826 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") 4827 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 4828 (match_operand:DF 2 "gpc_reg_operand" "f"))))] 4829 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 4830 && ! HONOR_SIGNED_ZEROS (DFmode)" 4831 "{fnms|fnmsub} %0,%1,%2,%3" 4832 [(set_attr "type" "dmul")]) 4833 4834(define_insn "sqrtdf2" 4835 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4836 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 4837 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" 4838 "fsqrt %0,%1" 4839 [(set_attr "type" "dsqrt")]) 4840 4841;; The conditional move instructions allow us to perform max and min 4842;; operations even when 4843 4844(define_expand "maxdf3" 4845 [(set (match_operand:DF 0 "gpc_reg_operand" "") 4846 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") 4847 (match_operand:DF 2 "gpc_reg_operand" "")) 4848 (match_dup 1) 4849 (match_dup 2)))] 4850 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4851 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") 4852 4853(define_expand "mindf3" 4854 [(set (match_operand:DF 0 "gpc_reg_operand" "") 4855 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") 4856 (match_operand:DF 2 "gpc_reg_operand" "")) 4857 (match_dup 2) 4858 (match_dup 1)))] 4859 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4860 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") 4861 4862(define_split 4863 [(set (match_operand:DF 0 "gpc_reg_operand" "") 4864 (match_operator:DF 3 "min_max_operator" 4865 [(match_operand:DF 1 "gpc_reg_operand" "") 4866 (match_operand:DF 2 "gpc_reg_operand" "")]))] 4867 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4868 [(const_int 0)] 4869 " 4870{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), 4871 operands[1], operands[2]); 4872 DONE; 4873}") 4874 4875(define_expand "movdfcc" 4876 [(set (match_operand:DF 0 "gpc_reg_operand" "") 4877 (if_then_else:DF (match_operand 1 "comparison_operator" "") 4878 (match_operand:DF 2 "gpc_reg_operand" "") 4879 (match_operand:DF 3 "gpc_reg_operand" "")))] 4880 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4881 " 4882{ 4883 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 4884 DONE; 4885 else 4886 FAIL; 4887}") 4888 4889(define_insn "*fseldfdf4" 4890 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4891 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 4892 (match_operand:DF 4 "zero_fp_constant" "F")) 4893 (match_operand:DF 2 "gpc_reg_operand" "f") 4894 (match_operand:DF 3 "gpc_reg_operand" "f")))] 4895 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" 4896 "fsel %0,%1,%2,%3" 4897 [(set_attr "type" "fp")]) 4898 4899(define_insn "*fselsfdf4" 4900 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4901 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 4902 (match_operand:SF 4 "zero_fp_constant" "F")) 4903 (match_operand:DF 2 "gpc_reg_operand" "f") 4904 (match_operand:DF 3 "gpc_reg_operand" "f")))] 4905 "TARGET_PPC_GFXOPT" 4906 "fsel %0,%1,%2,%3" 4907 [(set_attr "type" "fp")]) 4908 4909;; Conversions to and from floating-point. 4910 4911(define_expand "fixuns_truncsfsi2" 4912 [(set (match_operand:SI 0 "gpc_reg_operand" "") 4913 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] 4914 "TARGET_HARD_FLOAT && !TARGET_FPRS" 4915 "") 4916 4917(define_expand "fix_truncsfsi2" 4918 [(set (match_operand:SI 0 "gpc_reg_operand" "") 4919 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] 4920 "TARGET_HARD_FLOAT && !TARGET_FPRS" 4921 "") 4922 4923; For each of these conversions, there is a define_expand, a define_insn 4924; with a '#' template, and a define_split (with C code). The idea is 4925; to allow constant folding with the template of the define_insn, 4926; then to have the insns split later (between sched1 and final). 4927 4928(define_expand "floatsidf2" 4929 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") 4930 (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 4931 (use (match_dup 2)) 4932 (use (match_dup 3)) 4933 (clobber (match_dup 4)) 4934 (clobber (match_dup 5)) 4935 (clobber (match_dup 6))])] 4936 "TARGET_HARD_FLOAT && TARGET_FPRS" 4937 " 4938{ 4939 if (TARGET_POWERPC64) 4940 { 4941 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 4942 rtx t1 = gen_reg_rtx (DImode); 4943 rtx t2 = gen_reg_rtx (DImode); 4944 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); 4945 DONE; 4946 } 4947 4948 operands[2] = force_reg (SImode, GEN_INT (0x43300000)); 4949 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); 4950 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); 4951 operands[5] = gen_reg_rtx (DFmode); 4952 operands[6] = gen_reg_rtx (SImode); 4953}") 4954 4955(define_insn "*floatsidf2_internal" 4956 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") 4957 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 4958 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 4959 (use (match_operand:DF 3 "gpc_reg_operand" "f")) 4960 (clobber (match_operand:DF 4 "memory_operand" "=o")) 4961 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) 4962 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] 4963 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 4964 "#" 4965 [(set_attr "length" "24")]) 4966 4967(define_split 4968 [(set (match_operand:DF 0 "gpc_reg_operand" "") 4969 (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 4970 (use (match_operand:SI 2 "gpc_reg_operand" "")) 4971 (use (match_operand:DF 3 "gpc_reg_operand" "")) 4972 (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) 4973 (clobber (match_operand:DF 5 "gpc_reg_operand" "")) 4974 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] 4975 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 4976 [(set (match_operand:DF 0 "gpc_reg_operand" "") 4977 (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 4978 (use (match_operand:SI 2 "gpc_reg_operand" "")) 4979 (use (match_operand:DF 3 "gpc_reg_operand" "")) 4980 (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) 4981 (clobber (match_operand:DF 5 "gpc_reg_operand" "")) 4982 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] 4983 " 4984{ 4985 rtx lowword, highword; 4986 if (GET_CODE (operands[4]) != MEM) 4987 abort(); 4988 highword = XEXP (operands[4], 0); 4989 lowword = plus_constant (highword, 4); 4990 if (! WORDS_BIG_ENDIAN) 4991 { 4992 rtx tmp; 4993 tmp = highword; highword = lowword; lowword = tmp; 4994 } 4995 4996 emit_insn (gen_xorsi3 (operands[6], operands[1], 4997 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); 4998 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); 4999 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); 5000 emit_move_insn (operands[5], operands[4]); 5001 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); 5002 DONE; 5003}") 5004 5005(define_expand "floatunssisf2" 5006 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5007 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] 5008 "TARGET_HARD_FLOAT && !TARGET_FPRS" 5009 "") 5010 5011(define_expand "floatunssidf2" 5012 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") 5013 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5014 (use (match_dup 2)) 5015 (use (match_dup 3)) 5016 (clobber (match_dup 4)) 5017 (clobber (match_dup 5))])] 5018 "TARGET_HARD_FLOAT && TARGET_FPRS" 5019 " 5020{ 5021 if (TARGET_POWERPC64) 5022 { 5023 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 5024 rtx t1 = gen_reg_rtx (DImode); 5025 rtx t2 = gen_reg_rtx (DImode); 5026 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, 5027 t1, t2)); 5028 DONE; 5029 } 5030 5031 operands[2] = force_reg (SImode, GEN_INT (0x43300000)); 5032 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); 5033 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); 5034 operands[5] = gen_reg_rtx (DFmode); 5035}") 5036 5037(define_insn "*floatunssidf2_internal" 5038 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") 5039 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5040 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 5041 (use (match_operand:DF 3 "gpc_reg_operand" "f")) 5042 (clobber (match_operand:DF 4 "memory_operand" "=o")) 5043 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] 5044 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5045 "#" 5046 [(set_attr "length" "20")]) 5047 5048(define_split 5049 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5050 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5051 (use (match_operand:SI 2 "gpc_reg_operand" "")) 5052 (use (match_operand:DF 3 "gpc_reg_operand" "")) 5053 (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) 5054 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] 5055 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5056 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5057 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5058 (use (match_operand:SI 2 "gpc_reg_operand" "")) 5059 (use (match_operand:DF 3 "gpc_reg_operand" "")) 5060 (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) 5061 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] 5062 " 5063{ 5064 rtx lowword, highword; 5065 if (GET_CODE (operands[4]) != MEM) 5066 abort(); 5067 highword = XEXP (operands[4], 0); 5068 lowword = plus_constant (highword, 4); 5069 if (! WORDS_BIG_ENDIAN) 5070 { 5071 rtx tmp; 5072 tmp = highword; highword = lowword; lowword = tmp; 5073 } 5074 5075 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); 5076 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); 5077 emit_move_insn (operands[5], operands[4]); 5078 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); 5079 DONE; 5080}") 5081 5082(define_expand "fix_truncdfsi2" 5083 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 5084 (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) 5085 (clobber (match_dup 2)) 5086 (clobber (match_dup 3))])] 5087 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" 5088 " 5089{ 5090 operands[2] = gen_reg_rtx (DImode); 5091 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 5092}") 5093 5094(define_insn "*fix_truncdfsi2_internal" 5095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5096 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) 5097 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) 5098 (clobber (match_operand:DI 3 "memory_operand" "=o"))] 5099 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" 5100 "#" 5101 [(set_attr "length" "16")]) 5102 5103(define_split 5104 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5105 (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) 5106 (clobber (match_operand:DI 2 "gpc_reg_operand" "")) 5107 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] 5108 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" 5109 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5110 (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) 5111 (clobber (match_operand:DI 2 "gpc_reg_operand" "")) 5112 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] 5113 " 5114{ 5115 rtx lowword; 5116 if (GET_CODE (operands[3]) != MEM) 5117 abort(); 5118 lowword = XEXP (operands[3], 0); 5119 if (WORDS_BIG_ENDIAN) 5120 lowword = plus_constant (lowword, 4); 5121 5122 emit_insn (gen_fctiwz (operands[2], operands[1])); 5123 emit_move_insn (operands[3], operands[2]); 5124 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); 5125 DONE; 5126}") 5127 5128; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) 5129; rather than (set (subreg:SI (reg)) (fix:SI ...)) 5130; because the first makes it clear that operand 0 is not live 5131; before the instruction. 5132(define_insn "fctiwz" 5133 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") 5134 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 5135 UNSPEC_FCTIWZ))] 5136 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" 5137 "{fcirz|fctiwz} %0,%1" 5138 [(set_attr "type" "fp")]) 5139 5140(define_expand "floatsisf2" 5141 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5142 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] 5143 "TARGET_HARD_FLOAT && !TARGET_FPRS" 5144 "") 5145 5146(define_insn "floatdidf2" 5147 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5148 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] 5149 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5150 "fcfid %0,%1" 5151 [(set_attr "type" "fp")]) 5152 5153(define_insn_and_split "floatsidf_ppc64" 5154 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5155 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5156 (clobber (match_operand:DI 2 "memory_operand" "=o")) 5157 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) 5158 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] 5159 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5160 "#" 5161 "&& 1" 5162 [(set (match_dup 3) (sign_extend:DI (match_dup 1))) 5163 (set (match_dup 2) (match_dup 3)) 5164 (set (match_dup 4) (match_dup 2)) 5165 (set (match_dup 0) (float:DF (match_dup 4)))] 5166 "") 5167 5168(define_insn_and_split "floatunssidf_ppc64" 5169 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5170 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5171 (clobber (match_operand:DI 2 "memory_operand" "=o")) 5172 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) 5173 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] 5174 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5175 "#" 5176 "&& 1" 5177 [(set (match_dup 3) (zero_extend:DI (match_dup 1))) 5178 (set (match_dup 2) (match_dup 3)) 5179 (set (match_dup 4) (match_dup 2)) 5180 (set (match_dup 0) (float:DF (match_dup 4)))] 5181 "") 5182 5183(define_insn "fix_truncdfdi2" 5184 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") 5185 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] 5186 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5187 "fctidz %0,%1" 5188 [(set_attr "type" "fp")]) 5189 5190(define_expand "floatdisf2" 5191 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5192 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] 5193 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5194 " 5195{ 5196 rtx val = operands[1]; 5197 if (!flag_unsafe_math_optimizations) 5198 { 5199 rtx label = gen_label_rtx (); 5200 val = gen_reg_rtx (DImode); 5201 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label)); 5202 emit_label (label); 5203 } 5204 emit_insn (gen_floatdisf2_internal1 (operands[0], val)); 5205 DONE; 5206}") 5207 5208;; This is not IEEE compliant if rounding mode is "round to nearest". 5209;; If the DI->DF conversion is inexact, then it's possible to suffer 5210;; from double rounding. 5211(define_insn_and_split "floatdisf2_internal1" 5212 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5213 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) 5214 (clobber (match_scratch:DF 2 "=f"))] 5215 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5216 "#" 5217 "&& reload_completed" 5218 [(set (match_dup 2) 5219 (float:DF (match_dup 1))) 5220 (set (match_dup 0) 5221 (float_truncate:SF (match_dup 2)))] 5222 "") 5223 5224;; Twiddles bits to avoid double rounding. 5225;; Bits that might be truncated when converting to DFmode are replaced 5226;; by a bit that won't be lost at that stage, but is below the SFmode 5227;; rounding position. 5228(define_expand "floatdisf2_internal2" 5229 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") 5230 (const_int 53))) 5231 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1) 5232 (const_int 2047))) 5233 (clobber (scratch:CC))]) 5234 (set (match_dup 3) (plus:DI (match_dup 3) 5235 (const_int 1))) 5236 (set (match_dup 0) (plus:DI (match_dup 0) 5237 (const_int 2047))) 5238 (set (match_dup 4) (compare:CCUNS (match_dup 3) 5239 (const_int 2))) 5240 (set (match_dup 0) (ior:DI (match_dup 0) 5241 (match_dup 1))) 5242 (parallel [(set (match_dup 0) (and:DI (match_dup 0) 5243 (const_int -2048))) 5244 (clobber (scratch:CC))]) 5245 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) 5246 (label_ref (match_operand:DI 2 "" "")) 5247 (pc))) 5248 (set (match_dup 0) (match_dup 1))] 5249 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" 5250 " 5251{ 5252 operands[3] = gen_reg_rtx (DImode); 5253 operands[4] = gen_reg_rtx (CCUNSmode); 5254}") 5255 5256;; Define the DImode operations that can be done in a small number 5257;; of instructions. The & constraints are to prevent the register 5258;; allocator from allocating registers that overlap with the inputs 5259;; (for example, having an input in 7,8 and an output in 6,7). We 5260;; also allow for the output being the same as one of the inputs. 5261 5262(define_insn "*adddi3_noppc64" 5263 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") 5264 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") 5265 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] 5266 "! TARGET_POWERPC64" 5267 "* 5268{ 5269 if (WORDS_BIG_ENDIAN) 5270 return (GET_CODE (operands[2])) != CONST_INT 5271 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" 5272 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; 5273 else 5274 return (GET_CODE (operands[2])) != CONST_INT 5275 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" 5276 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; 5277}" 5278 [(set_attr "length" "8")]) 5279 5280(define_insn "*subdi3_noppc64" 5281 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") 5282 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") 5283 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] 5284 "! TARGET_POWERPC64" 5285 "* 5286{ 5287 if (WORDS_BIG_ENDIAN) 5288 return (GET_CODE (operands[1]) != CONST_INT) 5289 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" 5290 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; 5291 else 5292 return (GET_CODE (operands[1]) != CONST_INT) 5293 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" 5294 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; 5295}" 5296 [(set_attr "length" "8")]) 5297 5298(define_insn "*negdi2_noppc64" 5299 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 5300 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] 5301 "! TARGET_POWERPC64" 5302 "* 5303{ 5304 return (WORDS_BIG_ENDIAN) 5305 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" 5306 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; 5307}" 5308 [(set_attr "length" "8")]) 5309 5310(define_expand "mulsidi3" 5311 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5312 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 5313 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 5314 "! TARGET_POWERPC64" 5315 " 5316{ 5317 if (! TARGET_POWER && ! TARGET_POWERPC) 5318 { 5319 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 5320 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 5321 emit_insn (gen_mull_call ()); 5322 if (WORDS_BIG_ENDIAN) 5323 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); 5324 else 5325 { 5326 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), 5327 gen_rtx_REG (SImode, 3)); 5328 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), 5329 gen_rtx_REG (SImode, 4)); 5330 } 5331 DONE; 5332 } 5333 else if (TARGET_POWER) 5334 { 5335 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); 5336 DONE; 5337 } 5338}") 5339 5340(define_insn "mulsidi3_mq" 5341 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 5342 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 5343 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 5344 (clobber (match_scratch:SI 3 "=q"))] 5345 "TARGET_POWER" 5346 "mul %0,%1,%2\;mfmq %L0" 5347 [(set_attr "type" "imul") 5348 (set_attr "length" "8")]) 5349 5350(define_insn "*mulsidi3_no_mq" 5351 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 5352 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 5353 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 5354 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" 5355 "* 5356{ 5357 return (WORDS_BIG_ENDIAN) 5358 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" 5359 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; 5360}" 5361 [(set_attr "type" "imul") 5362 (set_attr "length" "8")]) 5363 5364(define_split 5365 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5366 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 5367 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 5368 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" 5369 [(set (match_dup 3) 5370 (truncate:SI 5371 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 5372 (sign_extend:DI (match_dup 2))) 5373 (const_int 32)))) 5374 (set (match_dup 4) 5375 (mult:SI (match_dup 1) 5376 (match_dup 2)))] 5377 " 5378{ 5379 int endian = (WORDS_BIG_ENDIAN == 0); 5380 operands[3] = operand_subword (operands[0], endian, 0, DImode); 5381 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); 5382}") 5383 5384(define_expand "umulsidi3" 5385 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5386 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 5387 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 5388 "TARGET_POWERPC && ! TARGET_POWERPC64" 5389 " 5390{ 5391 if (TARGET_POWER) 5392 { 5393 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); 5394 DONE; 5395 } 5396}") 5397 5398(define_insn "umulsidi3_mq" 5399 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 5400 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 5401 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 5402 (clobber (match_scratch:SI 3 "=q"))] 5403 "TARGET_POWERPC && TARGET_POWER" 5404 "* 5405{ 5406 return (WORDS_BIG_ENDIAN) 5407 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" 5408 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; 5409}" 5410 [(set_attr "type" "imul") 5411 (set_attr "length" "8")]) 5412 5413(define_insn "*umulsidi3_no_mq" 5414 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 5415 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 5416 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 5417 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" 5418 "* 5419{ 5420 return (WORDS_BIG_ENDIAN) 5421 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" 5422 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; 5423}" 5424 [(set_attr "type" "imul") 5425 (set_attr "length" "8")]) 5426 5427(define_split 5428 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5429 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 5430 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 5431 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" 5432 [(set (match_dup 3) 5433 (truncate:SI 5434 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 5435 (zero_extend:DI (match_dup 2))) 5436 (const_int 32)))) 5437 (set (match_dup 4) 5438 (mult:SI (match_dup 1) 5439 (match_dup 2)))] 5440 " 5441{ 5442 int endian = (WORDS_BIG_ENDIAN == 0); 5443 operands[3] = operand_subword (operands[0], endian, 0, DImode); 5444 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); 5445}") 5446 5447(define_expand "smulsi3_highpart" 5448 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5449 (truncate:SI 5450 (lshiftrt:DI (mult:DI (sign_extend:DI 5451 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5452 (sign_extend:DI 5453 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5454 (const_int 32))))] 5455 "" 5456 " 5457{ 5458 if (! TARGET_POWER && ! TARGET_POWERPC) 5459 { 5460 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 5461 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 5462 emit_insn (gen_mulh_call ()); 5463 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 5464 DONE; 5465 } 5466 else if (TARGET_POWER) 5467 { 5468 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); 5469 DONE; 5470 } 5471}") 5472 5473(define_insn "smulsi3_highpart_mq" 5474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5475 (truncate:SI 5476 (lshiftrt:DI (mult:DI (sign_extend:DI 5477 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5478 (sign_extend:DI 5479 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5480 (const_int 32)))) 5481 (clobber (match_scratch:SI 3 "=q"))] 5482 "TARGET_POWER" 5483 "mul %0,%1,%2" 5484 [(set_attr "type" "imul")]) 5485 5486(define_insn "*smulsi3_highpart_no_mq" 5487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5488 (truncate:SI 5489 (lshiftrt:DI (mult:DI (sign_extend:DI 5490 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5491 (sign_extend:DI 5492 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5493 (const_int 32))))] 5494 "TARGET_POWERPC && ! TARGET_POWER" 5495 "mulhw %0,%1,%2" 5496 [(set_attr "type" "imul")]) 5497 5498(define_expand "umulsi3_highpart" 5499 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5500 (truncate:SI 5501 (lshiftrt:DI (mult:DI (zero_extend:DI 5502 (match_operand:SI 1 "gpc_reg_operand" "")) 5503 (zero_extend:DI 5504 (match_operand:SI 2 "gpc_reg_operand" ""))) 5505 (const_int 32))))] 5506 "TARGET_POWERPC" 5507 " 5508{ 5509 if (TARGET_POWER) 5510 { 5511 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); 5512 DONE; 5513 } 5514}") 5515 5516(define_insn "umulsi3_highpart_mq" 5517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5518 (truncate:SI 5519 (lshiftrt:DI (mult:DI (zero_extend:DI 5520 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5521 (zero_extend:DI 5522 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5523 (const_int 32)))) 5524 (clobber (match_scratch:SI 3 "=q"))] 5525 "TARGET_POWERPC && TARGET_POWER" 5526 "mulhwu %0,%1,%2" 5527 [(set_attr "type" "imul")]) 5528 5529(define_insn "*umulsi3_highpart_no_mq" 5530 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5531 (truncate:SI 5532 (lshiftrt:DI (mult:DI (zero_extend:DI 5533 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5534 (zero_extend:DI 5535 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5536 (const_int 32))))] 5537 "TARGET_POWERPC && ! TARGET_POWER" 5538 "mulhwu %0,%1,%2" 5539 [(set_attr "type" "imul")]) 5540 5541;; If operands 0 and 2 are in the same register, we have a problem. But 5542;; operands 0 and 1 (the usual case) can be in the same register. That's 5543;; why we have the strange constraints below. 5544(define_insn "ashldi3_power" 5545 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") 5546 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 5547 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 5548 (clobber (match_scratch:SI 3 "=X,q,q,q"))] 5549 "TARGET_POWER" 5550 "@ 5551 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} 5552 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 5553 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 5554 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" 5555 [(set_attr "length" "8")]) 5556 5557(define_insn "lshrdi3_power" 5558 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") 5559 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 5560 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 5561 (clobber (match_scratch:SI 3 "=X,q,q,q"))] 5562 "TARGET_POWER" 5563 "@ 5564 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} 5565 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 5566 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 5567 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" 5568 [(set_attr "length" "8")]) 5569 5570;; Shift by a variable amount is too complex to be worth open-coding. We 5571;; just handle shifts by constants. 5572(define_insn "ashrdi3_power" 5573 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 5574 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 5575 (match_operand:SI 2 "const_int_operand" "M,i"))) 5576 (clobber (match_scratch:SI 3 "=X,q"))] 5577 "TARGET_POWER" 5578 "@ 5579 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 5580 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" 5581 [(set_attr "length" "8")]) 5582 5583(define_insn "ashrdi3_no_power" 5584 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") 5585 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 5586 (match_operand:SI 2 "const_int_operand" "M,i")))] 5587 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" 5588 "@ 5589 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 5590 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" 5591 [(set_attr "length" "8,12")]) 5592 5593(define_insn "*ashrdisi3_noppc64" 5594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5595 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 5596 (const_int 32)) 4))] 5597 "TARGET_32BIT && !TARGET_POWERPC64" 5598 "* 5599{ 5600 if (REGNO (operands[0]) == REGNO (operands[1])) 5601 return \"\"; 5602 else 5603 return \"mr %0,%1\"; 5604}" 5605 [(set_attr "length" "4")]) 5606 5607 5608;; PowerPC64 DImode operations. 5609 5610(define_expand "adddi3" 5611 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5612 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5613 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] 5614 "" 5615 " 5616{ 5617 if (! TARGET_POWERPC64) 5618 { 5619 if (non_short_cint_operand (operands[2], DImode)) 5620 FAIL; 5621 } 5622 else 5623 if (GET_CODE (operands[2]) == CONST_INT 5624 && ! add_operand (operands[2], DImode)) 5625 { 5626 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 5627 ? operands[0] : gen_reg_rtx (DImode)); 5628 5629 HOST_WIDE_INT val = INTVAL (operands[2]); 5630 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; 5631 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); 5632 5633 if (!CONST_OK_FOR_LETTER_P (rest, 'L')) 5634 FAIL; 5635 5636 /* The ordering here is important for the prolog expander. 5637 When space is allocated from the stack, adding 'low' first may 5638 produce a temporary deallocation (which would be bad). */ 5639 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); 5640 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); 5641 DONE; 5642 } 5643}") 5644 5645;; Discourage ai/addic because of carry but provide it in an alternative 5646;; allowing register zero as source. 5647 5648(define_insn "*adddi3_internal1" 5649 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") 5650 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") 5651 (match_operand:DI 2 "add_operand" "r,I,I,L")))] 5652 "TARGET_POWERPC64" 5653 "@ 5654 add %0,%1,%2 5655 addi %0,%1,%2 5656 addic %0,%1,%2 5657 addis %0,%1,%v2") 5658 5659(define_insn "*adddi3_internal2" 5660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 5661 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") 5662 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) 5663 (const_int 0))) 5664 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 5665 "TARGET_64BIT" 5666 "@ 5667 add. %3,%1,%2 5668 addic. %3,%1,%2 5669 # 5670 #" 5671 [(set_attr "type" "fast_compare,compare,compare,compare") 5672 (set_attr "length" "4,4,8,8")]) 5673 5674(define_split 5675 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 5676 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5677 (match_operand:DI 2 "reg_or_short_operand" "")) 5678 (const_int 0))) 5679 (clobber (match_scratch:DI 3 ""))] 5680 "TARGET_POWERPC64 && reload_completed" 5681 [(set (match_dup 3) 5682 (plus:DI (match_dup 1) (match_dup 2))) 5683 (set (match_dup 0) 5684 (compare:CC (match_dup 3) 5685 (const_int 0)))] 5686 "") 5687 5688(define_insn "*adddi3_internal3" 5689 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 5690 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") 5691 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) 5692 (const_int 0))) 5693 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 5694 (plus:DI (match_dup 1) (match_dup 2)))] 5695 "TARGET_64BIT" 5696 "@ 5697 add. %0,%1,%2 5698 addic. %0,%1,%2 5699 # 5700 #" 5701 [(set_attr "type" "fast_compare,compare,compare,compare") 5702 (set_attr "length" "4,4,8,8")]) 5703 5704(define_split 5705 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 5706 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5707 (match_operand:DI 2 "reg_or_short_operand" "")) 5708 (const_int 0))) 5709 (set (match_operand:DI 0 "gpc_reg_operand" "") 5710 (plus:DI (match_dup 1) (match_dup 2)))] 5711 "TARGET_POWERPC64 && reload_completed" 5712 [(set (match_dup 0) 5713 (plus:DI (match_dup 1) (match_dup 2))) 5714 (set (match_dup 3) 5715 (compare:CC (match_dup 0) 5716 (const_int 0)))] 5717 "") 5718 5719;; Split an add that we can't do in one insn into two insns, each of which 5720;; does one 16-bit part. This is used by combine. Note that the low-order 5721;; add should be last in case the result gets used in an address. 5722 5723(define_split 5724 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5725 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5726 (match_operand:DI 2 "non_add_cint_operand" "")))] 5727 "TARGET_POWERPC64" 5728 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 5729 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 5730" 5731{ 5732 HOST_WIDE_INT val = INTVAL (operands[2]); 5733 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; 5734 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); 5735 5736 operands[4] = GEN_INT (low); 5737 if (CONST_OK_FOR_LETTER_P (rest, 'L')) 5738 operands[3] = GEN_INT (rest); 5739 else if (! no_new_pseudos) 5740 { 5741 operands[3] = gen_reg_rtx (DImode); 5742 emit_move_insn (operands[3], operands[2]); 5743 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 5744 DONE; 5745 } 5746 else 5747 FAIL; 5748}") 5749 5750(define_insn "one_cmpldi2" 5751 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 5752 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 5753 "TARGET_POWERPC64" 5754 "nor %0,%1,%1") 5755 5756(define_insn "" 5757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 5758 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 5759 (const_int 0))) 5760 (clobber (match_scratch:DI 2 "=r,r"))] 5761 "TARGET_64BIT" 5762 "@ 5763 nor. %2,%1,%1 5764 #" 5765 [(set_attr "type" "compare") 5766 (set_attr "length" "4,8")]) 5767 5768(define_split 5769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 5770 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 5771 (const_int 0))) 5772 (clobber (match_scratch:DI 2 ""))] 5773 "TARGET_POWERPC64 && reload_completed" 5774 [(set (match_dup 2) 5775 (not:DI (match_dup 1))) 5776 (set (match_dup 0) 5777 (compare:CC (match_dup 2) 5778 (const_int 0)))] 5779 "") 5780 5781(define_insn "" 5782 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 5783 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 5784 (const_int 0))) 5785 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 5786 (not:DI (match_dup 1)))] 5787 "TARGET_64BIT" 5788 "@ 5789 nor. %0,%1,%1 5790 #" 5791 [(set_attr "type" "compare") 5792 (set_attr "length" "4,8")]) 5793 5794(define_split 5795 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 5796 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 5797 (const_int 0))) 5798 (set (match_operand:DI 0 "gpc_reg_operand" "") 5799 (not:DI (match_dup 1)))] 5800 "TARGET_POWERPC64 && reload_completed" 5801 [(set (match_dup 0) 5802 (not:DI (match_dup 1))) 5803 (set (match_dup 2) 5804 (compare:CC (match_dup 0) 5805 (const_int 0)))] 5806 "") 5807 5808(define_insn "" 5809 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 5810 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") 5811 (match_operand:DI 2 "gpc_reg_operand" "r,r")))] 5812 "TARGET_POWERPC64" 5813 "@ 5814 subf %0,%2,%1 5815 subfic %0,%2,%1") 5816 5817(define_insn "" 5818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 5819 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 5820 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 5821 (const_int 0))) 5822 (clobber (match_scratch:DI 3 "=r,r"))] 5823 "TARGET_64BIT" 5824 "@ 5825 subf. %3,%2,%1 5826 #" 5827 [(set_attr "type" "fast_compare") 5828 (set_attr "length" "4,8")]) 5829 5830(define_split 5831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 5832 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5833 (match_operand:DI 2 "gpc_reg_operand" "")) 5834 (const_int 0))) 5835 (clobber (match_scratch:DI 3 ""))] 5836 "TARGET_POWERPC64 && reload_completed" 5837 [(set (match_dup 3) 5838 (minus:DI (match_dup 1) (match_dup 2))) 5839 (set (match_dup 0) 5840 (compare:CC (match_dup 3) 5841 (const_int 0)))] 5842 "") 5843 5844(define_insn "" 5845 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 5846 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 5847 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 5848 (const_int 0))) 5849 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 5850 (minus:DI (match_dup 1) (match_dup 2)))] 5851 "TARGET_64BIT" 5852 "@ 5853 subf. %0,%2,%1 5854 #" 5855 [(set_attr "type" "fast_compare") 5856 (set_attr "length" "4,8")]) 5857 5858(define_split 5859 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 5860 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5861 (match_operand:DI 2 "gpc_reg_operand" "")) 5862 (const_int 0))) 5863 (set (match_operand:DI 0 "gpc_reg_operand" "") 5864 (minus:DI (match_dup 1) (match_dup 2)))] 5865 "TARGET_POWERPC64 && reload_completed" 5866 [(set (match_dup 0) 5867 (minus:DI (match_dup 1) (match_dup 2))) 5868 (set (match_dup 3) 5869 (compare:CC (match_dup 0) 5870 (const_int 0)))] 5871 "") 5872 5873(define_expand "subdi3" 5874 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5875 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") 5876 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] 5877 "" 5878 " 5879{ 5880 if (GET_CODE (operands[2]) == CONST_INT) 5881 { 5882 emit_insn (gen_adddi3 (operands[0], operands[1], 5883 negate_rtx (DImode, operands[2]))); 5884 DONE; 5885 } 5886}") 5887 5888(define_insn_and_split "absdi2" 5889 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 5890 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) 5891 (clobber (match_scratch:DI 2 "=&r,&r"))] 5892 "TARGET_POWERPC64" 5893 "#" 5894 "&& reload_completed" 5895 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) 5896 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) 5897 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] 5898 "") 5899 5900(define_insn_and_split "*nabsdi2" 5901 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 5902 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) 5903 (clobber (match_scratch:DI 2 "=&r,&r"))] 5904 "TARGET_POWERPC64" 5905 "#" 5906 "&& reload_completed" 5907 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) 5908 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) 5909 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] 5910 "") 5911 5912(define_expand "negdi2" 5913 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5914 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] 5915 "" 5916 "") 5917 5918(define_insn "" 5919 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 5920 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 5921 "TARGET_POWERPC64" 5922 "neg %0,%1") 5923 5924(define_insn "" 5925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 5926 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 5927 (const_int 0))) 5928 (clobber (match_scratch:DI 2 "=r,r"))] 5929 "TARGET_64BIT" 5930 "@ 5931 neg. %2,%1 5932 #" 5933 [(set_attr "type" "fast_compare") 5934 (set_attr "length" "4,8")]) 5935 5936(define_split 5937 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 5938 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) 5939 (const_int 0))) 5940 (clobber (match_scratch:DI 2 ""))] 5941 "TARGET_POWERPC64 && reload_completed" 5942 [(set (match_dup 2) 5943 (neg:DI (match_dup 1))) 5944 (set (match_dup 0) 5945 (compare:CC (match_dup 2) 5946 (const_int 0)))] 5947 "") 5948 5949(define_insn "" 5950 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 5951 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 5952 (const_int 0))) 5953 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 5954 (neg:DI (match_dup 1)))] 5955 "TARGET_64BIT" 5956 "@ 5957 neg. %0,%1 5958 #" 5959 [(set_attr "type" "fast_compare") 5960 (set_attr "length" "4,8")]) 5961 5962(define_split 5963 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 5964 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) 5965 (const_int 0))) 5966 (set (match_operand:DI 0 "gpc_reg_operand" "") 5967 (neg:DI (match_dup 1)))] 5968 "TARGET_POWERPC64 && reload_completed" 5969 [(set (match_dup 0) 5970 (neg:DI (match_dup 1))) 5971 (set (match_dup 2) 5972 (compare:CC (match_dup 0) 5973 (const_int 0)))] 5974 "") 5975 5976(define_insn "clzdi2" 5977 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 5978 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 5979 "TARGET_POWERPC64" 5980 "cntlzd %0,%1") 5981 5982(define_expand "ctzdi2" 5983 [(set (match_dup 2) 5984 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) 5985 (parallel [(set (match_dup 3) (and:DI (match_dup 1) 5986 (match_dup 2))) 5987 (clobber (scratch:CC))]) 5988 (set (match_dup 4) (clz:DI (match_dup 3))) 5989 (set (match_operand:DI 0 "gpc_reg_operand" "=r") 5990 (minus:DI (const_int 63) (match_dup 4)))] 5991 "TARGET_POWERPC64" 5992 { 5993 operands[2] = gen_reg_rtx (DImode); 5994 operands[3] = gen_reg_rtx (DImode); 5995 operands[4] = gen_reg_rtx (DImode); 5996 }) 5997 5998(define_expand "ffsdi2" 5999 [(set (match_dup 2) 6000 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) 6001 (parallel [(set (match_dup 3) (and:DI (match_dup 1) 6002 (match_dup 2))) 6003 (clobber (scratch:CC))]) 6004 (set (match_dup 4) (clz:DI (match_dup 3))) 6005 (set (match_operand:DI 0 "gpc_reg_operand" "=r") 6006 (minus:DI (const_int 64) (match_dup 4)))] 6007 "TARGET_POWERPC64" 6008 { 6009 operands[2] = gen_reg_rtx (DImode); 6010 operands[3] = gen_reg_rtx (DImode); 6011 operands[4] = gen_reg_rtx (DImode); 6012 }) 6013 6014(define_insn "muldi3" 6015 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6016 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") 6017 (match_operand:DI 2 "gpc_reg_operand" "r")))] 6018 "TARGET_POWERPC64" 6019 "mulld %0,%1,%2" 6020 [(set_attr "type" "lmul")]) 6021 6022(define_insn "*muldi3_internal1" 6023 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6024 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") 6025 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 6026 (const_int 0))) 6027 (clobber (match_scratch:DI 3 "=r,r"))] 6028 "TARGET_POWERPC64" 6029 "@ 6030 mulld. %3,%1,%2 6031 #" 6032 [(set_attr "type" "lmul_compare") 6033 (set_attr "length" "4,8")]) 6034 6035(define_split 6036 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6037 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") 6038 (match_operand:DI 2 "gpc_reg_operand" "")) 6039 (const_int 0))) 6040 (clobber (match_scratch:DI 3 ""))] 6041 "TARGET_POWERPC64 && reload_completed" 6042 [(set (match_dup 3) 6043 (mult:DI (match_dup 1) (match_dup 2))) 6044 (set (match_dup 0) 6045 (compare:CC (match_dup 3) 6046 (const_int 0)))] 6047 "") 6048 6049(define_insn "*muldi3_internal2" 6050 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6051 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") 6052 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 6053 (const_int 0))) 6054 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6055 (mult:DI (match_dup 1) (match_dup 2)))] 6056 "TARGET_POWERPC64" 6057 "@ 6058 mulld. %0,%1,%2 6059 #" 6060 [(set_attr "type" "lmul_compare") 6061 (set_attr "length" "4,8")]) 6062 6063(define_split 6064 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6065 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") 6066 (match_operand:DI 2 "gpc_reg_operand" "")) 6067 (const_int 0))) 6068 (set (match_operand:DI 0 "gpc_reg_operand" "") 6069 (mult:DI (match_dup 1) (match_dup 2)))] 6070 "TARGET_POWERPC64 && reload_completed" 6071 [(set (match_dup 0) 6072 (mult:DI (match_dup 1) (match_dup 2))) 6073 (set (match_dup 3) 6074 (compare:CC (match_dup 0) 6075 (const_int 0)))] 6076 "") 6077 6078(define_insn "smuldi3_highpart" 6079 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6080 (truncate:DI 6081 (lshiftrt:TI (mult:TI (sign_extend:TI 6082 (match_operand:DI 1 "gpc_reg_operand" "%r")) 6083 (sign_extend:TI 6084 (match_operand:DI 2 "gpc_reg_operand" "r"))) 6085 (const_int 64))))] 6086 "TARGET_POWERPC64" 6087 "mulhd %0,%1,%2" 6088 [(set_attr "type" "lmul")]) 6089 6090(define_insn "umuldi3_highpart" 6091 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6092 (truncate:DI 6093 (lshiftrt:TI (mult:TI (zero_extend:TI 6094 (match_operand:DI 1 "gpc_reg_operand" "%r")) 6095 (zero_extend:TI 6096 (match_operand:DI 2 "gpc_reg_operand" "r"))) 6097 (const_int 64))))] 6098 "TARGET_POWERPC64" 6099 "mulhdu %0,%1,%2" 6100 [(set_attr "type" "lmul")]) 6101 6102(define_expand "divdi3" 6103 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6104 (div:DI (match_operand:DI 1 "gpc_reg_operand" "") 6105 (match_operand:DI 2 "reg_or_cint_operand" "")))] 6106 "TARGET_POWERPC64" 6107 " 6108{ 6109 if (GET_CODE (operands[2]) == CONST_INT 6110 && INTVAL (operands[2]) > 0 6111 && exact_log2 (INTVAL (operands[2])) >= 0) 6112 ; 6113 else 6114 operands[2] = force_reg (DImode, operands[2]); 6115}") 6116 6117(define_expand "moddi3" 6118 [(use (match_operand:DI 0 "gpc_reg_operand" "")) 6119 (use (match_operand:DI 1 "gpc_reg_operand" "")) 6120 (use (match_operand:DI 2 "reg_or_cint_operand" ""))] 6121 "TARGET_POWERPC64" 6122 " 6123{ 6124 int i; 6125 rtx temp1; 6126 rtx temp2; 6127 6128 if (GET_CODE (operands[2]) != CONST_INT 6129 || INTVAL (operands[2]) <= 0 6130 || (i = exact_log2 (INTVAL (operands[2]))) < 0) 6131 FAIL; 6132 6133 temp1 = gen_reg_rtx (DImode); 6134 temp2 = gen_reg_rtx (DImode); 6135 6136 emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); 6137 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); 6138 emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); 6139 DONE; 6140}") 6141 6142(define_insn "" 6143 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6144 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6145 (match_operand:DI 2 "exact_log2_cint_operand" "N")))] 6146 "TARGET_POWERPC64" 6147 "sradi %0,%1,%p2\;addze %0,%0" 6148 [(set_attr "length" "8")]) 6149 6150(define_insn "" 6151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6152 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6153 (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) 6154 (const_int 0))) 6155 (clobber (match_scratch:DI 3 "=r,r"))] 6156 "TARGET_64BIT" 6157 "@ 6158 sradi %3,%1,%p2\;addze. %3,%3 6159 #" 6160 [(set_attr "type" "compare") 6161 (set_attr "length" "8,12")]) 6162 6163(define_split 6164 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6165 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") 6166 (match_operand:DI 2 "exact_log2_cint_operand" "")) 6167 (const_int 0))) 6168 (clobber (match_scratch:DI 3 ""))] 6169 "TARGET_POWERPC64 && reload_completed" 6170 [(set (match_dup 3) 6171 (div:DI (match_dup 1) (match_dup 2))) 6172 (set (match_dup 0) 6173 (compare:CC (match_dup 3) 6174 (const_int 0)))] 6175 "") 6176 6177(define_insn "" 6178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6179 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6180 (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) 6181 (const_int 0))) 6182 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6183 (div:DI (match_dup 1) (match_dup 2)))] 6184 "TARGET_64BIT" 6185 "@ 6186 sradi %0,%1,%p2\;addze. %0,%0 6187 #" 6188 [(set_attr "type" "compare") 6189 (set_attr "length" "8,12")]) 6190 6191(define_split 6192 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6193 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") 6194 (match_operand:DI 2 "exact_log2_cint_operand" "")) 6195 (const_int 0))) 6196 (set (match_operand:DI 0 "gpc_reg_operand" "") 6197 (div:DI (match_dup 1) (match_dup 2)))] 6198 "TARGET_POWERPC64 && reload_completed" 6199 [(set (match_dup 0) 6200 (div:DI (match_dup 1) (match_dup 2))) 6201 (set (match_dup 3) 6202 (compare:CC (match_dup 0) 6203 (const_int 0)))] 6204 "") 6205 6206(define_insn "" 6207 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6208 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6209 (match_operand:DI 2 "gpc_reg_operand" "r")))] 6210 "TARGET_POWERPC64" 6211 "divd %0,%1,%2" 6212 [(set_attr "type" "ldiv")]) 6213 6214(define_insn "udivdi3" 6215 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6216 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6217 (match_operand:DI 2 "gpc_reg_operand" "r")))] 6218 "TARGET_POWERPC64" 6219 "divdu %0,%1,%2" 6220 [(set_attr "type" "ldiv")]) 6221 6222(define_insn "rotldi3" 6223 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6224 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6225 (match_operand:DI 2 "reg_or_cint_operand" "ri")))] 6226 "TARGET_POWERPC64" 6227 "rld%I2cl %0,%1,%H2,0") 6228 6229(define_insn "*rotldi3_internal2" 6230 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6231 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6232 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6233 (const_int 0))) 6234 (clobber (match_scratch:DI 3 "=r,r"))] 6235 "TARGET_64BIT" 6236 "@ 6237 rld%I2cl. %3,%1,%H2,0 6238 #" 6239 [(set_attr "type" "delayed_compare") 6240 (set_attr "length" "4,8")]) 6241 6242(define_split 6243 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6244 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6245 (match_operand:DI 2 "reg_or_cint_operand" "")) 6246 (const_int 0))) 6247 (clobber (match_scratch:DI 3 ""))] 6248 "TARGET_POWERPC64 && reload_completed" 6249 [(set (match_dup 3) 6250 (rotate:DI (match_dup 1) (match_dup 2))) 6251 (set (match_dup 0) 6252 (compare:CC (match_dup 3) 6253 (const_int 0)))] 6254 "") 6255 6256(define_insn "*rotldi3_internal3" 6257 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6258 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6259 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6260 (const_int 0))) 6261 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6262 (rotate:DI (match_dup 1) (match_dup 2)))] 6263 "TARGET_64BIT" 6264 "@ 6265 rld%I2cl. %0,%1,%H2,0 6266 #" 6267 [(set_attr "type" "delayed_compare") 6268 (set_attr "length" "4,8")]) 6269 6270(define_split 6271 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6272 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6273 (match_operand:DI 2 "reg_or_cint_operand" "")) 6274 (const_int 0))) 6275 (set (match_operand:DI 0 "gpc_reg_operand" "") 6276 (rotate:DI (match_dup 1) (match_dup 2)))] 6277 "TARGET_POWERPC64 && reload_completed" 6278 [(set (match_dup 0) 6279 (rotate:DI (match_dup 1) (match_dup 2))) 6280 (set (match_dup 3) 6281 (compare:CC (match_dup 0) 6282 (const_int 0)))] 6283 "") 6284 6285(define_insn "*rotldi3_internal4" 6286 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6287 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6288 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 6289 (match_operand:DI 3 "mask64_operand" "n")))] 6290 "TARGET_POWERPC64" 6291 "rld%I2c%B3 %0,%1,%H2,%S3") 6292 6293(define_insn "*rotldi3_internal5" 6294 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6295 (compare:CC (and:DI 6296 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6297 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6298 (match_operand:DI 3 "mask64_operand" "n,n")) 6299 (const_int 0))) 6300 (clobber (match_scratch:DI 4 "=r,r"))] 6301 "TARGET_64BIT" 6302 "@ 6303 rld%I2c%B3. %4,%1,%H2,%S3 6304 #" 6305 [(set_attr "type" "delayed_compare") 6306 (set_attr "length" "4,8")]) 6307 6308(define_split 6309 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6310 (compare:CC (and:DI 6311 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6312 (match_operand:DI 2 "reg_or_cint_operand" "")) 6313 (match_operand:DI 3 "mask64_operand" "")) 6314 (const_int 0))) 6315 (clobber (match_scratch:DI 4 ""))] 6316 "TARGET_POWERPC64 && reload_completed" 6317 [(set (match_dup 4) 6318 (and:DI (rotate:DI (match_dup 1) 6319 (match_dup 2)) 6320 (match_dup 3))) 6321 (set (match_dup 0) 6322 (compare:CC (match_dup 4) 6323 (const_int 0)))] 6324 "") 6325 6326(define_insn "*rotldi3_internal6" 6327 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 6328 (compare:CC (and:DI 6329 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6330 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6331 (match_operand:DI 3 "mask64_operand" "n,n")) 6332 (const_int 0))) 6333 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6334 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6335 "TARGET_64BIT" 6336 "@ 6337 rld%I2c%B3. %0,%1,%H2,%S3 6338 #" 6339 [(set_attr "type" "delayed_compare") 6340 (set_attr "length" "4,8")]) 6341 6342(define_split 6343 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 6344 (compare:CC (and:DI 6345 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6346 (match_operand:DI 2 "reg_or_cint_operand" "")) 6347 (match_operand:DI 3 "mask64_operand" "")) 6348 (const_int 0))) 6349 (set (match_operand:DI 0 "gpc_reg_operand" "") 6350 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6351 "TARGET_POWERPC64 && reload_completed" 6352 [(set (match_dup 0) 6353 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) 6354 (set (match_dup 4) 6355 (compare:CC (match_dup 0) 6356 (const_int 0)))] 6357 "") 6358 6359(define_insn "*rotldi3_internal7" 6360 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6361 (zero_extend:DI 6362 (subreg:QI 6363 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6364 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] 6365 "TARGET_POWERPC64" 6366 "rld%I2cl %0,%1,%H2,56") 6367 6368(define_insn "*rotldi3_internal8" 6369 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6370 (compare:CC (zero_extend:DI 6371 (subreg:QI 6372 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6373 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6374 (const_int 0))) 6375 (clobber (match_scratch:DI 3 "=r,r"))] 6376 "TARGET_64BIT" 6377 "@ 6378 rld%I2cl. %3,%1,%H2,56 6379 #" 6380 [(set_attr "type" "delayed_compare") 6381 (set_attr "length" "4,8")]) 6382 6383(define_split 6384 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6385 (compare:CC (zero_extend:DI 6386 (subreg:QI 6387 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6388 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6389 (const_int 0))) 6390 (clobber (match_scratch:DI 3 ""))] 6391 "TARGET_POWERPC64 && reload_completed" 6392 [(set (match_dup 3) 6393 (zero_extend:DI (subreg:QI 6394 (rotate:DI (match_dup 1) 6395 (match_dup 2)) 0))) 6396 (set (match_dup 0) 6397 (compare:CC (match_dup 3) 6398 (const_int 0)))] 6399 "") 6400 6401(define_insn "*rotldi3_internal9" 6402 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6403 (compare:CC (zero_extend:DI 6404 (subreg:QI 6405 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6406 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6407 (const_int 0))) 6408 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6409 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6410 "TARGET_64BIT" 6411 "@ 6412 rld%I2cl. %0,%1,%H2,56 6413 #" 6414 [(set_attr "type" "delayed_compare") 6415 (set_attr "length" "4,8")]) 6416 6417(define_split 6418 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6419 (compare:CC (zero_extend:DI 6420 (subreg:QI 6421 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6422 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6423 (const_int 0))) 6424 (set (match_operand:DI 0 "gpc_reg_operand" "") 6425 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6426 "TARGET_POWERPC64 && reload_completed" 6427 [(set (match_dup 0) 6428 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 6429 (set (match_dup 3) 6430 (compare:CC (match_dup 0) 6431 (const_int 0)))] 6432 "") 6433 6434(define_insn "*rotldi3_internal10" 6435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6436 (zero_extend:DI 6437 (subreg:HI 6438 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6439 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] 6440 "TARGET_POWERPC64" 6441 "rld%I2cl %0,%1,%H2,48") 6442 6443(define_insn "*rotldi3_internal11" 6444 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6445 (compare:CC (zero_extend:DI 6446 (subreg:HI 6447 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6448 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6449 (const_int 0))) 6450 (clobber (match_scratch:DI 3 "=r,r"))] 6451 "TARGET_64BIT" 6452 "@ 6453 rld%I2cl. %3,%1,%H2,48 6454 #" 6455 [(set_attr "type" "delayed_compare") 6456 (set_attr "length" "4,8")]) 6457 6458(define_split 6459 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6460 (compare:CC (zero_extend:DI 6461 (subreg:HI 6462 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6463 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6464 (const_int 0))) 6465 (clobber (match_scratch:DI 3 ""))] 6466 "TARGET_POWERPC64 && reload_completed" 6467 [(set (match_dup 3) 6468 (zero_extend:DI (subreg:HI 6469 (rotate:DI (match_dup 1) 6470 (match_dup 2)) 0))) 6471 (set (match_dup 0) 6472 (compare:CC (match_dup 3) 6473 (const_int 0)))] 6474 "") 6475 6476(define_insn "*rotldi3_internal12" 6477 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6478 (compare:CC (zero_extend:DI 6479 (subreg:HI 6480 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6481 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6482 (const_int 0))) 6483 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6484 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6485 "TARGET_64BIT" 6486 "@ 6487 rld%I2cl. %0,%1,%H2,48 6488 #" 6489 [(set_attr "type" "delayed_compare") 6490 (set_attr "length" "4,8")]) 6491 6492(define_split 6493 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6494 (compare:CC (zero_extend:DI 6495 (subreg:HI 6496 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6497 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6498 (const_int 0))) 6499 (set (match_operand:DI 0 "gpc_reg_operand" "") 6500 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6501 "TARGET_POWERPC64 && reload_completed" 6502 [(set (match_dup 0) 6503 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 6504 (set (match_dup 3) 6505 (compare:CC (match_dup 0) 6506 (const_int 0)))] 6507 "") 6508 6509(define_insn "*rotldi3_internal13" 6510 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6511 (zero_extend:DI 6512 (subreg:SI 6513 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6514 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] 6515 "TARGET_POWERPC64" 6516 "rld%I2cl %0,%1,%H2,32") 6517 6518(define_insn "*rotldi3_internal14" 6519 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6520 (compare:CC (zero_extend:DI 6521 (subreg:SI 6522 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6523 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6524 (const_int 0))) 6525 (clobber (match_scratch:DI 3 "=r,r"))] 6526 "TARGET_64BIT" 6527 "@ 6528 rld%I2cl. %3,%1,%H2,32 6529 #" 6530 [(set_attr "type" "delayed_compare") 6531 (set_attr "length" "4,8")]) 6532 6533(define_split 6534 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6535 (compare:CC (zero_extend:DI 6536 (subreg:SI 6537 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6538 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6539 (const_int 0))) 6540 (clobber (match_scratch:DI 3 ""))] 6541 "TARGET_POWERPC64 && reload_completed" 6542 [(set (match_dup 3) 6543 (zero_extend:DI (subreg:SI 6544 (rotate:DI (match_dup 1) 6545 (match_dup 2)) 0))) 6546 (set (match_dup 0) 6547 (compare:CC (match_dup 3) 6548 (const_int 0)))] 6549 "") 6550 6551(define_insn "*rotldi3_internal15" 6552 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6553 (compare:CC (zero_extend:DI 6554 (subreg:SI 6555 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6556 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6557 (const_int 0))) 6558 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6559 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6560 "TARGET_64BIT" 6561 "@ 6562 rld%I2cl. %0,%1,%H2,32 6563 #" 6564 [(set_attr "type" "delayed_compare") 6565 (set_attr "length" "4,8")]) 6566 6567(define_split 6568 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6569 (compare:CC (zero_extend:DI 6570 (subreg:SI 6571 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6572 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6573 (const_int 0))) 6574 (set (match_operand:DI 0 "gpc_reg_operand" "") 6575 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6576 "TARGET_POWERPC64 && reload_completed" 6577 [(set (match_dup 0) 6578 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 6579 (set (match_dup 3) 6580 (compare:CC (match_dup 0) 6581 (const_int 0)))] 6582 "") 6583 6584(define_expand "ashldi3" 6585 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6586 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6587 (match_operand:SI 2 "reg_or_cint_operand" "")))] 6588 "TARGET_POWERPC64 || TARGET_POWER" 6589 " 6590{ 6591 if (TARGET_POWERPC64) 6592 ; 6593 else if (TARGET_POWER) 6594 { 6595 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); 6596 DONE; 6597 } 6598 else 6599 FAIL; 6600}") 6601 6602(define_insn "*ashldi3_internal1" 6603 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6604 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6605 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 6606 "TARGET_POWERPC64" 6607 "sld%I2 %0,%1,%H2" 6608 [(set_attr "length" "8")]) 6609 6610(define_insn "*ashldi3_internal2" 6611 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6612 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6613 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6614 (const_int 0))) 6615 (clobber (match_scratch:DI 3 "=r,r"))] 6616 "TARGET_64BIT" 6617 "@ 6618 sld%I2. %3,%1,%H2 6619 #" 6620 [(set_attr "type" "delayed_compare") 6621 (set_attr "length" "4,8")]) 6622 6623(define_split 6624 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6625 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6626 (match_operand:SI 2 "reg_or_cint_operand" "")) 6627 (const_int 0))) 6628 (clobber (match_scratch:DI 3 ""))] 6629 "TARGET_POWERPC64 && reload_completed" 6630 [(set (match_dup 3) 6631 (ashift:DI (match_dup 1) (match_dup 2))) 6632 (set (match_dup 0) 6633 (compare:CC (match_dup 3) 6634 (const_int 0)))] 6635 "") 6636 6637(define_insn "*ashldi3_internal3" 6638 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6639 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6640 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6641 (const_int 0))) 6642 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6643 (ashift:DI (match_dup 1) (match_dup 2)))] 6644 "TARGET_64BIT" 6645 "@ 6646 sld%I2. %0,%1,%H2 6647 #" 6648 [(set_attr "type" "delayed_compare") 6649 (set_attr "length" "4,8")]) 6650 6651(define_split 6652 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6653 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6654 (match_operand:SI 2 "reg_or_cint_operand" "")) 6655 (const_int 0))) 6656 (set (match_operand:DI 0 "gpc_reg_operand" "") 6657 (ashift:DI (match_dup 1) (match_dup 2)))] 6658 "TARGET_POWERPC64 && reload_completed" 6659 [(set (match_dup 0) 6660 (ashift:DI (match_dup 1) (match_dup 2))) 6661 (set (match_dup 3) 6662 (compare:CC (match_dup 0) 6663 (const_int 0)))] 6664 "") 6665 6666(define_insn "*ashldi3_internal4" 6667 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6668 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6669 (match_operand:SI 2 "const_int_operand" "i")) 6670 (match_operand:DI 3 "const_int_operand" "n")))] 6671 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" 6672 "rldic %0,%1,%H2,%W3") 6673 6674(define_insn "ashldi3_internal5" 6675 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6676 (compare:CC 6677 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6678 (match_operand:SI 2 "const_int_operand" "i,i")) 6679 (match_operand:DI 3 "const_int_operand" "n,n")) 6680 (const_int 0))) 6681 (clobber (match_scratch:DI 4 "=r,r"))] 6682 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" 6683 "@ 6684 rldic. %4,%1,%H2,%W3 6685 #" 6686 [(set_attr "type" "delayed_compare") 6687 (set_attr "length" "4,8")]) 6688 6689(define_split 6690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6691 (compare:CC 6692 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6693 (match_operand:SI 2 "const_int_operand" "")) 6694 (match_operand:DI 3 "const_int_operand" "")) 6695 (const_int 0))) 6696 (clobber (match_scratch:DI 4 ""))] 6697 "TARGET_POWERPC64 && reload_completed 6698 && includes_rldic_lshift_p (operands[2], operands[3])" 6699 [(set (match_dup 4) 6700 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 6701 (match_dup 3))) 6702 (set (match_dup 0) 6703 (compare:CC (match_dup 4) 6704 (const_int 0)))] 6705 "") 6706 6707(define_insn "*ashldi3_internal6" 6708 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 6709 (compare:CC 6710 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6711 (match_operand:SI 2 "const_int_operand" "i,i")) 6712 (match_operand:DI 3 "const_int_operand" "n,n")) 6713 (const_int 0))) 6714 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6715 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6716 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" 6717 "@ 6718 rldic. %0,%1,%H2,%W3 6719 #" 6720 [(set_attr "type" "delayed_compare") 6721 (set_attr "length" "4,8")]) 6722 6723(define_split 6724 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 6725 (compare:CC 6726 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6727 (match_operand:SI 2 "const_int_operand" "")) 6728 (match_operand:DI 3 "const_int_operand" "")) 6729 (const_int 0))) 6730 (set (match_operand:DI 0 "gpc_reg_operand" "") 6731 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6732 "TARGET_POWERPC64 && reload_completed 6733 && includes_rldic_lshift_p (operands[2], operands[3])" 6734 [(set (match_dup 0) 6735 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 6736 (match_dup 3))) 6737 (set (match_dup 4) 6738 (compare:CC (match_dup 0) 6739 (const_int 0)))] 6740 "") 6741 6742(define_insn "*ashldi3_internal7" 6743 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6744 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6745 (match_operand:SI 2 "const_int_operand" "i")) 6746 (match_operand:DI 3 "mask64_operand" "n")))] 6747 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" 6748 "rldicr %0,%1,%H2,%S3") 6749 6750(define_insn "ashldi3_internal8" 6751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6752 (compare:CC 6753 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6754 (match_operand:SI 2 "const_int_operand" "i,i")) 6755 (match_operand:DI 3 "mask64_operand" "n,n")) 6756 (const_int 0))) 6757 (clobber (match_scratch:DI 4 "=r,r"))] 6758 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" 6759 "@ 6760 rldicr. %4,%1,%H2,%S3 6761 #" 6762 [(set_attr "type" "delayed_compare") 6763 (set_attr "length" "4,8")]) 6764 6765(define_split 6766 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6767 (compare:CC 6768 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6769 (match_operand:SI 2 "const_int_operand" "")) 6770 (match_operand:DI 3 "mask64_operand" "")) 6771 (const_int 0))) 6772 (clobber (match_scratch:DI 4 ""))] 6773 "TARGET_POWERPC64 && reload_completed 6774 && includes_rldicr_lshift_p (operands[2], operands[3])" 6775 [(set (match_dup 4) 6776 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 6777 (match_dup 3))) 6778 (set (match_dup 0) 6779 (compare:CC (match_dup 4) 6780 (const_int 0)))] 6781 "") 6782 6783(define_insn "*ashldi3_internal9" 6784 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 6785 (compare:CC 6786 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6787 (match_operand:SI 2 "const_int_operand" "i,i")) 6788 (match_operand:DI 3 "mask64_operand" "n,n")) 6789 (const_int 0))) 6790 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6791 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6792 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" 6793 "@ 6794 rldicr. %0,%1,%H2,%S3 6795 #" 6796 [(set_attr "type" "delayed_compare") 6797 (set_attr "length" "4,8")]) 6798 6799(define_split 6800 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 6801 (compare:CC 6802 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6803 (match_operand:SI 2 "const_int_operand" "")) 6804 (match_operand:DI 3 "mask64_operand" "")) 6805 (const_int 0))) 6806 (set (match_operand:DI 0 "gpc_reg_operand" "") 6807 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6808 "TARGET_POWERPC64 && reload_completed 6809 && includes_rldicr_lshift_p (operands[2], operands[3])" 6810 [(set (match_dup 0) 6811 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 6812 (match_dup 3))) 6813 (set (match_dup 4) 6814 (compare:CC (match_dup 0) 6815 (const_int 0)))] 6816 "") 6817 6818(define_expand "lshrdi3" 6819 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6820 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 6821 (match_operand:SI 2 "reg_or_cint_operand" "")))] 6822 "TARGET_POWERPC64 || TARGET_POWER" 6823 " 6824{ 6825 if (TARGET_POWERPC64) 6826 ; 6827 else if (TARGET_POWER) 6828 { 6829 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); 6830 DONE; 6831 } 6832 else 6833 FAIL; 6834}") 6835 6836(define_insn "*lshrdi3_internal1" 6837 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6838 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6839 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 6840 "TARGET_POWERPC64" 6841 "srd%I2 %0,%1,%H2") 6842 6843(define_insn "*lshrdi3_internal2" 6844 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6845 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6846 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6847 (const_int 0))) 6848 (clobber (match_scratch:DI 3 "=r,r"))] 6849 "TARGET_64BIT " 6850 "@ 6851 srd%I2. %3,%1,%H2 6852 #" 6853 [(set_attr "type" "delayed_compare") 6854 (set_attr "length" "4,8")]) 6855 6856(define_split 6857 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6858 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 6859 (match_operand:SI 2 "reg_or_cint_operand" "")) 6860 (const_int 0))) 6861 (clobber (match_scratch:DI 3 ""))] 6862 "TARGET_POWERPC64 && reload_completed" 6863 [(set (match_dup 3) 6864 (lshiftrt:DI (match_dup 1) (match_dup 2))) 6865 (set (match_dup 0) 6866 (compare:CC (match_dup 3) 6867 (const_int 0)))] 6868 "") 6869 6870(define_insn "*lshrdi3_internal3" 6871 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6872 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6873 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6874 (const_int 0))) 6875 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6876 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 6877 "TARGET_64BIT" 6878 "@ 6879 srd%I2. %0,%1,%H2 6880 #" 6881 [(set_attr "type" "delayed_compare") 6882 (set_attr "length" "4,8")]) 6883 6884(define_split 6885 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6886 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 6887 (match_operand:SI 2 "reg_or_cint_operand" "")) 6888 (const_int 0))) 6889 (set (match_operand:DI 0 "gpc_reg_operand" "") 6890 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 6891 "TARGET_POWERPC64 && reload_completed" 6892 [(set (match_dup 0) 6893 (lshiftrt:DI (match_dup 1) (match_dup 2))) 6894 (set (match_dup 3) 6895 (compare:CC (match_dup 0) 6896 (const_int 0)))] 6897 "") 6898 6899(define_expand "ashrdi3" 6900 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6901 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 6902 (match_operand:SI 2 "reg_or_cint_operand" "")))] 6903 "WORDS_BIG_ENDIAN" 6904 " 6905{ 6906 if (TARGET_POWERPC64) 6907 ; 6908 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) 6909 { 6910 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); 6911 DONE; 6912 } 6913 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT 6914 && WORDS_BIG_ENDIAN) 6915 { 6916 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); 6917 DONE; 6918 } 6919 else 6920 FAIL; 6921}") 6922 6923(define_insn "*ashrdi3_internal1" 6924 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6925 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6926 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 6927 "TARGET_POWERPC64" 6928 "srad%I2 %0,%1,%H2") 6929 6930(define_insn "*ashrdi3_internal2" 6931 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6932 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6933 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6934 (const_int 0))) 6935 (clobber (match_scratch:DI 3 "=r,r"))] 6936 "TARGET_64BIT" 6937 "@ 6938 srad%I2. %3,%1,%H2 6939 #" 6940 [(set_attr "type" "delayed_compare") 6941 (set_attr "length" "4,8")]) 6942 6943(define_split 6944 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6945 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 6946 (match_operand:SI 2 "reg_or_cint_operand" "")) 6947 (const_int 0))) 6948 (clobber (match_scratch:DI 3 ""))] 6949 "TARGET_POWERPC64 && reload_completed" 6950 [(set (match_dup 3) 6951 (ashiftrt:DI (match_dup 1) (match_dup 2))) 6952 (set (match_dup 0) 6953 (compare:CC (match_dup 3) 6954 (const_int 0)))] 6955 "") 6956 6957(define_insn "*ashrdi3_internal3" 6958 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6959 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6960 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6961 (const_int 0))) 6962 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6963 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 6964 "TARGET_64BIT" 6965 "@ 6966 srad%I2. %0,%1,%H2 6967 #" 6968 [(set_attr "type" "delayed_compare") 6969 (set_attr "length" "4,8")]) 6970 6971(define_split 6972 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6973 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 6974 (match_operand:SI 2 "reg_or_cint_operand" "")) 6975 (const_int 0))) 6976 (set (match_operand:DI 0 "gpc_reg_operand" "") 6977 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 6978 "TARGET_POWERPC64 && reload_completed" 6979 [(set (match_dup 0) 6980 (ashiftrt:DI (match_dup 1) (match_dup 2))) 6981 (set (match_dup 3) 6982 (compare:CC (match_dup 0) 6983 (const_int 0)))] 6984 "") 6985 6986(define_insn "anddi3" 6987 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") 6988 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") 6989 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t"))) 6990 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))] 6991 "TARGET_POWERPC64" 6992 "@ 6993 and %0,%1,%2 6994 rldic%B2 %0,%1,0,%S2 6995 andi. %0,%1,%b2 6996 andis. %0,%1,%u2 6997 #" 6998 [(set_attr "length" "4,4,4,4,8")]) 6999 7000(define_split 7001 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7002 (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7003 (match_operand:DI 2 "mask64_2_operand" ""))) 7004 (clobber (match_scratch:CC 3 ""))] 7005 "TARGET_POWERPC64 7006 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) 7007 && !mask64_operand (operands[2], DImode)" 7008 [(set (match_dup 0) 7009 (and:DI (rotate:DI (match_dup 1) 7010 (match_dup 4)) 7011 (match_dup 5))) 7012 (set (match_dup 0) 7013 (and:DI (rotate:DI (match_dup 0) 7014 (match_dup 6)) 7015 (match_dup 7)))] 7016 " 7017{ 7018 build_mask64_2_operands (operands[2], &operands[4]); 7019}") 7020 7021(define_insn "*anddi3_internal2" 7022 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") 7023 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 7024 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) 7025 (const_int 0))) 7026 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) 7027 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] 7028 "TARGET_64BIT" 7029 "@ 7030 and. %3,%1,%2 7031 rldic%B2. %3,%1,0,%S2 7032 andi. %3,%1,%b2 7033 andis. %3,%1,%u2 7034 # 7035 # 7036 # 7037 # 7038 # 7039 #" 7040 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") 7041 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) 7042 7043(define_split 7044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7045 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7046 (match_operand:DI 2 "and64_operand" "")) 7047 (const_int 0))) 7048 (clobber (match_scratch:DI 3 "")) 7049 (clobber (match_scratch:CC 4 ""))] 7050 "TARGET_POWERPC64 && reload_completed" 7051 [(parallel [(set (match_dup 3) 7052 (and:DI (match_dup 1) 7053 (match_dup 2))) 7054 (clobber (match_dup 4))]) 7055 (set (match_dup 0) 7056 (compare:CC (match_dup 3) 7057 (const_int 0)))] 7058 "") 7059 7060(define_split 7061 [(set (match_operand:CC 0 "cc_reg_operand" "") 7062 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7063 (match_operand:DI 2 "mask64_2_operand" "")) 7064 (const_int 0))) 7065 (clobber (match_scratch:DI 3 "")) 7066 (clobber (match_scratch:CC 4 ""))] 7067 "TARGET_POWERPC64 && reload_completed 7068 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) 7069 && !mask64_operand (operands[2], DImode)" 7070 [(set (match_dup 3) 7071 (and:DI (rotate:DI (match_dup 1) 7072 (match_dup 5)) 7073 (match_dup 6))) 7074 (parallel [(set (match_dup 0) 7075 (compare:CC (and:DI (rotate:DI (match_dup 3) 7076 (match_dup 7)) 7077 (match_dup 8)) 7078 (const_int 0))) 7079 (clobber (match_dup 3))])] 7080 " 7081{ 7082 build_mask64_2_operands (operands[2], &operands[5]); 7083}") 7084 7085(define_insn "*anddi3_internal3" 7086 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") 7087 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 7088 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) 7089 (const_int 0))) 7090 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") 7091 (and:DI (match_dup 1) (match_dup 2))) 7092 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] 7093 "TARGET_64BIT" 7094 "@ 7095 and. %0,%1,%2 7096 rldic%B2. %0,%1,0,%S2 7097 andi. %0,%1,%b2 7098 andis. %0,%1,%u2 7099 # 7100 # 7101 # 7102 # 7103 # 7104 #" 7105 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") 7106 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) 7107 7108(define_split 7109 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7110 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7111 (match_operand:DI 2 "and64_operand" "")) 7112 (const_int 0))) 7113 (set (match_operand:DI 0 "gpc_reg_operand" "") 7114 (and:DI (match_dup 1) (match_dup 2))) 7115 (clobber (match_scratch:CC 4 ""))] 7116 "TARGET_POWERPC64 && reload_completed" 7117 [(parallel [(set (match_dup 0) 7118 (and:DI (match_dup 1) (match_dup 2))) 7119 (clobber (match_dup 4))]) 7120 (set (match_dup 3) 7121 (compare:CC (match_dup 0) 7122 (const_int 0)))] 7123 "") 7124 7125(define_split 7126 [(set (match_operand:CC 3 "cc_reg_operand" "") 7127 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7128 (match_operand:DI 2 "mask64_2_operand" "")) 7129 (const_int 0))) 7130 (set (match_operand:DI 0 "gpc_reg_operand" "") 7131 (and:DI (match_dup 1) (match_dup 2))) 7132 (clobber (match_scratch:CC 4 ""))] 7133 "TARGET_POWERPC64 && reload_completed 7134 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) 7135 && !mask64_operand (operands[2], DImode)" 7136 [(set (match_dup 0) 7137 (and:DI (rotate:DI (match_dup 1) 7138 (match_dup 5)) 7139 (match_dup 6))) 7140 (parallel [(set (match_dup 3) 7141 (compare:CC (and:DI (rotate:DI (match_dup 0) 7142 (match_dup 7)) 7143 (match_dup 8)) 7144 (const_int 0))) 7145 (set (match_dup 0) 7146 (and:DI (rotate:DI (match_dup 0) 7147 (match_dup 7)) 7148 (match_dup 8)))])] 7149 " 7150{ 7151 build_mask64_2_operands (operands[2], &operands[5]); 7152}") 7153 7154(define_expand "iordi3" 7155 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7156 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") 7157 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] 7158 "TARGET_POWERPC64" 7159 " 7160{ 7161 if (non_logical_cint_operand (operands[2], DImode)) 7162 { 7163 HOST_WIDE_INT value; 7164 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 7165 ? operands[0] : gen_reg_rtx (DImode)); 7166 7167 if (GET_CODE (operands[2]) == CONST_INT) 7168 { 7169 value = INTVAL (operands[2]); 7170 emit_insn (gen_iordi3 (tmp, operands[1], 7171 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 7172 } 7173 else 7174 { 7175 value = CONST_DOUBLE_LOW (operands[2]); 7176 emit_insn (gen_iordi3 (tmp, operands[1], 7177 immed_double_const (value 7178 & (~ (HOST_WIDE_INT) 0xffff), 7179 0, DImode))); 7180 } 7181 7182 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 7183 DONE; 7184 } 7185}") 7186 7187(define_expand "xordi3" 7188 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7189 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") 7190 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] 7191 "TARGET_POWERPC64" 7192 " 7193{ 7194 if (non_logical_cint_operand (operands[2], DImode)) 7195 { 7196 HOST_WIDE_INT value; 7197 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 7198 ? operands[0] : gen_reg_rtx (DImode)); 7199 7200 if (GET_CODE (operands[2]) == CONST_INT) 7201 { 7202 value = INTVAL (operands[2]); 7203 emit_insn (gen_xordi3 (tmp, operands[1], 7204 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 7205 } 7206 else 7207 { 7208 value = CONST_DOUBLE_LOW (operands[2]); 7209 emit_insn (gen_xordi3 (tmp, operands[1], 7210 immed_double_const (value 7211 & (~ (HOST_WIDE_INT) 0xffff), 7212 0, DImode))); 7213 } 7214 7215 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 7216 DONE; 7217 } 7218}") 7219 7220(define_insn "*booldi3_internal1" 7221 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") 7222 (match_operator:DI 3 "boolean_or_operator" 7223 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") 7224 (match_operand:DI 2 "logical_operand" "r,K,JF")]))] 7225 "TARGET_POWERPC64" 7226 "@ 7227 %q3 %0,%1,%2 7228 %q3i %0,%1,%b2 7229 %q3is %0,%1,%u2") 7230 7231(define_insn "*booldi3_internal2" 7232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7233 (compare:CC (match_operator:DI 4 "boolean_or_operator" 7234 [(match_operand:DI 1 "gpc_reg_operand" "%r,r") 7235 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7236 (const_int 0))) 7237 (clobber (match_scratch:DI 3 "=r,r"))] 7238 "TARGET_64BIT" 7239 "@ 7240 %q4. %3,%1,%2 7241 #" 7242 [(set_attr "type" "compare") 7243 (set_attr "length" "4,8")]) 7244 7245(define_split 7246 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7247 (compare:CC (match_operator:DI 4 "boolean_operator" 7248 [(match_operand:DI 1 "gpc_reg_operand" "") 7249 (match_operand:DI 2 "gpc_reg_operand" "")]) 7250 (const_int 0))) 7251 (clobber (match_scratch:DI 3 ""))] 7252 "TARGET_POWERPC64 && reload_completed" 7253 [(set (match_dup 3) (match_dup 4)) 7254 (set (match_dup 0) 7255 (compare:CC (match_dup 3) 7256 (const_int 0)))] 7257 "") 7258 7259(define_insn "*booldi3_internal3" 7260 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7261 (compare:CC (match_operator:DI 4 "boolean_operator" 7262 [(match_operand:DI 1 "gpc_reg_operand" "%r,r") 7263 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7264 (const_int 0))) 7265 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7266 (match_dup 4))] 7267 "TARGET_64BIT" 7268 "@ 7269 %q4. %0,%1,%2 7270 #" 7271 [(set_attr "type" "compare") 7272 (set_attr "length" "4,8")]) 7273 7274(define_split 7275 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7276 (compare:CC (match_operator:DI 4 "boolean_operator" 7277 [(match_operand:DI 1 "gpc_reg_operand" "") 7278 (match_operand:DI 2 "gpc_reg_operand" "")]) 7279 (const_int 0))) 7280 (set (match_operand:DI 0 "gpc_reg_operand" "") 7281 (match_dup 4))] 7282 "TARGET_POWERPC64 && reload_completed" 7283 [(set (match_dup 0) (match_dup 4)) 7284 (set (match_dup 3) 7285 (compare:CC (match_dup 0) 7286 (const_int 0)))] 7287 "") 7288 7289;; Split a logical operation that we can't do in one insn into two insns, 7290;; each of which does one 16-bit part. This is used by combine. 7291 7292(define_split 7293 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7294 (match_operator:DI 3 "boolean_or_operator" 7295 [(match_operand:DI 1 "gpc_reg_operand" "") 7296 (match_operand:DI 2 "non_logical_cint_operand" "")]))] 7297 "TARGET_POWERPC64" 7298 [(set (match_dup 0) (match_dup 4)) 7299 (set (match_dup 0) (match_dup 5))] 7300" 7301{ 7302 rtx i3,i4; 7303 7304 if (GET_CODE (operands[2]) == CONST_DOUBLE) 7305 { 7306 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); 7307 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), 7308 0, DImode); 7309 i4 = GEN_INT (value & 0xffff); 7310 } 7311 else 7312 { 7313 i3 = GEN_INT (INTVAL (operands[2]) 7314 & (~ (HOST_WIDE_INT) 0xffff)); 7315 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); 7316 } 7317 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, 7318 operands[1], i3); 7319 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, 7320 operands[0], i4); 7321}") 7322 7323(define_insn "*boolcdi3_internal1" 7324 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7325 (match_operator:DI 3 "boolean_operator" 7326 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) 7327 (match_operand:DI 2 "gpc_reg_operand" "r")]))] 7328 "TARGET_POWERPC64" 7329 "%q3 %0,%2,%1") 7330 7331(define_insn "*boolcdi3_internal2" 7332 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7333 (compare:CC (match_operator:DI 4 "boolean_operator" 7334 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 7335 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7336 (const_int 0))) 7337 (clobber (match_scratch:DI 3 "=r,r"))] 7338 "TARGET_64BIT" 7339 "@ 7340 %q4. %3,%2,%1 7341 #" 7342 [(set_attr "type" "compare") 7343 (set_attr "length" "4,8")]) 7344 7345(define_split 7346 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7347 (compare:CC (match_operator:DI 4 "boolean_operator" 7348 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7349 (match_operand:DI 2 "gpc_reg_operand" "")]) 7350 (const_int 0))) 7351 (clobber (match_scratch:DI 3 ""))] 7352 "TARGET_POWERPC64 && reload_completed" 7353 [(set (match_dup 3) (match_dup 4)) 7354 (set (match_dup 0) 7355 (compare:CC (match_dup 3) 7356 (const_int 0)))] 7357 "") 7358 7359(define_insn "*boolcdi3_internal3" 7360 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7361 (compare:CC (match_operator:DI 4 "boolean_operator" 7362 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) 7363 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7364 (const_int 0))) 7365 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7366 (match_dup 4))] 7367 "TARGET_64BIT" 7368 "@ 7369 %q4. %0,%2,%1 7370 #" 7371 [(set_attr "type" "compare") 7372 (set_attr "length" "4,8")]) 7373 7374(define_split 7375 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7376 (compare:CC (match_operator:DI 4 "boolean_operator" 7377 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7378 (match_operand:DI 2 "gpc_reg_operand" "")]) 7379 (const_int 0))) 7380 (set (match_operand:DI 0 "gpc_reg_operand" "") 7381 (match_dup 4))] 7382 "TARGET_POWERPC64 && reload_completed" 7383 [(set (match_dup 0) (match_dup 4)) 7384 (set (match_dup 3) 7385 (compare:CC (match_dup 0) 7386 (const_int 0)))] 7387 "") 7388 7389(define_insn "*boolccdi3_internal1" 7390 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7391 (match_operator:DI 3 "boolean_operator" 7392 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) 7393 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] 7394 "TARGET_POWERPC64" 7395 "%q3 %0,%1,%2") 7396 7397(define_insn "*boolccdi3_internal2" 7398 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7399 (compare:CC (match_operator:DI 4 "boolean_operator" 7400 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 7401 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) 7402 (const_int 0))) 7403 (clobber (match_scratch:DI 3 "=r,r"))] 7404 "TARGET_64BIT" 7405 "@ 7406 %q4. %3,%1,%2 7407 #" 7408 [(set_attr "type" "compare") 7409 (set_attr "length" "4,8")]) 7410 7411(define_split 7412 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7413 (compare:CC (match_operator:DI 4 "boolean_operator" 7414 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7415 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) 7416 (const_int 0))) 7417 (clobber (match_scratch:DI 3 ""))] 7418 "TARGET_POWERPC64 && reload_completed" 7419 [(set (match_dup 3) (match_dup 4)) 7420 (set (match_dup 0) 7421 (compare:CC (match_dup 3) 7422 (const_int 0)))] 7423 "") 7424 7425(define_insn "*boolccdi3_internal3" 7426 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7427 (compare:CC (match_operator:DI 4 "boolean_operator" 7428 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) 7429 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) 7430 (const_int 0))) 7431 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7432 (match_dup 4))] 7433 "TARGET_64BIT" 7434 "@ 7435 %q4. %0,%1,%2 7436 #" 7437 [(set_attr "type" "compare") 7438 (set_attr "length" "4,8")]) 7439 7440(define_split 7441 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7442 (compare:CC (match_operator:DI 4 "boolean_operator" 7443 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7444 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) 7445 (const_int 0))) 7446 (set (match_operand:DI 0 "gpc_reg_operand" "") 7447 (match_dup 4))] 7448 "TARGET_POWERPC64 && reload_completed" 7449 [(set (match_dup 0) (match_dup 4)) 7450 (set (match_dup 3) 7451 (compare:CC (match_dup 0) 7452 (const_int 0)))] 7453 "") 7454 7455;; Now define ways of moving data around. 7456 7457;; Elf specific ways of loading addresses for non-PIC code. 7458;; The output of this could be r0, but we make a very strong 7459;; preference for a base register because it will usually 7460;; be needed there. 7461(define_insn "elf_high" 7462 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") 7463 (high:SI (match_operand 1 "" "")))] 7464 "TARGET_ELF && ! TARGET_64BIT" 7465 "{liu|lis} %0,%1@ha") 7466 7467(define_insn "elf_low" 7468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 7469 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") 7470 (match_operand 2 "" "")))] 7471 "TARGET_ELF && ! TARGET_64BIT" 7472 "@ 7473 {cal|la} %0,%2@l(%1) 7474 {ai|addic} %0,%1,%K2") 7475 7476;; Mach-O PIC trickery. 7477(define_insn "macho_high" 7478 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") 7479 (high:SI (match_operand 1 "" "")))] 7480 "TARGET_MACHO && ! TARGET_64BIT" 7481 "{liu|lis} %0,ha16(%1)") 7482 7483(define_insn "macho_low" 7484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 7485 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") 7486 (match_operand 2 "" "")))] 7487 "TARGET_MACHO && ! TARGET_64BIT" 7488 "@ 7489 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} 7490 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") 7491 7492;; Set up a register with a value from the GOT table 7493 7494(define_expand "movsi_got" 7495 [(set (match_operand:SI 0 "gpc_reg_operand" "") 7496 (unspec:SI [(match_operand:SI 1 "got_operand" "") 7497 (match_dup 2)] UNSPEC_MOVSI_GOT))] 7498 "DEFAULT_ABI == ABI_V4 && flag_pic == 1" 7499 " 7500{ 7501 if (GET_CODE (operands[1]) == CONST) 7502 { 7503 rtx offset = const0_rtx; 7504 HOST_WIDE_INT value; 7505 7506 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); 7507 value = INTVAL (offset); 7508 if (value != 0) 7509 { 7510 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); 7511 emit_insn (gen_movsi_got (tmp, operands[1])); 7512 emit_insn (gen_addsi3 (operands[0], tmp, offset)); 7513 DONE; 7514 } 7515 } 7516 7517 operands[2] = rs6000_got_register (operands[1]); 7518}") 7519 7520(define_insn "*movsi_got_internal" 7521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7522 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") 7523 (match_operand:SI 2 "gpc_reg_operand" "b")] 7524 UNSPEC_MOVSI_GOT))] 7525 "DEFAULT_ABI == ABI_V4 && flag_pic == 1" 7526 "{l|lwz} %0,%a1@got(%2)" 7527 [(set_attr "type" "load")]) 7528 7529;; Used by sched, shorten_branches and final when the GOT pseudo reg 7530;; didn't get allocated to a hard register. 7531(define_split 7532 [(set (match_operand:SI 0 "gpc_reg_operand" "") 7533 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") 7534 (match_operand:SI 2 "memory_operand" "")] 7535 UNSPEC_MOVSI_GOT))] 7536 "DEFAULT_ABI == ABI_V4 7537 && flag_pic == 1 7538 && (reload_in_progress || reload_completed)" 7539 [(set (match_dup 0) (match_dup 2)) 7540 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 7541 UNSPEC_MOVSI_GOT))] 7542 "") 7543 7544;; For SI, we special-case integers that can't be loaded in one insn. We 7545;; do the load 16-bits at a time. We could do this by loading from memory, 7546;; and this is even supposed to be faster, but it is simpler not to get 7547;; integers in the TOC. 7548(define_expand "movsi" 7549 [(set (match_operand:SI 0 "general_operand" "") 7550 (match_operand:SI 1 "any_operand" ""))] 7551 "" 7552 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") 7553 7554(define_insn "movsi_low" 7555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7556 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") 7557 (match_operand 2 "" ""))))] 7558 "TARGET_MACHO && ! TARGET_64BIT" 7559 "{l|lwz} %0,lo16(%2)(%1)" 7560 [(set_attr "type" "load") 7561 (set_attr "length" "4")]) 7562 7563(define_insn "movsi_low_st" 7564 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") 7565 (match_operand 2 "" ""))) 7566 (match_operand:SI 0 "gpc_reg_operand" "r"))] 7567 "TARGET_MACHO && ! TARGET_64BIT" 7568 "{st|stw} %0,lo16(%2)(%1)" 7569 [(set_attr "type" "store") 7570 (set_attr "length" "4")]) 7571 7572(define_insn "movdf_low" 7573 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") 7574 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") 7575 (match_operand 2 "" ""))))] 7576 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" 7577 "* 7578{ 7579 switch (which_alternative) 7580 { 7581 case 0: 7582 return \"lfd %0,lo16(%2)(%1)\"; 7583 case 1: 7584 { 7585 rtx operands2[4]; 7586 operands2[0] = operands[0]; 7587 operands2[1] = operands[1]; 7588 operands2[2] = operands[2]; 7589 if (TARGET_POWERPC64 && TARGET_32BIT) 7590 /* Note, old assemblers didn't support relocation here. */ 7591 return \"ld %0,lo16(%2)(%1)\"; 7592 else 7593 { 7594 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); 7595 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); 7596#if TARGET_MACHO 7597 if (MACHO_DYNAMIC_NO_PIC_P) 7598 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); 7599 else 7600 /* We cannot rely on ha16(low half)==ha16(high half), alas, 7601 although in practice it almost always is. */ 7602 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); 7603#endif 7604 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); 7605 } 7606 } 7607 default: 7608 abort(); 7609 } 7610}" 7611 [(set_attr "type" "load") 7612 (set_attr "length" "4,12")]) 7613 7614(define_insn "movdf_low_st" 7615 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") 7616 (match_operand 2 "" ""))) 7617 (match_operand:DF 0 "gpc_reg_operand" "f"))] 7618 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" 7619 "stfd %0,lo16(%2)(%1)" 7620 [(set_attr "type" "store") 7621 (set_attr "length" "4")]) 7622 7623(define_insn "movsf_low" 7624 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") 7625 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") 7626 (match_operand 2 "" ""))))] 7627 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" 7628 "@ 7629 lfs %0,lo16(%2)(%1) 7630 {l|lwz} %0,lo16(%2)(%1)" 7631 [(set_attr "type" "load") 7632 (set_attr "length" "4")]) 7633 7634(define_insn "movsf_low_st" 7635 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") 7636 (match_operand 2 "" ""))) 7637 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] 7638 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" 7639 "@ 7640 stfs %0,lo16(%2)(%1) 7641 {st|stw} %0,lo16(%2)(%1)" 7642 [(set_attr "type" "store") 7643 (set_attr "length" "4")]) 7644 7645(define_insn "*movsi_internal1" 7646 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") 7647 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] 7648 "gpc_reg_operand (operands[0], SImode) 7649 || gpc_reg_operand (operands[1], SImode)" 7650 "@ 7651 mr %0,%1 7652 {cal|la} %0,%a1 7653 {l%U1%X1|lwz%U1%X1} %0,%1 7654 {st%U0%X0|stw%U0%X0} %1,%0 7655 {lil|li} %0,%1 7656 {liu|lis} %0,%v1 7657 # 7658 {cal|la} %0,%a1 7659 mf%1 %0 7660 mt%0 %1 7661 mt%0 %1 7662 mt%0 %1 7663 {cror 0,0,0|nop}" 7664 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") 7665 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) 7666 7667;; Split a load of a large constant into the appropriate two-insn 7668;; sequence. 7669 7670(define_split 7671 [(set (match_operand:SI 0 "gpc_reg_operand" "") 7672 (match_operand:SI 1 "const_int_operand" ""))] 7673 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 7674 && (INTVAL (operands[1]) & 0xffff) != 0" 7675 [(set (match_dup 0) 7676 (match_dup 2)) 7677 (set (match_dup 0) 7678 (ior:SI (match_dup 0) 7679 (match_dup 3)))] 7680 " 7681{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); 7682 7683 if (tem == operands[0]) 7684 DONE; 7685 else 7686 FAIL; 7687}") 7688 7689(define_insn "*movsi_internal2" 7690 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") 7691 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r") 7692 (const_int 0))) 7693 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] 7694 "TARGET_32BIT" 7695 "@ 7696 {cmpi|cmpwi} %2,%0,0 7697 mr. %0,%1 7698 #" 7699 [(set_attr "type" "cmp,compare,cmp") 7700 (set_attr "length" "4,4,8")]) 7701 7702(define_split 7703 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 7704 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 7705 (const_int 0))) 7706 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] 7707 "TARGET_32BIT && reload_completed" 7708 [(set (match_dup 0) (match_dup 1)) 7709 (set (match_dup 2) 7710 (compare:CC (match_dup 0) 7711 (const_int 0)))] 7712 "") 7713 7714(define_expand "movhi" 7715 [(set (match_operand:HI 0 "general_operand" "") 7716 (match_operand:HI 1 "any_operand" ""))] 7717 "" 7718 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") 7719 7720(define_insn "*movhi_internal" 7721 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 7722 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 7723 "gpc_reg_operand (operands[0], HImode) 7724 || gpc_reg_operand (operands[1], HImode)" 7725 "@ 7726 mr %0,%1 7727 lhz%U1%X1 %0,%1 7728 sth%U0%X0 %1,%0 7729 {lil|li} %0,%w1 7730 mf%1 %0 7731 mt%0 %1 7732 mt%0 %1 7733 {cror 0,0,0|nop}" 7734 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) 7735 7736(define_expand "movqi" 7737 [(set (match_operand:QI 0 "general_operand" "") 7738 (match_operand:QI 1 "any_operand" ""))] 7739 "" 7740 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") 7741 7742(define_insn "*movqi_internal" 7743 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 7744 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 7745 "gpc_reg_operand (operands[0], QImode) 7746 || gpc_reg_operand (operands[1], QImode)" 7747 "@ 7748 mr %0,%1 7749 lbz%U1%X1 %0,%1 7750 stb%U0%X0 %1,%0 7751 {lil|li} %0,%1 7752 mf%1 %0 7753 mt%0 %1 7754 mt%0 %1 7755 {cror 0,0,0|nop}" 7756 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) 7757 7758;; Here is how to move condition codes around. When we store CC data in 7759;; an integer register or memory, we store just the high-order 4 bits. 7760;; This lets us not shift in the most common case of CR0. 7761(define_expand "movcc" 7762 [(set (match_operand:CC 0 "nonimmediate_operand" "") 7763 (match_operand:CC 1 "nonimmediate_operand" ""))] 7764 "" 7765 "") 7766 7767(define_insn "*movcc_internal1" 7768 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") 7769 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] 7770 "register_operand (operands[0], CCmode) 7771 || register_operand (operands[1], CCmode)" 7772 "@ 7773 mcrf %0,%1 7774 mtcrf 128,%1 7775 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff 7776 mfcr %0%Q1 7777 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 7778 mr %0,%1 7779 mf%1 %0 7780 mt%0 %1 7781 mt%0 %1 7782 {l%U1%X1|lwz%U1%X1} %0,%1 7783 {st%U0%U1|stw%U0%U1} %1,%0" 7784 [(set (attr "type") 7785 (cond [(eq_attr "alternative" "0") 7786 (const_string "cr_logical") 7787 (eq_attr "alternative" "1,2") 7788 (const_string "mtcr") 7789 (eq_attr "alternative" "5,7") 7790 (const_string "integer") 7791 (eq_attr "alternative" "6") 7792 (const_string "mfjmpr") 7793 (eq_attr "alternative" "8") 7794 (const_string "mtjmpr") 7795 (eq_attr "alternative" "9") 7796 (const_string "load") 7797 (eq_attr "alternative" "10") 7798 (const_string "store") 7799 (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) 7800 (const_string "mfcrf") 7801 ] 7802 (const_string "mfcr"))) 7803 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) 7804 7805;; For floating-point, we normally deal with the floating-point registers 7806;; unless -msoft-float is used. The sole exception is that parameter passing 7807;; can produce floating-point values in fixed-point registers. Unless the 7808;; value is a simple constant or already in memory, we deal with this by 7809;; allocating memory and copying the value explicitly via that memory location. 7810(define_expand "movsf" 7811 [(set (match_operand:SF 0 "nonimmediate_operand" "") 7812 (match_operand:SF 1 "any_operand" ""))] 7813 "" 7814 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") 7815 7816(define_split 7817 [(set (match_operand:SF 0 "gpc_reg_operand" "") 7818 (match_operand:SF 1 "const_double_operand" ""))] 7819 "reload_completed 7820 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 7821 || (GET_CODE (operands[0]) == SUBREG 7822 && GET_CODE (SUBREG_REG (operands[0])) == REG 7823 && REGNO (SUBREG_REG (operands[0])) <= 31))" 7824 [(set (match_dup 2) (match_dup 3))] 7825 " 7826{ 7827 long l; 7828 REAL_VALUE_TYPE rv; 7829 7830 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 7831 REAL_VALUE_TO_TARGET_SINGLE (rv, l); 7832 7833 if (! TARGET_POWERPC64) 7834 operands[2] = operand_subword (operands[0], 0, 0, SFmode); 7835 else 7836 operands[2] = gen_lowpart (SImode, operands[0]); 7837 7838 operands[3] = gen_int_mode (l, SImode); 7839}") 7840 7841(define_insn "*movsf_hardfloat" 7842 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r") 7843 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] 7844 "(gpc_reg_operand (operands[0], SFmode) 7845 || gpc_reg_operand (operands[1], SFmode)) 7846 && (TARGET_HARD_FLOAT && TARGET_FPRS)" 7847 "@ 7848 mr %0,%1 7849 {l%U1%X1|lwz%U1%X1} %0,%1 7850 {st%U0%X0|stw%U0%X0} %1,%0 7851 fmr %0,%1 7852 lfs%U1%X1 %0,%1 7853 stfs%U0%X0 %1,%0 7854 mt%0 %1 7855 mt%0 %1 7856 mf%1 %0 7857 {cror 0,0,0|nop} 7858 # 7859 #" 7860 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") 7861 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) 7862 7863(define_insn "*movsf_softfloat" 7864 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") 7865 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] 7866 "(gpc_reg_operand (operands[0], SFmode) 7867 || gpc_reg_operand (operands[1], SFmode)) 7868 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" 7869 "@ 7870 mr %0,%1 7871 mt%0 %1 7872 mt%0 %1 7873 mf%1 %0 7874 {l%U1%X1|lwz%U1%X1} %0,%1 7875 {st%U0%X0|stw%U0%X0} %1,%0 7876 {lil|li} %0,%1 7877 {liu|lis} %0,%v1 7878 {cal|la} %0,%a1 7879 # 7880 # 7881 {cror 0,0,0|nop}" 7882 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") 7883 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) 7884 7885 7886(define_expand "movdf" 7887 [(set (match_operand:DF 0 "nonimmediate_operand" "") 7888 (match_operand:DF 1 "any_operand" ""))] 7889 "" 7890 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") 7891 7892(define_split 7893 [(set (match_operand:DF 0 "gpc_reg_operand" "") 7894 (match_operand:DF 1 "const_int_operand" ""))] 7895 "! TARGET_POWERPC64 && reload_completed 7896 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 7897 || (GET_CODE (operands[0]) == SUBREG 7898 && GET_CODE (SUBREG_REG (operands[0])) == REG 7899 && REGNO (SUBREG_REG (operands[0])) <= 31))" 7900 [(set (match_dup 2) (match_dup 4)) 7901 (set (match_dup 3) (match_dup 1))] 7902 " 7903{ 7904 int endian = (WORDS_BIG_ENDIAN == 0); 7905 HOST_WIDE_INT value = INTVAL (operands[1]); 7906 7907 operands[2] = operand_subword (operands[0], endian, 0, DFmode); 7908 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); 7909#if HOST_BITS_PER_WIDE_INT == 32 7910 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; 7911#else 7912 operands[4] = GEN_INT (value >> 32); 7913 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); 7914#endif 7915}") 7916 7917(define_split 7918 [(set (match_operand:DF 0 "gpc_reg_operand" "") 7919 (match_operand:DF 1 "const_double_operand" ""))] 7920 "! TARGET_POWERPC64 && reload_completed 7921 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 7922 || (GET_CODE (operands[0]) == SUBREG 7923 && GET_CODE (SUBREG_REG (operands[0])) == REG 7924 && REGNO (SUBREG_REG (operands[0])) <= 31))" 7925 [(set (match_dup 2) (match_dup 4)) 7926 (set (match_dup 3) (match_dup 5))] 7927 " 7928{ 7929 int endian = (WORDS_BIG_ENDIAN == 0); 7930 long l[2]; 7931 REAL_VALUE_TYPE rv; 7932 7933 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 7934 REAL_VALUE_TO_TARGET_DOUBLE (rv, l); 7935 7936 operands[2] = operand_subword (operands[0], endian, 0, DFmode); 7937 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); 7938 operands[4] = gen_int_mode (l[endian], SImode); 7939 operands[5] = gen_int_mode (l[1 - endian], SImode); 7940}") 7941 7942(define_split 7943 [(set (match_operand:DF 0 "gpc_reg_operand" "") 7944 (match_operand:DF 1 "easy_fp_constant" ""))] 7945 "TARGET_POWERPC64 && reload_completed 7946 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 7947 || (GET_CODE (operands[0]) == SUBREG 7948 && GET_CODE (SUBREG_REG (operands[0])) == REG 7949 && REGNO (SUBREG_REG (operands[0])) <= 31))" 7950 [(set (match_dup 2) (match_dup 3))] 7951 " 7952{ 7953 int endian = (WORDS_BIG_ENDIAN == 0); 7954 long l[2]; 7955 REAL_VALUE_TYPE rv; 7956#if HOST_BITS_PER_WIDE_INT >= 64 7957 HOST_WIDE_INT val; 7958#endif 7959 7960 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 7961 REAL_VALUE_TO_TARGET_DOUBLE (rv, l); 7962 7963 operands[2] = gen_lowpart (DImode, operands[0]); 7964 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ 7965#if HOST_BITS_PER_WIDE_INT >= 64 7966 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 7967 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); 7968 7969 operands[3] = gen_int_mode (val, DImode); 7970#else 7971 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); 7972#endif 7973}") 7974 7975;; Don't have reload use general registers to load a constant. First, 7976;; it might not work if the output operand is the equivalent of 7977;; a non-offsettable memref, but also it is less efficient than loading 7978;; the constant into an FP register, since it will probably be used there. 7979;; The "??" is a kludge until we can figure out a more reasonable way 7980;; of handling these non-offsettable values. 7981(define_insn "*movdf_hardfloat32" 7982 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") 7983 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] 7984 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS 7985 && (gpc_reg_operand (operands[0], DFmode) 7986 || gpc_reg_operand (operands[1], DFmode))" 7987 "* 7988{ 7989 switch (which_alternative) 7990 { 7991 default: 7992 abort (); 7993 case 0: 7994 /* We normally copy the low-numbered register first. However, if 7995 the first register operand 0 is the same as the second register 7996 of operand 1, we must copy in the opposite order. */ 7997 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 7998 return \"mr %L0,%L1\;mr %0,%1\"; 7999 else 8000 return \"mr %0,%1\;mr %L0,%L1\"; 8001 case 1: 8002 if (offsettable_memref_p (operands[1]) 8003 || (GET_CODE (operands[1]) == MEM 8004 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM 8005 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC 8006 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) 8007 { 8008 /* If the low-address word is used in the address, we must load 8009 it last. Otherwise, load it first. Note that we cannot have 8010 auto-increment in that case since the address register is 8011 known to be dead. */ 8012 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8013 operands[1], 0)) 8014 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 8015 else 8016 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 8017 } 8018 else 8019 { 8020 rtx addreg; 8021 8022 addreg = find_addr_reg (XEXP (operands[1], 0)); 8023 if (refers_to_regno_p (REGNO (operands[0]), 8024 REGNO (operands[0]) + 1, 8025 operands[1], 0)) 8026 { 8027 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); 8028 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); 8029 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 8030 return \"{lx|lwzx} %0,%1\"; 8031 } 8032 else 8033 { 8034 output_asm_insn (\"{lx|lwzx} %0,%1\", operands); 8035 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); 8036 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); 8037 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 8038 return \"\"; 8039 } 8040 } 8041 case 2: 8042 if (offsettable_memref_p (operands[0]) 8043 || (GET_CODE (operands[0]) == MEM 8044 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM 8045 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC 8046 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) 8047 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 8048 else 8049 { 8050 rtx addreg; 8051 8052 addreg = find_addr_reg (XEXP (operands[0], 0)); 8053 output_asm_insn (\"{stx|stwx} %1,%0\", operands); 8054 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); 8055 output_asm_insn (\"{stx|stwx} %L1,%0\", operands); 8056 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 8057 return \"\"; 8058 } 8059 case 3: 8060 return \"fmr %0,%1\"; 8061 case 4: 8062 return \"lfd%U1%X1 %0,%1\"; 8063 case 5: 8064 return \"stfd%U0%X0 %1,%0\"; 8065 case 6: 8066 case 7: 8067 case 8: 8068 return \"#\"; 8069 } 8070}" 8071 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*") 8072 (set_attr "length" "8,16,16,4,4,4,8,12,16")]) 8073 8074(define_insn "*movdf_softfloat32" 8075 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") 8076 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] 8077 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) 8078 && (gpc_reg_operand (operands[0], DFmode) 8079 || gpc_reg_operand (operands[1], DFmode))" 8080 "* 8081{ 8082 switch (which_alternative) 8083 { 8084 default: 8085 abort (); 8086 case 0: 8087 /* We normally copy the low-numbered register first. However, if 8088 the first register operand 0 is the same as the second register of 8089 operand 1, we must copy in the opposite order. */ 8090 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8091 return \"mr %L0,%L1\;mr %0,%1\"; 8092 else 8093 return \"mr %0,%1\;mr %L0,%L1\"; 8094 case 1: 8095 /* If the low-address word is used in the address, we must load 8096 it last. Otherwise, load it first. Note that we cannot have 8097 auto-increment in that case since the address register is 8098 known to be dead. */ 8099 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8100 operands[1], 0)) 8101 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 8102 else 8103 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 8104 case 2: 8105 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 8106 case 3: 8107 case 4: 8108 case 5: 8109 return \"#\"; 8110 } 8111}" 8112 [(set_attr "type" "*,load,store,*,*,*") 8113 (set_attr "length" "8,8,8,8,12,16")]) 8114 8115; ld/std require word-aligned displacements -> 'Y' constraint. 8116; List Y->r and r->Y before r->r for reload. 8117(define_insn "*movdf_hardfloat64" 8118 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r") 8119 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] 8120 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS 8121 && (gpc_reg_operand (operands[0], DFmode) 8122 || gpc_reg_operand (operands[1], DFmode))" 8123 "@ 8124 std%U0%X0 %1,%0 8125 ld%U1%X1 %0,%1 8126 mr %0,%1 8127 fmr %0,%1 8128 lfd%U1%X1 %0,%1 8129 stfd%U0%X0 %1,%0 8130 mt%0 %1 8131 mf%1 %0 8132 {cror 0,0,0|nop} 8133 # 8134 # 8135 #" 8136 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") 8137 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) 8138 8139(define_insn "*movdf_softfloat64" 8140 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") 8141 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] 8142 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) 8143 && (gpc_reg_operand (operands[0], DFmode) 8144 || gpc_reg_operand (operands[1], DFmode))" 8145 "@ 8146 ld%U1%X1 %0,%1 8147 std%U0%X0 %1,%0 8148 mr %0,%1 8149 mt%0 %1 8150 mf%1 %0 8151 # 8152 # 8153 # 8154 {cror 0,0,0|nop}" 8155 [(set_attr "type" "load,store,*,*,*,*,*,*,*") 8156 (set_attr "length" "4,4,4,4,4,8,12,16,4")]) 8157 8158(define_expand "movtf" 8159 [(set (match_operand:TF 0 "general_operand" "") 8160 (match_operand:TF 1 "any_operand" ""))] 8161 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8162 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8163 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") 8164 8165; It's important to list the o->f and f->o moves before f->f because 8166; otherwise reload, given m->f, will try to pick f->f and reload it, 8167; which doesn't make progress. 8168(define_insn_and_split "*movtf_internal" 8169 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r") 8170 (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))] 8171 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8172 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 8173 && (gpc_reg_operand (operands[0], TFmode) 8174 || gpc_reg_operand (operands[1], TFmode))" 8175 "#" 8176 "&& reload_completed" 8177 [(pc)] 8178{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } 8179 [(set_attr "length" "8,8,8,20,20")]) 8180 8181(define_expand "extenddftf2" 8182 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") 8183 (float_extend:TF (match_operand:DF 1 "input_operand" ""))) 8184 (use (match_dup 2))])] 8185 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8186 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8187{ 8188 operands[2] = CONST0_RTX (DFmode); 8189}) 8190 8191(define_insn_and_split "*extenddftf2_internal" 8192 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") 8193 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) 8194 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))] 8195 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8196 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8197 "#" 8198 "&& reload_completed" 8199 [(pc)] 8200{ 8201 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; 8202 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); 8203 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), 8204 operands[1]); 8205 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), 8206 operands[2]); 8207 DONE; 8208}) 8209 8210(define_expand "extendsftf2" 8211 [(set (match_operand:TF 0 "nonimmediate_operand" "") 8212 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] 8213 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8214 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8215{ 8216 rtx tmp = gen_reg_rtx (DFmode); 8217 emit_insn (gen_extendsfdf2 (tmp, operands[1])); 8218 emit_insn (gen_extenddftf2 (operands[0], tmp)); 8219 DONE; 8220}) 8221 8222(define_expand "trunctfdf2" 8223 [(set (match_operand:DF 0 "gpc_reg_operand" "") 8224 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))] 8225 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8226 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8227 "") 8228 8229(define_insn_and_split "trunctfdf2_internal1" 8230 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") 8231 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))] 8232 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT 8233 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8234 "@ 8235 # 8236 fmr %0,%1" 8237 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" 8238 [(const_int 0)] 8239{ 8240 emit_note (NOTE_INSN_DELETED); 8241 DONE; 8242} 8243 [(set_attr "type" "fp")]) 8244 8245(define_insn "trunctfdf2_internal2" 8246 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 8247 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8248 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT 8249 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8250 "fadd %0,%1,%L1" 8251 [(set_attr "type" "fp")]) 8252 8253(define_insn_and_split "trunctfsf2" 8254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 8255 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) 8256 (clobber (match_scratch:DF 2 "=f"))] 8257 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8258 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8259 "#" 8260 "&& reload_completed" 8261 [(set (match_dup 2) 8262 (float_truncate:DF (match_dup 1))) 8263 (set (match_dup 0) 8264 (float_truncate:SF (match_dup 2)))] 8265 "") 8266 8267(define_expand "floatsitf2" 8268 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8269 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))] 8270 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8271 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8272{ 8273 rtx tmp = gen_reg_rtx (DFmode); 8274 expand_float (tmp, operands[1], false); 8275 emit_insn (gen_extenddftf2 (operands[0], tmp)); 8276 DONE; 8277}) 8278 8279; fadd, but rounding towards zero. 8280; This is probably not the optimal code sequence. 8281(define_insn "fix_trunc_helper" 8282 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 8283 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] 8284 UNSPEC_FIX_TRUNC_TF)) 8285 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] 8286 "TARGET_HARD_FLOAT && TARGET_FPRS" 8287 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" 8288 [(set_attr "type" "fp") 8289 (set_attr "length" "20")]) 8290 8291(define_expand "fix_trunctfsi2" 8292 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 8293 (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) 8294 (clobber (match_dup 2)) 8295 (clobber (match_dup 3)) 8296 (clobber (match_dup 4)) 8297 (clobber (match_dup 5))])] 8298 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8299 && (TARGET_POWER2 || TARGET_POWERPC) 8300 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8301{ 8302 operands[2] = gen_reg_rtx (DFmode); 8303 operands[3] = gen_reg_rtx (DFmode); 8304 operands[4] = gen_reg_rtx (DImode); 8305 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 8306}) 8307 8308(define_insn_and_split "*fix_trunctfsi2_internal" 8309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 8310 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) 8311 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) 8312 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) 8313 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) 8314 (clobber (match_operand:DI 5 "memory_operand" "=o"))] 8315 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8316 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8317 "#" 8318 "&& reload_completed" 8319 [(pc)] 8320{ 8321 rtx lowword; 8322 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); 8323 8324 if (GET_CODE (operands[5]) != MEM) 8325 abort(); 8326 lowword = XEXP (operands[5], 0); 8327 if (WORDS_BIG_ENDIAN) 8328 lowword = plus_constant (lowword, 4); 8329 8330 emit_insn (gen_fctiwz (operands[4], operands[2])); 8331 emit_move_insn (operands[5], operands[4]); 8332 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); 8333 DONE; 8334}) 8335 8336(define_insn "negtf2" 8337 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8338 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8339 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8340 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8341 "* 8342{ 8343 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8344 return \"fneg %L0,%L1\;fneg %0,%1\"; 8345 else 8346 return \"fneg %0,%1\;fneg %L0,%L1\"; 8347}" 8348 [(set_attr "type" "fp") 8349 (set_attr "length" "8")]) 8350 8351(define_expand "abstf2" 8352 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8353 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8354 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8355 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8356 " 8357{ 8358 rtx label = gen_label_rtx (); 8359 emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); 8360 emit_label (label); 8361 DONE; 8362}") 8363 8364(define_expand "abstf2_internal" 8365 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8366 (match_operand:TF 1 "gpc_reg_operand" "f")) 8367 (set (match_dup 3) (match_dup 5)) 8368 (set (match_dup 5) (abs:DF (match_dup 5))) 8369 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) 8370 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) 8371 (label_ref (match_operand 2 "" "")) 8372 (pc))) 8373 (set (match_dup 6) (neg:DF (match_dup 6)))] 8374 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 8375 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 8376 " 8377{ 8378 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); 8379 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; 8380 operands[3] = gen_reg_rtx (DFmode); 8381 operands[4] = gen_reg_rtx (CCFPmode); 8382 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); 8383 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); 8384}") 8385 8386;; Next come the multi-word integer load and store and the load and store 8387;; multiple insns. 8388(define_expand "movdi" 8389 [(set (match_operand:DI 0 "general_operand" "") 8390 (match_operand:DI 1 "any_operand" ""))] 8391 "" 8392 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") 8393 8394(define_insn "*movdi_internal32" 8395 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") 8396 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] 8397 "! TARGET_POWERPC64 8398 && (gpc_reg_operand (operands[0], DImode) 8399 || gpc_reg_operand (operands[1], DImode))" 8400 "* 8401{ 8402 switch (which_alternative) 8403 { 8404 default: 8405 abort (); 8406 case 0: 8407 case 1: 8408 case 2: 8409 return \"#\"; 8410 case 3: 8411 return \"fmr %0,%1\"; 8412 case 4: 8413 return \"lfd%U1%X1 %0,%1\"; 8414 case 5: 8415 return \"stfd%U0%X0 %1,%0\"; 8416 case 6: 8417 case 7: 8418 case 8: 8419 case 9: 8420 case 10: 8421 return \"#\"; 8422 } 8423}" 8424 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")]) 8425 8426(define_split 8427 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8428 (match_operand:DI 1 "const_int_operand" ""))] 8429 "! TARGET_POWERPC64 && reload_completed" 8430 [(set (match_dup 2) (match_dup 4)) 8431 (set (match_dup 3) (match_dup 1))] 8432 " 8433{ 8434 HOST_WIDE_INT value = INTVAL (operands[1]); 8435 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, 8436 DImode); 8437 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, 8438 DImode); 8439#if HOST_BITS_PER_WIDE_INT == 32 8440 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; 8441#else 8442 operands[4] = GEN_INT (value >> 32); 8443 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); 8444#endif 8445}") 8446 8447(define_split 8448 [(set (match_operand:DI 0 "nonimmediate_operand" "") 8449 (match_operand:DI 1 "input_operand" ""))] 8450 "reload_completed && !TARGET_POWERPC64 8451 && gpr_or_gpr_p (operands[0], operands[1])" 8452 [(pc)] 8453{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 8454 8455(define_split 8456 [(set (match_operand:TI 0 "gpc_reg_operand" "") 8457 (match_operand:TI 1 "const_double_operand" ""))] 8458 "TARGET_POWERPC64" 8459 [(set (match_dup 2) (match_dup 4)) 8460 (set (match_dup 3) (match_dup 5))] 8461 " 8462{ 8463 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, 8464 TImode); 8465 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, 8466 TImode); 8467 if (GET_CODE (operands[1]) == CONST_DOUBLE) 8468 { 8469 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); 8470 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); 8471 } 8472 else if (GET_CODE (operands[1]) == CONST_INT) 8473 { 8474 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); 8475 operands[5] = operands[1]; 8476 } 8477 else 8478 FAIL; 8479}") 8480 8481(define_insn "*movdi_internal64" 8482 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,r,??f,f,m,r,*h,*h") 8483 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,R,f,m,f,*h,r,0"))] 8484 "TARGET_POWERPC64 8485 && (gpc_reg_operand (operands[0], DImode) 8486 || gpc_reg_operand (operands[1], DImode))" 8487 "@ 8488 std%U0%X0 %1,%0 8489 ld%U1%X1 %0,%1 8490 mr %0,%1 8491 li %0,%1 8492 lis %0,%v1 8493 # 8494 {cal|la} %0,%a1 8495 fmr %0,%1 8496 lfd%U1%X1 %0,%1 8497 stfd%U0%X0 %1,%0 8498 mf%1 %0 8499 mt%0 %1 8500 {cror 0,0,0|nop}" 8501 [(set_attr "type" "store,load,*,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") 8502 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) 8503 8504;; immediate value valid for a single instruction hiding in a const_double 8505(define_insn "" 8506 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 8507 (match_operand:DI 1 "const_double_operand" "F"))] 8508 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 8509 && GET_CODE (operands[1]) == CONST_DOUBLE 8510 && num_insns_constant (operands[1], DImode) == 1" 8511 "* 8512{ 8513 return ((unsigned HOST_WIDE_INT) 8514 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) 8515 ? \"li %0,%1\" : \"lis %0,%v1\"; 8516}") 8517 8518;; Generate all one-bits and clear left or right. 8519;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. 8520(define_split 8521 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8522 (match_operand:DI 1 "mask64_operand" ""))] 8523 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 8524 [(set (match_dup 0) (const_int -1)) 8525 (set (match_dup 0) 8526 (and:DI (rotate:DI (match_dup 0) 8527 (const_int 0)) 8528 (match_dup 1)))] 8529 "") 8530 8531;; Split a load of a large constant into the appropriate five-instruction 8532;; sequence. Handle anything in a constant number of insns. 8533;; When non-easy constants can go in the TOC, this should use 8534;; easy_fp_constant predicate. 8535(define_split 8536 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8537 (match_operand:DI 1 "const_int_operand" ""))] 8538 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 8539 [(set (match_dup 0) (match_dup 2)) 8540 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 8541 " 8542{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); 8543 8544 if (tem == operands[0]) 8545 DONE; 8546 else 8547 FAIL; 8548}") 8549 8550(define_split 8551 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8552 (match_operand:DI 1 "const_double_operand" ""))] 8553 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 8554 [(set (match_dup 0) (match_dup 2)) 8555 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 8556 " 8557{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); 8558 8559 if (tem == operands[0]) 8560 DONE; 8561 else 8562 FAIL; 8563}") 8564 8565(define_insn "*movdi_internal2" 8566 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") 8567 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r") 8568 (const_int 0))) 8569 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] 8570 "TARGET_64BIT" 8571 "@ 8572 cmpdi %2,%0,0 8573 mr. %0,%1 8574 #" 8575 [(set_attr "type" "cmp,compare,cmp") 8576 (set_attr "length" "4,4,8")]) 8577 8578(define_split 8579 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 8580 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") 8581 (const_int 0))) 8582 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] 8583 "TARGET_POWERPC64 && reload_completed" 8584 [(set (match_dup 0) (match_dup 1)) 8585 (set (match_dup 2) 8586 (compare:CC (match_dup 0) 8587 (const_int 0)))] 8588 "") 8589 8590;; TImode is similar, except that we usually want to compute the address into 8591;; a register and use lsi/stsi (the exception is during reload). MQ is also 8592;; clobbered in stsi for POWER, so we need a SCRATCH for it. 8593(define_expand "movti" 8594 [(parallel [(set (match_operand:TI 0 "general_operand" "") 8595 (match_operand:TI 1 "general_operand" "")) 8596 (clobber (scratch:SI))])] 8597 "" 8598 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") 8599 8600;; We say that MQ is clobbered in the last alternative because the first 8601;; alternative would never get used otherwise since it would need a reload 8602;; while the 2nd alternative would not. We put memory cases first so they 8603;; are preferred. Otherwise, we'd try to reload the output instead of 8604;; giving the SCRATCH mq. 8605 8606(define_insn "*movti_power" 8607 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") 8608 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) 8609 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] 8610 "TARGET_POWER && ! TARGET_POWERPC64 8611 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" 8612 "* 8613{ 8614 switch (which_alternative) 8615 { 8616 default: 8617 abort (); 8618 8619 case 0: 8620 if (TARGET_STRING) 8621 return \"{stsi|stswi} %1,%P0,16\"; 8622 case 1: 8623 case 2: 8624 return \"#\"; 8625 case 3: 8626 /* If the address is not used in the output, we can use lsi. Otherwise, 8627 fall through to generating four loads. */ 8628 if (TARGET_STRING 8629 && ! reg_overlap_mentioned_p (operands[0], operands[1])) 8630 return \"{lsi|lswi} %0,%P1,16\"; 8631 /* ... fall through ... */ 8632 case 4: 8633 return \"#\"; 8634 } 8635}" 8636 [(set_attr "type" "store,store,*,load,load")]) 8637 8638(define_insn "*movti_string" 8639 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") 8640 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))] 8641 "! TARGET_POWER && ! TARGET_POWERPC64 8642 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" 8643 "* 8644{ 8645 switch (which_alternative) 8646 { 8647 default: 8648 abort (); 8649 case 0: 8650 if (TARGET_STRING) 8651 return \"{stsi|stswi} %1,%P0,16\"; 8652 case 1: 8653 case 2: 8654 return \"#\"; 8655 case 3: 8656 /* If the address is not used in the output, we can use lsi. Otherwise, 8657 fall through to generating four loads. */ 8658 if (TARGET_STRING 8659 && ! reg_overlap_mentioned_p (operands[0], operands[1])) 8660 return \"{lsi|lswi} %0,%P1,16\"; 8661 /* ... fall through ... */ 8662 case 4: 8663 return \"#\"; 8664 } 8665}" 8666 [(set_attr "type" "store,store,*,load,load")]) 8667 8668(define_insn "*movti_ppc64" 8669 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r") 8670 (match_operand:TI 1 "input_operand" "r,r,o"))] 8671 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) 8672 || gpc_reg_operand (operands[1], TImode))" 8673 "@ 8674 # 8675 # 8676 #" 8677 [(set_attr "type" "*,load,store")]) 8678 8679(define_split 8680 [(set (match_operand:TI 0 "nonimmediate_operand" "") 8681 (match_operand:TI 1 "input_operand" ""))] 8682 "reload_completed 8683 && gpr_or_gpr_p (operands[0], operands[1])" 8684 [(pc)] 8685{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 8686 8687(define_expand "load_multiple" 8688 [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 8689 (match_operand:SI 1 "" "")) 8690 (use (match_operand:SI 2 "" ""))])] 8691 "TARGET_STRING && !TARGET_POWERPC64" 8692 " 8693{ 8694 int regno; 8695 int count; 8696 rtx op1; 8697 int i; 8698 8699 /* Support only loading a constant number of fixed-point registers from 8700 memory and only bother with this if more than two; the machine 8701 doesn't support more than eight. */ 8702 if (GET_CODE (operands[2]) != CONST_INT 8703 || INTVAL (operands[2]) <= 2 8704 || INTVAL (operands[2]) > 8 8705 || GET_CODE (operands[1]) != MEM 8706 || GET_CODE (operands[0]) != REG 8707 || REGNO (operands[0]) >= 32) 8708 FAIL; 8709 8710 count = INTVAL (operands[2]); 8711 regno = REGNO (operands[0]); 8712 8713 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 8714 op1 = replace_equiv_address (operands[1], 8715 force_reg (SImode, XEXP (operands[1], 0))); 8716 8717 for (i = 0; i < count; i++) 8718 XVECEXP (operands[3], 0, i) 8719 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), 8720 adjust_address_nv (op1, SImode, i * 4)); 8721}") 8722 8723(define_insn "*ldmsi8" 8724 [(match_parallel 0 "load_multiple_operation" 8725 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8726 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8727 (set (match_operand:SI 3 "gpc_reg_operand" "") 8728 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8729 (set (match_operand:SI 4 "gpc_reg_operand" "") 8730 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8731 (set (match_operand:SI 5 "gpc_reg_operand" "") 8732 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 8733 (set (match_operand:SI 6 "gpc_reg_operand" "") 8734 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) 8735 (set (match_operand:SI 7 "gpc_reg_operand" "") 8736 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) 8737 (set (match_operand:SI 8 "gpc_reg_operand" "") 8738 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) 8739 (set (match_operand:SI 9 "gpc_reg_operand" "") 8740 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] 8741 "TARGET_STRING && XVECLEN (operands[0], 0) == 8" 8742 "* 8743{ return rs6000_output_load_multiple (operands); }" 8744 [(set_attr "type" "load") 8745 (set_attr "length" "32")]) 8746 8747(define_insn "*ldmsi7" 8748 [(match_parallel 0 "load_multiple_operation" 8749 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8750 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8751 (set (match_operand:SI 3 "gpc_reg_operand" "") 8752 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8753 (set (match_operand:SI 4 "gpc_reg_operand" "") 8754 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8755 (set (match_operand:SI 5 "gpc_reg_operand" "") 8756 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 8757 (set (match_operand:SI 6 "gpc_reg_operand" "") 8758 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) 8759 (set (match_operand:SI 7 "gpc_reg_operand" "") 8760 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) 8761 (set (match_operand:SI 8 "gpc_reg_operand" "") 8762 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] 8763 "TARGET_STRING && XVECLEN (operands[0], 0) == 7" 8764 "* 8765{ return rs6000_output_load_multiple (operands); }" 8766 [(set_attr "type" "load") 8767 (set_attr "length" "32")]) 8768 8769(define_insn "*ldmsi6" 8770 [(match_parallel 0 "load_multiple_operation" 8771 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8772 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8773 (set (match_operand:SI 3 "gpc_reg_operand" "") 8774 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8775 (set (match_operand:SI 4 "gpc_reg_operand" "") 8776 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8777 (set (match_operand:SI 5 "gpc_reg_operand" "") 8778 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 8779 (set (match_operand:SI 6 "gpc_reg_operand" "") 8780 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) 8781 (set (match_operand:SI 7 "gpc_reg_operand" "") 8782 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] 8783 "TARGET_STRING && XVECLEN (operands[0], 0) == 6" 8784 "* 8785{ return rs6000_output_load_multiple (operands); }" 8786 [(set_attr "type" "load") 8787 (set_attr "length" "32")]) 8788 8789(define_insn "*ldmsi5" 8790 [(match_parallel 0 "load_multiple_operation" 8791 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8792 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8793 (set (match_operand:SI 3 "gpc_reg_operand" "") 8794 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8795 (set (match_operand:SI 4 "gpc_reg_operand" "") 8796 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8797 (set (match_operand:SI 5 "gpc_reg_operand" "") 8798 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 8799 (set (match_operand:SI 6 "gpc_reg_operand" "") 8800 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] 8801 "TARGET_STRING && XVECLEN (operands[0], 0) == 5" 8802 "* 8803{ return rs6000_output_load_multiple (operands); }" 8804 [(set_attr "type" "load") 8805 (set_attr "length" "32")]) 8806 8807(define_insn "*ldmsi4" 8808 [(match_parallel 0 "load_multiple_operation" 8809 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8810 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8811 (set (match_operand:SI 3 "gpc_reg_operand" "") 8812 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8813 (set (match_operand:SI 4 "gpc_reg_operand" "") 8814 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 8815 (set (match_operand:SI 5 "gpc_reg_operand" "") 8816 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] 8817 "TARGET_STRING && XVECLEN (operands[0], 0) == 4" 8818 "* 8819{ return rs6000_output_load_multiple (operands); }" 8820 [(set_attr "type" "load") 8821 (set_attr "length" "32")]) 8822 8823(define_insn "*ldmsi3" 8824 [(match_parallel 0 "load_multiple_operation" 8825 [(set (match_operand:SI 2 "gpc_reg_operand" "") 8826 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 8827 (set (match_operand:SI 3 "gpc_reg_operand" "") 8828 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 8829 (set (match_operand:SI 4 "gpc_reg_operand" "") 8830 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] 8831 "TARGET_STRING && XVECLEN (operands[0], 0) == 3" 8832 "* 8833{ return rs6000_output_load_multiple (operands); }" 8834 [(set_attr "type" "load") 8835 (set_attr "length" "32")]) 8836 8837(define_expand "store_multiple" 8838 [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 8839 (match_operand:SI 1 "" "")) 8840 (clobber (scratch:SI)) 8841 (use (match_operand:SI 2 "" ""))])] 8842 "TARGET_STRING && !TARGET_POWERPC64" 8843 " 8844{ 8845 int regno; 8846 int count; 8847 rtx to; 8848 rtx op0; 8849 int i; 8850 8851 /* Support only storing a constant number of fixed-point registers to 8852 memory and only bother with this if more than two; the machine 8853 doesn't support more than eight. */ 8854 if (GET_CODE (operands[2]) != CONST_INT 8855 || INTVAL (operands[2]) <= 2 8856 || INTVAL (operands[2]) > 8 8857 || GET_CODE (operands[0]) != MEM 8858 || GET_CODE (operands[1]) != REG 8859 || REGNO (operands[1]) >= 32) 8860 FAIL; 8861 8862 count = INTVAL (operands[2]); 8863 regno = REGNO (operands[1]); 8864 8865 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); 8866 to = force_reg (SImode, XEXP (operands[0], 0)); 8867 op0 = replace_equiv_address (operands[0], to); 8868 8869 XVECEXP (operands[3], 0, 0) 8870 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); 8871 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, 8872 gen_rtx_SCRATCH (SImode)); 8873 8874 for (i = 1; i < count; i++) 8875 XVECEXP (operands[3], 0, i + 1) 8876 = gen_rtx_SET (VOIDmode, 8877 adjust_address_nv (op0, SImode, i * 4), 8878 gen_rtx_REG (SImode, regno + i)); 8879}") 8880 8881(define_insn "*store_multiple_power" 8882 [(match_parallel 0 "store_multiple_operation" 8883 [(set (match_operand:SI 1 "indirect_operand" "=Q") 8884 (match_operand:SI 2 "gpc_reg_operand" "r")) 8885 (clobber (match_scratch:SI 3 "=q"))])] 8886 "TARGET_STRING && TARGET_POWER" 8887 "{stsi|stswi} %2,%P1,%O0" 8888 [(set_attr "type" "store")]) 8889 8890(define_insn "*stmsi8" 8891 [(match_parallel 0 "store_multiple_operation" 8892 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 8893 (match_operand:SI 2 "gpc_reg_operand" "r")) 8894 (clobber (match_scratch:SI 3 "X")) 8895 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 8896 (match_operand:SI 4 "gpc_reg_operand" "r")) 8897 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 8898 (match_operand:SI 5 "gpc_reg_operand" "r")) 8899 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 8900 (match_operand:SI 6 "gpc_reg_operand" "r")) 8901 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 8902 (match_operand:SI 7 "gpc_reg_operand" "r")) 8903 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 8904 (match_operand:SI 8 "gpc_reg_operand" "r")) 8905 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) 8906 (match_operand:SI 9 "gpc_reg_operand" "r")) 8907 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) 8908 (match_operand:SI 10 "gpc_reg_operand" "r"))])] 8909 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" 8910 "{stsi|stswi} %2,%1,%O0" 8911 [(set_attr "type" "store")]) 8912 8913(define_insn "*stmsi7" 8914 [(match_parallel 0 "store_multiple_operation" 8915 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 8916 (match_operand:SI 2 "gpc_reg_operand" "r")) 8917 (clobber (match_scratch:SI 3 "X")) 8918 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 8919 (match_operand:SI 4 "gpc_reg_operand" "r")) 8920 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 8921 (match_operand:SI 5 "gpc_reg_operand" "r")) 8922 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 8923 (match_operand:SI 6 "gpc_reg_operand" "r")) 8924 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 8925 (match_operand:SI 7 "gpc_reg_operand" "r")) 8926 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 8927 (match_operand:SI 8 "gpc_reg_operand" "r")) 8928 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) 8929 (match_operand:SI 9 "gpc_reg_operand" "r"))])] 8930 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" 8931 "{stsi|stswi} %2,%1,%O0" 8932 [(set_attr "type" "store")]) 8933 8934(define_insn "*stmsi6" 8935 [(match_parallel 0 "store_multiple_operation" 8936 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 8937 (match_operand:SI 2 "gpc_reg_operand" "r")) 8938 (clobber (match_scratch:SI 3 "X")) 8939 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 8940 (match_operand:SI 4 "gpc_reg_operand" "r")) 8941 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 8942 (match_operand:SI 5 "gpc_reg_operand" "r")) 8943 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 8944 (match_operand:SI 6 "gpc_reg_operand" "r")) 8945 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 8946 (match_operand:SI 7 "gpc_reg_operand" "r")) 8947 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 8948 (match_operand:SI 8 "gpc_reg_operand" "r"))])] 8949 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" 8950 "{stsi|stswi} %2,%1,%O0" 8951 [(set_attr "type" "store")]) 8952 8953(define_insn "*stmsi5" 8954 [(match_parallel 0 "store_multiple_operation" 8955 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 8956 (match_operand:SI 2 "gpc_reg_operand" "r")) 8957 (clobber (match_scratch:SI 3 "X")) 8958 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 8959 (match_operand:SI 4 "gpc_reg_operand" "r")) 8960 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 8961 (match_operand:SI 5 "gpc_reg_operand" "r")) 8962 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 8963 (match_operand:SI 6 "gpc_reg_operand" "r")) 8964 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 8965 (match_operand:SI 7 "gpc_reg_operand" "r"))])] 8966 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" 8967 "{stsi|stswi} %2,%1,%O0" 8968 [(set_attr "type" "store")]) 8969 8970(define_insn "*stmsi4" 8971 [(match_parallel 0 "store_multiple_operation" 8972 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 8973 (match_operand:SI 2 "gpc_reg_operand" "r")) 8974 (clobber (match_scratch:SI 3 "X")) 8975 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 8976 (match_operand:SI 4 "gpc_reg_operand" "r")) 8977 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 8978 (match_operand:SI 5 "gpc_reg_operand" "r")) 8979 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 8980 (match_operand:SI 6 "gpc_reg_operand" "r"))])] 8981 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" 8982 "{stsi|stswi} %2,%1,%O0" 8983 [(set_attr "type" "store")]) 8984 8985(define_insn "*stmsi3" 8986 [(match_parallel 0 "store_multiple_operation" 8987 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 8988 (match_operand:SI 2 "gpc_reg_operand" "r")) 8989 (clobber (match_scratch:SI 3 "X")) 8990 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 8991 (match_operand:SI 4 "gpc_reg_operand" "r")) 8992 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 8993 (match_operand:SI 5 "gpc_reg_operand" "r"))])] 8994 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" 8995 "{stsi|stswi} %2,%1,%O0" 8996 [(set_attr "type" "store")]) 8997 8998;; String/block move insn. 8999;; Argument 0 is the destination 9000;; Argument 1 is the source 9001;; Argument 2 is the length 9002;; Argument 3 is the alignment 9003 9004(define_expand "movstrsi" 9005 [(parallel [(set (match_operand:BLK 0 "" "") 9006 (match_operand:BLK 1 "" "")) 9007 (use (match_operand:SI 2 "" "")) 9008 (use (match_operand:SI 3 "" ""))])] 9009 "" 9010 " 9011{ 9012 if (expand_block_move (operands)) 9013 DONE; 9014 else 9015 FAIL; 9016}") 9017 9018;; Move up to 32 bytes at a time. The fixed registers are needed because the 9019;; register allocator doesn't have a clue about allocating 8 word registers. 9020;; rD/rS = r5 is preferred, efficient form. 9021(define_expand "movstrsi_8reg" 9022 [(parallel [(set (match_operand 0 "" "") 9023 (match_operand 1 "" "")) 9024 (use (match_operand 2 "" "")) 9025 (use (match_operand 3 "" "")) 9026 (clobber (reg:SI 5)) 9027 (clobber (reg:SI 6)) 9028 (clobber (reg:SI 7)) 9029 (clobber (reg:SI 8)) 9030 (clobber (reg:SI 9)) 9031 (clobber (reg:SI 10)) 9032 (clobber (reg:SI 11)) 9033 (clobber (reg:SI 12)) 9034 (clobber (match_scratch:SI 4 ""))])] 9035 "TARGET_STRING" 9036 "") 9037 9038(define_insn "" 9039 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9040 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9041 (use (match_operand:SI 2 "immediate_operand" "i")) 9042 (use (match_operand:SI 3 "immediate_operand" "i")) 9043 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9044 (clobber (reg:SI 6)) 9045 (clobber (reg:SI 7)) 9046 (clobber (reg:SI 8)) 9047 (clobber (reg:SI 9)) 9048 (clobber (reg:SI 10)) 9049 (clobber (reg:SI 11)) 9050 (clobber (reg:SI 12)) 9051 (clobber (match_scratch:SI 5 "=q"))] 9052 "TARGET_STRING && TARGET_POWER 9053 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) 9054 || INTVAL (operands[2]) == 0) 9055 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 9056 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 9057 && REGNO (operands[4]) == 5" 9058 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9059 [(set_attr "type" "load") 9060 (set_attr "length" "8")]) 9061 9062(define_insn "" 9063 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9064 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9065 (use (match_operand:SI 2 "immediate_operand" "i")) 9066 (use (match_operand:SI 3 "immediate_operand" "i")) 9067 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9068 (clobber (reg:SI 6)) 9069 (clobber (reg:SI 7)) 9070 (clobber (reg:SI 8)) 9071 (clobber (reg:SI 9)) 9072 (clobber (reg:SI 10)) 9073 (clobber (reg:SI 11)) 9074 (clobber (reg:SI 12)) 9075 (clobber (match_scratch:SI 5 "X"))] 9076 "TARGET_STRING && ! TARGET_POWER 9077 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) 9078 || INTVAL (operands[2]) == 0) 9079 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 9080 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 9081 && REGNO (operands[4]) == 5" 9082 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9083 [(set_attr "type" "load") 9084 (set_attr "length" "8")]) 9085 9086(define_insn "" 9087 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) 9088 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) 9089 (use (match_operand:SI 2 "immediate_operand" "i")) 9090 (use (match_operand:SI 3 "immediate_operand" "i")) 9091 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9092 (clobber (reg:SI 6)) 9093 (clobber (reg:SI 7)) 9094 (clobber (reg:SI 8)) 9095 (clobber (reg:SI 9)) 9096 (clobber (reg:SI 10)) 9097 (clobber (reg:SI 11)) 9098 (clobber (reg:SI 12)) 9099 (clobber (match_scratch:SI 5 "X"))] 9100 "TARGET_STRING && TARGET_POWERPC64 9101 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) 9102 || INTVAL (operands[2]) == 0) 9103 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 9104 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 9105 && REGNO (operands[4]) == 5" 9106 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9107 [(set_attr "type" "load") 9108 (set_attr "length" "8")]) 9109 9110;; Move up to 24 bytes at a time. The fixed registers are needed because the 9111;; register allocator doesn't have a clue about allocating 6 word registers. 9112;; rD/rS = r5 is preferred, efficient form. 9113(define_expand "movstrsi_6reg" 9114 [(parallel [(set (match_operand 0 "" "") 9115 (match_operand 1 "" "")) 9116 (use (match_operand 2 "" "")) 9117 (use (match_operand 3 "" "")) 9118 (clobber (reg:SI 5)) 9119 (clobber (reg:SI 6)) 9120 (clobber (reg:SI 7)) 9121 (clobber (reg:SI 8)) 9122 (clobber (reg:SI 9)) 9123 (clobber (reg:SI 10)) 9124 (clobber (match_scratch:SI 4 ""))])] 9125 "TARGET_STRING" 9126 "") 9127 9128(define_insn "" 9129 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9130 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9131 (use (match_operand:SI 2 "immediate_operand" "i")) 9132 (use (match_operand:SI 3 "immediate_operand" "i")) 9133 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9134 (clobber (reg:SI 6)) 9135 (clobber (reg:SI 7)) 9136 (clobber (reg:SI 8)) 9137 (clobber (reg:SI 9)) 9138 (clobber (reg:SI 10)) 9139 (clobber (match_scratch:SI 5 "=q"))] 9140 "TARGET_STRING && TARGET_POWER 9141 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 9142 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) 9143 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) 9144 && REGNO (operands[4]) == 5" 9145 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9146 [(set_attr "type" "load") 9147 (set_attr "length" "8")]) 9148 9149(define_insn "" 9150 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9151 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9152 (use (match_operand:SI 2 "immediate_operand" "i")) 9153 (use (match_operand:SI 3 "immediate_operand" "i")) 9154 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9155 (clobber (reg:SI 6)) 9156 (clobber (reg:SI 7)) 9157 (clobber (reg:SI 8)) 9158 (clobber (reg:SI 9)) 9159 (clobber (reg:SI 10)) 9160 (clobber (match_scratch:SI 5 "X"))] 9161 "TARGET_STRING && ! TARGET_POWER 9162 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 9163 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) 9164 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) 9165 && REGNO (operands[4]) == 5" 9166 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9167 [(set_attr "type" "load") 9168 (set_attr "length" "8")]) 9169 9170(define_insn "" 9171 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) 9172 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) 9173 (use (match_operand:SI 2 "immediate_operand" "i")) 9174 (use (match_operand:SI 3 "immediate_operand" "i")) 9175 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9176 (clobber (reg:SI 6)) 9177 (clobber (reg:SI 7)) 9178 (clobber (reg:SI 8)) 9179 (clobber (reg:SI 9)) 9180 (clobber (reg:SI 10)) 9181 (clobber (match_scratch:SI 5 "X"))] 9182 "TARGET_STRING && TARGET_POWERPC64 9183 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 9184 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) 9185 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) 9186 && REGNO (operands[4]) == 5" 9187 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9188 [(set_attr "type" "load") 9189 (set_attr "length" "8")]) 9190 9191;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill 9192;; problems with TImode. 9193;; rD/rS = r5 is preferred, efficient form. 9194(define_expand "movstrsi_4reg" 9195 [(parallel [(set (match_operand 0 "" "") 9196 (match_operand 1 "" "")) 9197 (use (match_operand 2 "" "")) 9198 (use (match_operand 3 "" "")) 9199 (clobber (reg:SI 5)) 9200 (clobber (reg:SI 6)) 9201 (clobber (reg:SI 7)) 9202 (clobber (reg:SI 8)) 9203 (clobber (match_scratch:SI 4 ""))])] 9204 "TARGET_STRING" 9205 "") 9206 9207(define_insn "" 9208 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9209 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9210 (use (match_operand:SI 2 "immediate_operand" "i")) 9211 (use (match_operand:SI 3 "immediate_operand" "i")) 9212 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9213 (clobber (reg:SI 6)) 9214 (clobber (reg:SI 7)) 9215 (clobber (reg:SI 8)) 9216 (clobber (match_scratch:SI 5 "=q"))] 9217 "TARGET_STRING && TARGET_POWER 9218 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 9219 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) 9220 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) 9221 && REGNO (operands[4]) == 5" 9222 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9223 [(set_attr "type" "load") 9224 (set_attr "length" "8")]) 9225 9226(define_insn "" 9227 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9228 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9229 (use (match_operand:SI 2 "immediate_operand" "i")) 9230 (use (match_operand:SI 3 "immediate_operand" "i")) 9231 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9232 (clobber (reg:SI 6)) 9233 (clobber (reg:SI 7)) 9234 (clobber (reg:SI 8)) 9235 (clobber (match_scratch:SI 5 "X"))] 9236 "TARGET_STRING && ! TARGET_POWER 9237 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 9238 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) 9239 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) 9240 && REGNO (operands[4]) == 5" 9241 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9242 [(set_attr "type" "load") 9243 (set_attr "length" "8")]) 9244 9245(define_insn "" 9246 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) 9247 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) 9248 (use (match_operand:SI 2 "immediate_operand" "i")) 9249 (use (match_operand:SI 3 "immediate_operand" "i")) 9250 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9251 (clobber (reg:SI 6)) 9252 (clobber (reg:SI 7)) 9253 (clobber (reg:SI 8)) 9254 (clobber (match_scratch:SI 5 "X"))] 9255 "TARGET_STRING && TARGET_POWERPC64 9256 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 9257 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) 9258 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) 9259 && REGNO (operands[4]) == 5" 9260 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9261 [(set_attr "type" "load") 9262 (set_attr "length" "8")]) 9263 9264;; Move up to 8 bytes at a time. 9265(define_expand "movstrsi_2reg" 9266 [(parallel [(set (match_operand 0 "" "") 9267 (match_operand 1 "" "")) 9268 (use (match_operand 2 "" "")) 9269 (use (match_operand 3 "" "")) 9270 (clobber (match_scratch:DI 4 "")) 9271 (clobber (match_scratch:SI 5 ""))])] 9272 "TARGET_STRING && ! TARGET_POWERPC64" 9273 "") 9274 9275(define_insn "" 9276 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9277 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9278 (use (match_operand:SI 2 "immediate_operand" "i")) 9279 (use (match_operand:SI 3 "immediate_operand" "i")) 9280 (clobber (match_scratch:DI 4 "=&r")) 9281 (clobber (match_scratch:SI 5 "=q"))] 9282 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 9283 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" 9284 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9285 [(set_attr "type" "load") 9286 (set_attr "length" "8")]) 9287 9288(define_insn "" 9289 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9290 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9291 (use (match_operand:SI 2 "immediate_operand" "i")) 9292 (use (match_operand:SI 3 "immediate_operand" "i")) 9293 (clobber (match_scratch:DI 4 "=&r")) 9294 (clobber (match_scratch:SI 5 "X"))] 9295 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 9296 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" 9297 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9298 [(set_attr "type" "load") 9299 (set_attr "length" "8")]) 9300 9301;; Move up to 4 bytes at a time. 9302(define_expand "movstrsi_1reg" 9303 [(parallel [(set (match_operand 0 "" "") 9304 (match_operand 1 "" "")) 9305 (use (match_operand 2 "" "")) 9306 (use (match_operand 3 "" "")) 9307 (clobber (match_scratch:SI 4 "")) 9308 (clobber (match_scratch:SI 5 ""))])] 9309 "TARGET_STRING" 9310 "") 9311 9312(define_insn "" 9313 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9314 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9315 (use (match_operand:SI 2 "immediate_operand" "i")) 9316 (use (match_operand:SI 3 "immediate_operand" "i")) 9317 (clobber (match_scratch:SI 4 "=&r")) 9318 (clobber (match_scratch:SI 5 "=q"))] 9319 "TARGET_STRING && TARGET_POWER 9320 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 9321 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9322 [(set_attr "type" "load") 9323 (set_attr "length" "8")]) 9324 9325(define_insn "" 9326 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9327 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9328 (use (match_operand:SI 2 "immediate_operand" "i")) 9329 (use (match_operand:SI 3 "immediate_operand" "i")) 9330 (clobber (match_scratch:SI 4 "=&r")) 9331 (clobber (match_scratch:SI 5 "X"))] 9332 "TARGET_STRING && ! TARGET_POWER 9333 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 9334 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9335 [(set_attr "type" "load") 9336 (set_attr "length" "8")]) 9337 9338(define_insn "" 9339 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) 9340 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) 9341 (use (match_operand:SI 2 "immediate_operand" "i")) 9342 (use (match_operand:SI 3 "immediate_operand" "i")) 9343 (clobber (match_scratch:SI 4 "=&r")) 9344 (clobber (match_scratch:SI 5 "X"))] 9345 "TARGET_STRING && TARGET_POWERPC64 9346 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 9347 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9348 [(set_attr "type" "load") 9349 (set_attr "length" "8")]) 9350 9351 9352;; Define insns that do load or store with update. Some of these we can 9353;; get by using pre-decrement or pre-increment, but the hardware can also 9354;; do cases where the increment is not the size of the object. 9355;; 9356;; In all these cases, we use operands 0 and 1 for the register being 9357;; incremented because those are the operands that local-alloc will 9358;; tie and these are the pair most likely to be tieable (and the ones 9359;; that will benefit the most). 9360 9361(define_insn "*movdi_update1" 9362 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") 9363 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 9364 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) 9365 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 9366 (plus:DI (match_dup 1) (match_dup 2)))] 9367 "TARGET_POWERPC64 && TARGET_UPDATE" 9368 "@ 9369 ldux %3,%0,%2 9370 ldu %3,%2(%0)" 9371 [(set_attr "type" "load_ux,load_u")]) 9372 9373(define_insn "movdi_update" 9374 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 9375 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))) 9376 (match_operand:DI 3 "gpc_reg_operand" "r,r")) 9377 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 9378 (plus:DI (match_dup 1) (match_dup 2)))] 9379 "TARGET_POWERPC64 && TARGET_UPDATE" 9380 "@ 9381 stdux %3,%0,%2 9382 stdu %3,%2(%0)" 9383 [(set_attr "type" "store_ux,store_u")]) 9384 9385(define_insn "*movsi_update1" 9386 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9387 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9388 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9389 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9390 (plus:SI (match_dup 1) (match_dup 2)))] 9391 "TARGET_UPDATE" 9392 "@ 9393 {lux|lwzux} %3,%0,%2 9394 {lu|lwzu} %3,%2(%0)" 9395 [(set_attr "type" "load_ux,load_u")]) 9396 9397(define_insn "*movsi_update2" 9398 [(set (match_operand:DI 3 "gpc_reg_operand" "=r") 9399 (sign_extend:DI 9400 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") 9401 (match_operand:DI 2 "gpc_reg_operand" "r"))))) 9402 (set (match_operand:DI 0 "gpc_reg_operand" "=b") 9403 (plus:DI (match_dup 1) (match_dup 2)))] 9404 "TARGET_POWERPC64" 9405 "lwaux %3,%0,%2" 9406 [(set_attr "type" "load_ext_ux")]) 9407 9408(define_insn "movsi_update" 9409 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9410 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9411 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 9412 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9413 (plus:SI (match_dup 1) (match_dup 2)))] 9414 "TARGET_UPDATE" 9415 "@ 9416 {stux|stwux} %3,%0,%2 9417 {stu|stwu} %3,%2(%0)" 9418 [(set_attr "type" "store_ux,store_u")]) 9419 9420(define_insn "*movhi_update1" 9421 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") 9422 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9423 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9424 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9425 (plus:SI (match_dup 1) (match_dup 2)))] 9426 "TARGET_UPDATE" 9427 "@ 9428 lhzux %3,%0,%2 9429 lhzu %3,%2(%0)" 9430 [(set_attr "type" "load_ux,load_u")]) 9431 9432(define_insn "*movhi_update2" 9433 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9434 (zero_extend:SI 9435 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9436 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 9437 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9438 (plus:SI (match_dup 1) (match_dup 2)))] 9439 "TARGET_UPDATE" 9440 "@ 9441 lhzux %3,%0,%2 9442 lhzu %3,%2(%0)" 9443 [(set_attr "type" "load_ux,load_u")]) 9444 9445(define_insn "*movhi_update3" 9446 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9447 (sign_extend:SI 9448 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9449 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 9450 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9451 (plus:SI (match_dup 1) (match_dup 2)))] 9452 "TARGET_UPDATE" 9453 "@ 9454 lhaux %3,%0,%2 9455 lhau %3,%2(%0)" 9456 [(set_attr "type" "load_ext_ux,load_ext_u")]) 9457 9458(define_insn "*movhi_update4" 9459 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9460 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9461 (match_operand:HI 3 "gpc_reg_operand" "r,r")) 9462 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9463 (plus:SI (match_dup 1) (match_dup 2)))] 9464 "TARGET_UPDATE" 9465 "@ 9466 sthux %3,%0,%2 9467 sthu %3,%2(%0)" 9468 [(set_attr "type" "store_ux,store_u")]) 9469 9470(define_insn "*movqi_update1" 9471 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") 9472 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9473 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9474 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9475 (plus:SI (match_dup 1) (match_dup 2)))] 9476 "TARGET_UPDATE" 9477 "@ 9478 lbzux %3,%0,%2 9479 lbzu %3,%2(%0)" 9480 [(set_attr "type" "load_ux,load_u")]) 9481 9482(define_insn "*movqi_update2" 9483 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9484 (zero_extend:SI 9485 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9486 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 9487 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9488 (plus:SI (match_dup 1) (match_dup 2)))] 9489 "TARGET_UPDATE" 9490 "@ 9491 lbzux %3,%0,%2 9492 lbzu %3,%2(%0)" 9493 [(set_attr "type" "load_ux,load_u")]) 9494 9495(define_insn "*movqi_update3" 9496 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9497 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9498 (match_operand:QI 3 "gpc_reg_operand" "r,r")) 9499 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9500 (plus:SI (match_dup 1) (match_dup 2)))] 9501 "TARGET_UPDATE" 9502 "@ 9503 stbux %3,%0,%2 9504 stbu %3,%2(%0)" 9505 [(set_attr "type" "store_ux,store_u")]) 9506 9507(define_insn "*movsf_update1" 9508 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") 9509 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9510 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9511 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9512 (plus:SI (match_dup 1) (match_dup 2)))] 9513 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" 9514 "@ 9515 lfsux %3,%0,%2 9516 lfsu %3,%2(%0)" 9517 [(set_attr "type" "fpload_ux,fpload_u")]) 9518 9519(define_insn "*movsf_update2" 9520 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9521 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9522 (match_operand:SF 3 "gpc_reg_operand" "f,f")) 9523 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9524 (plus:SI (match_dup 1) (match_dup 2)))] 9525 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" 9526 "@ 9527 stfsux %3,%0,%2 9528 stfsu %3,%2(%0)" 9529 [(set_attr "type" "fpstore_ux,fpstore_u")]) 9530 9531(define_insn "*movsf_update3" 9532 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") 9533 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9534 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9535 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9536 (plus:SI (match_dup 1) (match_dup 2)))] 9537 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" 9538 "@ 9539 {lux|lwzux} %3,%0,%2 9540 {lu|lwzu} %3,%2(%0)" 9541 [(set_attr "type" "load_ux,load_u")]) 9542 9543(define_insn "*movsf_update4" 9544 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9545 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9546 (match_operand:SF 3 "gpc_reg_operand" "r,r")) 9547 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9548 (plus:SI (match_dup 1) (match_dup 2)))] 9549 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" 9550 "@ 9551 {stux|stwux} %3,%0,%2 9552 {stu|stwu} %3,%2(%0)" 9553 [(set_attr "type" "store_ux,store_u")]) 9554 9555(define_insn "*movdf_update1" 9556 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") 9557 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9558 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9559 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9560 (plus:SI (match_dup 1) (match_dup 2)))] 9561 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" 9562 "@ 9563 lfdux %3,%0,%2 9564 lfdu %3,%2(%0)" 9565 [(set_attr "type" "fpload_ux,fpload_u")]) 9566 9567(define_insn "*movdf_update2" 9568 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9569 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9570 (match_operand:DF 3 "gpc_reg_operand" "f,f")) 9571 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9572 (plus:SI (match_dup 1) (match_dup 2)))] 9573 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" 9574 "@ 9575 stfdux %3,%0,%2 9576 stfdu %3,%2(%0)" 9577 [(set_attr "type" "fpstore_ux,fpstore_u")]) 9578 9579;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. 9580 9581(define_peephole 9582 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 9583 (match_operand:DF 1 "memory_operand" "")) 9584 (set (match_operand:DF 2 "gpc_reg_operand" "=f") 9585 (match_operand:DF 3 "memory_operand" ""))] 9586 "TARGET_POWER2 9587 && TARGET_HARD_FLOAT && TARGET_FPRS 9588 && registers_ok_for_quad_peep (operands[0], operands[2]) 9589 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) 9590 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" 9591 "lfq%U1%X1 %0,%1") 9592 9593(define_peephole 9594 [(set (match_operand:DF 0 "memory_operand" "") 9595 (match_operand:DF 1 "gpc_reg_operand" "f")) 9596 (set (match_operand:DF 2 "memory_operand" "") 9597 (match_operand:DF 3 "gpc_reg_operand" "f"))] 9598 "TARGET_POWER2 9599 && TARGET_HARD_FLOAT && TARGET_FPRS 9600 && registers_ok_for_quad_peep (operands[1], operands[3]) 9601 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) 9602 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" 9603 "stfq%U0%X0 %1,%0") 9604 9605;; TLS support. 9606 9607;; "b" output constraint here and on tls_ld to support tls linker optimization. 9608(define_insn "tls_gd_32" 9609 [(set (match_operand:SI 0 "register_operand" "=b") 9610 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9611 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9612 UNSPEC_TLSGD))] 9613 "HAVE_AS_TLS && !TARGET_64BIT" 9614 "addi %0,%1,%2@got@tlsgd") 9615 9616(define_insn "tls_gd_64" 9617 [(set (match_operand:DI 0 "register_operand" "=b") 9618 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9619 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9620 UNSPEC_TLSGD))] 9621 "HAVE_AS_TLS && TARGET_64BIT" 9622 "addi %0,%1,%2@got@tlsgd") 9623 9624(define_insn "tls_ld_32" 9625 [(set (match_operand:SI 0 "register_operand" "=b") 9626 (unspec:SI [(match_operand:SI 1 "register_operand" "b")] 9627 UNSPEC_TLSLD))] 9628 "HAVE_AS_TLS && !TARGET_64BIT" 9629 "addi %0,%1,%&@got@tlsld") 9630 9631(define_insn "tls_ld_64" 9632 [(set (match_operand:DI 0 "register_operand" "=b") 9633 (unspec:DI [(match_operand:DI 1 "register_operand" "b")] 9634 UNSPEC_TLSLD))] 9635 "HAVE_AS_TLS && TARGET_64BIT" 9636 "addi %0,%1,%&@got@tlsld") 9637 9638(define_insn "tls_dtprel_32" 9639 [(set (match_operand:SI 0 "register_operand" "=r") 9640 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9641 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9642 UNSPEC_TLSDTPREL))] 9643 "HAVE_AS_TLS && !TARGET_64BIT" 9644 "addi %0,%1,%2@dtprel") 9645 9646(define_insn "tls_dtprel_64" 9647 [(set (match_operand:DI 0 "register_operand" "=r") 9648 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9649 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9650 UNSPEC_TLSDTPREL))] 9651 "HAVE_AS_TLS && TARGET_64BIT" 9652 "addi %0,%1,%2@dtprel") 9653 9654(define_insn "tls_dtprel_ha_32" 9655 [(set (match_operand:SI 0 "register_operand" "=r") 9656 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9657 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9658 UNSPEC_TLSDTPRELHA))] 9659 "HAVE_AS_TLS && !TARGET_64BIT" 9660 "addis %0,%1,%2@dtprel@ha") 9661 9662(define_insn "tls_dtprel_ha_64" 9663 [(set (match_operand:DI 0 "register_operand" "=r") 9664 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9665 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9666 UNSPEC_TLSDTPRELHA))] 9667 "HAVE_AS_TLS && TARGET_64BIT" 9668 "addis %0,%1,%2@dtprel@ha") 9669 9670(define_insn "tls_dtprel_lo_32" 9671 [(set (match_operand:SI 0 "register_operand" "=r") 9672 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9673 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9674 UNSPEC_TLSDTPRELLO))] 9675 "HAVE_AS_TLS && !TARGET_64BIT" 9676 "addi %0,%1,%2@dtprel@l") 9677 9678(define_insn "tls_dtprel_lo_64" 9679 [(set (match_operand:DI 0 "register_operand" "=r") 9680 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9681 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9682 UNSPEC_TLSDTPRELLO))] 9683 "HAVE_AS_TLS && TARGET_64BIT" 9684 "addi %0,%1,%2@dtprel@l") 9685 9686(define_insn "tls_got_dtprel_32" 9687 [(set (match_operand:SI 0 "register_operand" "=r") 9688 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9689 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9690 UNSPEC_TLSGOTDTPREL))] 9691 "HAVE_AS_TLS && !TARGET_64BIT" 9692 "lwz %0,%2@got@dtprel(%1)") 9693 9694(define_insn "tls_got_dtprel_64" 9695 [(set (match_operand:DI 0 "register_operand" "=r") 9696 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9697 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9698 UNSPEC_TLSGOTDTPREL))] 9699 "HAVE_AS_TLS && TARGET_64BIT" 9700 "ld %0,%2@got@dtprel(%1)") 9701 9702(define_insn "tls_tprel_32" 9703 [(set (match_operand:SI 0 "register_operand" "=r") 9704 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9705 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9706 UNSPEC_TLSTPREL))] 9707 "HAVE_AS_TLS && !TARGET_64BIT" 9708 "addi %0,%1,%2@tprel") 9709 9710(define_insn "tls_tprel_64" 9711 [(set (match_operand:DI 0 "register_operand" "=r") 9712 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9713 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9714 UNSPEC_TLSTPREL))] 9715 "HAVE_AS_TLS && TARGET_64BIT" 9716 "addi %0,%1,%2@tprel") 9717 9718(define_insn "tls_tprel_ha_32" 9719 [(set (match_operand:SI 0 "register_operand" "=r") 9720 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9721 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9722 UNSPEC_TLSTPRELHA))] 9723 "HAVE_AS_TLS && !TARGET_64BIT" 9724 "addis %0,%1,%2@tprel@ha") 9725 9726(define_insn "tls_tprel_ha_64" 9727 [(set (match_operand:DI 0 "register_operand" "=r") 9728 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9729 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9730 UNSPEC_TLSTPRELHA))] 9731 "HAVE_AS_TLS && TARGET_64BIT" 9732 "addis %0,%1,%2@tprel@ha") 9733 9734(define_insn "tls_tprel_lo_32" 9735 [(set (match_operand:SI 0 "register_operand" "=r") 9736 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9737 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9738 UNSPEC_TLSTPRELLO))] 9739 "HAVE_AS_TLS && !TARGET_64BIT" 9740 "addi %0,%1,%2@tprel@l") 9741 9742(define_insn "tls_tprel_lo_64" 9743 [(set (match_operand:DI 0 "register_operand" "=r") 9744 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9745 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9746 UNSPEC_TLSTPRELLO))] 9747 "HAVE_AS_TLS && TARGET_64BIT" 9748 "addi %0,%1,%2@tprel@l") 9749 9750;; "b" output constraint here and on tls_tls input to support linker tls 9751;; optimization. The linker may edit the instructions emitted by a 9752;; tls_got_tprel/tls_tls pair to addis,addi. 9753(define_insn "tls_got_tprel_32" 9754 [(set (match_operand:SI 0 "register_operand" "=b") 9755 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9756 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9757 UNSPEC_TLSGOTTPREL))] 9758 "HAVE_AS_TLS && !TARGET_64BIT" 9759 "lwz %0,%2@got@tprel(%1)") 9760 9761(define_insn "tls_got_tprel_64" 9762 [(set (match_operand:DI 0 "register_operand" "=b") 9763 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9764 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9765 UNSPEC_TLSGOTTPREL))] 9766 "HAVE_AS_TLS && TARGET_64BIT" 9767 "ld %0,%2@got@tprel(%1)") 9768 9769(define_insn "tls_tls_32" 9770 [(set (match_operand:SI 0 "register_operand" "=r") 9771 (unspec:SI [(match_operand:SI 1 "register_operand" "b") 9772 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] 9773 UNSPEC_TLSTLS))] 9774 "HAVE_AS_TLS && !TARGET_64BIT" 9775 "add %0,%1,%2@tls") 9776 9777(define_insn "tls_tls_64" 9778 [(set (match_operand:DI 0 "register_operand" "=r") 9779 (unspec:DI [(match_operand:DI 1 "register_operand" "b") 9780 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] 9781 UNSPEC_TLSTLS))] 9782 "HAVE_AS_TLS && TARGET_64BIT" 9783 "add %0,%1,%2@tls") 9784 9785;; Next come insns related to the calling sequence. 9786;; 9787;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). 9788;; We move the back-chain and decrement the stack pointer. 9789 9790(define_expand "allocate_stack" 9791 [(set (match_operand 0 "gpc_reg_operand" "=r") 9792 (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) 9793 (set (reg 1) 9794 (minus (reg 1) (match_dup 1)))] 9795 "" 9796 " 9797{ rtx chain = gen_reg_rtx (Pmode); 9798 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); 9799 rtx neg_op0; 9800 9801 emit_move_insn (chain, stack_bot); 9802 9803 /* Check stack bounds if necessary. */ 9804 if (current_function_limit_stack) 9805 { 9806 rtx available; 9807 available = expand_binop (Pmode, sub_optab, 9808 stack_pointer_rtx, stack_limit_rtx, 9809 NULL_RTX, 1, OPTAB_WIDEN); 9810 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); 9811 } 9812 9813 if (GET_CODE (operands[1]) != CONST_INT 9814 || INTVAL (operands[1]) < -32767 9815 || INTVAL (operands[1]) > 32768) 9816 { 9817 neg_op0 = gen_reg_rtx (Pmode); 9818 if (TARGET_32BIT) 9819 emit_insn (gen_negsi2 (neg_op0, operands[1])); 9820 else 9821 emit_insn (gen_negdi2 (neg_op0, operands[1])); 9822 } 9823 else 9824 neg_op0 = GEN_INT (- INTVAL (operands[1])); 9825 9826 if (TARGET_UPDATE) 9827 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) 9828 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); 9829 9830 else 9831 { 9832 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) 9833 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); 9834 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); 9835 } 9836 9837 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 9838 DONE; 9839}") 9840 9841;; These patterns say how to save and restore the stack pointer. We need not 9842;; save the stack pointer at function level since we are careful to 9843;; preserve the backchain. At block level, we have to restore the backchain 9844;; when we restore the stack pointer. 9845;; 9846;; For nonlocal gotos, we must save both the stack pointer and its 9847;; backchain and restore both. Note that in the nonlocal case, the 9848;; save area is a memory location. 9849 9850(define_expand "save_stack_function" 9851 [(match_operand 0 "any_operand" "") 9852 (match_operand 1 "any_operand" "")] 9853 "" 9854 "DONE;") 9855 9856(define_expand "restore_stack_function" 9857 [(match_operand 0 "any_operand" "") 9858 (match_operand 1 "any_operand" "")] 9859 "" 9860 "DONE;") 9861 9862(define_expand "restore_stack_block" 9863 [(use (match_operand 0 "register_operand" "")) 9864 (set (match_dup 2) (match_dup 3)) 9865 (set (match_dup 0) (match_operand 1 "register_operand" "")) 9866 (set (match_dup 3) (match_dup 2))] 9867 "" 9868 " 9869{ 9870 operands[2] = gen_reg_rtx (Pmode); 9871 operands[3] = gen_rtx_MEM (Pmode, operands[0]); 9872}") 9873 9874(define_expand "save_stack_nonlocal" 9875 [(match_operand 0 "memory_operand" "") 9876 (match_operand 1 "register_operand" "")] 9877 "" 9878 " 9879{ 9880 rtx temp = gen_reg_rtx (Pmode); 9881 9882 /* Copy the backchain to the first word, sp to the second. */ 9883 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); 9884 emit_move_insn (operand_subword (operands[0], 0, 0, 9885 (TARGET_32BIT ? DImode : TImode)), 9886 temp); 9887 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), 9888 operands[1]); 9889 DONE; 9890}") 9891 9892(define_expand "restore_stack_nonlocal" 9893 [(match_operand 0 "register_operand" "") 9894 (match_operand 1 "memory_operand" "")] 9895 "" 9896 " 9897{ 9898 rtx temp = gen_reg_rtx (Pmode); 9899 9900 /* Restore the backchain from the first word, sp from the second. */ 9901 emit_move_insn (temp, 9902 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); 9903 emit_move_insn (operands[0], 9904 operand_subword (operands[1], 1, 0, 9905 (TARGET_32BIT ? DImode : TImode))); 9906 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); 9907 DONE; 9908}") 9909 9910;; TOC register handling. 9911 9912;; Code to initialize the TOC register... 9913 9914(define_insn "load_toc_aix_si" 9915 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9916 (unspec:SI [(const_int 0)] UNSPEC_TOC)) 9917 (use (reg:SI 2))])] 9918 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" 9919 "* 9920{ 9921 char buf[30]; 9922 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); 9923 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 9924 operands[2] = gen_rtx_REG (Pmode, 2); 9925 return \"{l|lwz} %0,%1(%2)\"; 9926}" 9927 [(set_attr "type" "load")]) 9928 9929(define_insn "load_toc_aix_di" 9930 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9931 (unspec:DI [(const_int 0)] UNSPEC_TOC)) 9932 (use (reg:DI 2))])] 9933 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" 9934 "* 9935{ 9936 char buf[30]; 9937#ifdef TARGET_RELOCATABLE 9938 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 9939 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); 9940#else 9941 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); 9942#endif 9943 if (TARGET_ELF) 9944 strcat (buf, \"@toc\"); 9945 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 9946 operands[2] = gen_rtx_REG (Pmode, 2); 9947 return \"ld %0,%1(%2)\"; 9948}" 9949 [(set_attr "type" "load")]) 9950 9951(define_insn "load_toc_v4_pic_si" 9952 [(set (match_operand:SI 0 "register_operand" "=l") 9953 (unspec:SI [(const_int 0)] UNSPEC_TOC))] 9954 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" 9955 "bl _GLOBAL_OFFSET_TABLE_@local-4" 9956 [(set_attr "type" "branch") 9957 (set_attr "length" "4")]) 9958 9959(define_insn "load_toc_v4_PIC_1" 9960 [(set (match_operand:SI 0 "register_operand" "=l") 9961 (match_operand:SI 1 "immediate_operand" "s")) 9962 (use (unspec [(match_dup 1)] UNSPEC_TOC))] 9963 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" 9964 "bcl 20,31,%1\\n%1:" 9965 [(set_attr "type" "branch") 9966 (set_attr "length" "4")]) 9967 9968(define_insn "load_toc_v4_PIC_1b" 9969 [(set (match_operand:SI 0 "register_operand" "=l") 9970 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 9971 UNSPEC_TOCPTR))] 9972 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" 9973 "bcl 20,31,$+8\\n\\t.long %1-$" 9974 [(set_attr "type" "branch") 9975 (set_attr "length" "8")]) 9976 9977(define_insn "load_toc_v4_PIC_2" 9978 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9979 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 9980 (minus:SI (match_operand:SI 2 "immediate_operand" "s") 9981 (match_operand:SI 3 "immediate_operand" "s")))))] 9982 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" 9983 "{l|lwz} %0,%2-%3(%1)" 9984 [(set_attr "type" "load")]) 9985 9986(define_insn "load_macho_picbase" 9987 [(set (match_operand:SI 0 "register_operand" "=l") 9988 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 9989 UNSPEC_LD_MPIC))] 9990 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" 9991 "bcl 20,31,%1\\n%1:" 9992 [(set_attr "type" "branch") 9993 (set_attr "length" "4")]) 9994 9995(define_insn "macho_correct_pic" 9996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9997 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") 9998 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s") 9999 (match_operand:SI 3 "immediate_operand" "s")] 10000 UNSPEC_MPIC_CORRECT)))] 10001 "DEFAULT_ABI == ABI_DARWIN" 10002 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)" 10003 [(set_attr "length" "8")]) 10004 10005;; If the TOC is shared over a translation unit, as happens with all 10006;; the kinds of PIC that we support, we need to restore the TOC 10007;; pointer only when jumping over units of translation. 10008;; On Darwin, we need to reload the picbase. 10009 10010(define_expand "builtin_setjmp_receiver" 10011 [(use (label_ref (match_operand 0 "" "")))] 10012 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) 10013 || (TARGET_TOC && TARGET_MINIMAL_TOC) 10014 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" 10015 " 10016{ 10017#if TARGET_MACHO 10018 if (DEFAULT_ABI == ABI_DARWIN) 10019 { 10020 const char *picbase = machopic_function_base_name (); 10021 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); 10022 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); 10023 rtx tmplabrtx; 10024 char tmplab[20]; 10025 10026 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", 10027 CODE_LABEL_NUMBER (operands[0])); 10028 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); 10029 10030 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); 10031 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); 10032 } 10033 else 10034#endif 10035 rs6000_emit_load_toc_table (FALSE); 10036 DONE; 10037}") 10038 10039;; A function pointer under AIX is a pointer to a data area whose first word 10040;; contains the actual address of the function, whose second word contains a 10041;; pointer to its TOC, and whose third word contains a value to place in the 10042;; static chain register (r11). Note that if we load the static chain, our 10043;; "trampoline" need not have any executable code. 10044 10045(define_expand "call_indirect_aix32" 10046 [(set (match_dup 2) 10047 (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) 10048 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) 10049 (reg:SI 2)) 10050 (set (reg:SI 2) 10051 (mem:SI (plus:SI (match_dup 0) 10052 (const_int 4)))) 10053 (set (reg:SI 11) 10054 (mem:SI (plus:SI (match_dup 0) 10055 (const_int 8)))) 10056 (parallel [(call (mem:SI (match_dup 2)) 10057 (match_operand 1 "" "")) 10058 (use (reg:SI 2)) 10059 (use (reg:SI 11)) 10060 (set (reg:SI 2) 10061 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 10062 (clobber (scratch:SI))])] 10063 "TARGET_32BIT" 10064 " 10065{ operands[2] = gen_reg_rtx (SImode); }") 10066 10067(define_expand "call_indirect_aix64" 10068 [(set (match_dup 2) 10069 (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) 10070 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) 10071 (reg:DI 2)) 10072 (set (reg:DI 2) 10073 (mem:DI (plus:DI (match_dup 0) 10074 (const_int 8)))) 10075 (set (reg:DI 11) 10076 (mem:DI (plus:DI (match_dup 0) 10077 (const_int 16)))) 10078 (parallel [(call (mem:SI (match_dup 2)) 10079 (match_operand 1 "" "")) 10080 (use (reg:DI 2)) 10081 (use (reg:DI 11)) 10082 (set (reg:DI 2) 10083 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10084 (clobber (scratch:SI))])] 10085 "TARGET_64BIT" 10086 " 10087{ operands[2] = gen_reg_rtx (DImode); }") 10088 10089(define_expand "call_value_indirect_aix32" 10090 [(set (match_dup 3) 10091 (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 10092 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) 10093 (reg:SI 2)) 10094 (set (reg:SI 2) 10095 (mem:SI (plus:SI (match_dup 1) 10096 (const_int 4)))) 10097 (set (reg:SI 11) 10098 (mem:SI (plus:SI (match_dup 1) 10099 (const_int 8)))) 10100 (parallel [(set (match_operand 0 "" "") 10101 (call (mem:SI (match_dup 3)) 10102 (match_operand 2 "" ""))) 10103 (use (reg:SI 2)) 10104 (use (reg:SI 11)) 10105 (set (reg:SI 2) 10106 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 10107 (clobber (scratch:SI))])] 10108 "TARGET_32BIT" 10109 " 10110{ operands[3] = gen_reg_rtx (SImode); }") 10111 10112(define_expand "call_value_indirect_aix64" 10113 [(set (match_dup 3) 10114 (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 10115 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) 10116 (reg:DI 2)) 10117 (set (reg:DI 2) 10118 (mem:DI (plus:DI (match_dup 1) 10119 (const_int 8)))) 10120 (set (reg:DI 11) 10121 (mem:DI (plus:DI (match_dup 1) 10122 (const_int 16)))) 10123 (parallel [(set (match_operand 0 "" "") 10124 (call (mem:SI (match_dup 3)) 10125 (match_operand 2 "" ""))) 10126 (use (reg:DI 2)) 10127 (use (reg:DI 11)) 10128 (set (reg:DI 2) 10129 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10130 (clobber (scratch:SI))])] 10131 "TARGET_64BIT" 10132 " 10133{ operands[3] = gen_reg_rtx (DImode); }") 10134 10135;; Now the definitions for the call and call_value insns 10136(define_expand "call" 10137 [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) 10138 (match_operand 1 "" "")) 10139 (use (match_operand 2 "" "")) 10140 (clobber (scratch:SI))])] 10141 "" 10142 " 10143{ 10144#if TARGET_MACHO 10145 if (MACHOPIC_INDIRECT) 10146 operands[0] = machopic_indirect_call_target (operands[0]); 10147#endif 10148 10149 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) 10150 abort (); 10151 10152 operands[0] = XEXP (operands[0], 0); 10153 10154 if (GET_CODE (operands[0]) != SYMBOL_REF 10155 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) 10156 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) 10157 { 10158 if (INTVAL (operands[2]) & CALL_LONG) 10159 operands[0] = rs6000_longcall_ref (operands[0]); 10160 10161 if (DEFAULT_ABI == ABI_V4 10162 || DEFAULT_ABI == ABI_DARWIN) 10163 operands[0] = force_reg (Pmode, operands[0]); 10164 10165 else if (DEFAULT_ABI == ABI_AIX) 10166 { 10167 /* AIX function pointers are really pointers to a three word 10168 area. */ 10169 emit_call_insn (TARGET_32BIT 10170 ? gen_call_indirect_aix32 (force_reg (SImode, 10171 operands[0]), 10172 operands[1]) 10173 : gen_call_indirect_aix64 (force_reg (DImode, 10174 operands[0]), 10175 operands[1])); 10176 DONE; 10177 } 10178 else 10179 abort (); 10180 } 10181}") 10182 10183(define_expand "call_value" 10184 [(parallel [(set (match_operand 0 "" "") 10185 (call (mem:SI (match_operand 1 "address_operand" "")) 10186 (match_operand 2 "" ""))) 10187 (use (match_operand 3 "" "")) 10188 (clobber (scratch:SI))])] 10189 "" 10190 " 10191{ 10192#if TARGET_MACHO 10193 if (MACHOPIC_INDIRECT) 10194 operands[1] = machopic_indirect_call_target (operands[1]); 10195#endif 10196 10197 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) 10198 abort (); 10199 10200 operands[1] = XEXP (operands[1], 0); 10201 10202 if (GET_CODE (operands[1]) != SYMBOL_REF 10203 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) 10204 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) 10205 { 10206 if (INTVAL (operands[3]) & CALL_LONG) 10207 operands[1] = rs6000_longcall_ref (operands[1]); 10208 10209 if (DEFAULT_ABI == ABI_V4 10210 || DEFAULT_ABI == ABI_DARWIN) 10211 operands[1] = force_reg (Pmode, operands[1]); 10212 10213 else if (DEFAULT_ABI == ABI_AIX) 10214 { 10215 /* AIX function pointers are really pointers to a three word 10216 area. */ 10217 emit_call_insn (TARGET_32BIT 10218 ? gen_call_value_indirect_aix32 (operands[0], 10219 force_reg (SImode, 10220 operands[1]), 10221 operands[2]) 10222 : gen_call_value_indirect_aix64 (operands[0], 10223 force_reg (DImode, 10224 operands[1]), 10225 operands[2])); 10226 DONE; 10227 } 10228 else 10229 abort (); 10230 } 10231}") 10232 10233;; Call to function in current module. No TOC pointer reload needed. 10234;; Operand2 is nonzero if we are using the V.4 calling sequence and 10235;; either the function was not prototyped, or it was prototyped as a 10236;; variable argument function. It is > 0 if FP registers were passed 10237;; and < 0 if they were not. 10238 10239(define_insn "*call_local32" 10240 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) 10241 (match_operand 1 "" "g,g")) 10242 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10243 (clobber (match_scratch:SI 3 "=l,l"))] 10244 "(INTVAL (operands[2]) & CALL_LONG) == 0" 10245 "* 10246{ 10247 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10248 output_asm_insn (\"crxor 6,6,6\", operands); 10249 10250 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10251 output_asm_insn (\"creqv 6,6,6\", operands); 10252 10253 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; 10254}" 10255 [(set_attr "type" "branch") 10256 (set_attr "length" "4,8")]) 10257 10258(define_insn "*call_local64" 10259 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) 10260 (match_operand 1 "" "g,g")) 10261 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10262 (clobber (match_scratch:SI 3 "=l,l"))] 10263 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" 10264 "* 10265{ 10266 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10267 output_asm_insn (\"crxor 6,6,6\", operands); 10268 10269 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10270 output_asm_insn (\"creqv 6,6,6\", operands); 10271 10272 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; 10273}" 10274 [(set_attr "type" "branch") 10275 (set_attr "length" "4,8")]) 10276 10277(define_insn "*call_value_local32" 10278 [(set (match_operand 0 "" "") 10279 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) 10280 (match_operand 2 "" "g,g"))) 10281 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10282 (clobber (match_scratch:SI 4 "=l,l"))] 10283 "(INTVAL (operands[3]) & CALL_LONG) == 0" 10284 "* 10285{ 10286 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10287 output_asm_insn (\"crxor 6,6,6\", operands); 10288 10289 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10290 output_asm_insn (\"creqv 6,6,6\", operands); 10291 10292 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; 10293}" 10294 [(set_attr "type" "branch") 10295 (set_attr "length" "4,8")]) 10296 10297 10298(define_insn "*call_value_local64" 10299 [(set (match_operand 0 "" "") 10300 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) 10301 (match_operand 2 "" "g,g"))) 10302 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10303 (clobber (match_scratch:SI 4 "=l,l"))] 10304 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" 10305 "* 10306{ 10307 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10308 output_asm_insn (\"crxor 6,6,6\", operands); 10309 10310 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10311 output_asm_insn (\"creqv 6,6,6\", operands); 10312 10313 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; 10314}" 10315 [(set_attr "type" "branch") 10316 (set_attr "length" "4,8")]) 10317 10318;; Call to function which may be in another module. Restore the TOC 10319;; pointer (r2) after the call unless this is System V. 10320;; Operand2 is nonzero if we are using the V.4 calling sequence and 10321;; either the function was not prototyped, or it was prototyped as a 10322;; variable argument function. It is > 0 if FP registers were passed 10323;; and < 0 if they were not. 10324 10325(define_insn "*call_indirect_nonlocal_aix32" 10326 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) 10327 (match_operand 1 "" "g")) 10328 (use (reg:SI 2)) 10329 (use (reg:SI 11)) 10330 (set (reg:SI 2) 10331 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 10332 (clobber (match_scratch:SI 2 "=l"))] 10333 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" 10334 "b%T0l\;{l|lwz} 2,20(1)" 10335 [(set_attr "type" "jmpreg") 10336 (set_attr "length" "8")]) 10337 10338(define_insn "*call_nonlocal_aix32" 10339 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) 10340 (match_operand 1 "" "g")) 10341 (use (match_operand:SI 2 "immediate_operand" "O")) 10342 (clobber (match_scratch:SI 3 "=l"))] 10343 "TARGET_32BIT 10344 && DEFAULT_ABI == ABI_AIX 10345 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10346 "bl %z0\;%." 10347 [(set_attr "type" "branch") 10348 (set_attr "length" "8")]) 10349 10350(define_insn "*call_indirect_nonlocal_aix64" 10351 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) 10352 (match_operand 1 "" "g")) 10353 (use (reg:DI 2)) 10354 (use (reg:DI 11)) 10355 (set (reg:DI 2) 10356 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10357 (clobber (match_scratch:SI 2 "=l"))] 10358 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" 10359 "b%T0l\;ld 2,40(1)" 10360 [(set_attr "type" "jmpreg") 10361 (set_attr "length" "8")]) 10362 10363(define_insn "*call_nonlocal_aix64" 10364 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) 10365 (match_operand 1 "" "g")) 10366 (use (match_operand:SI 2 "immediate_operand" "O")) 10367 (clobber (match_scratch:SI 3 "=l"))] 10368 "TARGET_64BIT 10369 && DEFAULT_ABI == ABI_AIX 10370 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10371 "bl %z0\;%." 10372 [(set_attr "type" "branch") 10373 (set_attr "length" "8")]) 10374 10375(define_insn "*call_value_indirect_nonlocal_aix32" 10376 [(set (match_operand 0 "" "") 10377 (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) 10378 (match_operand 2 "" "g"))) 10379 (use (reg:SI 2)) 10380 (use (reg:SI 11)) 10381 (set (reg:SI 2) 10382 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 10383 (clobber (match_scratch:SI 3 "=l"))] 10384 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" 10385 "b%T1l\;{l|lwz} 2,20(1)" 10386 [(set_attr "type" "jmpreg") 10387 (set_attr "length" "8")]) 10388 10389(define_insn "*call_value_nonlocal_aix32" 10390 [(set (match_operand 0 "" "") 10391 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) 10392 (match_operand 2 "" "g"))) 10393 (use (match_operand:SI 3 "immediate_operand" "O")) 10394 (clobber (match_scratch:SI 4 "=l"))] 10395 "TARGET_32BIT 10396 && DEFAULT_ABI == ABI_AIX 10397 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10398 "bl %z1\;%." 10399 [(set_attr "type" "branch") 10400 (set_attr "length" "8")]) 10401 10402(define_insn "*call_value_indirect_nonlocal_aix64" 10403 [(set (match_operand 0 "" "") 10404 (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) 10405 (match_operand 2 "" "g"))) 10406 (use (reg:DI 2)) 10407 (use (reg:DI 11)) 10408 (set (reg:DI 2) 10409 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10410 (clobber (match_scratch:SI 3 "=l"))] 10411 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" 10412 "b%T1l\;ld 2,40(1)" 10413 [(set_attr "type" "jmpreg") 10414 (set_attr "length" "8")]) 10415 10416(define_insn "*call_value_nonlocal_aix64" 10417 [(set (match_operand 0 "" "") 10418 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) 10419 (match_operand 2 "" "g"))) 10420 (use (match_operand:SI 3 "immediate_operand" "O")) 10421 (clobber (match_scratch:SI 4 "=l"))] 10422 "TARGET_64BIT 10423 && DEFAULT_ABI == ABI_AIX 10424 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10425 "bl %z1\;%." 10426 [(set_attr "type" "branch") 10427 (set_attr "length" "8")]) 10428 10429;; A function pointer under System V is just a normal pointer 10430;; operands[0] is the function pointer 10431;; operands[1] is the stack size to clean up 10432;; operands[2] is the value FUNCTION_ARG returns for the VOID argument 10433;; which indicates how to set cr1 10434 10435(define_insn "*call_indirect_nonlocal_sysv" 10436 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) 10437 (match_operand 1 "" "g,g")) 10438 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10439 (clobber (match_scratch:SI 3 "=l,l"))] 10440 "DEFAULT_ABI == ABI_V4 10441 || DEFAULT_ABI == ABI_DARWIN" 10442{ 10443 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10444 output_asm_insn ("crxor 6,6,6", operands); 10445 10446 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10447 output_asm_insn ("creqv 6,6,6", operands); 10448 10449 return "b%T0l"; 10450} 10451 [(set_attr "type" "jmpreg,jmpreg") 10452 (set_attr "length" "4,8")]) 10453 10454(define_insn "*call_nonlocal_sysv" 10455 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) 10456 (match_operand 1 "" "g,g")) 10457 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10458 (clobber (match_scratch:SI 3 "=l,l"))] 10459 "(DEFAULT_ABI == ABI_DARWIN 10460 || (DEFAULT_ABI == ABI_V4 10461 && (INTVAL (operands[2]) & CALL_LONG) == 0))" 10462{ 10463 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10464 output_asm_insn ("crxor 6,6,6", operands); 10465 10466 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10467 output_asm_insn ("creqv 6,6,6", operands); 10468 10469#if TARGET_MACHO 10470 return output_call(insn, operands, 0, 2); 10471#else 10472 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; 10473#endif 10474} 10475 [(set_attr "type" "branch,branch") 10476 (set_attr "length" "4,8")]) 10477 10478(define_insn "*call_value_indirect_nonlocal_sysv" 10479 [(set (match_operand 0 "" "") 10480 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) 10481 (match_operand 2 "" "g,g"))) 10482 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10483 (clobber (match_scratch:SI 4 "=l,l"))] 10484 "DEFAULT_ABI == ABI_V4 10485 || DEFAULT_ABI == ABI_DARWIN" 10486{ 10487 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10488 output_asm_insn ("crxor 6,6,6", operands); 10489 10490 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10491 output_asm_insn ("creqv 6,6,6", operands); 10492 10493 return "b%T1l"; 10494} 10495 [(set_attr "type" "jmpreg,jmpreg") 10496 (set_attr "length" "4,8")]) 10497 10498(define_insn "*call_value_nonlocal_sysv" 10499 [(set (match_operand 0 "" "") 10500 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) 10501 (match_operand 2 "" "g,g"))) 10502 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10503 (clobber (match_scratch:SI 4 "=l,l"))] 10504 "(DEFAULT_ABI == ABI_DARWIN 10505 || (DEFAULT_ABI == ABI_V4 10506 && (INTVAL (operands[3]) & CALL_LONG) == 0))" 10507{ 10508 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10509 output_asm_insn ("crxor 6,6,6", operands); 10510 10511 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10512 output_asm_insn ("creqv 6,6,6", operands); 10513 10514#if TARGET_MACHO 10515 return output_call(insn, operands, 1, 3); 10516#else 10517 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; 10518#endif 10519} 10520 [(set_attr "type" "branch,branch") 10521 (set_attr "length" "4,8")]) 10522 10523;; Call subroutine returning any type. 10524(define_expand "untyped_call" 10525 [(parallel [(call (match_operand 0 "" "") 10526 (const_int 0)) 10527 (match_operand 1 "" "") 10528 (match_operand 2 "" "")])] 10529 "" 10530 " 10531{ 10532 int i; 10533 10534 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); 10535 10536 for (i = 0; i < XVECLEN (operands[2], 0); i++) 10537 { 10538 rtx set = XVECEXP (operands[2], 0, i); 10539 emit_move_insn (SET_DEST (set), SET_SRC (set)); 10540 } 10541 10542 /* The optimizer does not know that the call sets the function value 10543 registers we stored in the result block. We avoid problems by 10544 claiming that all hard registers are used and clobbered at this 10545 point. */ 10546 emit_insn (gen_blockage ()); 10547 10548 DONE; 10549}") 10550 10551;; sibling call patterns 10552(define_expand "sibcall" 10553 [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) 10554 (match_operand 1 "" "")) 10555 (use (match_operand 2 "" "")) 10556 (use (match_operand 3 "" "")) 10557 (return)])] 10558 "" 10559 " 10560{ 10561#if TARGET_MACHO 10562 if (MACHOPIC_INDIRECT) 10563 operands[0] = machopic_indirect_call_target (operands[0]); 10564#endif 10565 10566 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) 10567 abort (); 10568 10569 operands[0] = XEXP (operands[0], 0); 10570 operands[3] = gen_reg_rtx (SImode); 10571 10572}") 10573 10574;; this and similar patterns must be marked as using LR, otherwise 10575;; dataflow will try to delete the store into it. This is true 10576;; even when the actual reg to jump to is in CTR, when LR was 10577;; saved and restored around the PIC-setting BCL. 10578(define_insn "*sibcall_local32" 10579 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) 10580 (match_operand 1 "" "g,g")) 10581 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10582 (use (match_operand:SI 3 "register_operand" "l,l")) 10583 (return)] 10584 "(INTVAL (operands[2]) & CALL_LONG) == 0" 10585 "* 10586{ 10587 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10588 output_asm_insn (\"crxor 6,6,6\", operands); 10589 10590 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10591 output_asm_insn (\"creqv 6,6,6\", operands); 10592 10593 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; 10594}" 10595 [(set_attr "type" "branch") 10596 (set_attr "length" "4,8")]) 10597 10598(define_insn "*sibcall_local64" 10599 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) 10600 (match_operand 1 "" "g,g")) 10601 (use (match_operand:SI 2 "immediate_operand" "O,n")) 10602 (use (match_operand:SI 3 "register_operand" "l,l")) 10603 (return)] 10604 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" 10605 "* 10606{ 10607 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10608 output_asm_insn (\"crxor 6,6,6\", operands); 10609 10610 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10611 output_asm_insn (\"creqv 6,6,6\", operands); 10612 10613 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; 10614}" 10615 [(set_attr "type" "branch") 10616 (set_attr "length" "4,8")]) 10617 10618(define_insn "*sibcall_value_local32" 10619 [(set (match_operand 0 "" "") 10620 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) 10621 (match_operand 2 "" "g,g"))) 10622 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10623 (use (match_operand:SI 4 "register_operand" "l,l")) 10624 (return)] 10625 "(INTVAL (operands[3]) & CALL_LONG) == 0" 10626 "* 10627{ 10628 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10629 output_asm_insn (\"crxor 6,6,6\", operands); 10630 10631 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10632 output_asm_insn (\"creqv 6,6,6\", operands); 10633 10634 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; 10635}" 10636 [(set_attr "type" "branch") 10637 (set_attr "length" "4,8")]) 10638 10639 10640(define_insn "*sibcall_value_local64" 10641 [(set (match_operand 0 "" "") 10642 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) 10643 (match_operand 2 "" "g,g"))) 10644 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10645 (use (match_operand:SI 4 "register_operand" "l,l")) 10646 (return)] 10647 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" 10648 "* 10649{ 10650 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10651 output_asm_insn (\"crxor 6,6,6\", operands); 10652 10653 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10654 output_asm_insn (\"creqv 6,6,6\", operands); 10655 10656 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; 10657}" 10658 [(set_attr "type" "branch") 10659 (set_attr "length" "4,8")]) 10660 10661(define_insn "*sibcall_nonlocal_aix32" 10662 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) 10663 (match_operand 1 "" "g")) 10664 (use (match_operand:SI 2 "immediate_operand" "O")) 10665 (use (match_operand:SI 3 "register_operand" "l")) 10666 (return)] 10667 "TARGET_32BIT 10668 && DEFAULT_ABI == ABI_AIX 10669 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10670 "b %z0" 10671 [(set_attr "type" "branch") 10672 (set_attr "length" "4")]) 10673 10674(define_insn "*sibcall_nonlocal_aix64" 10675 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) 10676 (match_operand 1 "" "g")) 10677 (use (match_operand:SI 2 "immediate_operand" "O")) 10678 (use (match_operand:SI 3 "register_operand" "l")) 10679 (return)] 10680 "TARGET_64BIT 10681 && DEFAULT_ABI == ABI_AIX 10682 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10683 "b %z0" 10684 [(set_attr "type" "branch") 10685 (set_attr "length" "4")]) 10686 10687(define_insn "*sibcall_value_nonlocal_aix32" 10688 [(set (match_operand 0 "" "") 10689 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) 10690 (match_operand 2 "" "g"))) 10691 (use (match_operand:SI 3 "immediate_operand" "O")) 10692 (use (match_operand:SI 4 "register_operand" "l")) 10693 (return)] 10694 "TARGET_32BIT 10695 && DEFAULT_ABI == ABI_AIX 10696 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10697 "b %z1" 10698 [(set_attr "type" "branch") 10699 (set_attr "length" "4")]) 10700 10701(define_insn "*sibcall_value_nonlocal_aix64" 10702 [(set (match_operand 0 "" "") 10703 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) 10704 (match_operand 2 "" "g"))) 10705 (use (match_operand:SI 3 "immediate_operand" "O")) 10706 (use (match_operand:SI 4 "register_operand" "l")) 10707 (return)] 10708 "TARGET_64BIT 10709 && DEFAULT_ABI == ABI_AIX 10710 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10711 "b %z1" 10712 [(set_attr "type" "branch") 10713 (set_attr "length" "4")]) 10714 10715(define_insn "*sibcall_nonlocal_sysv" 10716 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) 10717 (match_operand 1 "" "")) 10718 (use (match_operand 2 "immediate_operand" "O,n")) 10719 (use (match_operand:SI 3 "register_operand" "l,l")) 10720 (return)] 10721 "(DEFAULT_ABI == ABI_DARWIN 10722 || DEFAULT_ABI == ABI_V4) 10723 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10724 "* 10725{ 10726 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10727 output_asm_insn (\"crxor 6,6,6\", operands); 10728 10729 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10730 output_asm_insn (\"creqv 6,6,6\", operands); 10731 10732 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; 10733}" 10734 [(set_attr "type" "branch,branch") 10735 (set_attr "length" "4,8")]) 10736 10737(define_expand "sibcall_value" 10738 [(parallel [(set (match_operand 0 "register_operand" "") 10739 (call (mem:SI (match_operand 1 "address_operand" "")) 10740 (match_operand 2 "" ""))) 10741 (use (match_operand 3 "" "")) 10742 (use (match_operand 4 "" "")) 10743 (return)])] 10744 "" 10745 " 10746{ 10747#if TARGET_MACHO 10748 if (MACHOPIC_INDIRECT) 10749 operands[1] = machopic_indirect_call_target (operands[1]); 10750#endif 10751 10752 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) 10753 abort (); 10754 10755 operands[1] = XEXP (operands[1], 0); 10756 operands[4] = gen_reg_rtx (SImode); 10757 10758}") 10759 10760(define_insn "*sibcall_value_nonlocal_sysv" 10761 [(set (match_operand 0 "" "") 10762 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) 10763 (match_operand 2 "" ""))) 10764 (use (match_operand:SI 3 "immediate_operand" "O,n")) 10765 (use (match_operand:SI 4 "register_operand" "l,l")) 10766 (return)] 10767 "(DEFAULT_ABI == ABI_DARWIN 10768 || DEFAULT_ABI == ABI_V4) 10769 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10770 "* 10771{ 10772 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10773 output_asm_insn (\"crxor 6,6,6\", operands); 10774 10775 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10776 output_asm_insn (\"creqv 6,6,6\", operands); 10777 10778 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; 10779}" 10780 [(set_attr "type" "branch,branch") 10781 (set_attr "length" "4,8")]) 10782 10783(define_expand "sibcall_epilogue" 10784 [(use (const_int 0))] 10785 "TARGET_SCHED_PROLOG" 10786 " 10787{ 10788 rs6000_emit_epilogue (TRUE); 10789 DONE; 10790}") 10791 10792;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 10793;; all of memory. This blocks insns from being moved across this point. 10794 10795(define_insn "blockage" 10796 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] 10797 "" 10798 "") 10799 10800;; Compare insns are next. Note that the RS/6000 has two types of compares, 10801;; signed & unsigned, and one type of branch. 10802;; 10803;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc 10804;; insns, and branches. We store the operands of compares until we see 10805;; how it is used. 10806(define_expand "cmpsi" 10807 [(set (cc0) 10808 (compare (match_operand:SI 0 "gpc_reg_operand" "") 10809 (match_operand:SI 1 "reg_or_short_operand" "")))] 10810 "" 10811 " 10812{ 10813 /* Take care of the possibility that operands[1] might be negative but 10814 this might be a logical operation. That insn doesn't exist. */ 10815 if (GET_CODE (operands[1]) == CONST_INT 10816 && INTVAL (operands[1]) < 0) 10817 operands[1] = force_reg (SImode, operands[1]); 10818 10819 rs6000_compare_op0 = operands[0]; 10820 rs6000_compare_op1 = operands[1]; 10821 rs6000_compare_fp_p = 0; 10822 DONE; 10823}") 10824 10825(define_expand "cmpdi" 10826 [(set (cc0) 10827 (compare (match_operand:DI 0 "gpc_reg_operand" "") 10828 (match_operand:DI 1 "reg_or_short_operand" "")))] 10829 "TARGET_POWERPC64" 10830 " 10831{ 10832 /* Take care of the possibility that operands[1] might be negative but 10833 this might be a logical operation. That insn doesn't exist. */ 10834 if (GET_CODE (operands[1]) == CONST_INT 10835 && INTVAL (operands[1]) < 0) 10836 operands[1] = force_reg (DImode, operands[1]); 10837 10838 rs6000_compare_op0 = operands[0]; 10839 rs6000_compare_op1 = operands[1]; 10840 rs6000_compare_fp_p = 0; 10841 DONE; 10842}") 10843 10844(define_expand "cmpsf" 10845 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") 10846 (match_operand:SF 1 "gpc_reg_operand" "")))] 10847 "TARGET_HARD_FLOAT" 10848 " 10849{ 10850 rs6000_compare_op0 = operands[0]; 10851 rs6000_compare_op1 = operands[1]; 10852 rs6000_compare_fp_p = 1; 10853 DONE; 10854}") 10855 10856(define_expand "cmpdf" 10857 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") 10858 (match_operand:DF 1 "gpc_reg_operand" "")))] 10859 "TARGET_HARD_FLOAT && TARGET_FPRS" 10860 " 10861{ 10862 rs6000_compare_op0 = operands[0]; 10863 rs6000_compare_op1 = operands[1]; 10864 rs6000_compare_fp_p = 1; 10865 DONE; 10866}") 10867 10868(define_expand "cmptf" 10869 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") 10870 (match_operand:TF 1 "gpc_reg_operand" "")))] 10871 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) 10872 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 10873 " 10874{ 10875 rs6000_compare_op0 = operands[0]; 10876 rs6000_compare_op1 = operands[1]; 10877 rs6000_compare_fp_p = 1; 10878 DONE; 10879}") 10880 10881(define_expand "beq" 10882 [(use (match_operand 0 "" ""))] 10883 "" 10884 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") 10885 10886(define_expand "bne" 10887 [(use (match_operand 0 "" ""))] 10888 "" 10889 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") 10890 10891(define_expand "bge" 10892 [(use (match_operand 0 "" ""))] 10893 "" 10894 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") 10895 10896(define_expand "bgt" 10897 [(use (match_operand 0 "" ""))] 10898 "" 10899 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") 10900 10901(define_expand "ble" 10902 [(use (match_operand 0 "" ""))] 10903 "" 10904 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") 10905 10906(define_expand "blt" 10907 [(use (match_operand 0 "" ""))] 10908 "" 10909 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") 10910 10911(define_expand "bgeu" 10912 [(use (match_operand 0 "" ""))] 10913 "" 10914 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") 10915 10916(define_expand "bgtu" 10917 [(use (match_operand 0 "" ""))] 10918 "" 10919 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") 10920 10921(define_expand "bleu" 10922 [(use (match_operand 0 "" ""))] 10923 "" 10924 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") 10925 10926(define_expand "bltu" 10927 [(use (match_operand 0 "" ""))] 10928 "" 10929 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") 10930 10931(define_expand "bunordered" 10932 [(use (match_operand 0 "" ""))] 10933 "" 10934 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") 10935 10936(define_expand "bordered" 10937 [(use (match_operand 0 "" ""))] 10938 "" 10939 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") 10940 10941(define_expand "buneq" 10942 [(use (match_operand 0 "" ""))] 10943 "" 10944 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") 10945 10946(define_expand "bunge" 10947 [(use (match_operand 0 "" ""))] 10948 "" 10949 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") 10950 10951(define_expand "bungt" 10952 [(use (match_operand 0 "" ""))] 10953 "" 10954 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") 10955 10956(define_expand "bunle" 10957 [(use (match_operand 0 "" ""))] 10958 "" 10959 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") 10960 10961(define_expand "bunlt" 10962 [(use (match_operand 0 "" ""))] 10963 "" 10964 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") 10965 10966(define_expand "bltgt" 10967 [(use (match_operand 0 "" ""))] 10968 "" 10969 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") 10970 10971;; For SNE, we would prefer that the xor/abs sequence be used for integers. 10972;; For SEQ, likewise, except that comparisons with zero should be done 10973;; with an scc insns. However, due to the order that combine see the 10974;; resulting insns, we must, in fact, allow SEQ for integers. Fail in 10975;; the cases we don't want to handle. 10976(define_expand "seq" 10977 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10978 "" 10979 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") 10980 10981(define_expand "sne" 10982 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10983 "" 10984 " 10985{ 10986 if (! rs6000_compare_fp_p) 10987 FAIL; 10988 10989 rs6000_emit_sCOND (NE, operands[0]); 10990 DONE; 10991}") 10992 10993;; A >= 0 is best done the portable way for A an integer. 10994(define_expand "sge" 10995 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10996 "" 10997 " 10998{ 10999 if (! rs6000_compare_fp_p 11000 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) 11001 FAIL; 11002 11003 rs6000_emit_sCOND (GE, operands[0]); 11004 DONE; 11005}") 11006 11007;; A > 0 is best done using the portable sequence, so fail in that case. 11008(define_expand "sgt" 11009 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11010 "" 11011 " 11012{ 11013 if (! rs6000_compare_fp_p 11014 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) 11015 FAIL; 11016 11017 rs6000_emit_sCOND (GT, operands[0]); 11018 DONE; 11019}") 11020 11021;; A <= 0 is best done the portable way for A an integer. 11022(define_expand "sle" 11023 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11024 "" 11025 " 11026{ 11027 if (! rs6000_compare_fp_p 11028 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) 11029 FAIL; 11030 11031 rs6000_emit_sCOND (LE, operands[0]); 11032 DONE; 11033}") 11034 11035;; A < 0 is best done in the portable way for A an integer. 11036(define_expand "slt" 11037 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11038 "" 11039 " 11040{ 11041 if (! rs6000_compare_fp_p 11042 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) 11043 FAIL; 11044 11045 rs6000_emit_sCOND (LT, operands[0]); 11046 DONE; 11047}") 11048 11049(define_expand "sgeu" 11050 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11051 "" 11052 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") 11053 11054(define_expand "sgtu" 11055 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11056 "" 11057 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") 11058 11059(define_expand "sleu" 11060 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11061 "" 11062 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") 11063 11064(define_expand "sltu" 11065 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11066 "" 11067 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") 11068 11069(define_expand "sunordered" 11070 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11071 "" 11072 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") 11073 11074(define_expand "sordered" 11075 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11076 "" 11077 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") 11078 11079(define_expand "suneq" 11080 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11081 "" 11082 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") 11083 11084(define_expand "sunge" 11085 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11086 "" 11087 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") 11088 11089(define_expand "sungt" 11090 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11091 "" 11092 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") 11093 11094(define_expand "sunle" 11095 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11096 "" 11097 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") 11098 11099(define_expand "sunlt" 11100 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11101 "" 11102 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") 11103 11104(define_expand "sltgt" 11105 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 11106 "" 11107 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") 11108 11109 11110;; Here are the actual compare insns. 11111(define_insn "*cmpsi_internal1" 11112 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 11113 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 11114 (match_operand:SI 2 "reg_or_short_operand" "rI")))] 11115 "" 11116 "{cmp%I2|cmpw%I2} %0,%1,%2" 11117 [(set_attr "type" "cmp")]) 11118 11119(define_insn "*cmpdi_internal1" 11120 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 11121 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") 11122 (match_operand:DI 2 "reg_or_short_operand" "rI")))] 11123 "TARGET_POWERPC64" 11124 "cmpd%I2 %0,%1,%2" 11125 [(set_attr "type" "cmp")]) 11126 11127;; If we are comparing a register for equality with a large constant, 11128;; we can do this with an XOR followed by a compare. But we need a scratch 11129;; register for the result of the XOR. 11130 11131(define_split 11132 [(set (match_operand:CC 0 "cc_reg_operand" "") 11133 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 11134 (match_operand:SI 2 "non_short_cint_operand" ""))) 11135 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 11136 "find_single_use (operands[0], insn, 0) 11137 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ 11138 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" 11139 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) 11140 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] 11141 " 11142{ 11143 /* Get the constant we are comparing against, C, and see what it looks like 11144 sign-extended to 16 bits. Then see what constant could be XOR'ed 11145 with C to get the sign-extended value. */ 11146 11147 HOST_WIDE_INT c = INTVAL (operands[2]); 11148 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; 11149 HOST_WIDE_INT xorv = c ^ sextc; 11150 11151 operands[4] = GEN_INT (xorv); 11152 operands[5] = GEN_INT (sextc); 11153}") 11154 11155(define_insn "*cmpsi_internal2" 11156 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 11157 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 11158 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] 11159 "" 11160 "{cmpl%I2|cmplw%I2} %0,%1,%b2" 11161 [(set_attr "type" "cmp")]) 11162 11163(define_insn "*cmpdi_internal2" 11164 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 11165 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") 11166 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] 11167 "" 11168 "cmpld%I2 %0,%1,%b2" 11169 [(set_attr "type" "cmp")]) 11170 11171;; The following two insns don't exist as single insns, but if we provide 11172;; them, we can swap an add and compare, which will enable us to overlap more 11173;; of the required delay between a compare and branch. We generate code for 11174;; them by splitting. 11175 11176(define_insn "" 11177 [(set (match_operand:CC 3 "cc_reg_operand" "=y") 11178 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 11179 (match_operand:SI 2 "short_cint_operand" "i"))) 11180 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 11181 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 11182 "" 11183 "#" 11184 [(set_attr "length" "8")]) 11185 11186(define_insn "" 11187 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") 11188 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 11189 (match_operand:SI 2 "u_short_cint_operand" "i"))) 11190 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 11191 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 11192 "" 11193 "#" 11194 [(set_attr "length" "8")]) 11195 11196(define_split 11197 [(set (match_operand:CC 3 "cc_reg_operand" "") 11198 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 11199 (match_operand:SI 2 "short_cint_operand" ""))) 11200 (set (match_operand:SI 0 "gpc_reg_operand" "") 11201 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 11202 "" 11203 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) 11204 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 11205 11206(define_split 11207 [(set (match_operand:CCUNS 3 "cc_reg_operand" "") 11208 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") 11209 (match_operand:SI 2 "u_short_cint_operand" ""))) 11210 (set (match_operand:SI 0 "gpc_reg_operand" "") 11211 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 11212 "" 11213 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) 11214 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 11215 11216(define_insn "*cmpsf_internal1" 11217 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 11218 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") 11219 (match_operand:SF 2 "gpc_reg_operand" "f")))] 11220 "TARGET_HARD_FLOAT && TARGET_FPRS" 11221 "fcmpu %0,%1,%2" 11222 [(set_attr "type" "fpcompare")]) 11223 11224(define_insn "*cmpdf_internal1" 11225 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 11226 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") 11227 (match_operand:DF 2 "gpc_reg_operand" "f")))] 11228 "TARGET_HARD_FLOAT && TARGET_FPRS" 11229 "fcmpu %0,%1,%2" 11230 [(set_attr "type" "fpcompare")]) 11231 11232;; Only need to compare second words if first words equal 11233(define_insn "*cmptf_internal1" 11234 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 11235 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") 11236 (match_operand:TF 2 "gpc_reg_operand" "f")))] 11237 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT 11238 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 11239 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" 11240 [(set_attr "type" "fpcompare") 11241 (set_attr "length" "12")]) 11242 11243(define_insn_and_split "*cmptf_internal2" 11244 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 11245 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") 11246 (match_operand:TF 2 "gpc_reg_operand" "f"))) 11247 (clobber (match_scratch:DF 3 "=f")) 11248 (clobber (match_scratch:DF 4 "=f")) 11249 (clobber (match_scratch:DF 5 "=f")) 11250 (clobber (match_scratch:DF 6 "=f")) 11251 (clobber (match_scratch:DF 7 "=f")) 11252 (clobber (match_scratch:DF 8 "=f")) 11253 (clobber (match_scratch:DF 9 "=f")) 11254 (clobber (match_scratch:DF 10 "=f"))] 11255 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT 11256 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 11257 "#" 11258 "&& reload_completed" 11259 [(set (match_dup 3) (match_dup 13)) 11260 (set (match_dup 4) (match_dup 14)) 11261 (set (match_dup 9) (abs:DF (match_dup 5))) 11262 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3))) 11263 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0)) 11264 (label_ref (match_dup 11)) 11265 (pc))) 11266 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7))) 11267 (set (pc) (label_ref (match_dup 12))) 11268 (match_dup 11) 11269 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7))) 11270 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8))) 11271 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9))) 11272 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4))) 11273 (match_dup 12)] 11274{ 11275 REAL_VALUE_TYPE rv; 11276 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; 11277 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); 11278 11279 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word); 11280 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word); 11281 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word); 11282 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word); 11283 operands[11] = gen_label_rtx (); 11284 operands[12] = gen_label_rtx (); 11285 real_inf (&rv); 11286 operands[13] = force_const_mem (DFmode, 11287 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode)); 11288 operands[14] = force_const_mem (DFmode, 11289 CONST_DOUBLE_FROM_REAL_VALUE (dconst0, 11290 DFmode)); 11291 if (TARGET_TOC) 11292 { 11293 operands[13] = gen_rtx_MEM (DFmode, 11294 create_TOC_reference (XEXP (operands[13], 0))); 11295 operands[14] = gen_rtx_MEM (DFmode, 11296 create_TOC_reference (XEXP (operands[14], 0))); 11297 set_mem_alias_set (operands[13], get_TOC_alias_set ()); 11298 set_mem_alias_set (operands[14], get_TOC_alias_set ()); 11299 RTX_UNCHANGING_P (operands[13]) = 1; 11300 RTX_UNCHANGING_P (operands[14]) = 1; 11301 } 11302}) 11303 11304;; Now we have the scc insns. We can do some combinations because of the 11305;; way the machine works. 11306;; 11307;; Note that this is probably faster if we can put an insn between the 11308;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most 11309;; cases the insns below which don't use an intermediate CR field will 11310;; be used instead. 11311(define_insn "" 11312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11313 (match_operator:SI 1 "scc_comparison_operator" 11314 [(match_operand 2 "cc_reg_operand" "y") 11315 (const_int 0)]))] 11316 "" 11317 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" 11318 [(set (attr "type") 11319 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) 11320 (const_string "mfcrf") 11321 ] 11322 (const_string "mfcr"))) 11323 (set_attr "length" "12")]) 11324 11325;; Same as above, but get the EQ bit. 11326(define_insn "move_from_CR_eq_bit" 11327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11328 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))] 11329 "TARGET_E500" 11330 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1" 11331 [(set_attr "type" "mfcr") 11332 (set_attr "length" "12")]) 11333 11334;; Same as above, but get the OV/ORDERED bit. 11335(define_insn "move_from_CR_ov_bit" 11336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11337 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] 11338 "TARGET_ISEL" 11339 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" 11340 [(set_attr "type" "mfcr") 11341 (set_attr "length" "12")]) 11342 11343(define_insn "" 11344 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11345 (match_operator:DI 1 "scc_comparison_operator" 11346 [(match_operand 2 "cc_reg_operand" "y") 11347 (const_int 0)]))] 11348 "TARGET_POWERPC64" 11349 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" 11350 [(set (attr "type") 11351 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) 11352 (const_string "mfcrf") 11353 ] 11354 (const_string "mfcr"))) 11355 (set_attr "length" "12")]) 11356 11357(define_insn "" 11358 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11359 (compare:CC (match_operator:SI 1 "scc_comparison_operator" 11360 [(match_operand 2 "cc_reg_operand" "y,y") 11361 (const_int 0)]) 11362 (const_int 0))) 11363 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 11364 (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 11365 "TARGET_32BIT" 11366 "@ 11367 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 11368 #" 11369 [(set_attr "type" "delayed_compare") 11370 (set_attr "length" "12,16")]) 11371 11372(define_split 11373 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11374 (compare:CC (match_operator:SI 1 "scc_comparison_operator" 11375 [(match_operand 2 "cc_reg_operand" "") 11376 (const_int 0)]) 11377 (const_int 0))) 11378 (set (match_operand:SI 3 "gpc_reg_operand" "") 11379 (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 11380 "TARGET_32BIT && reload_completed" 11381 [(set (match_dup 3) 11382 (match_op_dup 1 [(match_dup 2) (const_int 0)])) 11383 (set (match_dup 0) 11384 (compare:CC (match_dup 3) 11385 (const_int 0)))] 11386 "") 11387 11388(define_insn "" 11389 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11390 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 11391 [(match_operand 2 "cc_reg_operand" "y") 11392 (const_int 0)]) 11393 (match_operand:SI 3 "const_int_operand" "n")))] 11394 "" 11395 "* 11396{ 11397 int is_bit = ccr_bit (operands[1], 1); 11398 int put_bit = 31 - (INTVAL (operands[3]) & 31); 11399 int count; 11400 11401 if (is_bit >= put_bit) 11402 count = is_bit - put_bit; 11403 else 11404 count = 32 - (put_bit - is_bit); 11405 11406 operands[4] = GEN_INT (count); 11407 operands[5] = GEN_INT (put_bit); 11408 11409 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; 11410}" 11411 [(set (attr "type") 11412 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) 11413 (const_string "mfcrf") 11414 ] 11415 (const_string "mfcr"))) 11416 (set_attr "length" "12")]) 11417 11418(define_insn "" 11419 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11420 (compare:CC 11421 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 11422 [(match_operand 2 "cc_reg_operand" "y,y") 11423 (const_int 0)]) 11424 (match_operand:SI 3 "const_int_operand" "n,n")) 11425 (const_int 0))) 11426 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") 11427 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 11428 (match_dup 3)))] 11429 "" 11430 "* 11431{ 11432 int is_bit = ccr_bit (operands[1], 1); 11433 int put_bit = 31 - (INTVAL (operands[3]) & 31); 11434 int count; 11435 11436 /* Force split for non-cc0 compare. */ 11437 if (which_alternative == 1) 11438 return \"#\"; 11439 11440 if (is_bit >= put_bit) 11441 count = is_bit - put_bit; 11442 else 11443 count = 32 - (put_bit - is_bit); 11444 11445 operands[5] = GEN_INT (count); 11446 operands[6] = GEN_INT (put_bit); 11447 11448 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; 11449}" 11450 [(set_attr "type" "delayed_compare") 11451 (set_attr "length" "12,16")]) 11452 11453(define_split 11454 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11455 (compare:CC 11456 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 11457 [(match_operand 2 "cc_reg_operand" "") 11458 (const_int 0)]) 11459 (match_operand:SI 3 "const_int_operand" "")) 11460 (const_int 0))) 11461 (set (match_operand:SI 4 "gpc_reg_operand" "") 11462 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 11463 (match_dup 3)))] 11464 "reload_completed" 11465 [(set (match_dup 4) 11466 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 11467 (match_dup 3))) 11468 (set (match_dup 0) 11469 (compare:CC (match_dup 4) 11470 (const_int 0)))] 11471 "") 11472 11473;; There is a 3 cycle delay between consecutive mfcr instructions 11474;; so it is useful to combine 2 scc instructions to use only one mfcr. 11475 11476(define_peephole 11477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11478 (match_operator:SI 1 "scc_comparison_operator" 11479 [(match_operand 2 "cc_reg_operand" "y") 11480 (const_int 0)])) 11481 (set (match_operand:SI 3 "gpc_reg_operand" "=r") 11482 (match_operator:SI 4 "scc_comparison_operator" 11483 [(match_operand 5 "cc_reg_operand" "y") 11484 (const_int 0)]))] 11485 "REGNO (operands[2]) != REGNO (operands[5])" 11486 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" 11487 [(set_attr "type" "mfcr") 11488 (set_attr "length" "20")]) 11489 11490(define_peephole 11491 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11492 (match_operator:DI 1 "scc_comparison_operator" 11493 [(match_operand 2 "cc_reg_operand" "y") 11494 (const_int 0)])) 11495 (set (match_operand:DI 3 "gpc_reg_operand" "=r") 11496 (match_operator:DI 4 "scc_comparison_operator" 11497 [(match_operand 5 "cc_reg_operand" "y") 11498 (const_int 0)]))] 11499 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" 11500 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" 11501 [(set_attr "type" "mfcr") 11502 (set_attr "length" "20")]) 11503 11504;; There are some scc insns that can be done directly, without a compare. 11505;; These are faster because they don't involve the communications between 11506;; the FXU and branch units. In fact, we will be replacing all of the 11507;; integer scc insns here or in the portable methods in emit_store_flag. 11508;; 11509;; Also support (neg (scc ..)) since that construct is used to replace 11510;; branches, (plus (scc ..) ..) since that construct is common and 11511;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the 11512;; cases where it is no more expensive than (neg (scc ..)). 11513 11514;; Have reload force a constant into a register for the simple insns that 11515;; otherwise won't accept constants. We do this because it is faster than 11516;; the cmp/mfcr sequence we would otherwise generate. 11517 11518(define_insn "" 11519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 11520 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 11521 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) 11522 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] 11523 "TARGET_32BIT" 11524 "@ 11525 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 11526 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 11527 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 11528 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 11529 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" 11530 [(set_attr "length" "12,8,12,12,12")]) 11531 11532(define_insn "" 11533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") 11534 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") 11535 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) 11536 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] 11537 "TARGET_64BIT" 11538 "@ 11539 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 11540 subfic %3,%1,0\;adde %0,%3,%1 11541 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 11542 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 11543 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" 11544 [(set_attr "length" "12,8,12,12,12")]) 11545 11546(define_insn "" 11547 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 11548 (compare:CC 11549 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 11550 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) 11551 (const_int 0))) 11552 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") 11553 (eq:SI (match_dup 1) (match_dup 2))) 11554 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] 11555 "TARGET_32BIT" 11556 "@ 11557 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 11558 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 11559 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 11560 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 11561 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 11562 # 11563 # 11564 # 11565 # 11566 #" 11567 [(set_attr "type" "compare") 11568 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 11569 11570(define_split 11571 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11572 (compare:CC 11573 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 11574 (match_operand:SI 2 "reg_or_cint_operand" "")) 11575 (const_int 0))) 11576 (set (match_operand:SI 0 "gpc_reg_operand" "") 11577 (eq:SI (match_dup 1) (match_dup 2))) 11578 (clobber (match_scratch:SI 3 ""))] 11579 "TARGET_32BIT && reload_completed" 11580 [(parallel [(set (match_dup 0) 11581 (eq:SI (match_dup 1) (match_dup 2))) 11582 (clobber (match_dup 3))]) 11583 (set (match_dup 4) 11584 (compare:CC (match_dup 0) 11585 (const_int 0)))] 11586 "") 11587 11588(define_insn "" 11589 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 11590 (compare:CC 11591 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 11592 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) 11593 (const_int 0))) 11594 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") 11595 (eq:DI (match_dup 1) (match_dup 2))) 11596 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] 11597 "TARGET_64BIT" 11598 "@ 11599 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 11600 subfic %3,%1,0\;adde. %0,%3,%1 11601 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 11602 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 11603 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 11604 # 11605 # 11606 # 11607 # 11608 #" 11609 [(set_attr "type" "compare") 11610 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 11611 11612(define_split 11613 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11614 (compare:CC 11615 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") 11616 (match_operand:DI 2 "reg_or_cint_operand" "")) 11617 (const_int 0))) 11618 (set (match_operand:DI 0 "gpc_reg_operand" "") 11619 (eq:DI (match_dup 1) (match_dup 2))) 11620 (clobber (match_scratch:DI 3 ""))] 11621 "TARGET_64BIT && reload_completed" 11622 [(parallel [(set (match_dup 0) 11623 (eq:DI (match_dup 1) (match_dup 2))) 11624 (clobber (match_dup 3))]) 11625 (set (match_dup 4) 11626 (compare:CC (match_dup 0) 11627 (const_int 0)))] 11628 "") 11629 11630;; We have insns of the form shown by the first define_insn below. If 11631;; there is something inside the comparison operation, we must split it. 11632(define_split 11633 [(set (match_operand:SI 0 "gpc_reg_operand" "") 11634 (plus:SI (match_operator 1 "comparison_operator" 11635 [(match_operand:SI 2 "" "") 11636 (match_operand:SI 3 11637 "reg_or_cint_operand" "")]) 11638 (match_operand:SI 4 "gpc_reg_operand" ""))) 11639 (clobber (match_operand:SI 5 "register_operand" ""))] 11640 "! gpc_reg_operand (operands[2], SImode)" 11641 [(set (match_dup 5) (match_dup 2)) 11642 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) 11643 (match_dup 4)))]) 11644 11645(define_insn "" 11646 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") 11647 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 11648 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) 11649 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] 11650 "TARGET_32BIT" 11651 "@ 11652 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 11653 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 11654 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 11655 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 11656 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" 11657 [(set_attr "length" "12,8,12,12,12")]) 11658 11659(define_insn "" 11660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 11661 (compare:CC 11662 (plus:SI 11663 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 11664 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) 11665 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) 11666 (const_int 0))) 11667 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] 11668 "TARGET_32BIT" 11669 "@ 11670 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 11671 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 11672 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 11673 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 11674 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 11675 # 11676 # 11677 # 11678 # 11679 #" 11680 [(set_attr "type" "compare") 11681 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 11682 11683(define_split 11684 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11685 (compare:CC 11686 (plus:SI 11687 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 11688 (match_operand:SI 2 "reg_or_cint_operand" "")) 11689 (match_operand:SI 3 "gpc_reg_operand" "")) 11690 (const_int 0))) 11691 (clobber (match_scratch:SI 4 ""))] 11692 "TARGET_32BIT && reload_completed" 11693 [(set (match_dup 4) 11694 (plus:SI (eq:SI (match_dup 1) 11695 (match_dup 2)) 11696 (match_dup 3))) 11697 (set (match_dup 0) 11698 (compare:CC (match_dup 4) 11699 (const_int 0)))] 11700 "") 11701 11702(define_insn "" 11703 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 11704 (compare:CC 11705 (plus:SI 11706 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 11707 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) 11708 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) 11709 (const_int 0))) 11710 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") 11711 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11712 "TARGET_32BIT" 11713 "@ 11714 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 11715 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 11716 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 11717 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 11718 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 11719 # 11720 # 11721 # 11722 # 11723 #" 11724 [(set_attr "type" "compare") 11725 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 11726 11727(define_split 11728 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11729 (compare:CC 11730 (plus:SI 11731 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 11732 (match_operand:SI 2 "reg_or_cint_operand" "")) 11733 (match_operand:SI 3 "gpc_reg_operand" "")) 11734 (const_int 0))) 11735 (set (match_operand:SI 0 "gpc_reg_operand" "") 11736 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11737 "TARGET_32BIT && reload_completed" 11738 [(set (match_dup 0) 11739 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 11740 (set (match_dup 4) 11741 (compare:CC (match_dup 0) 11742 (const_int 0)))] 11743 "") 11744 11745(define_insn "" 11746 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 11747 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 11748 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] 11749 "TARGET_32BIT" 11750 "@ 11751 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 11752 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 11753 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 11754 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 11755 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 11756 [(set_attr "length" "12,8,12,12,12")]) 11757 11758;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, 11759;; since it nabs/sr is just as fast. 11760(define_insn "*ne0" 11761 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 11762 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 11763 (const_int 31))) 11764 (clobber (match_scratch:SI 2 "=&r"))] 11765 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" 11766 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" 11767 [(set_attr "length" "8")]) 11768 11769(define_insn "" 11770 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11771 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) 11772 (const_int 63))) 11773 (clobber (match_scratch:DI 2 "=&r"))] 11774 "TARGET_64BIT" 11775 "addic %2,%1,-1\;subfe %0,%2,%1" 11776 [(set_attr "length" "8")]) 11777 11778;; This is what (plus (ne X (const_int 0)) Y) looks like. 11779(define_insn "" 11780 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11781 (plus:SI (lshiftrt:SI 11782 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 11783 (const_int 31)) 11784 (match_operand:SI 2 "gpc_reg_operand" "r"))) 11785 (clobber (match_scratch:SI 3 "=&r"))] 11786 "TARGET_32BIT" 11787 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" 11788 [(set_attr "length" "8")]) 11789 11790(define_insn "" 11791 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11792 (plus:DI (lshiftrt:DI 11793 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) 11794 (const_int 63)) 11795 (match_operand:DI 2 "gpc_reg_operand" "r"))) 11796 (clobber (match_scratch:DI 3 "=&r"))] 11797 "TARGET_64BIT" 11798 "addic %3,%1,-1\;addze %0,%2" 11799 [(set_attr "length" "8")]) 11800 11801(define_insn "" 11802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11803 (compare:CC 11804 (plus:SI (lshiftrt:SI 11805 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) 11806 (const_int 31)) 11807 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 11808 (const_int 0))) 11809 (clobber (match_scratch:SI 3 "=&r,&r")) 11810 (clobber (match_scratch:SI 4 "=X,&r"))] 11811 "TARGET_32BIT" 11812 "@ 11813 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 11814 #" 11815 [(set_attr "type" "compare") 11816 (set_attr "length" "8,12")]) 11817 11818(define_split 11819 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11820 (compare:CC 11821 (plus:SI (lshiftrt:SI 11822 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 11823 (const_int 31)) 11824 (match_operand:SI 2 "gpc_reg_operand" "")) 11825 (const_int 0))) 11826 (clobber (match_scratch:SI 3 "")) 11827 (clobber (match_scratch:SI 4 ""))] 11828 "TARGET_32BIT && reload_completed" 11829 [(parallel [(set (match_dup 3) 11830 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) 11831 (const_int 31)) 11832 (match_dup 2))) 11833 (clobber (match_dup 4))]) 11834 (set (match_dup 0) 11835 (compare:CC (match_dup 3) 11836 (const_int 0)))] 11837 "") 11838 11839(define_insn "" 11840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11841 (compare:CC 11842 (plus:DI (lshiftrt:DI 11843 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) 11844 (const_int 63)) 11845 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 11846 (const_int 0))) 11847 (clobber (match_scratch:DI 3 "=&r,&r"))] 11848 "TARGET_64BIT" 11849 "@ 11850 addic %3,%1,-1\;addze. %3,%2 11851 #" 11852 [(set_attr "type" "compare") 11853 (set_attr "length" "8,12")]) 11854 11855(define_split 11856 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11857 (compare:CC 11858 (plus:DI (lshiftrt:DI 11859 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 11860 (const_int 63)) 11861 (match_operand:DI 2 "gpc_reg_operand" "")) 11862 (const_int 0))) 11863 (clobber (match_scratch:DI 3 ""))] 11864 "TARGET_64BIT && reload_completed" 11865 [(set (match_dup 3) 11866 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) 11867 (const_int 63)) 11868 (match_dup 2))) 11869 (set (match_dup 0) 11870 (compare:CC (match_dup 3) 11871 (const_int 0)))] 11872 "") 11873 11874(define_insn "" 11875 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 11876 (compare:CC 11877 (plus:SI (lshiftrt:SI 11878 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) 11879 (const_int 31)) 11880 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 11881 (const_int 0))) 11882 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11883 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 11884 (match_dup 2))) 11885 (clobber (match_scratch:SI 3 "=&r,&r"))] 11886 "TARGET_32BIT" 11887 "@ 11888 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 11889 #" 11890 [(set_attr "type" "compare") 11891 (set_attr "length" "8,12")]) 11892 11893(define_split 11894 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11895 (compare:CC 11896 (plus:SI (lshiftrt:SI 11897 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 11898 (const_int 31)) 11899 (match_operand:SI 2 "gpc_reg_operand" "")) 11900 (const_int 0))) 11901 (set (match_operand:SI 0 "gpc_reg_operand" "") 11902 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 11903 (match_dup 2))) 11904 (clobber (match_scratch:SI 3 ""))] 11905 "TARGET_32BIT && reload_completed" 11906 [(parallel [(set (match_dup 0) 11907 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 11908 (match_dup 2))) 11909 (clobber (match_dup 3))]) 11910 (set (match_dup 4) 11911 (compare:CC (match_dup 0) 11912 (const_int 0)))] 11913 "") 11914 11915(define_insn "" 11916 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 11917 (compare:CC 11918 (plus:DI (lshiftrt:DI 11919 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) 11920 (const_int 63)) 11921 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 11922 (const_int 0))) 11923 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 11924 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) 11925 (match_dup 2))) 11926 (clobber (match_scratch:DI 3 "=&r,&r"))] 11927 "TARGET_64BIT" 11928 "@ 11929 addic %3,%1,-1\;addze. %0,%2 11930 #" 11931 [(set_attr "type" "compare") 11932 (set_attr "length" "8,12")]) 11933 11934(define_split 11935 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11936 (compare:CC 11937 (plus:DI (lshiftrt:DI 11938 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 11939 (const_int 63)) 11940 (match_operand:DI 2 "gpc_reg_operand" "")) 11941 (const_int 0))) 11942 (set (match_operand:DI 0 "gpc_reg_operand" "") 11943 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) 11944 (match_dup 2))) 11945 (clobber (match_scratch:DI 3 ""))] 11946 "TARGET_64BIT && reload_completed" 11947 [(parallel [(set (match_dup 0) 11948 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) 11949 (match_dup 2))) 11950 (clobber (match_dup 3))]) 11951 (set (match_dup 4) 11952 (compare:CC (match_dup 0) 11953 (const_int 0)))] 11954 "") 11955 11956(define_insn "" 11957 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11958 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11959 (match_operand:SI 2 "reg_or_short_operand" "r,O"))) 11960 (clobber (match_scratch:SI 3 "=r,X"))] 11961 "TARGET_POWER" 11962 "@ 11963 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 11964 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" 11965 [(set_attr "length" "12")]) 11966 11967(define_insn "" 11968 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 11969 (compare:CC 11970 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 11971 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) 11972 (const_int 0))) 11973 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 11974 (le:SI (match_dup 1) (match_dup 2))) 11975 (clobber (match_scratch:SI 3 "=r,X,r,X"))] 11976 "TARGET_POWER" 11977 "@ 11978 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 11979 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 11980 # 11981 #" 11982 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") 11983 (set_attr "length" "12,12,16,16")]) 11984 11985(define_split 11986 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11987 (compare:CC 11988 (le:SI (match_operand:SI 1 "gpc_reg_operand" "") 11989 (match_operand:SI 2 "reg_or_short_operand" "")) 11990 (const_int 0))) 11991 (set (match_operand:SI 0 "gpc_reg_operand" "") 11992 (le:SI (match_dup 1) (match_dup 2))) 11993 (clobber (match_scratch:SI 3 ""))] 11994 "TARGET_POWER && reload_completed" 11995 [(parallel [(set (match_dup 0) 11996 (le:SI (match_dup 1) (match_dup 2))) 11997 (clobber (match_dup 3))]) 11998 (set (match_dup 4) 11999 (compare:CC (match_dup 0) 12000 (const_int 0)))] 12001 "") 12002 12003(define_insn "" 12004 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12005 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12006 (match_operand:SI 2 "reg_or_short_operand" "r,O")) 12007 (match_operand:SI 3 "gpc_reg_operand" "r,r")))] 12008 "TARGET_POWER" 12009 "@ 12010 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 12011 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" 12012 [(set_attr "length" "12")]) 12013 12014(define_insn "" 12015 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 12016 (compare:CC 12017 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12018 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) 12019 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12020 (const_int 0))) 12021 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 12022 "TARGET_POWER" 12023 "@ 12024 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 12025 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 12026 # 12027 #" 12028 [(set_attr "type" "compare") 12029 (set_attr "length" "12,12,16,16")]) 12030 12031(define_split 12032 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12033 (compare:CC 12034 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") 12035 (match_operand:SI 2 "reg_or_short_operand" "")) 12036 (match_operand:SI 3 "gpc_reg_operand" "")) 12037 (const_int 0))) 12038 (clobber (match_scratch:SI 4 ""))] 12039 "TARGET_POWER && reload_completed" 12040 [(set (match_dup 4) 12041 (plus:SI (le:SI (match_dup 1) (match_dup 2)) 12042 (match_dup 3))) 12043 (set (match_dup 0) 12044 (compare:CC (match_dup 4) 12045 (const_int 0)))] 12046 "") 12047 12048(define_insn "" 12049 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12050 (compare:CC 12051 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12052 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) 12053 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12054 (const_int 0))) 12055 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12056 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12057 "TARGET_POWER" 12058 "@ 12059 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 12060 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 12061 # 12062 #" 12063 [(set_attr "type" "compare") 12064 (set_attr "length" "12,12,16,16")]) 12065 12066(define_split 12067 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12068 (compare:CC 12069 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") 12070 (match_operand:SI 2 "reg_or_short_operand" "")) 12071 (match_operand:SI 3 "gpc_reg_operand" "")) 12072 (const_int 0))) 12073 (set (match_operand:SI 0 "gpc_reg_operand" "") 12074 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12075 "TARGET_POWER && reload_completed" 12076 [(set (match_dup 0) 12077 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12078 (set (match_dup 4) 12079 (compare:CC (match_dup 0) 12080 (const_int 0)))] 12081 "") 12082 12083(define_insn "" 12084 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12085 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12086 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] 12087 "TARGET_POWER" 12088 "@ 12089 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 12090 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" 12091 [(set_attr "length" "12")]) 12092 12093(define_insn "" 12094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12095 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12096 (match_operand:SI 2 "reg_or_short_operand" "rI")))] 12097 "TARGET_32BIT" 12098 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 12099 [(set_attr "length" "12")]) 12100 12101(define_insn "" 12102 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 12103 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") 12104 (match_operand:DI 2 "reg_or_short_operand" "rI")))] 12105 "TARGET_64BIT" 12106 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" 12107 [(set_attr "length" "12")]) 12108 12109(define_insn "" 12110 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12111 (compare:CC 12112 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 12113 (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) 12114 (const_int 0))) 12115 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 12116 (leu:DI (match_dup 1) (match_dup 2)))] 12117 "TARGET_64BIT" 12118 "@ 12119 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 12120 #" 12121 [(set_attr "type" "compare") 12122 (set_attr "length" "12,16")]) 12123 12124(define_split 12125 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12126 (compare:CC 12127 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") 12128 (match_operand:DI 2 "reg_or_short_operand" "")) 12129 (const_int 0))) 12130 (set (match_operand:DI 0 "gpc_reg_operand" "") 12131 (leu:DI (match_dup 1) (match_dup 2)))] 12132 "TARGET_64BIT && reload_completed" 12133 [(set (match_dup 0) 12134 (leu:DI (match_dup 1) (match_dup 2))) 12135 (set (match_dup 3) 12136 (compare:CC (match_dup 0) 12137 (const_int 0)))] 12138 "") 12139 12140(define_insn "" 12141 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12142 (compare:CC 12143 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12144 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12145 (const_int 0))) 12146 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12147 (leu:SI (match_dup 1) (match_dup 2)))] 12148 "TARGET_32BIT" 12149 "@ 12150 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 12151 #" 12152 [(set_attr "type" "compare") 12153 (set_attr "length" "12,16")]) 12154 12155(define_split 12156 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12157 (compare:CC 12158 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12159 (match_operand:SI 2 "reg_or_short_operand" "")) 12160 (const_int 0))) 12161 (set (match_operand:SI 0 "gpc_reg_operand" "") 12162 (leu:SI (match_dup 1) (match_dup 2)))] 12163 "TARGET_32BIT && reload_completed" 12164 [(set (match_dup 0) 12165 (leu:SI (match_dup 1) (match_dup 2))) 12166 (set (match_dup 3) 12167 (compare:CC (match_dup 0) 12168 (const_int 0)))] 12169 "") 12170 12171(define_insn "" 12172 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 12173 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12174 (match_operand:SI 2 "reg_or_short_operand" "rI")) 12175 (match_operand:SI 3 "gpc_reg_operand" "r")))] 12176 "TARGET_32BIT" 12177 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" 12178 [(set_attr "length" "8")]) 12179 12180(define_insn "" 12181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12182 (compare:CC 12183 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12184 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12185 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12186 (const_int 0))) 12187 (clobber (match_scratch:SI 4 "=&r,&r"))] 12188 "TARGET_32BIT" 12189 "@ 12190 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 12191 #" 12192 [(set_attr "type" "compare") 12193 (set_attr "length" "8,12")]) 12194 12195(define_split 12196 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12197 (compare:CC 12198 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12199 (match_operand:SI 2 "reg_or_short_operand" "")) 12200 (match_operand:SI 3 "gpc_reg_operand" "")) 12201 (const_int 0))) 12202 (clobber (match_scratch:SI 4 ""))] 12203 "TARGET_32BIT && reload_completed" 12204 [(set (match_dup 4) 12205 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) 12206 (match_dup 3))) 12207 (set (match_dup 0) 12208 (compare:CC (match_dup 4) 12209 (const_int 0)))] 12210 "") 12211 12212(define_insn "" 12213 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12214 (compare:CC 12215 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12216 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12217 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12218 (const_int 0))) 12219 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12220 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12221 "TARGET_32BIT" 12222 "@ 12223 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 12224 #" 12225 [(set_attr "type" "compare") 12226 (set_attr "length" "8,12")]) 12227 12228(define_split 12229 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12230 (compare:CC 12231 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12232 (match_operand:SI 2 "reg_or_short_operand" "")) 12233 (match_operand:SI 3 "gpc_reg_operand" "")) 12234 (const_int 0))) 12235 (set (match_operand:SI 0 "gpc_reg_operand" "") 12236 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12237 "TARGET_32BIT && reload_completed" 12238 [(set (match_dup 0) 12239 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12240 (set (match_dup 4) 12241 (compare:CC (match_dup 0) 12242 (const_int 0)))] 12243 "") 12244 12245(define_insn "" 12246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12247 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12248 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 12249 "TARGET_32BIT" 12250 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" 12251 [(set_attr "length" "12")]) 12252 12253(define_insn "" 12254 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 12255 (and:SI (neg:SI 12256 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12257 (match_operand:SI 2 "reg_or_short_operand" "rI"))) 12258 (match_operand:SI 3 "gpc_reg_operand" "r")))] 12259 "TARGET_32BIT" 12260 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" 12261 [(set_attr "length" "12")]) 12262 12263(define_insn "" 12264 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12265 (compare:CC 12266 (and:SI (neg:SI 12267 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12268 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) 12269 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12270 (const_int 0))) 12271 (clobber (match_scratch:SI 4 "=&r,&r"))] 12272 "TARGET_32BIT" 12273 "@ 12274 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 12275 #" 12276 [(set_attr "type" "compare") 12277 (set_attr "length" "12,16")]) 12278 12279(define_split 12280 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12281 (compare:CC 12282 (and:SI (neg:SI 12283 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12284 (match_operand:SI 2 "reg_or_short_operand" ""))) 12285 (match_operand:SI 3 "gpc_reg_operand" "")) 12286 (const_int 0))) 12287 (clobber (match_scratch:SI 4 ""))] 12288 "TARGET_32BIT && reload_completed" 12289 [(set (match_dup 4) 12290 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) 12291 (match_dup 3))) 12292 (set (match_dup 0) 12293 (compare:CC (match_dup 4) 12294 (const_int 0)))] 12295 "") 12296 12297(define_insn "" 12298 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12299 (compare:CC 12300 (and:SI (neg:SI 12301 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12302 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) 12303 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12304 (const_int 0))) 12305 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12306 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 12307 "TARGET_32BIT" 12308 "@ 12309 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 12310 #" 12311 [(set_attr "type" "compare") 12312 (set_attr "length" "12,16")]) 12313 12314(define_split 12315 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12316 (compare:CC 12317 (and:SI (neg:SI 12318 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12319 (match_operand:SI 2 "reg_or_short_operand" ""))) 12320 (match_operand:SI 3 "gpc_reg_operand" "")) 12321 (const_int 0))) 12322 (set (match_operand:SI 0 "gpc_reg_operand" "") 12323 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 12324 "TARGET_32BIT && reload_completed" 12325 [(set (match_dup 0) 12326 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) 12327 (match_dup 3))) 12328 (set (match_dup 4) 12329 (compare:CC (match_dup 0) 12330 (const_int 0)))] 12331 "") 12332 12333(define_insn "" 12334 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12335 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12336 (match_operand:SI 2 "reg_or_short_operand" "rI")))] 12337 "TARGET_POWER" 12338 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" 12339 [(set_attr "length" "12")]) 12340 12341(define_insn "" 12342 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12343 (compare:CC 12344 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12345 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12346 (const_int 0))) 12347 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12348 (lt:SI (match_dup 1) (match_dup 2)))] 12349 "TARGET_POWER" 12350 "@ 12351 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 12352 #" 12353 [(set_attr "type" "delayed_compare") 12354 (set_attr "length" "12,16")]) 12355 12356(define_split 12357 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12358 (compare:CC 12359 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12360 (match_operand:SI 2 "reg_or_short_operand" "")) 12361 (const_int 0))) 12362 (set (match_operand:SI 0 "gpc_reg_operand" "") 12363 (lt:SI (match_dup 1) (match_dup 2)))] 12364 "TARGET_POWER && reload_completed" 12365 [(set (match_dup 0) 12366 (lt:SI (match_dup 1) (match_dup 2))) 12367 (set (match_dup 3) 12368 (compare:CC (match_dup 0) 12369 (const_int 0)))] 12370 "") 12371 12372(define_insn "" 12373 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 12374 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12375 (match_operand:SI 2 "reg_or_short_operand" "rI")) 12376 (match_operand:SI 3 "gpc_reg_operand" "r")))] 12377 "TARGET_POWER" 12378 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" 12379 [(set_attr "length" "12")]) 12380 12381(define_insn "" 12382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12383 (compare:CC 12384 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12385 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12386 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12387 (const_int 0))) 12388 (clobber (match_scratch:SI 4 "=&r,&r"))] 12389 "TARGET_POWER" 12390 "@ 12391 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 12392 #" 12393 [(set_attr "type" "compare") 12394 (set_attr "length" "12,16")]) 12395 12396(define_split 12397 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12398 (compare:CC 12399 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12400 (match_operand:SI 2 "reg_or_short_operand" "")) 12401 (match_operand:SI 3 "gpc_reg_operand" "")) 12402 (const_int 0))) 12403 (clobber (match_scratch:SI 4 ""))] 12404 "TARGET_POWER && reload_completed" 12405 [(set (match_dup 4) 12406 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) 12407 (match_dup 3))) 12408 (set (match_dup 0) 12409 (compare:CC (match_dup 4) 12410 (const_int 0)))] 12411 "") 12412 12413(define_insn "" 12414 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12415 (compare:CC 12416 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12417 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12418 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12419 (const_int 0))) 12420 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12421 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12422 "TARGET_POWER" 12423 "@ 12424 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 12425 #" 12426 [(set_attr "type" "compare") 12427 (set_attr "length" "12,16")]) 12428 12429(define_split 12430 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12431 (compare:CC 12432 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12433 (match_operand:SI 2 "reg_or_short_operand" "")) 12434 (match_operand:SI 3 "gpc_reg_operand" "")) 12435 (const_int 0))) 12436 (set (match_operand:SI 0 "gpc_reg_operand" "") 12437 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12438 "TARGET_POWER && reload_completed" 12439 [(set (match_dup 0) 12440 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12441 (set (match_dup 4) 12442 (compare:CC (match_dup 0) 12443 (const_int 0)))] 12444 "") 12445 12446(define_insn "" 12447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12448 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12449 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 12450 "TARGET_POWER" 12451 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" 12452 [(set_attr "length" "12")]) 12453 12454(define_insn "" 12455 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12456 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12457 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 12458 "TARGET_32BIT" 12459 "@ 12460 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 12461 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 12462 [(set_attr "length" "12")]) 12463 12464(define_insn "" 12465 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 12466 (compare:CC 12467 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12468 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12469 (const_int 0))) 12470 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 12471 (ltu:SI (match_dup 1) (match_dup 2)))] 12472 "TARGET_32BIT" 12473 "@ 12474 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 12475 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 12476 # 12477 #" 12478 [(set_attr "type" "compare") 12479 (set_attr "length" "12,12,16,16")]) 12480 12481(define_split 12482 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12483 (compare:CC 12484 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12485 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 12486 (const_int 0))) 12487 (set (match_operand:SI 0 "gpc_reg_operand" "") 12488 (ltu:SI (match_dup 1) (match_dup 2)))] 12489 "TARGET_32BIT && reload_completed" 12490 [(set (match_dup 0) 12491 (ltu:SI (match_dup 1) (match_dup 2))) 12492 (set (match_dup 3) 12493 (compare:CC (match_dup 0) 12494 (const_int 0)))] 12495 "") 12496 12497(define_insn "" 12498 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12499 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12500 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 12501 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] 12502 "TARGET_32BIT" 12503 "@ 12504 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3 12505 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" 12506 [(set_attr "length" "12")]) 12507 12508(define_insn "" 12509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 12510 (compare:CC 12511 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12512 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12513 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12514 (const_int 0))) 12515 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 12516 "TARGET_32BIT" 12517 "@ 12518 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 12519 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 12520 # 12521 #" 12522 [(set_attr "type" "compare") 12523 (set_attr "length" "12,12,16,16")]) 12524 12525(define_split 12526 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12527 (compare:CC 12528 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12529 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 12530 (match_operand:SI 3 "gpc_reg_operand" "")) 12531 (const_int 0))) 12532 (clobber (match_scratch:SI 4 ""))] 12533 "TARGET_32BIT && reload_completed" 12534 [(set (match_dup 4) 12535 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) 12536 (match_dup 3))) 12537 (set (match_dup 0) 12538 (compare:CC (match_dup 4) 12539 (const_int 0)))] 12540 "") 12541 12542(define_insn "" 12543 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12544 (compare:CC 12545 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12546 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12547 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12548 (const_int 0))) 12549 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12550 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12551 "TARGET_32BIT" 12552 "@ 12553 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 12554 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 12555 # 12556 #" 12557 [(set_attr "type" "compare") 12558 (set_attr "length" "12,12,16,16")]) 12559 12560(define_split 12561 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12562 (compare:CC 12563 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12564 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 12565 (match_operand:SI 3 "gpc_reg_operand" "")) 12566 (const_int 0))) 12567 (set (match_operand:SI 0 "gpc_reg_operand" "") 12568 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12569 "TARGET_32BIT && reload_completed" 12570 [(set (match_dup 0) 12571 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12572 (set (match_dup 4) 12573 (compare:CC (match_dup 0) 12574 (const_int 0)))] 12575 "") 12576 12577(define_insn "" 12578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12579 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12580 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] 12581 "TARGET_32BIT" 12582 "@ 12583 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 12584 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" 12585 [(set_attr "length" "8")]) 12586 12587(define_insn "" 12588 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12589 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12590 (match_operand:SI 2 "reg_or_short_operand" "rI"))) 12591 (clobber (match_scratch:SI 3 "=r"))] 12592 "TARGET_POWER" 12593 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" 12594 [(set_attr "length" "12")]) 12595 12596(define_insn "" 12597 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12598 (compare:CC 12599 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12600 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12601 (const_int 0))) 12602 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12603 (ge:SI (match_dup 1) (match_dup 2))) 12604 (clobber (match_scratch:SI 3 "=r,r"))] 12605 "TARGET_POWER" 12606 "@ 12607 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 12608 #" 12609 [(set_attr "type" "compare") 12610 (set_attr "length" "12,16")]) 12611 12612(define_split 12613 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12614 (compare:CC 12615 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") 12616 (match_operand:SI 2 "reg_or_short_operand" "")) 12617 (const_int 0))) 12618 (set (match_operand:SI 0 "gpc_reg_operand" "") 12619 (ge:SI (match_dup 1) (match_dup 2))) 12620 (clobber (match_scratch:SI 3 ""))] 12621 "TARGET_POWER && reload_completed" 12622 [(parallel [(set (match_dup 0) 12623 (ge:SI (match_dup 1) (match_dup 2))) 12624 (clobber (match_dup 3))]) 12625 (set (match_dup 4) 12626 (compare:CC (match_dup 0) 12627 (const_int 0)))] 12628 "") 12629 12630(define_insn "" 12631 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 12632 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12633 (match_operand:SI 2 "reg_or_short_operand" "rI")) 12634 (match_operand:SI 3 "gpc_reg_operand" "r")))] 12635 "TARGET_POWER" 12636 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" 12637 [(set_attr "length" "12")]) 12638 12639(define_insn "" 12640 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12641 (compare:CC 12642 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12643 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12644 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12645 (const_int 0))) 12646 (clobber (match_scratch:SI 4 "=&r,&r"))] 12647 "TARGET_POWER" 12648 "@ 12649 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 12650 #" 12651 [(set_attr "type" "compare") 12652 (set_attr "length" "12,16")]) 12653 12654(define_split 12655 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12656 (compare:CC 12657 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") 12658 (match_operand:SI 2 "reg_or_short_operand" "")) 12659 (match_operand:SI 3 "gpc_reg_operand" "")) 12660 (const_int 0))) 12661 (clobber (match_scratch:SI 4 ""))] 12662 "TARGET_POWER && reload_completed" 12663 [(set (match_dup 4) 12664 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) 12665 (match_dup 3))) 12666 (set (match_dup 0) 12667 (compare:CC (match_dup 4) 12668 (const_int 0)))] 12669 "") 12670 12671(define_insn "" 12672 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12673 (compare:CC 12674 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12675 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12676 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12677 (const_int 0))) 12678 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12679 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12680 "TARGET_POWER" 12681 "@ 12682 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 12683 #" 12684 [(set_attr "type" "compare") 12685 (set_attr "length" "12,16")]) 12686 12687(define_split 12688 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12689 (compare:CC 12690 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") 12691 (match_operand:SI 2 "reg_or_short_operand" "")) 12692 (match_operand:SI 3 "gpc_reg_operand" "")) 12693 (const_int 0))) 12694 (set (match_operand:SI 0 "gpc_reg_operand" "") 12695 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12696 "TARGET_POWER && reload_completed" 12697 [(set (match_dup 0) 12698 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12699 (set (match_dup 4) 12700 (compare:CC (match_dup 0) 12701 (const_int 0)))] 12702 "") 12703 12704(define_insn "" 12705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12706 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12707 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 12708 "TARGET_POWER" 12709 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 12710 [(set_attr "length" "12")]) 12711 12712(define_insn "" 12713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12714 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12715 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 12716 "TARGET_32BIT" 12717 "@ 12718 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 12719 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 12720 [(set_attr "length" "12")]) 12721 12722(define_insn "" 12723 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 12724 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 12725 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] 12726 "TARGET_64BIT" 12727 "@ 12728 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 12729 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" 12730 [(set_attr "length" "12")]) 12731 12732(define_insn "" 12733 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 12734 (compare:CC 12735 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12736 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12737 (const_int 0))) 12738 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 12739 (geu:SI (match_dup 1) (match_dup 2)))] 12740 "TARGET_32BIT" 12741 "@ 12742 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 12743 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 12744 # 12745 #" 12746 [(set_attr "type" "compare") 12747 (set_attr "length" "12,12,16,16")]) 12748 12749(define_split 12750 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12751 (compare:CC 12752 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12753 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 12754 (const_int 0))) 12755 (set (match_operand:SI 0 "gpc_reg_operand" "") 12756 (geu:SI (match_dup 1) (match_dup 2)))] 12757 "TARGET_32BIT && reload_completed" 12758 [(set (match_dup 0) 12759 (geu:SI (match_dup 1) (match_dup 2))) 12760 (set (match_dup 3) 12761 (compare:CC (match_dup 0) 12762 (const_int 0)))] 12763 "") 12764 12765(define_insn "" 12766 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 12767 (compare:CC 12768 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 12769 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12770 (const_int 0))) 12771 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 12772 (geu:DI (match_dup 1) (match_dup 2)))] 12773 "TARGET_64BIT" 12774 "@ 12775 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 12776 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 12777 # 12778 #" 12779 [(set_attr "type" "compare") 12780 (set_attr "length" "12,12,16,16")]) 12781 12782(define_split 12783 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12784 (compare:CC 12785 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") 12786 (match_operand:DI 2 "reg_or_neg_short_operand" "")) 12787 (const_int 0))) 12788 (set (match_operand:DI 0 "gpc_reg_operand" "") 12789 (geu:DI (match_dup 1) (match_dup 2)))] 12790 "TARGET_64BIT && reload_completed" 12791 [(set (match_dup 0) 12792 (geu:DI (match_dup 1) (match_dup 2))) 12793 (set (match_dup 3) 12794 (compare:CC (match_dup 0) 12795 (const_int 0)))] 12796 "") 12797 12798(define_insn "" 12799 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12800 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12801 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 12802 (match_operand:SI 3 "gpc_reg_operand" "r,r")))] 12803 "TARGET_32BIT" 12804 "@ 12805 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 12806 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" 12807 [(set_attr "length" "8")]) 12808 12809(define_insn "" 12810 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 12811 (compare:CC 12812 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12813 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12814 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12815 (const_int 0))) 12816 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 12817 "TARGET_32BIT" 12818 "@ 12819 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 12820 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 12821 # 12822 #" 12823 [(set_attr "type" "compare") 12824 (set_attr "length" "8,8,12,12")]) 12825 12826(define_split 12827 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12828 (compare:CC 12829 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12830 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 12831 (match_operand:SI 3 "gpc_reg_operand" "")) 12832 (const_int 0))) 12833 (clobber (match_scratch:SI 4 ""))] 12834 "TARGET_32BIT && reload_completed" 12835 [(set (match_dup 4) 12836 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) 12837 (match_dup 3))) 12838 (set (match_dup 0) 12839 (compare:CC (match_dup 4) 12840 (const_int 0)))] 12841 "") 12842 12843(define_insn "" 12844 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12845 (compare:CC 12846 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12847 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12848 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12849 (const_int 0))) 12850 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12851 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12852 "TARGET_32BIT" 12853 "@ 12854 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 12855 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 12856 # 12857 #" 12858 [(set_attr "type" "compare") 12859 (set_attr "length" "8,8,12,12")]) 12860 12861(define_split 12862 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12863 (compare:CC 12864 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12865 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 12866 (match_operand:SI 3 "gpc_reg_operand" "")) 12867 (const_int 0))) 12868 (set (match_operand:SI 0 "gpc_reg_operand" "") 12869 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12870 "TARGET_32BIT && reload_completed" 12871 [(set (match_dup 0) 12872 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12873 (set (match_dup 4) 12874 (compare:CC (match_dup 0) 12875 (const_int 0)))] 12876 "") 12877 12878(define_insn "" 12879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12880 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12881 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] 12882 "TARGET_32BIT" 12883 "@ 12884 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 12885 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" 12886 [(set_attr "length" "12")]) 12887 12888(define_insn "" 12889 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12890 (and:SI (neg:SI 12891 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12892 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 12893 (match_operand:SI 3 "gpc_reg_operand" "r,r")))] 12894 "TARGET_32BIT" 12895 "@ 12896 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 12897 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" 12898 [(set_attr "length" "12")]) 12899 12900(define_insn "" 12901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 12902 (compare:CC 12903 (and:SI (neg:SI 12904 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12905 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) 12906 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12907 (const_int 0))) 12908 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 12909 "TARGET_32BIT" 12910 "@ 12911 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 12912 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 12913 # 12914 #" 12915 [(set_attr "type" "compare") 12916 (set_attr "length" "12,12,16,16")]) 12917 12918(define_split 12919 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12920 (compare:CC 12921 (and:SI (neg:SI 12922 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12923 (match_operand:SI 2 "reg_or_neg_short_operand" ""))) 12924 (match_operand:SI 3 "gpc_reg_operand" "")) 12925 (const_int 0))) 12926 (clobber (match_scratch:SI 4 ""))] 12927 "TARGET_32BIT && reload_completed" 12928 [(set (match_dup 4) 12929 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) 12930 (match_dup 3))) 12931 (set (match_dup 0) 12932 (compare:CC (match_dup 4) 12933 (const_int 0)))] 12934 "") 12935 12936(define_insn "" 12937 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12938 (compare:CC 12939 (and:SI (neg:SI 12940 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12941 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) 12942 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12943 (const_int 0))) 12944 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12945 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 12946 "TARGET_32BIT" 12947 "@ 12948 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 12949 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 12950 # 12951 #" 12952 [(set_attr "type" "compare") 12953 (set_attr "length" "12,12,16,16")]) 12954 12955(define_split 12956 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12957 (compare:CC 12958 (and:SI (neg:SI 12959 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12960 (match_operand:SI 2 "reg_or_neg_short_operand" ""))) 12961 (match_operand:SI 3 "gpc_reg_operand" "")) 12962 (const_int 0))) 12963 (set (match_operand:SI 0 "gpc_reg_operand" "") 12964 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 12965 "TARGET_32BIT && reload_completed" 12966 [(set (match_dup 0) 12967 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 12968 (set (match_dup 4) 12969 (compare:CC (match_dup 0) 12970 (const_int 0)))] 12971 "") 12972 12973(define_insn "" 12974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12975 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12976 (const_int 0)))] 12977 "TARGET_32BIT" 12978 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" 12979 [(set_attr "length" "12")]) 12980 12981(define_insn "" 12982 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 12983 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 12984 (const_int 0)))] 12985 "TARGET_64BIT" 12986 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" 12987 [(set_attr "length" "12")]) 12988 12989(define_insn "" 12990 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 12991 (compare:CC 12992 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12993 (const_int 0)) 12994 (const_int 0))) 12995 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12996 (gt:SI (match_dup 1) (const_int 0)))] 12997 "TARGET_32BIT" 12998 "@ 12999 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 13000 #" 13001 [(set_attr "type" "delayed_compare") 13002 (set_attr "length" "12,16")]) 13003 13004(define_split 13005 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 13006 (compare:CC 13007 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13008 (const_int 0)) 13009 (const_int 0))) 13010 (set (match_operand:SI 0 "gpc_reg_operand" "") 13011 (gt:SI (match_dup 1) (const_int 0)))] 13012 "TARGET_32BIT && reload_completed" 13013 [(set (match_dup 0) 13014 (gt:SI (match_dup 1) (const_int 0))) 13015 (set (match_dup 2) 13016 (compare:CC (match_dup 0) 13017 (const_int 0)))] 13018 "") 13019 13020(define_insn "" 13021 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 13022 (compare:CC 13023 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 13024 (const_int 0)) 13025 (const_int 0))) 13026 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 13027 (gt:DI (match_dup 1) (const_int 0)))] 13028 "TARGET_64BIT" 13029 "@ 13030 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 13031 #" 13032 [(set_attr "type" "delayed_compare") 13033 (set_attr "length" "12,16")]) 13034 13035(define_split 13036 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 13037 (compare:CC 13038 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 13039 (const_int 0)) 13040 (const_int 0))) 13041 (set (match_operand:DI 0 "gpc_reg_operand" "") 13042 (gt:DI (match_dup 1) (const_int 0)))] 13043 "TARGET_64BIT && reload_completed" 13044 [(set (match_dup 0) 13045 (gt:DI (match_dup 1) (const_int 0))) 13046 (set (match_dup 2) 13047 (compare:CC (match_dup 0) 13048 (const_int 0)))] 13049 "") 13050 13051(define_insn "" 13052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13053 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13054 (match_operand:SI 2 "reg_or_short_operand" "r")))] 13055 "TARGET_POWER" 13056 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" 13057 [(set_attr "length" "12")]) 13058 13059(define_insn "" 13060 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13061 (compare:CC 13062 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13063 (match_operand:SI 2 "reg_or_short_operand" "r,r")) 13064 (const_int 0))) 13065 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 13066 (gt:SI (match_dup 1) (match_dup 2)))] 13067 "TARGET_POWER" 13068 "@ 13069 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 13070 #" 13071 [(set_attr "type" "delayed_compare") 13072 (set_attr "length" "12,16")]) 13073 13074(define_split 13075 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 13076 (compare:CC 13077 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13078 (match_operand:SI 2 "reg_or_short_operand" "")) 13079 (const_int 0))) 13080 (set (match_operand:SI 0 "gpc_reg_operand" "") 13081 (gt:SI (match_dup 1) (match_dup 2)))] 13082 "TARGET_POWER && reload_completed" 13083 [(set (match_dup 0) 13084 (gt:SI (match_dup 1) (match_dup 2))) 13085 (set (match_dup 3) 13086 (compare:CC (match_dup 0) 13087 (const_int 0)))] 13088 "") 13089 13090(define_insn "" 13091 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 13092 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13093 (const_int 0)) 13094 (match_operand:SI 2 "gpc_reg_operand" "r")))] 13095 "TARGET_32BIT" 13096 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" 13097 [(set_attr "length" "12")]) 13098 13099(define_insn "" 13100 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 13101 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 13102 (const_int 0)) 13103 (match_operand:DI 2 "gpc_reg_operand" "r")))] 13104 "TARGET_64BIT" 13105 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" 13106 [(set_attr "length" "12")]) 13107 13108(define_insn "" 13109 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13110 (compare:CC 13111 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13112 (const_int 0)) 13113 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 13114 (const_int 0))) 13115 (clobber (match_scratch:SI 3 "=&r,&r"))] 13116 "TARGET_32BIT" 13117 "@ 13118 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 13119 #" 13120 [(set_attr "type" "compare") 13121 (set_attr "length" "12,16")]) 13122 13123(define_split 13124 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13125 (compare:CC 13126 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13127 (const_int 0)) 13128 (match_operand:SI 2 "gpc_reg_operand" "")) 13129 (const_int 0))) 13130 (clobber (match_scratch:SI 3 ""))] 13131 "TARGET_32BIT && reload_completed" 13132 [(set (match_dup 3) 13133 (plus:SI (gt:SI (match_dup 1) (const_int 0)) 13134 (match_dup 2))) 13135 (set (match_dup 0) 13136 (compare:CC (match_dup 3) 13137 (const_int 0)))] 13138 "") 13139 13140(define_insn "" 13141 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13142 (compare:CC 13143 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 13144 (const_int 0)) 13145 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 13146 (const_int 0))) 13147 (clobber (match_scratch:DI 3 "=&r,&r"))] 13148 "TARGET_64BIT" 13149 "@ 13150 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 13151 #" 13152 [(set_attr "type" "compare") 13153 (set_attr "length" "12,16")]) 13154 13155(define_split 13156 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13157 (compare:CC 13158 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 13159 (const_int 0)) 13160 (match_operand:DI 2 "gpc_reg_operand" "")) 13161 (const_int 0))) 13162 (clobber (match_scratch:DI 3 ""))] 13163 "TARGET_64BIT && reload_completed" 13164 [(set (match_dup 3) 13165 (plus:DI (gt:DI (match_dup 1) (const_int 0)) 13166 (match_dup 2))) 13167 (set (match_dup 0) 13168 (compare:CC (match_dup 3) 13169 (const_int 0)))] 13170 "") 13171 13172(define_insn "" 13173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13174 (compare:CC 13175 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13176 (const_int 0)) 13177 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 13178 (const_int 0))) 13179 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 13180 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] 13181 "TARGET_32BIT" 13182 "@ 13183 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 13184 #" 13185 [(set_attr "type" "compare") 13186 (set_attr "length" "12,16")]) 13187 13188(define_split 13189 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 13190 (compare:CC 13191 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13192 (const_int 0)) 13193 (match_operand:SI 2 "gpc_reg_operand" "")) 13194 (const_int 0))) 13195 (set (match_operand:SI 0 "gpc_reg_operand" "") 13196 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] 13197 "TARGET_32BIT && reload_completed" 13198 [(set (match_dup 0) 13199 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) 13200 (set (match_dup 3) 13201 (compare:CC (match_dup 0) 13202 (const_int 0)))] 13203 "") 13204 13205(define_insn "" 13206 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13207 (compare:CC 13208 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 13209 (const_int 0)) 13210 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 13211 (const_int 0))) 13212 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") 13213 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] 13214 "TARGET_64BIT" 13215 "@ 13216 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 13217 #" 13218 [(set_attr "type" "compare") 13219 (set_attr "length" "12,16")]) 13220 13221(define_split 13222 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 13223 (compare:CC 13224 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 13225 (const_int 0)) 13226 (match_operand:DI 2 "gpc_reg_operand" "")) 13227 (const_int 0))) 13228 (set (match_operand:DI 0 "gpc_reg_operand" "") 13229 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] 13230 "TARGET_64BIT && reload_completed" 13231 [(set (match_dup 0) 13232 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) 13233 (set (match_dup 3) 13234 (compare:CC (match_dup 0) 13235 (const_int 0)))] 13236 "") 13237 13238(define_insn "" 13239 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 13240 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13241 (match_operand:SI 2 "reg_or_short_operand" "r")) 13242 (match_operand:SI 3 "gpc_reg_operand" "r")))] 13243 "TARGET_POWER" 13244 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" 13245 [(set_attr "length" "12")]) 13246 13247(define_insn "" 13248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13249 (compare:CC 13250 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13251 (match_operand:SI 2 "reg_or_short_operand" "r,r")) 13252 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 13253 (const_int 0))) 13254 (clobber (match_scratch:SI 4 "=&r,&r"))] 13255 "TARGET_POWER" 13256 "@ 13257 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 13258 #" 13259 [(set_attr "type" "compare") 13260 (set_attr "length" "12,16")]) 13261 13262(define_split 13263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13264 (compare:CC 13265 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13266 (match_operand:SI 2 "reg_or_short_operand" "")) 13267 (match_operand:SI 3 "gpc_reg_operand" "")) 13268 (const_int 0))) 13269 (clobber (match_scratch:SI 4 ""))] 13270 "TARGET_POWER && reload_completed" 13271 [(set (match_dup 4) 13272 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 13273 (set (match_dup 0) 13274 (compare:CC (match_dup 4) 13275 (const_int 0)))] 13276 "") 13277 13278(define_insn "" 13279 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 13280 (compare:CC 13281 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13282 (match_operand:SI 2 "reg_or_short_operand" "r,r")) 13283 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 13284 (const_int 0))) 13285 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 13286 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13287 "TARGET_POWER" 13288 "@ 13289 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 13290 #" 13291 [(set_attr "type" "compare") 13292 (set_attr "length" "12,16")]) 13293 13294(define_split 13295 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 13296 (compare:CC 13297 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 13298 (match_operand:SI 2 "reg_or_short_operand" "")) 13299 (match_operand:SI 3 "gpc_reg_operand" "")) 13300 (const_int 0))) 13301 (set (match_operand:SI 0 "gpc_reg_operand" "") 13302 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13303 "TARGET_POWER && reload_completed" 13304 [(set (match_dup 0) 13305 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 13306 (set (match_dup 4) 13307 (compare:CC (match_dup 0) 13308 (const_int 0)))] 13309 "") 13310 13311(define_insn "" 13312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13313 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13314 (const_int 0))))] 13315 "TARGET_32BIT" 13316 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" 13317 [(set_attr "length" "12")]) 13318 13319(define_insn "" 13320 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 13321 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 13322 (const_int 0))))] 13323 "TARGET_64BIT" 13324 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" 13325 [(set_attr "length" "12")]) 13326 13327(define_insn "" 13328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13329 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13330 (match_operand:SI 2 "reg_or_short_operand" "r"))))] 13331 "TARGET_POWER" 13332 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" 13333 [(set_attr "length" "12")]) 13334 13335(define_insn "" 13336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13337 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13338 (match_operand:SI 2 "reg_or_short_operand" "rI")))] 13339 "TARGET_32BIT" 13340 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 13341 [(set_attr "length" "12")]) 13342 13343(define_insn "" 13344 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 13345 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") 13346 (match_operand:DI 2 "reg_or_short_operand" "rI")))] 13347 "TARGET_64BIT" 13348 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" 13349 [(set_attr "length" "12")]) 13350 13351(define_insn "" 13352 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13353 (compare:CC 13354 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13355 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 13356 (const_int 0))) 13357 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 13358 (gtu:SI (match_dup 1) (match_dup 2)))] 13359 "TARGET_32BIT" 13360 "@ 13361 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 13362 #" 13363 [(set_attr "type" "compare") 13364 (set_attr "length" "12,16")]) 13365 13366(define_split 13367 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 13368 (compare:CC 13369 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") 13370 (match_operand:SI 2 "reg_or_short_operand" "")) 13371 (const_int 0))) 13372 (set (match_operand:SI 0 "gpc_reg_operand" "") 13373 (gtu:SI (match_dup 1) (match_dup 2)))] 13374 "TARGET_32BIT && reload_completed" 13375 [(set (match_dup 0) 13376 (gtu:SI (match_dup 1) (match_dup 2))) 13377 (set (match_dup 3) 13378 (compare:CC (match_dup 0) 13379 (const_int 0)))] 13380 "") 13381 13382(define_insn "" 13383 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13384 (compare:CC 13385 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 13386 (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) 13387 (const_int 0))) 13388 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 13389 (gtu:DI (match_dup 1) (match_dup 2)))] 13390 "TARGET_64BIT" 13391 "@ 13392 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 13393 #" 13394 [(set_attr "type" "compare") 13395 (set_attr "length" "12,16")]) 13396 13397(define_split 13398 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 13399 (compare:CC 13400 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") 13401 (match_operand:DI 2 "reg_or_short_operand" "")) 13402 (const_int 0))) 13403 (set (match_operand:DI 0 "gpc_reg_operand" "") 13404 (gtu:DI (match_dup 1) (match_dup 2)))] 13405 "TARGET_64BIT && reload_completed" 13406 [(set (match_dup 0) 13407 (gtu:DI (match_dup 1) (match_dup 2))) 13408 (set (match_dup 3) 13409 (compare:CC (match_dup 0) 13410 (const_int 0)))] 13411 "") 13412 13413(define_insn "" 13414 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 13415 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13416 (match_operand:SI 2 "reg_or_short_operand" "I,rI")) 13417 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))] 13418 "TARGET_32BIT" 13419 "@ 13420 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 13421 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" 13422 [(set_attr "length" "8,12")]) 13423 13424(define_insn "" 13425 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") 13426 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 13427 (match_operand:DI 2 "reg_or_short_operand" "I,rI")) 13428 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] 13429 "TARGET_64BIT" 13430 "@ 13431 addic %0,%1,%k2\;addze %0,%3 13432 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" 13433 [(set_attr "length" "8,12")]) 13434 13435(define_insn "" 13436 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 13437 (compare:CC 13438 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 13439 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) 13440 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 13441 (const_int 0))) 13442 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 13443 "TARGET_32BIT" 13444 "@ 13445 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 13446 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 13447 # 13448 #" 13449 [(set_attr "type" "compare") 13450 (set_attr "length" "8,12,12,16")]) 13451 13452(define_split 13453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13454 (compare:CC 13455 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") 13456 (match_operand:SI 2 "reg_or_short_operand" "")) 13457 (match_operand:SI 3 "gpc_reg_operand" "")) 13458 (const_int 0))) 13459 (clobber (match_scratch:SI 4 ""))] 13460 "TARGET_32BIT && reload_completed" 13461 [(set (match_dup 4) 13462 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) 13463 (match_dup 3))) 13464 (set (match_dup 0) 13465 (compare:CC (match_dup 4) 13466 (const_int 0)))] 13467 "") 13468 13469(define_insn "" 13470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 13471 (compare:CC 13472 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 13473 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) 13474 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) 13475 (const_int 0))) 13476 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] 13477 "TARGET_64BIT" 13478 "@ 13479 addic %4,%1,%k2\;addze. %4,%3 13480 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 13481 # 13482 #" 13483 [(set_attr "type" "compare") 13484 (set_attr "length" "8,12,12,16")]) 13485 13486(define_split 13487 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13488 (compare:CC 13489 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") 13490 (match_operand:DI 2 "reg_or_short_operand" "")) 13491 (match_operand:DI 3 "gpc_reg_operand" "")) 13492 (const_int 0))) 13493 (clobber (match_scratch:DI 4 ""))] 13494 "TARGET_64BIT && reload_completed" 13495 [(set (match_dup 4) 13496 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) 13497 (match_dup 3))) 13498 (set (match_dup 0) 13499 (compare:CC (match_dup 4) 13500 (const_int 0)))] 13501 "") 13502 13503(define_insn "" 13504 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 13505 (compare:CC 13506 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 13507 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) 13508 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 13509 (const_int 0))) 13510 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 13511 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13512 "TARGET_32BIT" 13513 "@ 13514 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 13515 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 13516 # 13517 #" 13518 [(set_attr "type" "compare") 13519 (set_attr "length" "8,12,12,16")]) 13520 13521(define_split 13522 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 13523 (compare:CC 13524 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") 13525 (match_operand:SI 2 "reg_or_short_operand" "")) 13526 (match_operand:SI 3 "gpc_reg_operand" "")) 13527 (const_int 0))) 13528 (set (match_operand:SI 0 "gpc_reg_operand" "") 13529 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13530 "TARGET_32BIT && reload_completed" 13531 [(set (match_dup 0) 13532 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 13533 (set (match_dup 4) 13534 (compare:CC (match_dup 0) 13535 (const_int 0)))] 13536 "") 13537 13538(define_insn "" 13539 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 13540 (compare:CC 13541 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 13542 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) 13543 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) 13544 (const_int 0))) 13545 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 13546 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13547 "TARGET_64BIT" 13548 "@ 13549 addic %0,%1,%k2\;addze. %0,%3 13550 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 13551 # 13552 #" 13553 [(set_attr "type" "compare") 13554 (set_attr "length" "8,12,12,16")]) 13555 13556(define_split 13557 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 13558 (compare:CC 13559 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") 13560 (match_operand:DI 2 "reg_or_short_operand" "")) 13561 (match_operand:DI 3 "gpc_reg_operand" "")) 13562 (const_int 0))) 13563 (set (match_operand:DI 0 "gpc_reg_operand" "") 13564 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13565 "TARGET_64BIT && reload_completed" 13566 [(set (match_dup 0) 13567 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) 13568 (set (match_dup 4) 13569 (compare:CC (match_dup 0) 13570 (const_int 0)))] 13571 "") 13572 13573(define_insn "" 13574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13575 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 13576 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 13577 "TARGET_32BIT" 13578 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" 13579 [(set_attr "length" "8")]) 13580 13581(define_insn "" 13582 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 13583 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") 13584 (match_operand:DI 2 "reg_or_short_operand" "rI"))))] 13585 "TARGET_64BIT" 13586 "subf%I2c %0,%1,%2\;subfe %0,%0,%0" 13587 [(set_attr "length" "8")]) 13588 13589;; Define both directions of branch and return. If we need a reload 13590;; register, we'd rather use CR0 since it is much easier to copy a 13591;; register CC value to there. 13592 13593(define_insn "" 13594 [(set (pc) 13595 (if_then_else (match_operator 1 "branch_comparison_operator" 13596 [(match_operand 2 13597 "cc_reg_operand" "y") 13598 (const_int 0)]) 13599 (label_ref (match_operand 0 "" "")) 13600 (pc)))] 13601 "" 13602 "* 13603{ 13604 return output_cbranch (operands[1], \"%l0\", 0, insn); 13605}" 13606 [(set_attr "type" "branch")]) 13607 13608(define_insn "" 13609 [(set (pc) 13610 (if_then_else (match_operator 0 "branch_comparison_operator" 13611 [(match_operand 1 13612 "cc_reg_operand" "y") 13613 (const_int 0)]) 13614 (return) 13615 (pc)))] 13616 "direct_return ()" 13617 "* 13618{ 13619 return output_cbranch (operands[0], NULL, 0, insn); 13620}" 13621 [(set_attr "type" "branch") 13622 (set_attr "length" "4")]) 13623 13624(define_insn "" 13625 [(set (pc) 13626 (if_then_else (match_operator 1 "branch_comparison_operator" 13627 [(match_operand 2 13628 "cc_reg_operand" "y") 13629 (const_int 0)]) 13630 (pc) 13631 (label_ref (match_operand 0 "" ""))))] 13632 "" 13633 "* 13634{ 13635 return output_cbranch (operands[1], \"%l0\", 1, insn); 13636}" 13637 [(set_attr "type" "branch")]) 13638 13639(define_insn "" 13640 [(set (pc) 13641 (if_then_else (match_operator 0 "branch_comparison_operator" 13642 [(match_operand 1 13643 "cc_reg_operand" "y") 13644 (const_int 0)]) 13645 (pc) 13646 (return)))] 13647 "direct_return ()" 13648 "* 13649{ 13650 return output_cbranch (operands[0], NULL, 1, insn); 13651}" 13652 [(set_attr "type" "branch") 13653 (set_attr "length" "4")]) 13654 13655;; Logic on condition register values. 13656 13657; This pattern matches things like 13658; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) 13659; (eq:SI (reg:CCFP 68) (const_int 0))) 13660; (const_int 1))) 13661; which are generated by the branch logic. 13662; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) 13663 13664(define_insn "*cceq_ior_compare" 13665 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") 13666 (compare:CCEQ (match_operator:SI 1 "boolean_operator" 13667 [(match_operator:SI 2 13668 "branch_positive_comparison_operator" 13669 [(match_operand 3 13670 "cc_reg_operand" "y,y") 13671 (const_int 0)]) 13672 (match_operator:SI 4 13673 "branch_positive_comparison_operator" 13674 [(match_operand 5 13675 "cc_reg_operand" "0,y") 13676 (const_int 0)])]) 13677 (const_int 1)))] 13678 "" 13679 "cr%q1 %E0,%j2,%j4" 13680 [(set_attr "type" "cr_logical,delayed_cr")]) 13681 13682; Why is the constant -1 here, but 1 in the previous pattern? 13683; Because ~1 has all but the low bit set. 13684(define_insn "" 13685 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") 13686 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" 13687 [(not:SI (match_operator:SI 2 13688 "branch_positive_comparison_operator" 13689 [(match_operand 3 13690 "cc_reg_operand" "y,y") 13691 (const_int 0)])) 13692 (match_operator:SI 4 13693 "branch_positive_comparison_operator" 13694 [(match_operand 5 13695 "cc_reg_operand" "0,y") 13696 (const_int 0)])]) 13697 (const_int -1)))] 13698 "" 13699 "cr%q1 %E0,%j2,%j4" 13700 [(set_attr "type" "cr_logical,delayed_cr")]) 13701 13702(define_insn "*cceq_rev_compare" 13703 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") 13704 (compare:CCEQ (match_operator:SI 1 13705 "branch_positive_comparison_operator" 13706 [(match_operand 2 13707 "cc_reg_operand" "0,y") 13708 (const_int 0)]) 13709 (const_int 0)))] 13710 "" 13711 "{crnor %E0,%j1,%j1|crnot %E0,%j1}" 13712 [(set_attr "type" "cr_logical,delayed_cr")]) 13713 13714;; If we are comparing the result of two comparisons, this can be done 13715;; using creqv or crxor. 13716 13717(define_insn_and_split "" 13718 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 13719 (compare:CCEQ (match_operator 1 "branch_comparison_operator" 13720 [(match_operand 2 "cc_reg_operand" "y") 13721 (const_int 0)]) 13722 (match_operator 3 "branch_comparison_operator" 13723 [(match_operand 4 "cc_reg_operand" "y") 13724 (const_int 0)])))] 13725 "" 13726 "#" 13727 "" 13728 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) 13729 (match_dup 5)))] 13730 " 13731{ 13732 int positive_1, positive_2; 13733 13734 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); 13735 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); 13736 13737 if (! positive_1) 13738 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]), 13739 GET_CODE (operands[1])), 13740 SImode, 13741 operands[2], const0_rtx); 13742 else if (GET_MODE (operands[1]) != SImode) 13743 operands[1] = gen_rtx (GET_CODE (operands[1]), 13744 SImode, 13745 operands[2], const0_rtx); 13746 13747 if (! positive_2) 13748 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]), 13749 GET_CODE (operands[3])), 13750 SImode, 13751 operands[4], const0_rtx); 13752 else if (GET_MODE (operands[3]) != SImode) 13753 operands[3] = gen_rtx (GET_CODE (operands[3]), 13754 SImode, 13755 operands[4], const0_rtx); 13756 13757 if (positive_1 == positive_2) 13758 { 13759 operands[1] = gen_rtx_NOT (SImode, operands[1]); 13760 operands[5] = constm1_rtx; 13761 } 13762 else 13763 { 13764 operands[5] = const1_rtx; 13765 } 13766}") 13767 13768;; Unconditional branch and return. 13769 13770(define_insn "jump" 13771 [(set (pc) 13772 (label_ref (match_operand 0 "" "")))] 13773 "" 13774 "b %l0" 13775 [(set_attr "type" "branch")]) 13776 13777(define_insn "return" 13778 [(return)] 13779 "direct_return ()" 13780 "{br|blr}" 13781 [(set_attr "type" "jmpreg")]) 13782 13783(define_expand "indirect_jump" 13784 [(set (pc) (match_operand 0 "register_operand" ""))] 13785 "" 13786 " 13787{ 13788 if (TARGET_32BIT) 13789 emit_jump_insn (gen_indirect_jumpsi (operands[0])); 13790 else 13791 emit_jump_insn (gen_indirect_jumpdi (operands[0])); 13792 DONE; 13793}") 13794 13795(define_insn "indirect_jumpsi" 13796 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] 13797 "TARGET_32BIT" 13798 "@ 13799 bctr 13800 {br|blr}" 13801 [(set_attr "type" "jmpreg")]) 13802 13803(define_insn "indirect_jumpdi" 13804 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] 13805 "TARGET_64BIT" 13806 "@ 13807 bctr 13808 blr" 13809 [(set_attr "type" "jmpreg")]) 13810 13811;; Table jump for switch statements: 13812(define_expand "tablejump" 13813 [(use (match_operand 0 "" "")) 13814 (use (label_ref (match_operand 1 "" "")))] 13815 "" 13816 " 13817{ 13818 if (TARGET_32BIT) 13819 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); 13820 else 13821 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); 13822 DONE; 13823}") 13824 13825(define_expand "tablejumpsi" 13826 [(set (match_dup 3) 13827 (plus:SI (match_operand:SI 0 "" "") 13828 (match_dup 2))) 13829 (parallel [(set (pc) (match_dup 3)) 13830 (use (label_ref (match_operand 1 "" "")))])] 13831 "TARGET_32BIT" 13832 " 13833{ operands[0] = force_reg (SImode, operands[0]); 13834 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); 13835 operands[3] = gen_reg_rtx (SImode); 13836}") 13837 13838(define_expand "tablejumpdi" 13839 [(set (match_dup 4) 13840 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) 13841 (set (match_dup 3) 13842 (plus:DI (match_dup 4) 13843 (match_dup 2))) 13844 (parallel [(set (pc) (match_dup 3)) 13845 (use (label_ref (match_operand 1 "" "")))])] 13846 "TARGET_64BIT" 13847 " 13848{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); 13849 operands[3] = gen_reg_rtx (DImode); 13850 operands[4] = gen_reg_rtx (DImode); 13851}") 13852 13853(define_insn "" 13854 [(set (pc) 13855 (match_operand:SI 0 "register_operand" "c,*l")) 13856 (use (label_ref (match_operand 1 "" "")))] 13857 "TARGET_32BIT" 13858 "@ 13859 bctr 13860 {br|blr}" 13861 [(set_attr "type" "jmpreg")]) 13862 13863(define_insn "" 13864 [(set (pc) 13865 (match_operand:DI 0 "register_operand" "c,*l")) 13866 (use (label_ref (match_operand 1 "" "")))] 13867 "TARGET_64BIT" 13868 "@ 13869 bctr 13870 blr" 13871 [(set_attr "type" "jmpreg")]) 13872 13873(define_insn "nop" 13874 [(const_int 0)] 13875 "" 13876 "{cror 0,0,0|nop}") 13877 13878;; Define the subtract-one-and-jump insns, starting with the template 13879;; so loop.c knows what to generate. 13880 13881(define_expand "doloop_end" 13882 [(use (match_operand 0 "" "")) ; loop pseudo 13883 (use (match_operand 1 "" "")) ; iterations; zero if unknown 13884 (use (match_operand 2 "" "")) ; max iterations 13885 (use (match_operand 3 "" "")) ; loop level 13886 (use (match_operand 4 "" ""))] ; label 13887 "" 13888 " 13889{ 13890 /* Only use this on innermost loops. */ 13891 if (INTVAL (operands[3]) > 1) 13892 FAIL; 13893 if (TARGET_64BIT) 13894 { 13895 if (GET_MODE (operands[0]) != DImode) 13896 FAIL; 13897 emit_jump_insn (gen_ctrdi (operands[0], operands[4])); 13898 } 13899 else 13900 { 13901 if (GET_MODE (operands[0]) != SImode) 13902 FAIL; 13903 emit_jump_insn (gen_ctrsi (operands[0], operands[4])); 13904 } 13905 DONE; 13906}") 13907 13908(define_expand "ctrsi" 13909 [(parallel [(set (pc) 13910 (if_then_else (ne (match_operand:SI 0 "register_operand" "") 13911 (const_int 1)) 13912 (label_ref (match_operand 1 "" "")) 13913 (pc))) 13914 (set (match_dup 0) 13915 (plus:SI (match_dup 0) 13916 (const_int -1))) 13917 (clobber (match_scratch:CC 2 "")) 13918 (clobber (match_scratch:SI 3 ""))])] 13919 "TARGET_32BIT" 13920 "") 13921 13922(define_expand "ctrdi" 13923 [(parallel [(set (pc) 13924 (if_then_else (ne (match_operand:DI 0 "register_operand" "") 13925 (const_int 1)) 13926 (label_ref (match_operand 1 "" "")) 13927 (pc))) 13928 (set (match_dup 0) 13929 (plus:DI (match_dup 0) 13930 (const_int -1))) 13931 (clobber (match_scratch:CC 2 "")) 13932 (clobber (match_scratch:DI 3 ""))])] 13933 "TARGET_64BIT" 13934 "") 13935 13936;; We need to be able to do this for any operand, including MEM, or we 13937;; will cause reload to blow up since we don't allow output reloads on 13938;; JUMP_INSNs. 13939;; For the length attribute to be calculated correctly, the 13940;; label MUST be operand 0. 13941 13942(define_insn "*ctrsi_internal1" 13943 [(set (pc) 13944 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") 13945 (const_int 1)) 13946 (label_ref (match_operand 0 "" "")) 13947 (pc))) 13948 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") 13949 (plus:SI (match_dup 1) 13950 (const_int -1))) 13951 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 13952 (clobber (match_scratch:SI 4 "=X,X,&r,r"))] 13953 "TARGET_32BIT" 13954 "* 13955{ 13956 if (which_alternative != 0) 13957 return \"#\"; 13958 else if (get_attr_length (insn) == 4) 13959 return \"{bdn|bdnz} %l0\"; 13960 else 13961 return \"bdz $+8\;b %l0\"; 13962}" 13963 [(set_attr "type" "branch") 13964 (set_attr "length" "*,12,16,16")]) 13965 13966(define_insn "*ctrsi_internal2" 13967 [(set (pc) 13968 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") 13969 (const_int 1)) 13970 (pc) 13971 (label_ref (match_operand 0 "" "")))) 13972 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") 13973 (plus:SI (match_dup 1) 13974 (const_int -1))) 13975 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 13976 (clobber (match_scratch:SI 4 "=X,X,&r,r"))] 13977 "TARGET_32BIT" 13978 "* 13979{ 13980 if (which_alternative != 0) 13981 return \"#\"; 13982 else if (get_attr_length (insn) == 4) 13983 return \"bdz %l0\"; 13984 else 13985 return \"{bdn|bdnz} $+8\;b %l0\"; 13986}" 13987 [(set_attr "type" "branch") 13988 (set_attr "length" "*,12,16,16")]) 13989 13990(define_insn "*ctrdi_internal1" 13991 [(set (pc) 13992 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") 13993 (const_int 1)) 13994 (label_ref (match_operand 0 "" "")) 13995 (pc))) 13996 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") 13997 (plus:DI (match_dup 1) 13998 (const_int -1))) 13999 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14000 (clobber (match_scratch:DI 4 "=X,X,&r,r"))] 14001 "TARGET_64BIT" 14002 "* 14003{ 14004 if (which_alternative != 0) 14005 return \"#\"; 14006 else if (get_attr_length (insn) == 4) 14007 return \"{bdn|bdnz} %l0\"; 14008 else 14009 return \"bdz $+8\;b %l0\"; 14010}" 14011 [(set_attr "type" "branch") 14012 (set_attr "length" "*,12,16,16")]) 14013 14014(define_insn "*ctrdi_internal2" 14015 [(set (pc) 14016 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") 14017 (const_int 1)) 14018 (pc) 14019 (label_ref (match_operand 0 "" "")))) 14020 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") 14021 (plus:DI (match_dup 1) 14022 (const_int -1))) 14023 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14024 (clobber (match_scratch:DI 4 "=X,X,&r,r"))] 14025 "TARGET_64BIT" 14026 "* 14027{ 14028 if (which_alternative != 0) 14029 return \"#\"; 14030 else if (get_attr_length (insn) == 4) 14031 return \"bdz %l0\"; 14032 else 14033 return \"{bdn|bdnz} $+8\;b %l0\"; 14034}" 14035 [(set_attr "type" "branch") 14036 (set_attr "length" "*,12,16,16")]) 14037 14038;; Similar, but we can use GE since we have a REG_NONNEG. 14039 14040(define_insn "*ctrsi_internal3" 14041 [(set (pc) 14042 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r") 14043 (const_int 0)) 14044 (label_ref (match_operand 0 "" "")) 14045 (pc))) 14046 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") 14047 (plus:SI (match_dup 1) 14048 (const_int -1))) 14049 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14050 (clobber (match_scratch:SI 4 "=X,X,&r,r"))] 14051 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)" 14052 "* 14053{ 14054 if (which_alternative != 0) 14055 return \"#\"; 14056 else if (get_attr_length (insn) == 4) 14057 return \"{bdn|bdnz} %l0\"; 14058 else 14059 return \"bdz $+8\;b %l0\"; 14060}" 14061 [(set_attr "type" "branch") 14062 (set_attr "length" "*,12,16,16")]) 14063 14064(define_insn "*ctrsi_internal4" 14065 [(set (pc) 14066 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r") 14067 (const_int 0)) 14068 (pc) 14069 (label_ref (match_operand 0 "" "")))) 14070 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") 14071 (plus:SI (match_dup 1) 14072 (const_int -1))) 14073 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14074 (clobber (match_scratch:SI 4 "=X,X,&r,r"))] 14075 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)" 14076 "* 14077{ 14078 if (which_alternative != 0) 14079 return \"#\"; 14080 else if (get_attr_length (insn) == 4) 14081 return \"bdz %l0\"; 14082 else 14083 return \"{bdn|bdnz} $+8\;b %l0\"; 14084}" 14085 [(set_attr "type" "branch") 14086 (set_attr "length" "*,12,16,16")]) 14087 14088(define_insn "*ctrdi_internal3" 14089 [(set (pc) 14090 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r") 14091 (const_int 0)) 14092 (label_ref (match_operand 0 "" "")) 14093 (pc))) 14094 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") 14095 (plus:DI (match_dup 1) 14096 (const_int -1))) 14097 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14098 (clobber (match_scratch:DI 4 "=X,X,&r,r"))] 14099 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)" 14100 "* 14101{ 14102 if (which_alternative != 0) 14103 return \"#\"; 14104 else if (get_attr_length (insn) == 4) 14105 return \"{bdn|bdnz} %l0\"; 14106 else 14107 return \"bdz $+8\;b %l0\"; 14108}" 14109 [(set_attr "type" "branch") 14110 (set_attr "length" "*,12,16,16")]) 14111 14112(define_insn "*ctrdi_internal4" 14113 [(set (pc) 14114 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r") 14115 (const_int 0)) 14116 (pc) 14117 (label_ref (match_operand 0 "" "")))) 14118 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") 14119 (plus:DI (match_dup 1) 14120 (const_int -1))) 14121 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14122 (clobber (match_scratch:DI 4 "=X,X,&r,r"))] 14123 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)" 14124 "* 14125{ 14126 if (which_alternative != 0) 14127 return \"#\"; 14128 else if (get_attr_length (insn) == 4) 14129 return \"bdz %l0\"; 14130 else 14131 return \"{bdn|bdnz} $+8\;b %l0\"; 14132}" 14133 [(set_attr "type" "branch") 14134 (set_attr "length" "*,12,16,16")]) 14135 14136;; Similar but use EQ 14137 14138(define_insn "*ctrsi_internal5" 14139 [(set (pc) 14140 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") 14141 (const_int 1)) 14142 (label_ref (match_operand 0 "" "")) 14143 (pc))) 14144 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") 14145 (plus:SI (match_dup 1) 14146 (const_int -1))) 14147 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14148 (clobber (match_scratch:SI 4 "=X,X,&r,r"))] 14149 "TARGET_32BIT" 14150 "* 14151{ 14152 if (which_alternative != 0) 14153 return \"#\"; 14154 else if (get_attr_length (insn) == 4) 14155 return \"bdz %l0\"; 14156 else 14157 return \"{bdn|bdnz} $+8\;b %l0\"; 14158}" 14159 [(set_attr "type" "branch") 14160 (set_attr "length" "*,12,16,16")]) 14161 14162(define_insn "*ctrsi_internal6" 14163 [(set (pc) 14164 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") 14165 (const_int 1)) 14166 (pc) 14167 (label_ref (match_operand 0 "" "")))) 14168 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l") 14169 (plus:SI (match_dup 1) 14170 (const_int -1))) 14171 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14172 (clobber (match_scratch:SI 4 "=X,X,&r,r"))] 14173 "TARGET_32BIT" 14174 "* 14175{ 14176 if (which_alternative != 0) 14177 return \"#\"; 14178 else if (get_attr_length (insn) == 4) 14179 return \"{bdn|bdnz} %l0\"; 14180 else 14181 return \"bdz $+8\;b %l0\"; 14182}" 14183 [(set_attr "type" "branch") 14184 (set_attr "length" "*,12,16,16")]) 14185 14186(define_insn "*ctrdi_internal5" 14187 [(set (pc) 14188 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") 14189 (const_int 1)) 14190 (label_ref (match_operand 0 "" "")) 14191 (pc))) 14192 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") 14193 (plus:DI (match_dup 1) 14194 (const_int -1))) 14195 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14196 (clobber (match_scratch:DI 4 "=X,X,&r,r"))] 14197 "TARGET_64BIT" 14198 "* 14199{ 14200 if (which_alternative != 0) 14201 return \"#\"; 14202 else if (get_attr_length (insn) == 4) 14203 return \"bdz %l0\"; 14204 else 14205 return \"{bdn|bdnz} $+8\;b %l0\"; 14206}" 14207 [(set_attr "type" "branch") 14208 (set_attr "length" "*,12,16,16")]) 14209 14210(define_insn "*ctrdi_internal6" 14211 [(set (pc) 14212 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") 14213 (const_int 1)) 14214 (pc) 14215 (label_ref (match_operand 0 "" "")))) 14216 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l") 14217 (plus:DI (match_dup 1) 14218 (const_int -1))) 14219 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14220 (clobber (match_scratch:DI 4 "=X,X,&r,r"))] 14221 "TARGET_64BIT" 14222 "* 14223{ 14224 if (which_alternative != 0) 14225 return \"#\"; 14226 else if (get_attr_length (insn) == 4) 14227 return \"{bdn|bdnz} %l0\"; 14228 else 14229 return \"bdz $+8\;b %l0\"; 14230}" 14231 [(set_attr "type" "branch") 14232 (set_attr "length" "*,12,16,16")]) 14233 14234;; Now the splitters if we could not allocate the CTR register 14235 14236(define_split 14237 [(set (pc) 14238 (if_then_else (match_operator 2 "comparison_operator" 14239 [(match_operand:SI 1 "gpc_reg_operand" "") 14240 (const_int 1)]) 14241 (match_operand 5 "" "") 14242 (match_operand 6 "" ""))) 14243 (set (match_operand:SI 0 "gpc_reg_operand" "") 14244 (plus:SI (match_dup 1) 14245 (const_int -1))) 14246 (clobber (match_scratch:CC 3 "")) 14247 (clobber (match_scratch:SI 4 ""))] 14248 "TARGET_32BIT && reload_completed" 14249 [(parallel [(set (match_dup 3) 14250 (compare:CC (plus:SI (match_dup 1) 14251 (const_int -1)) 14252 (const_int 0))) 14253 (set (match_dup 0) 14254 (plus:SI (match_dup 1) 14255 (const_int -1)))]) 14256 (set (pc) (if_then_else (match_dup 7) 14257 (match_dup 5) 14258 (match_dup 6)))] 14259 " 14260{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 14261 const0_rtx); }") 14262 14263(define_split 14264 [(set (pc) 14265 (if_then_else (match_operator 2 "comparison_operator" 14266 [(match_operand:SI 1 "gpc_reg_operand" "") 14267 (const_int 1)]) 14268 (match_operand 5 "" "") 14269 (match_operand 6 "" ""))) 14270 (set (match_operand:SI 0 "nonimmediate_operand" "") 14271 (plus:SI (match_dup 1) (const_int -1))) 14272 (clobber (match_scratch:CC 3 "")) 14273 (clobber (match_scratch:SI 4 ""))] 14274 "TARGET_32BIT && reload_completed 14275 && ! gpc_reg_operand (operands[0], SImode)" 14276 [(parallel [(set (match_dup 3) 14277 (compare:CC (plus:SI (match_dup 1) 14278 (const_int -1)) 14279 (const_int 0))) 14280 (set (match_dup 4) 14281 (plus:SI (match_dup 1) 14282 (const_int -1)))]) 14283 (set (match_dup 0) 14284 (match_dup 4)) 14285 (set (pc) (if_then_else (match_dup 7) 14286 (match_dup 5) 14287 (match_dup 6)))] 14288 " 14289{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 14290 const0_rtx); }") 14291(define_split 14292 [(set (pc) 14293 (if_then_else (match_operator 2 "comparison_operator" 14294 [(match_operand:DI 1 "gpc_reg_operand" "") 14295 (const_int 1)]) 14296 (match_operand 5 "" "") 14297 (match_operand 6 "" ""))) 14298 (set (match_operand:DI 0 "gpc_reg_operand" "") 14299 (plus:DI (match_dup 1) 14300 (const_int -1))) 14301 (clobber (match_scratch:CC 3 "")) 14302 (clobber (match_scratch:DI 4 ""))] 14303 "TARGET_64BIT && reload_completed" 14304 [(parallel [(set (match_dup 3) 14305 (compare:CC (plus:DI (match_dup 1) 14306 (const_int -1)) 14307 (const_int 0))) 14308 (set (match_dup 0) 14309 (plus:DI (match_dup 1) 14310 (const_int -1)))]) 14311 (set (pc) (if_then_else (match_dup 7) 14312 (match_dup 5) 14313 (match_dup 6)))] 14314 " 14315{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 14316 const0_rtx); }") 14317 14318(define_split 14319 [(set (pc) 14320 (if_then_else (match_operator 2 "comparison_operator" 14321 [(match_operand:DI 1 "gpc_reg_operand" "") 14322 (const_int 1)]) 14323 (match_operand 5 "" "") 14324 (match_operand 6 "" ""))) 14325 (set (match_operand:DI 0 "nonimmediate_operand" "") 14326 (plus:DI (match_dup 1) (const_int -1))) 14327 (clobber (match_scratch:CC 3 "")) 14328 (clobber (match_scratch:DI 4 ""))] 14329 "TARGET_64BIT && reload_completed 14330 && ! gpc_reg_operand (operands[0], DImode)" 14331 [(parallel [(set (match_dup 3) 14332 (compare:CC (plus:DI (match_dup 1) 14333 (const_int -1)) 14334 (const_int 0))) 14335 (set (match_dup 4) 14336 (plus:DI (match_dup 1) 14337 (const_int -1)))]) 14338 (set (match_dup 0) 14339 (match_dup 4)) 14340 (set (pc) (if_then_else (match_dup 7) 14341 (match_dup 5) 14342 (match_dup 6)))] 14343 " 14344{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 14345 const0_rtx); }") 14346 14347(define_insn "trap" 14348 [(trap_if (const_int 1) (const_int 0))] 14349 "" 14350 "{t 31,0,0|trap}") 14351 14352(define_expand "conditional_trap" 14353 [(trap_if (match_operator 0 "trap_comparison_operator" 14354 [(match_dup 2) (match_dup 3)]) 14355 (match_operand 1 "const_int_operand" ""))] 14356 "" 14357 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; 14358 operands[2] = rs6000_compare_op0; 14359 operands[3] = rs6000_compare_op1;") 14360 14361(define_insn "" 14362 [(trap_if (match_operator 0 "trap_comparison_operator" 14363 [(match_operand:SI 1 "register_operand" "r") 14364 (match_operand:SI 2 "reg_or_short_operand" "rI")]) 14365 (const_int 0))] 14366 "" 14367 "{t|tw}%V0%I2 %1,%2") 14368 14369(define_insn "" 14370 [(trap_if (match_operator 0 "trap_comparison_operator" 14371 [(match_operand:DI 1 "register_operand" "r") 14372 (match_operand:DI 2 "reg_or_short_operand" "rI")]) 14373 (const_int 0))] 14374 "TARGET_POWERPC64" 14375 "td%V0%I2 %1,%2") 14376 14377;; Insns related to generating the function prologue and epilogue. 14378 14379(define_expand "prologue" 14380 [(use (const_int 0))] 14381 "TARGET_SCHED_PROLOG" 14382 " 14383{ 14384 rs6000_emit_prologue (); 14385 DONE; 14386}") 14387 14388(define_insn "*movesi_from_cr_one" 14389 [(match_parallel 0 "mfcr_operation" 14390 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 14391 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") 14392 (match_operand 3 "immediate_operand" "n")] 14393 UNSPEC_MOVESI_FROM_CR))])] 14394 "TARGET_MFCRF" 14395 "* 14396{ 14397 int mask = 0; 14398 int i; 14399 for (i = 0; i < XVECLEN (operands[0], 0); i++) 14400 { 14401 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); 14402 operands[4] = GEN_INT (mask); 14403 output_asm_insn (\"mfcr %1,%4\", operands); 14404 } 14405 return \"\"; 14406}" 14407 [(set_attr "type" "mfcrf")]) 14408 14409(define_insn "movesi_from_cr" 14410 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 14411 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) 14412 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 14413 UNSPEC_MOVESI_FROM_CR))] 14414 "" 14415 "mfcr %0" 14416 [(set_attr "type" "mfcr")]) 14417 14418(define_insn "*stmw" 14419 [(match_parallel 0 "stmw_operation" 14420 [(set (match_operand:SI 1 "memory_operand" "=m") 14421 (match_operand:SI 2 "gpc_reg_operand" "r"))])] 14422 "TARGET_MULTIPLE" 14423 "{stm|stmw} %2,%1") 14424 14425(define_insn "*save_fpregs_si" 14426 [(match_parallel 0 "any_operand" 14427 [(clobber (match_operand:SI 1 "register_operand" "=l")) 14428 (use (match_operand:SI 2 "call_operand" "s")) 14429 (set (match_operand:DF 3 "memory_operand" "=m") 14430 (match_operand:DF 4 "gpc_reg_operand" "f"))])] 14431 "TARGET_32BIT" 14432 "bl %z2" 14433 [(set_attr "type" "branch") 14434 (set_attr "length" "4")]) 14435 14436(define_insn "*save_fpregs_di" 14437 [(match_parallel 0 "any_operand" 14438 [(clobber (match_operand:DI 1 "register_operand" "=l")) 14439 (use (match_operand:DI 2 "call_operand" "s")) 14440 (set (match_operand:DF 3 "memory_operand" "=m") 14441 (match_operand:DF 4 "gpc_reg_operand" "f"))])] 14442 "TARGET_64BIT" 14443 "bl %z2" 14444 [(set_attr "type" "branch") 14445 (set_attr "length" "4")]) 14446 14447; These are to explain that changes to the stack pointer should 14448; not be moved over stores to stack memory. 14449(define_insn "stack_tie" 14450 [(set (match_operand:BLK 0 "memory_operand" "+m") 14451 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] 14452 "" 14453 "" 14454 [(set_attr "length" "0")]) 14455 14456 14457(define_expand "epilogue" 14458 [(use (const_int 0))] 14459 "TARGET_SCHED_PROLOG" 14460 " 14461{ 14462 rs6000_emit_epilogue (FALSE); 14463 DONE; 14464}") 14465 14466; On some processors, doing the mtcrf one CC register at a time is 14467; faster (like on the 604e). On others, doing them all at once is 14468; faster; for instance, on the 601 and 750. 14469 14470(define_expand "movsi_to_cr_one" 14471 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 14472 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 14473 (match_dup 2)] UNSPEC_MOVESI_TO_CR))] 14474 "" 14475 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") 14476 14477(define_insn "*movsi_to_cr" 14478 [(match_parallel 0 "mtcrf_operation" 14479 [(set (match_operand:CC 1 "cc_reg_operand" "=y") 14480 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") 14481 (match_operand 3 "immediate_operand" "n")] 14482 UNSPEC_MOVESI_TO_CR))])] 14483 "" 14484 "* 14485{ 14486 int mask = 0; 14487 int i; 14488 for (i = 0; i < XVECLEN (operands[0], 0); i++) 14489 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); 14490 operands[4] = GEN_INT (mask); 14491 return \"mtcrf %4,%2\"; 14492}" 14493 [(set_attr "type" "mtcr")]) 14494 14495(define_insn "*mtcrfsi" 14496 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 14497 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 14498 (match_operand 2 "immediate_operand" "n")] 14499 UNSPEC_MOVESI_TO_CR))] 14500 "GET_CODE (operands[0]) == REG 14501 && CR_REGNO_P (REGNO (operands[0])) 14502 && GET_CODE (operands[2]) == CONST_INT 14503 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" 14504 "mtcrf %R0,%1" 14505 [(set_attr "type" "mtcr")]) 14506 14507; The load-multiple instructions have similar properties. 14508; Note that "load_multiple" is a name known to the machine-independent 14509; code that actually corresponds to the powerpc load-string. 14510 14511(define_insn "*lmw" 14512 [(match_parallel 0 "lmw_operation" 14513 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 14514 (match_operand:SI 2 "memory_operand" "m"))])] 14515 "TARGET_MULTIPLE" 14516 "{lm|lmw} %1,%2") 14517 14518(define_insn "*return_internal_si" 14519 [(return) 14520 (use (match_operand:SI 0 "register_operand" "lc"))] 14521 "TARGET_32BIT" 14522 "b%T0" 14523 [(set_attr "type" "jmpreg")]) 14524 14525(define_insn "*return_internal_di" 14526 [(return) 14527 (use (match_operand:DI 0 "register_operand" "lc"))] 14528 "TARGET_64BIT" 14529 "b%T0" 14530 [(set_attr "type" "jmpreg")]) 14531 14532; FIXME: This would probably be somewhat simpler if the Cygnus sibcall 14533; stuff was in GCC. Oh, and "any_operand" is a bit flexible... 14534 14535(define_insn "*return_and_restore_fpregs_si" 14536 [(match_parallel 0 "any_operand" 14537 [(return) 14538 (use (match_operand:SI 1 "register_operand" "l")) 14539 (use (match_operand:SI 2 "call_operand" "s")) 14540 (set (match_operand:DF 3 "gpc_reg_operand" "=f") 14541 (match_operand:DF 4 "memory_operand" "m"))])] 14542 "TARGET_32BIT" 14543 "b %z2") 14544 14545(define_insn "*return_and_restore_fpregs_di" 14546 [(match_parallel 0 "any_operand" 14547 [(return) 14548 (use (match_operand:DI 1 "register_operand" "l")) 14549 (use (match_operand:DI 2 "call_operand" "s")) 14550 (set (match_operand:DF 3 "gpc_reg_operand" "=f") 14551 (match_operand:DF 4 "memory_operand" "m"))])] 14552 "TARGET_64BIT" 14553 "b %z2") 14554 14555; This is used in compiling the unwind routines. 14556(define_expand "eh_return" 14557 [(use (match_operand 0 "general_operand" ""))] 14558 "" 14559 " 14560{ 14561 if (TARGET_32BIT) 14562 emit_insn (gen_eh_set_lr_si (operands[0])); 14563 else 14564 emit_insn (gen_eh_set_lr_di (operands[0])); 14565 DONE; 14566}") 14567 14568; We can't expand this before we know where the link register is stored. 14569(define_insn "eh_set_lr_si" 14570 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 14571 UNSPECV_EH_RR) 14572 (clobber (match_scratch:SI 1 "=&b"))] 14573 "TARGET_32BIT" 14574 "#") 14575 14576(define_insn "eh_set_lr_di" 14577 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 14578 UNSPECV_EH_RR) 14579 (clobber (match_scratch:DI 1 "=&b"))] 14580 "TARGET_64BIT" 14581 "#") 14582 14583(define_split 14584 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) 14585 (clobber (match_scratch 1 ""))] 14586 "reload_completed" 14587 [(const_int 0)] 14588 " 14589{ 14590 rs6000_emit_eh_reg_restore (operands[0], operands[1]); 14591 DONE; 14592}") 14593 14594(define_insn "prefetch" 14595 [(prefetch (match_operand:V4SI 0 "address_operand" "p") 14596 (match_operand:SI 1 "const_int_operand" "n") 14597 (match_operand:SI 2 "const_int_operand" "n"))] 14598 "TARGET_POWERPC" 14599 "* 14600{ 14601 if (GET_CODE (operands[0]) == REG) 14602 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; 14603 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; 14604}" 14605 [(set_attr "type" "load")]) 14606 14607(include "altivec.md") 14608(include "spe.md") 14609