rs6000.md revision 104752
1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3;; 1999, 2000, 2001 Free Software Foundation, Inc. 4;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 5 6;; This file is part of GNU CC. 7 8;; GNU CC is free software; you can redistribute it and/or modify 9;; it under the terms of the GNU General Public License as published by 10;; the Free Software Foundation; either version 2, or (at your option) 11;; any later version. 12 13;; GNU CC is distributed in the hope that it will be useful, 14;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16;; GNU General Public License for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GNU CC; see the file COPYING. If not, write to 20;; the Free Software Foundation, 59 Temple Place - Suite 330, 21;; Boston, MA 02111-1307, USA. 22 23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 24 25;; `unspec' values used in rs6000.md: 26;; Number Use 27;; 0 frsp for POWER machines 28;; 0/v blockage 29;; 5 used to tie the stack contents and the stack pointer 30;; 6 address of a word pointing to the TOC 31;; 7 address of the TOC (more-or-less) 32;; 8 movsi_got 33;; 9/v eh_reg_restore 34;; 10 fctiwz 35;; 19 movesi_from_cr 36;; 20 movesi_to_cr 37 38;; Define an insn type attribute. This is used in function unit delay 39;; computations. 40(define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec" 41 (const_string "integer")) 42 43;; Length (in bytes). 44; '(pc)' in the following doesn't include the instruction itself; it is 45; calculated as if the instruction had zero size. 46(define_attr "length" "" 47 (if_then_else (eq_attr "type" "branch") 48 (if_then_else (and (ge (minus (match_dup 0) (pc)) 49 (const_int -32768)) 50 (lt (minus (match_dup 0) (pc)) 51 (const_int 32764))) 52 (const_int 4) 53 (const_int 8)) 54 (const_int 4))) 55 56;; Processor type -- this attribute must exactly match the processor_type 57;; enumeration in rs6000.h. 58 59(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450" 60 (const (symbol_ref "rs6000_cpu_attr"))) 61 62; (define_function_unit NAME MULTIPLICITY SIMULTANEITY 63; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) 64 65; Load/Store Unit -- pure PowerPC only 66; (POWER and 601 use Integer Unit) 67(define_function_unit "lsu" 1 0 68 (and (eq_attr "type" "load") 69 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) 70 2 1) 71 72(define_function_unit "lsu" 1 0 73 (and (eq_attr "type" "load,vecload") 74 (eq_attr "cpu" "ppc7450")) 75 3 1) 76 77(define_function_unit "lsu" 1 0 78 (and (eq_attr "type" "store,fpstore") 79 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630")) 80 1 1) 81 82(define_function_unit "lsu" 1 0 83 (and (eq_attr "type" "store,fpstore") 84 (eq_attr "cpu" "ppc750,ppc7400")) 85 2 1) 86 87(define_function_unit "lsu" 1 0 88 (and (eq_attr "type" "store,vecstore") 89 (eq_attr "cpu" "ppc7450")) 90 3 1) 91 92(define_function_unit "lsu" 1 0 93 (and (eq_attr "type" "fpstore") 94 (eq_attr "cpu" "ppc7450")) 95 3 3) 96 97(define_function_unit "lsu" 1 0 98 (and (eq_attr "type" "fpload") 99 (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400")) 100 2 1) 101 102(define_function_unit "lsu" 1 0 103 (and (eq_attr "type" "fpload") 104 (eq_attr "cpu" "ppc7450")) 105 4 1) 106 107(define_function_unit "lsu" 1 0 108 (and (eq_attr "type" "fpload") 109 (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) 110 3 1) 111 112(define_function_unit "iu" 1 0 113 (and (eq_attr "type" "load") 114 (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601")) 115 2 1) 116 117(define_function_unit "iu" 1 0 118 (and (eq_attr "type" "store,fpstore") 119 (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601")) 120 1 1) 121 122(define_function_unit "fpu" 1 0 123 (and (eq_attr "type" "fpstore") 124 (eq_attr "cpu" "rios1,ppc601")) 125 0 1) 126 127(define_function_unit "iu" 1 0 128 (and (eq_attr "type" "fpload") 129 (eq_attr "cpu" "rios1")) 130 2 1) 131 132(define_function_unit "iu" 1 0 133 (and (eq_attr "type" "fpload") 134 (eq_attr "cpu" "ppc601")) 135 3 1) 136 137(define_function_unit "iu2" 2 0 138 (and (eq_attr "type" "load,fpload") 139 (eq_attr "cpu" "rios2")) 140 2 1) 141 142(define_function_unit "iu2" 2 0 143 (and (eq_attr "type" "store,fpstore") 144 (eq_attr "cpu" "rios2")) 145 1 1) 146 147; Integer Unit (RIOS1, PPC601, PPC603, RS64a) 148(define_function_unit "iu" 1 0 149 (and (eq_attr "type" "integer") 150 (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603")) 151 1 1) 152 153(define_function_unit "iu" 1 0 154 (and (eq_attr "type" "cr_logical") 155 (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601")) 156 1 1) 157 158(define_function_unit "iu" 1 0 159 (and (eq_attr "type" "imul,imul2,imul3") 160 (eq_attr "cpu" "ppc403")) 161 4 4) 162 163(define_function_unit "iu" 1 0 164 (and (eq_attr "type" "imul") 165 (eq_attr "cpu" "ppc405")) 166 4 3) 167 168(define_function_unit "iu" 1 0 169 (and (eq_attr "type" "imul2,imul3") 170 (eq_attr "cpu" "ppc405")) 171 3 2) 172 173(define_function_unit "iu" 1 0 174 (and (eq_attr "type" "imul") 175 (eq_attr "cpu" "rios1")) 176 5 5) 177 178(define_function_unit "iu" 1 0 179 (and (eq_attr "type" "imul2") 180 (eq_attr "cpu" "rios1")) 181 4 4) 182 183(define_function_unit "iu" 1 0 184 (and (eq_attr "type" "imul3") 185 (eq_attr "cpu" "rios1")) 186 3 3) 187 188(define_function_unit "iu" 1 0 189 (and (eq_attr "type" "imul,imul2,imul3") 190 (eq_attr "cpu" "ppc601,ppc603")) 191 5 5) 192 193(define_function_unit "iu" 1 0 194 (and (eq_attr "type" "imul") 195 (eq_attr "cpu" "rs64a")) 196 20 20) 197 198(define_function_unit "iu" 1 0 199 (and (eq_attr "type" "imul2") 200 (eq_attr "cpu" "rs64a")) 201 12 12) 202 203(define_function_unit "iu" 1 0 204 (and (eq_attr "type" "imul3") 205 (eq_attr "cpu" "rs64a")) 206 8 8) 207 208(define_function_unit "iu" 1 0 209 (and (eq_attr "type" "lmul") 210 (eq_attr "cpu" "rs64a")) 211 34 34) 212 213(define_function_unit "iu" 1 0 214 (and (eq_attr "type" "idiv") 215 (eq_attr "cpu" "rios1")) 216 19 19) 217 218(define_function_unit "iu" 1 0 219 (and (eq_attr "type" "idiv") 220 (eq_attr "cpu" "rs64a")) 221 66 66) 222 223(define_function_unit "iu" 1 0 224 (and (eq_attr "type" "ldiv") 225 (eq_attr "cpu" "rs64a")) 226 66 66) 227 228(define_function_unit "iu" 1 0 229 (and (eq_attr "type" "idiv") 230 (eq_attr "cpu" "ppc403")) 231 33 33) 232 233(define_function_unit "iu" 1 0 234 (and (eq_attr "type" "idiv") 235 (eq_attr "cpu" "ppc405")) 236 35 35) 237 238(define_function_unit "iu" 1 0 239 (and (eq_attr "type" "idiv") 240 (eq_attr "cpu" "ppc601")) 241 36 36) 242 243(define_function_unit "iu" 1 0 244 (and (eq_attr "type" "idiv") 245 (eq_attr "cpu" "ppc603")) 246 37 36) 247 248; RIOS2 has two integer units: a primary one which can perform all 249; operations and a secondary one which is fed in lock step with the first 250; and can perform "simple" integer operations. 251; To catch this we define a 'dummy' imuldiv-unit that is also needed 252; for the complex insns. 253(define_function_unit "iu2" 2 0 254 (and (eq_attr "type" "integer") 255 (eq_attr "cpu" "rios2")) 256 1 1) 257 258(define_function_unit "iu2" 2 0 259 (and (eq_attr "type" "imul,imul2,imul3") 260 (eq_attr "cpu" "rios2")) 261 2 2) 262 263(define_function_unit "iu2" 2 0 264 (and (eq_attr "type" "idiv") 265 (eq_attr "cpu" "rios2")) 266 13 13) 267 268(define_function_unit "imuldiv" 1 0 269 (and (eq_attr "type" "imul,imul2,imul3") 270 (eq_attr "cpu" "rios2")) 271 2 2) 272 273(define_function_unit "imuldiv" 1 0 274 (and (eq_attr "type" "idiv") 275 (eq_attr "cpu" "rios2")) 276 13 13) 277 278; MPCCORE has separate IMUL/IDIV unit for multicycle instructions 279; Divide latency varies greatly from 2-11, use 6 as average 280(define_function_unit "imuldiv" 1 0 281 (and (eq_attr "type" "imul,imul2,imul3") 282 (eq_attr "cpu" "mpccore")) 283 2 1) 284 285(define_function_unit "imuldiv" 1 0 286 (and (eq_attr "type" "idiv") 287 (eq_attr "cpu" "mpccore")) 288 6 6) 289 290; PPC604{,e} has two units that perform integer operations 291; and one unit for divide/multiply operations (and move 292; from/to spr). 293(define_function_unit "iu2" 2 0 294 (and (eq_attr "type" "integer") 295 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 296 1 1) 297 298(define_function_unit "imuldiv" 1 0 299 (and (eq_attr "type" "imul,imul2,imul3") 300 (eq_attr "cpu" "ppc604")) 301 4 2) 302 303(define_function_unit "imuldiv" 1 0 304 (and (eq_attr "type" "imul,imul2,imul3") 305 (eq_attr "cpu" "ppc604e")) 306 2 1) 307 308(define_function_unit "imuldiv" 1 0 309 (and (eq_attr "type" "imul") 310 (eq_attr "cpu" "ppc620,ppc630")) 311 5 3) 312 313(define_function_unit "imuldiv" 1 0 314 (and (eq_attr "type" "imul2") 315 (eq_attr "cpu" "ppc620,ppc630")) 316 4 3) 317 318(define_function_unit "imuldiv" 1 0 319 (and (eq_attr "type" "imul3") 320 (eq_attr "cpu" "ppc620,ppc630")) 321 3 3) 322 323(define_function_unit "imuldiv" 1 0 324 (and (eq_attr "type" "lmul") 325 (eq_attr "cpu" "ppc620,ppc630")) 326 7 5) 327 328(define_function_unit "imuldiv" 1 0 329 (and (eq_attr "type" "idiv") 330 (eq_attr "cpu" "ppc604,ppc604e")) 331 20 19) 332 333(define_function_unit "imuldiv" 1 0 334 (and (eq_attr "type" "idiv") 335 (eq_attr "cpu" "ppc620")) 336 37 36) 337 338(define_function_unit "imuldiv" 1 0 339 (and (eq_attr "type" "idiv") 340 (eq_attr "cpu" "ppc630")) 341 21 20) 342 343(define_function_unit "imuldiv" 1 0 344 (and (eq_attr "type" "ldiv") 345 (eq_attr "cpu" "ppc620,ppc630")) 346 37 36) 347 348; PPC7450 has 3 integer units (for most integer insns) and one mul/div 349; unit, which also does CR-logical insns and move to/from SPR. 350; It also has 4 vector units, one for each type of vector instruction. 351; However, we can only dispatch 2 instructions per cycle. 352; We model this as saying that dispatching two of the same type of instruction 353; in a row incurs a single cycle delay. 354(define_function_unit "iu3" 3 0 355 (and (eq_attr "type" "integer") 356 (eq_attr "cpu" "ppc7450")) 357 1 1) 358 359(define_function_unit "imuldiv" 1 0 360 (and (eq_attr "type" "imul") 361 (eq_attr "cpu" "ppc7450")) 362 4 2) 363 364(define_function_unit "imuldiv" 1 0 365 (and (eq_attr "type" "imul2,imul3") 366 (eq_attr "cpu" "ppc7450")) 367 3 1) 368 369(define_function_unit "imuldiv" 1 0 370 (and (eq_attr "type" "idiv") 371 (eq_attr "cpu" "ppc7450")) 372 23 23) 373 374(define_function_unit "imuldiv" 1 0 375 (and (eq_attr "type" "cr_logical") 376 (eq_attr "cpu" "ppc7450")) 377 1 1) 378(define_function_unit "vec_alu2" 2 0 379 (and (eq_attr "type" "vecsimple") 380 (eq_attr "cpu" "ppc7450")) 381 1 2 [(eq_attr "type" "vecsimple")]) 382(define_function_unit "vec_alu2" 2 0 383 (and (eq_attr "type" "vecsimple") 384 (eq_attr "cpu" "ppc7450")) 385 1 1 [(eq_attr "type" "!vecsimple")]) 386(define_function_unit "vec_alu2" 2 0 387 (and (eq_attr "type" "veccomplex") 388 (eq_attr "cpu" "ppc7450")) 389 4 2 [(eq_attr "type" "veccomplex")]) 390(define_function_unit "vec_alu2" 2 0 391 (and (eq_attr "type" "veccomplex") 392 (eq_attr "cpu" "ppc7450")) 393 4 1 [(eq_attr "type" "!veccomplex")]) 394(define_function_unit "vec_alu2" 2 0 395 (and (eq_attr "type" "veccmp") 396 (eq_attr "cpu" "ppc7450")) 397 2 2 [(eq_attr "type" "veccmp")]) 398(define_function_unit "vec_alu2" 2 0 399 (and (eq_attr "type" "veccmp") 400 (eq_attr "cpu" "ppc7450")) 401 2 1 [(eq_attr "type" "!veccmp")]) 402(define_function_unit "vec_alu2" 2 0 403 (and (eq_attr "type" "vecfloat") 404 (eq_attr "cpu" "ppc7450")) 405 4 2 [(eq_attr "type" "vecfloat")]) 406(define_function_unit "vec_alu2" 2 0 407 (and (eq_attr "type" "vecfloat") 408 (eq_attr "cpu" "ppc7450")) 409 4 1 [(eq_attr "type" "!vecfloat")]) 410(define_function_unit "vec_alu2" 2 0 411 (and (eq_attr "type" "vecperm") 412 (eq_attr "cpu" "ppc7450")) 413 2 2 [(eq_attr "type" "vecperm")]) 414(define_function_unit "vec_alu2" 2 0 415 (and (eq_attr "type" "vecperm") 416 (eq_attr "cpu" "ppc7450")) 417 2 1 [(eq_attr "type" "!vecperm")]) 418 419; PPC750 has two integer units: a primary one which can perform all 420; operations and a secondary one which is fed in lock step with the first 421; and can perform "simple" integer operations. 422; To catch this we define a 'dummy' imuldiv-unit that is also needed 423; for the complex insns. 424(define_function_unit "iu2" 2 0 425 (and (eq_attr "type" "integer") 426 (eq_attr "cpu" "ppc750,ppc7400")) 427 1 1) 428 429(define_function_unit "iu2" 2 0 430 (and (eq_attr "type" "imul") 431 (eq_attr "cpu" "ppc750,ppc7400")) 432 4 4) 433 434(define_function_unit "iu2" 2 0 435 (and (eq_attr "type" "imul2") 436 (eq_attr "cpu" "ppc750,ppc7400")) 437 3 2) 438 439(define_function_unit "iu2" 2 0 440 (and (eq_attr "type" "imul3") 441 (eq_attr "cpu" "ppc750,ppc7400")) 442 2 1) 443 444(define_function_unit "iu2" 2 0 445 (and (eq_attr "type" "idiv") 446 (eq_attr "cpu" "ppc750,ppc7400")) 447 19 19) 448 449(define_function_unit "imuldiv" 1 0 450 (and (eq_attr "type" "imul") 451 (eq_attr "cpu" "ppc750,ppc7400")) 452 4 4) 453 454(define_function_unit "imuldiv" 1 0 455 (and (eq_attr "type" "imul2") 456 (eq_attr "cpu" "ppc750,ppc7400")) 457 3 2) 458 459(define_function_unit "imuldiv" 1 0 460 (and (eq_attr "type" "imul3") 461 (eq_attr "cpu" "ppc750,ppc7400")) 462 2 1) 463 464(define_function_unit "imuldiv" 1 0 465 (and (eq_attr "type" "idiv") 466 (eq_attr "cpu" "ppc750,ppc7400")) 467 19 19) 468 469; CR-logical operations are execute-serialized, that is they don't 470; start (and block the function unit) until all preceding operations 471; have finished. They don't block dispatch of other insns, though. 472; I've imitated this by giving them longer latency. 473(define_function_unit "sru" 1 0 474 (and (eq_attr "type" "cr_logical") 475 (eq_attr "cpu" "ppc603,ppc750,ppc7400")) 476 3 2) 477 478; compare is done on integer unit, but feeds insns which 479; execute on the branch unit. 480(define_function_unit "iu" 1 0 481 (and (eq_attr "type" "compare") 482 (eq_attr "cpu" "rios1")) 483 4 1) 484 485(define_function_unit "iu" 1 0 486 (and (eq_attr "type" "delayed_compare") 487 (eq_attr "cpu" "rios1")) 488 5 1) 489 490(define_function_unit "iu" 1 0 491 (and (eq_attr "type" "compare,delayed_compare") 492 (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) 493 3 1) 494 495; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare 496; and a following branch, to reduce mispredicts 497(define_function_unit "iu3" 3 0 498 (and (eq_attr "type" "compare,delayed_compare") 499 (eq_attr "cpu" "ppc7450")) 500 1 1) 501 502(define_function_unit "iu2" 2 0 503 (and (eq_attr "type" "compare,delayed_compare") 504 (eq_attr "cpu" "rios2")) 505 3 1) 506 507(define_function_unit "iu2" 2 0 508 (and (eq_attr "type" "compare,delayed_compare") 509 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) 510 1 1) 511 512; fp compare uses fp unit 513(define_function_unit "fpu" 1 0 514 (and (eq_attr "type" "fpcompare") 515 (eq_attr "cpu" "rios1")) 516 9 1) 517 518; rios1 and rios2 have different fpcompare delays 519(define_function_unit "fpu2" 2 0 520 (and (eq_attr "type" "fpcompare") 521 (eq_attr "cpu" "rios2,ppc630")) 522 5 1) 523 524; on ppc601 and ppc603, fpcompare takes also 2 cycles from 525; the integer unit 526; here we do not define delays, just occupy the unit. The dependencies 527; will be assigned by the fpcompare definition in the fpu. 528(define_function_unit "iu" 1 0 529 (and (eq_attr "type" "fpcompare") 530 (eq_attr "cpu" "ppc601,ppc603")) 531 0 2) 532 533; fp compare uses fp unit 534(define_function_unit "fpu" 1 0 535 (and (eq_attr "type" "fpcompare") 536 (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) 537 5 1) 538 539(define_function_unit "fpu" 1 0 540 (and (eq_attr "type" "fpcompare") 541 (eq_attr "cpu" "ppc750,ppc7400,ppc7450")) 542 3 1) 543 544(define_function_unit "fpu" 1 0 545 (and (eq_attr "type" "fpcompare") 546 (eq_attr "cpu" "mpccore")) 547 1 1) 548 549(define_function_unit "bpu" 1 0 550 (and (eq_attr "type" "mtjmpr") 551 (eq_attr "cpu" "rios1,rios2,rs64a")) 552 5 1) 553 554(define_function_unit "bpu" 1 0 555 (and (eq_attr "type" "mtjmpr") 556 (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) 557 4 1) 558 559(define_function_unit "sru" 1 0 560 (and (eq_attr "type" "mtjmpr") 561 (eq_attr "cpu" "ppc750,ppc7400")) 562 2 2) 563 564(define_function_unit "imuldiv" 1 0 565 (and (eq_attr "type" "mtjmpr") 566 (eq_attr "cpu" "ppc7450")) 567 2 2) 568 569(define_function_unit "bpu" 1 0 570 (and (eq_attr "type" "cr_logical") 571 (eq_attr "cpu" "rios1,rios2,ppc604")) 572 4 1) 573 574(define_function_unit "cru" 1 0 575 (and (eq_attr "type" "cr_logical") 576 (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a")) 577 1 1) 578 579; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. 580(define_function_unit "bpu" 1 0 581 (eq_attr "type" "jmpreg") 582 1 1) 583 584(define_function_unit "bpu" 1 0 585 (eq_attr "type" "branch") 586 1 1) 587 588; Floating Point Unit 589(define_function_unit "fpu" 1 0 590 (and (eq_attr "type" "fp,dmul") 591 (eq_attr "cpu" "rios1")) 592 2 1) 593 594(define_function_unit "fpu" 1 0 595 (and (eq_attr "type" "fp") 596 (eq_attr "cpu" "rs64a,mpccore")) 597 4 2) 598 599(define_function_unit "fpu" 1 0 600 (and (eq_attr "type" "fp") 601 (eq_attr "cpu" "ppc601")) 602 4 1) 603 604(define_function_unit "fpu" 1 0 605 (and (eq_attr "type" "fp") 606 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400")) 607 3 1) 608 609(define_function_unit "fpu" 1 0 610 (and (eq_attr "type" "fp,dmul") 611 (eq_attr "cpu" "ppc7450")) 612 5 1) 613 614(define_function_unit "fpu" 1 0 615 (and (eq_attr "type" "dmul") 616 (eq_attr "cpu" "rs64a")) 617 7 2) 618 619(define_function_unit "fpu" 1 0 620 (and (eq_attr "type" "dmul") 621 (eq_attr "cpu" "mpccore")) 622 5 5) 623 624(define_function_unit "fpu" 1 0 625 (and (eq_attr "type" "dmul") 626 (eq_attr "cpu" "ppc601")) 627 5 2) 628 629; is this true? 630(define_function_unit "fpu" 1 0 631 (and (eq_attr "type" "dmul") 632 (eq_attr "cpu" "ppc603,ppc750")) 633 4 2) 634 635(define_function_unit "fpu" 1 0 636 (and (eq_attr "type" "dmul") 637 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400")) 638 3 1) 639 640(define_function_unit "fpu" 1 0 641 (and (eq_attr "type" "sdiv,ddiv") 642 (eq_attr "cpu" "rios1")) 643 19 19) 644 645(define_function_unit "fpu" 1 0 646 (and (eq_attr "type" "sdiv") 647 (eq_attr "cpu" "rs64a")) 648 31 31) 649 650(define_function_unit "fpu" 1 0 651 (and (eq_attr "type" "sdiv") 652 (eq_attr "cpu" "ppc601,ppc750,ppc7400")) 653 17 17) 654 655(define_function_unit "fpu" 1 0 656 (and (eq_attr "type" "sdiv") 657 (eq_attr "cpu" "ppc7450")) 658 21 21) 659 660(define_function_unit "fpu" 1 0 661 (and (eq_attr "type" "sdiv") 662 (eq_attr "cpu" "mpccore")) 663 10 10) 664 665(define_function_unit "fpu" 1 0 666 (and (eq_attr "type" "sdiv") 667 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) 668 18 18) 669 670(define_function_unit "fpu" 1 0 671 (and (eq_attr "type" "ddiv") 672 (eq_attr "cpu" "mpccore")) 673 17 17) 674 675(define_function_unit "fpu" 1 0 676 (and (eq_attr "type" "ddiv") 677 (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400")) 678 31 31) 679 680(define_function_unit "fpu" 1 0 681 (and (eq_attr "type" "ddiv") 682 (eq_attr "cpu" "ppc7450")) 683 35 35) 684 685(define_function_unit "fpu" 1 0 686 (and (eq_attr "type" "ddiv") 687 (eq_attr "cpu" "ppc603")) 688 33 33) 689 690(define_function_unit "fpu" 1 0 691 (and (eq_attr "type" "ssqrt") 692 (eq_attr "cpu" "ppc620")) 693 31 31) 694 695(define_function_unit "fpu" 1 0 696 (and (eq_attr "type" "dsqrt") 697 (eq_attr "cpu" "ppc620")) 698 31 31) 699 700; RIOS2 has two symmetric FPUs. 701(define_function_unit "fpu2" 2 0 702 (and (eq_attr "type" "fp") 703 (eq_attr "cpu" "rios2")) 704 2 1) 705 706(define_function_unit "fpu2" 2 0 707 (and (eq_attr "type" "fp") 708 (eq_attr "cpu" "ppc630")) 709 3 1) 710 711(define_function_unit "fpu2" 2 0 712 (and (eq_attr "type" "dmul") 713 (eq_attr "cpu" "rios2")) 714 2 1) 715 716(define_function_unit "fpu2" 2 0 717 (and (eq_attr "type" "dmul") 718 (eq_attr "cpu" "ppc630")) 719 3 1) 720 721(define_function_unit "fpu2" 2 0 722 (and (eq_attr "type" "sdiv,ddiv") 723 (eq_attr "cpu" "rios2")) 724 17 17) 725 726(define_function_unit "fpu2" 2 0 727 (and (eq_attr "type" "sdiv") 728 (eq_attr "cpu" "ppc630")) 729 17 17) 730 731(define_function_unit "fpu2" 2 0 732 (and (eq_attr "type" "ddiv") 733 (eq_attr "cpu" "ppc630")) 734 21 21) 735 736(define_function_unit "fpu2" 2 0 737 (and (eq_attr "type" "ssqrt,dsqrt") 738 (eq_attr "cpu" "rios2")) 739 26 26) 740 741(define_function_unit "fpu2" 2 0 742 (and (eq_attr "type" "ssqrt") 743 (eq_attr "cpu" "ppc630")) 744 18 18) 745 746(define_function_unit "fpu2" 2 0 747 (and (eq_attr "type" "dsqrt") 748 (eq_attr "cpu" "ppc630")) 749 26 26) 750 751 752;; Start with fixed-point load and store insns. Here we put only the more 753;; complex forms. Basic data transfer is done later. 754 755(define_expand "zero_extendqidi2" 756 [(set (match_operand:DI 0 "gpc_reg_operand" "") 757 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] 758 "TARGET_POWERPC64" 759 "") 760 761(define_insn "" 762 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 763 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 764 "TARGET_POWERPC64" 765 "@ 766 lbz%U1%X1 %0,%1 767 rldicl %0,%1,0,56" 768 [(set_attr "type" "load,*")]) 769 770(define_insn "" 771 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 772 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 773 (const_int 0))) 774 (clobber (match_scratch:DI 2 "=r,r"))] 775 "TARGET_POWERPC64" 776 "@ 777 rldicl. %2,%1,0,56 778 #" 779 [(set_attr "type" "compare") 780 (set_attr "length" "4,8")]) 781 782(define_split 783 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 784 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 785 (const_int 0))) 786 (clobber (match_scratch:DI 2 ""))] 787 "TARGET_POWERPC64 && reload_completed" 788 [(set (match_dup 2) 789 (zero_extend:DI (match_dup 1))) 790 (set (match_dup 0) 791 (compare:CC (match_dup 2) 792 (const_int 0)))] 793 "") 794 795(define_insn "" 796 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 797 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 798 (const_int 0))) 799 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 800 (zero_extend:DI (match_dup 1)))] 801 "TARGET_POWERPC64" 802 "@ 803 rldicl. %0,%1,0,56 804 #" 805 [(set_attr "type" "compare") 806 (set_attr "length" "4,8")]) 807 808(define_split 809 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 810 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 811 (const_int 0))) 812 (set (match_operand:DI 0 "gpc_reg_operand" "") 813 (zero_extend:DI (match_dup 1)))] 814 "TARGET_POWERPC64 && reload_completed" 815 [(set (match_dup 0) 816 (zero_extend:DI (match_dup 1))) 817 (set (match_dup 2) 818 (compare:CC (match_dup 0) 819 (const_int 0)))] 820 "") 821 822(define_insn "extendqidi2" 823 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 824 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] 825 "TARGET_POWERPC64" 826 "extsb %0,%1") 827 828(define_insn "" 829 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 830 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 831 (const_int 0))) 832 (clobber (match_scratch:DI 2 "=r,r"))] 833 "TARGET_POWERPC64" 834 "@ 835 extsb. %2,%1 836 #" 837 [(set_attr "type" "compare") 838 (set_attr "length" "4,8")]) 839 840(define_split 841 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 842 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 843 (const_int 0))) 844 (clobber (match_scratch:DI 2 ""))] 845 "TARGET_POWERPC64 && reload_completed" 846 [(set (match_dup 2) 847 (sign_extend:DI (match_dup 1))) 848 (set (match_dup 0) 849 (compare:CC (match_dup 2) 850 (const_int 0)))] 851 "") 852 853(define_insn "" 854 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 855 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 856 (const_int 0))) 857 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 858 (sign_extend:DI (match_dup 1)))] 859 "TARGET_POWERPC64" 860 "@ 861 extsb. %0,%1 862 #" 863 [(set_attr "type" "compare") 864 (set_attr "length" "4,8")]) 865 866(define_split 867 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 868 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 869 (const_int 0))) 870 (set (match_operand:DI 0 "gpc_reg_operand" "") 871 (sign_extend:DI (match_dup 1)))] 872 "TARGET_POWERPC64 && reload_completed" 873 [(set (match_dup 0) 874 (sign_extend:DI (match_dup 1))) 875 (set (match_dup 2) 876 (compare:CC (match_dup 0) 877 (const_int 0)))] 878 "") 879 880(define_expand "zero_extendhidi2" 881 [(set (match_operand:DI 0 "gpc_reg_operand" "") 882 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 883 "TARGET_POWERPC64" 884 "") 885 886(define_insn "" 887 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 888 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 889 "TARGET_POWERPC64" 890 "@ 891 lhz%U1%X1 %0,%1 892 rldicl %0,%1,0,48" 893 [(set_attr "type" "load,*")]) 894 895(define_insn "" 896 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 897 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 898 (const_int 0))) 899 (clobber (match_scratch:DI 2 "=r,r"))] 900 "TARGET_POWERPC64" 901 "@ 902 rldicl. %2,%1,0,48 903 #" 904 [(set_attr "type" "compare") 905 (set_attr "length" "4,8")]) 906 907(define_split 908 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 909 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 910 (const_int 0))) 911 (clobber (match_scratch:DI 2 ""))] 912 "TARGET_POWERPC64 && reload_completed" 913 [(set (match_dup 2) 914 (zero_extend:DI (match_dup 1))) 915 (set (match_dup 0) 916 (compare:CC (match_dup 2) 917 (const_int 0)))] 918 "") 919 920(define_insn "" 921 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 922 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 923 (const_int 0))) 924 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 925 (zero_extend:DI (match_dup 1)))] 926 "TARGET_POWERPC64" 927 "@ 928 rldicl. %0,%1,0,48 929 #" 930 [(set_attr "type" "compare") 931 (set_attr "length" "4,8")]) 932 933(define_split 934 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 935 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 936 (const_int 0))) 937 (set (match_operand:DI 0 "gpc_reg_operand" "") 938 (zero_extend:DI (match_dup 1)))] 939 "TARGET_POWERPC64 && reload_completed" 940 [(set (match_dup 0) 941 (zero_extend:DI (match_dup 1))) 942 (set (match_dup 2) 943 (compare:CC (match_dup 0) 944 (const_int 0)))] 945 "") 946 947(define_expand "extendhidi2" 948 [(set (match_operand:DI 0 "gpc_reg_operand" "") 949 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 950 "TARGET_POWERPC64" 951 "") 952 953(define_insn "" 954 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 955 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 956 "TARGET_POWERPC64" 957 "@ 958 lha%U1%X1 %0,%1 959 extsh %0,%1" 960 [(set_attr "type" "load,*")]) 961 962(define_insn "" 963 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 964 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 965 (const_int 0))) 966 (clobber (match_scratch:DI 2 "=r,r"))] 967 "TARGET_POWERPC64" 968 "@ 969 extsh. %2,%1 970 #" 971 [(set_attr "type" "compare") 972 (set_attr "length" "4,8")]) 973 974(define_split 975 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 976 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 977 (const_int 0))) 978 (clobber (match_scratch:DI 2 ""))] 979 "TARGET_POWERPC64 && reload_completed" 980 [(set (match_dup 2) 981 (sign_extend:DI (match_dup 1))) 982 (set (match_dup 0) 983 (compare:CC (match_dup 2) 984 (const_int 0)))] 985 "") 986 987(define_insn "" 988 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 989 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 990 (const_int 0))) 991 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 992 (sign_extend:DI (match_dup 1)))] 993 "TARGET_POWERPC64" 994 "@ 995 extsh. %0,%1 996 #" 997 [(set_attr "type" "compare") 998 (set_attr "length" "4,8")]) 999 1000(define_split 1001 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1002 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 1003 (const_int 0))) 1004 (set (match_operand:DI 0 "gpc_reg_operand" "") 1005 (sign_extend:DI (match_dup 1)))] 1006 "TARGET_POWERPC64 && reload_completed" 1007 [(set (match_dup 0) 1008 (sign_extend:DI (match_dup 1))) 1009 (set (match_dup 2) 1010 (compare:CC (match_dup 0) 1011 (const_int 0)))] 1012 "") 1013 1014(define_expand "zero_extendsidi2" 1015 [(set (match_operand:DI 0 "gpc_reg_operand" "") 1016 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 1017 "TARGET_POWERPC64" 1018 "") 1019 1020(define_insn "" 1021 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 1022 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] 1023 "TARGET_POWERPC64" 1024 "@ 1025 lwz%U1%X1 %0,%1 1026 rldicl %0,%1,0,32" 1027 [(set_attr "type" "load,*")]) 1028 1029(define_insn "" 1030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1031 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1032 (const_int 0))) 1033 (clobber (match_scratch:DI 2 "=r,r"))] 1034 "TARGET_POWERPC64" 1035 "@ 1036 rldicl. %2,%1,0,32 1037 #" 1038 [(set_attr "type" "compare") 1039 (set_attr "length" "4,8")]) 1040 1041(define_split 1042 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1043 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 1044 (const_int 0))) 1045 (clobber (match_scratch:DI 2 ""))] 1046 "TARGET_POWERPC64 && reload_completed" 1047 [(set (match_dup 2) 1048 (zero_extend:DI (match_dup 1))) 1049 (set (match_dup 0) 1050 (compare:CC (match_dup 2) 1051 (const_int 0)))] 1052 "") 1053 1054(define_insn "" 1055 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1056 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1057 (const_int 0))) 1058 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 1059 (zero_extend:DI (match_dup 1)))] 1060 "TARGET_POWERPC64" 1061 "@ 1062 rldicl. %0,%1,0,32 1063 #" 1064 [(set_attr "type" "compare") 1065 (set_attr "length" "4,8")]) 1066 1067(define_split 1068 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1069 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 1070 (const_int 0))) 1071 (set (match_operand:DI 0 "gpc_reg_operand" "") 1072 (zero_extend:DI (match_dup 1)))] 1073 "TARGET_POWERPC64 && reload_completed" 1074 [(set (match_dup 0) 1075 (zero_extend:DI (match_dup 1))) 1076 (set (match_dup 2) 1077 (compare:CC (match_dup 0) 1078 (const_int 0)))] 1079 "") 1080 1081(define_expand "extendsidi2" 1082 [(set (match_operand:DI 0 "gpc_reg_operand" "") 1083 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 1084 "TARGET_POWERPC64" 1085 "") 1086 1087(define_insn "" 1088 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 1089 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] 1090 "TARGET_POWERPC64" 1091 "@ 1092 lwa%U1%X1 %0,%1 1093 extsw %0,%1" 1094 [(set_attr "type" "load,*")]) 1095 1096(define_insn "" 1097 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1098 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1099 (const_int 0))) 1100 (clobber (match_scratch:DI 2 "=r,r"))] 1101 "TARGET_POWERPC64" 1102 "@ 1103 extsw. %2,%1 1104 #" 1105 [(set_attr "type" "compare") 1106 (set_attr "length" "4,8")]) 1107 1108(define_split 1109 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1110 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 1111 (const_int 0))) 1112 (clobber (match_scratch:DI 2 ""))] 1113 "TARGET_POWERPC64 && reload_completed" 1114 [(set (match_dup 2) 1115 (sign_extend:DI (match_dup 1))) 1116 (set (match_dup 0) 1117 (compare:CC (match_dup 2) 1118 (const_int 0)))] 1119 "") 1120 1121(define_insn "" 1122 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1123 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1124 (const_int 0))) 1125 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 1126 (sign_extend:DI (match_dup 1)))] 1127 "TARGET_POWERPC64" 1128 "@ 1129 extsw. %0,%1 1130 #" 1131 [(set_attr "type" "compare") 1132 (set_attr "length" "4,8")]) 1133 1134(define_split 1135 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1136 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 1137 (const_int 0))) 1138 (set (match_operand:DI 0 "gpc_reg_operand" "") 1139 (sign_extend:DI (match_dup 1)))] 1140 "TARGET_POWERPC64 && reload_completed" 1141 [(set (match_dup 0) 1142 (sign_extend:DI (match_dup 1))) 1143 (set (match_dup 2) 1144 (compare:CC (match_dup 0) 1145 (const_int 0)))] 1146 "") 1147 1148(define_expand "zero_extendqisi2" 1149 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1150 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] 1151 "" 1152 "") 1153 1154(define_insn "" 1155 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1156 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 1157 "" 1158 "@ 1159 lbz%U1%X1 %0,%1 1160 {rlinm|rlwinm} %0,%1,0,0xff" 1161 [(set_attr "type" "load,*")]) 1162 1163(define_insn "" 1164 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1165 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1166 (const_int 0))) 1167 (clobber (match_scratch:SI 2 "=r,r"))] 1168 "" 1169 "@ 1170 {andil.|andi.} %2,%1,0xff 1171 #" 1172 [(set_attr "type" "compare") 1173 (set_attr "length" "4,8")]) 1174 1175(define_split 1176 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1177 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 1178 (const_int 0))) 1179 (clobber (match_scratch:SI 2 ""))] 1180 "reload_completed" 1181 [(set (match_dup 2) 1182 (zero_extend:SI (match_dup 1))) 1183 (set (match_dup 0) 1184 (compare:CC (match_dup 2) 1185 (const_int 0)))] 1186 "") 1187 1188(define_insn "" 1189 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1190 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1191 (const_int 0))) 1192 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1193 (zero_extend:SI (match_dup 1)))] 1194 "" 1195 "@ 1196 {andil.|andi.} %0,%1,0xff 1197 #" 1198 [(set_attr "type" "compare") 1199 (set_attr "length" "4,8")]) 1200 1201(define_split 1202 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1203 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 1204 (const_int 0))) 1205 (set (match_operand:SI 0 "gpc_reg_operand" "") 1206 (zero_extend:SI (match_dup 1)))] 1207 "reload_completed" 1208 [(set (match_dup 0) 1209 (zero_extend:SI (match_dup 1))) 1210 (set (match_dup 2) 1211 (compare:CC (match_dup 0) 1212 (const_int 0)))] 1213 "") 1214 1215(define_expand "extendqisi2" 1216 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 1217 (use (match_operand:QI 1 "gpc_reg_operand" ""))] 1218 "" 1219 " 1220{ 1221 if (TARGET_POWERPC) 1222 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); 1223 else if (TARGET_POWER) 1224 emit_insn (gen_extendqisi2_power (operands[0], operands[1])); 1225 else 1226 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); 1227 DONE; 1228}") 1229 1230(define_insn "extendqisi2_ppc" 1231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1232 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] 1233 "TARGET_POWERPC" 1234 "extsb %0,%1") 1235 1236(define_insn "" 1237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1238 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1239 (const_int 0))) 1240 (clobber (match_scratch:SI 2 "=r,r"))] 1241 "TARGET_POWERPC" 1242 "@ 1243 extsb. %2,%1 1244 #" 1245 [(set_attr "type" "compare") 1246 (set_attr "length" "4,8")]) 1247 1248(define_split 1249 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1250 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 1251 (const_int 0))) 1252 (clobber (match_scratch:SI 2 ""))] 1253 "TARGET_POWERPC && reload_completed" 1254 [(set (match_dup 2) 1255 (sign_extend:SI (match_dup 1))) 1256 (set (match_dup 0) 1257 (compare:CC (match_dup 2) 1258 (const_int 0)))] 1259 "") 1260 1261(define_insn "" 1262 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1263 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1264 (const_int 0))) 1265 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1266 (sign_extend:SI (match_dup 1)))] 1267 "TARGET_POWERPC" 1268 "@ 1269 extsb. %0,%1 1270 #" 1271 [(set_attr "type" "compare") 1272 (set_attr "length" "4,8")]) 1273 1274(define_split 1275 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1276 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 1277 (const_int 0))) 1278 (set (match_operand:SI 0 "gpc_reg_operand" "") 1279 (sign_extend:SI (match_dup 1)))] 1280 "TARGET_POWERPC && reload_completed" 1281 [(set (match_dup 0) 1282 (sign_extend:SI (match_dup 1))) 1283 (set (match_dup 2) 1284 (compare:CC (match_dup 0) 1285 (const_int 0)))] 1286 "") 1287 1288(define_expand "extendqisi2_power" 1289 [(parallel [(set (match_dup 2) 1290 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 1291 (const_int 24))) 1292 (clobber (scratch:SI))]) 1293 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 1294 (ashiftrt:SI (match_dup 2) 1295 (const_int 24))) 1296 (clobber (scratch:SI))])] 1297 "TARGET_POWER" 1298 " 1299{ operands[1] = gen_lowpart (SImode, operands[1]); 1300 operands[2] = gen_reg_rtx (SImode); }") 1301 1302(define_expand "extendqisi2_no_power" 1303 [(set (match_dup 2) 1304 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 1305 (const_int 24))) 1306 (set (match_operand:SI 0 "gpc_reg_operand" "") 1307 (ashiftrt:SI (match_dup 2) 1308 (const_int 24)))] 1309 "! TARGET_POWER && ! TARGET_POWERPC" 1310 " 1311{ operands[1] = gen_lowpart (SImode, operands[1]); 1312 operands[2] = gen_reg_rtx (SImode); }") 1313 1314(define_expand "zero_extendqihi2" 1315 [(set (match_operand:HI 0 "gpc_reg_operand" "") 1316 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] 1317 "" 1318 "") 1319 1320(define_insn "" 1321 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 1322 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 1323 "" 1324 "@ 1325 lbz%U1%X1 %0,%1 1326 {rlinm|rlwinm} %0,%1,0,0xff" 1327 [(set_attr "type" "load,*")]) 1328 1329(define_insn "" 1330 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1331 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1332 (const_int 0))) 1333 (clobber (match_scratch:HI 2 "=r,r"))] 1334 "" 1335 "@ 1336 {andil.|andi.} %2,%1,0xff 1337 #" 1338 [(set_attr "type" "compare") 1339 (set_attr "length" "4,8")]) 1340 1341(define_split 1342 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1343 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 1344 (const_int 0))) 1345 (clobber (match_scratch:HI 2 ""))] 1346 "reload_completed" 1347 [(set (match_dup 2) 1348 (zero_extend:HI (match_dup 1))) 1349 (set (match_dup 0) 1350 (compare:CC (match_dup 2) 1351 (const_int 0)))] 1352 "") 1353 1354(define_insn "" 1355 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1356 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1357 (const_int 0))) 1358 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 1359 (zero_extend:HI (match_dup 1)))] 1360 "" 1361 "@ 1362 {andil.|andi.} %0,%1,0xff 1363 #" 1364 [(set_attr "type" "compare") 1365 (set_attr "length" "4,8")]) 1366 1367(define_split 1368 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1369 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 1370 (const_int 0))) 1371 (set (match_operand:HI 0 "gpc_reg_operand" "") 1372 (zero_extend:HI (match_dup 1)))] 1373 "reload_completed" 1374 [(set (match_dup 0) 1375 (zero_extend:HI (match_dup 1))) 1376 (set (match_dup 2) 1377 (compare:CC (match_dup 0) 1378 (const_int 0)))] 1379 "") 1380 1381(define_expand "extendqihi2" 1382 [(use (match_operand:HI 0 "gpc_reg_operand" "")) 1383 (use (match_operand:QI 1 "gpc_reg_operand" ""))] 1384 "" 1385 " 1386{ 1387 if (TARGET_POWERPC) 1388 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); 1389 else if (TARGET_POWER) 1390 emit_insn (gen_extendqihi2_power (operands[0], operands[1])); 1391 else 1392 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); 1393 DONE; 1394}") 1395 1396(define_insn "extendqihi2_ppc" 1397 [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 1398 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] 1399 "TARGET_POWERPC" 1400 "extsb %0,%1") 1401 1402(define_insn "" 1403 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1404 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1405 (const_int 0))) 1406 (clobber (match_scratch:HI 2 "=r,r"))] 1407 "TARGET_POWERPC" 1408 "@ 1409 extsb. %2,%1 1410 #" 1411 [(set_attr "type" "compare") 1412 (set_attr "length" "4,8")]) 1413 1414(define_split 1415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1416 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 1417 (const_int 0))) 1418 (clobber (match_scratch:HI 2 ""))] 1419 "TARGET_POWERPC && reload_completed" 1420 [(set (match_dup 2) 1421 (sign_extend:HI (match_dup 1))) 1422 (set (match_dup 0) 1423 (compare:CC (match_dup 2) 1424 (const_int 0)))] 1425 "") 1426 1427(define_insn "" 1428 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1429 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1430 (const_int 0))) 1431 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 1432 (sign_extend:HI (match_dup 1)))] 1433 "TARGET_POWERPC" 1434 "@ 1435 extsb. %0,%1 1436 #" 1437 [(set_attr "type" "compare") 1438 (set_attr "length" "4,8")]) 1439 1440(define_split 1441 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1442 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 1443 (const_int 0))) 1444 (set (match_operand:HI 0 "gpc_reg_operand" "") 1445 (sign_extend:HI (match_dup 1)))] 1446 "TARGET_POWERPC && reload_completed" 1447 [(set (match_dup 0) 1448 (sign_extend:HI (match_dup 1))) 1449 (set (match_dup 2) 1450 (compare:CC (match_dup 0) 1451 (const_int 0)))] 1452 "") 1453 1454(define_expand "extendqihi2_power" 1455 [(parallel [(set (match_dup 2) 1456 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 1457 (const_int 24))) 1458 (clobber (scratch:SI))]) 1459 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") 1460 (ashiftrt:SI (match_dup 2) 1461 (const_int 24))) 1462 (clobber (scratch:SI))])] 1463 "TARGET_POWER" 1464 " 1465{ operands[0] = gen_lowpart (SImode, operands[0]); 1466 operands[1] = gen_lowpart (SImode, operands[1]); 1467 operands[2] = gen_reg_rtx (SImode); }") 1468 1469(define_expand "extendqihi2_no_power" 1470 [(set (match_dup 2) 1471 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") 1472 (const_int 24))) 1473 (set (match_operand:HI 0 "gpc_reg_operand" "") 1474 (ashiftrt:SI (match_dup 2) 1475 (const_int 24)))] 1476 "! TARGET_POWER && ! TARGET_POWERPC" 1477 " 1478{ operands[0] = gen_lowpart (SImode, operands[0]); 1479 operands[1] = gen_lowpart (SImode, operands[1]); 1480 operands[2] = gen_reg_rtx (SImode); }") 1481 1482(define_expand "zero_extendhisi2" 1483 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1484 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 1485 "" 1486 "") 1487 1488(define_insn "" 1489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1490 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 1491 "" 1492 "@ 1493 lhz%U1%X1 %0,%1 1494 {rlinm|rlwinm} %0,%1,0,0xffff" 1495 [(set_attr "type" "load,*")]) 1496 1497(define_insn "" 1498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1499 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 1500 (const_int 0))) 1501 (clobber (match_scratch:SI 2 "=r,r"))] 1502 "" 1503 "@ 1504 {andil.|andi.} %2,%1,0xffff 1505 #" 1506 [(set_attr "type" "compare") 1507 (set_attr "length" "4,8")]) 1508 1509(define_split 1510 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1511 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 1512 (const_int 0))) 1513 (clobber (match_scratch:SI 2 ""))] 1514 "reload_completed" 1515 [(set (match_dup 2) 1516 (zero_extend:SI (match_dup 1))) 1517 (set (match_dup 0) 1518 (compare:CC (match_dup 2) 1519 (const_int 0)))] 1520 "") 1521 1522(define_insn "" 1523 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1524 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 1525 (const_int 0))) 1526 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1527 (zero_extend:SI (match_dup 1)))] 1528 "" 1529 "@ 1530 {andil.|andi.} %0,%1,0xffff 1531 #" 1532 [(set_attr "type" "compare") 1533 (set_attr "length" "4,8")]) 1534 1535(define_split 1536 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1537 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 1538 (const_int 0))) 1539 (set (match_operand:SI 0 "gpc_reg_operand" "") 1540 (zero_extend:SI (match_dup 1)))] 1541 "reload_completed" 1542 [(set (match_dup 0) 1543 (zero_extend:SI (match_dup 1))) 1544 (set (match_dup 2) 1545 (compare:CC (match_dup 0) 1546 (const_int 0)))] 1547 "") 1548 1549(define_expand "extendhisi2" 1550 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1551 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 1552 "" 1553 "") 1554 1555(define_insn "" 1556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1557 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 1558 "" 1559 "@ 1560 lha%U1%X1 %0,%1 1561 {exts|extsh} %0,%1" 1562 [(set_attr "type" "load,*")]) 1563 1564(define_insn "" 1565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1566 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 1567 (const_int 0))) 1568 (clobber (match_scratch:SI 2 "=r,r"))] 1569 "" 1570 "@ 1571 {exts.|extsh.} %2,%1 1572 #" 1573 [(set_attr "type" "compare") 1574 (set_attr "length" "4,8")]) 1575 1576(define_split 1577 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1578 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 1579 (const_int 0))) 1580 (clobber (match_scratch:SI 2 ""))] 1581 "reload_completed" 1582 [(set (match_dup 2) 1583 (sign_extend:SI (match_dup 1))) 1584 (set (match_dup 0) 1585 (compare:CC (match_dup 2) 1586 (const_int 0)))] 1587 "") 1588 1589(define_insn "" 1590 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1591 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 1592 (const_int 0))) 1593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1594 (sign_extend:SI (match_dup 1)))] 1595 "" 1596 "@ 1597 {exts.|extsh.} %0,%1 1598 #" 1599 [(set_attr "type" "compare") 1600 (set_attr "length" "4,8")]) 1601 1602(define_split 1603 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1604 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 1605 (const_int 0))) 1606 (set (match_operand:SI 0 "gpc_reg_operand" "") 1607 (sign_extend:SI (match_dup 1)))] 1608 "reload_completed" 1609 [(set (match_dup 0) 1610 (sign_extend:SI (match_dup 1))) 1611 (set (match_dup 2) 1612 (compare:CC (match_dup 0) 1613 (const_int 0)))] 1614 "") 1615 1616;; Fixed-point arithmetic insns. 1617 1618;; Discourage ai/addic because of carry but provide it in an alternative 1619;; allowing register zero as source. 1620(define_expand "addsi3" 1621 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1622 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1623 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] 1624 "" 1625 " 1626{ 1627 if (GET_CODE (operands[2]) == CONST_INT 1628 && ! add_operand (operands[2], SImode)) 1629 { 1630 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 1631 ? operands[0] : gen_reg_rtx (SImode)); 1632 1633 HOST_WIDE_INT val = INTVAL (operands[2]); 1634 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 1635 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); 1636 1637 /* The ordering here is important for the prolog expander. 1638 When space is allocated from the stack, adding 'low' first may 1639 produce a temporary deallocation (which would be bad). */ 1640 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); 1641 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); 1642 DONE; 1643 } 1644}") 1645 1646(define_insn "*addsi3_internal1" 1647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") 1648 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") 1649 (match_operand:SI 2 "add_operand" "r,I,I,L")))] 1650 "" 1651 "@ 1652 {cax|add} %0,%1,%2 1653 {cal %0,%2(%1)|addi %0,%1,%2} 1654 {ai|addic} %0,%1,%2 1655 {cau|addis} %0,%1,%v2" 1656 [(set_attr "length" "4,4,4,4")]) 1657 1658(define_insn "addsi3_high" 1659 [(set (match_operand:SI 0 "gpc_reg_operand" "=b") 1660 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 1661 (high:SI (match_operand 2 "" ""))))] 1662 "TARGET_MACHO && !TARGET_64BIT" 1663 "{cau|addis} %0,%1,ha16(%2)" 1664 [(set_attr "length" "4")]) 1665 1666(define_insn "*addsi3_internal2" 1667 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 1668 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1669 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) 1670 (const_int 0))) 1671 (clobber (match_scratch:SI 3 "=r,r,r,r"))] 1672 "! TARGET_POWERPC64" 1673 "@ 1674 {cax.|add.} %3,%1,%2 1675 {ai.|addic.} %3,%1,%2 1676 # 1677 #" 1678 [(set_attr "type" "compare") 1679 (set_attr "length" "4,4,8,8")]) 1680 1681(define_split 1682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1683 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1684 (match_operand:SI 2 "reg_or_short_operand" "")) 1685 (const_int 0))) 1686 (clobber (match_scratch:SI 3 ""))] 1687 "! TARGET_POWERPC64 && reload_completed" 1688 [(set (match_dup 3) 1689 (plus:SI (match_dup 1) 1690 (match_dup 2))) 1691 (set (match_dup 0) 1692 (compare:CC (match_dup 3) 1693 (const_int 0)))] 1694 "") 1695 1696(define_insn "*addsi3_internal3" 1697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 1698 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 1699 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) 1700 (const_int 0))) 1701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 1702 (plus:SI (match_dup 1) 1703 (match_dup 2)))] 1704 "! TARGET_POWERPC64" 1705 "@ 1706 {cax.|add.} %0,%1,%2 1707 {ai.|addic.} %0,%1,%2 1708 # 1709 #" 1710 [(set_attr "type" "compare") 1711 (set_attr "length" "4,4,8,8")]) 1712 1713(define_split 1714 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1715 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1716 (match_operand:SI 2 "reg_or_short_operand" "")) 1717 (const_int 0))) 1718 (set (match_operand:SI 0 "gpc_reg_operand" "") 1719 (plus:SI (match_dup 1) (match_dup 2)))] 1720 "! TARGET_POWERPC64 && reload_completed" 1721 [(set (match_dup 0) 1722 (plus:SI (match_dup 1) 1723 (match_dup 2))) 1724 (set (match_dup 3) 1725 (compare:CC (match_dup 0) 1726 (const_int 0)))] 1727 "") 1728 1729;; Split an add that we can't do in one insn into two insns, each of which 1730;; does one 16-bit part. This is used by combine. Note that the low-order 1731;; add should be last in case the result gets used in an address. 1732 1733(define_split 1734 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1735 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1736 (match_operand:SI 2 "non_add_cint_operand" "")))] 1737 "" 1738 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 1739 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 1740" 1741{ 1742 HOST_WIDE_INT val = INTVAL (operands[2]); 1743 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 1744 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); 1745 1746 operands[3] = GEN_INT (rest); 1747 operands[4] = GEN_INT (low); 1748}") 1749 1750(define_insn "one_cmplsi2" 1751 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1752 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 1753 "" 1754 "nor %0,%1,%1") 1755 1756(define_insn "" 1757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1758 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1759 (const_int 0))) 1760 (clobber (match_scratch:SI 2 "=r,r"))] 1761 "! TARGET_POWERPC64" 1762 "@ 1763 nor. %2,%1,%1 1764 #" 1765 [(set_attr "type" "compare") 1766 (set_attr "length" "4,8")]) 1767 1768(define_split 1769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1770 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 1771 (const_int 0))) 1772 (clobber (match_scratch:SI 2 ""))] 1773 "! TARGET_POWERPC64 && reload_completed" 1774 [(set (match_dup 2) 1775 (not:SI (match_dup 1))) 1776 (set (match_dup 0) 1777 (compare:CC (match_dup 2) 1778 (const_int 0)))] 1779 "") 1780 1781(define_insn "" 1782 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1783 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 1784 (const_int 0))) 1785 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1786 (not:SI (match_dup 1)))] 1787 "! TARGET_POWERPC64" 1788 "@ 1789 nor. %0,%1,%1 1790 #" 1791 [(set_attr "type" "compare") 1792 (set_attr "length" "4,8")]) 1793 1794(define_split 1795 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 1796 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 1797 (const_int 0))) 1798 (set (match_operand:SI 0 "gpc_reg_operand" "") 1799 (not:SI (match_dup 1)))] 1800 "! TARGET_POWERPC64 && reload_completed" 1801 [(set (match_dup 0) 1802 (not:SI (match_dup 1))) 1803 (set (match_dup 2) 1804 (compare:CC (match_dup 0) 1805 (const_int 0)))] 1806 "") 1807 1808(define_insn "" 1809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1810 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") 1811 (match_operand:SI 2 "gpc_reg_operand" "r")))] 1812 "! TARGET_POWERPC" 1813 "{sf%I1|subf%I1c} %0,%2,%1") 1814 1815(define_insn "" 1816 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1817 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") 1818 (match_operand:SI 2 "gpc_reg_operand" "r,r")))] 1819 "TARGET_POWERPC" 1820 "@ 1821 subf %0,%2,%1 1822 subfic %0,%2,%1") 1823 1824(define_insn "" 1825 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1826 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1827 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1828 (const_int 0))) 1829 (clobber (match_scratch:SI 3 "=r,r"))] 1830 "! TARGET_POWERPC" 1831 "@ 1832 {sf.|subfc.} %3,%2,%1 1833 #" 1834 [(set_attr "type" "compare") 1835 (set_attr "length" "4,8")]) 1836 1837(define_insn "" 1838 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1839 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1840 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1841 (const_int 0))) 1842 (clobber (match_scratch:SI 3 "=r,r"))] 1843 "TARGET_POWERPC && ! TARGET_POWERPC64" 1844 "@ 1845 subf. %3,%2,%1 1846 #" 1847 [(set_attr "type" "compare") 1848 (set_attr "length" "4,8")]) 1849 1850(define_split 1851 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1852 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1853 (match_operand:SI 2 "gpc_reg_operand" "")) 1854 (const_int 0))) 1855 (clobber (match_scratch:SI 3 ""))] 1856 "! TARGET_POWERPC64 && reload_completed" 1857 [(set (match_dup 3) 1858 (minus:SI (match_dup 1) 1859 (match_dup 2))) 1860 (set (match_dup 0) 1861 (compare:CC (match_dup 3) 1862 (const_int 0)))] 1863 "") 1864 1865(define_insn "" 1866 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1867 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1868 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1869 (const_int 0))) 1870 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1871 (minus:SI (match_dup 1) (match_dup 2)))] 1872 "! TARGET_POWERPC" 1873 "@ 1874 {sf.|subfc.} %0,%2,%1 1875 #" 1876 [(set_attr "type" "compare") 1877 (set_attr "length" "4,8")]) 1878 1879(define_insn "" 1880 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 1881 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 1882 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 1883 (const_int 0))) 1884 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1885 (minus:SI (match_dup 1) 1886 (match_dup 2)))] 1887 "TARGET_POWERPC && ! TARGET_POWERPC64" 1888 "@ 1889 subf. %0,%2,%1 1890 #" 1891 [(set_attr "type" "compare") 1892 (set_attr "length" "4,8")]) 1893 1894(define_split 1895 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1896 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") 1897 (match_operand:SI 2 "gpc_reg_operand" "")) 1898 (const_int 0))) 1899 (set (match_operand:SI 0 "gpc_reg_operand" "") 1900 (minus:SI (match_dup 1) 1901 (match_dup 2)))] 1902 "! TARGET_POWERPC64 && reload_completed" 1903 [(set (match_dup 0) 1904 (minus:SI (match_dup 1) 1905 (match_dup 2))) 1906 (set (match_dup 3) 1907 (compare:CC (match_dup 0) 1908 (const_int 0)))] 1909 "") 1910 1911(define_expand "subsi3" 1912 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1913 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") 1914 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] 1915 "" 1916 " 1917{ 1918 if (GET_CODE (operands[2]) == CONST_INT) 1919 { 1920 emit_insn (gen_addsi3 (operands[0], operands[1], 1921 negate_rtx (SImode, operands[2]))); 1922 DONE; 1923 } 1924}") 1925 1926;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] 1927;; instruction and some auxiliary computations. Then we just have a single 1928;; DEFINE_INSN for doz[i] and the define_splits to make them if made by 1929;; combine. 1930 1931(define_expand "sminsi3" 1932 [(set (match_dup 3) 1933 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 1934 (match_operand:SI 2 "reg_or_short_operand" "")) 1935 (const_int 0) 1936 (minus:SI (match_dup 2) (match_dup 1)))) 1937 (set (match_operand:SI 0 "gpc_reg_operand" "") 1938 (minus:SI (match_dup 2) (match_dup 3)))] 1939 "TARGET_POWER" 1940 " 1941{ operands[3] = gen_reg_rtx (SImode); }") 1942 1943(define_split 1944 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1945 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") 1946 (match_operand:SI 2 "reg_or_short_operand" ""))) 1947 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1948 "TARGET_POWER" 1949 [(set (match_dup 3) 1950 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 1951 (const_int 0) 1952 (minus:SI (match_dup 2) (match_dup 1)))) 1953 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] 1954 "") 1955 1956(define_expand "smaxsi3" 1957 [(set (match_dup 3) 1958 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 1959 (match_operand:SI 2 "reg_or_short_operand" "")) 1960 (const_int 0) 1961 (minus:SI (match_dup 2) (match_dup 1)))) 1962 (set (match_operand:SI 0 "gpc_reg_operand" "") 1963 (plus:SI (match_dup 3) (match_dup 1)))] 1964 "TARGET_POWER" 1965 " 1966{ operands[3] = gen_reg_rtx (SImode); }") 1967 1968(define_split 1969 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1970 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") 1971 (match_operand:SI 2 "reg_or_short_operand" ""))) 1972 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 1973 "TARGET_POWER" 1974 [(set (match_dup 3) 1975 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) 1976 (const_int 0) 1977 (minus:SI (match_dup 2) (match_dup 1)))) 1978 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] 1979 "") 1980 1981(define_expand "uminsi3" 1982 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 1983 (match_dup 5))) 1984 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 1985 (match_dup 5))) 1986 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 1987 (const_int 0) 1988 (minus:SI (match_dup 4) (match_dup 3)))) 1989 (set (match_operand:SI 0 "gpc_reg_operand" "") 1990 (minus:SI (match_dup 2) (match_dup 3)))] 1991 "TARGET_POWER" 1992 " 1993{ 1994 operands[3] = gen_reg_rtx (SImode); 1995 operands[4] = gen_reg_rtx (SImode); 1996 operands[5] = GEN_INT (-2147483647 - 1); 1997}") 1998 1999(define_expand "umaxsi3" 2000 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 2001 (match_dup 5))) 2002 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") 2003 (match_dup 5))) 2004 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) 2005 (const_int 0) 2006 (minus:SI (match_dup 4) (match_dup 3)))) 2007 (set (match_operand:SI 0 "gpc_reg_operand" "") 2008 (plus:SI (match_dup 3) (match_dup 1)))] 2009 "TARGET_POWER" 2010 " 2011{ 2012 operands[3] = gen_reg_rtx (SImode); 2013 operands[4] = gen_reg_rtx (SImode); 2014 operands[5] = GEN_INT (-2147483647 - 1); 2015}") 2016 2017(define_insn "" 2018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2019 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") 2020 (match_operand:SI 2 "reg_or_short_operand" "rI")) 2021 (const_int 0) 2022 (minus:SI (match_dup 2) (match_dup 1))))] 2023 "TARGET_POWER" 2024 "doz%I2 %0,%1,%2") 2025 2026(define_insn "" 2027 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2028 (compare:CC 2029 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") 2030 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 2031 (const_int 0) 2032 (minus:SI (match_dup 2) (match_dup 1))) 2033 (const_int 0))) 2034 (clobber (match_scratch:SI 3 "=r,r"))] 2035 "TARGET_POWER" 2036 "@ 2037 doz%I2. %3,%1,%2 2038 #" 2039 [(set_attr "type" "delayed_compare") 2040 (set_attr "length" "4,8")]) 2041 2042(define_split 2043 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2044 (compare:CC 2045 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") 2046 (match_operand:SI 2 "reg_or_short_operand" "")) 2047 (const_int 0) 2048 (minus:SI (match_dup 2) (match_dup 1))) 2049 (const_int 0))) 2050 (clobber (match_scratch:SI 3 ""))] 2051 "TARGET_POWER && reload_completed" 2052 [(set (match_dup 3) 2053 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 2054 (const_int 0) 2055 (minus:SI (match_dup 2) (match_dup 1)))) 2056 (set (match_dup 0) 2057 (compare:CC (match_dup 3) 2058 (const_int 0)))] 2059 "") 2060 2061(define_insn "" 2062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2063 (compare:CC 2064 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") 2065 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 2066 (const_int 0) 2067 (minus:SI (match_dup 2) (match_dup 1))) 2068 (const_int 0))) 2069 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2070 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 2071 (const_int 0) 2072 (minus:SI (match_dup 2) (match_dup 1))))] 2073 "TARGET_POWER" 2074 "@ 2075 doz%I2. %0,%1,%2 2076 #" 2077 [(set_attr "type" "delayed_compare") 2078 (set_attr "length" "4,8")]) 2079 2080(define_split 2081 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2082 (compare:CC 2083 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") 2084 (match_operand:SI 2 "reg_or_short_operand" "")) 2085 (const_int 0) 2086 (minus:SI (match_dup 2) (match_dup 1))) 2087 (const_int 0))) 2088 (set (match_operand:SI 0 "gpc_reg_operand" "") 2089 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 2090 (const_int 0) 2091 (minus:SI (match_dup 2) (match_dup 1))))] 2092 "TARGET_POWER && reload_completed" 2093 [(set (match_dup 0) 2094 (if_then_else:SI (gt (match_dup 1) (match_dup 2)) 2095 (const_int 0) 2096 (minus:SI (match_dup 2) (match_dup 1)))) 2097 (set (match_dup 3) 2098 (compare:CC (match_dup 0) 2099 (const_int 0)))] 2100 "") 2101 2102;; We don't need abs with condition code because such comparisons should 2103;; never be done. 2104(define_expand "abssi2" 2105 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2106 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] 2107 "" 2108 " 2109{ 2110 if (! TARGET_POWER) 2111 { 2112 emit_insn (gen_abssi2_nopower (operands[0], operands[1])); 2113 DONE; 2114 } 2115}") 2116 2117(define_insn "abssi2_power" 2118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2119 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 2120 "TARGET_POWER" 2121 "abs %0,%1") 2122 2123(define_insn "abssi2_nopower" 2124 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 2125 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) 2126 (clobber (match_scratch:SI 2 "=&r,&r"))] 2127 "! TARGET_POWER" 2128 "* 2129{ 2130 return (TARGET_POWERPC) 2131 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" 2132 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; 2133}" 2134 [(set_attr "length" "12")]) 2135 2136(define_split 2137 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2138 (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 2139 (clobber (match_scratch:SI 2 ""))] 2140 "! TARGET_POWER && reload_completed" 2141 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 2142 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) 2143 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] 2144 "") 2145 2146(define_insn "*nabs_power" 2147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2148 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] 2149 "TARGET_POWER" 2150 "nabs %0,%1") 2151 2152(define_insn "*nabs_no_power" 2153 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 2154 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) 2155 (clobber (match_scratch:SI 2 "=&r,&r"))] 2156 "! TARGET_POWER" 2157 "* 2158{ 2159 return (TARGET_POWERPC) 2160 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" 2161 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; 2162}" 2163 [(set_attr "length" "12")]) 2164 2165(define_split 2166 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2167 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))) 2168 (clobber (match_scratch:SI 2 ""))] 2169 "! TARGET_POWER && reload_completed" 2170 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 2171 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) 2172 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] 2173 "") 2174 2175(define_insn "negsi2" 2176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2177 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 2178 "" 2179 "neg %0,%1") 2180 2181(define_insn "" 2182 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2183 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 2184 (const_int 0))) 2185 (clobber (match_scratch:SI 2 "=r,r"))] 2186 "! TARGET_POWERPC64" 2187 "@ 2188 neg. %2,%1 2189 #" 2190 [(set_attr "type" "compare") 2191 (set_attr "length" "4,8")]) 2192 2193(define_split 2194 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2195 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) 2196 (const_int 0))) 2197 (clobber (match_scratch:SI 2 ""))] 2198 "! TARGET_POWERPC64 && reload_completed" 2199 [(set (match_dup 2) 2200 (neg:SI (match_dup 1))) 2201 (set (match_dup 0) 2202 (compare:CC (match_dup 2) 2203 (const_int 0)))] 2204 "") 2205 2206(define_insn "" 2207 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 2208 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 2209 (const_int 0))) 2210 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2211 (neg:SI (match_dup 1)))] 2212 "! TARGET_POWERPC64" 2213 "@ 2214 neg. %0,%1 2215 #" 2216 [(set_attr "type" "compare") 2217 (set_attr "length" "4,8")]) 2218 2219(define_split 2220 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 2221 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) 2222 (const_int 0))) 2223 (set (match_operand:SI 0 "gpc_reg_operand" "") 2224 (neg:SI (match_dup 1)))] 2225 "! TARGET_POWERPC64 && reload_completed" 2226 [(set (match_dup 0) 2227 (neg:SI (match_dup 1))) 2228 (set (match_dup 2) 2229 (compare:CC (match_dup 0) 2230 (const_int 0)))] 2231 "") 2232 2233(define_insn "ffssi2" 2234 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 2235 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 2236 "" 2237 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" 2238 [(set_attr "length" "16")]) 2239 2240(define_expand "mulsi3" 2241 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2242 (use (match_operand:SI 1 "gpc_reg_operand" "")) 2243 (use (match_operand:SI 2 "reg_or_short_operand" ""))] 2244 "" 2245 " 2246{ 2247 if (TARGET_POWER) 2248 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); 2249 else 2250 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); 2251 DONE; 2252}") 2253 2254(define_insn "mulsi3_mq" 2255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2256 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2257 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 2258 (clobber (match_scratch:SI 3 "=q,q"))] 2259 "TARGET_POWER" 2260 "@ 2261 {muls|mullw} %0,%1,%2 2262 {muli|mulli} %0,%1,%2" 2263 [(set (attr "type") 2264 (cond [(match_operand:SI 2 "s8bit_cint_operand" "") 2265 (const_string "imul3") 2266 (match_operand:SI 2 "short_cint_operand" "") 2267 (const_string "imul2")] 2268 (const_string "imul")))]) 2269 2270(define_insn "mulsi3_no_mq" 2271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2272 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2273 (match_operand:SI 2 "reg_or_short_operand" "r,I")))] 2274 "! TARGET_POWER" 2275 "@ 2276 {muls|mullw} %0,%1,%2 2277 {muli|mulli} %0,%1,%2" 2278 [(set (attr "type") 2279 (cond [(match_operand:SI 2 "s8bit_cint_operand" "") 2280 (const_string "imul3") 2281 (match_operand:SI 2 "short_cint_operand" "") 2282 (const_string "imul2")] 2283 (const_string "imul")))]) 2284 2285(define_insn "" 2286 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2287 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2288 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2289 (const_int 0))) 2290 (clobber (match_scratch:SI 3 "=r,r")) 2291 (clobber (match_scratch:SI 4 "=q,q"))] 2292 "TARGET_POWER" 2293 "@ 2294 {muls.|mullw.} %3,%1,%2 2295 #" 2296 [(set_attr "type" "delayed_compare") 2297 (set_attr "length" "4,8")]) 2298 2299(define_split 2300 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2301 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2302 (match_operand:SI 2 "gpc_reg_operand" "")) 2303 (const_int 0))) 2304 (clobber (match_scratch:SI 3 "")) 2305 (clobber (match_scratch:SI 4 ""))] 2306 "TARGET_POWER && reload_completed" 2307 [(parallel [(set (match_dup 3) 2308 (mult:SI (match_dup 1) (match_dup 2))) 2309 (clobber (match_dup 4))]) 2310 (set (match_dup 0) 2311 (compare:CC (match_dup 3) 2312 (const_int 0)))] 2313 "") 2314 2315(define_insn "" 2316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2317 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2318 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2319 (const_int 0))) 2320 (clobber (match_scratch:SI 3 "=r,r"))] 2321 "! TARGET_POWER" 2322 "@ 2323 {muls.|mullw.} %3,%1,%2 2324 #" 2325 [(set_attr "type" "delayed_compare") 2326 (set_attr "length" "4,8")]) 2327 2328(define_split 2329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2330 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2331 (match_operand:SI 2 "gpc_reg_operand" "")) 2332 (const_int 0))) 2333 (clobber (match_scratch:SI 3 ""))] 2334 "! TARGET_POWER && reload_completed" 2335 [(set (match_dup 3) 2336 (mult:SI (match_dup 1) (match_dup 2))) 2337 (set (match_dup 0) 2338 (compare:CC (match_dup 3) 2339 (const_int 0)))] 2340 "") 2341 2342(define_insn "" 2343 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2344 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2345 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2346 (const_int 0))) 2347 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2348 (mult:SI (match_dup 1) (match_dup 2))) 2349 (clobber (match_scratch:SI 4 "=q,q"))] 2350 "TARGET_POWER" 2351 "@ 2352 {muls.|mullw.} %0,%1,%2 2353 #" 2354 [(set_attr "type" "delayed_compare") 2355 (set_attr "length" "4,8")]) 2356 2357(define_split 2358 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2359 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2360 (match_operand:SI 2 "gpc_reg_operand" "")) 2361 (const_int 0))) 2362 (set (match_operand:SI 0 "gpc_reg_operand" "") 2363 (mult:SI (match_dup 1) (match_dup 2))) 2364 (clobber (match_scratch:SI 4 ""))] 2365 "TARGET_POWER && reload_completed" 2366 [(parallel [(set (match_dup 0) 2367 (mult:SI (match_dup 1) (match_dup 2))) 2368 (clobber (match_dup 4))]) 2369 (set (match_dup 3) 2370 (compare:CC (match_dup 0) 2371 (const_int 0)))] 2372 "") 2373 2374(define_insn "" 2375 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2376 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2377 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2378 (const_int 0))) 2379 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2380 (mult:SI (match_dup 1) (match_dup 2)))] 2381 "! TARGET_POWER" 2382 "@ 2383 {muls.|mullw.} %0,%1,%2 2384 #" 2385 [(set_attr "type" "delayed_compare") 2386 (set_attr "length" "4,8")]) 2387 2388(define_split 2389 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2390 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2391 (match_operand:SI 2 "gpc_reg_operand" "")) 2392 (const_int 0))) 2393 (set (match_operand:SI 0 "gpc_reg_operand" "") 2394 (mult:SI (match_dup 1) (match_dup 2)))] 2395 "! TARGET_POWER && reload_completed" 2396 [(set (match_dup 0) 2397 (mult:SI (match_dup 1) (match_dup 2))) 2398 (set (match_dup 3) 2399 (compare:CC (match_dup 0) 2400 (const_int 0)))] 2401 "") 2402 2403;; Operand 1 is divided by operand 2; quotient goes to operand 2404;; 0 and remainder to operand 3. 2405;; ??? At some point, see what, if anything, we can do about if (x % y == 0). 2406 2407(define_expand "divmodsi4" 2408 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 2409 (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 2410 (match_operand:SI 2 "gpc_reg_operand" ""))) 2411 (set (match_operand:SI 3 "gpc_reg_operand" "") 2412 (mod:SI (match_dup 1) (match_dup 2)))])] 2413 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" 2414 " 2415{ 2416 if (! TARGET_POWER && ! TARGET_POWERPC) 2417 { 2418 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 2419 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 2420 emit_insn (gen_divss_call ()); 2421 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 2422 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); 2423 DONE; 2424 } 2425}") 2426 2427(define_insn "" 2428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2429 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2430 (match_operand:SI 2 "gpc_reg_operand" "r"))) 2431 (set (match_operand:SI 3 "gpc_reg_operand" "=q") 2432 (mod:SI (match_dup 1) (match_dup 2)))] 2433 "TARGET_POWER" 2434 "divs %0,%1,%2" 2435 [(set_attr "type" "idiv")]) 2436 2437(define_expand "udivsi3" 2438 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2439 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 2440 (match_operand:SI 2 "gpc_reg_operand" "")))] 2441 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" 2442 " 2443{ 2444 if (! TARGET_POWER && ! TARGET_POWERPC) 2445 { 2446 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 2447 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 2448 emit_insn (gen_quous_call ()); 2449 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 2450 DONE; 2451 } 2452 else if (TARGET_POWER) 2453 { 2454 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); 2455 DONE; 2456 } 2457}") 2458 2459(define_insn "udivsi3_mq" 2460 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2461 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2462 (match_operand:SI 2 "gpc_reg_operand" "r"))) 2463 (clobber (match_scratch:SI 3 "=q"))] 2464 "TARGET_POWERPC && TARGET_POWER" 2465 "divwu %0,%1,%2" 2466 [(set_attr "type" "idiv")]) 2467 2468(define_insn "*udivsi3_no_mq" 2469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2470 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2471 (match_operand:SI 2 "gpc_reg_operand" "r")))] 2472 "TARGET_POWERPC && ! TARGET_POWER" 2473 "divwu %0,%1,%2" 2474 [(set_attr "type" "idiv")]) 2475 2476;; For powers of two we can do srai/aze for divide and then adjust for 2477;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be 2478;; used; for PowerPC, force operands into register and do a normal divide; 2479;; for AIX common-mode, use quoss call on register operands. 2480(define_expand "divsi3" 2481 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2482 (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 2483 (match_operand:SI 2 "reg_or_cint_operand" "")))] 2484 "" 2485 " 2486{ 2487 if (GET_CODE (operands[2]) == CONST_INT 2488 && INTVAL (operands[2]) > 0 2489 && exact_log2 (INTVAL (operands[2])) >= 0) 2490 ; 2491 else if (TARGET_POWERPC) 2492 { 2493 operands[2] = force_reg (SImode, operands[2]); 2494 if (TARGET_POWER) 2495 { 2496 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); 2497 DONE; 2498 } 2499 } 2500 else if (TARGET_POWER) 2501 FAIL; 2502 else 2503 { 2504 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 2505 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 2506 emit_insn (gen_quoss_call ()); 2507 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 2508 DONE; 2509 } 2510}") 2511 2512(define_insn "divsi3_mq" 2513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2514 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2515 (match_operand:SI 2 "gpc_reg_operand" "r"))) 2516 (clobber (match_scratch:SI 3 "=q"))] 2517 "TARGET_POWERPC && TARGET_POWER" 2518 "divw %0,%1,%2" 2519 [(set_attr "type" "idiv")]) 2520 2521(define_insn "*divsi3_no_mq" 2522 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2523 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2524 (match_operand:SI 2 "gpc_reg_operand" "r")))] 2525 "TARGET_POWERPC && ! TARGET_POWER" 2526 "divw %0,%1,%2" 2527 [(set_attr "type" "idiv")]) 2528 2529(define_expand "modsi3" 2530 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2531 (use (match_operand:SI 1 "gpc_reg_operand" "")) 2532 (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 2533 "" 2534 " 2535{ 2536 int i; 2537 rtx temp1; 2538 rtx temp2; 2539 2540 if (GET_CODE (operands[2]) != CONST_INT 2541 || INTVAL (operands[2]) < 0 2542 || (i = exact_log2 (INTVAL (operands[2]))) < 0) 2543 FAIL; 2544 2545 temp1 = gen_reg_rtx (SImode); 2546 temp2 = gen_reg_rtx (SImode); 2547 2548 emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); 2549 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); 2550 emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); 2551 DONE; 2552}") 2553 2554(define_insn "" 2555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2556 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") 2557 (match_operand:SI 2 "exact_log2_cint_operand" "N")))] 2558 "" 2559 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" 2560 [(set_attr "length" "8")]) 2561 2562(define_insn "" 2563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2564 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2565 (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) 2566 (const_int 0))) 2567 (clobber (match_scratch:SI 3 "=r,r"))] 2568 "" 2569 "@ 2570 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 2571 #" 2572 [(set_attr "type" "compare") 2573 (set_attr "length" "8,12")]) 2574 2575(define_split 2576 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2577 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 2578 (match_operand:SI 2 "exact_log2_cint_operand" "")) 2579 (const_int 0))) 2580 (clobber (match_scratch:SI 3 ""))] 2581 "reload_completed" 2582 [(set (match_dup 3) 2583 (div:SI (match_dup 1) (match_dup 2))) 2584 (set (match_dup 0) 2585 (compare:CC (match_dup 3) 2586 (const_int 0)))] 2587 "") 2588 2589(define_insn "" 2590 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2591 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 2592 (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) 2593 (const_int 0))) 2594 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2595 (div:SI (match_dup 1) (match_dup 2)))] 2596 "" 2597 "@ 2598 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 2599 #" 2600 [(set_attr "type" "compare") 2601 (set_attr "length" "8,12")]) 2602 2603(define_split 2604 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2605 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") 2606 (match_operand:SI 2 "exact_log2_cint_operand" "")) 2607 (const_int 0))) 2608 (set (match_operand:SI 0 "gpc_reg_operand" "") 2609 (div:SI (match_dup 1) (match_dup 2)))] 2610 "reload_completed" 2611 [(set (match_dup 0) 2612 (div:SI (match_dup 1) (match_dup 2))) 2613 (set (match_dup 3) 2614 (compare:CC (match_dup 0) 2615 (const_int 0)))] 2616 "") 2617 2618(define_insn "" 2619 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2620 (udiv:SI 2621 (plus:DI (ashift:DI 2622 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) 2623 (const_int 32)) 2624 (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) 2625 (match_operand:SI 3 "gpc_reg_operand" "r"))) 2626 (set (match_operand:SI 2 "register_operand" "=*q") 2627 (umod:SI 2628 (plus:DI (ashift:DI 2629 (zero_extend:DI (match_dup 1)) (const_int 32)) 2630 (zero_extend:DI (match_dup 4))) 2631 (match_dup 3)))] 2632 "TARGET_POWER" 2633 "div %0,%1,%3" 2634 [(set_attr "type" "idiv")]) 2635 2636;; To do unsigned divide we handle the cases of the divisor looking like a 2637;; negative number. If it is a constant that is less than 2**31, we don't 2638;; have to worry about the branches. So make a few subroutines here. 2639;; 2640;; First comes the normal case. 2641(define_expand "udivmodsi4_normal" 2642 [(set (match_dup 4) (const_int 0)) 2643 (parallel [(set (match_operand:SI 0 "" "") 2644 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 2645 (const_int 32)) 2646 (zero_extend:DI (match_operand:SI 1 "" ""))) 2647 (match_operand:SI 2 "" ""))) 2648 (set (match_operand:SI 3 "" "") 2649 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) 2650 (const_int 32)) 2651 (zero_extend:DI (match_dup 1))) 2652 (match_dup 2)))])] 2653 "TARGET_POWER" 2654 " 2655{ operands[4] = gen_reg_rtx (SImode); }") 2656 2657;; This handles the branches. 2658(define_expand "udivmodsi4_tests" 2659 [(set (match_operand:SI 0 "" "") (const_int 0)) 2660 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) 2661 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) 2662 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) 2663 (label_ref (match_operand:SI 4 "" "")) (pc))) 2664 (set (match_dup 0) (const_int 1)) 2665 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) 2666 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) 2667 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) 2668 (label_ref (match_dup 4)) (pc)))] 2669 "TARGET_POWER" 2670 " 2671{ operands[5] = gen_reg_rtx (CCUNSmode); 2672 operands[6] = gen_reg_rtx (CCmode); 2673}") 2674 2675(define_expand "udivmodsi4" 2676 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 2677 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") 2678 (match_operand:SI 2 "reg_or_cint_operand" ""))) 2679 (set (match_operand:SI 3 "gpc_reg_operand" "") 2680 (umod:SI (match_dup 1) (match_dup 2)))])] 2681 "" 2682 " 2683{ 2684 rtx label = 0; 2685 2686 if (! TARGET_POWER) 2687 { 2688 if (! TARGET_POWERPC) 2689 { 2690 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 2691 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 2692 emit_insn (gen_divus_call ()); 2693 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 2694 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); 2695 DONE; 2696 } 2697 else 2698 FAIL; 2699 } 2700 2701 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) 2702 { 2703 operands[2] = force_reg (SImode, operands[2]); 2704 label = gen_label_rtx (); 2705 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], 2706 operands[3], label)); 2707 } 2708 else 2709 operands[2] = force_reg (SImode, operands[2]); 2710 2711 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], 2712 operands[3])); 2713 if (label) 2714 emit_label (label); 2715 2716 DONE; 2717}") 2718 2719;; AIX architecture-independent common-mode multiply (DImode), 2720;; divide/modulus, and quotient subroutine calls. Input operands in R3 and 2721;; R4; results in R3 and sometimes R4; link register always clobbered by bla 2722;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but 2723;; assumed unused if generating common-mode, so ignore. 2724(define_insn "mulh_call" 2725 [(set (reg:SI 3) 2726 (truncate:SI 2727 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) 2728 (sign_extend:DI (reg:SI 4))) 2729 (const_int 32)))) 2730 (clobber (match_scratch:SI 0 "=l"))] 2731 "! TARGET_POWER && ! TARGET_POWERPC" 2732 "bla __mulh" 2733 [(set_attr "type" "imul")]) 2734 2735(define_insn "mull_call" 2736 [(set (reg:DI 3) 2737 (mult:DI (sign_extend:DI (reg:SI 3)) 2738 (sign_extend:DI (reg:SI 4)))) 2739 (clobber (match_scratch:SI 0 "=l")) 2740 (clobber (reg:SI 0))] 2741 "! TARGET_POWER && ! TARGET_POWERPC" 2742 "bla __mull" 2743 [(set_attr "type" "imul")]) 2744 2745(define_insn "divss_call" 2746 [(set (reg:SI 3) 2747 (div:SI (reg:SI 3) (reg:SI 4))) 2748 (set (reg:SI 4) 2749 (mod:SI (reg:SI 3) (reg:SI 4))) 2750 (clobber (match_scratch:SI 0 "=l")) 2751 (clobber (reg:SI 0))] 2752 "! TARGET_POWER && ! TARGET_POWERPC" 2753 "bla __divss" 2754 [(set_attr "type" "idiv")]) 2755 2756(define_insn "divus_call" 2757 [(set (reg:SI 3) 2758 (udiv:SI (reg:SI 3) (reg:SI 4))) 2759 (set (reg:SI 4) 2760 (umod:SI (reg:SI 3) (reg:SI 4))) 2761 (clobber (match_scratch:SI 0 "=l")) 2762 (clobber (reg:SI 0)) 2763 (clobber (match_scratch:CC 1 "=x")) 2764 (clobber (reg:CC 69))] 2765 "! TARGET_POWER && ! TARGET_POWERPC" 2766 "bla __divus" 2767 [(set_attr "type" "idiv")]) 2768 2769(define_insn "quoss_call" 2770 [(set (reg:SI 3) 2771 (div:SI (reg:SI 3) (reg:SI 4))) 2772 (clobber (match_scratch:SI 0 "=l"))] 2773 "! TARGET_POWER && ! TARGET_POWERPC" 2774 "bla __quoss" 2775 [(set_attr "type" "idiv")]) 2776 2777(define_insn "quous_call" 2778 [(set (reg:SI 3) 2779 (udiv:SI (reg:SI 3) (reg:SI 4))) 2780 (clobber (match_scratch:SI 0 "=l")) 2781 (clobber (reg:SI 0)) 2782 (clobber (match_scratch:CC 1 "=x")) 2783 (clobber (reg:CC 69))] 2784 "! TARGET_POWER && ! TARGET_POWERPC" 2785 "bla __quous" 2786 [(set_attr "type" "idiv")]) 2787 2788;; Logical instructions 2789;; The logical instructions are mostly combined by using match_operator, 2790;; but the plain AND insns are somewhat different because there is no 2791;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all 2792;; those rotate-and-mask operations. Thus, the AND insns come first. 2793 2794(define_insn "andsi3" 2795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 2796 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 2797 (match_operand:SI 2 "and_operand" "?r,T,K,L"))) 2798 (clobber (match_scratch:CC 3 "=X,X,x,x"))] 2799 "" 2800 "@ 2801 and %0,%1,%2 2802 {rlinm|rlwinm} %0,%1,0,%m2,%M2 2803 {andil.|andi.} %0,%1,%b2 2804 {andiu.|andis.} %0,%1,%u2") 2805 2806;; Note to set cr's other than cr0 we do the and immediate and then 2807;; the test again -- this avoids a mcrf which on the higher end 2808;; machines causes an execution serialization 2809 2810(define_insn "*andsi3_internal2" 2811 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2812 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2813 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2814 (const_int 0))) 2815 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) 2816 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2817 "! TARGET_POWERPC64" 2818 "@ 2819 and. %3,%1,%2 2820 {andil.|andi.} %3,%1,%b2 2821 {andiu.|andis.} %3,%1,%u2 2822 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 2823 # 2824 # 2825 # 2826 #" 2827 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2828 (set_attr "length" "4,4,4,4,8,8,8,8")]) 2829 2830(define_split 2831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2832 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2833 (match_operand:SI 2 "and_operand" "")) 2834 (const_int 0))) 2835 (clobber (match_scratch:SI 3 "")) 2836 (clobber (match_scratch:CC 4 ""))] 2837 "! TARGET_POWERPC64 && reload_completed" 2838 [(parallel [(set (match_dup 3) 2839 (and:SI (match_dup 1) 2840 (match_dup 2))) 2841 (clobber (match_dup 4))]) 2842 (set (match_dup 0) 2843 (compare:CC (match_dup 3) 2844 (const_int 0)))] 2845 "") 2846 2847(define_insn "*andsi3_internal3" 2848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2849 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2850 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2851 (const_int 0))) 2852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") 2853 (and:SI (match_dup 1) 2854 (match_dup 2))) 2855 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2856 "! TARGET_POWERPC64" 2857 "@ 2858 and. %0,%1,%2 2859 {andil.|andi.} %0,%1,%b2 2860 {andiu.|andis.} %0,%1,%u2 2861 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 2862 # 2863 # 2864 # 2865 #" 2866 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 2867 (set_attr "length" "4,4,4,4,8,8,8,8")]) 2868 2869(define_split 2870 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2871 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2872 (match_operand:SI 2 "and_operand" "")) 2873 (const_int 0))) 2874 (set (match_operand:SI 0 "gpc_reg_operand" "") 2875 (and:SI (match_dup 1) 2876 (match_dup 2))) 2877 (clobber (match_scratch:CC 4 ""))] 2878 "! TARGET_POWERPC64 && reload_completed" 2879 [(parallel [(set (match_dup 0) 2880 (and:SI (match_dup 1) 2881 (match_dup 2))) 2882 (clobber (match_dup 4))]) 2883 (set (match_dup 3) 2884 (compare:CC (match_dup 0) 2885 (const_int 0)))] 2886 "") 2887 2888(define_expand "iorsi3" 2889 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2890 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") 2891 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] 2892 "" 2893 " 2894{ 2895 if (GET_CODE (operands[2]) == CONST_INT 2896 && ! logical_operand (operands[2], SImode)) 2897 { 2898 HOST_WIDE_INT value = INTVAL (operands[2]); 2899 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 2900 ? operands[0] : gen_reg_rtx (SImode)); 2901 2902 emit_insn (gen_iorsi3 (tmp, operands[1], 2903 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 2904 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 2905 DONE; 2906 } 2907}") 2908 2909(define_expand "xorsi3" 2910 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2911 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 2912 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] 2913 "" 2914 " 2915{ 2916 if (GET_CODE (operands[2]) == CONST_INT 2917 && ! logical_operand (operands[2], SImode)) 2918 { 2919 HOST_WIDE_INT value = INTVAL (operands[2]); 2920 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 2921 ? operands[0] : gen_reg_rtx (SImode)); 2922 2923 emit_insn (gen_xorsi3 (tmp, operands[1], 2924 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 2925 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 2926 DONE; 2927 } 2928}") 2929 2930(define_insn "*boolsi3_internal1" 2931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 2932 (match_operator:SI 3 "boolean_or_operator" 2933 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 2934 (match_operand:SI 2 "logical_operand" "r,K,L")]))] 2935 "" 2936 "@ 2937 %q3 %0,%1,%2 2938 {%q3il|%q3i} %0,%1,%b2 2939 {%q3iu|%q3is} %0,%1,%u2") 2940 2941(define_insn "*boolsi3_internal2" 2942 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2943 (compare:CC (match_operator:SI 4 "boolean_or_operator" 2944 [(match_operand:SI 1 "gpc_reg_operand" "%r,r") 2945 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 2946 (const_int 0))) 2947 (clobber (match_scratch:SI 3 "=r,r"))] 2948 "! TARGET_POWERPC64" 2949 "@ 2950 %q4. %3,%1,%2 2951 #" 2952 [(set_attr "type" "compare") 2953 (set_attr "length" "4,8")]) 2954 2955(define_split 2956 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2957 (compare:CC (match_operator:SI 4 "boolean_operator" 2958 [(match_operand:SI 1 "gpc_reg_operand" "") 2959 (match_operand:SI 2 "gpc_reg_operand" "")]) 2960 (const_int 0))) 2961 (clobber (match_scratch:SI 3 ""))] 2962 "! TARGET_POWERPC64 && reload_completed" 2963 [(set (match_dup 3) (match_dup 4)) 2964 (set (match_dup 0) 2965 (compare:CC (match_dup 3) 2966 (const_int 0)))] 2967 "") 2968 2969(define_insn "*boolsi3_internal3" 2970 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2971 (compare:CC (match_operator:SI 4 "boolean_operator" 2972 [(match_operand:SI 1 "gpc_reg_operand" "%r,r") 2973 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 2974 (const_int 0))) 2975 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2976 (match_dup 4))] 2977 "! TARGET_POWERPC64" 2978 "@ 2979 %q4. %0,%1,%2 2980 #" 2981 [(set_attr "type" "compare") 2982 (set_attr "length" "4,8")]) 2983 2984(define_split 2985 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2986 (compare:CC (match_operator:SI 4 "boolean_operator" 2987 [(match_operand:SI 1 "gpc_reg_operand" "") 2988 (match_operand:SI 2 "gpc_reg_operand" "")]) 2989 (const_int 0))) 2990 (set (match_operand:SI 0 "gpc_reg_operand" "") 2991 (match_dup 4))] 2992 "! TARGET_POWERPC64 && reload_completed" 2993 [(set (match_dup 0) (match_dup 4)) 2994 (set (match_dup 3) 2995 (compare:CC (match_dup 0) 2996 (const_int 0)))] 2997 "") 2998 2999;; Split an logical operation that we can't do in one insn into two insns, 3000;; each of which does one 16-bit part. This is used by combine. 3001 3002(define_split 3003 [(set (match_operand:SI 0 "gpc_reg_operand" "") 3004 (match_operator:SI 3 "boolean_or_operator" 3005 [(match_operand:SI 1 "gpc_reg_operand" "") 3006 (match_operand:SI 2 "non_logical_cint_operand" "")]))] 3007 "" 3008 [(set (match_dup 0) (match_dup 4)) 3009 (set (match_dup 0) (match_dup 5))] 3010" 3011{ 3012 rtx i; 3013 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); 3014 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, 3015 operands[1], i); 3016 i = GEN_INT (INTVAL (operands[2]) & 0xffff); 3017 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, 3018 operands[0], i); 3019}") 3020 3021(define_insn "*boolcsi3_internal1" 3022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3023 (match_operator:SI 3 "boolean_operator" 3024 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 3025 (match_operand:SI 2 "gpc_reg_operand" "r")]))] 3026 "" 3027 "%q3 %0,%2,%1") 3028 3029(define_insn "*boolcsi3_internal2" 3030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3031 (compare:CC (match_operator:SI 4 "boolean_operator" 3032 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 3033 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 3034 (const_int 0))) 3035 (clobber (match_scratch:SI 3 "=r,r"))] 3036 "! TARGET_POWERPC64" 3037 "@ 3038 %q4. %3,%2,%1 3039 #" 3040 [(set_attr "type" "compare") 3041 (set_attr "length" "4,8")]) 3042 3043(define_split 3044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3045 (compare:CC (match_operator:SI 4 "boolean_operator" 3046 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3047 (match_operand:SI 2 "gpc_reg_operand" "")]) 3048 (const_int 0))) 3049 (clobber (match_scratch:SI 3 ""))] 3050 "! TARGET_POWERPC64 && reload_completed" 3051 [(set (match_dup 3) (match_dup 4)) 3052 (set (match_dup 0) 3053 (compare:CC (match_dup 3) 3054 (const_int 0)))] 3055 "") 3056 3057(define_insn "*boolcsi3_internal3" 3058 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3059 (compare:CC (match_operator:SI 4 "boolean_operator" 3060 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) 3061 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 3062 (const_int 0))) 3063 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3064 (match_dup 4))] 3065 "! TARGET_POWERPC64" 3066 "@ 3067 %q4. %0,%2,%1 3068 #" 3069 [(set_attr "type" "compare") 3070 (set_attr "length" "4,8")]) 3071 3072(define_split 3073 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3074 (compare:CC (match_operator:SI 4 "boolean_operator" 3075 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3076 (match_operand:SI 2 "gpc_reg_operand" "")]) 3077 (const_int 0))) 3078 (set (match_operand:SI 0 "gpc_reg_operand" "") 3079 (match_dup 4))] 3080 "! TARGET_POWERPC64 && reload_completed" 3081 [(set (match_dup 0) (match_dup 4)) 3082 (set (match_dup 3) 3083 (compare:CC (match_dup 0) 3084 (const_int 0)))] 3085 "") 3086 3087(define_insn "*boolccsi3_internal1" 3088 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3089 (match_operator:SI 3 "boolean_operator" 3090 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 3091 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] 3092 "" 3093 "%q3 %0,%1,%2") 3094 3095(define_insn "*boolccsi3_internal2" 3096 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3097 (compare:CC (match_operator:SI 4 "boolean_operator" 3098 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 3099 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) 3100 (const_int 0))) 3101 (clobber (match_scratch:SI 3 "=r,r"))] 3102 "! TARGET_POWERPC64" 3103 "@ 3104 %q4. %3,%1,%2 3105 #" 3106 [(set_attr "type" "compare") 3107 (set_attr "length" "4,8")]) 3108 3109(define_split 3110 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3111 (compare:CC (match_operator:SI 4 "boolean_operator" 3112 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3113 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) 3114 (const_int 0))) 3115 (clobber (match_scratch:SI 3 ""))] 3116 "! TARGET_POWERPC64 && reload_completed" 3117 [(set (match_dup 3) (match_dup 4)) 3118 (set (match_dup 0) 3119 (compare:CC (match_dup 3) 3120 (const_int 0)))] 3121 "") 3122 3123(define_insn "*boolccsi3_internal3" 3124 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3125 (compare:CC (match_operator:SI 4 "boolean_operator" 3126 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) 3127 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) 3128 (const_int 0))) 3129 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3130 (match_dup 4))] 3131 "! TARGET_POWERPC64" 3132 "@ 3133 %q4. %0,%1,%2 3134 #" 3135 [(set_attr "type" "compare") 3136 (set_attr "length" "4,8")]) 3137 3138(define_split 3139 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3140 (compare:CC (match_operator:SI 4 "boolean_operator" 3141 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3142 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) 3143 (const_int 0))) 3144 (set (match_operand:SI 0 "gpc_reg_operand" "") 3145 (match_dup 4))] 3146 "! TARGET_POWERPC64 && reload_completed" 3147 [(set (match_dup 0) (match_dup 4)) 3148 (set (match_dup 3) 3149 (compare:CC (match_dup 0) 3150 (const_int 0)))] 3151 "") 3152 3153;; maskir insn. We need four forms because things might be in arbitrary 3154;; orders. Don't define forms that only set CR fields because these 3155;; would modify an input register. 3156 3157(define_insn "*maskir_internal1" 3158 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3159 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 3160 (match_operand:SI 1 "gpc_reg_operand" "0")) 3161 (and:SI (match_dup 2) 3162 (match_operand:SI 3 "gpc_reg_operand" "r"))))] 3163 "TARGET_POWER" 3164 "maskir %0,%3,%2") 3165 3166(define_insn "*maskir_internal2" 3167 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3168 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) 3169 (match_operand:SI 1 "gpc_reg_operand" "0")) 3170 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3171 (match_dup 2))))] 3172 "TARGET_POWER" 3173 "maskir %0,%3,%2") 3174 3175(define_insn "*maskir_internal3" 3176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3177 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") 3178 (match_operand:SI 3 "gpc_reg_operand" "r")) 3179 (and:SI (not:SI (match_dup 2)) 3180 (match_operand:SI 1 "gpc_reg_operand" "0"))))] 3181 "TARGET_POWER" 3182 "maskir %0,%3,%2") 3183 3184(define_insn "*maskir_internal4" 3185 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3186 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3187 (match_operand:SI 2 "gpc_reg_operand" "r")) 3188 (and:SI (not:SI (match_dup 2)) 3189 (match_operand:SI 1 "gpc_reg_operand" "0"))))] 3190 "TARGET_POWER" 3191 "maskir %0,%3,%2") 3192 3193(define_insn "*maskir_internal5" 3194 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3195 (compare:CC 3196 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) 3197 (match_operand:SI 1 "gpc_reg_operand" "0,0")) 3198 (and:SI (match_dup 2) 3199 (match_operand:SI 3 "gpc_reg_operand" "r,r"))) 3200 (const_int 0))) 3201 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3202 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3203 (and:SI (match_dup 2) (match_dup 3))))] 3204 "TARGET_POWER" 3205 "@ 3206 maskir. %0,%3,%2 3207 #" 3208 [(set_attr "type" "compare") 3209 (set_attr "length" "4,8")]) 3210 3211(define_split 3212 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3213 (compare:CC 3214 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) 3215 (match_operand:SI 1 "gpc_reg_operand" "")) 3216 (and:SI (match_dup 2) 3217 (match_operand:SI 3 "gpc_reg_operand" ""))) 3218 (const_int 0))) 3219 (set (match_operand:SI 0 "gpc_reg_operand" "") 3220 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3221 (and:SI (match_dup 2) (match_dup 3))))] 3222 "TARGET_POWER && reload_completed" 3223 [(set (match_dup 0) 3224 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3225 (and:SI (match_dup 2) (match_dup 3)))) 3226 (set (match_dup 4) 3227 (compare:CC (match_dup 0) 3228 (const_int 0)))] 3229 "") 3230 3231(define_insn "*maskir_internal6" 3232 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3233 (compare:CC 3234 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) 3235 (match_operand:SI 1 "gpc_reg_operand" "0,0")) 3236 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") 3237 (match_dup 2))) 3238 (const_int 0))) 3239 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3240 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3241 (and:SI (match_dup 3) (match_dup 2))))] 3242 "TARGET_POWER" 3243 "@ 3244 maskir. %0,%3,%2 3245 #" 3246 [(set_attr "type" "compare") 3247 (set_attr "length" "4,8")]) 3248 3249(define_split 3250 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3251 (compare:CC 3252 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) 3253 (match_operand:SI 1 "gpc_reg_operand" "")) 3254 (and:SI (match_operand:SI 3 "gpc_reg_operand" "") 3255 (match_dup 2))) 3256 (const_int 0))) 3257 (set (match_operand:SI 0 "gpc_reg_operand" "") 3258 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3259 (and:SI (match_dup 3) (match_dup 2))))] 3260 "TARGET_POWER && reload_completed" 3261 [(set (match_dup 0) 3262 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) 3263 (and:SI (match_dup 3) (match_dup 2)))) 3264 (set (match_dup 4) 3265 (compare:CC (match_dup 0) 3266 (const_int 0)))] 3267 "") 3268 3269(define_insn "*maskir_internal7" 3270 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3271 (compare:CC 3272 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") 3273 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 3274 (and:SI (not:SI (match_dup 2)) 3275 (match_operand:SI 1 "gpc_reg_operand" "0,0"))) 3276 (const_int 0))) 3277 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3278 (ior:SI (and:SI (match_dup 2) (match_dup 3)) 3279 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 3280 "TARGET_POWER" 3281 "@ 3282 maskir. %0,%3,%2 3283 #" 3284 [(set_attr "type" "compare") 3285 (set_attr "length" "4,8")]) 3286 3287(define_split 3288 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3289 (compare:CC 3290 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") 3291 (match_operand:SI 3 "gpc_reg_operand" "")) 3292 (and:SI (not:SI (match_dup 2)) 3293 (match_operand:SI 1 "gpc_reg_operand" ""))) 3294 (const_int 0))) 3295 (set (match_operand:SI 0 "gpc_reg_operand" "") 3296 (ior:SI (and:SI (match_dup 2) (match_dup 3)) 3297 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 3298 "TARGET_POWER && reload_completed" 3299 [(set (match_dup 0) 3300 (ior:SI (and:SI (match_dup 2) (match_dup 3)) 3301 (and:SI (not:SI (match_dup 2)) (match_dup 1)))) 3302 (set (match_dup 4) 3303 (compare:CC (match_dup 0) 3304 (const_int 0)))] 3305 "") 3306 3307(define_insn "*maskir_internal8" 3308 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3309 (compare:CC 3310 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") 3311 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 3312 (and:SI (not:SI (match_dup 2)) 3313 (match_operand:SI 1 "gpc_reg_operand" "0,0"))) 3314 (const_int 0))) 3315 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3316 (ior:SI (and:SI (match_dup 3) (match_dup 2)) 3317 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 3318 "TARGET_POWER" 3319 "@ 3320 maskir. %0,%3,%2 3321 #" 3322 [(set_attr "type" "compare") 3323 (set_attr "length" "4,8")]) 3324 3325(define_split 3326 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3327 (compare:CC 3328 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") 3329 (match_operand:SI 2 "gpc_reg_operand" "")) 3330 (and:SI (not:SI (match_dup 2)) 3331 (match_operand:SI 1 "gpc_reg_operand" ""))) 3332 (const_int 0))) 3333 (set (match_operand:SI 0 "gpc_reg_operand" "") 3334 (ior:SI (and:SI (match_dup 3) (match_dup 2)) 3335 (and:SI (not:SI (match_dup 2)) (match_dup 1))))] 3336 "TARGET_POWER && reload_completed" 3337 [(set (match_dup 0) 3338 (ior:SI (and:SI (match_dup 3) (match_dup 2)) 3339 (and:SI (not:SI (match_dup 2)) (match_dup 1)))) 3340 (set (match_dup 4) 3341 (compare:CC (match_dup 0) 3342 (const_int 0)))] 3343 "") 3344 3345;; Rotate and shift insns, in all their variants. These support shifts, 3346;; field inserts and extracts, and various combinations thereof. 3347(define_expand "insv" 3348 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") 3349 (match_operand:SI 1 "const_int_operand" "") 3350 (match_operand:SI 2 "const_int_operand" "")) 3351 (match_operand 3 "gpc_reg_operand" ""))] 3352 "" 3353 " 3354{ 3355 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 3356 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 3357 compiler if the address of the structure is taken later. */ 3358 if (GET_CODE (operands[0]) == SUBREG 3359 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) 3360 FAIL; 3361 3362 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) 3363 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); 3364 else 3365 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); 3366 DONE; 3367}") 3368 3369(define_insn "insvsi" 3370 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3371 (match_operand:SI 1 "const_int_operand" "i") 3372 (match_operand:SI 2 "const_int_operand" "i")) 3373 (match_operand:SI 3 "gpc_reg_operand" "r"))] 3374 "" 3375 "* 3376{ 3377 int start = INTVAL (operands[2]) & 31; 3378 int size = INTVAL (operands[1]) & 31; 3379 3380 operands[4] = GEN_INT (32 - start - size); 3381 operands[1] = GEN_INT (start + size - 1); 3382 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3383}") 3384 3385(define_insn "*insvsi_internal1" 3386 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3387 (match_operand:SI 1 "const_int_operand" "i") 3388 (match_operand:SI 2 "const_int_operand" "i")) 3389 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3390 (match_operand:SI 4 "const_int_operand" "i")))] 3391 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 3392 "* 3393{ 3394 int shift = INTVAL (operands[4]) & 31; 3395 int start = INTVAL (operands[2]) & 31; 3396 int size = INTVAL (operands[1]) & 31; 3397 3398 operands[4] = GEN_INT (shift - start - size); 3399 operands[1] = GEN_INT (start + size - 1); 3400 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3401}") 3402 3403(define_insn "*insvsi_internal2" 3404 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3405 (match_operand:SI 1 "const_int_operand" "i") 3406 (match_operand:SI 2 "const_int_operand" "i")) 3407 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3408 (match_operand:SI 4 "const_int_operand" "i")))] 3409 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 3410 "* 3411{ 3412 int shift = INTVAL (operands[4]) & 31; 3413 int start = INTVAL (operands[2]) & 31; 3414 int size = INTVAL (operands[1]) & 31; 3415 3416 operands[4] = GEN_INT (32 - shift - start - size); 3417 operands[1] = GEN_INT (start + size - 1); 3418 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3419}") 3420 3421(define_insn "*insvsi_internal3" 3422 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3423 (match_operand:SI 1 "const_int_operand" "i") 3424 (match_operand:SI 2 "const_int_operand" "i")) 3425 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3426 (match_operand:SI 4 "const_int_operand" "i")))] 3427 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 3428 "* 3429{ 3430 int shift = INTVAL (operands[4]) & 31; 3431 int start = INTVAL (operands[2]) & 31; 3432 int size = INTVAL (operands[1]) & 31; 3433 3434 operands[4] = GEN_INT (32 - shift - start - size); 3435 operands[1] = GEN_INT (start + size - 1); 3436 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; 3437}") 3438 3439(define_insn "*insvsi_internal4" 3440 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3441 (match_operand:SI 1 "const_int_operand" "i") 3442 (match_operand:SI 2 "const_int_operand" "i")) 3443 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3444 (match_operand:SI 4 "const_int_operand" "i") 3445 (match_operand:SI 5 "const_int_operand" "i")))] 3446 "INTVAL (operands[4]) >= INTVAL (operands[1])" 3447 "* 3448{ 3449 int extract_start = INTVAL (operands[5]) & 31; 3450 int extract_size = INTVAL (operands[4]) & 31; 3451 int insert_start = INTVAL (operands[2]) & 31; 3452 int insert_size = INTVAL (operands[1]) & 31; 3453 3454/* Align extract field with insert field */ 3455 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); 3456 operands[1] = GEN_INT (insert_start + insert_size - 1); 3457 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; 3458}") 3459 3460(define_insn "insvdi" 3461 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") 3462 (match_operand:SI 1 "const_int_operand" "i") 3463 (match_operand:SI 2 "const_int_operand" "i")) 3464 (match_operand:DI 3 "gpc_reg_operand" "r"))] 3465 "TARGET_POWERPC64" 3466 "* 3467{ 3468 int start = INTVAL (operands[2]) & 63; 3469 int size = INTVAL (operands[1]) & 63; 3470 3471 operands[1] = GEN_INT (64 - start - size); 3472 return \"rldimi %0,%3,%H1,%H2\"; 3473}") 3474 3475(define_expand "extzv" 3476 [(set (match_operand 0 "gpc_reg_operand" "") 3477 (zero_extract (match_operand 1 "gpc_reg_operand" "") 3478 (match_operand:SI 2 "const_int_operand" "") 3479 (match_operand:SI 3 "const_int_operand" "")))] 3480 "" 3481 " 3482{ 3483 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 3484 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 3485 compiler if the address of the structure is taken later. */ 3486 if (GET_CODE (operands[0]) == SUBREG 3487 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) 3488 FAIL; 3489 3490 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) 3491 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); 3492 else 3493 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); 3494 DONE; 3495}") 3496 3497(define_insn "extzvsi" 3498 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3499 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3500 (match_operand:SI 2 "const_int_operand" "i") 3501 (match_operand:SI 3 "const_int_operand" "i")))] 3502 "" 3503 "* 3504{ 3505 int start = INTVAL (operands[3]) & 31; 3506 int size = INTVAL (operands[2]) & 31; 3507 3508 if (start + size >= 32) 3509 operands[3] = const0_rtx; 3510 else 3511 operands[3] = GEN_INT (start + size); 3512 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; 3513}") 3514 3515(define_insn "*extzvsi_internal1" 3516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3517 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3518 (match_operand:SI 2 "const_int_operand" "i,i") 3519 (match_operand:SI 3 "const_int_operand" "i,i")) 3520 (const_int 0))) 3521 (clobber (match_scratch:SI 4 "=r,r"))] 3522 "! TARGET_POWERPC64" 3523 "* 3524{ 3525 int start = INTVAL (operands[3]) & 31; 3526 int size = INTVAL (operands[2]) & 31; 3527 3528 /* Force split for non-cc0 compare. */ 3529 if (which_alternative == 1) 3530 return \"#\"; 3531 3532 /* If the bitfield being tested fits in the upper or lower half of a 3533 word, it is possible to use andiu. or andil. to test it. This is 3534 useful because the condition register set-use delay is smaller for 3535 andi[ul]. than for rlinm. This doesn't work when the starting bit 3536 position is 0 because the LT and GT bits may be set wrong. */ 3537 3538 if ((start > 0 && start + size <= 16) || start >= 16) 3539 { 3540 operands[3] = GEN_INT (((1 << (16 - (start & 15))) 3541 - (1 << (16 - (start & 15) - size)))); 3542 if (start < 16) 3543 return \"{andiu.|andis.} %4,%1,%3\"; 3544 else 3545 return \"{andil.|andi.} %4,%1,%3\"; 3546 } 3547 3548 if (start + size >= 32) 3549 operands[3] = const0_rtx; 3550 else 3551 operands[3] = GEN_INT (start + size); 3552 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; 3553}" 3554 [(set_attr "type" "compare") 3555 (set_attr "length" "4,8")]) 3556 3557(define_split 3558 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3559 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 3560 (match_operand:SI 2 "const_int_operand" "") 3561 (match_operand:SI 3 "const_int_operand" "")) 3562 (const_int 0))) 3563 (clobber (match_scratch:SI 4 ""))] 3564 "! TARGET_POWERPC64 && reload_completed" 3565 [(set (match_dup 4) 3566 (zero_extract:SI (match_dup 1) (match_dup 2) 3567 (match_dup 3))) 3568 (set (match_dup 0) 3569 (compare:CC (match_dup 4) 3570 (const_int 0)))] 3571 "") 3572 3573(define_insn "*extzvsi_internal2" 3574 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3575 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3576 (match_operand:SI 2 "const_int_operand" "i,i") 3577 (match_operand:SI 3 "const_int_operand" "i,i")) 3578 (const_int 0))) 3579 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3580 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 3581 "! TARGET_POWERPC64" 3582 "* 3583{ 3584 int start = INTVAL (operands[3]) & 31; 3585 int size = INTVAL (operands[2]) & 31; 3586 3587 /* Force split for non-cc0 compare. */ 3588 if (which_alternative == 1) 3589 return \"#\"; 3590 3591 if (start >= 16 && start + size == 32) 3592 { 3593 operands[3] = GEN_INT ((1 << (32 - start)) - 1); 3594 return \"{andil.|andi.} %0,%1,%3\"; 3595 } 3596 3597 if (start + size >= 32) 3598 operands[3] = const0_rtx; 3599 else 3600 operands[3] = GEN_INT (start + size); 3601 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; 3602}" 3603 [(set_attr "type" "delayed_compare") 3604 (set_attr "length" "4,8")]) 3605 3606(define_split 3607 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3608 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 3609 (match_operand:SI 2 "const_int_operand" "") 3610 (match_operand:SI 3 "const_int_operand" "")) 3611 (const_int 0))) 3612 (set (match_operand:SI 0 "gpc_reg_operand" "") 3613 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 3614 "! TARGET_POWERPC64 && reload_completed" 3615 [(set (match_dup 0) 3616 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) 3617 (set (match_dup 4) 3618 (compare:CC (match_dup 0) 3619 (const_int 0)))] 3620 "") 3621 3622(define_insn "extzvdi" 3623 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3624 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3625 (match_operand:SI 2 "const_int_operand" "i") 3626 (match_operand:SI 3 "const_int_operand" "i")))] 3627 "TARGET_POWERPC64" 3628 "* 3629{ 3630 int start = INTVAL (operands[3]) & 63; 3631 int size = INTVAL (operands[2]) & 63; 3632 3633 if (start + size >= 64) 3634 operands[3] = const0_rtx; 3635 else 3636 operands[3] = GEN_INT (start + size); 3637 operands[2] = GEN_INT (64 - size); 3638 return \"rldicl %0,%1,%3,%2\"; 3639}") 3640 3641(define_insn "*extzvdi_internal1" 3642 [(set (match_operand:CC 0 "gpc_reg_operand" "=x") 3643 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3644 (match_operand:SI 2 "const_int_operand" "i") 3645 (match_operand:SI 3 "const_int_operand" "i")) 3646 (const_int 0))) 3647 (clobber (match_scratch:DI 4 "=r"))] 3648 "TARGET_POWERPC64" 3649 "* 3650{ 3651 int start = INTVAL (operands[3]) & 63; 3652 int size = INTVAL (operands[2]) & 63; 3653 3654 if (start + size >= 64) 3655 operands[3] = const0_rtx; 3656 else 3657 operands[3] = GEN_INT (start + size); 3658 operands[2] = GEN_INT (64 - size); 3659 return \"rldicl. %4,%1,%3,%2\"; 3660}") 3661 3662(define_insn "*extzvdi_internal2" 3663 [(set (match_operand:CC 4 "gpc_reg_operand" "=x") 3664 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3665 (match_operand:SI 2 "const_int_operand" "i") 3666 (match_operand:SI 3 "const_int_operand" "i")) 3667 (const_int 0))) 3668 (set (match_operand:DI 0 "gpc_reg_operand" "=r") 3669 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] 3670 "TARGET_POWERPC64" 3671 "* 3672{ 3673 int start = INTVAL (operands[3]) & 63; 3674 int size = INTVAL (operands[2]) & 63; 3675 3676 if (start + size >= 64) 3677 operands[3] = const0_rtx; 3678 else 3679 operands[3] = GEN_INT (start + size); 3680 operands[2] = GEN_INT (64 - size); 3681 return \"rldicl. %0,%1,%3,%2\"; 3682}") 3683 3684(define_insn "rotlsi3" 3685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3686 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3687 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 3688 "" 3689 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") 3690 3691(define_insn "*rotlsi3_internal2" 3692 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3693 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3694 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3695 (const_int 0))) 3696 (clobber (match_scratch:SI 3 "=r,r"))] 3697 "! TARGET_POWERPC64" 3698 "@ 3699 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff 3700 #" 3701 [(set_attr "type" "delayed_compare") 3702 (set_attr "length" "4,8")]) 3703 3704(define_split 3705 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3706 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3707 (match_operand:SI 2 "reg_or_cint_operand" "")) 3708 (const_int 0))) 3709 (clobber (match_scratch:SI 3 ""))] 3710 "! TARGET_POWERPC64 && reload_completed" 3711 [(set (match_dup 3) 3712 (rotate:SI (match_dup 1) (match_dup 2))) 3713 (set (match_dup 0) 3714 (compare:CC (match_dup 3) 3715 (const_int 0)))] 3716 "") 3717 3718(define_insn "*rotlsi3_internal3" 3719 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3720 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3721 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3722 (const_int 0))) 3723 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3724 (rotate:SI (match_dup 1) (match_dup 2)))] 3725 "! TARGET_POWERPC64" 3726 "@ 3727 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff 3728 #" 3729 [(set_attr "type" "delayed_compare") 3730 (set_attr "length" "4,8")]) 3731 3732(define_split 3733 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3734 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3735 (match_operand:SI 2 "reg_or_cint_operand" "")) 3736 (const_int 0))) 3737 (set (match_operand:SI 0 "gpc_reg_operand" "") 3738 (rotate:SI (match_dup 1) (match_dup 2)))] 3739 "! TARGET_POWERPC64 && reload_completed" 3740 [(set (match_dup 0) 3741 (rotate:SI (match_dup 1) (match_dup 2))) 3742 (set (match_dup 3) 3743 (compare:CC (match_dup 0) 3744 (const_int 0)))] 3745 "") 3746 3747(define_insn "*rotlsi3_internal4" 3748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3749 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3750 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3751 (match_operand:SI 3 "mask_operand" "T")))] 3752 "" 3753 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") 3754 3755(define_insn "*rotlsi3_internal5" 3756 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3757 (compare:CC (and:SI 3758 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3759 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3760 (match_operand:SI 3 "mask_operand" "T,T")) 3761 (const_int 0))) 3762 (clobber (match_scratch:SI 4 "=r,r"))] 3763 "! TARGET_POWERPC64" 3764 "@ 3765 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 3766 #" 3767 [(set_attr "type" "delayed_compare") 3768 (set_attr "length" "4,8")]) 3769 3770(define_split 3771 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3772 (compare:CC (and:SI 3773 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3774 (match_operand:SI 2 "reg_or_cint_operand" "")) 3775 (match_operand:SI 3 "mask_operand" "")) 3776 (const_int 0))) 3777 (clobber (match_scratch:SI 4 ""))] 3778 "! TARGET_POWERPC64 && reload_completed" 3779 [(set (match_dup 4) 3780 (and:SI (rotate:SI (match_dup 1) 3781 (match_dup 2)) 3782 (match_dup 3))) 3783 (set (match_dup 0) 3784 (compare:CC (match_dup 4) 3785 (const_int 0)))] 3786 "") 3787 3788(define_insn "*rotlsi3_internal6" 3789 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3790 (compare:CC (and:SI 3791 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3792 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 3793 (match_operand:SI 3 "mask_operand" "T,T")) 3794 (const_int 0))) 3795 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3796 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3797 "! TARGET_POWERPC64" 3798 "@ 3799 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 3800 #" 3801 [(set_attr "type" "delayed_compare") 3802 (set_attr "length" "4,8")]) 3803 3804(define_split 3805 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 3806 (compare:CC (and:SI 3807 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3808 (match_operand:SI 2 "reg_or_cint_operand" "")) 3809 (match_operand:SI 3 "mask_operand" "")) 3810 (const_int 0))) 3811 (set (match_operand:SI 0 "gpc_reg_operand" "") 3812 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3813 "! TARGET_POWERPC64 && reload_completed" 3814 [(set (match_dup 0) 3815 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 3816 (set (match_dup 4) 3817 (compare:CC (match_dup 0) 3818 (const_int 0)))] 3819 "") 3820 3821(define_insn "*rotlsi3_internal7" 3822 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3823 (zero_extend:SI 3824 (subreg:QI 3825 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3826 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 3827 "" 3828 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") 3829 3830(define_insn "*rotlsi3_internal8" 3831 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3832 (compare:CC (zero_extend:SI 3833 (subreg:QI 3834 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3835 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3836 (const_int 0))) 3837 (clobber (match_scratch:SI 3 "=r,r"))] 3838 "" 3839 "@ 3840 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff 3841 #" 3842 [(set_attr "type" "delayed_compare") 3843 (set_attr "length" "4,8")]) 3844 3845(define_split 3846 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3847 (compare:CC (zero_extend:SI 3848 (subreg:QI 3849 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3850 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 3851 (const_int 0))) 3852 (clobber (match_scratch:SI 3 ""))] 3853 "reload_completed" 3854 [(set (match_dup 3) 3855 (zero_extend:SI (subreg:QI 3856 (rotate:SI (match_dup 1) 3857 (match_dup 2)) 0))) 3858 (set (match_dup 0) 3859 (compare:CC (match_dup 3) 3860 (const_int 0)))] 3861 "") 3862 3863(define_insn "*rotlsi3_internal9" 3864 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3865 (compare:CC (zero_extend:SI 3866 (subreg:QI 3867 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3868 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3869 (const_int 0))) 3870 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3871 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 3872 "" 3873 "@ 3874 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff 3875 #" 3876 [(set_attr "type" "delayed_compare") 3877 (set_attr "length" "4,8")]) 3878 3879(define_split 3880 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3881 (compare:CC (zero_extend:SI 3882 (subreg:QI 3883 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3884 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 3885 (const_int 0))) 3886 (set (match_operand:SI 0 "gpc_reg_operand" "") 3887 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 3888 "reload_completed" 3889 [(set (match_dup 0) 3890 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) 3891 (set (match_dup 3) 3892 (compare:CC (match_dup 0) 3893 (const_int 0)))] 3894 "") 3895 3896(define_insn "*rotlsi3_internal10" 3897 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3898 (zero_extend:SI 3899 (subreg:HI 3900 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3901 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 3902 "" 3903 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") 3904 3905(define_insn "*rotlsi3_internal11" 3906 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3907 (compare:CC (zero_extend:SI 3908 (subreg:HI 3909 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3910 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3911 (const_int 0))) 3912 (clobber (match_scratch:SI 3 "=r,r"))] 3913 "" 3914 "@ 3915 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff 3916 #" 3917 [(set_attr "type" "delayed_compare") 3918 (set_attr "length" "4,8")]) 3919 3920(define_split 3921 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 3922 (compare:CC (zero_extend:SI 3923 (subreg:HI 3924 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3925 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 3926 (const_int 0))) 3927 (clobber (match_scratch:SI 3 ""))] 3928 "reload_completed" 3929 [(set (match_dup 3) 3930 (zero_extend:SI (subreg:HI 3931 (rotate:SI (match_dup 1) 3932 (match_dup 2)) 0))) 3933 (set (match_dup 0) 3934 (compare:CC (match_dup 3) 3935 (const_int 0)))] 3936 "") 3937 3938(define_insn "*rotlsi3_internal12" 3939 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3940 (compare:CC (zero_extend:SI 3941 (subreg:HI 3942 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3943 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) 3944 (const_int 0))) 3945 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3946 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 3947 "" 3948 "@ 3949 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff 3950 #" 3951 [(set_attr "type" "delayed_compare") 3952 (set_attr "length" "4,8")]) 3953 3954(define_split 3955 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 3956 (compare:CC (zero_extend:SI 3957 (subreg:HI 3958 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3959 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 3960 (const_int 0))) 3961 (set (match_operand:SI 0 "gpc_reg_operand" "") 3962 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 3963 "reload_completed" 3964 [(set (match_dup 0) 3965 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) 3966 (set (match_dup 3) 3967 (compare:CC (match_dup 0) 3968 (const_int 0)))] 3969 "") 3970 3971;; Note that we use "sle." instead of "sl." so that we can set 3972;; SHIFT_COUNT_TRUNCATED. 3973 3974(define_expand "ashlsi3" 3975 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 3976 (use (match_operand:SI 1 "gpc_reg_operand" "")) 3977 (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 3978 "" 3979 " 3980{ 3981 if (TARGET_POWER) 3982 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); 3983 else 3984 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); 3985 DONE; 3986}") 3987 3988(define_insn "ashlsi3_power" 3989 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3990 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3991 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 3992 (clobber (match_scratch:SI 3 "=q,X"))] 3993 "TARGET_POWER" 3994 "@ 3995 sle %0,%1,%2 3996 {sli|slwi} %0,%1,%h2") 3997 3998(define_insn "ashlsi3_no_power" 3999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4000 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4001 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 4002 "! TARGET_POWER" 4003 "{sl|slw}%I2 %0,%1,%h2") 4004 4005(define_insn "" 4006 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4007 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4008 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4009 (const_int 0))) 4010 (clobber (match_scratch:SI 3 "=r,r,r,r")) 4011 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4012 "TARGET_POWER" 4013 "@ 4014 sle. %3,%1,%2 4015 {sli.|slwi.} %3,%1,%h2 4016 # 4017 #" 4018 [(set_attr "type" "delayed_compare") 4019 (set_attr "length" "4,4,8,8")]) 4020 4021(define_split 4022 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4023 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4024 (match_operand:SI 2 "reg_or_cint_operand" "")) 4025 (const_int 0))) 4026 (clobber (match_scratch:SI 3 "")) 4027 (clobber (match_scratch:SI 4 ""))] 4028 "TARGET_POWER && reload_completed" 4029 [(parallel [(set (match_dup 3) 4030 (ashift:SI (match_dup 1) (match_dup 2))) 4031 (clobber (match_dup 4))]) 4032 (set (match_dup 0) 4033 (compare:CC (match_dup 3) 4034 (const_int 0)))] 4035 "") 4036 4037(define_insn "" 4038 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4039 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4040 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4041 (const_int 0))) 4042 (clobber (match_scratch:SI 3 "=r,r"))] 4043 "! TARGET_POWER && ! TARGET_POWERPC64" 4044 "@ 4045 {sl|slw}%I2. %3,%1,%h2 4046 #" 4047 [(set_attr "type" "delayed_compare") 4048 (set_attr "length" "4,8")]) 4049 4050(define_split 4051 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4052 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4053 (match_operand:SI 2 "reg_or_cint_operand" "")) 4054 (const_int 0))) 4055 (clobber (match_scratch:SI 3 ""))] 4056 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" 4057 [(set (match_dup 3) 4058 (ashift:SI (match_dup 1) (match_dup 2))) 4059 (set (match_dup 0) 4060 (compare:CC (match_dup 3) 4061 (const_int 0)))] 4062 "") 4063 4064(define_insn "" 4065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4066 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4067 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4068 (const_int 0))) 4069 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4070 (ashift:SI (match_dup 1) (match_dup 2))) 4071 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4072 "TARGET_POWER" 4073 "@ 4074 sle. %0,%1,%2 4075 {sli.|slwi.} %0,%1,%h2 4076 # 4077 #" 4078 [(set_attr "type" "delayed_compare") 4079 (set_attr "length" "4,4,8,8")]) 4080 4081(define_split 4082 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4083 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4084 (match_operand:SI 2 "reg_or_cint_operand" "")) 4085 (const_int 0))) 4086 (set (match_operand:SI 0 "gpc_reg_operand" "") 4087 (ashift:SI (match_dup 1) (match_dup 2))) 4088 (clobber (match_scratch:SI 4 ""))] 4089 "TARGET_POWER && reload_completed" 4090 [(parallel [(set (match_dup 0) 4091 (ashift:SI (match_dup 1) (match_dup 2))) 4092 (clobber (match_dup 4))]) 4093 (set (match_dup 3) 4094 (compare:CC (match_dup 0) 4095 (const_int 0)))] 4096 "") 4097 4098(define_insn "" 4099 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4100 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4101 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4102 (const_int 0))) 4103 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4104 (ashift:SI (match_dup 1) (match_dup 2)))] 4105 "! TARGET_POWER && ! TARGET_POWERPC64" 4106 "@ 4107 {sl|slw}%I2. %0,%1,%h2 4108 #" 4109 [(set_attr "type" "delayed_compare") 4110 (set_attr "length" "4,8")]) 4111 4112(define_split 4113 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4114 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4115 (match_operand:SI 2 "reg_or_cint_operand" "")) 4116 (const_int 0))) 4117 (set (match_operand:SI 0 "gpc_reg_operand" "") 4118 (ashift:SI (match_dup 1) (match_dup 2)))] 4119 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" 4120 [(set (match_dup 0) 4121 (ashift:SI (match_dup 1) (match_dup 2))) 4122 (set (match_dup 3) 4123 (compare:CC (match_dup 0) 4124 (const_int 0)))] 4125 "") 4126 4127(define_insn "" 4128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4129 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4130 (match_operand:SI 2 "const_int_operand" "i")) 4131 (match_operand:SI 3 "mask_operand" "T")))] 4132 "includes_lshift_p (operands[2], operands[3])" 4133 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") 4134 4135(define_insn "" 4136 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4137 (compare:CC 4138 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4139 (match_operand:SI 2 "const_int_operand" "i,i")) 4140 (match_operand:SI 3 "mask_operand" "T,T")) 4141 (const_int 0))) 4142 (clobber (match_scratch:SI 4 "=r,r"))] 4143 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" 4144 "@ 4145 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 4146 #" 4147 [(set_attr "type" "delayed_compare") 4148 (set_attr "length" "4,8")]) 4149 4150(define_split 4151 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4152 (compare:CC 4153 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4154 (match_operand:SI 2 "const_int_operand" "")) 4155 (match_operand:SI 3 "mask_operand" "")) 4156 (const_int 0))) 4157 (clobber (match_scratch:SI 4 ""))] 4158 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" 4159 [(set (match_dup 4) 4160 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) 4161 (match_dup 3))) 4162 (set (match_dup 0) 4163 (compare:CC (match_dup 4) 4164 (const_int 0)))] 4165 "") 4166 4167(define_insn "" 4168 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 4169 (compare:CC 4170 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4171 (match_operand:SI 2 "const_int_operand" "i,i")) 4172 (match_operand:SI 3 "mask_operand" "T,T")) 4173 (const_int 0))) 4174 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4175 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4176 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" 4177 "@ 4178 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 4179 #" 4180 [(set_attr "type" "delayed_compare") 4181 (set_attr "length" "4,8")]) 4182 4183(define_split 4184 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 4185 (compare:CC 4186 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4187 (match_operand:SI 2 "const_int_operand" "")) 4188 (match_operand:SI 3 "mask_operand" "")) 4189 (const_int 0))) 4190 (set (match_operand:SI 0 "gpc_reg_operand" "") 4191 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4192 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" 4193 [(set (match_dup 0) 4194 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 4195 (set (match_dup 4) 4196 (compare:CC (match_dup 0) 4197 (const_int 0)))] 4198 "") 4199 4200;; The AIX assembler mis-handles "sri x,x,0", so write that case as 4201;; "sli x,x,0". 4202(define_expand "lshrsi3" 4203 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 4204 (use (match_operand:SI 1 "gpc_reg_operand" "")) 4205 (use (match_operand:SI 2 "reg_or_cint_operand" ""))] 4206 "" 4207 " 4208{ 4209 if (TARGET_POWER) 4210 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); 4211 else 4212 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); 4213 DONE; 4214}") 4215 4216(define_insn "lshrsi3_power" 4217 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 4218 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") 4219 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) 4220 (clobber (match_scratch:SI 3 "=q,X,X"))] 4221 "TARGET_POWER" 4222 "@ 4223 sre %0,%1,%2 4224 mr %0,%1 4225 {s%A2i|s%A2wi} %0,%1,%h2") 4226 4227(define_insn "lshrsi3_no_power" 4228 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4229 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4230 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] 4231 "! TARGET_POWER" 4232 "@ 4233 mr %0,%1 4234 {sr|srw}%I2 %0,%1,%h2") 4235 4236(define_insn "" 4237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") 4238 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") 4239 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) 4240 (const_int 0))) 4241 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) 4242 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] 4243 "TARGET_POWER" 4244 "@ 4245 sre. %3,%1,%2 4246 mr. %1,%1 4247 {s%A2i.|s%A2wi.} %3,%1,%h2 4248 # 4249 # 4250 #" 4251 [(set_attr "type" "delayed_compare") 4252 (set_attr "length" "4,4,4,8,8,8")]) 4253 4254(define_split 4255 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4256 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4257 (match_operand:SI 2 "reg_or_cint_operand" "")) 4258 (const_int 0))) 4259 (clobber (match_scratch:SI 3 "")) 4260 (clobber (match_scratch:SI 4 ""))] 4261 "TARGET_POWER && reload_completed" 4262 [(parallel [(set (match_dup 3) 4263 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4264 (clobber (match_dup 4))]) 4265 (set (match_dup 0) 4266 (compare:CC (match_dup 3) 4267 (const_int 0)))] 4268 "") 4269 4270(define_insn "" 4271 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4272 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4273 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) 4274 (const_int 0))) 4275 (clobber (match_scratch:SI 3 "=X,r,X,r"))] 4276 "! TARGET_POWER && ! TARGET_POWERPC64" 4277 "@ 4278 mr. %1,%1 4279 {sr|srw}%I2. %3,%1,%h2 4280 # 4281 #" 4282 [(set_attr "type" "delayed_compare") 4283 (set_attr "length" "4,4,8,8")]) 4284 4285(define_split 4286 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4287 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4288 (match_operand:SI 2 "reg_or_cint_operand" "")) 4289 (const_int 0))) 4290 (clobber (match_scratch:SI 3 ""))] 4291 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" 4292 [(set (match_dup 3) 4293 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4294 (set (match_dup 0) 4295 (compare:CC (match_dup 3) 4296 (const_int 0)))] 4297 "") 4298 4299(define_insn "" 4300 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") 4301 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") 4302 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) 4303 (const_int 0))) 4304 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") 4305 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4306 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] 4307 "TARGET_POWER" 4308 "@ 4309 sre. %0,%1,%2 4310 mr. %0,%1 4311 {s%A2i.|s%A2wi.} %0,%1,%h2 4312 # 4313 # 4314 #" 4315 [(set_attr "type" "delayed_compare") 4316 (set_attr "length" "4,4,4,8,8,8")]) 4317 4318(define_split 4319 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4320 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4321 (match_operand:SI 2 "reg_or_cint_operand" "")) 4322 (const_int 0))) 4323 (set (match_operand:SI 0 "gpc_reg_operand" "") 4324 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4325 (clobber (match_scratch:SI 4 ""))] 4326 "TARGET_POWER && reload_completed" 4327 [(parallel [(set (match_dup 0) 4328 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4329 (clobber (match_dup 4))]) 4330 (set (match_dup 3) 4331 (compare:CC (match_dup 0) 4332 (const_int 0)))] 4333 "") 4334 4335(define_insn "" 4336 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4337 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4338 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) 4339 (const_int 0))) 4340 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4341 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 4342 "! TARGET_POWER && ! TARGET_POWERPC64" 4343 "@ 4344 mr. %0,%1 4345 {sr|srw}%I2. %0,%1,%h2 4346 # 4347 #" 4348 [(set_attr "type" "delayed_compare") 4349 (set_attr "length" "4,4,8,8")]) 4350 4351(define_split 4352 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4353 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4354 (match_operand:SI 2 "reg_or_cint_operand" "")) 4355 (const_int 0))) 4356 (set (match_operand:SI 0 "gpc_reg_operand" "") 4357 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 4358 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" 4359 [(set (match_dup 0) 4360 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4361 (set (match_dup 3) 4362 (compare:CC (match_dup 0) 4363 (const_int 0)))] 4364 "") 4365 4366(define_insn "" 4367 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4368 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4369 (match_operand:SI 2 "const_int_operand" "i")) 4370 (match_operand:SI 3 "mask_operand" "T")))] 4371 "includes_rshift_p (operands[2], operands[3])" 4372 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") 4373 4374(define_insn "" 4375 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4376 (compare:CC 4377 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4378 (match_operand:SI 2 "const_int_operand" "i,i")) 4379 (match_operand:SI 3 "mask_operand" "T,T")) 4380 (const_int 0))) 4381 (clobber (match_scratch:SI 4 "=r,r"))] 4382 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" 4383 "@ 4384 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 4385 #" 4386 [(set_attr "type" "delayed_compare") 4387 (set_attr "length" "4,8")]) 4388 4389(define_split 4390 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4391 (compare:CC 4392 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4393 (match_operand:SI 2 "const_int_operand" "")) 4394 (match_operand:SI 3 "mask_operand" "")) 4395 (const_int 0))) 4396 (clobber (match_scratch:SI 4 ""))] 4397 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" 4398 [(set (match_dup 4) 4399 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) 4400 (match_dup 3))) 4401 (set (match_dup 0) 4402 (compare:CC (match_dup 4) 4403 (const_int 0)))] 4404 "") 4405 4406(define_insn "" 4407 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 4408 (compare:CC 4409 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4410 (match_operand:SI 2 "const_int_operand" "i,i")) 4411 (match_operand:SI 3 "mask_operand" "T,T")) 4412 (const_int 0))) 4413 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4414 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4415 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" 4416 "@ 4417 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 4418 #" 4419 [(set_attr "type" "delayed_compare") 4420 (set_attr "length" "4,8")]) 4421 4422(define_split 4423 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 4424 (compare:CC 4425 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4426 (match_operand:SI 2 "const_int_operand" "")) 4427 (match_operand:SI 3 "mask_operand" "")) 4428 (const_int 0))) 4429 (set (match_operand:SI 0 "gpc_reg_operand" "") 4430 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4431 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" 4432 [(set (match_dup 0) 4433 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 4434 (set (match_dup 4) 4435 (compare:CC (match_dup 0) 4436 (const_int 0)))] 4437 "") 4438 4439(define_insn "" 4440 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4441 (zero_extend:SI 4442 (subreg:QI 4443 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4444 (match_operand:SI 2 "const_int_operand" "i")) 0)))] 4445 "includes_rshift_p (operands[2], GEN_INT (255))" 4446 "{rlinm|rlwinm} %0,%1,%s2,0xff") 4447 4448(define_insn "" 4449 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4450 (compare:CC 4451 (zero_extend:SI 4452 (subreg:QI 4453 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4454 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4455 (const_int 0))) 4456 (clobber (match_scratch:SI 3 "=r,r"))] 4457 "includes_rshift_p (operands[2], GEN_INT (255))" 4458 "@ 4459 {rlinm.|rlwinm.} %3,%1,%s2,0xff 4460 #" 4461 [(set_attr "type" "delayed_compare") 4462 (set_attr "length" "4,8")]) 4463 4464(define_split 4465 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4466 (compare:CC 4467 (zero_extend:SI 4468 (subreg:QI 4469 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4470 (match_operand:SI 2 "const_int_operand" "")) 0)) 4471 (const_int 0))) 4472 (clobber (match_scratch:SI 3 ""))] 4473 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4474 [(set (match_dup 3) 4475 (zero_extend:SI (subreg:QI 4476 (lshiftrt:SI (match_dup 1) 4477 (match_dup 2)) 0))) 4478 (set (match_dup 0) 4479 (compare:CC (match_dup 3) 4480 (const_int 0)))] 4481 "") 4482 4483(define_insn "" 4484 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4485 (compare:CC 4486 (zero_extend:SI 4487 (subreg:QI 4488 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4489 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4490 (const_int 0))) 4491 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4492 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4493 "includes_rshift_p (operands[2], GEN_INT (255))" 4494 "@ 4495 {rlinm.|rlwinm.} %0,%1,%s2,0xff 4496 #" 4497 [(set_attr "type" "delayed_compare") 4498 (set_attr "length" "4,8")]) 4499 4500(define_split 4501 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4502 (compare:CC 4503 (zero_extend:SI 4504 (subreg:QI 4505 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4506 (match_operand:SI 2 "const_int_operand" "")) 0)) 4507 (const_int 0))) 4508 (set (match_operand:SI 0 "gpc_reg_operand" "") 4509 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4510 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4511 [(set (match_dup 0) 4512 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) 4513 (set (match_dup 3) 4514 (compare:CC (match_dup 0) 4515 (const_int 0)))] 4516 "") 4517 4518(define_insn "" 4519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4520 (zero_extend:SI 4521 (subreg:HI 4522 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4523 (match_operand:SI 2 "const_int_operand" "i")) 0)))] 4524 "includes_rshift_p (operands[2], GEN_INT (65535))" 4525 "{rlinm|rlwinm} %0,%1,%s2,0xffff") 4526 4527(define_insn "" 4528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4529 (compare:CC 4530 (zero_extend:SI 4531 (subreg:HI 4532 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4533 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4534 (const_int 0))) 4535 (clobber (match_scratch:SI 3 "=r,r"))] 4536 "includes_rshift_p (operands[2], GEN_INT (65535))" 4537 "@ 4538 {rlinm.|rlwinm.} %3,%1,%s2,0xffff 4539 #" 4540 [(set_attr "type" "delayed_compare") 4541 (set_attr "length" "4,8")]) 4542 4543(define_split 4544 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4545 (compare:CC 4546 (zero_extend:SI 4547 (subreg:HI 4548 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4549 (match_operand:SI 2 "const_int_operand" "")) 0)) 4550 (const_int 0))) 4551 (clobber (match_scratch:SI 3 ""))] 4552 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4553 [(set (match_dup 3) 4554 (zero_extend:SI (subreg:HI 4555 (lshiftrt:SI (match_dup 1) 4556 (match_dup 2)) 0))) 4557 (set (match_dup 0) 4558 (compare:CC (match_dup 3) 4559 (const_int 0)))] 4560 "") 4561 4562(define_insn "" 4563 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4564 (compare:CC 4565 (zero_extend:SI 4566 (subreg:HI 4567 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4568 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4569 (const_int 0))) 4570 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4571 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4572 "includes_rshift_p (operands[2], GEN_INT (65535))" 4573 "@ 4574 {rlinm.|rlwinm.} %0,%1,%s2,0xffff 4575 #" 4576 [(set_attr "type" "delayed_compare") 4577 (set_attr "length" "4,8")]) 4578 4579(define_split 4580 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4581 (compare:CC 4582 (zero_extend:SI 4583 (subreg:HI 4584 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4585 (match_operand:SI 2 "const_int_operand" "")) 0)) 4586 (const_int 0))) 4587 (set (match_operand:SI 0 "gpc_reg_operand" "") 4588 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4589 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4590 [(set (match_dup 0) 4591 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) 4592 (set (match_dup 3) 4593 (compare:CC (match_dup 0) 4594 (const_int 0)))] 4595 "") 4596 4597(define_insn "" 4598 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 4599 (const_int 1) 4600 (match_operand:SI 1 "gpc_reg_operand" "r")) 4601 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 4602 (const_int 31)))] 4603 "TARGET_POWER" 4604 "rrib %0,%1,%2") 4605 4606(define_insn "" 4607 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 4608 (const_int 1) 4609 (match_operand:SI 1 "gpc_reg_operand" "r")) 4610 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") 4611 (const_int 31)))] 4612 "TARGET_POWER" 4613 "rrib %0,%1,%2") 4614 4615(define_insn "" 4616 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 4617 (const_int 1) 4618 (match_operand:SI 1 "gpc_reg_operand" "r")) 4619 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") 4620 (const_int 1) 4621 (const_int 0)))] 4622 "TARGET_POWER" 4623 "rrib %0,%1,%2") 4624 4625(define_expand "ashrsi3" 4626 [(set (match_operand:SI 0 "gpc_reg_operand" "") 4627 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4628 (match_operand:SI 2 "reg_or_cint_operand" "")))] 4629 "" 4630 " 4631{ 4632 if (TARGET_POWER) 4633 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); 4634 else 4635 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); 4636 DONE; 4637}") 4638 4639(define_insn "ashrsi3_power" 4640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4641 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4642 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) 4643 (clobber (match_scratch:SI 3 "=q,X"))] 4644 "TARGET_POWER" 4645 "@ 4646 srea %0,%1,%2 4647 {srai|srawi} %0,%1,%h2") 4648 4649(define_insn "ashrsi3_no_power" 4650 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4651 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4652 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 4653 "! TARGET_POWER" 4654 "{sra|sraw}%I2 %0,%1,%h2") 4655 4656(define_insn "" 4657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4658 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4659 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4660 (const_int 0))) 4661 (clobber (match_scratch:SI 3 "=r,r,r,r")) 4662 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4663 "TARGET_POWER" 4664 "@ 4665 srea. %3,%1,%2 4666 {srai.|srawi.} %3,%1,%h2 4667 # 4668 #" 4669 [(set_attr "type" "delayed_compare") 4670 (set_attr "length" "4,4,8,8")]) 4671 4672(define_split 4673 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4674 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4675 (match_operand:SI 2 "reg_or_cint_operand" "")) 4676 (const_int 0))) 4677 (clobber (match_scratch:SI 3 "")) 4678 (clobber (match_scratch:SI 4 ""))] 4679 "TARGET_POWER && reload_completed" 4680 [(parallel [(set (match_dup 3) 4681 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4682 (clobber (match_dup 4))]) 4683 (set (match_dup 0) 4684 (compare:CC (match_dup 3) 4685 (const_int 0)))] 4686 "") 4687 4688(define_insn "" 4689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4690 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4691 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4692 (const_int 0))) 4693 (clobber (match_scratch:SI 3 "=r,r"))] 4694 "! TARGET_POWER" 4695 "@ 4696 {sra|sraw}%I2. %3,%1,%h2 4697 #" 4698 [(set_attr "type" "delayed_compare") 4699 (set_attr "length" "4,8")]) 4700 4701(define_split 4702 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4703 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4704 (match_operand:SI 2 "reg_or_cint_operand" "")) 4705 (const_int 0))) 4706 (clobber (match_scratch:SI 3 ""))] 4707 "! TARGET_POWER && reload_completed" 4708 [(set (match_dup 3) 4709 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4710 (set (match_dup 0) 4711 (compare:CC (match_dup 3) 4712 (const_int 0)))] 4713 "") 4714 4715(define_insn "" 4716 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4717 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4718 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4719 (const_int 0))) 4720 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4721 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4722 (clobber (match_scratch:SI 4 "=q,X,q,X"))] 4723 "TARGET_POWER" 4724 "@ 4725 srea. %0,%1,%2 4726 {srai.|srawi.} %0,%1,%h2 4727 # 4728 #" 4729 [(set_attr "type" "delayed_compare") 4730 (set_attr "length" "4,4,8,8")]) 4731 4732(define_split 4733 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4734 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4735 (match_operand:SI 2 "reg_or_cint_operand" "")) 4736 (const_int 0))) 4737 (set (match_operand:SI 0 "gpc_reg_operand" "") 4738 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4739 (clobber (match_scratch:SI 4 ""))] 4740 "TARGET_POWER && reload_completed" 4741 [(parallel [(set (match_dup 0) 4742 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4743 (clobber (match_dup 4))]) 4744 (set (match_dup 3) 4745 (compare:CC (match_dup 0) 4746 (const_int 0)))] 4747 "") 4748 4749(define_insn "" 4750 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4751 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4752 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 4753 (const_int 0))) 4754 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4755 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 4756 "! TARGET_POWER" 4757 "@ 4758 {sra|sraw}%I2. %0,%1,%h2 4759 #" 4760 [(set_attr "type" "delayed_compare") 4761 (set_attr "length" "4,8")]) 4762 4763(define_split 4764 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4765 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4766 (match_operand:SI 2 "reg_or_cint_operand" "")) 4767 (const_int 0))) 4768 (set (match_operand:SI 0 "gpc_reg_operand" "") 4769 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 4770 "! TARGET_POWER && reload_completed" 4771 [(set (match_dup 0) 4772 (ashiftrt:SI (match_dup 1) (match_dup 2))) 4773 (set (match_dup 3) 4774 (compare:CC (match_dup 0) 4775 (const_int 0)))] 4776 "") 4777 4778;; Floating-point insns, excluding normal data motion. 4779;; 4780;; PowerPC has a full set of single-precision floating point instructions. 4781;; 4782;; For the POWER architecture, we pretend that we have both SFmode and 4783;; DFmode insns, while, in fact, all fp insns are actually done in double. 4784;; The only conversions we will do will be when storing to memory. In that 4785;; case, we will use the "frsp" instruction before storing. 4786;; 4787;; Note that when we store into a single-precision memory location, we need to 4788;; use the frsp insn first. If the register being stored isn't dead, we 4789;; need a scratch register for the frsp. But this is difficult when the store 4790;; is done by reload. It is not incorrect to do the frsp on the register in 4791;; this case, we just lose precision that we would have otherwise gotten but 4792;; is not guaranteed. Perhaps this should be tightened up at some point. 4793 4794(define_insn "extendsfdf2" 4795 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 4796 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4797 "TARGET_HARD_FLOAT" 4798 "* 4799{ 4800 if (REGNO (operands[0]) == REGNO (operands[1])) 4801 return \"\"; 4802 else 4803 return \"fmr %0,%1\"; 4804}" 4805 [(set_attr "type" "fp")]) 4806 4807(define_insn "truncdfsf2" 4808 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4809 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] 4810 "TARGET_HARD_FLOAT" 4811 "frsp %0,%1" 4812 [(set_attr "type" "fp")]) 4813 4814(define_insn "aux_truncdfsf2" 4815 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4816 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] 4817 "! TARGET_POWERPC && TARGET_HARD_FLOAT" 4818 "frsp %0,%1" 4819 [(set_attr "type" "fp")]) 4820 4821(define_insn "negsf2" 4822 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4823 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4824 "TARGET_HARD_FLOAT" 4825 "fneg %0,%1" 4826 [(set_attr "type" "fp")]) 4827 4828(define_insn "abssf2" 4829 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4830 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 4831 "TARGET_HARD_FLOAT" 4832 "fabs %0,%1" 4833 [(set_attr "type" "fp")]) 4834 4835(define_insn "" 4836 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4837 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] 4838 "TARGET_HARD_FLOAT" 4839 "fnabs %0,%1" 4840 [(set_attr "type" "fp")]) 4841 4842(define_expand "addsf3" 4843 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4844 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") 4845 (match_operand:SF 2 "gpc_reg_operand" "")))] 4846 "TARGET_HARD_FLOAT" 4847 "") 4848 4849(define_insn "" 4850 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4851 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4852 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4853 "TARGET_POWERPC && TARGET_HARD_FLOAT" 4854 "fadds %0,%1,%2" 4855 [(set_attr "type" "fp")]) 4856 4857(define_insn "" 4858 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4859 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4860 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4861 "! TARGET_POWERPC && TARGET_HARD_FLOAT" 4862 "{fa|fadd} %0,%1,%2" 4863 [(set_attr "type" "fp")]) 4864 4865(define_expand "subsf3" 4866 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4867 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") 4868 (match_operand:SF 2 "gpc_reg_operand" "")))] 4869 "TARGET_HARD_FLOAT" 4870 "") 4871 4872(define_insn "" 4873 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4874 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 4875 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4876 "TARGET_POWERPC && TARGET_HARD_FLOAT" 4877 "fsubs %0,%1,%2" 4878 [(set_attr "type" "fp")]) 4879 4880(define_insn "" 4881 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4882 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") 4883 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4884 "! TARGET_POWERPC && TARGET_HARD_FLOAT" 4885 "{fs|fsub} %0,%1,%2" 4886 [(set_attr "type" "fp")]) 4887 4888(define_expand "mulsf3" 4889 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4890 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") 4891 (match_operand:SF 2 "gpc_reg_operand" "")))] 4892 "TARGET_HARD_FLOAT" 4893 "") 4894 4895(define_insn "" 4896 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4897 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4898 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4899 "TARGET_POWERPC && TARGET_HARD_FLOAT" 4900 "fmuls %0,%1,%2" 4901 [(set_attr "type" "fp")]) 4902 4903(define_insn "" 4904 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4905 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4906 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4907 "! TARGET_POWERPC && TARGET_HARD_FLOAT" 4908 "{fm|fmul} %0,%1,%2" 4909 [(set_attr "type" "dmul")]) 4910 4911(define_expand "divsf3" 4912 [(set (match_operand:SF 0 "gpc_reg_operand" "") 4913 (div:SF (match_operand:SF 1 "gpc_reg_operand" "") 4914 (match_operand:SF 2 "gpc_reg_operand" "")))] 4915 "TARGET_HARD_FLOAT" 4916 "") 4917 4918(define_insn "" 4919 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4920 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 4921 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4922 "TARGET_POWERPC && TARGET_HARD_FLOAT" 4923 "fdivs %0,%1,%2" 4924 [(set_attr "type" "sdiv")]) 4925 4926(define_insn "" 4927 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4928 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") 4929 (match_operand:SF 2 "gpc_reg_operand" "f")))] 4930 "! TARGET_POWERPC && TARGET_HARD_FLOAT" 4931 "{fd|fdiv} %0,%1,%2" 4932 [(set_attr "type" "ddiv")]) 4933 4934(define_insn "" 4935 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4936 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4937 (match_operand:SF 2 "gpc_reg_operand" "f")) 4938 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4939 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 4940 "fmadds %0,%1,%2,%3" 4941 [(set_attr "type" "fp")]) 4942 4943(define_insn "" 4944 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4945 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4946 (match_operand:SF 2 "gpc_reg_operand" "f")) 4947 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4948 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 4949 "{fma|fmadd} %0,%1,%2,%3" 4950 [(set_attr "type" "dmul")]) 4951 4952(define_insn "" 4953 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4954 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4955 (match_operand:SF 2 "gpc_reg_operand" "f")) 4956 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4957 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 4958 "fmsubs %0,%1,%2,%3" 4959 [(set_attr "type" "fp")]) 4960 4961(define_insn "" 4962 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4963 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4964 (match_operand:SF 2 "gpc_reg_operand" "f")) 4965 (match_operand:SF 3 "gpc_reg_operand" "f")))] 4966 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 4967 "{fms|fmsub} %0,%1,%2,%3" 4968 [(set_attr "type" "dmul")]) 4969 4970(define_insn "" 4971 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4972 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4973 (match_operand:SF 2 "gpc_reg_operand" "f")) 4974 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 4975 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 4976 "fnmadds %0,%1,%2,%3" 4977 [(set_attr "type" "fp")]) 4978 4979(define_insn "" 4980 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4981 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4982 (match_operand:SF 2 "gpc_reg_operand" "f")) 4983 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 4984 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 4985 "{fnma|fnmadd} %0,%1,%2,%3" 4986 [(set_attr "type" "dmul")]) 4987 4988(define_insn "" 4989 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4990 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 4991 (match_operand:SF 2 "gpc_reg_operand" "f")) 4992 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 4993 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 4994 "fnmsubs %0,%1,%2,%3" 4995 [(set_attr "type" "fp")]) 4996 4997(define_insn "" 4998 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 4999 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5000 (match_operand:SF 2 "gpc_reg_operand" "f")) 5001 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 5002 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 5003 "{fnms|fnmsub} %0,%1,%2,%3" 5004 [(set_attr "type" "dmul")]) 5005 5006(define_expand "sqrtsf2" 5007 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5008 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] 5009 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" 5010 "") 5011 5012(define_insn "" 5013 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5014 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 5015 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" 5016 "fsqrts %0,%1" 5017 [(set_attr "type" "ssqrt")]) 5018 5019(define_insn "" 5020 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5021 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] 5022 "TARGET_POWER2 && TARGET_HARD_FLOAT" 5023 "fsqrt %0,%1" 5024 [(set_attr "type" "dsqrt")]) 5025 5026;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a 5027;; fsel instruction and some auxiliary computations. Then we just have a 5028;; single DEFINE_INSN for fsel and the define_splits to make them if made by 5029;; combine. 5030(define_expand "maxsf3" 5031 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5032 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") 5033 (match_operand:SF 2 "gpc_reg_operand" "")) 5034 (match_dup 1) 5035 (match_dup 2)))] 5036 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5037 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") 5038 5039(define_expand "minsf3" 5040 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5041 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") 5042 (match_operand:SF 2 "gpc_reg_operand" "")) 5043 (match_dup 2) 5044 (match_dup 1)))] 5045 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5046 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") 5047 5048(define_split 5049 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5050 (match_operator:SF 3 "min_max_operator" 5051 [(match_operand:SF 1 "gpc_reg_operand" "") 5052 (match_operand:SF 2 "gpc_reg_operand" "")]))] 5053 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5054 [(const_int 0)] 5055 " 5056{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), 5057 operands[1], operands[2]); 5058 DONE; 5059}") 5060 5061(define_expand "movsfcc" 5062 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5063 (if_then_else:SF (match_operand 1 "comparison_operator" "") 5064 (match_operand:SF 2 "gpc_reg_operand" "") 5065 (match_operand:SF 3 "gpc_reg_operand" "")))] 5066 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5067 " 5068{ 5069 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 5070 DONE; 5071 else 5072 FAIL; 5073}") 5074 5075(define_insn "*fselsfsf4" 5076 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5077 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 5078 (match_operand:SF 4 "zero_fp_constant" "F")) 5079 (match_operand:SF 2 "gpc_reg_operand" "f") 5080 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5081 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5082 "fsel %0,%1,%2,%3" 5083 [(set_attr "type" "fp")]) 5084 5085(define_insn "*fseldfsf4" 5086 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5087 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 5088 (match_operand:DF 4 "zero_fp_constant" "F")) 5089 (match_operand:SF 2 "gpc_reg_operand" "f") 5090 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5091 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5092 "fsel %0,%1,%2,%3" 5093 [(set_attr "type" "fp")]) 5094 5095(define_insn "negdf2" 5096 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5097 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 5098 "TARGET_HARD_FLOAT" 5099 "fneg %0,%1" 5100 [(set_attr "type" "fp")]) 5101 5102(define_insn "absdf2" 5103 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5104 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 5105 "TARGET_HARD_FLOAT" 5106 "fabs %0,%1" 5107 [(set_attr "type" "fp")]) 5108 5109(define_insn "" 5110 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5111 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] 5112 "TARGET_HARD_FLOAT" 5113 "fnabs %0,%1" 5114 [(set_attr "type" "fp")]) 5115 5116(define_insn "adddf3" 5117 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5118 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5119 (match_operand:DF 2 "gpc_reg_operand" "f")))] 5120 "TARGET_HARD_FLOAT" 5121 "{fa|fadd} %0,%1,%2" 5122 [(set_attr "type" "fp")]) 5123 5124(define_insn "subdf3" 5125 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5126 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") 5127 (match_operand:DF 2 "gpc_reg_operand" "f")))] 5128 "TARGET_HARD_FLOAT" 5129 "{fs|fsub} %0,%1,%2" 5130 [(set_attr "type" "fp")]) 5131 5132(define_insn "muldf3" 5133 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5134 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5135 (match_operand:DF 2 "gpc_reg_operand" "f")))] 5136 "TARGET_HARD_FLOAT" 5137 "{fm|fmul} %0,%1,%2" 5138 [(set_attr "type" "dmul")]) 5139 5140(define_insn "divdf3" 5141 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5142 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") 5143 (match_operand:DF 2 "gpc_reg_operand" "f")))] 5144 "TARGET_HARD_FLOAT" 5145 "{fd|fdiv} %0,%1,%2" 5146 [(set_attr "type" "ddiv")]) 5147 5148(define_insn "" 5149 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5150 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5151 (match_operand:DF 2 "gpc_reg_operand" "f")) 5152 (match_operand:DF 3 "gpc_reg_operand" "f")))] 5153 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 5154 "{fma|fmadd} %0,%1,%2,%3" 5155 [(set_attr "type" "dmul")]) 5156 5157(define_insn "" 5158 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5159 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5160 (match_operand:DF 2 "gpc_reg_operand" "f")) 5161 (match_operand:DF 3 "gpc_reg_operand" "f")))] 5162 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 5163 "{fms|fmsub} %0,%1,%2,%3" 5164 [(set_attr "type" "dmul")]) 5165 5166(define_insn "" 5167 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5168 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5169 (match_operand:DF 2 "gpc_reg_operand" "f")) 5170 (match_operand:DF 3 "gpc_reg_operand" "f"))))] 5171 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 5172 "{fnma|fnmadd} %0,%1,%2,%3" 5173 [(set_attr "type" "dmul")]) 5174 5175(define_insn "" 5176 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5177 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 5178 (match_operand:DF 2 "gpc_reg_operand" "f")) 5179 (match_operand:DF 3 "gpc_reg_operand" "f"))))] 5180 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" 5181 "{fnms|fnmsub} %0,%1,%2,%3" 5182 [(set_attr "type" "dmul")]) 5183 5184(define_insn "sqrtdf2" 5185 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5186 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 5187 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" 5188 "fsqrt %0,%1" 5189 [(set_attr "type" "dsqrt")]) 5190 5191;; The conditional move instructions allow us to perform max and min 5192;; operations even when 5193 5194(define_expand "maxdf3" 5195 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5196 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") 5197 (match_operand:DF 2 "gpc_reg_operand" "")) 5198 (match_dup 1) 5199 (match_dup 2)))] 5200 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5201 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") 5202 5203(define_expand "mindf3" 5204 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5205 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") 5206 (match_operand:DF 2 "gpc_reg_operand" "")) 5207 (match_dup 2) 5208 (match_dup 1)))] 5209 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5210 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") 5211 5212(define_split 5213 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5214 (match_operator:DF 3 "min_max_operator" 5215 [(match_operand:DF 1 "gpc_reg_operand" "") 5216 (match_operand:DF 2 "gpc_reg_operand" "")]))] 5217 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5218 [(const_int 0)] 5219 " 5220{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), 5221 operands[1], operands[2]); 5222 DONE; 5223}") 5224 5225(define_expand "movdfcc" 5226 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5227 (if_then_else:DF (match_operand 1 "comparison_operator" "") 5228 (match_operand:DF 2 "gpc_reg_operand" "") 5229 (match_operand:DF 3 "gpc_reg_operand" "")))] 5230 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5231 " 5232{ 5233 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 5234 DONE; 5235 else 5236 FAIL; 5237}") 5238 5239(define_insn "*fseldfdf4" 5240 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5241 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 5242 (match_operand:DF 4 "zero_fp_constant" "F")) 5243 (match_operand:DF 2 "gpc_reg_operand" "f") 5244 (match_operand:DF 3 "gpc_reg_operand" "f")))] 5245 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" 5246 "fsel %0,%1,%2,%3" 5247 [(set_attr "type" "fp")]) 5248 5249(define_insn "*fselsfdf4" 5250 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5251 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 5252 (match_operand:SF 4 "zero_fp_constant" "F")) 5253 (match_operand:DF 2 "gpc_reg_operand" "f") 5254 (match_operand:DF 3 "gpc_reg_operand" "f")))] 5255 "TARGET_PPC_GFXOPT" 5256 "fsel %0,%1,%2,%3" 5257 [(set_attr "type" "fp")]) 5258 5259;; Conversions to and from floating-point. 5260 5261; For each of these conversions, there is a define_expand, a define_insn 5262; with a '#' template, and a define_split (with C code). The idea is 5263; to allow constant folding with the template of the define_insn, 5264; then to have the insns split later (between sched1 and final). 5265 5266(define_expand "floatsidf2" 5267 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") 5268 (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5269 (use (match_dup 2)) 5270 (use (match_dup 3)) 5271 (clobber (match_dup 4)) 5272 (clobber (match_dup 5)) 5273 (clobber (match_dup 6))])] 5274 "TARGET_HARD_FLOAT" 5275 " 5276{ 5277 if (TARGET_POWERPC64) 5278 { 5279 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 5280 rtx t1 = gen_reg_rtx (DImode); 5281 rtx t2 = gen_reg_rtx (DImode); 5282 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); 5283 DONE; 5284 } 5285 5286 operands[2] = force_reg (SImode, GEN_INT (0x43300000)); 5287 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); 5288 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); 5289 operands[5] = gen_reg_rtx (DFmode); 5290 operands[6] = gen_reg_rtx (SImode); 5291}") 5292 5293(define_insn "*floatsidf2_internal" 5294 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") 5295 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5296 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 5297 (use (match_operand:DF 3 "gpc_reg_operand" "f")) 5298 (clobber (match_operand:DF 4 "memory_operand" "=o")) 5299 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f")) 5300 (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))] 5301 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 5302 "#" 5303 [(set_attr "length" "24")]) 5304 5305(define_split 5306 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5307 (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5308 (use (match_operand:SI 2 "gpc_reg_operand" "")) 5309 (use (match_operand:DF 3 "gpc_reg_operand" "")) 5310 (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) 5311 (clobber (match_operand:DF 5 "gpc_reg_operand" "")) 5312 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] 5313 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 5314 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5315 (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5316 (use (match_operand:SI 2 "gpc_reg_operand" "")) 5317 (use (match_operand:DF 3 "gpc_reg_operand" "")) 5318 (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) 5319 (clobber (match_operand:DF 5 "gpc_reg_operand" "")) 5320 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] 5321 " 5322{ 5323 rtx lowword, highword; 5324 if (GET_CODE (operands[4]) != MEM) 5325 abort(); 5326 highword = XEXP (operands[4], 0); 5327 lowword = plus_constant (highword, 4); 5328 if (! WORDS_BIG_ENDIAN) 5329 { 5330 rtx tmp; 5331 tmp = highword; highword = lowword; lowword = tmp; 5332 } 5333 5334 emit_insn (gen_xorsi3 (operands[6], operands[1], 5335 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); 5336 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); 5337 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); 5338 emit_move_insn (operands[5], operands[4]); 5339 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); 5340 DONE; 5341}") 5342 5343(define_expand "floatunssidf2" 5344 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") 5345 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5346 (use (match_dup 2)) 5347 (use (match_dup 3)) 5348 (clobber (match_dup 4)) 5349 (clobber (match_dup 5))])] 5350 "TARGET_HARD_FLOAT" 5351 " 5352{ 5353 if (TARGET_POWERPC64) 5354 { 5355 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 5356 rtx t1 = gen_reg_rtx (DImode); 5357 rtx t2 = gen_reg_rtx (DImode); 5358 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, 5359 t1, t2)); 5360 DONE; 5361 } 5362 5363 operands[2] = force_reg (SImode, GEN_INT (0x43300000)); 5364 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); 5365 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); 5366 operands[5] = gen_reg_rtx (DFmode); 5367}") 5368 5369(define_insn "*floatunssidf2_internal" 5370 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") 5371 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5372 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 5373 (use (match_operand:DF 3 "gpc_reg_operand" "f")) 5374 (clobber (match_operand:DF 4 "memory_operand" "=o")) 5375 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))] 5376 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 5377 "#" 5378 [(set_attr "length" "20")]) 5379 5380(define_split 5381 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5382 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5383 (use (match_operand:SI 2 "gpc_reg_operand" "")) 5384 (use (match_operand:DF 3 "gpc_reg_operand" "")) 5385 (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) 5386 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] 5387 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" 5388 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5389 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 5390 (use (match_operand:SI 2 "gpc_reg_operand" "")) 5391 (use (match_operand:DF 3 "gpc_reg_operand" "")) 5392 (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) 5393 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] 5394 " 5395{ 5396 rtx lowword, highword; 5397 if (GET_CODE (operands[4]) != MEM) 5398 abort(); 5399 highword = XEXP (operands[4], 0); 5400 lowword = plus_constant (highword, 4); 5401 if (! WORDS_BIG_ENDIAN) 5402 { 5403 rtx tmp; 5404 tmp = highword; highword = lowword; lowword = tmp; 5405 } 5406 5407 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); 5408 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); 5409 emit_move_insn (operands[5], operands[4]); 5410 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); 5411 DONE; 5412}") 5413 5414(define_expand "fix_truncdfsi2" 5415 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 5416 (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) 5417 (clobber (match_dup 2)) 5418 (clobber (match_dup 3))])] 5419 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" 5420 " 5421{ 5422 operands[2] = gen_reg_rtx (DImode); 5423 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 5424}") 5425 5426(define_insn "*fix_truncdfsi2_internal" 5427 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5428 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) 5429 (clobber (match_operand:DI 2 "gpc_reg_operand" "=*f")) 5430 (clobber (match_operand:DI 3 "memory_operand" "=o"))] 5431 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" 5432 "#" 5433 [(set_attr "length" "16")]) 5434 5435(define_split 5436 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5437 (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) 5438 (clobber (match_operand:DI 2 "gpc_reg_operand" "")) 5439 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] 5440 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" 5441 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5442 (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) 5443 (clobber (match_operand:DI 2 "gpc_reg_operand" "")) 5444 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] 5445 " 5446{ 5447 rtx lowword; 5448 if (GET_CODE (operands[3]) != MEM) 5449 abort(); 5450 lowword = XEXP (operands[3], 0); 5451 if (WORDS_BIG_ENDIAN) 5452 lowword = plus_constant (lowword, 4); 5453 5454 emit_insn (gen_fctiwz (operands[2], operands[1])); 5455 emit_move_insn (operands[3], operands[2]); 5456 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); 5457 DONE; 5458}") 5459 5460; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10)) 5461; rather than (set (subreg:SI (reg)) (fix:SI ...)) 5462; because the first makes it clear that operand 0 is not live 5463; before the instruction. 5464(define_insn "fctiwz" 5465 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") 5466 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] 5467 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" 5468 "{fcirz|fctiwz} %0,%1" 5469 [(set_attr "type" "fp")]) 5470 5471(define_insn "floatdidf2" 5472 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5473 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] 5474 "TARGET_POWERPC64 && TARGET_HARD_FLOAT" 5475 "fcfid %0,%1" 5476 [(set_attr "type" "fp")]) 5477 5478(define_insn_and_split "floatsidf_ppc64" 5479 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5480 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5481 (clobber (match_operand:DI 2 "memory_operand" "=o")) 5482 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) 5483 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] 5484 "TARGET_POWERPC64 && TARGET_HARD_FLOAT" 5485 "#" 5486 "" 5487 [(set (match_dup 3) (sign_extend:DI (match_dup 1))) 5488 (set (match_dup 2) (match_dup 3)) 5489 (set (match_dup 4) (match_dup 2)) 5490 (set (match_dup 0) (float:DF (match_dup 4)))] 5491 "") 5492 5493(define_insn_and_split "floatunssidf_ppc64" 5494 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 5495 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5496 (clobber (match_operand:DI 2 "memory_operand" "=o")) 5497 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) 5498 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] 5499 "TARGET_POWERPC64 && TARGET_HARD_FLOAT" 5500 "#" 5501 "" 5502 [(set (match_dup 3) (zero_extend:DI (match_dup 1))) 5503 (set (match_dup 2) (match_dup 3)) 5504 (set (match_dup 4) (match_dup 2)) 5505 (set (match_dup 0) (float:DF (match_dup 4)))] 5506 "") 5507 5508(define_insn "fix_truncdfdi2" 5509 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") 5510 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] 5511 "TARGET_POWERPC64 && TARGET_HARD_FLOAT" 5512 "fctidz %0,%1" 5513 [(set_attr "type" "fp")]) 5514 5515;; Define the DImode operations that can be done in a small number 5516;; of instructions. The & constraints are to prevent the register 5517;; allocator from allocating registers that overlap with the inputs 5518;; (for example, having an input in 7,8 and an output in 6,7). We 5519;; also allow for the output being the same as one of the inputs. 5520 5521(define_insn "*adddi3_noppc64" 5522 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") 5523 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") 5524 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] 5525 "! TARGET_POWERPC64" 5526 "* 5527{ 5528 if (WORDS_BIG_ENDIAN) 5529 return (GET_CODE (operands[2])) != CONST_INT 5530 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" 5531 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; 5532 else 5533 return (GET_CODE (operands[2])) != CONST_INT 5534 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" 5535 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; 5536}" 5537 [(set_attr "length" "8")]) 5538 5539(define_insn "*subdi3_noppc64" 5540 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") 5541 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") 5542 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] 5543 "! TARGET_POWERPC64" 5544 "* 5545{ 5546 if (WORDS_BIG_ENDIAN) 5547 return (GET_CODE (operands[1]) != CONST_INT) 5548 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" 5549 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; 5550 else 5551 return (GET_CODE (operands[1]) != CONST_INT) 5552 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" 5553 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; 5554}" 5555 [(set_attr "length" "8")]) 5556 5557(define_insn "*negdi2_noppc64" 5558 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 5559 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] 5560 "! TARGET_POWERPC64" 5561 "* 5562{ 5563 return (WORDS_BIG_ENDIAN) 5564 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" 5565 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; 5566}" 5567 [(set_attr "length" "8")]) 5568 5569(define_expand "mulsidi3" 5570 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5571 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 5572 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 5573 "! TARGET_POWERPC64" 5574 " 5575{ 5576 if (! TARGET_POWER && ! TARGET_POWERPC) 5577 { 5578 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 5579 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 5580 emit_insn (gen_mull_call ()); 5581 if (WORDS_BIG_ENDIAN) 5582 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); 5583 else 5584 { 5585 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), 5586 gen_rtx_REG (SImode, 3)); 5587 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), 5588 gen_rtx_REG (SImode, 4)); 5589 } 5590 DONE; 5591 } 5592 else if (TARGET_POWER) 5593 { 5594 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); 5595 DONE; 5596 } 5597}") 5598 5599(define_insn "mulsidi3_mq" 5600 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 5601 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 5602 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 5603 (clobber (match_scratch:SI 3 "=q"))] 5604 "TARGET_POWER" 5605 "mul %0,%1,%2\;mfmq %L0" 5606 [(set_attr "type" "imul") 5607 (set_attr "length" "8")]) 5608 5609(define_insn "*mulsidi3_no_mq" 5610 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 5611 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 5612 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 5613 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" 5614 "* 5615{ 5616 return (WORDS_BIG_ENDIAN) 5617 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" 5618 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; 5619}" 5620 [(set_attr "type" "imul") 5621 (set_attr "length" "8")]) 5622 5623(define_split 5624 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5625 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 5626 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 5627 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" 5628 [(set (match_dup 3) 5629 (truncate:SI 5630 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 5631 (sign_extend:DI (match_dup 2))) 5632 (const_int 32)))) 5633 (set (match_dup 4) 5634 (mult:SI (match_dup 1) 5635 (match_dup 2)))] 5636 " 5637{ 5638 int endian = (WORDS_BIG_ENDIAN == 0); 5639 operands[3] = operand_subword (operands[0], endian, 0, DImode); 5640 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); 5641}") 5642 5643(define_expand "umulsidi3" 5644 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5645 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 5646 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 5647 "TARGET_POWERPC && ! TARGET_POWERPC64" 5648 " 5649{ 5650 if (TARGET_POWER) 5651 { 5652 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); 5653 DONE; 5654 } 5655}") 5656 5657(define_insn "umulsidi3_mq" 5658 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 5659 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 5660 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) 5661 (clobber (match_scratch:SI 3 "=q"))] 5662 "TARGET_POWERPC && TARGET_POWER" 5663 "* 5664{ 5665 return (WORDS_BIG_ENDIAN) 5666 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" 5667 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; 5668}" 5669 [(set_attr "type" "imul") 5670 (set_attr "length" "8")]) 5671 5672(define_insn "*umulsidi3_no_mq" 5673 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 5674 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 5675 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 5676 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" 5677 "* 5678{ 5679 return (WORDS_BIG_ENDIAN) 5680 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" 5681 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; 5682}" 5683 [(set_attr "type" "imul") 5684 (set_attr "length" "8")]) 5685 5686(define_split 5687 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5688 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 5689 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 5690 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" 5691 [(set (match_dup 3) 5692 (truncate:SI 5693 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 5694 (zero_extend:DI (match_dup 2))) 5695 (const_int 32)))) 5696 (set (match_dup 4) 5697 (mult:SI (match_dup 1) 5698 (match_dup 2)))] 5699 " 5700{ 5701 int endian = (WORDS_BIG_ENDIAN == 0); 5702 operands[3] = operand_subword (operands[0], endian, 0, DImode); 5703 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); 5704}") 5705 5706(define_expand "smulsi3_highpart" 5707 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5708 (truncate:SI 5709 (lshiftrt:DI (mult:DI (sign_extend:DI 5710 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5711 (sign_extend:DI 5712 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5713 (const_int 32))))] 5714 "" 5715 " 5716{ 5717 if (! TARGET_POWER && ! TARGET_POWERPC) 5718 { 5719 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); 5720 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); 5721 emit_insn (gen_mulh_call ()); 5722 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 5723 DONE; 5724 } 5725 else if (TARGET_POWER) 5726 { 5727 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); 5728 DONE; 5729 } 5730}") 5731 5732(define_insn "smulsi3_highpart_mq" 5733 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5734 (truncate:SI 5735 (lshiftrt:DI (mult:DI (sign_extend:DI 5736 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5737 (sign_extend:DI 5738 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5739 (const_int 32)))) 5740 (clobber (match_scratch:SI 3 "=q"))] 5741 "TARGET_POWER" 5742 "mul %0,%1,%2" 5743 [(set_attr "type" "imul")]) 5744 5745(define_insn "*smulsi3_highpart_no_mq" 5746 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5747 (truncate:SI 5748 (lshiftrt:DI (mult:DI (sign_extend:DI 5749 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5750 (sign_extend:DI 5751 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5752 (const_int 32))))] 5753 "TARGET_POWERPC && ! TARGET_POWER" 5754 "mulhw %0,%1,%2" 5755 [(set_attr "type" "imul")]) 5756 5757(define_expand "umulsi3_highpart" 5758 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5759 (truncate:SI 5760 (lshiftrt:DI (mult:DI (zero_extend:DI 5761 (match_operand:SI 1 "gpc_reg_operand" "")) 5762 (zero_extend:DI 5763 (match_operand:SI 2 "gpc_reg_operand" ""))) 5764 (const_int 32))))] 5765 "TARGET_POWERPC" 5766 " 5767{ 5768 if (TARGET_POWER) 5769 { 5770 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); 5771 DONE; 5772 } 5773}") 5774 5775(define_insn "umulsi3_highpart_mq" 5776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5777 (truncate:SI 5778 (lshiftrt:DI (mult:DI (zero_extend:DI 5779 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5780 (zero_extend:DI 5781 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5782 (const_int 32)))) 5783 (clobber (match_scratch:SI 3 "=q"))] 5784 "TARGET_POWERPC && TARGET_POWER" 5785 "mulhwu %0,%1,%2" 5786 [(set_attr "type" "imul")]) 5787 5788(define_insn "*umulsi3_highpart_no_mq" 5789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 5790 (truncate:SI 5791 (lshiftrt:DI (mult:DI (zero_extend:DI 5792 (match_operand:SI 1 "gpc_reg_operand" "%r")) 5793 (zero_extend:DI 5794 (match_operand:SI 2 "gpc_reg_operand" "r"))) 5795 (const_int 32))))] 5796 "TARGET_POWERPC && ! TARGET_POWER" 5797 "mulhwu %0,%1,%2" 5798 [(set_attr "type" "imul")]) 5799 5800;; If operands 0 and 2 are in the same register, we have a problem. But 5801;; operands 0 and 1 (the usual case) can be in the same register. That's 5802;; why we have the strange constraints below. 5803(define_insn "ashldi3_power" 5804 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") 5805 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 5806 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 5807 (clobber (match_scratch:SI 3 "=X,q,q,q"))] 5808 "TARGET_POWER" 5809 "@ 5810 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} 5811 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 5812 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 5813 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" 5814 [(set_attr "length" "8")]) 5815 5816(define_insn "lshrdi3_power" 5817 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") 5818 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") 5819 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) 5820 (clobber (match_scratch:SI 3 "=X,q,q,q"))] 5821 "TARGET_POWER" 5822 "@ 5823 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} 5824 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 5825 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 5826 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" 5827 [(set_attr "length" "8")]) 5828 5829;; Shift by a variable amount is too complex to be worth open-coding. We 5830;; just handle shifts by constants. 5831(define_insn "ashrdi3_power" 5832 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 5833 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 5834 (match_operand:SI 2 "const_int_operand" "M,i"))) 5835 (clobber (match_scratch:SI 3 "=X,q"))] 5836 "TARGET_POWER" 5837 "@ 5838 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 5839 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" 5840 [(set_attr "length" "8")]) 5841 5842;; PowerPC64 DImode operations. 5843 5844(define_expand "adddi3" 5845 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5846 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5847 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] 5848 "" 5849 " 5850{ 5851 if (! TARGET_POWERPC64) 5852 { 5853 if (non_short_cint_operand (operands[2], DImode)) 5854 FAIL; 5855 } 5856 else 5857 if (GET_CODE (operands[2]) == CONST_INT 5858 && ! add_operand (operands[2], DImode)) 5859 { 5860 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 5861 ? operands[0] : gen_reg_rtx (DImode)); 5862 5863 HOST_WIDE_INT val = INTVAL (operands[2]); 5864 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 5865 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); 5866 5867 if (!CONST_OK_FOR_LETTER_P (rest, 'L')) 5868 FAIL; 5869 5870 /* The ordering here is important for the prolog expander. 5871 When space is allocated from the stack, adding 'low' first may 5872 produce a temporary deallocation (which would be bad). */ 5873 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); 5874 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); 5875 DONE; 5876 } 5877}") 5878 5879;; Discourage ai/addic because of carry but provide it in an alternative 5880;; allowing register zero as source. 5881 5882(define_insn "*adddi3_internal1" 5883 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") 5884 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") 5885 (match_operand:DI 2 "add_operand" "r,I,I,L")))] 5886 "TARGET_POWERPC64" 5887 "@ 5888 add %0,%1,%2 5889 addi %0,%1,%2 5890 addic %0,%1,%2 5891 addis %0,%1,%v2") 5892 5893(define_insn "*adddi3_internal2" 5894 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 5895 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") 5896 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) 5897 (const_int 0))) 5898 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 5899 "TARGET_POWERPC64" 5900 "@ 5901 add. %3,%1,%2 5902 addic. %3,%1,%2 5903 # 5904 #" 5905 [(set_attr "type" "compare") 5906 (set_attr "length" "4,4,8,8")]) 5907 5908(define_split 5909 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 5910 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5911 (match_operand:DI 2 "reg_or_short_operand" "")) 5912 (const_int 0))) 5913 (clobber (match_scratch:DI 3 ""))] 5914 "TARGET_POWERPC64 && reload_completed" 5915 [(set (match_dup 3) 5916 (plus:DI (match_dup 1) (match_dup 2))) 5917 (set (match_dup 0) 5918 (compare:CC (match_dup 3) 5919 (const_int 0)))] 5920 "") 5921 5922(define_insn "*adddi3_internal3" 5923 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 5924 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") 5925 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) 5926 (const_int 0))) 5927 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 5928 (plus:DI (match_dup 1) (match_dup 2)))] 5929 "TARGET_POWERPC64" 5930 "@ 5931 add. %0,%1,%2 5932 addic. %0,%1,%2 5933 # 5934 #" 5935 [(set_attr "type" "compare") 5936 (set_attr "length" "4,4,8,8")]) 5937 5938(define_split 5939 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 5940 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5941 (match_operand:DI 2 "reg_or_short_operand" "")) 5942 (const_int 0))) 5943 (set (match_operand:DI 0 "gpc_reg_operand" "") 5944 (plus:DI (match_dup 1) (match_dup 2)))] 5945 "TARGET_POWERPC64 && reload_completed" 5946 [(set (match_dup 0) 5947 (plus:DI (match_dup 1) (match_dup 2))) 5948 (set (match_dup 3) 5949 (compare:CC (match_dup 0) 5950 (const_int 0)))] 5951 "") 5952 5953;; Split an add that we can't do in one insn into two insns, each of which 5954;; does one 16-bit part. This is used by combine. Note that the low-order 5955;; add should be last in case the result gets used in an address. 5956 5957(define_split 5958 [(set (match_operand:DI 0 "gpc_reg_operand" "") 5959 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") 5960 (match_operand:DI 2 "non_add_cint_operand" "")))] 5961 "TARGET_POWERPC64" 5962 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 5963 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 5964" 5965{ 5966 HOST_WIDE_INT val = INTVAL (operands[2]); 5967 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 5968 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); 5969 5970 operands[4] = GEN_INT (low); 5971 if (CONST_OK_FOR_LETTER_P (rest, 'L')) 5972 operands[3] = GEN_INT (rest); 5973 else if (! no_new_pseudos) 5974 { 5975 operands[3] = gen_reg_rtx (DImode); 5976 emit_move_insn (operands[3], operands[2]); 5977 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 5978 DONE; 5979 } 5980 else 5981 FAIL; 5982}") 5983 5984(define_insn "one_cmpldi2" 5985 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 5986 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 5987 "TARGET_POWERPC64" 5988 "nor %0,%1,%1") 5989 5990(define_insn "" 5991 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 5992 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 5993 (const_int 0))) 5994 (clobber (match_scratch:DI 2 "=r,r"))] 5995 "TARGET_POWERPC64" 5996 "@ 5997 nor. %2,%1,%1 5998 #" 5999 [(set_attr "type" "compare") 6000 (set_attr "length" "4,8")]) 6001 6002(define_split 6003 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6004 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 6005 (const_int 0))) 6006 (clobber (match_scratch:DI 2 ""))] 6007 "TARGET_POWERPC64 && reload_completed" 6008 [(set (match_dup 2) 6009 (not:DI (match_dup 1))) 6010 (set (match_dup 0) 6011 (compare:CC (match_dup 2) 6012 (const_int 0)))] 6013 "") 6014 6015(define_insn "" 6016 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 6017 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 6018 (const_int 0))) 6019 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6020 (not:DI (match_dup 1)))] 6021 "TARGET_POWERPC64" 6022 "@ 6023 nor. %0,%1,%1 6024 #" 6025 [(set_attr "type" "compare") 6026 (set_attr "length" "4,8")]) 6027 6028(define_split 6029 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 6030 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 6031 (const_int 0))) 6032 (set (match_operand:DI 0 "gpc_reg_operand" "") 6033 (not:DI (match_dup 1)))] 6034 "TARGET_POWERPC64 && reload_completed" 6035 [(set (match_dup 0) 6036 (not:DI (match_dup 1))) 6037 (set (match_dup 2) 6038 (compare:CC (match_dup 0) 6039 (const_int 0)))] 6040 "") 6041 6042(define_insn "" 6043 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6044 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") 6045 (match_operand:DI 2 "gpc_reg_operand" "r,r")))] 6046 "TARGET_POWERPC64" 6047 "@ 6048 subf %0,%2,%1 6049 subfic %0,%2,%1") 6050 6051(define_insn "" 6052 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6053 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6054 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 6055 (const_int 0))) 6056 (clobber (match_scratch:DI 3 "=r,r"))] 6057 "TARGET_POWERPC64" 6058 "@ 6059 subf. %3,%2,%1 6060 #" 6061 [(set_attr "type" "compare") 6062 (set_attr "length" "4,8")]) 6063 6064(define_split 6065 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6066 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") 6067 (match_operand:DI 2 "gpc_reg_operand" "")) 6068 (const_int 0))) 6069 (clobber (match_scratch:DI 3 ""))] 6070 "TARGET_POWERPC64 && reload_completed" 6071 [(set (match_dup 3) 6072 (minus:DI (match_dup 1) (match_dup 2))) 6073 (set (match_dup 0) 6074 (compare:CC (match_dup 3) 6075 (const_int 0)))] 6076 "") 6077 6078(define_insn "" 6079 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6080 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6081 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 6082 (const_int 0))) 6083 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6084 (minus:DI (match_dup 1) (match_dup 2)))] 6085 "TARGET_POWERPC64" 6086 "@ 6087 subf. %0,%2,%1 6088 #" 6089 [(set_attr "type" "compare") 6090 (set_attr "length" "4,8")]) 6091 6092(define_split 6093 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6094 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") 6095 (match_operand:DI 2 "gpc_reg_operand" "")) 6096 (const_int 0))) 6097 (set (match_operand:DI 0 "gpc_reg_operand" "") 6098 (minus:DI (match_dup 1) (match_dup 2)))] 6099 "TARGET_POWERPC64 && reload_completed" 6100 [(set (match_dup 0) 6101 (minus:DI (match_dup 1) (match_dup 2))) 6102 (set (match_dup 3) 6103 (compare:CC (match_dup 0) 6104 (const_int 0)))] 6105 "") 6106 6107(define_expand "subdi3" 6108 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6109 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") 6110 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] 6111 "" 6112 " 6113{ 6114 if (GET_CODE (operands[2]) == CONST_INT) 6115 { 6116 emit_insn (gen_adddi3 (operands[0], operands[1], 6117 negate_rtx (DImode, operands[2]))); 6118 DONE; 6119 } 6120}") 6121 6122(define_insn "absdi2" 6123 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 6124 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) 6125 (clobber (match_scratch:DI 2 "=&r,&r"))] 6126 "TARGET_POWERPC64" 6127 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" 6128 [(set_attr "length" "12")]) 6129 6130(define_split 6131 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6132 (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 6133 (clobber (match_scratch:DI 2 ""))] 6134 "TARGET_POWERPC64 && reload_completed" 6135 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) 6136 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) 6137 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] 6138 "") 6139 6140(define_insn "*nabsdi2" 6141 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 6142 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) 6143 (clobber (match_scratch:DI 2 "=&r,&r"))] 6144 "TARGET_POWERPC64" 6145 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" 6146 [(set_attr "length" "12")]) 6147 6148(define_split 6149 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6150 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))) 6151 (clobber (match_scratch:DI 2 ""))] 6152 "TARGET_POWERPC64 && reload_completed" 6153 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) 6154 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) 6155 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] 6156 "") 6157 6158(define_expand "negdi2" 6159 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6160 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] 6161 "" 6162 "") 6163 6164(define_insn "" 6165 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6166 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 6167 "TARGET_POWERPC64" 6168 "neg %0,%1") 6169 6170(define_insn "" 6171 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6172 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 6173 (const_int 0))) 6174 (clobber (match_scratch:DI 2 "=r,r"))] 6175 "TARGET_POWERPC64" 6176 "@ 6177 neg. %2,%1 6178 #" 6179 [(set_attr "type" "compare") 6180 (set_attr "length" "4,8")]) 6181 6182(define_split 6183 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6184 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) 6185 (const_int 0))) 6186 (clobber (match_scratch:DI 2 ""))] 6187 "TARGET_POWERPC64 && reload_completed" 6188 [(set (match_dup 2) 6189 (neg:DI (match_dup 1))) 6190 (set (match_dup 0) 6191 (compare:CC (match_dup 2) 6192 (const_int 0)))] 6193 "") 6194 6195(define_insn "" 6196 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 6197 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 6198 (const_int 0))) 6199 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6200 (neg:DI (match_dup 1)))] 6201 "TARGET_POWERPC64" 6202 "@ 6203 neg. %0,%1 6204 #" 6205 [(set_attr "type" "compare") 6206 (set_attr "length" "4,8")]) 6207 6208(define_split 6209 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 6210 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) 6211 (const_int 0))) 6212 (set (match_operand:DI 0 "gpc_reg_operand" "") 6213 (neg:DI (match_dup 1)))] 6214 "TARGET_POWERPC64 && reload_completed" 6215 [(set (match_dup 0) 6216 (neg:DI (match_dup 1))) 6217 (set (match_dup 2) 6218 (compare:CC (match_dup 0) 6219 (const_int 0)))] 6220 "") 6221 6222(define_insn "ffsdi2" 6223 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 6224 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] 6225 "TARGET_POWERPC64" 6226 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" 6227 [(set_attr "length" "16")]) 6228 6229(define_insn "muldi3" 6230 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6231 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") 6232 (match_operand:DI 2 "gpc_reg_operand" "r")))] 6233 "TARGET_POWERPC64" 6234 "mulld %0,%1,%2" 6235 [(set_attr "type" "lmul")]) 6236 6237(define_insn "smuldi3_highpart" 6238 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6239 (truncate:DI 6240 (lshiftrt:TI (mult:TI (sign_extend:TI 6241 (match_operand:DI 1 "gpc_reg_operand" "%r")) 6242 (sign_extend:TI 6243 (match_operand:DI 2 "gpc_reg_operand" "r"))) 6244 (const_int 64))))] 6245 "TARGET_POWERPC64" 6246 "mulhd %0,%1,%2" 6247 [(set_attr "type" "lmul")]) 6248 6249(define_insn "umuldi3_highpart" 6250 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6251 (truncate:DI 6252 (lshiftrt:TI (mult:TI (zero_extend:TI 6253 (match_operand:DI 1 "gpc_reg_operand" "%r")) 6254 (zero_extend:TI 6255 (match_operand:DI 2 "gpc_reg_operand" "r"))) 6256 (const_int 64))))] 6257 "TARGET_POWERPC64" 6258 "mulhdu %0,%1,%2" 6259 [(set_attr "type" "lmul")]) 6260 6261(define_expand "divdi3" 6262 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6263 (div:DI (match_operand:DI 1 "gpc_reg_operand" "") 6264 (match_operand:DI 2 "reg_or_cint_operand" "")))] 6265 "TARGET_POWERPC64" 6266 " 6267{ 6268 if (GET_CODE (operands[2]) == CONST_INT 6269 && INTVAL (operands[2]) > 0 6270 && exact_log2 (INTVAL (operands[2])) >= 0) 6271 ; 6272 else 6273 operands[2] = force_reg (DImode, operands[2]); 6274}") 6275 6276(define_expand "moddi3" 6277 [(use (match_operand:DI 0 "gpc_reg_operand" "")) 6278 (use (match_operand:DI 1 "gpc_reg_operand" "")) 6279 (use (match_operand:DI 2 "reg_or_cint_operand" ""))] 6280 "TARGET_POWERPC64" 6281 " 6282{ 6283 int i; 6284 rtx temp1; 6285 rtx temp2; 6286 6287 if (GET_CODE (operands[2]) != CONST_INT 6288 || INTVAL (operands[2]) <= 0 6289 || (i = exact_log2 (INTVAL (operands[2]))) < 0) 6290 FAIL; 6291 6292 temp1 = gen_reg_rtx (DImode); 6293 temp2 = gen_reg_rtx (DImode); 6294 6295 emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); 6296 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); 6297 emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); 6298 DONE; 6299}") 6300 6301(define_insn "" 6302 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6303 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6304 (match_operand:DI 2 "exact_log2_cint_operand" "N")))] 6305 "TARGET_POWERPC64" 6306 "sradi %0,%1,%p2\;addze %0,%0" 6307 [(set_attr "length" "8")]) 6308 6309(define_insn "" 6310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6311 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6312 (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) 6313 (const_int 0))) 6314 (clobber (match_scratch:DI 3 "=r,r"))] 6315 "TARGET_POWERPC64" 6316 "@ 6317 sradi %3,%1,%p2\;addze. %3,%3 6318 #" 6319 [(set_attr "type" "compare") 6320 (set_attr "length" "8,12")]) 6321 6322(define_split 6323 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6324 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") 6325 (match_operand:DI 2 "exact_log2_cint_operand" "")) 6326 (const_int 0))) 6327 (clobber (match_scratch:DI 3 ""))] 6328 "TARGET_POWERPC64 && reload_completed" 6329 [(set (match_dup 3) 6330 (div:DI (match_dup 1) (match_dup 2))) 6331 (set (match_dup 0) 6332 (compare:CC (match_dup 3) 6333 (const_int 0)))] 6334 "") 6335 6336(define_insn "" 6337 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6338 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6339 (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) 6340 (const_int 0))) 6341 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6342 (div:DI (match_dup 1) (match_dup 2)))] 6343 "TARGET_POWERPC64" 6344 "@ 6345 sradi %0,%1,%p2\;addze. %0,%0 6346 #" 6347 [(set_attr "type" "compare") 6348 (set_attr "length" "8,12")]) 6349 6350(define_split 6351 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6352 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") 6353 (match_operand:DI 2 "exact_log2_cint_operand" "")) 6354 (const_int 0))) 6355 (set (match_operand:DI 0 "gpc_reg_operand" "") 6356 (div:DI (match_dup 1) (match_dup 2)))] 6357 "TARGET_POWERPC64 && reload_completed" 6358 [(set (match_dup 0) 6359 (div:DI (match_dup 1) (match_dup 2))) 6360 (set (match_dup 3) 6361 (compare:CC (match_dup 0) 6362 (const_int 0)))] 6363 "") 6364 6365(define_insn "" 6366 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6367 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6368 (match_operand:DI 2 "gpc_reg_operand" "r")))] 6369 "TARGET_POWERPC64" 6370 "divd %0,%1,%2" 6371 [(set_attr "type" "ldiv")]) 6372 6373(define_insn "udivdi3" 6374 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6375 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6376 (match_operand:DI 2 "gpc_reg_operand" "r")))] 6377 "TARGET_POWERPC64" 6378 "divdu %0,%1,%2" 6379 [(set_attr "type" "ldiv")]) 6380 6381(define_insn "rotldi3" 6382 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6383 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6384 (match_operand:DI 2 "reg_or_cint_operand" "ri")))] 6385 "TARGET_POWERPC64" 6386 "rld%I2cl %0,%1,%H2,0") 6387 6388(define_insn "*rotldi3_internal2" 6389 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6390 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6391 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6392 (const_int 0))) 6393 (clobber (match_scratch:DI 3 "=r,r"))] 6394 "TARGET_POWERPC64" 6395 "@ 6396 rld%I2cl. %3,%1,%H2,0 6397 #" 6398 [(set_attr "type" "delayed_compare") 6399 (set_attr "length" "4,8")]) 6400 6401(define_split 6402 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6403 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6404 (match_operand:DI 2 "reg_or_cint_operand" "")) 6405 (const_int 0))) 6406 (clobber (match_scratch:DI 3 ""))] 6407 "TARGET_POWERPC64 && reload_completed" 6408 [(set (match_dup 3) 6409 (rotate:DI (match_dup 1) (match_dup 2))) 6410 (set (match_dup 0) 6411 (compare:CC (match_dup 3) 6412 (const_int 0)))] 6413 "") 6414 6415(define_insn "*rotldi3_internal3" 6416 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6417 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6418 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6419 (const_int 0))) 6420 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6421 (rotate:DI (match_dup 1) (match_dup 2)))] 6422 "TARGET_POWERPC64" 6423 "@ 6424 rld%I2cl. %0,%1,%H2,0 6425 #" 6426 [(set_attr "type" "delayed_compare") 6427 (set_attr "length" "4,8")]) 6428 6429(define_split 6430 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6431 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6432 (match_operand:DI 2 "reg_or_cint_operand" "")) 6433 (const_int 0))) 6434 (set (match_operand:DI 0 "gpc_reg_operand" "") 6435 (rotate:DI (match_dup 1) (match_dup 2)))] 6436 "TARGET_POWERPC64 && reload_completed" 6437 [(set (match_dup 0) 6438 (rotate:DI (match_dup 1) (match_dup 2))) 6439 (set (match_dup 3) 6440 (compare:CC (match_dup 0) 6441 (const_int 0)))] 6442 "") 6443 6444(define_insn "*rotldi3_internal4" 6445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6446 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6447 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 6448 (match_operand:DI 3 "mask64_operand" "S")))] 6449 "TARGET_POWERPC64" 6450 "rld%I2c%B3 %0,%1,%H2,%S3") 6451 6452(define_insn "*rotldi3_internal5" 6453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6454 (compare:CC (and:DI 6455 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6456 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6457 (match_operand:DI 3 "mask64_operand" "S,S")) 6458 (const_int 0))) 6459 (clobber (match_scratch:DI 4 "=r,r"))] 6460 "TARGET_POWERPC64" 6461 "@ 6462 rld%I2c%B3. %4,%1,%H2,%S3 6463 #" 6464 [(set_attr "type" "delayed_compare") 6465 (set_attr "length" "4,8")]) 6466 6467(define_split 6468 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6469 (compare:CC (and:DI 6470 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6471 (match_operand:DI 2 "reg_or_cint_operand" "")) 6472 (match_operand:DI 3 "mask64_operand" "")) 6473 (const_int 0))) 6474 (clobber (match_scratch:DI 4 ""))] 6475 "TARGET_POWERPC64 && reload_completed" 6476 [(set (match_dup 4) 6477 (and:DI (rotate:DI (match_dup 1) 6478 (match_dup 2)) 6479 (match_dup 3))) 6480 (set (match_dup 0) 6481 (compare:CC (match_dup 4) 6482 (const_int 0)))] 6483 "") 6484 6485(define_insn "*rotldi3_internal6" 6486 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 6487 (compare:CC (and:DI 6488 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6489 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 6490 (match_operand:DI 3 "mask64_operand" "S,S")) 6491 (const_int 0))) 6492 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6493 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6494 "TARGET_POWERPC64" 6495 "@ 6496 rld%I2c%B3. %0,%1,%H2,%S3 6497 #" 6498 [(set_attr "type" "delayed_compare") 6499 (set_attr "length" "4,8")]) 6500 6501(define_split 6502 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 6503 (compare:CC (and:DI 6504 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6505 (match_operand:DI 2 "reg_or_cint_operand" "")) 6506 (match_operand:DI 3 "mask64_operand" "")) 6507 (const_int 0))) 6508 (set (match_operand:DI 0 "gpc_reg_operand" "") 6509 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6510 "TARGET_POWERPC64 && reload_completed" 6511 [(set (match_dup 0) 6512 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) 6513 (set (match_dup 4) 6514 (compare:CC (match_dup 0) 6515 (const_int 0)))] 6516 "") 6517 6518(define_insn "*rotldi3_internal7" 6519 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6520 (zero_extend:DI 6521 (subreg:QI 6522 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6523 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] 6524 "TARGET_POWERPC64" 6525 "rld%I2cl %0,%1,%H2,56") 6526 6527(define_insn "*rotldi3_internal8" 6528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6529 (compare:CC (zero_extend:DI 6530 (subreg:QI 6531 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6532 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6533 (const_int 0))) 6534 (clobber (match_scratch:DI 3 "=r,r"))] 6535 "TARGET_POWERPC64" 6536 "@ 6537 rld%I2cl. %3,%1,%H2,56 6538 #" 6539 [(set_attr "type" "delayed_compare") 6540 (set_attr "length" "4,8")]) 6541 6542(define_split 6543 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6544 (compare:CC (zero_extend:DI 6545 (subreg:QI 6546 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6547 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6548 (const_int 0))) 6549 (clobber (match_scratch:DI 3 ""))] 6550 "TARGET_POWERPC64 && reload_completed" 6551 [(set (match_dup 3) 6552 (zero_extend:DI (subreg:QI 6553 (rotate:DI (match_dup 1) 6554 (match_dup 2)) 0))) 6555 (set (match_dup 0) 6556 (compare:CC (match_dup 3) 6557 (const_int 0)))] 6558 "") 6559 6560(define_insn "*rotldi3_internal9" 6561 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6562 (compare:CC (zero_extend:DI 6563 (subreg:QI 6564 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6565 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6566 (const_int 0))) 6567 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6568 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6569 "TARGET_POWERPC64" 6570 "@ 6571 rld%I2cl. %0,%1,%H2,56 6572 #" 6573 [(set_attr "type" "delayed_compare") 6574 (set_attr "length" "4,8")]) 6575 6576(define_split 6577 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6578 (compare:CC (zero_extend:DI 6579 (subreg:QI 6580 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6581 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6582 (const_int 0))) 6583 (set (match_operand:DI 0 "gpc_reg_operand" "") 6584 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6585 "TARGET_POWERPC64 && reload_completed" 6586 [(set (match_dup 0) 6587 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 6588 (set (match_dup 3) 6589 (compare:CC (match_dup 0) 6590 (const_int 0)))] 6591 "") 6592 6593(define_insn "*rotldi3_internal10" 6594 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6595 (zero_extend:DI 6596 (subreg:HI 6597 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6598 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] 6599 "TARGET_POWERPC64" 6600 "rld%I2cl %0,%1,%H2,48") 6601 6602(define_insn "*rotldi3_internal11" 6603 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6604 (compare:CC (zero_extend:DI 6605 (subreg:HI 6606 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6607 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6608 (const_int 0))) 6609 (clobber (match_scratch:DI 3 "=r,r"))] 6610 "TARGET_POWERPC64" 6611 "@ 6612 rld%I2cl. %3,%1,%H2,48 6613 #" 6614 [(set_attr "type" "delayed_compare") 6615 (set_attr "length" "4,8")]) 6616 6617(define_split 6618 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6619 (compare:CC (zero_extend:DI 6620 (subreg:HI 6621 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6622 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6623 (const_int 0))) 6624 (clobber (match_scratch:DI 3 ""))] 6625 "TARGET_POWERPC64 && reload_completed" 6626 [(set (match_dup 3) 6627 (zero_extend:DI (subreg:HI 6628 (rotate:DI (match_dup 1) 6629 (match_dup 2)) 0))) 6630 (set (match_dup 0) 6631 (compare:CC (match_dup 3) 6632 (const_int 0)))] 6633 "") 6634 6635(define_insn "*rotldi3_internal12" 6636 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6637 (compare:CC (zero_extend:DI 6638 (subreg:HI 6639 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6640 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6641 (const_int 0))) 6642 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6643 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6644 "TARGET_POWERPC64" 6645 "@ 6646 rld%I2cl. %0,%1,%H2,48 6647 #" 6648 [(set_attr "type" "delayed_compare") 6649 (set_attr "length" "4,8")]) 6650 6651(define_split 6652 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6653 (compare:CC (zero_extend:DI 6654 (subreg:HI 6655 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6656 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6657 (const_int 0))) 6658 (set (match_operand:DI 0 "gpc_reg_operand" "") 6659 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6660 "TARGET_POWERPC64 && reload_completed" 6661 [(set (match_dup 0) 6662 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 6663 (set (match_dup 3) 6664 (compare:CC (match_dup 0) 6665 (const_int 0)))] 6666 "") 6667 6668(define_insn "*rotldi3_internal13" 6669 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6670 (zero_extend:DI 6671 (subreg:SI 6672 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6673 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] 6674 "TARGET_POWERPC64" 6675 "rld%I2cl %0,%1,%H2,32") 6676 6677(define_insn "*rotldi3_internal14" 6678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6679 (compare:CC (zero_extend:DI 6680 (subreg:SI 6681 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6682 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6683 (const_int 0))) 6684 (clobber (match_scratch:DI 3 "=r,r"))] 6685 "TARGET_POWERPC64" 6686 "@ 6687 rld%I2cl. %3,%1,%H2,32 6688 #" 6689 [(set_attr "type" "delayed_compare") 6690 (set_attr "length" "4,8")]) 6691 6692(define_split 6693 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6694 (compare:CC (zero_extend:DI 6695 (subreg:SI 6696 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6697 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6698 (const_int 0))) 6699 (clobber (match_scratch:DI 3 ""))] 6700 "TARGET_POWERPC64 && reload_completed" 6701 [(set (match_dup 3) 6702 (zero_extend:DI (subreg:SI 6703 (rotate:DI (match_dup 1) 6704 (match_dup 2)) 0))) 6705 (set (match_dup 0) 6706 (compare:CC (match_dup 3) 6707 (const_int 0)))] 6708 "") 6709 6710(define_insn "*rotldi3_internal15" 6711 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6712 (compare:CC (zero_extend:DI 6713 (subreg:SI 6714 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6715 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) 6716 (const_int 0))) 6717 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6718 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6719 "TARGET_POWERPC64" 6720 "@ 6721 rld%I2cl. %0,%1,%H2,32 6722 #" 6723 [(set_attr "type" "delayed_compare") 6724 (set_attr "length" "4,8")]) 6725 6726(define_split 6727 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6728 (compare:CC (zero_extend:DI 6729 (subreg:SI 6730 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6731 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 6732 (const_int 0))) 6733 (set (match_operand:DI 0 "gpc_reg_operand" "") 6734 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 6735 "TARGET_POWERPC64 && reload_completed" 6736 [(set (match_dup 0) 6737 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 6738 (set (match_dup 3) 6739 (compare:CC (match_dup 0) 6740 (const_int 0)))] 6741 "") 6742 6743(define_expand "ashldi3" 6744 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6745 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6746 (match_operand:SI 2 "reg_or_cint_operand" "")))] 6747 "TARGET_POWERPC64 || TARGET_POWER" 6748 " 6749{ 6750 if (TARGET_POWERPC64) 6751 ; 6752 else if (TARGET_POWER) 6753 { 6754 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); 6755 DONE; 6756 } 6757 else 6758 FAIL; 6759}") 6760 6761(define_insn "*ashldi3_internal1" 6762 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6763 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6764 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 6765 "TARGET_POWERPC64" 6766 "sld%I2 %0,%1,%H2" 6767 [(set_attr "length" "8")]) 6768 6769(define_insn "*ashldi3_internal2" 6770 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6771 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6772 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6773 (const_int 0))) 6774 (clobber (match_scratch:DI 3 "=r,r"))] 6775 "TARGET_POWERPC64" 6776 "@ 6777 sld%I2. %3,%1,%H2 6778 #" 6779 [(set_attr "type" "delayed_compare") 6780 (set_attr "length" "4,8")]) 6781 6782(define_split 6783 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6784 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6785 (match_operand:SI 2 "reg_or_cint_operand" "")) 6786 (const_int 0))) 6787 (clobber (match_scratch:DI 3 ""))] 6788 "TARGET_POWERPC64 && reload_completed" 6789 [(set (match_dup 3) 6790 (ashift:DI (match_dup 1) (match_dup 2))) 6791 (set (match_dup 0) 6792 (compare:CC (match_dup 3) 6793 (const_int 0)))] 6794 "") 6795 6796(define_insn "*ashldi3_internal3" 6797 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6798 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6799 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 6800 (const_int 0))) 6801 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6802 (ashift:DI (match_dup 1) (match_dup 2)))] 6803 "TARGET_POWERPC64" 6804 "@ 6805 sld%I2. %0,%1,%H2 6806 #" 6807 [(set_attr "type" "delayed_compare") 6808 (set_attr "length" "4,8")]) 6809 6810(define_split 6811 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 6812 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6813 (match_operand:SI 2 "reg_or_cint_operand" "")) 6814 (const_int 0))) 6815 (set (match_operand:DI 0 "gpc_reg_operand" "") 6816 (ashift:DI (match_dup 1) (match_dup 2)))] 6817 "TARGET_POWERPC64 && reload_completed" 6818 [(set (match_dup 0) 6819 (ashift:DI (match_dup 1) (match_dup 2))) 6820 (set (match_dup 3) 6821 (compare:CC (match_dup 0) 6822 (const_int 0)))] 6823 "") 6824 6825(define_insn "*ashldi3_internal4" 6826 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6827 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6828 (match_operand:SI 2 "const_int_operand" "i")) 6829 (match_operand:DI 3 "const_int_operand" "n")))] 6830 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" 6831 "rldic %0,%1,%H2,%W3") 6832 6833(define_insn "ashldi3_internal5" 6834 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6835 (compare:CC 6836 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6837 (match_operand:SI 2 "const_int_operand" "i,i")) 6838 (match_operand:DI 3 "const_int_operand" "n,n")) 6839 (const_int 0))) 6840 (clobber (match_scratch:DI 4 "=r,r"))] 6841 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" 6842 "@ 6843 rldic. %4,%1,%H2,%W3 6844 #" 6845 [(set_attr "type" "delayed_compare") 6846 (set_attr "length" "4,8")]) 6847 6848(define_split 6849 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6850 (compare:CC 6851 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6852 (match_operand:SI 2 "const_int_operand" "")) 6853 (match_operand:DI 3 "const_int_operand" "")) 6854 (const_int 0))) 6855 (clobber (match_scratch:DI 4 ""))] 6856 "TARGET_POWERPC64 && reload_completed 6857 && includes_rldic_lshift_p (operands[2], operands[3])" 6858 [(set (match_dup 4) 6859 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 6860 (match_dup 3))) 6861 (set (match_dup 0) 6862 (compare:CC (match_dup 4) 6863 (const_int 0)))] 6864 "") 6865 6866(define_insn "*ashldi3_internal6" 6867 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 6868 (compare:CC 6869 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6870 (match_operand:SI 2 "const_int_operand" "i,i")) 6871 (match_operand:DI 3 "const_int_operand" "n,n")) 6872 (const_int 0))) 6873 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6874 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6875 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" 6876 "@ 6877 rldic. %0,%1,%H2,%W3 6878 #" 6879 [(set_attr "type" "delayed_compare") 6880 (set_attr "length" "4,8")]) 6881 6882(define_split 6883 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 6884 (compare:CC 6885 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6886 (match_operand:SI 2 "const_int_operand" "")) 6887 (match_operand:DI 3 "const_int_operand" "")) 6888 (const_int 0))) 6889 (set (match_operand:DI 0 "gpc_reg_operand" "") 6890 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6891 "TARGET_POWERPC64 && reload_completed 6892 && includes_rldic_lshift_p (operands[2], operands[3])" 6893 [(set (match_dup 0) 6894 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 6895 (match_dup 3))) 6896 (set (match_dup 4) 6897 (compare:CC (match_dup 0) 6898 (const_int 0)))] 6899 "") 6900 6901(define_insn "*ashldi3_internal7" 6902 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6903 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6904 (match_operand:SI 2 "const_int_operand" "i")) 6905 (match_operand:DI 3 "mask64_operand" "S")))] 6906 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" 6907 "rldicr %0,%1,%H2,%S3") 6908 6909(define_insn "ashldi3_internal8" 6910 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6911 (compare:CC 6912 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6913 (match_operand:SI 2 "const_int_operand" "i,i")) 6914 (match_operand:DI 3 "mask64_operand" "S,S")) 6915 (const_int 0))) 6916 (clobber (match_scratch:DI 4 "=r,r"))] 6917 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" 6918 "@ 6919 rldicr. %4,%1,%H2,%S3 6920 #" 6921 [(set_attr "type" "delayed_compare") 6922 (set_attr "length" "4,8")]) 6923 6924(define_split 6925 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6926 (compare:CC 6927 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6928 (match_operand:SI 2 "const_int_operand" "")) 6929 (match_operand:DI 3 "mask64_operand" "")) 6930 (const_int 0))) 6931 (clobber (match_scratch:DI 4 ""))] 6932 "TARGET_POWERPC64 && reload_completed 6933 && includes_rldicr_lshift_p (operands[2], operands[3])" 6934 [(set (match_dup 4) 6935 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 6936 (match_dup 3))) 6937 (set (match_dup 0) 6938 (compare:CC (match_dup 4) 6939 (const_int 0)))] 6940 "") 6941 6942(define_insn "*ashldi3_internal9" 6943 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 6944 (compare:CC 6945 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6946 (match_operand:SI 2 "const_int_operand" "i,i")) 6947 (match_operand:DI 3 "mask64_operand" "S,S")) 6948 (const_int 0))) 6949 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6950 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6951 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" 6952 "@ 6953 rldicr. %0,%1,%H2,%S3 6954 #" 6955 [(set_attr "type" "delayed_compare") 6956 (set_attr "length" "4,8")]) 6957 6958(define_split 6959 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 6960 (compare:CC 6961 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 6962 (match_operand:SI 2 "const_int_operand" "")) 6963 (match_operand:DI 3 "mask64_operand" "")) 6964 (const_int 0))) 6965 (set (match_operand:DI 0 "gpc_reg_operand" "") 6966 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 6967 "TARGET_POWERPC64 && reload_completed 6968 && includes_rldicr_lshift_p (operands[2], operands[3])" 6969 [(set (match_dup 0) 6970 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 6971 (match_dup 3))) 6972 (set (match_dup 4) 6973 (compare:CC (match_dup 0) 6974 (const_int 0)))] 6975 "") 6976 6977(define_expand "lshrdi3" 6978 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6979 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 6980 (match_operand:SI 2 "reg_or_cint_operand" "")))] 6981 "TARGET_POWERPC64 || TARGET_POWER" 6982 " 6983{ 6984 if (TARGET_POWERPC64) 6985 ; 6986 else if (TARGET_POWER) 6987 { 6988 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); 6989 DONE; 6990 } 6991 else 6992 FAIL; 6993}") 6994 6995(define_insn "*lshrdi3_internal1" 6996 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6997 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6998 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 6999 "TARGET_POWERPC64" 7000 "srd%I2 %0,%1,%H2") 7001 7002(define_insn "*lshrdi3_internal2" 7003 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7004 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7005 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 7006 (const_int 0))) 7007 (clobber (match_scratch:DI 3 "=r,r"))] 7008 "TARGET_POWERPC64" 7009 "@ 7010 srd%I2. %3,%1,%H2 7011 #" 7012 [(set_attr "type" "delayed_compare") 7013 (set_attr "length" "4,8")]) 7014 7015(define_split 7016 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7017 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7018 (match_operand:SI 2 "reg_or_cint_operand" "")) 7019 (const_int 0))) 7020 (clobber (match_scratch:DI 3 ""))] 7021 "TARGET_POWERPC64 && reload_completed" 7022 [(set (match_dup 3) 7023 (lshiftrt:DI (match_dup 1) (match_dup 2))) 7024 (set (match_dup 0) 7025 (compare:CC (match_dup 3) 7026 (const_int 0)))] 7027 "") 7028 7029(define_insn "*lshrdi3_internal3" 7030 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7031 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7032 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 7033 (const_int 0))) 7034 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7035 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 7036 "TARGET_POWERPC64" 7037 "@ 7038 srd%I2. %0,%1,%H2 7039 #" 7040 [(set_attr "type" "delayed_compare") 7041 (set_attr "length" "4,8")]) 7042 7043(define_split 7044 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7045 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7046 (match_operand:SI 2 "reg_or_cint_operand" "")) 7047 (const_int 0))) 7048 (set (match_operand:DI 0 "gpc_reg_operand" "") 7049 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 7050 "TARGET_POWERPC64 && reload_completed" 7051 [(set (match_dup 0) 7052 (lshiftrt:DI (match_dup 1) (match_dup 2))) 7053 (set (match_dup 3) 7054 (compare:CC (match_dup 0) 7055 (const_int 0)))] 7056 "") 7057 7058(define_expand "ashrdi3" 7059 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7060 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7061 (match_operand:SI 2 "reg_or_cint_operand" "")))] 7062 "TARGET_POWERPC64 || TARGET_POWER" 7063 " 7064{ 7065 if (TARGET_POWERPC64) 7066 ; 7067 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) 7068 { 7069 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); 7070 DONE; 7071 } 7072 else 7073 FAIL; 7074}") 7075 7076(define_insn "*ashrdi3_internal1" 7077 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7078 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 7079 (match_operand:SI 2 "reg_or_cint_operand" "ri")))] 7080 "TARGET_POWERPC64" 7081 "srad%I2 %0,%1,%H2") 7082 7083(define_insn "*ashrdi3_internal2" 7084 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7085 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7086 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 7087 (const_int 0))) 7088 (clobber (match_scratch:DI 3 "=r,r"))] 7089 "TARGET_POWERPC64" 7090 "@ 7091 srad%I2. %3,%1,%H2 7092 #" 7093 [(set_attr "type" "delayed_compare") 7094 (set_attr "length" "4,8")]) 7095 7096(define_split 7097 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7098 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7099 (match_operand:SI 2 "reg_or_cint_operand" "")) 7100 (const_int 0))) 7101 (clobber (match_scratch:DI 3 ""))] 7102 "TARGET_POWERPC64 && reload_completed" 7103 [(set (match_dup 3) 7104 (ashiftrt:DI (match_dup 1) (match_dup 2))) 7105 (set (match_dup 0) 7106 (compare:CC (match_dup 3) 7107 (const_int 0)))] 7108 "") 7109 7110(define_insn "*ashrdi3_internal3" 7111 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7112 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7113 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 7114 (const_int 0))) 7115 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7116 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 7117 "TARGET_POWERPC64" 7118 "@ 7119 srad%I2. %0,%1,%H2 7120 #" 7121 [(set_attr "type" "delayed_compare") 7122 (set_attr "length" "4,8")]) 7123 7124(define_split 7125 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7126 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7127 (match_operand:SI 2 "reg_or_cint_operand" "")) 7128 (const_int 0))) 7129 (set (match_operand:DI 0 "gpc_reg_operand" "") 7130 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 7131 "TARGET_POWERPC64 && reload_completed" 7132 [(set (match_dup 0) 7133 (ashiftrt:DI (match_dup 1) (match_dup 2))) 7134 (set (match_dup 3) 7135 (compare:CC (match_dup 0) 7136 (const_int 0)))] 7137 "") 7138 7139(define_insn "anddi3" 7140 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7141 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") 7142 (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) 7143 (clobber (match_scratch:CC 3 "=X,X,x,x"))] 7144 "TARGET_POWERPC64" 7145 "@ 7146 and %0,%1,%2 7147 rldic%B2 %0,%1,0,%S2 7148 andi. %0,%1,%b2 7149 andis. %0,%1,%u2") 7150 7151(define_insn "*anddi3_internal2" 7152 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") 7153 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,") 7154 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) 7155 (const_int 0))) 7156 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r")) 7157 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] 7158 "TARGET_POWERPC64" 7159 "@ 7160 and. %3,%1,%2 7161 rldic%B2. %3,%1,0,%S2 7162 andi. %3,%1,%b2 7163 andis. %3,%1,%u2 7164 # 7165 # 7166 # 7167 #" 7168 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") 7169 (set_attr "length" "4,4,4,4,8,8,8,8")]) 7170 7171(define_split 7172 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7173 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7174 (match_operand:DI 2 "and64_operand" "")) 7175 (const_int 0))) 7176 (clobber (match_scratch:DI 3 "")) 7177 (clobber (match_scratch:CC 4 ""))] 7178 "TARGET_POWERPC64 && reload_completed" 7179 [(parallel [(set (match_dup 3) 7180 (and:DI (match_dup 1) 7181 (match_dup 2))) 7182 (clobber (match_dup 4))]) 7183 (set (match_dup 0) 7184 (compare:CC (match_dup 3) 7185 (const_int 0)))] 7186 "") 7187 7188(define_insn "*anddi3_internal3" 7189 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") 7190 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 7191 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) 7192 (const_int 0))) 7193 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") 7194 (and:DI (match_dup 1) (match_dup 2))) 7195 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] 7196 "TARGET_POWERPC64" 7197 "@ 7198 and. %0,%1,%2 7199 rldic%B2. %0,%1,0,%S2 7200 andi. %0,%1,%b2 7201 andis. %0,%1,%u2 7202 # 7203 # 7204 # 7205 #" 7206 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") 7207 (set_attr "length" "4,4,4,4,8,8,8,8")]) 7208 7209(define_split 7210 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7211 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7212 (match_operand:DI 2 "and64_operand" "")) 7213 (const_int 0))) 7214 (set (match_operand:DI 0 "gpc_reg_operand" "") 7215 (and:DI (match_dup 1) (match_dup 2))) 7216 (clobber (match_scratch:CC 4 ""))] 7217 "TARGET_POWERPC64 && reload_completed" 7218 [(parallel [(set (match_dup 0) 7219 (and:DI (match_dup 1) (match_dup 2))) 7220 (clobber (match_dup 4))]) 7221 (set (match_dup 3) 7222 (compare:CC (match_dup 0) 7223 (const_int 0)))] 7224 "") 7225 7226(define_expand "iordi3" 7227 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7228 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") 7229 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] 7230 "TARGET_POWERPC64" 7231 " 7232{ 7233 if (non_logical_cint_operand (operands[2], DImode)) 7234 { 7235 HOST_WIDE_INT value; 7236 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 7237 ? operands[0] : gen_reg_rtx (DImode)); 7238 7239 if (GET_CODE (operands[2]) == CONST_INT) 7240 { 7241 value = INTVAL (operands[2]); 7242 emit_insn (gen_iordi3 (tmp, operands[1], 7243 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 7244 } 7245 else 7246 { 7247 value = CONST_DOUBLE_LOW (operands[2]); 7248 emit_insn (gen_iordi3 (tmp, operands[1], 7249 immed_double_const (value 7250 & (~ (HOST_WIDE_INT) 0xffff), 7251 0, DImode))); 7252 } 7253 7254 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 7255 DONE; 7256 } 7257}") 7258 7259(define_expand "xordi3" 7260 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7261 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") 7262 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] 7263 "TARGET_POWERPC64" 7264 " 7265{ 7266 if (non_logical_cint_operand (operands[2], DImode)) 7267 { 7268 HOST_WIDE_INT value; 7269 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) 7270 ? operands[0] : gen_reg_rtx (DImode)); 7271 7272 if (GET_CODE (operands[2]) == CONST_INT) 7273 { 7274 value = INTVAL (operands[2]); 7275 emit_insn (gen_xordi3 (tmp, operands[1], 7276 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 7277 } 7278 else 7279 { 7280 value = CONST_DOUBLE_LOW (operands[2]); 7281 emit_insn (gen_xordi3 (tmp, operands[1], 7282 immed_double_const (value 7283 & (~ (HOST_WIDE_INT) 0xffff), 7284 0, DImode))); 7285 } 7286 7287 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 7288 DONE; 7289 } 7290}") 7291 7292(define_insn "*booldi3_internal1" 7293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") 7294 (match_operator:DI 3 "boolean_or_operator" 7295 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") 7296 (match_operand:DI 2 "logical_operand" "r,K,JF")]))] 7297 "TARGET_POWERPC64" 7298 "@ 7299 %q3 %0,%1,%2 7300 %q3i %0,%1,%b2 7301 %q3is %0,%1,%u2") 7302 7303(define_insn "*booldi3_internal2" 7304 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7305 (compare:CC (match_operator:DI 4 "boolean_or_operator" 7306 [(match_operand:DI 1 "gpc_reg_operand" "%r,r") 7307 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7308 (const_int 0))) 7309 (clobber (match_scratch:DI 3 "=r,r"))] 7310 "TARGET_POWERPC64" 7311 "@ 7312 %q4. %3,%1,%2 7313 #" 7314 [(set_attr "type" "compare") 7315 (set_attr "length" "4,8")]) 7316 7317(define_split 7318 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7319 (compare:CC (match_operator:DI 4 "boolean_operator" 7320 [(match_operand:DI 1 "gpc_reg_operand" "") 7321 (match_operand:DI 2 "gpc_reg_operand" "")]) 7322 (const_int 0))) 7323 (clobber (match_scratch:DI 3 ""))] 7324 "TARGET_POWERPC64 && reload_completed" 7325 [(set (match_dup 3) (match_dup 4)) 7326 (set (match_dup 0) 7327 (compare:CC (match_dup 3) 7328 (const_int 0)))] 7329 "") 7330 7331(define_insn "*booldi3_internal3" 7332 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7333 (compare:CC (match_operator:DI 4 "boolean_operator" 7334 [(match_operand:DI 1 "gpc_reg_operand" "%r,r") 7335 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7336 (const_int 0))) 7337 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7338 (match_dup 4))] 7339 "TARGET_POWERPC64" 7340 "@ 7341 %q4. %0,%1,%2 7342 #" 7343 [(set_attr "type" "compare") 7344 (set_attr "length" "4,8")]) 7345 7346(define_split 7347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7348 (compare:CC (match_operator:DI 4 "boolean_operator" 7349 [(match_operand:DI 1 "gpc_reg_operand" "") 7350 (match_operand:DI 2 "gpc_reg_operand" "")]) 7351 (const_int 0))) 7352 (set (match_operand:DI 0 "gpc_reg_operand" "") 7353 (match_dup 4))] 7354 "TARGET_POWERPC64 && reload_completed" 7355 [(set (match_dup 0) (match_dup 4)) 7356 (set (match_dup 3) 7357 (compare:CC (match_dup 0) 7358 (const_int 0)))] 7359 "") 7360 7361;; Split an logical operation that we can't do in one insn into two insns, 7362;; each of which does one 16-bit part. This is used by combine. 7363 7364(define_split 7365 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7366 (match_operator:DI 3 "boolean_or_operator" 7367 [(match_operand:DI 1 "gpc_reg_operand" "") 7368 (match_operand:DI 2 "non_logical_cint_operand" "")]))] 7369 "TARGET_POWERPC64" 7370 [(set (match_dup 0) (match_dup 4)) 7371 (set (match_dup 0) (match_dup 5))] 7372" 7373{ 7374 rtx i3,i4; 7375 7376 if (GET_CODE (operands[2]) == CONST_DOUBLE) 7377 { 7378 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); 7379 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), 7380 0, DImode); 7381 i4 = GEN_INT (value & 0xffff); 7382 } 7383 else 7384 { 7385 i3 = GEN_INT (INTVAL (operands[2]) 7386 & (~ (HOST_WIDE_INT) 0xffff)); 7387 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); 7388 } 7389 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, 7390 operands[1], i3); 7391 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, 7392 operands[0], i4); 7393}") 7394 7395(define_insn "*boolcdi3_internal1" 7396 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7397 (match_operator:DI 3 "boolean_operator" 7398 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) 7399 (match_operand:DI 2 "gpc_reg_operand" "r")]))] 7400 "TARGET_POWERPC64" 7401 "%q3 %0,%2,%1") 7402 7403(define_insn "*boolcdi3_internal2" 7404 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7405 (compare:CC (match_operator:DI 4 "boolean_operator" 7406 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 7407 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7408 (const_int 0))) 7409 (clobber (match_scratch:DI 3 "=r,r"))] 7410 "TARGET_POWERPC64" 7411 "@ 7412 %q4. %3,%2,%1 7413 #" 7414 [(set_attr "type" "compare") 7415 (set_attr "length" "4,8")]) 7416 7417(define_split 7418 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7419 (compare:CC (match_operator:DI 4 "boolean_operator" 7420 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7421 (match_operand:DI 2 "gpc_reg_operand" "")]) 7422 (const_int 0))) 7423 (clobber (match_scratch:DI 3 ""))] 7424 "TARGET_POWERPC64 && reload_completed" 7425 [(set (match_dup 3) (match_dup 4)) 7426 (set (match_dup 0) 7427 (compare:CC (match_dup 3) 7428 (const_int 0)))] 7429 "") 7430 7431(define_insn "*boolcdi3_internal3" 7432 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7433 (compare:CC (match_operator:DI 4 "boolean_operator" 7434 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) 7435 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 7436 (const_int 0))) 7437 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7438 (match_dup 4))] 7439 "TARGET_POWERPC64" 7440 "@ 7441 %q4. %0,%2,%1 7442 #" 7443 [(set_attr "type" "compare") 7444 (set_attr "length" "4,8")]) 7445 7446(define_split 7447 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7448 (compare:CC (match_operator:DI 4 "boolean_operator" 7449 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7450 (match_operand:DI 2 "gpc_reg_operand" "")]) 7451 (const_int 0))) 7452 (set (match_operand:DI 0 "gpc_reg_operand" "") 7453 (match_dup 4))] 7454 "TARGET_POWERPC64 && reload_completed" 7455 [(set (match_dup 0) (match_dup 4)) 7456 (set (match_dup 3) 7457 (compare:CC (match_dup 0) 7458 (const_int 0)))] 7459 "") 7460 7461(define_insn "*boolccdi3_internal1" 7462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7463 (match_operator:DI 3 "boolean_operator" 7464 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) 7465 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] 7466 "TARGET_POWERPC64" 7467 "%q3 %0,%1,%2") 7468 7469(define_insn "*boolccdi3_internal2" 7470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7471 (compare:CC (match_operator:DI 4 "boolean_operator" 7472 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 7473 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) 7474 (const_int 0))) 7475 (clobber (match_scratch:DI 3 "=r,r"))] 7476 "TARGET_POWERPC64" 7477 "@ 7478 %q4. %3,%1,%2 7479 #" 7480 [(set_attr "type" "compare") 7481 (set_attr "length" "4,8")]) 7482 7483(define_split 7484 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7485 (compare:CC (match_operator:DI 4 "boolean_operator" 7486 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7487 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) 7488 (const_int 0))) 7489 (clobber (match_scratch:DI 3 ""))] 7490 "TARGET_POWERPC64 && reload_completed" 7491 [(set (match_dup 3) (match_dup 4)) 7492 (set (match_dup 0) 7493 (compare:CC (match_dup 3) 7494 (const_int 0)))] 7495 "") 7496 7497(define_insn "*boolccdi3_internal3" 7498 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 7499 (compare:CC (match_operator:DI 4 "boolean_operator" 7500 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) 7501 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) 7502 (const_int 0))) 7503 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7504 (match_dup 4))] 7505 "TARGET_POWERPC64" 7506 "@ 7507 %q4. %0,%1,%2 7508 #" 7509 [(set_attr "type" "compare") 7510 (set_attr "length" "4,8")]) 7511 7512(define_split 7513 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7514 (compare:CC (match_operator:DI 4 "boolean_operator" 7515 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 7516 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) 7517 (const_int 0))) 7518 (set (match_operand:DI 0 "gpc_reg_operand" "") 7519 (match_dup 4))] 7520 "TARGET_POWERPC64 && reload_completed" 7521 [(set (match_dup 0) (match_dup 4)) 7522 (set (match_dup 3) 7523 (compare:CC (match_dup 0) 7524 (const_int 0)))] 7525 "") 7526 7527;; Now define ways of moving data around. 7528 7529;; Elf specific ways of loading addresses for non-PIC code. 7530;; The output of this could be r0, but we make a very strong 7531;; preference for a base register because it will usually 7532;; be needed there. 7533(define_insn "elf_high" 7534 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") 7535 (high:SI (match_operand 1 "" "")))] 7536 "TARGET_ELF && ! TARGET_64BIT" 7537 "{liu|lis} %0,%1@ha") 7538 7539(define_insn "elf_low" 7540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 7541 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") 7542 (match_operand 2 "" "")))] 7543 "TARGET_ELF && ! TARGET_64BIT" 7544 "@ 7545 {cal|la} %0,%2@l(%1) 7546 {ai|addic} %0,%1,%K2") 7547 7548;; Mach-O PIC trickery. 7549(define_insn "macho_high" 7550 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") 7551 (high:SI (match_operand 1 "" "")))] 7552 "TARGET_MACHO && ! TARGET_64BIT" 7553 "{liu|lis} %0,ha16(%1)") 7554 7555(define_insn "macho_low" 7556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 7557 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") 7558 (match_operand 2 "" "")))] 7559 "TARGET_MACHO && ! TARGET_64BIT" 7560 "@ 7561 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} 7562 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") 7563 7564;; Set up a register with a value from the GOT table 7565 7566(define_expand "movsi_got" 7567 [(set (match_operand:SI 0 "gpc_reg_operand" "") 7568 (unspec:SI [(match_operand:SI 1 "got_operand" "") 7569 (match_dup 2)] 8))] 7570 "DEFAULT_ABI == ABI_V4 && flag_pic == 1" 7571 " 7572{ 7573 if (GET_CODE (operands[1]) == CONST) 7574 { 7575 rtx offset = const0_rtx; 7576 HOST_WIDE_INT value; 7577 7578 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); 7579 value = INTVAL (offset); 7580 if (value != 0) 7581 { 7582 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); 7583 emit_insn (gen_movsi_got (tmp, operands[1])); 7584 emit_insn (gen_addsi3 (operands[0], tmp, offset)); 7585 DONE; 7586 } 7587 } 7588 7589 operands[2] = rs6000_got_register (operands[1]); 7590}") 7591 7592(define_insn "*movsi_got_internal" 7593 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7594 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") 7595 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] 7596 "DEFAULT_ABI == ABI_V4 && flag_pic == 1" 7597 "{l|lwz} %0,%a1@got(%2)" 7598 [(set_attr "type" "load")]) 7599 7600;; Used by sched, shorten_branches and final when the GOT pseudo reg 7601;; didn't get allocated to a hard register. 7602(define_split 7603 [(set (match_operand:SI 0 "gpc_reg_operand" "") 7604 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") 7605 (match_operand:SI 2 "memory_operand" "")] 8))] 7606 "DEFAULT_ABI == ABI_V4 7607 && flag_pic == 1 7608 && (reload_in_progress || reload_completed)" 7609 [(set (match_dup 0) (match_dup 2)) 7610 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))] 7611 "") 7612 7613;; For SI, we special-case integers that can't be loaded in one insn. We 7614;; do the load 16-bits at a time. We could do this by loading from memory, 7615;; and this is even supposed to be faster, but it is simpler not to get 7616;; integers in the TOC. 7617(define_expand "movsi" 7618 [(set (match_operand:SI 0 "general_operand" "") 7619 (match_operand:SI 1 "any_operand" ""))] 7620 "" 7621 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") 7622 7623(define_insn "movsi_low" 7624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 7625 (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b") 7626 (match_operand 2 "" ""))))] 7627 "TARGET_MACHO && ! TARGET_64BIT" 7628 "{l|lwz} %0,lo16(%2)(%1)" 7629 [(set_attr "type" "load") 7630 (set_attr "length" "4")]) 7631 7632(define_insn "movsi_low_st" 7633 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b") 7634 (match_operand 2 "" ""))) 7635 (match_operand:SI 0 "gpc_reg_operand" "r"))] 7636 "TARGET_MACHO && ! TARGET_64BIT" 7637 "{st|stw} %0,lo16(%2)(%1)" 7638 [(set_attr "type" "store") 7639 (set_attr "length" "4")]) 7640 7641(define_insn "movdf_low" 7642 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") 7643 (mem:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b") 7644 (match_operand 2 "" ""))))] 7645 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" 7646 "* 7647{ 7648 switch (which_alternative) 7649 { 7650 case 0: 7651 return \"lfd %0,lo16(%2)(%1)\"; 7652 case 1: 7653 { 7654 rtx operands2[4]; 7655 operands2[0] = operands[0]; 7656 operands2[1] = operands[1]; 7657 operands2[2] = operands[2]; 7658 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); 7659 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); 7660 /* We cannot rely on ha16(low half)==ha16(high half), alas, 7661 although in practice it almost always is. */ 7662 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); 7663 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); 7664 } 7665 default: 7666 abort(); 7667 } 7668}" 7669 [(set_attr "type" "load") 7670 (set_attr "length" "4,12")]) 7671 7672(define_insn "movdf_low_st" 7673 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "b") 7674 (match_operand 2 "" ""))) 7675 (match_operand:DF 0 "gpc_reg_operand" "f"))] 7676 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" 7677 "stfd %0,lo16(%2)(%1)" 7678 [(set_attr "type" "store") 7679 (set_attr "length" "4")]) 7680 7681(define_insn "movsf_low" 7682 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") 7683 (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b") 7684 (match_operand 2 "" ""))))] 7685 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" 7686 "@ 7687 lfs %0,lo16(%2)(%1) 7688 {l|lwz} %0,lo16(%2)(%1)" 7689 [(set_attr "type" "load") 7690 (set_attr "length" "4")]) 7691 7692(define_insn "movsf_low_st" 7693 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b") 7694 (match_operand 2 "" ""))) 7695 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] 7696 "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" 7697 "@ 7698 stfs %0,lo16(%2)(%1) 7699 {st|stw} %0,lo16(%2)(%1)" 7700 [(set_attr "type" "store") 7701 (set_attr "length" "4")]) 7702 7703(define_insn "*movsi_internal1" 7704 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") 7705 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] 7706 "gpc_reg_operand (operands[0], SImode) 7707 || gpc_reg_operand (operands[1], SImode)" 7708 "@ 7709 mr %0,%1 7710 {cal|la} %0,%a1 7711 {l%U1%X1|lwz%U1%X1} %0,%1 7712 {st%U0%X0|stw%U0%X0} %1,%0 7713 {lil|li} %0,%1 7714 {liu|lis} %0,%v1 7715 # 7716 {cal|la} %0,%a1 7717 mf%1 %0 7718 mt%0 %1 7719 mt%0 %1 7720 mt%0 %1 7721 cror 0,0,0" 7722 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*") 7723 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) 7724 7725;; Split a load of a large constant into the appropriate two-insn 7726;; sequence. 7727 7728(define_split 7729 [(set (match_operand:SI 0 "gpc_reg_operand" "") 7730 (match_operand:SI 1 "const_int_operand" ""))] 7731 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 7732 && (INTVAL (operands[1]) & 0xffff) != 0" 7733 [(set (match_dup 0) 7734 (match_dup 2)) 7735 (set (match_dup 0) 7736 (ior:SI (match_dup 0) 7737 (match_dup 3)))] 7738 " 7739{ 7740 operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); 7741 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); 7742}") 7743 7744(define_insn "*movsi_internal2" 7745 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 7746 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") 7747 (const_int 0))) 7748 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] 7749 "! TARGET_POWERPC64" 7750 "@ 7751 mr. %0,%1 7752 #" 7753 [(set_attr "type" "compare") 7754 (set_attr "length" "4,8")]) 7755 7756(define_split 7757 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 7758 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 7759 (const_int 0))) 7760 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] 7761 "! TARGET_POWERPC64 && reload_completed" 7762 [(set (match_dup 0) (match_dup 1)) 7763 (set (match_dup 2) 7764 (compare:CC (match_dup 0) 7765 (const_int 0)))] 7766 "") 7767 7768(define_expand "movhi" 7769 [(set (match_operand:HI 0 "general_operand" "") 7770 (match_operand:HI 1 "any_operand" ""))] 7771 "" 7772 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") 7773 7774(define_insn "" 7775 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 7776 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 7777 "gpc_reg_operand (operands[0], HImode) 7778 || gpc_reg_operand (operands[1], HImode)" 7779 "@ 7780 mr %0,%1 7781 lhz%U1%X1 %0,%1 7782 sth%U0%X0 %1,%0 7783 {lil|li} %0,%w1 7784 mf%1 %0 7785 mt%0 %1 7786 mt%0 %1 7787 cror 0,0,0" 7788 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) 7789 7790(define_expand "movqi" 7791 [(set (match_operand:QI 0 "general_operand" "") 7792 (match_operand:QI 1 "any_operand" ""))] 7793 "" 7794 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") 7795 7796(define_insn "" 7797 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") 7798 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] 7799 "gpc_reg_operand (operands[0], QImode) 7800 || gpc_reg_operand (operands[1], QImode)" 7801 "@ 7802 mr %0,%1 7803 lbz%U1%X1 %0,%1 7804 stb%U0%X0 %1,%0 7805 {lil|li} %0,%1 7806 mf%1 %0 7807 mt%0 %1 7808 mt%0 %1 7809 cror 0,0,0" 7810 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) 7811 7812;; Here is how to move condition codes around. When we store CC data in 7813;; an integer register or memory, we store just the high-order 4 bits. 7814;; This lets us not shift in the most common case of CR0. 7815(define_expand "movcc" 7816 [(set (match_operand:CC 0 "nonimmediate_operand" "") 7817 (match_operand:CC 1 "nonimmediate_operand" ""))] 7818 "" 7819 "") 7820 7821(define_insn "" 7822 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") 7823 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] 7824 "register_operand (operands[0], CCmode) 7825 || register_operand (operands[1], CCmode)" 7826 "@ 7827 mcrf %0,%1 7828 mtcrf 128,%1 7829 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff 7830 mfcr %0 7831 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 7832 mr %0,%1 7833 {l%U1%X1|lwz%U1%X1} %0,%1 7834 {st%U0%U1|stw%U0%U1} %1,%0" 7835 [(set_attr "type" "*,*,*,compare,*,*,load,store") 7836 (set_attr "length" "*,*,12,*,8,*,*,*")]) 7837 7838;; For floating-point, we normally deal with the floating-point registers 7839;; unless -msoft-float is used. The sole exception is that parameter passing 7840;; can produce floating-point values in fixed-point registers. Unless the 7841;; value is a simple constant or already in memory, we deal with this by 7842;; allocating memory and copying the value explicitly via that memory location. 7843(define_expand "movsf" 7844 [(set (match_operand:SF 0 "nonimmediate_operand" "") 7845 (match_operand:SF 1 "any_operand" ""))] 7846 "" 7847 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") 7848 7849(define_split 7850 [(set (match_operand:SF 0 "gpc_reg_operand" "") 7851 (match_operand:SF 1 "const_double_operand" ""))] 7852 "reload_completed 7853 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 7854 || (GET_CODE (operands[0]) == SUBREG 7855 && GET_CODE (SUBREG_REG (operands[0])) == REG 7856 && REGNO (SUBREG_REG (operands[0])) <= 31))" 7857 [(set (match_dup 2) (match_dup 3))] 7858 " 7859{ 7860 long l; 7861 REAL_VALUE_TYPE rv; 7862 7863 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 7864 REAL_VALUE_TO_TARGET_SINGLE (rv, l); 7865 7866 if (! TARGET_POWERPC64) 7867 operands[2] = operand_subword (operands[0], 0, 0, SFmode); 7868 else 7869 operands[2] = gen_lowpart (SImode, operands[0]); 7870 7871 operands[3] = GEN_INT (trunc_int_for_mode (l, SImode)); 7872}") 7873 7874(define_insn "*movsf_hardfloat" 7875 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") 7876 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] 7877 "(gpc_reg_operand (operands[0], SFmode) 7878 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" 7879 "@ 7880 mr %0,%1 7881 {l%U1%X1|lwz%U1%X1} %0,%1 7882 {st%U0%X0|stw%U0%X0} %1,%0 7883 fmr %0,%1 7884 lfs%U1%X1 %0,%1 7885 stfs%U0%X0 %1,%0 7886 # 7887 #" 7888 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") 7889 (set_attr "length" "4,4,4,4,4,4,4,8")]) 7890 7891(define_insn "*movsf_softfloat" 7892 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") 7893 (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] 7894 "(gpc_reg_operand (operands[0], SFmode) 7895 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" 7896 "@ 7897 mr %0,%1 7898 {l%U1%X1|lwz%U1%X1} %0,%1 7899 {st%U0%X0|stw%U0%X0} %1,%0 7900 {lil|li} %0,%1 7901 {liu|lis} %0,%v1 7902 {cal|la} %0,%a1 7903 # 7904 #" 7905 [(set_attr "type" "*,load,store,*,*,*,*,*") 7906 (set_attr "length" "4,4,4,4,4,4,4,8")]) 7907 7908 7909(define_expand "movdf" 7910 [(set (match_operand:DF 0 "nonimmediate_operand" "") 7911 (match_operand:DF 1 "any_operand" ""))] 7912 "" 7913 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") 7914 7915(define_split 7916 [(set (match_operand:DF 0 "gpc_reg_operand" "") 7917 (match_operand:DF 1 "const_int_operand" ""))] 7918 "! TARGET_POWERPC64 && reload_completed 7919 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 7920 || (GET_CODE (operands[0]) == SUBREG 7921 && GET_CODE (SUBREG_REG (operands[0])) == REG 7922 && REGNO (SUBREG_REG (operands[0])) <= 31))" 7923 [(set (match_dup 2) (match_dup 4)) 7924 (set (match_dup 3) (match_dup 1))] 7925 " 7926{ 7927 int endian = (WORDS_BIG_ENDIAN == 0); 7928 HOST_WIDE_INT value = INTVAL (operands[1]); 7929 7930 operands[2] = operand_subword (operands[0], endian, 0, DFmode); 7931 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); 7932#if HOST_BITS_PER_WIDE_INT == 32 7933 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; 7934#else 7935 operands[4] = GEN_INT (value >> 32); 7936 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); 7937#endif 7938}") 7939 7940(define_split 7941 [(set (match_operand:DF 0 "gpc_reg_operand" "") 7942 (match_operand:DF 1 "const_double_operand" ""))] 7943 "! TARGET_POWERPC64 && reload_completed 7944 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 7945 || (GET_CODE (operands[0]) == SUBREG 7946 && GET_CODE (SUBREG_REG (operands[0])) == REG 7947 && REGNO (SUBREG_REG (operands[0])) <= 31))" 7948 [(set (match_dup 2) (match_dup 4)) 7949 (set (match_dup 3) (match_dup 5))] 7950 " 7951{ 7952 int endian = (WORDS_BIG_ENDIAN == 0); 7953 long l[2]; 7954 REAL_VALUE_TYPE rv; 7955 7956 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 7957 REAL_VALUE_TO_TARGET_DOUBLE (rv, l); 7958 7959 operands[2] = operand_subword (operands[0], endian, 0, DFmode); 7960 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); 7961 operands[4] = GEN_INT (trunc_int_for_mode (l[endian], SImode)); 7962 operands[5] = GEN_INT (trunc_int_for_mode (l[1 - endian], SImode)); 7963}") 7964 7965(define_split 7966 [(set (match_operand:DF 0 "gpc_reg_operand" "") 7967 (match_operand:DF 1 "easy_fp_constant" ""))] 7968 "TARGET_POWERPC64 && reload_completed 7969 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 7970 || (GET_CODE (operands[0]) == SUBREG 7971 && GET_CODE (SUBREG_REG (operands[0])) == REG 7972 && REGNO (SUBREG_REG (operands[0])) <= 31))" 7973 [(set (match_dup 2) (match_dup 3))] 7974 " 7975{ 7976 int endian = (WORDS_BIG_ENDIAN == 0); 7977 long l[2]; 7978 REAL_VALUE_TYPE rv; 7979 HOST_WIDE_INT val; 7980 7981 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 7982 REAL_VALUE_TO_TARGET_DOUBLE (rv, l); 7983 7984 operands[2] = gen_lowpart (DImode, operands[0]); 7985 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ 7986#if HOST_BITS_PER_WIDE_INT >= 64 7987 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 | 7988 ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); 7989 7990 operands[3] = immed_double_const (val, -(val < 0), DImode); 7991#else 7992 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); 7993#endif 7994}") 7995 7996;; Don't have reload use general registers to load a constant. First, 7997;; it might not work if the output operand is the equivalent of 7998;; a non-offsettable memref, but also it is less efficient than loading 7999;; the constant into an FP register, since it will probably be used there. 8000;; The "??" is a kludge until we can figure out a more reasonable way 8001;; of handling these non-offsettable values. 8002(define_insn "*movdf_hardfloat32" 8003 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") 8004 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] 8005 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT 8006 && (gpc_reg_operand (operands[0], DFmode) 8007 || gpc_reg_operand (operands[1], DFmode))" 8008 "* 8009{ 8010 switch (which_alternative) 8011 { 8012 default: 8013 abort (); 8014 case 0: 8015 /* We normally copy the low-numbered register first. However, if 8016 the first register operand 0 is the same as the second register 8017 of operand 1, we must copy in the opposite order. */ 8018 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8019 return \"mr %L0,%L1\;mr %0,%1\"; 8020 else 8021 return \"mr %0,%1\;mr %L0,%L1\"; 8022 case 1: 8023 if (offsettable_memref_p (operands[1]) 8024 || (GET_CODE (operands[1]) == MEM 8025 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM 8026 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC 8027 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) 8028 { 8029 /* If the low-address word is used in the address, we must load 8030 it last. Otherwise, load it first. Note that we cannot have 8031 auto-increment in that case since the address register is 8032 known to be dead. */ 8033 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8034 operands[1], 0)) 8035 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 8036 else 8037 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 8038 } 8039 else 8040 { 8041 rtx addreg; 8042 8043 addreg = find_addr_reg (XEXP (operands[1], 0)); 8044 if (refers_to_regno_p (REGNO (operands[0]), 8045 REGNO (operands[0]) + 1, 8046 operands[1], 0)) 8047 { 8048 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); 8049 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); 8050 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 8051 return \"{lx|lwzx} %0,%1\"; 8052 } 8053 else 8054 { 8055 output_asm_insn (\"{lx|lwzx} %0,%1\", operands); 8056 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); 8057 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); 8058 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 8059 return \"\"; 8060 } 8061 } 8062 case 2: 8063 if (offsettable_memref_p (operands[0]) 8064 || (GET_CODE (operands[0]) == MEM 8065 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM 8066 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC 8067 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) 8068 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 8069 else 8070 { 8071 rtx addreg; 8072 8073 addreg = find_addr_reg (XEXP (operands[0], 0)); 8074 output_asm_insn (\"{stx|stwx} %1,%0\", operands); 8075 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); 8076 output_asm_insn (\"{stx|stwx} %L1,%0\", operands); 8077 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 8078 return \"\"; 8079 } 8080 case 3: 8081 case 4: 8082 case 5: 8083 return \"#\"; 8084 case 6: 8085 return \"fmr %0,%1\"; 8086 case 7: 8087 return \"lfd%U1%X1 %0,%1\"; 8088 case 8: 8089 return \"stfd%U0%X0 %1,%0\"; 8090 } 8091}" 8092 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") 8093 (set_attr "length" "8,16,16,8,12,16,*,*,*")]) 8094 8095(define_insn "*movdf_softfloat32" 8096 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") 8097 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] 8098 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT 8099 && (gpc_reg_operand (operands[0], DFmode) 8100 || gpc_reg_operand (operands[1], DFmode))" 8101 "* 8102{ 8103 switch (which_alternative) 8104 { 8105 default: 8106 abort (); 8107 case 0: 8108 /* We normally copy the low-numbered register first. However, if 8109 the first register operand 0 is the same as the second register of 8110 operand 1, we must copy in the opposite order. */ 8111 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8112 return \"mr %L0,%L1\;mr %0,%1\"; 8113 else 8114 return \"mr %0,%1\;mr %L0,%L1\"; 8115 case 1: 8116 /* If the low-address word is used in the address, we must load 8117 it last. Otherwise, load it first. Note that we cannot have 8118 auto-increment in that case since the address register is 8119 known to be dead. */ 8120 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8121 operands[1], 0)) 8122 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 8123 else 8124 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 8125 case 2: 8126 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 8127 case 3: 8128 case 4: 8129 case 5: 8130 return \"#\"; 8131 } 8132}" 8133 [(set_attr "type" "*,load,store,*,*,*") 8134 (set_attr "length" "8,8,8,8,12,16")]) 8135 8136(define_insn "*movdf_hardfloat64" 8137 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") 8138 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] 8139 "TARGET_POWERPC64 && TARGET_HARD_FLOAT 8140 && (gpc_reg_operand (operands[0], DFmode) 8141 || gpc_reg_operand (operands[1], DFmode))" 8142 "@ 8143 mr %0,%1 8144 ld%U1%X1 %0,%1 8145 std%U0%X0 %1,%0 8146 # 8147 # 8148 # 8149 fmr %0,%1 8150 lfd%U1%X1 %0,%1 8151 stfd%U0%X0 %1,%0" 8152 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") 8153 (set_attr "length" "4,4,4,8,12,16,4,4,4")]) 8154 8155(define_insn "*movdf_softfloat64" 8156 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") 8157 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] 8158 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT 8159 && (gpc_reg_operand (operands[0], DFmode) 8160 || gpc_reg_operand (operands[1], DFmode))" 8161 "@ 8162 mr %0,%1 8163 ld%U1%X1 %0,%1 8164 std%U0%X0 %1,%0 8165 # 8166 # 8167 #" 8168 [(set_attr "type" "*,load,store,*,*,*") 8169 (set_attr "length" "*,*,*,8,12,16")]) 8170 8171(define_expand "movtf" 8172 [(set (match_operand:TF 0 "general_operand" "") 8173 (match_operand:TF 1 "any_operand" ""))] 8174 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8175 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") 8176 8177(define_insn "*movtf_internal" 8178 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r") 8179 (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))] 8180 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128 8181 && (gpc_reg_operand (operands[0], TFmode) 8182 || gpc_reg_operand (operands[1], TFmode))" 8183 "* 8184{ 8185 switch (which_alternative) 8186 { 8187 default: 8188 abort (); 8189 case 0: 8190 /* We normally copy the low-numbered register first. However, if 8191 the first register operand 0 is the same as the second register of 8192 operand 1, we must copy in the opposite order. */ 8193 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8194 return \"fmr %L0,%L1\;fmr %0,%1\"; 8195 else 8196 return \"fmr %0,%1\;fmr %L0,%L1\"; 8197 case 1: 8198 return \"lfd %0,%1\;lfd %L0,%L1\"; 8199 case 2: 8200 return \"stfd %1,%0\;stfd %L1,%L0\"; 8201 case 3: 8202 case 4: 8203 case 5: 8204 return \"#\"; 8205 } 8206}" 8207 [(set_attr "type" "fp,fpload,fpstore,*,*,*") 8208 (set_attr "length" "8,8,8,12,16,20")]) 8209 8210(define_split 8211 [(set (match_operand:TF 0 "gpc_reg_operand" "") 8212 (match_operand:TF 1 "const_double_operand" ""))] 8213 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8214 [(set (match_dup 3) (match_dup 1)) 8215 (set (match_dup 0) 8216 (float_extend:TF (match_dup 3)))] 8217 " 8218{ 8219 operands[2] = operand_subword (operands[1], 0, 0, DFmode); 8220 operands[3] = gen_reg_rtx (DFmode); 8221}") 8222 8223(define_insn_and_split "extenddftf2" 8224 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8225 (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))] 8226 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8227 "#" 8228 "" 8229 [(set (match_dup 2) (match_dup 3))] 8230 " 8231{ 8232 operands[2] = gen_rtx_REG (DFmode, REGNO (operands[0] + 1)); 8233 operands[3] = CONST0_RTX (DFmode); 8234}") 8235 8236(define_insn_and_split "extendsftf2" 8237 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8238 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))] 8239 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8240 "#" 8241 "" 8242 [(set (match_dup 2) (match_dup 3))] 8243 " 8244{ 8245 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0] + 1)); 8246 operands[3] = CONST0_RTX (SFmode); 8247}") 8248 8249(define_insn "trunctfdf2" 8250 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 8251 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8252 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8253 "fadd %0,%1,%L1" 8254 [(set_attr "type" "fp") 8255 (set_attr "length" "8")]) 8256 8257(define_insn_and_split "trunctfsf2" 8258 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 8259 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8260 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8261 "#" 8262 "" 8263 [(set (match_dup 2) 8264 (float_truncate:DF (match_dup 1))) 8265 (set (match_dup 0) 8266 (float_truncate:SF (match_dup 2)))] 8267 " 8268{ 8269 operands[2] = gen_reg_rtx (DFmode); 8270}") 8271 8272(define_expand "floatditf2" 8273 [(set (match_dup 2) 8274 (float:DF (match_operand:DI 1 "gpc_reg_operand" ""))) 8275 (set (match_operand:TF 0 "gpc_reg_operand" "") 8276 (float_extend:TF (match_dup 2)))] 8277 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 8278 && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8279 "{ operands[2] = gen_reg_rtx (DFmode); }") 8280 8281(define_expand "floatsitf2" 8282 [(set (match_dup 2) 8283 (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) 8284 (set (match_operand:TF 0 "gpc_reg_operand" "") 8285 (float_extend:TF (match_dup 2)))] 8286 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8287 "{ operands[2] = gen_reg_rtx (DFmode); }") 8288 8289(define_expand "fix_trunctfdi2" 8290 [(set (match_dup 2) 8291 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) 8292 (set (match_operand:DI 0 "gpc_reg_operand" "") 8293 (fix:SI (match_dup 2)))] 8294 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 8295 && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8296 "{ operands[2] = gen_reg_rtx (DFmode); }") 8297 8298(define_expand "fix_trunctfsi2" 8299 [(set (match_dup 2) 8300 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) 8301 (set (match_operand:SI 0 "gpc_reg_operand" "") 8302 (fix:SI (match_dup 2)))] 8303 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8304 "{ operands[2] = gen_reg_rtx (DFmode); }") 8305 8306(define_insn "negtf2" 8307 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8308 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8309 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8310 "* 8311{ 8312 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8313 return \"fneg %L0,%L1\;fneg %0,%1\"; 8314 else 8315 return \"fneg %0,%1\;fneg %L0,%L1\"; 8316}" 8317 [(set_attr "type" "fp") 8318 (set_attr "length" "8")]) 8319 8320(define_insn "abstf2" 8321 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8322 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] 8323 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8324 "* 8325{ 8326 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8327 return \"fabs %L0,%L1\;fabs %0,%1\"; 8328 else 8329 return \"fabs %0,%1\;fabs %L0,%L1\"; 8330}" 8331 [(set_attr "type" "fp") 8332 (set_attr "length" "8")]) 8333 8334(define_insn "" 8335 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 8336 (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))] 8337 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 8338 "* 8339{ 8340 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8341 return \"fnabs %L0,%L1\;fnabs %0,%1\"; 8342 else 8343 return \"fnabs %0,%1\;fnabs %L0,%L1\"; 8344}" 8345 [(set_attr "type" "fp") 8346 (set_attr "length" "8")]) 8347 8348;; Next come the multi-word integer load and store and the load and store 8349;; multiple insns. 8350(define_expand "movdi" 8351 [(set (match_operand:DI 0 "general_operand" "") 8352 (match_operand:DI 1 "any_operand" ""))] 8353 "" 8354 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") 8355 8356(define_insn "*movdi_internal32" 8357 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") 8358 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] 8359 "! TARGET_POWERPC64 8360 && (gpc_reg_operand (operands[0], DImode) 8361 || gpc_reg_operand (operands[1], DImode))" 8362 "* 8363{ 8364 switch (which_alternative) 8365 { 8366 default: 8367 abort (); 8368 case 0: 8369 /* We normally copy the low-numbered register first. However, if 8370 the first register operand 0 is the same as the second register of 8371 operand 1, we must copy in the opposite order. */ 8372 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8373 return \"mr %L0,%L1\;mr %0,%1\"; 8374 else 8375 return \"mr %0,%1\;mr %L0,%L1\"; 8376 case 1: 8377 /* If the low-address word is used in the address, we must load it 8378 last. Otherwise, load it first. Note that we cannot have 8379 auto-increment in that case since the address register is known to be 8380 dead. */ 8381 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8382 operands[1], 0)) 8383 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; 8384 else 8385 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; 8386 case 2: 8387 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; 8388 case 3: 8389 return \"fmr %0,%1\"; 8390 case 4: 8391 return \"lfd%U1%X1 %0,%1\"; 8392 case 5: 8393 return \"stfd%U0%X0 %1,%0\"; 8394 case 6: 8395 case 7: 8396 case 8: 8397 case 9: 8398 case 10: 8399 return \"#\"; 8400 } 8401}" 8402 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") 8403 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) 8404 8405(define_split 8406 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8407 (match_operand:DI 1 "const_int_operand" ""))] 8408 "! TARGET_POWERPC64 && reload_completed" 8409 [(set (match_dup 2) (match_dup 4)) 8410 (set (match_dup 3) (match_dup 1))] 8411 " 8412{ 8413 HOST_WIDE_INT value = INTVAL (operands[1]); 8414 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, 8415 DImode); 8416 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, 8417 DImode); 8418#if HOST_BITS_PER_WIDE_INT == 32 8419 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; 8420#else 8421 operands[4] = GEN_INT (value >> 32); 8422 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); 8423#endif 8424}") 8425 8426(define_split 8427 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8428 (match_operand:DI 1 "const_double_operand" ""))] 8429 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" 8430 [(set (match_dup 2) (match_dup 4)) 8431 (set (match_dup 3) (match_dup 5))] 8432 " 8433{ 8434 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, 8435 DImode); 8436 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, 8437 DImode); 8438 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); 8439 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); 8440}") 8441 8442(define_insn "*movdi_internal64" 8443 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") 8444 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] 8445 "TARGET_POWERPC64 8446 && (gpc_reg_operand (operands[0], DImode) 8447 || gpc_reg_operand (operands[1], DImode))" 8448 "@ 8449 mr %0,%1 8450 ld%U1%X1 %0,%1 8451 std%U0%X0 %1,%0 8452 li %0,%1 8453 lis %0,%v1 8454 # 8455 {cal|la} %0,%a1 8456 fmr %0,%1 8457 lfd%U1%X1 %0,%1 8458 stfd%U0%X0 %1,%0 8459 mf%1 %0 8460 mt%0 %1 8461 cror 0,0,0" 8462 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") 8463 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) 8464 8465;; immediate value valid for a single instruction hiding in a const_double 8466(define_insn "" 8467 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 8468 (match_operand:DI 1 "const_double_operand" "F"))] 8469 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 8470 && GET_CODE (operands[1]) == CONST_DOUBLE 8471 && num_insns_constant (operands[1], DImode) == 1" 8472 "* 8473{ 8474 return ((unsigned HOST_WIDE_INT) 8475 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) 8476 ? \"li %0,%1\" : \"lis %0,%v1\"; 8477}") 8478 8479;; Generate all one-bits and clear left or right. 8480;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. 8481(define_split 8482 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8483 (match_operand:DI 1 "mask64_operand" ""))] 8484 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 8485 [(set (match_dup 0) (const_int -1)) 8486 (set (match_dup 0) 8487 (and:DI (rotate:DI (match_dup 0) 8488 (const_int 0)) 8489 (match_dup 1)))] 8490 "") 8491 8492;; Split a load of a large constant into the appropriate five-instruction 8493;; sequence. Handle anything in a constant number of insns. 8494;; When non-easy constants can go in the TOC, this should use 8495;; easy_fp_constant predicate. 8496(define_split 8497 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8498 (match_operand:DI 1 "const_int_operand" ""))] 8499 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 8500 [(set (match_dup 0) (match_dup 2)) 8501 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 8502 " 8503{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); 8504 8505 if (tem == operands[0]) 8506 DONE; 8507 else 8508 FAIL; 8509}") 8510 8511(define_split 8512 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8513 (match_operand:DI 1 "const_double_operand" ""))] 8514 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 8515 [(set (match_dup 0) (match_dup 2)) 8516 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 8517 " 8518{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); 8519 8520 if (tem == operands[0]) 8521 DONE; 8522 else 8523 FAIL; 8524}") 8525 8526;; Split a load of a large constant into the appropriate five-instruction 8527(define_insn "*movdi_internal2" 8528 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 8529 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") 8530 (const_int 0))) 8531 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] 8532 "TARGET_POWERPC64" 8533 "@ 8534 mr. %0,%1 8535 #" 8536 [(set_attr "type" "compare") 8537 (set_attr "length" "4,8")]) 8538 8539(define_split 8540 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 8541 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") 8542 (const_int 0))) 8543 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] 8544 "TARGET_POWERPC64 && reload_completed" 8545 [(set (match_dup 0) (match_dup 1)) 8546 (set (match_dup 2) 8547 (compare:CC (match_dup 0) 8548 (const_int 0)))] 8549 "") 8550 8551;; TImode is similar, except that we usually want to compute the address into 8552;; a register and use lsi/stsi (the exception is during reload). MQ is also 8553;; clobbered in stsi for POWER, so we need a SCRATCH for it. 8554(define_expand "movti" 8555 [(parallel [(set (match_operand:TI 0 "general_operand" "") 8556 (match_operand:TI 1 "general_operand" "")) 8557 (clobber (scratch:SI))])] 8558 "TARGET_STRING || TARGET_POWERPC64" 8559 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") 8560 8561;; We say that MQ is clobbered in the last alternative because the first 8562;; alternative would never get used otherwise since it would need a reload 8563;; while the 2nd alternative would not. We put memory cases first so they 8564;; are preferred. Otherwise, we'd try to reload the output instead of 8565;; giving the SCRATCH mq. 8566(define_insn "*movti_power" 8567 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") 8568 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) 8569 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] 8570 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 8571 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" 8572 "* 8573{ 8574 switch (which_alternative) 8575 { 8576 default: 8577 abort (); 8578 8579 case 0: 8580 return \"{stsi|stswi} %1,%P0,16\"; 8581 8582 case 1: 8583 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; 8584 8585 case 2: 8586 /* Normally copy registers with lowest numbered register copied first. 8587 But copy in the other order if the first register of the output 8588 is the second, third, or fourth register in the input. */ 8589 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 8590 && REGNO (operands[0]) <= REGNO (operands[1]) + 3) 8591 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; 8592 else 8593 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; 8594 case 3: 8595 /* If the address is not used in the output, we can use lsi. Otherwise, 8596 fall through to generating four loads. */ 8597 if (! reg_overlap_mentioned_p (operands[0], operands[1])) 8598 return \"{lsi|lswi} %0,%P1,16\"; 8599 /* ... fall through ... */ 8600 case 4: 8601 /* If the address register is the same as the register for the lowest- 8602 addressed word, load it last. Similarly for the next two words. 8603 Otherwise load lowest address to highest. */ 8604 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8605 operands[1], 0)) 8606 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; 8607 else if (refers_to_regno_p (REGNO (operands[0]) + 1, 8608 REGNO (operands[0]) + 2, operands[1], 0)) 8609 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; 8610 else if (refers_to_regno_p (REGNO (operands[0]) + 2, 8611 REGNO (operands[0]) + 3, operands[1], 0)) 8612 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; 8613 else 8614 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; 8615 } 8616}" 8617 [(set_attr "type" "store,store,*,load,load") 8618 (set_attr "length" "*,16,16,*,16")]) 8619 8620(define_insn "*movti_string" 8621 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") 8622 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) 8623 (clobber (match_scratch:SI 2 "=X,X,X"))] 8624 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 8625 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" 8626 "* 8627{ 8628 switch (which_alternative) 8629 { 8630 default: 8631 abort (); 8632 8633 case 0: 8634 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; 8635 8636 case 1: 8637 /* Normally copy registers with lowest numbered register copied first. 8638 But copy in the other order if the first register of the output 8639 is the second, third, or fourth register in the input. */ 8640 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 8641 && REGNO (operands[0]) <= REGNO (operands[1]) + 3) 8642 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; 8643 else 8644 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; 8645 case 2: 8646 /* If the address register is the same as the register for the lowest- 8647 addressed word, load it last. Similarly for the next two words. 8648 Otherwise load lowest address to highest. */ 8649 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8650 operands[1], 0)) 8651 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; 8652 else if (refers_to_regno_p (REGNO (operands[0]) + 1, 8653 REGNO (operands[0]) + 2, operands[1], 0)) 8654 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; 8655 else if (refers_to_regno_p (REGNO (operands[0]) + 2, 8656 REGNO (operands[0]) + 3, operands[1], 0)) 8657 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; 8658 else 8659 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; 8660 } 8661}" 8662 [(set_attr "type" "store,*,load") 8663 (set_attr "length" "16,16,16")]) 8664 8665(define_insn "*movti_ppc64" 8666 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") 8667 (match_operand:TI 1 "input_operand" "r,m,r"))] 8668 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) 8669 || gpc_reg_operand (operands[1], TImode))" 8670 "* 8671{ 8672 switch (which_alternative) 8673 { 8674 default: 8675 abort (); 8676 case 0: 8677 /* We normally copy the low-numbered register first. However, if 8678 the first register operand 0 is the same as the second register of 8679 operand 1, we must copy in the opposite order. */ 8680 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 8681 return \"mr %L0,%L1\;mr %0,%1\"; 8682 else 8683 return \"mr %0,%1\;mr %L0,%L1\"; 8684 case 1: 8685 /* If the low-address word is used in the address, we must load it 8686 last. Otherwise, load it first. Note that we cannot have 8687 auto-increment in that case since the address register is known to be 8688 dead. */ 8689 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 8690 operands[1], 0)) 8691 return \"ld %L0,%L1\;ld %0,%1\"; 8692 else 8693 return \"ld%U1 %0,%1\;ld %L0,%L1\"; 8694 case 2: 8695 return \"std%U0 %1,%0\;std %L1,%L0\"; 8696 } 8697}" 8698 [(set_attr "type" "*,load,store") 8699 (set_attr "length" "8,8,8")]) 8700 8701(define_expand "load_multiple" 8702 [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 8703 (match_operand:SI 1 "" "")) 8704 (use (match_operand:SI 2 "" ""))])] 8705 "TARGET_STRING && !TARGET_POWERPC64" 8706 " 8707{ 8708 int regno; 8709 int count; 8710 rtx op1; 8711 int i; 8712 8713 /* Support only loading a constant number of fixed-point registers from 8714 memory and only bother with this if more than two; the machine 8715 doesn't support more than eight. */ 8716 if (GET_CODE (operands[2]) != CONST_INT 8717 || INTVAL (operands[2]) <= 2 8718 || INTVAL (operands[2]) > 8 8719 || GET_CODE (operands[1]) != MEM 8720 || GET_CODE (operands[0]) != REG 8721 || REGNO (operands[0]) >= 32) 8722 FAIL; 8723 8724 count = INTVAL (operands[2]); 8725 regno = REGNO (operands[0]); 8726 8727 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 8728 op1 = replace_equiv_address (operands[1], 8729 force_reg (SImode, XEXP (operands[1], 0))); 8730 8731 for (i = 0; i < count; i++) 8732 XVECEXP (operands[3], 0, i) 8733 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), 8734 adjust_address (op1, SImode, i * 4)); 8735}") 8736 8737(define_insn "" 8738 [(match_parallel 0 "load_multiple_operation" 8739 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 8740 (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] 8741 "TARGET_STRING" 8742 "* 8743{ 8744 /* We have to handle the case where the pseudo used to contain the address 8745 is assigned to one of the output registers. */ 8746 int i, j; 8747 int words = XVECLEN (operands[0], 0); 8748 rtx xop[10]; 8749 8750 if (XVECLEN (operands[0], 0) == 1) 8751 return \"{l|lwz} %1,0(%2)\"; 8752 8753 for (i = 0; i < words; i++) 8754 if (refers_to_regno_p (REGNO (operands[1]) + i, 8755 REGNO (operands[1]) + i + 1, operands[2], 0)) 8756 { 8757 if (i == words-1) 8758 { 8759 xop[0] = operands[1]; 8760 xop[1] = operands[2]; 8761 xop[2] = GEN_INT (4 * (words-1)); 8762 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); 8763 return \"\"; 8764 } 8765 else if (i == 0) 8766 { 8767 xop[0] = operands[1]; 8768 xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 8769 xop[2] = GEN_INT (4 * (words-1)); 8770 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); 8771 return \"\"; 8772 } 8773 else 8774 { 8775 for (j = 0; j < words; j++) 8776 if (j != i) 8777 { 8778 xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); 8779 xop[1] = operands[2]; 8780 xop[2] = GEN_INT (j * 4); 8781 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); 8782 } 8783 xop[0] = operands[2]; 8784 xop[1] = GEN_INT (i * 4); 8785 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); 8786 return \"\"; 8787 } 8788 } 8789 8790 return \"{lsi|lswi} %1,%2,%N0\"; 8791}" 8792 [(set_attr "type" "load") 8793 (set_attr "length" "32")]) 8794 8795 8796(define_expand "store_multiple" 8797 [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 8798 (match_operand:SI 1 "" "")) 8799 (clobber (scratch:SI)) 8800 (use (match_operand:SI 2 "" ""))])] 8801 "TARGET_STRING && !TARGET_POWERPC64" 8802 " 8803{ 8804 int regno; 8805 int count; 8806 rtx to; 8807 rtx op0; 8808 int i; 8809 8810 /* Support only storing a constant number of fixed-point registers to 8811 memory and only bother with this if more than two; the machine 8812 doesn't support more than eight. */ 8813 if (GET_CODE (operands[2]) != CONST_INT 8814 || INTVAL (operands[2]) <= 2 8815 || INTVAL (operands[2]) > 8 8816 || GET_CODE (operands[0]) != MEM 8817 || GET_CODE (operands[1]) != REG 8818 || REGNO (operands[1]) >= 32) 8819 FAIL; 8820 8821 count = INTVAL (operands[2]); 8822 regno = REGNO (operands[1]); 8823 8824 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); 8825 to = force_reg (SImode, XEXP (operands[0], 0)); 8826 op0 = replace_equiv_address (operands[0], to); 8827 8828 XVECEXP (operands[3], 0, 0) 8829 = gen_rtx_SET (VOIDmode, adjust_address (op0, SImode, 0), operands[1]); 8830 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, 8831 gen_rtx_SCRATCH (SImode)); 8832 8833 for (i = 1; i < count; i++) 8834 XVECEXP (operands[3], 0, i + 1) 8835 = gen_rtx_SET (VOIDmode, 8836 adjust_address (op0, SImode, i * 4), 8837 gen_rtx_REG (SImode, regno + i)); 8838}") 8839 8840(define_insn "" 8841 [(match_parallel 0 "store_multiple_operation" 8842 [(set (match_operand:SI 1 "indirect_operand" "=Q") 8843 (match_operand:SI 2 "gpc_reg_operand" "r")) 8844 (clobber (match_scratch:SI 3 "=q"))])] 8845 "TARGET_STRING && TARGET_POWER" 8846 "{stsi|stswi} %2,%P1,%O0" 8847 [(set_attr "type" "store")]) 8848 8849(define_insn "" 8850 [(match_parallel 0 "store_multiple_operation" 8851 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 8852 (match_operand:SI 2 "gpc_reg_operand" "r")) 8853 (clobber (match_scratch:SI 3 "X"))])] 8854 "TARGET_STRING && ! TARGET_POWER" 8855 "{stsi|stswi} %2,%1,%O0" 8856 [(set_attr "type" "store")]) 8857 8858 8859;; String/block move insn. 8860;; Argument 0 is the destination 8861;; Argument 1 is the source 8862;; Argument 2 is the length 8863;; Argument 3 is the alignment 8864 8865(define_expand "movstrsi" 8866 [(parallel [(set (match_operand:BLK 0 "" "") 8867 (match_operand:BLK 1 "" "")) 8868 (use (match_operand:SI 2 "" "")) 8869 (use (match_operand:SI 3 "" ""))])] 8870 "" 8871 " 8872{ 8873 if (expand_block_move (operands)) 8874 DONE; 8875 else 8876 FAIL; 8877}") 8878 8879;; Move up to 32 bytes at a time. The fixed registers are needed because the 8880;; register allocator doesn't have a clue about allocating 8 word registers. 8881;; rD/rS = r5 is preferred, efficient form. 8882(define_expand "movstrsi_8reg" 8883 [(parallel [(set (match_operand 0 "" "") 8884 (match_operand 1 "" "")) 8885 (use (match_operand 2 "" "")) 8886 (use (match_operand 3 "" "")) 8887 (clobber (reg:SI 5)) 8888 (clobber (reg:SI 6)) 8889 (clobber (reg:SI 7)) 8890 (clobber (reg:SI 8)) 8891 (clobber (reg:SI 9)) 8892 (clobber (reg:SI 10)) 8893 (clobber (reg:SI 11)) 8894 (clobber (reg:SI 12)) 8895 (clobber (match_scratch:SI 4 ""))])] 8896 "TARGET_STRING" 8897 "") 8898 8899(define_insn "" 8900 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 8901 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 8902 (use (match_operand:SI 2 "immediate_operand" "i")) 8903 (use (match_operand:SI 3 "immediate_operand" "i")) 8904 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 8905 (clobber (reg:SI 6)) 8906 (clobber (reg:SI 7)) 8907 (clobber (reg:SI 8)) 8908 (clobber (reg:SI 9)) 8909 (clobber (reg:SI 10)) 8910 (clobber (reg:SI 11)) 8911 (clobber (reg:SI 12)) 8912 (clobber (match_scratch:SI 5 "=q"))] 8913 "TARGET_STRING && TARGET_POWER 8914 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) 8915 || INTVAL (operands[2]) == 0) 8916 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 8917 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 8918 && REGNO (operands[4]) == 5" 8919 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 8920 [(set_attr "type" "load") 8921 (set_attr "length" "8")]) 8922 8923(define_insn "" 8924 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 8925 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 8926 (use (match_operand:SI 2 "immediate_operand" "i")) 8927 (use (match_operand:SI 3 "immediate_operand" "i")) 8928 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 8929 (clobber (reg:SI 6)) 8930 (clobber (reg:SI 7)) 8931 (clobber (reg:SI 8)) 8932 (clobber (reg:SI 9)) 8933 (clobber (reg:SI 10)) 8934 (clobber (reg:SI 11)) 8935 (clobber (reg:SI 12)) 8936 (clobber (match_scratch:SI 5 "X"))] 8937 "TARGET_STRING && ! TARGET_POWER 8938 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) 8939 || INTVAL (operands[2]) == 0) 8940 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 8941 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 8942 && REGNO (operands[4]) == 5" 8943 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 8944 [(set_attr "type" "load") 8945 (set_attr "length" "8")]) 8946 8947(define_insn "" 8948 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) 8949 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) 8950 (use (match_operand:SI 2 "immediate_operand" "i")) 8951 (use (match_operand:SI 3 "immediate_operand" "i")) 8952 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 8953 (clobber (reg:SI 6)) 8954 (clobber (reg:SI 7)) 8955 (clobber (reg:SI 8)) 8956 (clobber (reg:SI 9)) 8957 (clobber (reg:SI 10)) 8958 (clobber (reg:SI 11)) 8959 (clobber (reg:SI 12)) 8960 (clobber (match_scratch:SI 5 "X"))] 8961 "TARGET_STRING && TARGET_POWERPC64 8962 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) 8963 || INTVAL (operands[2]) == 0) 8964 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 8965 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 8966 && REGNO (operands[4]) == 5" 8967 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 8968 [(set_attr "type" "load") 8969 (set_attr "length" "8")]) 8970 8971;; Move up to 24 bytes at a time. The fixed registers are needed because the 8972;; register allocator doesn't have a clue about allocating 6 word registers. 8973;; rD/rS = r5 is preferred, efficient form. 8974(define_expand "movstrsi_6reg" 8975 [(parallel [(set (match_operand 0 "" "") 8976 (match_operand 1 "" "")) 8977 (use (match_operand 2 "" "")) 8978 (use (match_operand 3 "" "")) 8979 (clobber (reg:SI 5)) 8980 (clobber (reg:SI 6)) 8981 (clobber (reg:SI 7)) 8982 (clobber (reg:SI 8)) 8983 (clobber (reg:SI 9)) 8984 (clobber (reg:SI 10)) 8985 (clobber (match_scratch:SI 4 ""))])] 8986 "TARGET_STRING" 8987 "") 8988 8989(define_insn "" 8990 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 8991 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 8992 (use (match_operand:SI 2 "immediate_operand" "i")) 8993 (use (match_operand:SI 3 "immediate_operand" "i")) 8994 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 8995 (clobber (reg:SI 6)) 8996 (clobber (reg:SI 7)) 8997 (clobber (reg:SI 8)) 8998 (clobber (reg:SI 9)) 8999 (clobber (reg:SI 10)) 9000 (clobber (match_scratch:SI 5 "=q"))] 9001 "TARGET_STRING && TARGET_POWER 9002 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 9003 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) 9004 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) 9005 && REGNO (operands[4]) == 5" 9006 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9007 [(set_attr "type" "load") 9008 (set_attr "length" "8")]) 9009 9010(define_insn "" 9011 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9012 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9013 (use (match_operand:SI 2 "immediate_operand" "i")) 9014 (use (match_operand:SI 3 "immediate_operand" "i")) 9015 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9016 (clobber (reg:SI 6)) 9017 (clobber (reg:SI 7)) 9018 (clobber (reg:SI 8)) 9019 (clobber (reg:SI 9)) 9020 (clobber (reg:SI 10)) 9021 (clobber (match_scratch:SI 5 "X"))] 9022 "TARGET_STRING && ! TARGET_POWER 9023 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 9024 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) 9025 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) 9026 && REGNO (operands[4]) == 5" 9027 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9028 [(set_attr "type" "load") 9029 (set_attr "length" "8")]) 9030 9031(define_insn "" 9032 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) 9033 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) 9034 (use (match_operand:SI 2 "immediate_operand" "i")) 9035 (use (match_operand:SI 3 "immediate_operand" "i")) 9036 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9037 (clobber (reg:SI 6)) 9038 (clobber (reg:SI 7)) 9039 (clobber (reg:SI 8)) 9040 (clobber (reg:SI 9)) 9041 (clobber (reg:SI 10)) 9042 (clobber (match_scratch:SI 5 "X"))] 9043 "TARGET_STRING && TARGET_POWERPC64 9044 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 9045 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) 9046 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) 9047 && REGNO (operands[4]) == 5" 9048 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9049 [(set_attr "type" "load") 9050 (set_attr "length" "8")]) 9051 9052;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill 9053;; problems with TImode. 9054;; rD/rS = r5 is preferred, efficient form. 9055(define_expand "movstrsi_4reg" 9056 [(parallel [(set (match_operand 0 "" "") 9057 (match_operand 1 "" "")) 9058 (use (match_operand 2 "" "")) 9059 (use (match_operand 3 "" "")) 9060 (clobber (reg:SI 5)) 9061 (clobber (reg:SI 6)) 9062 (clobber (reg:SI 7)) 9063 (clobber (reg:SI 8)) 9064 (clobber (match_scratch:SI 4 ""))])] 9065 "TARGET_STRING" 9066 "") 9067 9068(define_insn "" 9069 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9070 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9071 (use (match_operand:SI 2 "immediate_operand" "i")) 9072 (use (match_operand:SI 3 "immediate_operand" "i")) 9073 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9074 (clobber (reg:SI 6)) 9075 (clobber (reg:SI 7)) 9076 (clobber (reg:SI 8)) 9077 (clobber (match_scratch:SI 5 "=q"))] 9078 "TARGET_STRING && TARGET_POWER 9079 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 9080 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) 9081 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) 9082 && REGNO (operands[4]) == 5" 9083 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9084 [(set_attr "type" "load") 9085 (set_attr "length" "8")]) 9086 9087(define_insn "" 9088 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9089 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9090 (use (match_operand:SI 2 "immediate_operand" "i")) 9091 (use (match_operand:SI 3 "immediate_operand" "i")) 9092 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9093 (clobber (reg:SI 6)) 9094 (clobber (reg:SI 7)) 9095 (clobber (reg:SI 8)) 9096 (clobber (match_scratch:SI 5 "X"))] 9097 "TARGET_STRING && ! TARGET_POWER 9098 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 9099 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) 9100 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) 9101 && REGNO (operands[4]) == 5" 9102 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9103 [(set_attr "type" "load") 9104 (set_attr "length" "8")]) 9105 9106(define_insn "" 9107 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) 9108 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) 9109 (use (match_operand:SI 2 "immediate_operand" "i")) 9110 (use (match_operand:SI 3 "immediate_operand" "i")) 9111 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) 9112 (clobber (reg:SI 6)) 9113 (clobber (reg:SI 7)) 9114 (clobber (reg:SI 8)) 9115 (clobber (match_scratch:SI 5 "X"))] 9116 "TARGET_STRING && TARGET_POWERPC64 9117 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 9118 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) 9119 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) 9120 && REGNO (operands[4]) == 5" 9121 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9122 [(set_attr "type" "load") 9123 (set_attr "length" "8")]) 9124 9125;; Move up to 8 bytes at a time. 9126(define_expand "movstrsi_2reg" 9127 [(parallel [(set (match_operand 0 "" "") 9128 (match_operand 1 "" "")) 9129 (use (match_operand 2 "" "")) 9130 (use (match_operand 3 "" "")) 9131 (clobber (match_scratch:DI 4 "")) 9132 (clobber (match_scratch:SI 5 ""))])] 9133 "TARGET_STRING && ! TARGET_POWERPC64" 9134 "") 9135 9136(define_insn "" 9137 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9138 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9139 (use (match_operand:SI 2 "immediate_operand" "i")) 9140 (use (match_operand:SI 3 "immediate_operand" "i")) 9141 (clobber (match_scratch:DI 4 "=&r")) 9142 (clobber (match_scratch:SI 5 "=q"))] 9143 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 9144 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" 9145 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9146 [(set_attr "type" "load") 9147 (set_attr "length" "8")]) 9148 9149(define_insn "" 9150 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9151 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9152 (use (match_operand:SI 2 "immediate_operand" "i")) 9153 (use (match_operand:SI 3 "immediate_operand" "i")) 9154 (clobber (match_scratch:DI 4 "=&r")) 9155 (clobber (match_scratch:SI 5 "X"))] 9156 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 9157 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" 9158 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9159 [(set_attr "type" "load") 9160 (set_attr "length" "8")]) 9161 9162;; Move up to 4 bytes at a time. 9163(define_expand "movstrsi_1reg" 9164 [(parallel [(set (match_operand 0 "" "") 9165 (match_operand 1 "" "")) 9166 (use (match_operand 2 "" "")) 9167 (use (match_operand 3 "" "")) 9168 (clobber (match_scratch:SI 4 "")) 9169 (clobber (match_scratch:SI 5 ""))])] 9170 "TARGET_STRING" 9171 "") 9172 9173(define_insn "" 9174 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9175 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9176 (use (match_operand:SI 2 "immediate_operand" "i")) 9177 (use (match_operand:SI 3 "immediate_operand" "i")) 9178 (clobber (match_scratch:SI 4 "=&r")) 9179 (clobber (match_scratch:SI 5 "=q"))] 9180 "TARGET_STRING && TARGET_POWER 9181 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 9182 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9183 [(set_attr "type" "load") 9184 (set_attr "length" "8")]) 9185 9186(define_insn "" 9187 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 9188 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 9189 (use (match_operand:SI 2 "immediate_operand" "i")) 9190 (use (match_operand:SI 3 "immediate_operand" "i")) 9191 (clobber (match_scratch:SI 4 "=&r")) 9192 (clobber (match_scratch:SI 5 "X"))] 9193 "TARGET_STRING && ! TARGET_POWER 9194 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 9195 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9196 [(set_attr "type" "load") 9197 (set_attr "length" "8")]) 9198 9199(define_insn "" 9200 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) 9201 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) 9202 (use (match_operand:SI 2 "immediate_operand" "i")) 9203 (use (match_operand:SI 3 "immediate_operand" "i")) 9204 (clobber (match_scratch:SI 4 "=&r")) 9205 (clobber (match_scratch:SI 5 "X"))] 9206 "TARGET_STRING && TARGET_POWERPC64 9207 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 9208 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" 9209 [(set_attr "type" "load") 9210 (set_attr "length" "8")]) 9211 9212 9213;; Define insns that do load or store with update. Some of these we can 9214;; get by using pre-decrement or pre-increment, but the hardware can also 9215;; do cases where the increment is not the size of the object. 9216;; 9217;; In all these cases, we use operands 0 and 1 for the register being 9218;; incremented because those are the operands that local-alloc will 9219;; tie and these are the pair most likely to be tieable (and the ones 9220;; that will benefit the most). 9221 9222(define_insn "*movdi_update1" 9223 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") 9224 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 9225 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) 9226 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 9227 (plus:DI (match_dup 1) (match_dup 2)))] 9228 "TARGET_POWERPC64 && TARGET_UPDATE" 9229 "@ 9230 ldux %3,%0,%2 9231 ldu %3,%2(%0)" 9232 [(set_attr "type" "load")]) 9233 9234(define_insn "*movdi_update2" 9235 [(set (match_operand:DI 3 "gpc_reg_operand" "=r") 9236 (sign_extend:DI 9237 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") 9238 (match_operand:DI 2 "gpc_reg_operand" "r"))))) 9239 (set (match_operand:DI 0 "gpc_reg_operand" "=b") 9240 (plus:DI (match_dup 1) (match_dup 2)))] 9241 "TARGET_POWERPC64" 9242 "lwaux %3,%0,%2" 9243 [(set_attr "type" "load")]) 9244 9245(define_insn "movdi_update" 9246 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 9247 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))) 9248 (match_operand:DI 3 "gpc_reg_operand" "r,r")) 9249 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 9250 (plus:DI (match_dup 1) (match_dup 2)))] 9251 "TARGET_POWERPC64 && TARGET_UPDATE" 9252 "@ 9253 stdux %3,%0,%2 9254 stdu %3,%2(%0)" 9255 [(set_attr "type" "store")]) 9256 9257(define_insn "*movsi_update1" 9258 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9259 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9260 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9261 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9262 (plus:SI (match_dup 1) (match_dup 2)))] 9263 "" 9264 "@ 9265 {lux|lwzux} %3,%0,%2 9266 {lu|lwzu} %3,%2(%0)" 9267 [(set_attr "type" "load")]) 9268 9269(define_insn "movsi_update" 9270 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9271 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9272 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 9273 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9274 (plus:SI (match_dup 1) (match_dup 2)))] 9275 "TARGET_UPDATE" 9276 "@ 9277 {stux|stwux} %3,%0,%2 9278 {stu|stwu} %3,%2(%0)" 9279 [(set_attr "type" "store")]) 9280 9281(define_insn "*movhi_update" 9282 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") 9283 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9284 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9285 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9286 (plus:SI (match_dup 1) (match_dup 2)))] 9287 "TARGET_UPDATE" 9288 "@ 9289 lhzux %3,%0,%2 9290 lhzu %3,%2(%0)" 9291 [(set_attr "type" "load")]) 9292 9293(define_insn "*movhi_update2" 9294 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9295 (zero_extend:SI 9296 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9297 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 9298 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9299 (plus:SI (match_dup 1) (match_dup 2)))] 9300 "TARGET_UPDATE" 9301 "@ 9302 lhzux %3,%0,%2 9303 lhzu %3,%2(%0)" 9304 [(set_attr "type" "load")]) 9305 9306(define_insn "*movhi_update3" 9307 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9308 (sign_extend:SI 9309 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9310 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 9311 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9312 (plus:SI (match_dup 1) (match_dup 2)))] 9313 "TARGET_UPDATE" 9314 "@ 9315 lhaux %3,%0,%2 9316 lhau %3,%2(%0)" 9317 [(set_attr "type" "load")]) 9318 9319(define_insn "*movhi_update4" 9320 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9321 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9322 (match_operand:HI 3 "gpc_reg_operand" "r,r")) 9323 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9324 (plus:SI (match_dup 1) (match_dup 2)))] 9325 "TARGET_UPDATE" 9326 "@ 9327 sthux %3,%0,%2 9328 sthu %3,%2(%0)" 9329 [(set_attr "type" "store")]) 9330 9331(define_insn "*movqi_update1" 9332 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") 9333 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9334 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9335 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9336 (plus:SI (match_dup 1) (match_dup 2)))] 9337 "TARGET_UPDATE" 9338 "@ 9339 lbzux %3,%0,%2 9340 lbzu %3,%2(%0)" 9341 [(set_attr "type" "load")]) 9342 9343(define_insn "*movqi_update2" 9344 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 9345 (zero_extend:SI 9346 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9347 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 9348 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9349 (plus:SI (match_dup 1) (match_dup 2)))] 9350 "TARGET_UPDATE" 9351 "@ 9352 lbzux %3,%0,%2 9353 lbzu %3,%2(%0)" 9354 [(set_attr "type" "load")]) 9355 9356(define_insn "*movqi_update3" 9357 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9358 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9359 (match_operand:QI 3 "gpc_reg_operand" "r,r")) 9360 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9361 (plus:SI (match_dup 1) (match_dup 2)))] 9362 "TARGET_UPDATE" 9363 "@ 9364 stbux %3,%0,%2 9365 stbu %3,%2(%0)" 9366 [(set_attr "type" "store")]) 9367 9368(define_insn "*movsf_update1" 9369 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") 9370 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9371 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9372 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9373 (plus:SI (match_dup 1) (match_dup 2)))] 9374 "TARGET_HARD_FLOAT && TARGET_UPDATE" 9375 "@ 9376 lfsux %3,%0,%2 9377 lfsu %3,%2(%0)" 9378 [(set_attr "type" "fpload")]) 9379 9380(define_insn "*movsf_update2" 9381 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9382 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9383 (match_operand:SF 3 "gpc_reg_operand" "f,f")) 9384 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9385 (plus:SI (match_dup 1) (match_dup 2)))] 9386 "TARGET_HARD_FLOAT && TARGET_UPDATE" 9387 "@ 9388 stfsux %3,%0,%2 9389 stfsu %3,%2(%0)" 9390 [(set_attr "type" "fpstore")]) 9391 9392(define_insn "*movsf_update3" 9393 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") 9394 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9395 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9396 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9397 (plus:SI (match_dup 1) (match_dup 2)))] 9398 "TARGET_SOFT_FLOAT && TARGET_UPDATE" 9399 "@ 9400 {lux|lwzux} %3,%0,%2 9401 {lu|lwzu} %3,%2(%0)" 9402 [(set_attr "type" "load")]) 9403 9404(define_insn "*movsf_update4" 9405 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9406 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9407 (match_operand:SF 3 "gpc_reg_operand" "r,r")) 9408 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9409 (plus:SI (match_dup 1) (match_dup 2)))] 9410 "TARGET_SOFT_FLOAT && TARGET_UPDATE" 9411 "@ 9412 {stux|stwux} %3,%0,%2 9413 {stu|stwu} %3,%2(%0)" 9414 [(set_attr "type" "store")]) 9415 9416(define_insn "*movdf_update1" 9417 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") 9418 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9419 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 9420 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9421 (plus:SI (match_dup 1) (match_dup 2)))] 9422 "TARGET_HARD_FLOAT && TARGET_UPDATE" 9423 "@ 9424 lfdux %3,%0,%2 9425 lfdu %3,%2(%0)" 9426 [(set_attr "type" "fpload")]) 9427 9428(define_insn "*movdf_update2" 9429 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 9430 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 9431 (match_operand:DF 3 "gpc_reg_operand" "f,f")) 9432 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 9433 (plus:SI (match_dup 1) (match_dup 2)))] 9434 "TARGET_HARD_FLOAT && TARGET_UPDATE" 9435 "@ 9436 stfdux %3,%0,%2 9437 stfdu %3,%2(%0)" 9438 [(set_attr "type" "fpstore")]) 9439 9440;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. 9441 9442(define_peephole 9443 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 9444 (match_operand:DF 1 "memory_operand" "")) 9445 (set (match_operand:DF 2 "gpc_reg_operand" "=f") 9446 (match_operand:DF 3 "memory_operand" ""))] 9447 "TARGET_POWER2 9448 && TARGET_HARD_FLOAT 9449 && registers_ok_for_quad_peep (operands[0], operands[2]) 9450 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) 9451 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" 9452 "lfq%U1%X1 %0,%1") 9453 9454(define_peephole 9455 [(set (match_operand:DF 0 "memory_operand" "") 9456 (match_operand:DF 1 "gpc_reg_operand" "f")) 9457 (set (match_operand:DF 2 "memory_operand" "") 9458 (match_operand:DF 3 "gpc_reg_operand" "f"))] 9459 "TARGET_POWER2 9460 && TARGET_HARD_FLOAT 9461 && registers_ok_for_quad_peep (operands[1], operands[3]) 9462 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) 9463 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" 9464 "stfq%U0%X0 %1,%0") 9465 9466;; Next come insns related to the calling sequence. 9467;; 9468;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). 9469;; We move the back-chain and decrement the stack pointer. 9470 9471(define_expand "allocate_stack" 9472 [(set (match_operand 0 "gpc_reg_operand" "=r") 9473 (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) 9474 (set (reg 1) 9475 (minus (reg 1) (match_dup 1)))] 9476 "" 9477 " 9478{ rtx chain = gen_reg_rtx (Pmode); 9479 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); 9480 rtx neg_op0; 9481 9482 emit_move_insn (chain, stack_bot); 9483 9484 /* Check stack bounds if necessary. */ 9485 if (current_function_limit_stack) 9486 { 9487 rtx available; 9488 available = expand_binop (Pmode, sub_optab, 9489 stack_pointer_rtx, stack_limit_rtx, 9490 NULL_RTX, 1, OPTAB_WIDEN); 9491 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); 9492 } 9493 9494 if (GET_CODE (operands[1]) != CONST_INT 9495 || INTVAL (operands[1]) < -32767 9496 || INTVAL (operands[1]) > 32768) 9497 { 9498 neg_op0 = gen_reg_rtx (Pmode); 9499 if (TARGET_32BIT) 9500 emit_insn (gen_negsi2 (neg_op0, operands[1])); 9501 else 9502 emit_insn (gen_negdi2 (neg_op0, operands[1])); 9503 } 9504 else 9505 neg_op0 = GEN_INT (- INTVAL (operands[1])); 9506 9507 if (TARGET_UPDATE) 9508 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) 9509 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); 9510 9511 else 9512 { 9513 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) 9514 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); 9515 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); 9516 } 9517 9518 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 9519 DONE; 9520}") 9521 9522;; These patterns say how to save and restore the stack pointer. We need not 9523;; save the stack pointer at function level since we are careful to 9524;; preserve the backchain. At block level, we have to restore the backchain 9525;; when we restore the stack pointer. 9526;; 9527;; For nonlocal gotos, we must save both the stack pointer and its 9528;; backchain and restore both. Note that in the nonlocal case, the 9529;; save area is a memory location. 9530 9531(define_expand "save_stack_function" 9532 [(match_operand 0 "any_operand" "") 9533 (match_operand 1 "any_operand" "")] 9534 "" 9535 "DONE;") 9536 9537(define_expand "restore_stack_function" 9538 [(match_operand 0 "any_operand" "") 9539 (match_operand 1 "any_operand" "")] 9540 "" 9541 "DONE;") 9542 9543(define_expand "restore_stack_block" 9544 [(use (match_operand 0 "register_operand" "")) 9545 (set (match_dup 2) (match_dup 3)) 9546 (set (match_dup 0) (match_operand 1 "register_operand" "")) 9547 (set (match_dup 3) (match_dup 2))] 9548 "" 9549 " 9550{ 9551 operands[2] = gen_reg_rtx (Pmode); 9552 operands[3] = gen_rtx_MEM (Pmode, operands[0]); 9553}") 9554 9555(define_expand "save_stack_nonlocal" 9556 [(match_operand 0 "memory_operand" "") 9557 (match_operand 1 "register_operand" "")] 9558 "" 9559 " 9560{ 9561 rtx temp = gen_reg_rtx (Pmode); 9562 9563 /* Copy the backchain to the first word, sp to the second. */ 9564 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); 9565 emit_move_insn (operand_subword (operands[0], 0, 0, 9566 (TARGET_32BIT ? DImode : TImode)), 9567 temp); 9568 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), 9569 operands[1]); 9570 DONE; 9571}") 9572 9573(define_expand "restore_stack_nonlocal" 9574 [(match_operand 0 "register_operand" "") 9575 (match_operand 1 "memory_operand" "")] 9576 "" 9577 " 9578{ 9579 rtx temp = gen_reg_rtx (Pmode); 9580 9581 /* Restore the backchain from the first word, sp from the second. */ 9582 emit_move_insn (temp, 9583 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); 9584 emit_move_insn (operands[0], 9585 operand_subword (operands[1], 1, 0, 9586 (TARGET_32BIT ? DImode : TImode))); 9587 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); 9588 DONE; 9589}") 9590 9591;; TOC register handling. 9592 9593;; Code to initialize the TOC register... 9594 9595(define_insn "load_toc_aix_si" 9596 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9597 (unspec:SI [(const_int 0)] 7)) 9598 (use (reg:SI 2))])] 9599 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" 9600 "* 9601{ 9602 char buf[30]; 9603 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); 9604 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 9605 operands[2] = gen_rtx_REG (Pmode, 2); 9606 return \"{l|lwz} %0,%1(%2)\"; 9607}" 9608 [(set_attr "type" "load")]) 9609 9610(define_insn "load_toc_aix_di" 9611 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 9612 (unspec:DI [(const_int 0)] 7)) 9613 (use (reg:DI 2))])] 9614 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" 9615 "* 9616{ 9617 char buf[30]; 9618#ifdef TARGET_RELOCATABLE 9619 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 9620 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); 9621#else 9622 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); 9623#endif 9624 if (TARGET_ELF) 9625 strcat (buf, \"@toc\"); 9626 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 9627 operands[2] = gen_rtx_REG (Pmode, 2); 9628 return \"ld %0,%1(%2)\"; 9629}" 9630 [(set_attr "type" "load")]) 9631 9632(define_insn "load_toc_v4_pic_si" 9633 [(set (match_operand:SI 0 "register_operand" "=l") 9634 (unspec:SI [(const_int 0)] 7))] 9635 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" 9636 "bl _GLOBAL_OFFSET_TABLE_@local-4" 9637 [(set_attr "type" "branch") 9638 (set_attr "length" "4")]) 9639 9640(define_insn "load_toc_v4_PIC_1" 9641 [(set (match_operand:SI 0 "register_operand" "=l") 9642 (match_operand:SI 1 "immediate_operand" "s")) 9643 (unspec [(match_dup 1)] 7)] 9644 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" 9645 "bl %1\\n%1:" 9646 [(set_attr "type" "branch") 9647 (set_attr "length" "4")]) 9648 9649(define_insn "load_toc_v4_PIC_1b" 9650 [(set (match_operand:SI 0 "register_operand" "=l") 9651 (match_operand:SI 1 "immediate_operand" "s")) 9652 (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] 9653 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" 9654 "bl %1\\n\\t.long %2-%1+4\\n%1:" 9655 [(set_attr "type" "branch") 9656 (set_attr "length" "8")]) 9657 9658(define_insn "load_toc_v4_PIC_2" 9659 [(set (match_operand:SI 0 "register_operand" "=r") 9660 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "b") 9661 (minus:SI (match_operand:SI 2 "immediate_operand" "s") 9662 (match_operand:SI 3 "immediate_operand" "s")))))] 9663 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" 9664 "{l|lwz} %0,%2-%3(%1)" 9665 [(set_attr "type" "load")]) 9666 9667(define_insn "load_macho_picbase" 9668 [(set (match_operand:SI 0 "register_operand" "=l") 9669 (unspec:SI [(const_int 0)] 15))] 9670 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" 9671 "* 9672{ 9673#if TARGET_MACHO 9674 char *picbase = machopic_function_base_name (); 9675 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); 9676#endif 9677 return \"bcl 20,31,%1\\n%1:\"; 9678}" 9679 [(set_attr "type" "branch") 9680 (set_attr "length" "4")]) 9681 9682;; If the TOC is shared over a translation unit, as happens with all 9683;; the kinds of PIC that we support, we need to restore the TOC 9684;; pointer only when jumping over units of translation. 9685 9686(define_expand "builtin_setjmp_receiver" 9687 [(use (label_ref (match_operand 0 "" "")))] 9688 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) 9689 || (TARGET_TOC && TARGET_MINIMAL_TOC)" 9690 " 9691{ 9692 rs6000_emit_load_toc_table (FALSE); 9693 DONE; 9694}") 9695 9696;; A function pointer under AIX is a pointer to a data area whose first word 9697;; contains the actual address of the function, whose second word contains a 9698;; pointer to its TOC, and whose third word contains a value to place in the 9699;; static chain register (r11). Note that if we load the static chain, our 9700;; "trampoline" need not have any executable code. 9701 9702(define_expand "call_indirect_aix32" 9703 [(set (match_dup 2) 9704 (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) 9705 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) 9706 (reg:SI 2)) 9707 (set (reg:SI 2) 9708 (mem:SI (plus:SI (match_dup 0) 9709 (const_int 4)))) 9710 (set (reg:SI 11) 9711 (mem:SI (plus:SI (match_dup 0) 9712 (const_int 8)))) 9713 (parallel [(call (mem:SI (match_dup 2)) 9714 (match_operand 1 "" "")) 9715 (use (reg:SI 2)) 9716 (use (reg:SI 11)) 9717 (set (reg:SI 2) 9718 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 9719 (clobber (scratch:SI))])] 9720 "TARGET_32BIT" 9721 " 9722{ operands[2] = gen_reg_rtx (SImode); }") 9723 9724(define_expand "call_indirect_aix64" 9725 [(set (match_dup 2) 9726 (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) 9727 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) 9728 (reg:DI 2)) 9729 (set (reg:DI 2) 9730 (mem:DI (plus:DI (match_dup 0) 9731 (const_int 8)))) 9732 (set (reg:DI 11) 9733 (mem:DI (plus:DI (match_dup 0) 9734 (const_int 16)))) 9735 (parallel [(call (mem:SI (match_dup 2)) 9736 (match_operand 1 "" "")) 9737 (use (reg:DI 2)) 9738 (use (reg:DI 11)) 9739 (set (reg:DI 2) 9740 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 9741 (clobber (scratch:SI))])] 9742 "TARGET_64BIT" 9743 " 9744{ operands[2] = gen_reg_rtx (DImode); }") 9745 9746(define_expand "call_value_indirect_aix32" 9747 [(set (match_dup 3) 9748 (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 9749 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) 9750 (reg:SI 2)) 9751 (set (reg:SI 2) 9752 (mem:SI (plus:SI (match_dup 1) 9753 (const_int 4)))) 9754 (set (reg:SI 11) 9755 (mem:SI (plus:SI (match_dup 1) 9756 (const_int 8)))) 9757 (parallel [(set (match_operand 0 "" "") 9758 (call (mem:SI (match_dup 3)) 9759 (match_operand 2 "" ""))) 9760 (use (reg:SI 2)) 9761 (use (reg:SI 11)) 9762 (set (reg:SI 2) 9763 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 9764 (clobber (scratch:SI))])] 9765 "TARGET_32BIT" 9766 " 9767{ operands[3] = gen_reg_rtx (SImode); }") 9768 9769(define_expand "call_value_indirect_aix64" 9770 [(set (match_dup 3) 9771 (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 9772 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) 9773 (reg:DI 2)) 9774 (set (reg:DI 2) 9775 (mem:DI (plus:DI (match_dup 1) 9776 (const_int 8)))) 9777 (set (reg:DI 11) 9778 (mem:DI (plus:DI (match_dup 1) 9779 (const_int 16)))) 9780 (parallel [(set (match_operand 0 "" "") 9781 (call (mem:SI (match_dup 3)) 9782 (match_operand 2 "" ""))) 9783 (use (reg:DI 2)) 9784 (use (reg:DI 11)) 9785 (set (reg:DI 2) 9786 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 9787 (clobber (scratch:SI))])] 9788 "TARGET_64BIT" 9789 " 9790{ operands[3] = gen_reg_rtx (DImode); }") 9791 9792;; Now the definitions for the call and call_value insns 9793(define_expand "call" 9794 [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) 9795 (match_operand 1 "" "")) 9796 (use (match_operand 2 "" "")) 9797 (clobber (scratch:SI))])] 9798 "" 9799 " 9800{ 9801#if TARGET_MACHO 9802 if (flag_pic) 9803 operands[0] = machopic_indirect_call_target (operands[0]); 9804#endif 9805 9806 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) 9807 abort (); 9808 9809 operands[0] = XEXP (operands[0], 0); 9810 9811 if (GET_CODE (operands[0]) != SYMBOL_REF 9812 || (INTVAL (operands[2]) & CALL_LONG) != 0) 9813 { 9814 if (INTVAL (operands[2]) & CALL_LONG) 9815 operands[0] = rs6000_longcall_ref (operands[0]); 9816 9817 if (DEFAULT_ABI == ABI_V4 9818 || DEFAULT_ABI == ABI_AIX_NODESC 9819 || DEFAULT_ABI == ABI_DARWIN) 9820 operands[0] = force_reg (Pmode, operands[0]); 9821 9822 else if (DEFAULT_ABI == ABI_AIX) 9823 { 9824 /* AIX function pointers are really pointers to a three word 9825 area. */ 9826 emit_call_insn (TARGET_32BIT 9827 ? gen_call_indirect_aix32 (force_reg (SImode, 9828 operands[0]), 9829 operands[1]) 9830 : gen_call_indirect_aix64 (force_reg (DImode, 9831 operands[0]), 9832 operands[1])); 9833 DONE; 9834 } 9835 else 9836 abort (); 9837 } 9838}") 9839 9840(define_expand "call_value" 9841 [(parallel [(set (match_operand 0 "" "") 9842 (call (mem:SI (match_operand 1 "address_operand" "")) 9843 (match_operand 2 "" ""))) 9844 (use (match_operand 3 "" "")) 9845 (clobber (scratch:SI))])] 9846 "" 9847 " 9848{ 9849#if TARGET_MACHO 9850 if (flag_pic) 9851 operands[1] = machopic_indirect_call_target (operands[1]); 9852#endif 9853 9854 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) 9855 abort (); 9856 9857 operands[1] = XEXP (operands[1], 0); 9858 9859 if (GET_CODE (operands[1]) != SYMBOL_REF 9860 || (INTVAL (operands[3]) & CALL_LONG) != 0) 9861 { 9862 if (INTVAL (operands[3]) & CALL_LONG) 9863 operands[1] = rs6000_longcall_ref (operands[1]); 9864 9865 if (DEFAULT_ABI == ABI_V4 9866 || DEFAULT_ABI == ABI_AIX_NODESC 9867 || DEFAULT_ABI == ABI_DARWIN) 9868 operands[0] = force_reg (Pmode, operands[0]); 9869 9870 else if (DEFAULT_ABI == ABI_AIX) 9871 { 9872 /* AIX function pointers are really pointers to a three word 9873 area. */ 9874 emit_call_insn (TARGET_32BIT 9875 ? gen_call_value_indirect_aix32 (operands[0], 9876 force_reg (SImode, 9877 operands[1]), 9878 operands[2]) 9879 : gen_call_value_indirect_aix64 (operands[0], 9880 force_reg (DImode, 9881 operands[1]), 9882 operands[2])); 9883 DONE; 9884 } 9885 else 9886 abort (); 9887 } 9888}") 9889 9890;; Call to function in current module. No TOC pointer reload needed. 9891;; Operand2 is non-zero if we are using the V.4 calling sequence and 9892;; either the function was not prototyped, or it was prototyped as a 9893;; variable argument function. It is > 0 if FP registers were passed 9894;; and < 0 if they were not. 9895 9896(define_insn "*call_local32" 9897 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) 9898 (match_operand 1 "" "g,g")) 9899 (use (match_operand:SI 2 "immediate_operand" "O,n")) 9900 (clobber (match_scratch:SI 3 "=l,l"))] 9901 "(INTVAL (operands[2]) & CALL_LONG) == 0" 9902 "* 9903{ 9904 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 9905 output_asm_insn (\"crxor 6,6,6\", operands); 9906 9907 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 9908 output_asm_insn (\"creqv 6,6,6\", operands); 9909 9910 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; 9911}" 9912 [(set_attr "type" "branch") 9913 (set_attr "length" "4,8")]) 9914 9915(define_insn "*call_local64" 9916 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) 9917 (match_operand 1 "" "g,g")) 9918 (use (match_operand:SI 2 "immediate_operand" "O,n")) 9919 (clobber (match_scratch:SI 3 "=l,l"))] 9920 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" 9921 "* 9922{ 9923 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 9924 output_asm_insn (\"crxor 6,6,6\", operands); 9925 9926 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 9927 output_asm_insn (\"creqv 6,6,6\", operands); 9928 9929 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; 9930}" 9931 [(set_attr "type" "branch") 9932 (set_attr "length" "4,8")]) 9933 9934(define_insn "*call_value_local32" 9935 [(set (match_operand 0 "" "") 9936 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) 9937 (match_operand 2 "" "g,g"))) 9938 (use (match_operand:SI 3 "immediate_operand" "O,n")) 9939 (clobber (match_scratch:SI 4 "=l,l"))] 9940 "(INTVAL (operands[3]) & CALL_LONG) == 0" 9941 "* 9942{ 9943 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 9944 output_asm_insn (\"crxor 6,6,6\", operands); 9945 9946 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 9947 output_asm_insn (\"creqv 6,6,6\", operands); 9948 9949 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; 9950}" 9951 [(set_attr "type" "branch") 9952 (set_attr "length" "4,8")]) 9953 9954 9955(define_insn "*call_value_local64" 9956 [(set (match_operand 0 "" "") 9957 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) 9958 (match_operand 2 "" "g,g"))) 9959 (use (match_operand:SI 3 "immediate_operand" "O,n")) 9960 (clobber (match_scratch:SI 4 "=l,l"))] 9961 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" 9962 "* 9963{ 9964 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 9965 output_asm_insn (\"crxor 6,6,6\", operands); 9966 9967 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 9968 output_asm_insn (\"creqv 6,6,6\", operands); 9969 9970 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; 9971}" 9972 [(set_attr "type" "branch") 9973 (set_attr "length" "4,8")]) 9974 9975;; Call to function which may be in another module. Restore the TOC 9976;; pointer (r2) after the call unless this is System V. 9977;; Operand2 is non-zero if we are using the V.4 calling sequence and 9978;; either the function was not prototyped, or it was prototyped as a 9979;; variable argument function. It is > 0 if FP registers were passed 9980;; and < 0 if they were not. 9981 9982(define_insn "*call_indirect_nonlocal_aix32" 9983 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) 9984 (match_operand 1 "" "g")) 9985 (use (reg:SI 2)) 9986 (use (reg:SI 11)) 9987 (set (reg:SI 2) 9988 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 9989 (clobber (match_scratch:SI 2 "=l"))] 9990 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" 9991 "b%T0l\;{l|lwz} 2,20(1)" 9992 [(set_attr "type" "jmpreg") 9993 (set_attr "length" "8")]) 9994 9995(define_insn "*call_nonlocal_aix32" 9996 [(call (mem:SI (match_operand:SI 0 "call_operand" "s")) 9997 (match_operand 1 "" "g")) 9998 (use (match_operand:SI 2 "immediate_operand" "O")) 9999 (clobber (match_scratch:SI 3 "=l"))] 10000 "TARGET_32BIT 10001 && DEFAULT_ABI == ABI_AIX 10002 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10003 "bl %z0\;%." 10004 [(set_attr "type" "branch") 10005 (set_attr "length" "8")]) 10006 10007(define_insn "*call_indirect_nonlocal_aix64" 10008 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) 10009 (match_operand 1 "" "g")) 10010 (use (reg:DI 2)) 10011 (use (reg:DI 11)) 10012 (set (reg:DI 2) 10013 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10014 (clobber (match_scratch:SI 2 "=l"))] 10015 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" 10016 "b%T0l\;ld 2,40(1)" 10017 [(set_attr "type" "jmpreg") 10018 (set_attr "length" "8")]) 10019 10020(define_insn "*call_nonlocal_aix64" 10021 [(call (mem:SI (match_operand:DI 0 "call_operand" "s")) 10022 (match_operand 1 "" "g")) 10023 (use (match_operand:SI 2 "immediate_operand" "O")) 10024 (clobber (match_scratch:SI 3 "=l"))] 10025 "TARGET_64BIT 10026 && DEFAULT_ABI == ABI_AIX 10027 && (INTVAL (operands[2]) & CALL_LONG) == 0" 10028 "bl %z0\;%." 10029 [(set_attr "type" "branch") 10030 (set_attr "length" "8")]) 10031 10032(define_insn "*call_value_indirect_nonlocal_aix32" 10033 [(set (match_operand 0 "" "") 10034 (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) 10035 (match_operand 2 "" "g"))) 10036 (use (reg:SI 2)) 10037 (use (reg:SI 11)) 10038 (set (reg:SI 2) 10039 (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) 10040 (clobber (match_scratch:SI 3 "=l"))] 10041 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" 10042 "b%T1l\;{l|lwz} 2,20(1)" 10043 [(set_attr "type" "jmpreg") 10044 (set_attr "length" "8")]) 10045 10046(define_insn "*call_value_nonlocal_aix32" 10047 [(set (match_operand 0 "" "") 10048 (call (mem:SI (match_operand:SI 1 "call_operand" "s")) 10049 (match_operand 2 "" "g"))) 10050 (use (match_operand:SI 3 "immediate_operand" "O")) 10051 (clobber (match_scratch:SI 4 "=l"))] 10052 "TARGET_32BIT 10053 && DEFAULT_ABI == ABI_AIX 10054 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10055 "bl %z1\;%." 10056 [(set_attr "type" "branch") 10057 (set_attr "length" "8")]) 10058 10059(define_insn "*call_value_indirect_nonlocal_aix64" 10060 [(set (match_operand 0 "" "") 10061 (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) 10062 (match_operand 2 "" "g"))) 10063 (use (reg:DI 2)) 10064 (use (reg:DI 11)) 10065 (set (reg:DI 2) 10066 (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) 10067 (clobber (match_scratch:SI 3 "=l"))] 10068 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" 10069 "b%T1l\;ld 2,40(1)" 10070 [(set_attr "type" "jmpreg") 10071 (set_attr "length" "8")]) 10072 10073(define_insn "*call_value_nonlocal_aix64" 10074 [(set (match_operand 0 "" "") 10075 (call (mem:SI (match_operand:DI 1 "call_operand" "s")) 10076 (match_operand 2 "" "g"))) 10077 (use (match_operand:SI 3 "immediate_operand" "O")) 10078 (clobber (match_scratch:SI 4 "=l"))] 10079 "TARGET_64BIT 10080 && DEFAULT_ABI == ABI_AIX 10081 && (INTVAL (operands[3]) & CALL_LONG) == 0" 10082 "bl %z1\;%." 10083 [(set_attr "type" "branch") 10084 (set_attr "length" "8")]) 10085 10086;; A function pointer under System V is just a normal pointer 10087;; operands[0] is the function pointer 10088;; operands[1] is the stack size to clean up 10089;; operands[2] is the value FUNCTION_ARG returns for the VOID argument 10090;; which indicates how to set cr1 10091 10092(define_insn "*call_nonlocal_sysv" 10093 [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s")) 10094 (match_operand 1 "" "g,g,g,g")) 10095 (use (match_operand:SI 2 "immediate_operand" "O,n,O,n")) 10096 (clobber (match_scratch:SI 3 "=l,l,l,l"))] 10097 "DEFAULT_ABI == ABI_AIX_NODESC 10098 || DEFAULT_ABI == ABI_V4 10099 || DEFAULT_ABI == ABI_DARWIN" 10100 "* 10101{ 10102 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 10103 output_asm_insn (\"crxor 6,6,6\", operands); 10104 10105 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 10106 output_asm_insn (\"creqv 6,6,6\", operands); 10107 10108 switch (which_alternative) 10109 { 10110 default: 10111 abort (); 10112 case 0: 10113 case 1: 10114 return \"b%T0l\"; 10115 case 2: 10116 case 3: 10117 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; 10118 } 10119}" 10120 [(set_attr "type" "jmpreg,jmpreg,branch,branch") 10121 (set_attr "length" "4,8,4,8")]) 10122 10123(define_insn "*call_value_nonlocal_sysv" 10124 [(set (match_operand 0 "" "") 10125 (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s")) 10126 (match_operand 2 "" "g,g,g,g"))) 10127 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n")) 10128 (clobber (match_scratch:SI 4 "=l,l,l,l"))] 10129 "DEFAULT_ABI == ABI_AIX_NODESC 10130 || DEFAULT_ABI == ABI_V4 10131 || DEFAULT_ABI == ABI_DARWIN" 10132 "* 10133{ 10134 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 10135 output_asm_insn (\"crxor 6,6,6\", operands); 10136 10137 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 10138 output_asm_insn (\"creqv 6,6,6\", operands); 10139 10140 switch (which_alternative) 10141 { 10142 default: 10143 abort (); 10144 case 0: 10145 case 1: 10146 return \"b%T1l\"; 10147 case 2: 10148 case 3: 10149 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; 10150 } 10151}" 10152 [(set_attr "type" "jmpreg,jmpreg,branch,branch") 10153 (set_attr "length" "4,8,4,8")]) 10154 10155;; Call subroutine returning any type. 10156(define_expand "untyped_call" 10157 [(parallel [(call (match_operand 0 "" "") 10158 (const_int 0)) 10159 (match_operand 1 "" "") 10160 (match_operand 2 "" "")])] 10161 "" 10162 " 10163{ 10164 int i; 10165 10166 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); 10167 10168 for (i = 0; i < XVECLEN (operands[2], 0); i++) 10169 { 10170 rtx set = XVECEXP (operands[2], 0, i); 10171 emit_move_insn (SET_DEST (set), SET_SRC (set)); 10172 } 10173 10174 /* The optimizer does not know that the call sets the function value 10175 registers we stored in the result block. We avoid problems by 10176 claiming that all hard registers are used and clobbered at this 10177 point. */ 10178 emit_insn (gen_blockage ()); 10179 10180 DONE; 10181}") 10182 10183;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 10184;; all of memory. This blocks insns from being moved across this point. 10185 10186(define_insn "blockage" 10187 [(unspec_volatile [(const_int 0)] 0)] 10188 "" 10189 "") 10190 10191;; Compare insns are next. Note that the RS/6000 has two types of compares, 10192;; signed & unsigned, and one type of branch. 10193;; 10194;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc 10195;; insns, and branches. We store the operands of compares until we see 10196;; how it is used. 10197(define_expand "cmpsi" 10198 [(set (cc0) 10199 (compare (match_operand:SI 0 "gpc_reg_operand" "") 10200 (match_operand:SI 1 "reg_or_short_operand" "")))] 10201 "" 10202 " 10203{ 10204 /* Take care of the possibility that operands[1] might be negative but 10205 this might be a logical operation. That insn doesn't exist. */ 10206 if (GET_CODE (operands[1]) == CONST_INT 10207 && INTVAL (operands[1]) < 0) 10208 operands[1] = force_reg (SImode, operands[1]); 10209 10210 rs6000_compare_op0 = operands[0]; 10211 rs6000_compare_op1 = operands[1]; 10212 rs6000_compare_fp_p = 0; 10213 DONE; 10214}") 10215 10216(define_expand "cmpdi" 10217 [(set (cc0) 10218 (compare (match_operand:DI 0 "gpc_reg_operand" "") 10219 (match_operand:DI 1 "reg_or_short_operand" "")))] 10220 "TARGET_POWERPC64" 10221 " 10222{ 10223 /* Take care of the possibility that operands[1] might be negative but 10224 this might be a logical operation. That insn doesn't exist. */ 10225 if (GET_CODE (operands[1]) == CONST_INT 10226 && INTVAL (operands[1]) < 0) 10227 operands[1] = force_reg (DImode, operands[1]); 10228 10229 rs6000_compare_op0 = operands[0]; 10230 rs6000_compare_op1 = operands[1]; 10231 rs6000_compare_fp_p = 0; 10232 DONE; 10233}") 10234 10235(define_expand "cmpsf" 10236 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") 10237 (match_operand:SF 1 "gpc_reg_operand" "")))] 10238 "TARGET_HARD_FLOAT" 10239 " 10240{ 10241 rs6000_compare_op0 = operands[0]; 10242 rs6000_compare_op1 = operands[1]; 10243 rs6000_compare_fp_p = 1; 10244 DONE; 10245}") 10246 10247(define_expand "cmpdf" 10248 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") 10249 (match_operand:DF 1 "gpc_reg_operand" "")))] 10250 "TARGET_HARD_FLOAT" 10251 " 10252{ 10253 rs6000_compare_op0 = operands[0]; 10254 rs6000_compare_op1 = operands[1]; 10255 rs6000_compare_fp_p = 1; 10256 DONE; 10257}") 10258 10259(define_expand "cmptf" 10260 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") 10261 (match_operand:TF 1 "gpc_reg_operand" "")))] 10262 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 10263 " 10264{ 10265 rs6000_compare_op0 = operands[0]; 10266 rs6000_compare_op1 = operands[1]; 10267 rs6000_compare_fp_p = 1; 10268 DONE; 10269}") 10270 10271(define_expand "beq" 10272 [(use (match_operand 0 "" ""))] 10273 "" 10274 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") 10275 10276(define_expand "bne" 10277 [(use (match_operand 0 "" ""))] 10278 "" 10279 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") 10280 10281(define_expand "bge" 10282 [(use (match_operand 0 "" ""))] 10283 "" 10284 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") 10285 10286(define_expand "bgt" 10287 [(use (match_operand 0 "" ""))] 10288 "" 10289 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") 10290 10291(define_expand "ble" 10292 [(use (match_operand 0 "" ""))] 10293 "" 10294 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") 10295 10296(define_expand "blt" 10297 [(use (match_operand 0 "" ""))] 10298 "" 10299 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") 10300 10301(define_expand "bgeu" 10302 [(use (match_operand 0 "" ""))] 10303 "" 10304 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") 10305 10306(define_expand "bgtu" 10307 [(use (match_operand 0 "" ""))] 10308 "" 10309 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") 10310 10311(define_expand "bleu" 10312 [(use (match_operand 0 "" ""))] 10313 "" 10314 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") 10315 10316(define_expand "bltu" 10317 [(use (match_operand 0 "" ""))] 10318 "" 10319 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") 10320 10321(define_expand "bunordered" 10322 [(use (match_operand 0 "" ""))] 10323 "" 10324 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") 10325 10326(define_expand "bordered" 10327 [(use (match_operand 0 "" ""))] 10328 "" 10329 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") 10330 10331(define_expand "buneq" 10332 [(use (match_operand 0 "" ""))] 10333 "" 10334 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") 10335 10336(define_expand "bunge" 10337 [(use (match_operand 0 "" ""))] 10338 "" 10339 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") 10340 10341(define_expand "bungt" 10342 [(use (match_operand 0 "" ""))] 10343 "" 10344 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") 10345 10346(define_expand "bunle" 10347 [(use (match_operand 0 "" ""))] 10348 "" 10349 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") 10350 10351(define_expand "bunlt" 10352 [(use (match_operand 0 "" ""))] 10353 "" 10354 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") 10355 10356(define_expand "bltgt" 10357 [(use (match_operand 0 "" ""))] 10358 "" 10359 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") 10360 10361;; For SNE, we would prefer that the xor/abs sequence be used for integers. 10362;; For SEQ, likewise, except that comparisons with zero should be done 10363;; with an scc insns. However, due to the order that combine see the 10364;; resulting insns, we must, in fact, allow SEQ for integers. Fail in 10365;; the cases we don't want to handle. 10366(define_expand "seq" 10367 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10368 "" 10369 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") 10370 10371(define_expand "sne" 10372 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10373 "" 10374 " 10375{ 10376 if (! rs6000_compare_fp_p) 10377 FAIL; 10378 10379 rs6000_emit_sCOND (NE, operands[0]); 10380 DONE; 10381}") 10382 10383;; A > 0 is best done using the portable sequence, so fail in that case. 10384(define_expand "sgt" 10385 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10386 "" 10387 " 10388{ 10389 if (! rs6000_compare_fp_p 10390 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) 10391 FAIL; 10392 10393 rs6000_emit_sCOND (GT, operands[0]); 10394 DONE; 10395}") 10396 10397;; A < 0 is best done in the portable way for A an integer. 10398(define_expand "slt" 10399 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10400 "" 10401 " 10402{ 10403 if (! rs6000_compare_fp_p 10404 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) 10405 FAIL; 10406 10407 rs6000_emit_sCOND (LT, operands[0]); 10408 DONE; 10409}") 10410 10411;; A >= 0 is best done the portable way for A an integer. 10412(define_expand "sge" 10413 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10414 "" 10415 " 10416{ 10417 if (! rs6000_compare_fp_p 10418 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) 10419 FAIL; 10420 10421 rs6000_emit_sCOND (GE, operands[0]); 10422 DONE; 10423}") 10424 10425;; A <= 0 is best done the portable way for A an integer. 10426(define_expand "sle" 10427 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10428 "" 10429 " 10430{ 10431 if (! rs6000_compare_fp_p 10432 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) 10433 FAIL; 10434 10435 rs6000_emit_sCOND (LE, operands[0]); 10436 DONE; 10437}") 10438 10439(define_expand "sgtu" 10440 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10441 "" 10442 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") 10443 10444(define_expand "sltu" 10445 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10446 "" 10447 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") 10448 10449(define_expand "sgeu" 10450 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10451 "" 10452 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") 10453 10454(define_expand "sleu" 10455 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 10456 "" 10457 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") 10458 10459;; Here are the actual compare insns. 10460(define_insn "*cmpsi_internal1" 10461 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 10462 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 10463 (match_operand:SI 2 "reg_or_short_operand" "rI")))] 10464 "" 10465 "{cmp%I2|cmpw%I2} %0,%1,%2" 10466 [(set_attr "type" "compare")]) 10467 10468(define_insn "*cmpdi_internal1" 10469 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 10470 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") 10471 (match_operand:DI 2 "reg_or_short_operand" "rI")))] 10472 "TARGET_POWERPC64" 10473 "cmpd%I2 %0,%1,%2" 10474 [(set_attr "type" "compare")]) 10475 10476;; If we are comparing a register for equality with a large constant, 10477;; we can do this with an XOR followed by a compare. But we need a scratch 10478;; register for the result of the XOR. 10479 10480(define_split 10481 [(set (match_operand:CC 0 "cc_reg_operand" "") 10482 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 10483 (match_operand:SI 2 "non_short_cint_operand" ""))) 10484 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] 10485 "find_single_use (operands[0], insn, 0) 10486 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ 10487 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" 10488 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) 10489 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] 10490 " 10491{ 10492 /* Get the constant we are comparing against, C, and see what it looks like 10493 sign-extended to 16 bits. Then see what constant could be XOR'ed 10494 with C to get the sign-extended value. */ 10495 10496 HOST_WIDE_INT c = INTVAL (operands[2]); 10497 HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000); 10498 HOST_WIDE_INT xorv = c ^ sextc; 10499 10500 operands[4] = GEN_INT (xorv); 10501 operands[5] = GEN_INT (sextc); 10502}") 10503 10504(define_insn "*cmpsi_internal2" 10505 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 10506 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 10507 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] 10508 "" 10509 "{cmpl%I2|cmplw%I2} %0,%1,%b2" 10510 [(set_attr "type" "compare")]) 10511 10512(define_insn "*cmpdi_internal2" 10513 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 10514 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") 10515 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] 10516 "" 10517 "cmpld%I2 %0,%1,%b2" 10518 [(set_attr "type" "compare")]) 10519 10520;; The following two insns don't exist as single insns, but if we provide 10521;; them, we can swap an add and compare, which will enable us to overlap more 10522;; of the required delay between a compare and branch. We generate code for 10523;; them by splitting. 10524 10525(define_insn "" 10526 [(set (match_operand:CC 3 "cc_reg_operand" "=y") 10527 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 10528 (match_operand:SI 2 "short_cint_operand" "i"))) 10529 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 10530 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 10531 "" 10532 "#" 10533 [(set_attr "length" "8")]) 10534 10535(define_insn "" 10536 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") 10537 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 10538 (match_operand:SI 2 "u_short_cint_operand" "i"))) 10539 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 10540 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 10541 "" 10542 "#" 10543 [(set_attr "length" "8")]) 10544 10545(define_split 10546 [(set (match_operand:CC 3 "cc_reg_operand" "") 10547 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 10548 (match_operand:SI 2 "short_cint_operand" ""))) 10549 (set (match_operand:SI 0 "gpc_reg_operand" "") 10550 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 10551 "" 10552 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) 10553 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 10554 10555(define_split 10556 [(set (match_operand:CCUNS 3 "cc_reg_operand" "") 10557 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") 10558 (match_operand:SI 2 "u_short_cint_operand" ""))) 10559 (set (match_operand:SI 0 "gpc_reg_operand" "") 10560 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 10561 "" 10562 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) 10563 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 10564 10565(define_insn "*cmpsf_internal1" 10566 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 10567 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") 10568 (match_operand:SF 2 "gpc_reg_operand" "f")))] 10569 "TARGET_HARD_FLOAT" 10570 "fcmpu %0,%1,%2" 10571 [(set_attr "type" "fpcompare")]) 10572 10573(define_insn "*cmpdf_internal1" 10574 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 10575 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") 10576 (match_operand:DF 2 "gpc_reg_operand" "f")))] 10577 "TARGET_HARD_FLOAT" 10578 "fcmpu %0,%1,%2" 10579 [(set_attr "type" "fpcompare")]) 10580 10581;; Only need to compare second words if first words equal 10582(define_insn "*cmptf_internal1" 10583 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 10584 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") 10585 (match_operand:TF 2 "gpc_reg_operand" "f")))] 10586 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" 10587 "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2" 10588 [(set_attr "type" "fpcompare") 10589 (set_attr "length" "12")]) 10590 10591;; Now we have the scc insns. We can do some combinations because of the 10592;; way the machine works. 10593;; 10594;; Note that this is probably faster if we can put an insn between the 10595;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most 10596;; cases the insns below which don't use an intermediate CR field will 10597;; be used instead. 10598(define_insn "" 10599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 10600 (match_operator:SI 1 "scc_comparison_operator" 10601 [(match_operand 2 "cc_reg_operand" "y") 10602 (const_int 0)]))] 10603 "" 10604 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" 10605 [(set_attr "length" "12")]) 10606 10607(define_insn "" 10608 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 10609 (match_operator:DI 1 "scc_comparison_operator" 10610 [(match_operand 2 "cc_reg_operand" "y") 10611 (const_int 0)]))] 10612 "TARGET_POWERPC64" 10613 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" 10614 [(set_attr "length" "12")]) 10615 10616(define_insn "" 10617 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 10618 (compare:CC (match_operator:SI 1 "scc_comparison_operator" 10619 [(match_operand 2 "cc_reg_operand" "y,y") 10620 (const_int 0)]) 10621 (const_int 0))) 10622 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 10623 (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 10624 "! TARGET_POWERPC64" 10625 "@ 10626 %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 10627 #" 10628 [(set_attr "type" "delayed_compare") 10629 (set_attr "length" "12,16")]) 10630 10631(define_split 10632 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 10633 (compare:CC (match_operator:SI 1 "scc_comparison_operator" 10634 [(match_operand 2 "cc_reg_operand" "") 10635 (const_int 0)]) 10636 (const_int 0))) 10637 (set (match_operand:SI 3 "gpc_reg_operand" "") 10638 (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 10639 "! TARGET_POWERPC64 && reload_completed" 10640 [(set (match_dup 3) 10641 (match_op_dup 1 [(match_dup 2) (const_int 0)])) 10642 (set (match_dup 0) 10643 (compare:CC (match_dup 3) 10644 (const_int 0)))] 10645 "") 10646 10647(define_insn "" 10648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 10649 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 10650 [(match_operand 2 "cc_reg_operand" "y") 10651 (const_int 0)]) 10652 (match_operand:SI 3 "const_int_operand" "n")))] 10653 "" 10654 "* 10655{ 10656 int is_bit = ccr_bit (operands[1], 1); 10657 int put_bit = 31 - (INTVAL (operands[3]) & 31); 10658 int count; 10659 10660 if (is_bit >= put_bit) 10661 count = is_bit - put_bit; 10662 else 10663 count = 32 - (put_bit - is_bit); 10664 10665 operands[4] = GEN_INT (count); 10666 operands[5] = GEN_INT (put_bit); 10667 10668 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; 10669}" 10670 [(set_attr "length" "12")]) 10671 10672(define_insn "" 10673 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 10674 (compare:CC 10675 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 10676 [(match_operand 2 "cc_reg_operand" "y,y") 10677 (const_int 0)]) 10678 (match_operand:SI 3 "const_int_operand" "n,n")) 10679 (const_int 0))) 10680 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") 10681 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 10682 (match_dup 3)))] 10683 "! TARGET_POWERPC64" 10684 "* 10685{ 10686 int is_bit = ccr_bit (operands[1], 1); 10687 int put_bit = 31 - (INTVAL (operands[3]) & 31); 10688 int count; 10689 10690 /* Force split for non-cc0 compare. */ 10691 if (which_alternative == 1) 10692 return \"#\"; 10693 10694 if (is_bit >= put_bit) 10695 count = is_bit - put_bit; 10696 else 10697 count = 32 - (put_bit - is_bit); 10698 10699 operands[5] = GEN_INT (count); 10700 operands[6] = GEN_INT (put_bit); 10701 10702 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; 10703}" 10704 [(set_attr "type" "delayed_compare") 10705 (set_attr "length" "12,16")]) 10706 10707(define_split 10708 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 10709 (compare:CC 10710 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 10711 [(match_operand 2 "cc_reg_operand" "") 10712 (const_int 0)]) 10713 (match_operand:SI 3 "const_int_operand" "")) 10714 (const_int 0))) 10715 (set (match_operand:SI 4 "gpc_reg_operand" "") 10716 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 10717 (match_dup 3)))] 10718 "! TARGET_POWERPC64 && reload_completed" 10719 [(set (match_dup 4) 10720 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 10721 (match_dup 3))) 10722 (set (match_dup 0) 10723 (compare:CC (match_dup 4) 10724 (const_int 0)))] 10725 "") 10726 10727;; There is a 3 cycle delay between consecutive mfcr instructions 10728;; so it is useful to combine 2 scc instructions to use only one mfcr. 10729 10730(define_peephole 10731 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 10732 (match_operator:SI 1 "scc_comparison_operator" 10733 [(match_operand 2 "cc_reg_operand" "y") 10734 (const_int 0)])) 10735 (set (match_operand:SI 3 "gpc_reg_operand" "=r") 10736 (match_operator:SI 4 "scc_comparison_operator" 10737 [(match_operand 5 "cc_reg_operand" "y") 10738 (const_int 0)]))] 10739 "REGNO (operands[2]) != REGNO (operands[5])" 10740 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" 10741 [(set_attr "length" "20")]) 10742 10743(define_peephole 10744 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 10745 (match_operator:DI 1 "scc_comparison_operator" 10746 [(match_operand 2 "cc_reg_operand" "y") 10747 (const_int 0)])) 10748 (set (match_operand:DI 3 "gpc_reg_operand" "=r") 10749 (match_operator:DI 4 "scc_comparison_operator" 10750 [(match_operand 5 "cc_reg_operand" "y") 10751 (const_int 0)]))] 10752 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" 10753 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" 10754 [(set_attr "length" "20")]) 10755 10756;; There are some scc insns that can be done directly, without a compare. 10757;; These are faster because they don't involve the communications between 10758;; the FXU and branch units. In fact, we will be replacing all of the 10759;; integer scc insns here or in the portable methods in emit_store_flag. 10760;; 10761;; Also support (neg (scc ..)) since that construct is used to replace 10762;; branches, (plus (scc ..) ..) since that construct is common and 10763;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the 10764;; cases where it is no more expensive than (neg (scc ..)). 10765 10766;; Have reload force a constant into a register for the simple insns that 10767;; otherwise won't accept constants. We do this because it is faster than 10768;; the cmp/mfcr sequence we would otherwise generate. 10769 10770(define_insn "" 10771 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 10772 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 10773 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) 10774 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] 10775 "! TARGET_POWERPC64" 10776 "@ 10777 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 10778 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 10779 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 10780 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 10781 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" 10782 [(set_attr "length" "12,8,12,12,12")]) 10783 10784(define_insn "" 10785 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") 10786 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") 10787 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) 10788 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] 10789 "TARGET_POWERPC64" 10790 "@ 10791 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 10792 subfic %3,%1,0\;adde %0,%3,%1 10793 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 10794 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 10795 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" 10796 [(set_attr "length" "12,8,12,12,12")]) 10797 10798(define_insn "" 10799 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 10800 (compare:CC 10801 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 10802 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) 10803 (const_int 0))) 10804 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") 10805 (eq:SI (match_dup 1) (match_dup 2))) 10806 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] 10807 "! TARGET_POWERPC64" 10808 "@ 10809 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 10810 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 10811 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 10812 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 10813 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 10814 # 10815 # 10816 # 10817 # 10818 #" 10819 [(set_attr "type" "compare") 10820 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 10821 10822(define_split 10823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 10824 (compare:CC 10825 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 10826 (match_operand:SI 2 "reg_or_cint_operand" "")) 10827 (const_int 0))) 10828 (set (match_operand:SI 0 "gpc_reg_operand" "") 10829 (eq:SI (match_dup 1) (match_dup 2))) 10830 (clobber (match_scratch:SI 3 ""))] 10831 "! TARGET_POWERPC64 && reload_completed" 10832 [(parallel [(set (match_dup 0) 10833 (eq:SI (match_dup 1) (match_dup 2))) 10834 (clobber (match_dup 3))]) 10835 (set (match_dup 4) 10836 (compare:CC (match_dup 0) 10837 (const_int 0)))] 10838 "") 10839 10840(define_insn "" 10841 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 10842 (compare:CC 10843 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 10844 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) 10845 (const_int 0))) 10846 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") 10847 (eq:DI (match_dup 1) (match_dup 2))) 10848 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] 10849 "TARGET_POWERPC64" 10850 "@ 10851 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 10852 subfic %3,%1,0\;adde. %0,%3,%1 10853 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 10854 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 10855 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 10856 # 10857 # 10858 # 10859 # 10860 #" 10861 [(set_attr "type" "compare") 10862 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 10863 10864(define_split 10865 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 10866 (compare:CC 10867 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") 10868 (match_operand:DI 2 "reg_or_cint_operand" "")) 10869 (const_int 0))) 10870 (set (match_operand:DI 0 "gpc_reg_operand" "") 10871 (eq:DI (match_dup 1) (match_dup 2))) 10872 (clobber (match_scratch:DI 3 ""))] 10873 "TARGET_POWERPC64 && reload_completed" 10874 [(parallel [(set (match_dup 0) 10875 (eq:DI (match_dup 1) (match_dup 2))) 10876 (clobber (match_dup 3))]) 10877 (set (match_dup 4) 10878 (compare:CC (match_dup 0) 10879 (const_int 0)))] 10880 "") 10881 10882;; We have insns of the form shown by the first define_insn below. If 10883;; there is something inside the comparison operation, we must split it. 10884(define_split 10885 [(set (match_operand:SI 0 "gpc_reg_operand" "") 10886 (plus:SI (match_operator 1 "comparison_operator" 10887 [(match_operand:SI 2 "" "") 10888 (match_operand:SI 3 10889 "reg_or_cint_operand" "")]) 10890 (match_operand:SI 4 "gpc_reg_operand" ""))) 10891 (clobber (match_operand:SI 5 "register_operand" ""))] 10892 "! gpc_reg_operand (operands[2], SImode)" 10893 [(set (match_dup 5) (match_dup 2)) 10894 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) 10895 (match_dup 4)))]) 10896 10897(define_insn "" 10898 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") 10899 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 10900 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) 10901 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] 10902 "! TARGET_POWERPC64" 10903 "@ 10904 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 10905 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 10906 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 10907 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 10908 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" 10909 [(set_attr "length" "12,8,12,12,12")]) 10910 10911(define_insn "" 10912 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 10913 (compare:CC 10914 (plus:SI 10915 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 10916 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) 10917 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) 10918 (const_int 0))) 10919 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] 10920 "! TARGET_POWERPC64" 10921 "@ 10922 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 10923 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 10924 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 10925 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 10926 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 10927 # 10928 # 10929 # 10930 # 10931 #" 10932 [(set_attr "type" "compare") 10933 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 10934 10935(define_split 10936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 10937 (compare:CC 10938 (plus:SI 10939 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 10940 (match_operand:SI 2 "reg_or_cint_operand" "")) 10941 (match_operand:SI 3 "gpc_reg_operand" "")) 10942 (const_int 0))) 10943 (clobber (match_scratch:SI 4 ""))] 10944 "! TARGET_POWERPC64 && reload_completed" 10945 [(set (match_dup 4) 10946 (plus:SI (eq:SI (match_dup 1) 10947 (match_dup 2)) 10948 (match_dup 3))) 10949 (set (match_dup 0) 10950 (compare:CC (match_dup 4) 10951 (const_int 0)))] 10952 "") 10953 10954(define_insn "" 10955 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 10956 (compare:CC 10957 (plus:SI 10958 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 10959 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) 10960 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) 10961 (const_int 0))) 10962 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") 10963 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 10964 "! TARGET_POWERPC64" 10965 "@ 10966 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 10967 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 10968 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 10969 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 10970 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 10971 # 10972 # 10973 # 10974 # 10975 #" 10976 [(set_attr "type" "compare") 10977 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 10978 10979(define_split 10980 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 10981 (compare:CC 10982 (plus:SI 10983 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 10984 (match_operand:SI 2 "reg_or_cint_operand" "")) 10985 (match_operand:SI 3 "gpc_reg_operand" "")) 10986 (const_int 0))) 10987 (set (match_operand:SI 0 "gpc_reg_operand" "") 10988 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 10989 "! TARGET_POWERPC64 && reload_completed" 10990 [(set (match_dup 0) 10991 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 10992 (set (match_dup 4) 10993 (compare:CC (match_dup 0) 10994 (const_int 0)))] 10995 "") 10996 10997(define_insn "" 10998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") 10999 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 11000 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] 11001 "! TARGET_POWERPC64" 11002 "@ 11003 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 11004 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 11005 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 11006 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 11007 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 11008 [(set_attr "length" "12,8,12,12,12")]) 11009 11010;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, 11011;; since it nabs/sr is just as fast. 11012(define_insn "*ne0" 11013 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 11014 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 11015 (const_int 31))) 11016 (clobber (match_scratch:SI 2 "=&r"))] 11017 "! TARGET_POWER && ! TARGET_POWERPC64" 11018 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" 11019 [(set_attr "length" "8")]) 11020 11021(define_insn "" 11022 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11023 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) 11024 (const_int 63))) 11025 (clobber (match_scratch:DI 2 "=&r"))] 11026 "TARGET_POWERPC64" 11027 "addic %2,%1,-1\;subfe %0,%2,%1" 11028 [(set_attr "length" "8")]) 11029 11030;; This is what (plus (ne X (const_int 0)) Y) looks like. 11031(define_insn "" 11032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11033 (plus:SI (lshiftrt:SI 11034 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) 11035 (const_int 31)) 11036 (match_operand:SI 2 "gpc_reg_operand" "r"))) 11037 (clobber (match_scratch:SI 3 "=&r"))] 11038 "! TARGET_POWERPC64" 11039 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" 11040 [(set_attr "length" "8")]) 11041 11042(define_insn "" 11043 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11044 (plus:DI (lshiftrt:DI 11045 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) 11046 (const_int 63)) 11047 (match_operand:DI 2 "gpc_reg_operand" "r"))) 11048 (clobber (match_scratch:DI 3 "=&r"))] 11049 "TARGET_POWERPC64" 11050 "addic %3,%1,-1\;addze %0,%2" 11051 [(set_attr "length" "8")]) 11052 11053(define_insn "" 11054 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11055 (compare:CC 11056 (plus:SI (lshiftrt:SI 11057 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) 11058 (const_int 31)) 11059 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 11060 (const_int 0))) 11061 (clobber (match_scratch:SI 3 "=&r,&r")) 11062 (clobber (match_scratch:SI 4 "=X,&r"))] 11063 "! TARGET_POWERPC64" 11064 "@ 11065 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 11066 #" 11067 [(set_attr "type" "compare") 11068 (set_attr "length" "8,12")]) 11069 11070(define_split 11071 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11072 (compare:CC 11073 (plus:SI (lshiftrt:SI 11074 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 11075 (const_int 31)) 11076 (match_operand:SI 2 "gpc_reg_operand" "")) 11077 (const_int 0))) 11078 (clobber (match_scratch:SI 3 "")) 11079 (clobber (match_scratch:SI 4 ""))] 11080 "! TARGET_POWERPC64 && reload_completed" 11081 [(parallel [(set (match_dup 3) 11082 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) 11083 (const_int 31)) 11084 (match_dup 2))) 11085 (clobber (match_dup 4))]) 11086 (set (match_dup 0) 11087 (compare:CC (match_dup 3) 11088 (const_int 0)))] 11089 "") 11090 11091(define_insn "" 11092 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11093 (compare:CC 11094 (plus:DI (lshiftrt:DI 11095 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) 11096 (const_int 63)) 11097 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 11098 (const_int 0))) 11099 (clobber (match_scratch:DI 3 "=&r,&r"))] 11100 "TARGET_POWERPC64" 11101 "@ 11102 addic %3,%1,-1\;addze. %3,%2 11103 #" 11104 [(set_attr "type" "compare") 11105 (set_attr "length" "8,12")]) 11106 11107(define_split 11108 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11109 (compare:CC 11110 (plus:DI (lshiftrt:DI 11111 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 11112 (const_int 63)) 11113 (match_operand:DI 2 "gpc_reg_operand" "")) 11114 (const_int 0))) 11115 (clobber (match_scratch:DI 3 ""))] 11116 "TARGET_POWERPC64 && reload_completed" 11117 [(set (match_dup 3) 11118 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) 11119 (const_int 63)) 11120 (match_dup 2))) 11121 (set (match_dup 0) 11122 (compare:CC (match_dup 3) 11123 (const_int 0)))] 11124 "") 11125 11126(define_insn "" 11127 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 11128 (compare:CC 11129 (plus:SI (lshiftrt:SI 11130 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) 11131 (const_int 31)) 11132 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 11133 (const_int 0))) 11134 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11135 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 11136 (match_dup 2))) 11137 (clobber (match_scratch:SI 3 "=&r,&r"))] 11138 "! TARGET_POWERPC64" 11139 "@ 11140 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 11141 #" 11142 [(set_attr "type" "compare") 11143 (set_attr "length" "8,12")]) 11144 11145(define_split 11146 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11147 (compare:CC 11148 (plus:SI (lshiftrt:SI 11149 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) 11150 (const_int 31)) 11151 (match_operand:SI 2 "gpc_reg_operand" "")) 11152 (const_int 0))) 11153 (set (match_operand:SI 0 "gpc_reg_operand" "") 11154 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 11155 (match_dup 2))) 11156 (clobber (match_scratch:SI 3 ""))] 11157 "! TARGET_POWERPC64 && reload_completed" 11158 [(parallel [(set (match_dup 0) 11159 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) 11160 (match_dup 2))) 11161 (clobber (match_dup 3))]) 11162 (set (match_dup 4) 11163 (compare:CC (match_dup 0) 11164 (const_int 0)))] 11165 "") 11166 11167(define_insn "" 11168 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 11169 (compare:CC 11170 (plus:DI (lshiftrt:DI 11171 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) 11172 (const_int 63)) 11173 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 11174 (const_int 0))) 11175 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 11176 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) 11177 (match_dup 2))) 11178 (clobber (match_scratch:DI 3 "=&r,&r"))] 11179 "TARGET_POWERPC64" 11180 "@ 11181 addic %3,%1,-1\;addze. %0,%2 11182 #" 11183 [(set_attr "type" "compare") 11184 (set_attr "length" "8,12")]) 11185 11186(define_split 11187 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11188 (compare:CC 11189 (plus:DI (lshiftrt:DI 11190 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 11191 (const_int 63)) 11192 (match_operand:DI 2 "gpc_reg_operand" "")) 11193 (const_int 0))) 11194 (set (match_operand:DI 0 "gpc_reg_operand" "") 11195 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) 11196 (match_dup 2))) 11197 (clobber (match_scratch:DI 3 ""))] 11198 "TARGET_POWERPC64 && reload_completed" 11199 [(parallel [(set (match_dup 0) 11200 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) 11201 (match_dup 2))) 11202 (clobber (match_dup 3))]) 11203 (set (match_dup 4) 11204 (compare:CC (match_dup 0) 11205 (const_int 0)))] 11206 "") 11207 11208(define_insn "" 11209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11210 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11211 (match_operand:SI 2 "reg_or_short_operand" "r,O"))) 11212 (clobber (match_scratch:SI 3 "=r,X"))] 11213 "TARGET_POWER" 11214 "@ 11215 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 11216 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" 11217 [(set_attr "length" "12")]) 11218 11219(define_insn "" 11220 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 11221 (compare:CC 11222 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 11223 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) 11224 (const_int 0))) 11225 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 11226 (le:SI (match_dup 1) (match_dup 2))) 11227 (clobber (match_scratch:SI 3 "=r,X,r,X"))] 11228 "TARGET_POWER" 11229 "@ 11230 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 11231 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 11232 # 11233 #" 11234 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") 11235 (set_attr "length" "12,12,16,16")]) 11236 11237(define_split 11238 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11239 (compare:CC 11240 (le:SI (match_operand:SI 1 "gpc_reg_operand" "") 11241 (match_operand:SI 2 "reg_or_short_operand" "")) 11242 (const_int 0))) 11243 (set (match_operand:SI 0 "gpc_reg_operand" "") 11244 (le:SI (match_dup 1) (match_dup 2))) 11245 (clobber (match_scratch:SI 3 ""))] 11246 "TARGET_POWER && reload_completed" 11247 [(parallel [(set (match_dup 0) 11248 (le:SI (match_dup 1) (match_dup 2))) 11249 (clobber (match_dup 3))]) 11250 (set (match_dup 4) 11251 (compare:CC (match_dup 0) 11252 (const_int 0)))] 11253 "") 11254 11255(define_insn "" 11256 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 11257 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11258 (match_operand:SI 2 "reg_or_short_operand" "r,O")) 11259 (match_operand:SI 3 "gpc_reg_operand" "r,r")))] 11260 "TARGET_POWER" 11261 "@ 11262 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 11263 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" 11264 [(set_attr "length" "12")]) 11265 11266(define_insn "" 11267 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 11268 (compare:CC 11269 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 11270 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) 11271 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 11272 (const_int 0))) 11273 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 11274 "TARGET_POWER" 11275 "@ 11276 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 11277 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 11278 # 11279 #" 11280 [(set_attr "type" "compare") 11281 (set_attr "length" "12,12,16,16")]) 11282 11283(define_split 11284 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11285 (compare:CC 11286 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") 11287 (match_operand:SI 2 "reg_or_short_operand" "")) 11288 (match_operand:SI 3 "gpc_reg_operand" "")) 11289 (const_int 0))) 11290 (clobber (match_scratch:SI 4 ""))] 11291 "TARGET_POWER && reload_completed" 11292 [(set (match_dup 4) 11293 (plus:SI (le:SI (match_dup 1) (match_dup 2)) 11294 (match_dup 3))) 11295 (set (match_dup 0) 11296 (compare:CC (match_dup 4) 11297 (const_int 0)))] 11298 "") 11299 11300(define_insn "" 11301 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 11302 (compare:CC 11303 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 11304 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) 11305 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 11306 (const_int 0))) 11307 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 11308 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11309 "TARGET_POWER" 11310 "@ 11311 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 11312 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 11313 # 11314 #" 11315 [(set_attr "type" "compare") 11316 (set_attr "length" "12,12,16,16")]) 11317 11318(define_split 11319 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11320 (compare:CC 11321 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") 11322 (match_operand:SI 2 "reg_or_short_operand" "")) 11323 (match_operand:SI 3 "gpc_reg_operand" "")) 11324 (const_int 0))) 11325 (set (match_operand:SI 0 "gpc_reg_operand" "") 11326 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11327 "TARGET_POWER && reload_completed" 11328 [(set (match_dup 0) 11329 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 11330 (set (match_dup 4) 11331 (compare:CC (match_dup 0) 11332 (const_int 0)))] 11333 "") 11334 11335(define_insn "" 11336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11337 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11338 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] 11339 "TARGET_POWER" 11340 "@ 11341 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 11342 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" 11343 [(set_attr "length" "12")]) 11344 11345(define_insn "" 11346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11347 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11348 (match_operand:SI 2 "reg_or_short_operand" "rI")))] 11349 "! TARGET_POWERPC64" 11350 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 11351 [(set_attr "length" "12")]) 11352 11353(define_insn "" 11354 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11355 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") 11356 (match_operand:DI 2 "reg_or_short_operand" "rI")))] 11357 "TARGET_POWERPC64" 11358 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" 11359 [(set_attr "length" "12")]) 11360 11361(define_insn "" 11362 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 11363 (compare:CC 11364 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 11365 (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) 11366 (const_int 0))) 11367 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 11368 (leu:DI (match_dup 1) (match_dup 2)))] 11369 "TARGET_POWERPC64" 11370 "@ 11371 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 11372 #" 11373 [(set_attr "type" "compare") 11374 (set_attr "length" "12,16")]) 11375 11376(define_split 11377 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 11378 (compare:CC 11379 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") 11380 (match_operand:DI 2 "reg_or_short_operand" "")) 11381 (const_int 0))) 11382 (set (match_operand:DI 0 "gpc_reg_operand" "") 11383 (leu:DI (match_dup 1) (match_dup 2)))] 11384 "TARGET_POWERPC64 && reload_completed" 11385 [(set (match_dup 0) 11386 (leu:DI (match_dup 1) (match_dup 2))) 11387 (set (match_dup 3) 11388 (compare:CC (match_dup 0) 11389 (const_int 0)))] 11390 "") 11391 11392(define_insn "" 11393 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 11394 (compare:CC 11395 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11396 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 11397 (const_int 0))) 11398 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11399 (leu:SI (match_dup 1) (match_dup 2)))] 11400 "! TARGET_POWERPC64" 11401 "@ 11402 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 11403 #" 11404 [(set_attr "type" "compare") 11405 (set_attr "length" "12,16")]) 11406 11407(define_split 11408 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 11409 (compare:CC 11410 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 11411 (match_operand:SI 2 "reg_or_short_operand" "")) 11412 (const_int 0))) 11413 (set (match_operand:SI 0 "gpc_reg_operand" "") 11414 (leu:SI (match_dup 1) (match_dup 2)))] 11415 "! TARGET_POWERPC64 && reload_completed" 11416 [(set (match_dup 0) 11417 (leu:SI (match_dup 1) (match_dup 2))) 11418 (set (match_dup 3) 11419 (compare:CC (match_dup 0) 11420 (const_int 0)))] 11421 "") 11422 11423(define_insn "" 11424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 11425 (compare:CC 11426 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 11427 (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) 11428 (const_int 0))) 11429 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 11430 (leu:DI (match_dup 1) (match_dup 2)))] 11431 "TARGET_POWERPC64" 11432 "@ 11433 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 11434 #" 11435 [(set_attr "type" "compare") 11436 (set_attr "length" "12,16")]) 11437 11438(define_insn "" 11439 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 11440 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11441 (match_operand:SI 2 "reg_or_short_operand" "rI")) 11442 (match_operand:SI 3 "gpc_reg_operand" "r")))] 11443 "! TARGET_POWERPC64" 11444 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" 11445 [(set_attr "length" "8")]) 11446 11447(define_insn "" 11448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11449 (compare:CC 11450 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11451 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 11452 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11453 (const_int 0))) 11454 (clobber (match_scratch:SI 4 "=&r,&r"))] 11455 "! TARGET_POWERPC64" 11456 "@ 11457 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 11458 #" 11459 [(set_attr "type" "compare") 11460 (set_attr "length" "8,12")]) 11461 11462(define_split 11463 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11464 (compare:CC 11465 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 11466 (match_operand:SI 2 "reg_or_short_operand" "")) 11467 (match_operand:SI 3 "gpc_reg_operand" "")) 11468 (const_int 0))) 11469 (clobber (match_scratch:SI 4 ""))] 11470 "! TARGET_POWERPC64 && reload_completed" 11471 [(set (match_dup 4) 11472 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) 11473 (match_dup 3))) 11474 (set (match_dup 0) 11475 (compare:CC (match_dup 4) 11476 (const_int 0)))] 11477 "") 11478 11479(define_insn "" 11480 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 11481 (compare:CC 11482 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11483 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 11484 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11485 (const_int 0))) 11486 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 11487 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11488 "! TARGET_POWERPC64" 11489 "@ 11490 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 11491 #" 11492 [(set_attr "type" "compare") 11493 (set_attr "length" "8,12")]) 11494 11495(define_split 11496 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11497 (compare:CC 11498 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 11499 (match_operand:SI 2 "reg_or_short_operand" "")) 11500 (match_operand:SI 3 "gpc_reg_operand" "")) 11501 (const_int 0))) 11502 (set (match_operand:SI 0 "gpc_reg_operand" "") 11503 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11504 "! TARGET_POWERPC64 && reload_completed" 11505 [(set (match_dup 0) 11506 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 11507 (set (match_dup 4) 11508 (compare:CC (match_dup 0) 11509 (const_int 0)))] 11510 "") 11511 11512(define_insn "" 11513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11514 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11515 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 11516 "! TARGET_POWERPC64" 11517 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" 11518 [(set_attr "length" "12")]) 11519 11520(define_insn "" 11521 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 11522 (and:SI (neg:SI 11523 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11524 (match_operand:SI 2 "reg_or_short_operand" "rI"))) 11525 (match_operand:SI 3 "gpc_reg_operand" "r")))] 11526 "! TARGET_POWERPC64" 11527 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" 11528 [(set_attr "length" "12")]) 11529 11530(define_insn "" 11531 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11532 (compare:CC 11533 (and:SI (neg:SI 11534 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11535 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) 11536 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11537 (const_int 0))) 11538 (clobber (match_scratch:SI 4 "=&r,&r"))] 11539 "! TARGET_POWERPC64" 11540 "@ 11541 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 11542 #" 11543 [(set_attr "type" "compare") 11544 (set_attr "length" "12,16")]) 11545 11546(define_split 11547 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11548 (compare:CC 11549 (and:SI (neg:SI 11550 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 11551 (match_operand:SI 2 "reg_or_short_operand" ""))) 11552 (match_operand:SI 3 "gpc_reg_operand" "")) 11553 (const_int 0))) 11554 (clobber (match_scratch:SI 4 ""))] 11555 "! TARGET_POWERPC64 && reload_completed" 11556 [(set (match_dup 4) 11557 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) 11558 (match_dup 3))) 11559 (set (match_dup 0) 11560 (compare:CC (match_dup 4) 11561 (const_int 0)))] 11562 "") 11563 11564(define_insn "" 11565 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 11566 (compare:CC 11567 (and:SI (neg:SI 11568 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11569 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) 11570 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11571 (const_int 0))) 11572 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 11573 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 11574 "! TARGET_POWERPC64" 11575 "@ 11576 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 11577 #" 11578 [(set_attr "type" "compare") 11579 (set_attr "length" "12,16")]) 11580 11581(define_split 11582 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11583 (compare:CC 11584 (and:SI (neg:SI 11585 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 11586 (match_operand:SI 2 "reg_or_short_operand" ""))) 11587 (match_operand:SI 3 "gpc_reg_operand" "")) 11588 (const_int 0))) 11589 (set (match_operand:SI 0 "gpc_reg_operand" "") 11590 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 11591 "! TARGET_POWERPC64 && reload_completed" 11592 [(set (match_dup 0) 11593 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) 11594 (match_dup 3))) 11595 (set (match_dup 4) 11596 (compare:CC (match_dup 0) 11597 (const_int 0)))] 11598 "") 11599 11600(define_insn "" 11601 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11602 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11603 (match_operand:SI 2 "reg_or_short_operand" "rI")))] 11604 "TARGET_POWER" 11605 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" 11606 [(set_attr "length" "12")]) 11607 11608(define_insn "" 11609 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 11610 (compare:CC 11611 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11612 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 11613 (const_int 0))) 11614 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11615 (lt:SI (match_dup 1) (match_dup 2)))] 11616 "TARGET_POWER" 11617 "@ 11618 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 11619 #" 11620 [(set_attr "type" "delayed_compare") 11621 (set_attr "length" "12,16")]) 11622 11623(define_split 11624 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 11625 (compare:CC 11626 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") 11627 (match_operand:SI 2 "reg_or_short_operand" "")) 11628 (const_int 0))) 11629 (set (match_operand:SI 0 "gpc_reg_operand" "") 11630 (lt:SI (match_dup 1) (match_dup 2)))] 11631 "TARGET_POWER && reload_completed" 11632 [(set (match_dup 0) 11633 (lt:SI (match_dup 1) (match_dup 2))) 11634 (set (match_dup 3) 11635 (compare:CC (match_dup 0) 11636 (const_int 0)))] 11637 "") 11638 11639(define_insn "" 11640 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 11641 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11642 (match_operand:SI 2 "reg_or_short_operand" "rI")) 11643 (match_operand:SI 3 "gpc_reg_operand" "r")))] 11644 "TARGET_POWER" 11645 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" 11646 [(set_attr "length" "12")]) 11647 11648(define_insn "" 11649 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11650 (compare:CC 11651 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11652 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 11653 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11654 (const_int 0))) 11655 (clobber (match_scratch:SI 4 "=&r,&r"))] 11656 "TARGET_POWER" 11657 "@ 11658 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 11659 #" 11660 [(set_attr "type" "compare") 11661 (set_attr "length" "12,16")]) 11662 11663(define_split 11664 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11665 (compare:CC 11666 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") 11667 (match_operand:SI 2 "reg_or_short_operand" "")) 11668 (match_operand:SI 3 "gpc_reg_operand" "")) 11669 (const_int 0))) 11670 (clobber (match_scratch:SI 4 ""))] 11671 "TARGET_POWER && reload_completed" 11672 [(set (match_dup 4) 11673 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) 11674 (match_dup 3))) 11675 (set (match_dup 0) 11676 (compare:CC (match_dup 4) 11677 (const_int 0)))] 11678 "") 11679 11680(define_insn "" 11681 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 11682 (compare:CC 11683 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11684 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 11685 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11686 (const_int 0))) 11687 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 11688 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11689 "TARGET_POWER" 11690 "@ 11691 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 11692 #" 11693 [(set_attr "type" "compare") 11694 (set_attr "length" "12,16")]) 11695 11696(define_split 11697 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11698 (compare:CC 11699 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") 11700 (match_operand:SI 2 "reg_or_short_operand" "")) 11701 (match_operand:SI 3 "gpc_reg_operand" "")) 11702 (const_int 0))) 11703 (set (match_operand:SI 0 "gpc_reg_operand" "") 11704 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11705 "TARGET_POWER && reload_completed" 11706 [(set (match_dup 0) 11707 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 11708 (set (match_dup 4) 11709 (compare:CC (match_dup 0) 11710 (const_int 0)))] 11711 "") 11712 11713(define_insn "" 11714 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11715 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11716 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 11717 "TARGET_POWER" 11718 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" 11719 [(set_attr "length" "12")]) 11720 11721(define_insn "" 11722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11723 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11724 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 11725 "! TARGET_POWERPC64" 11726 "@ 11727 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 11728 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 11729 [(set_attr "length" "12")]) 11730 11731(define_insn "" 11732 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 11733 (compare:CC 11734 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 11735 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 11736 (const_int 0))) 11737 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 11738 (ltu:SI (match_dup 1) (match_dup 2)))] 11739 "! TARGET_POWERPC64" 11740 "@ 11741 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 11742 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 11743 # 11744 #" 11745 [(set_attr "type" "compare") 11746 (set_attr "length" "12,12,16,16")]) 11747 11748(define_split 11749 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 11750 (compare:CC 11751 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") 11752 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 11753 (const_int 0))) 11754 (set (match_operand:SI 0 "gpc_reg_operand" "") 11755 (ltu:SI (match_dup 1) (match_dup 2)))] 11756 "! TARGET_POWERPC64 && reload_completed" 11757 [(set (match_dup 0) 11758 (ltu:SI (match_dup 1) (match_dup 2))) 11759 (set (match_dup 3) 11760 (compare:CC (match_dup 0) 11761 (const_int 0)))] 11762 "") 11763 11764(define_insn "" 11765 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 11766 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11767 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 11768 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] 11769 "! TARGET_POWERPC64" 11770 "@ 11771 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3 11772 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" 11773 [(set_attr "length" "12")]) 11774 11775(define_insn "" 11776 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 11777 (compare:CC 11778 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 11779 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 11780 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 11781 (const_int 0))) 11782 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 11783 "! TARGET_POWERPC64" 11784 "@ 11785 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 11786 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 11787 # 11788 #" 11789 [(set_attr "type" "compare") 11790 (set_attr "length" "12,12,16,16")]) 11791 11792(define_split 11793 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11794 (compare:CC 11795 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") 11796 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 11797 (match_operand:SI 3 "gpc_reg_operand" "")) 11798 (const_int 0))) 11799 (clobber (match_scratch:SI 4 ""))] 11800 "! TARGET_POWERPC64 && reload_completed" 11801 [(set (match_dup 4) 11802 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) 11803 (match_dup 3))) 11804 (set (match_dup 0) 11805 (compare:CC (match_dup 4) 11806 (const_int 0)))] 11807 "") 11808 11809(define_insn "" 11810 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 11811 (compare:CC 11812 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 11813 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 11814 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 11815 (const_int 0))) 11816 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 11817 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11818 "! TARGET_POWERPC64" 11819 "@ 11820 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 11821 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 11822 # 11823 #" 11824 [(set_attr "type" "compare") 11825 (set_attr "length" "12,12,16,16")]) 11826 11827(define_split 11828 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11829 (compare:CC 11830 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") 11831 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 11832 (match_operand:SI 3 "gpc_reg_operand" "")) 11833 (const_int 0))) 11834 (set (match_operand:SI 0 "gpc_reg_operand" "") 11835 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11836 "! TARGET_POWERPC64 && reload_completed" 11837 [(set (match_dup 0) 11838 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 11839 (set (match_dup 4) 11840 (compare:CC (match_dup 0) 11841 (const_int 0)))] 11842 "") 11843 11844(define_insn "" 11845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11846 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11847 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] 11848 "! TARGET_POWERPC64" 11849 "@ 11850 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 11851 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" 11852 [(set_attr "length" "8")]) 11853 11854(define_insn "" 11855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11856 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11857 (match_operand:SI 2 "reg_or_short_operand" "rI"))) 11858 (clobber (match_scratch:SI 3 "=r"))] 11859 "TARGET_POWER" 11860 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" 11861 [(set_attr "length" "12")]) 11862 11863(define_insn "" 11864 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 11865 (compare:CC 11866 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11867 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 11868 (const_int 0))) 11869 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11870 (ge:SI (match_dup 1) (match_dup 2))) 11871 (clobber (match_scratch:SI 3 "=r,r"))] 11872 "TARGET_POWER" 11873 "@ 11874 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 11875 #" 11876 [(set_attr "type" "compare") 11877 (set_attr "length" "12,16")]) 11878 11879(define_split 11880 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11881 (compare:CC 11882 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") 11883 (match_operand:SI 2 "reg_or_short_operand" "")) 11884 (const_int 0))) 11885 (set (match_operand:SI 0 "gpc_reg_operand" "") 11886 (ge:SI (match_dup 1) (match_dup 2))) 11887 (clobber (match_scratch:SI 3 ""))] 11888 "TARGET_POWER && reload_completed" 11889 [(parallel [(set (match_dup 0) 11890 (ge:SI (match_dup 1) (match_dup 2))) 11891 (clobber (match_dup 3))]) 11892 (set (match_dup 4) 11893 (compare:CC (match_dup 0) 11894 (const_int 0)))] 11895 "") 11896 11897(define_insn "" 11898 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 11899 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11900 (match_operand:SI 2 "reg_or_short_operand" "rI")) 11901 (match_operand:SI 3 "gpc_reg_operand" "r")))] 11902 "TARGET_POWER" 11903 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" 11904 [(set_attr "length" "12")]) 11905 11906(define_insn "" 11907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 11908 (compare:CC 11909 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11910 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 11911 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11912 (const_int 0))) 11913 (clobber (match_scratch:SI 4 "=&r,&r"))] 11914 "TARGET_POWER" 11915 "@ 11916 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 11917 #" 11918 [(set_attr "type" "compare") 11919 (set_attr "length" "12,16")]) 11920 11921(define_split 11922 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 11923 (compare:CC 11924 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") 11925 (match_operand:SI 2 "reg_or_short_operand" "")) 11926 (match_operand:SI 3 "gpc_reg_operand" "")) 11927 (const_int 0))) 11928 (clobber (match_scratch:SI 4 ""))] 11929 "TARGET_POWER && reload_completed" 11930 [(set (match_dup 4) 11931 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) 11932 (match_dup 3))) 11933 (set (match_dup 0) 11934 (compare:CC (match_dup 4) 11935 (const_int 0)))] 11936 "") 11937 11938(define_insn "" 11939 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 11940 (compare:CC 11941 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11942 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 11943 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11944 (const_int 0))) 11945 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 11946 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11947 "TARGET_POWER" 11948 "@ 11949 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 11950 #" 11951 [(set_attr "type" "compare") 11952 (set_attr "length" "12,16")]) 11953 11954(define_split 11955 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 11956 (compare:CC 11957 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") 11958 (match_operand:SI 2 "reg_or_short_operand" "")) 11959 (match_operand:SI 3 "gpc_reg_operand" "")) 11960 (const_int 0))) 11961 (set (match_operand:SI 0 "gpc_reg_operand" "") 11962 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 11963 "TARGET_POWER && reload_completed" 11964 [(set (match_dup 0) 11965 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 11966 (set (match_dup 4) 11967 (compare:CC (match_dup 0) 11968 (const_int 0)))] 11969 "") 11970 11971(define_insn "" 11972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11973 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") 11974 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 11975 "TARGET_POWER" 11976 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" 11977 [(set_attr "length" "12")]) 11978 11979(define_insn "" 11980 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 11981 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 11982 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] 11983 "! TARGET_POWERPC64" 11984 "@ 11985 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 11986 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" 11987 [(set_attr "length" "12")]) 11988 11989(define_insn "" 11990 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 11991 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 11992 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] 11993 "TARGET_POWERPC64" 11994 "@ 11995 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 11996 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" 11997 [(set_attr "length" "12")]) 11998 11999(define_insn "" 12000 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 12001 (compare:CC 12002 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12003 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12004 (const_int 0))) 12005 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 12006 (geu:SI (match_dup 1) (match_dup 2)))] 12007 "! TARGET_POWERPC64" 12008 "@ 12009 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 12010 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 12011 # 12012 #" 12013 [(set_attr "type" "compare") 12014 (set_attr "length" "12,12,16,16")]) 12015 12016(define_split 12017 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12018 (compare:CC 12019 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12020 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 12021 (const_int 0))) 12022 (set (match_operand:SI 0 "gpc_reg_operand" "") 12023 (geu:SI (match_dup 1) (match_dup 2)))] 12024 "! TARGET_POWERPC64 && reload_completed" 12025 [(set (match_dup 0) 12026 (geu:SI (match_dup 1) (match_dup 2))) 12027 (set (match_dup 3) 12028 (compare:CC (match_dup 0) 12029 (const_int 0)))] 12030 "") 12031 12032(define_insn "" 12033 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 12034 (compare:CC 12035 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 12036 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12037 (const_int 0))) 12038 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 12039 (geu:DI (match_dup 1) (match_dup 2)))] 12040 "TARGET_POWERPC64" 12041 "@ 12042 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 12043 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 12044 # 12045 #" 12046 [(set_attr "type" "compare") 12047 (set_attr "length" "12,12,16,16")]) 12048 12049(define_split 12050 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12051 (compare:CC 12052 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") 12053 (match_operand:DI 2 "reg_or_neg_short_operand" "")) 12054 (const_int 0))) 12055 (set (match_operand:DI 0 "gpc_reg_operand" "") 12056 (geu:DI (match_dup 1) (match_dup 2)))] 12057 "TARGET_POWERPC64 && reload_completed" 12058 [(set (match_dup 0) 12059 (geu:DI (match_dup 1) (match_dup 2))) 12060 (set (match_dup 3) 12061 (compare:CC (match_dup 0) 12062 (const_int 0)))] 12063 "") 12064 12065(define_insn "" 12066 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12067 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12068 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) 12069 (match_operand:SI 3 "gpc_reg_operand" "r,r")))] 12070 "! TARGET_POWERPC64" 12071 "@ 12072 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 12073 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" 12074 [(set_attr "length" "8")]) 12075 12076(define_insn "" 12077 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 12078 (compare:CC 12079 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12080 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12081 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12082 (const_int 0))) 12083 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 12084 "! TARGET_POWERPC64" 12085 "@ 12086 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 12087 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 12088 # 12089 #" 12090 [(set_attr "type" "compare") 12091 (set_attr "length" "8,8,12,12")]) 12092 12093(define_split 12094 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12095 (compare:CC 12096 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12097 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 12098 (match_operand:SI 3 "gpc_reg_operand" "")) 12099 (const_int 0))) 12100 (clobber (match_scratch:SI 4 ""))] 12101 "! TARGET_POWERPC64 && reload_completed" 12102 [(set (match_dup 4) 12103 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) 12104 (match_dup 3))) 12105 (set (match_dup 0) 12106 (compare:CC (match_dup 4) 12107 (const_int 0)))] 12108 "") 12109 12110(define_insn "" 12111 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12112 (compare:CC 12113 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12114 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 12115 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12116 (const_int 0))) 12117 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12118 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12119 "! TARGET_POWERPC64" 12120 "@ 12121 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 12122 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 12123 # 12124 #" 12125 [(set_attr "type" "compare") 12126 (set_attr "length" "8,8,12,12")]) 12127 12128(define_split 12129 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12130 (compare:CC 12131 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12132 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 12133 (match_operand:SI 3 "gpc_reg_operand" "")) 12134 (const_int 0))) 12135 (set (match_operand:SI 0 "gpc_reg_operand" "") 12136 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12137 "! TARGET_POWERPC64 && reload_completed" 12138 [(set (match_dup 0) 12139 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12140 (set (match_dup 4) 12141 (compare:CC (match_dup 0) 12142 (const_int 0)))] 12143 "") 12144 12145(define_insn "" 12146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12147 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12148 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] 12149 "! TARGET_POWERPC64" 12150 "@ 12151 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 12152 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" 12153 [(set_attr "length" "12")]) 12154 12155(define_insn "" 12156 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12157 (and:SI (neg:SI 12158 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12159 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) 12160 (match_operand:SI 3 "gpc_reg_operand" "r,r")))] 12161 "! TARGET_POWERPC64" 12162 "@ 12163 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 12164 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" 12165 [(set_attr "length" "12")]) 12166 12167(define_insn "" 12168 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 12169 (compare:CC 12170 (and:SI (neg:SI 12171 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12172 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) 12173 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12174 (const_int 0))) 12175 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 12176 "! TARGET_POWERPC64" 12177 "@ 12178 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 12179 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 12180 # 12181 #" 12182 [(set_attr "type" "compare") 12183 (set_attr "length" "12,12,16,16")]) 12184 12185(define_split 12186 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12187 (compare:CC 12188 (and:SI (neg:SI 12189 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12190 (match_operand:SI 2 "reg_or_neg_short_operand" ""))) 12191 (match_operand:SI 3 "gpc_reg_operand" "")) 12192 (const_int 0))) 12193 (clobber (match_scratch:SI 4 ""))] 12194 "! TARGET_POWERPC64 && reload_completed" 12195 [(set (match_dup 4) 12196 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) 12197 (match_dup 3))) 12198 (set (match_dup 0) 12199 (compare:CC (match_dup 4) 12200 (const_int 0)))] 12201 "") 12202 12203(define_insn "" 12204 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12205 (compare:CC 12206 (and:SI (neg:SI 12207 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12208 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) 12209 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12210 (const_int 0))) 12211 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12212 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 12213 "! TARGET_POWERPC64" 12214 "@ 12215 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 12216 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 12217 # 12218 #" 12219 [(set_attr "type" "compare") 12220 (set_attr "length" "12,12,16,16")]) 12221 12222(define_split 12223 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12224 (compare:CC 12225 (and:SI (neg:SI 12226 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12227 (match_operand:SI 2 "reg_or_neg_short_operand" ""))) 12228 (match_operand:SI 3 "gpc_reg_operand" "")) 12229 (const_int 0))) 12230 (set (match_operand:SI 0 "gpc_reg_operand" "") 12231 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 12232 "! TARGET_POWERPC64 && reload_completed" 12233 [(set (match_dup 0) 12234 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 12235 (set (match_dup 4) 12236 (compare:CC (match_dup 0) 12237 (const_int 0)))] 12238 "") 12239 12240(define_insn "" 12241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12242 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12243 (const_int 0)))] 12244 "! TARGET_POWERPC64" 12245 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" 12246 [(set_attr "length" "12")]) 12247 12248(define_insn "" 12249 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 12250 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 12251 (const_int 0)))] 12252 "TARGET_POWERPC64" 12253 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" 12254 [(set_attr "length" "12")]) 12255 12256(define_insn "" 12257 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 12258 (compare:CC 12259 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12260 (const_int 0)) 12261 (const_int 0))) 12262 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12263 (gt:SI (match_dup 1) (const_int 0)))] 12264 "! TARGET_POWERPC64" 12265 "@ 12266 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 12267 #" 12268 [(set_attr "type" "delayed_compare") 12269 (set_attr "length" "12,16")]) 12270 12271(define_split 12272 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 12273 (compare:CC 12274 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12275 (const_int 0)) 12276 (const_int 0))) 12277 (set (match_operand:SI 0 "gpc_reg_operand" "") 12278 (gt:SI (match_dup 1) (const_int 0)))] 12279 "! TARGET_POWERPC64 && reload_completed" 12280 [(set (match_dup 0) 12281 (gt:SI (match_dup 1) (const_int 0))) 12282 (set (match_dup 2) 12283 (compare:CC (match_dup 0) 12284 (const_int 0)))] 12285 "") 12286 12287(define_insn "" 12288 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 12289 (compare:CC 12290 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 12291 (const_int 0)) 12292 (const_int 0))) 12293 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 12294 (gt:DI (match_dup 1) (const_int 0)))] 12295 "TARGET_POWERPC64" 12296 "@ 12297 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 12298 #" 12299 [(set_attr "type" "delayed_compare") 12300 (set_attr "length" "12,16")]) 12301 12302(define_split 12303 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 12304 (compare:CC 12305 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 12306 (const_int 0)) 12307 (const_int 0))) 12308 (set (match_operand:DI 0 "gpc_reg_operand" "") 12309 (gt:DI (match_dup 1) (const_int 0)))] 12310 "TARGET_POWERPC64 && reload_completed" 12311 [(set (match_dup 0) 12312 (gt:DI (match_dup 1) (const_int 0))) 12313 (set (match_dup 2) 12314 (compare:CC (match_dup 0) 12315 (const_int 0)))] 12316 "") 12317 12318(define_insn "" 12319 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12320 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12321 (match_operand:SI 2 "reg_or_short_operand" "r")))] 12322 "TARGET_POWER" 12323 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" 12324 [(set_attr "length" "12")]) 12325 12326(define_insn "" 12327 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12328 (compare:CC 12329 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12330 (match_operand:SI 2 "reg_or_short_operand" "r,r")) 12331 (const_int 0))) 12332 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12333 (gt:SI (match_dup 1) (match_dup 2)))] 12334 "TARGET_POWER" 12335 "@ 12336 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 12337 #" 12338 [(set_attr "type" "delayed_compare") 12339 (set_attr "length" "12,16")]) 12340 12341(define_split 12342 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12343 (compare:CC 12344 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12345 (match_operand:SI 2 "reg_or_short_operand" "")) 12346 (const_int 0))) 12347 (set (match_operand:SI 0 "gpc_reg_operand" "") 12348 (gt:SI (match_dup 1) (match_dup 2)))] 12349 "TARGET_POWER && reload_completed" 12350 [(set (match_dup 0) 12351 (gt:SI (match_dup 1) (match_dup 2))) 12352 (set (match_dup 3) 12353 (compare:CC (match_dup 0) 12354 (const_int 0)))] 12355 "") 12356 12357(define_insn "" 12358 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 12359 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12360 (const_int 0)) 12361 (match_operand:SI 2 "gpc_reg_operand" "r")))] 12362 "! TARGET_POWERPC64" 12363 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" 12364 [(set_attr "length" "12")]) 12365 12366(define_insn "" 12367 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 12368 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 12369 (const_int 0)) 12370 (match_operand:DI 2 "gpc_reg_operand" "r")))] 12371 "TARGET_POWERPC64" 12372 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" 12373 [(set_attr "length" "12")]) 12374 12375(define_insn "" 12376 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12377 (compare:CC 12378 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12379 (const_int 0)) 12380 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 12381 (const_int 0))) 12382 (clobber (match_scratch:SI 3 "=&r,&r"))] 12383 "! TARGET_POWERPC64" 12384 "@ 12385 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 12386 #" 12387 [(set_attr "type" "compare") 12388 (set_attr "length" "12,16")]) 12389 12390(define_split 12391 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12392 (compare:CC 12393 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12394 (const_int 0)) 12395 (match_operand:SI 2 "gpc_reg_operand" "")) 12396 (const_int 0))) 12397 (clobber (match_scratch:SI 3 ""))] 12398 "! TARGET_POWERPC64 && reload_completed" 12399 [(set (match_dup 3) 12400 (plus:SI (gt:SI (match_dup 1) (const_int 0)) 12401 (match_dup 2))) 12402 (set (match_dup 0) 12403 (compare:CC (match_dup 3) 12404 (const_int 0)))] 12405 "") 12406 12407(define_insn "" 12408 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12409 (compare:CC 12410 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 12411 (const_int 0)) 12412 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 12413 (const_int 0))) 12414 (clobber (match_scratch:DI 3 "=&r,&r"))] 12415 "TARGET_POWERPC64" 12416 "@ 12417 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 12418 #" 12419 [(set_attr "type" "compare") 12420 (set_attr "length" "12,16")]) 12421 12422(define_split 12423 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12424 (compare:CC 12425 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 12426 (const_int 0)) 12427 (match_operand:DI 2 "gpc_reg_operand" "")) 12428 (const_int 0))) 12429 (clobber (match_scratch:DI 3 ""))] 12430 "TARGET_POWERPC64 && reload_completed" 12431 [(set (match_dup 3) 12432 (plus:DI (gt:DI (match_dup 1) (const_int 0)) 12433 (match_dup 2))) 12434 (set (match_dup 0) 12435 (compare:CC (match_dup 3) 12436 (const_int 0)))] 12437 "") 12438 12439(define_insn "" 12440 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12441 (compare:CC 12442 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12443 (const_int 0)) 12444 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 12445 (const_int 0))) 12446 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12447 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] 12448 "! TARGET_POWERPC64" 12449 "@ 12450 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 12451 #" 12452 [(set_attr "type" "compare") 12453 (set_attr "length" "12,16")]) 12454 12455(define_split 12456 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12457 (compare:CC 12458 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12459 (const_int 0)) 12460 (match_operand:SI 2 "gpc_reg_operand" "")) 12461 (const_int 0))) 12462 (set (match_operand:SI 0 "gpc_reg_operand" "") 12463 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] 12464 "! TARGET_POWERPC64 && reload_completed" 12465 [(set (match_dup 0) 12466 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) 12467 (set (match_dup 3) 12468 (compare:CC (match_dup 0) 12469 (const_int 0)))] 12470 "") 12471 12472(define_insn "" 12473 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12474 (compare:CC 12475 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 12476 (const_int 0)) 12477 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 12478 (const_int 0))) 12479 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") 12480 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] 12481 "TARGET_POWERPC64" 12482 "@ 12483 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 12484 #" 12485 [(set_attr "type" "compare") 12486 (set_attr "length" "12,16")]) 12487 12488(define_split 12489 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12490 (compare:CC 12491 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 12492 (const_int 0)) 12493 (match_operand:DI 2 "gpc_reg_operand" "")) 12494 (const_int 0))) 12495 (set (match_operand:DI 0 "gpc_reg_operand" "") 12496 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] 12497 "TARGET_POWERPC64 && reload_completed" 12498 [(set (match_dup 0) 12499 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) 12500 (set (match_dup 3) 12501 (compare:CC (match_dup 0) 12502 (const_int 0)))] 12503 "") 12504 12505(define_insn "" 12506 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") 12507 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12508 (match_operand:SI 2 "reg_or_short_operand" "r")) 12509 (match_operand:SI 3 "gpc_reg_operand" "r")))] 12510 "TARGET_POWER" 12511 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" 12512 [(set_attr "length" "12")]) 12513 12514(define_insn "" 12515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 12516 (compare:CC 12517 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12518 (match_operand:SI 2 "reg_or_short_operand" "r,r")) 12519 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12520 (const_int 0))) 12521 (clobber (match_scratch:SI 4 "=&r,&r"))] 12522 "TARGET_POWER" 12523 "@ 12524 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 12525 #" 12526 [(set_attr "type" "compare") 12527 (set_attr "length" "12,16")]) 12528 12529(define_split 12530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12531 (compare:CC 12532 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12533 (match_operand:SI 2 "reg_or_short_operand" "")) 12534 (match_operand:SI 3 "gpc_reg_operand" "")) 12535 (const_int 0))) 12536 (clobber (match_scratch:SI 4 ""))] 12537 "TARGET_POWER && reload_completed" 12538 [(set (match_dup 4) 12539 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12540 (set (match_dup 0) 12541 (compare:CC (match_dup 4) 12542 (const_int 0)))] 12543 "") 12544 12545(define_insn "" 12546 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 12547 (compare:CC 12548 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12549 (match_operand:SI 2 "reg_or_short_operand" "r,r")) 12550 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 12551 (const_int 0))) 12552 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12553 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12554 "TARGET_POWER" 12555 "@ 12556 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 12557 #" 12558 [(set_attr "type" "compare") 12559 (set_attr "length" "12,16")]) 12560 12561(define_split 12562 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12563 (compare:CC 12564 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 12565 (match_operand:SI 2 "reg_or_short_operand" "")) 12566 (match_operand:SI 3 "gpc_reg_operand" "")) 12567 (const_int 0))) 12568 (set (match_operand:SI 0 "gpc_reg_operand" "") 12569 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12570 "TARGET_POWER && reload_completed" 12571 [(set (match_dup 0) 12572 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12573 (set (match_dup 4) 12574 (compare:CC (match_dup 0) 12575 (const_int 0)))] 12576 "") 12577 12578(define_insn "" 12579 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12580 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12581 (const_int 0))))] 12582 "! TARGET_POWERPC64" 12583 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" 12584 [(set_attr "length" "12")]) 12585 12586(define_insn "" 12587 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 12588 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 12589 (const_int 0))))] 12590 "TARGET_POWERPC64" 12591 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" 12592 [(set_attr "length" "12")]) 12593 12594(define_insn "" 12595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12596 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12597 (match_operand:SI 2 "reg_or_short_operand" "r"))))] 12598 "TARGET_POWER" 12599 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" 12600 [(set_attr "length" "12")]) 12601 12602(define_insn "" 12603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12604 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12605 (match_operand:SI 2 "reg_or_short_operand" "rI")))] 12606 "! TARGET_POWERPC64" 12607 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" 12608 [(set_attr "length" "12")]) 12609 12610(define_insn "" 12611 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 12612 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") 12613 (match_operand:DI 2 "reg_or_short_operand" "rI")))] 12614 "TARGET_POWERPC64" 12615 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" 12616 [(set_attr "length" "12")]) 12617 12618(define_insn "" 12619 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12620 (compare:CC 12621 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12622 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 12623 (const_int 0))) 12624 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12625 (gtu:SI (match_dup 1) (match_dup 2)))] 12626 "! TARGET_POWERPC64" 12627 "@ 12628 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 12629 #" 12630 [(set_attr "type" "compare") 12631 (set_attr "length" "12,16")]) 12632 12633(define_split 12634 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12635 (compare:CC 12636 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12637 (match_operand:SI 2 "reg_or_short_operand" "")) 12638 (const_int 0))) 12639 (set (match_operand:SI 0 "gpc_reg_operand" "") 12640 (gtu:SI (match_dup 1) (match_dup 2)))] 12641 "! TARGET_POWERPC64 && reload_completed" 12642 [(set (match_dup 0) 12643 (gtu:SI (match_dup 1) (match_dup 2))) 12644 (set (match_dup 3) 12645 (compare:CC (match_dup 0) 12646 (const_int 0)))] 12647 "") 12648 12649(define_insn "" 12650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 12651 (compare:CC 12652 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 12653 (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) 12654 (const_int 0))) 12655 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 12656 (gtu:DI (match_dup 1) (match_dup 2)))] 12657 "TARGET_POWERPC64" 12658 "@ 12659 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 12660 #" 12661 [(set_attr "type" "compare") 12662 (set_attr "length" "12,16")]) 12663 12664(define_split 12665 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 12666 (compare:CC 12667 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") 12668 (match_operand:DI 2 "reg_or_short_operand" "")) 12669 (const_int 0))) 12670 (set (match_operand:DI 0 "gpc_reg_operand" "") 12671 (gtu:DI (match_dup 1) (match_dup 2)))] 12672 "TARGET_POWERPC64 && reload_completed" 12673 [(set (match_dup 0) 12674 (gtu:DI (match_dup 1) (match_dup 2))) 12675 (set (match_dup 3) 12676 (compare:CC (match_dup 0) 12677 (const_int 0)))] 12678 "") 12679 12680(define_insn "" 12681 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 12682 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 12683 (match_operand:SI 2 "reg_or_short_operand" "I,rI")) 12684 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))] 12685 "! TARGET_POWERPC64" 12686 "@ 12687 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 12688 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" 12689 [(set_attr "length" "8,12")]) 12690 12691(define_insn "" 12692 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") 12693 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 12694 (match_operand:DI 2 "reg_or_short_operand" "I,rI")) 12695 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] 12696 "TARGET_POWERPC64" 12697 "@ 12698 addic %0,%1,%k2\;addze %0,%3 12699 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" 12700 [(set_attr "length" "8,12")]) 12701 12702(define_insn "" 12703 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 12704 (compare:CC 12705 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12706 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) 12707 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12708 (const_int 0))) 12709 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 12710 "! TARGET_POWERPC64" 12711 "@ 12712 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 12713 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 12714 # 12715 #" 12716 [(set_attr "type" "compare") 12717 (set_attr "length" "8,12,12,16")]) 12718 12719(define_split 12720 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12721 (compare:CC 12722 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12723 (match_operand:SI 2 "reg_or_short_operand" "")) 12724 (match_operand:SI 3 "gpc_reg_operand" "")) 12725 (const_int 0))) 12726 (clobber (match_scratch:SI 4 ""))] 12727 "! TARGET_POWERPC64 && reload_completed" 12728 [(set (match_dup 4) 12729 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) 12730 (match_dup 3))) 12731 (set (match_dup 0) 12732 (compare:CC (match_dup 4) 12733 (const_int 0)))] 12734 "") 12735 12736(define_insn "" 12737 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 12738 (compare:CC 12739 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 12740 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) 12741 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) 12742 (const_int 0))) 12743 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] 12744 "TARGET_POWERPC64" 12745 "@ 12746 addic %4,%1,%k2\;addze. %4,%3 12747 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 12748 # 12749 #" 12750 [(set_attr "type" "compare") 12751 (set_attr "length" "8,12,12,16")]) 12752 12753(define_split 12754 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 12755 (compare:CC 12756 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") 12757 (match_operand:DI 2 "reg_or_short_operand" "")) 12758 (match_operand:DI 3 "gpc_reg_operand" "")) 12759 (const_int 0))) 12760 (clobber (match_scratch:DI 4 ""))] 12761 "TARGET_POWERPC64 && reload_completed" 12762 [(set (match_dup 4) 12763 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) 12764 (match_dup 3))) 12765 (set (match_dup 0) 12766 (compare:CC (match_dup 4) 12767 (const_int 0)))] 12768 "") 12769 12770(define_insn "" 12771 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12772 (compare:CC 12773 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 12774 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) 12775 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 12776 (const_int 0))) 12777 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12778 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12779 "! TARGET_POWERPC64" 12780 "@ 12781 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 12782 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 12783 # 12784 #" 12785 [(set_attr "type" "compare") 12786 (set_attr "length" "8,12,12,16")]) 12787 12788(define_split 12789 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12790 (compare:CC 12791 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") 12792 (match_operand:SI 2 "reg_or_short_operand" "")) 12793 (match_operand:SI 3 "gpc_reg_operand" "")) 12794 (const_int 0))) 12795 (set (match_operand:SI 0 "gpc_reg_operand" "") 12796 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12797 "! TARGET_POWERPC64 && reload_completed" 12798 [(set (match_dup 0) 12799 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 12800 (set (match_dup 4) 12801 (compare:CC (match_dup 0) 12802 (const_int 0)))] 12803 "") 12804 12805(define_insn "" 12806 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 12807 (compare:CC 12808 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 12809 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) 12810 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) 12811 (const_int 0))) 12812 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 12813 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12814 "TARGET_POWERPC64" 12815 "@ 12816 addic %0,%1,%k2\;addze. %0,%3 12817 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 12818 # 12819 #" 12820 [(set_attr "type" "compare") 12821 (set_attr "length" "8,12,12,16")]) 12822 12823(define_split 12824 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 12825 (compare:CC 12826 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") 12827 (match_operand:DI 2 "reg_or_short_operand" "")) 12828 (match_operand:DI 3 "gpc_reg_operand" "")) 12829 (const_int 0))) 12830 (set (match_operand:DI 0 "gpc_reg_operand" "") 12831 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 12832 "TARGET_POWERPC64 && reload_completed" 12833 [(set (match_dup 0) 12834 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) 12835 (set (match_dup 4) 12836 (compare:CC (match_dup 0) 12837 (const_int 0)))] 12838 "") 12839 12840(define_insn "" 12841 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12842 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") 12843 (match_operand:SI 2 "reg_or_short_operand" "rI"))))] 12844 "! TARGET_POWERPC64" 12845 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" 12846 [(set_attr "length" "8")]) 12847 12848(define_insn "" 12849 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 12850 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") 12851 (match_operand:DI 2 "reg_or_short_operand" "rI"))))] 12852 "TARGET_POWERPC64" 12853 "subf%I2c %0,%1,%2\;subfe %0,%0,%0" 12854 [(set_attr "length" "8")]) 12855 12856;; Define both directions of branch and return. If we need a reload 12857;; register, we'd rather use CR0 since it is much easier to copy a 12858;; register CC value to there. 12859 12860(define_insn "" 12861 [(set (pc) 12862 (if_then_else (match_operator 1 "branch_comparison_operator" 12863 [(match_operand 2 12864 "cc_reg_operand" "x,?y") 12865 (const_int 0)]) 12866 (label_ref (match_operand 0 "" "")) 12867 (pc)))] 12868 "" 12869 "* 12870{ 12871 return output_cbranch (operands[1], \"%l0\", 0, insn); 12872}" 12873 [(set_attr "type" "branch")]) 12874 12875(define_insn "" 12876 [(set (pc) 12877 (if_then_else (match_operator 0 "branch_comparison_operator" 12878 [(match_operand 1 12879 "cc_reg_operand" "x,?y") 12880 (const_int 0)]) 12881 (return) 12882 (pc)))] 12883 "direct_return ()" 12884 "* 12885{ 12886 return output_cbranch (operands[0], NULL, 0, insn); 12887}" 12888 [(set_attr "type" "branch") 12889 (set_attr "length" "4")]) 12890 12891(define_insn "" 12892 [(set (pc) 12893 (if_then_else (match_operator 1 "branch_comparison_operator" 12894 [(match_operand 2 12895 "cc_reg_operand" "x,?y") 12896 (const_int 0)]) 12897 (pc) 12898 (label_ref (match_operand 0 "" ""))))] 12899 "" 12900 "* 12901{ 12902 return output_cbranch (operands[1], \"%l0\", 1, insn); 12903}" 12904 [(set_attr "type" "branch")]) 12905 12906(define_insn "" 12907 [(set (pc) 12908 (if_then_else (match_operator 0 "branch_comparison_operator" 12909 [(match_operand 1 12910 "cc_reg_operand" "x,?y") 12911 (const_int 0)]) 12912 (pc) 12913 (return)))] 12914 "direct_return ()" 12915 "* 12916{ 12917 return output_cbranch (operands[0], NULL, 1, insn); 12918}" 12919 [(set_attr "type" "branch") 12920 (set_attr "length" "4")]) 12921 12922;; Logic on condition register values. 12923 12924; This pattern matches things like 12925; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) 12926; (eq:SI (reg:CCFP 68) (const_int 0))) 12927; (const_int 1))) 12928; which are generated by the branch logic. 12929 12930(define_insn "" 12931 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 12932 (compare:CCEQ (match_operator:SI 1 "boolean_operator" 12933 [(match_operator:SI 2 12934 "branch_positive_comparison_operator" 12935 [(match_operand 3 12936 "cc_reg_operand" "y") 12937 (const_int 0)]) 12938 (match_operator:SI 4 12939 "branch_positive_comparison_operator" 12940 [(match_operand 5 12941 "cc_reg_operand" "y") 12942 (const_int 0)])]) 12943 (const_int 1)))] 12944 "" 12945 "cr%q1 %E0,%j2,%j4" 12946 [(set_attr "type" "cr_logical")]) 12947 12948; Why is the constant -1 here, but 1 in the previous pattern? 12949; Because ~1 has all but the low bit set. 12950(define_insn "" 12951 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 12952 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" 12953 [(not:SI (match_operator:SI 2 12954 "branch_positive_comparison_operator" 12955 [(match_operand 3 12956 "cc_reg_operand" "y") 12957 (const_int 0)])) 12958 (match_operator:SI 4 12959 "branch_positive_comparison_operator" 12960 [(match_operand 5 12961 "cc_reg_operand" "y") 12962 (const_int 0)])]) 12963 (const_int -1)))] 12964 "" 12965 "cr%q1 %E0,%j2,%j4" 12966 [(set_attr "type" "cr_logical")]) 12967 12968(define_insn "" 12969 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 12970 (compare:CCEQ (match_operator:SI 1 12971 "branch_positive_comparison_operator" 12972 [(match_operand 2 12973 "cc_reg_operand" "y") 12974 (const_int 0)]) 12975 (const_int 0)))] 12976 "" 12977 "{crnor %E0,%j1,%j1|crnot %E0,%j1}" 12978 [(set_attr "type" "cr_logical")]) 12979 12980;; If we are comparing the result of two comparisons, this can be done 12981;; using creqv or crxor. 12982 12983(define_insn_and_split "" 12984 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 12985 (compare:CCEQ (match_operator 1 "branch_comparison_operator" 12986 [(match_operand 2 "cc_reg_operand" "y") 12987 (const_int 0)]) 12988 (match_operator 3 "branch_comparison_operator" 12989 [(match_operand 4 "cc_reg_operand" "y") 12990 (const_int 0)])))] 12991 "" 12992 "#" 12993 "" 12994 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) 12995 (match_dup 5)))] 12996 " 12997{ 12998 int positive_1, positive_2; 12999 13000 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); 13001 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); 13002 13003 if (! positive_1) 13004 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]), 13005 GET_CODE (operands[1])), 13006 SImode, 13007 operands[2], const0_rtx); 13008 else if (GET_MODE (operands[1]) != SImode) 13009 operands[1] = gen_rtx (GET_CODE (operands[1]), 13010 SImode, 13011 operands[2], const0_rtx); 13012 13013 if (! positive_2) 13014 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]), 13015 GET_CODE (operands[3])), 13016 SImode, 13017 operands[4], const0_rtx); 13018 else if (GET_MODE (operands[3]) != SImode) 13019 operands[3] = gen_rtx (GET_CODE (operands[3]), 13020 SImode, 13021 operands[4], const0_rtx); 13022 13023 if (positive_1 == positive_2) 13024 { 13025 operands[1] = gen_rtx_NOT (SImode, operands[1]); 13026 operands[5] = constm1_rtx; 13027 } 13028 else 13029 { 13030 operands[5] = const1_rtx; 13031 } 13032}") 13033 13034;; Unconditional branch and return. 13035 13036(define_insn "jump" 13037 [(set (pc) 13038 (label_ref (match_operand 0 "" "")))] 13039 "" 13040 "b %l0" 13041 [(set_attr "type" "branch")]) 13042 13043(define_insn "return" 13044 [(return)] 13045 "direct_return ()" 13046 "{br|blr}" 13047 [(set_attr "type" "jmpreg")]) 13048 13049(define_expand "indirect_jump" 13050 [(set (pc) (match_operand 0 "register_operand" ""))] 13051 "" 13052 " 13053{ 13054 if (TARGET_32BIT) 13055 emit_jump_insn (gen_indirect_jumpsi (operands[0])); 13056 else 13057 emit_jump_insn (gen_indirect_jumpdi (operands[0])); 13058 DONE; 13059}") 13060 13061(define_insn "indirect_jumpsi" 13062 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] 13063 "TARGET_32BIT" 13064 "@ 13065 bctr 13066 {br|blr}" 13067 [(set_attr "type" "jmpreg")]) 13068 13069(define_insn "indirect_jumpdi" 13070 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] 13071 "TARGET_64BIT" 13072 "@ 13073 bctr 13074 blr" 13075 [(set_attr "type" "jmpreg")]) 13076 13077;; Table jump for switch statements: 13078(define_expand "tablejump" 13079 [(use (match_operand 0 "" "")) 13080 (use (label_ref (match_operand 1 "" "")))] 13081 "" 13082 " 13083{ 13084 if (TARGET_32BIT) 13085 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); 13086 else 13087 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); 13088 DONE; 13089}") 13090 13091(define_expand "tablejumpsi" 13092 [(set (match_dup 3) 13093 (plus:SI (match_operand:SI 0 "" "") 13094 (match_dup 2))) 13095 (parallel [(set (pc) (match_dup 3)) 13096 (use (label_ref (match_operand 1 "" "")))])] 13097 "TARGET_32BIT" 13098 " 13099{ operands[0] = force_reg (SImode, operands[0]); 13100 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); 13101 operands[3] = gen_reg_rtx (SImode); 13102}") 13103 13104(define_expand "tablejumpdi" 13105 [(set (match_dup 4) 13106 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) 13107 (set (match_dup 3) 13108 (plus:DI (match_dup 4) 13109 (match_dup 2))) 13110 (parallel [(set (pc) (match_dup 3)) 13111 (use (label_ref (match_operand 1 "" "")))])] 13112 "TARGET_64BIT" 13113 " 13114{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); 13115 operands[3] = gen_reg_rtx (DImode); 13116 operands[4] = gen_reg_rtx (DImode); 13117}") 13118 13119(define_insn "" 13120 [(set (pc) 13121 (match_operand:SI 0 "register_operand" "c,*l")) 13122 (use (label_ref (match_operand 1 "" "")))] 13123 "TARGET_32BIT" 13124 "@ 13125 bctr 13126 {br|blr}" 13127 [(set_attr "type" "jmpreg")]) 13128 13129(define_insn "" 13130 [(set (pc) 13131 (match_operand:DI 0 "register_operand" "c,*l")) 13132 (use (label_ref (match_operand 1 "" "")))] 13133 "TARGET_64BIT" 13134 "@ 13135 bctr 13136 blr" 13137 [(set_attr "type" "jmpreg")]) 13138 13139(define_insn "nop" 13140 [(const_int 0)] 13141 "" 13142 "{cror 0,0,0|nop}") 13143 13144;; Define the subtract-one-and-jump insns, starting with the template 13145;; so loop.c knows what to generate. 13146 13147(define_expand "doloop_end" 13148 [(use (match_operand 0 "" "")) ; loop pseudo 13149 (use (match_operand 1 "" "")) ; iterations; zero if unknown 13150 (use (match_operand 2 "" "")) ; max iterations 13151 (use (match_operand 3 "" "")) ; loop level 13152 (use (match_operand 4 "" ""))] ; label 13153 "" 13154 " 13155{ 13156 /* Only use this on innermost loops. */ 13157 if (INTVAL (operands[3]) > 1) 13158 FAIL; 13159 if (TARGET_POWERPC64) 13160 { 13161 if (GET_MODE (operands[0]) != DImode) 13162 FAIL; 13163 emit_jump_insn (gen_ctrdi (operands[0], operands[4])); 13164 } 13165 else 13166 { 13167 if (GET_MODE (operands[0]) != SImode) 13168 FAIL; 13169 emit_jump_insn (gen_ctrsi (operands[0], operands[4])); 13170 } 13171 DONE; 13172}") 13173 13174(define_expand "ctrsi" 13175 [(parallel [(set (pc) 13176 (if_then_else (ne (match_operand:SI 0 "register_operand" "") 13177 (const_int 1)) 13178 (label_ref (match_operand 1 "" "")) 13179 (pc))) 13180 (set (match_dup 0) 13181 (plus:SI (match_dup 0) 13182 (const_int -1))) 13183 (clobber (match_scratch:CC 2 "")) 13184 (clobber (match_scratch:SI 3 ""))])] 13185 "! TARGET_POWERPC64" 13186 "") 13187 13188(define_expand "ctrdi" 13189 [(parallel [(set (pc) 13190 (if_then_else (ne (match_operand:DI 0 "register_operand" "") 13191 (const_int 1)) 13192 (label_ref (match_operand 1 "" "")) 13193 (pc))) 13194 (set (match_dup 0) 13195 (plus:DI (match_dup 0) 13196 (const_int -1))) 13197 (clobber (match_scratch:CC 2 "")) 13198 (clobber (match_scratch:DI 3 ""))])] 13199 "TARGET_POWERPC64" 13200 "") 13201 13202;; We need to be able to do this for any operand, including MEM, or we 13203;; will cause reload to blow up since we don't allow output reloads on 13204;; JUMP_INSNs. 13205;; For the length attribute to be calculated correctly, the 13206;; label MUST be operand 0. 13207 13208(define_insn "*ctrsi_internal1" 13209 [(set (pc) 13210 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") 13211 (const_int 1)) 13212 (label_ref (match_operand 0 "" "")) 13213 (pc))) 13214 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 13215 (plus:SI (match_dup 1) 13216 (const_int -1))) 13217 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13218 (clobber (match_scratch:SI 4 "=X,X,r"))] 13219 "! TARGET_POWERPC64" 13220 "* 13221{ 13222 if (which_alternative != 0) 13223 return \"#\"; 13224 else if (get_attr_length (insn) == 4) 13225 return \"{bdn|bdnz} %l0\"; 13226 else 13227 return \"bdz $+8\;b %l0\"; 13228}" 13229 [(set_attr "type" "branch") 13230 (set_attr "length" "*,12,16")]) 13231 13232(define_insn "*ctrsi_internal2" 13233 [(set (pc) 13234 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") 13235 (const_int 1)) 13236 (pc) 13237 (label_ref (match_operand 0 "" "")))) 13238 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 13239 (plus:SI (match_dup 1) 13240 (const_int -1))) 13241 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13242 (clobber (match_scratch:SI 4 "=X,X,r"))] 13243 "! TARGET_POWERPC64" 13244 "* 13245{ 13246 if (which_alternative != 0) 13247 return \"#\"; 13248 else if (get_attr_length (insn) == 4) 13249 return \"bdz %l0\"; 13250 else 13251 return \"{bdn|bdnz} $+8\;b %l0\"; 13252}" 13253 [(set_attr "type" "branch") 13254 (set_attr "length" "*,12,16")]) 13255 13256(define_insn "*ctrdi_internal1" 13257 [(set (pc) 13258 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") 13259 (const_int 1)) 13260 (label_ref (match_operand 0 "" "")) 13261 (pc))) 13262 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") 13263 (plus:DI (match_dup 1) 13264 (const_int -1))) 13265 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13266 (clobber (match_scratch:DI 4 "=X,X,r"))] 13267 "TARGET_POWERPC64" 13268 "* 13269{ 13270 if (which_alternative != 0) 13271 return \"#\"; 13272 else if (get_attr_length (insn) == 4) 13273 return \"{bdn|bdnz} %l0\"; 13274 else 13275 return \"bdz $+8\;b %l0\"; 13276}" 13277 [(set_attr "type" "branch") 13278 (set_attr "length" "*,12,16")]) 13279 13280(define_insn "*ctrdi_internal2" 13281 [(set (pc) 13282 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") 13283 (const_int 1)) 13284 (pc) 13285 (label_ref (match_operand 0 "" "")))) 13286 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") 13287 (plus:DI (match_dup 1) 13288 (const_int -1))) 13289 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13290 (clobber (match_scratch:DI 4 "=X,X,r"))] 13291 "TARGET_POWERPC64" 13292 "* 13293{ 13294 if (which_alternative != 0) 13295 return \"#\"; 13296 else if (get_attr_length (insn) == 4) 13297 return \"bdz %l0\"; 13298 else 13299 return \"{bdn|bdnz} $+8\;b %l0\"; 13300}" 13301 [(set_attr "type" "branch") 13302 (set_attr "length" "*,12,16")]) 13303 13304;; Similar, but we can use GE since we have a REG_NONNEG. 13305 13306(define_insn "*ctrsi_internal3" 13307 [(set (pc) 13308 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") 13309 (const_int 0)) 13310 (label_ref (match_operand 0 "" "")) 13311 (pc))) 13312 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 13313 (plus:SI (match_dup 1) 13314 (const_int -1))) 13315 (clobber (match_scratch:CC 3 "=X,&x,&X")) 13316 (clobber (match_scratch:SI 4 "=X,X,r"))] 13317 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" 13318 "* 13319{ 13320 if (which_alternative != 0) 13321 return \"#\"; 13322 else if (get_attr_length (insn) == 4) 13323 return \"{bdn|bdnz} %l0\"; 13324 else 13325 return \"bdz $+8\;b %l0\"; 13326}" 13327 [(set_attr "type" "branch") 13328 (set_attr "length" "*,12,16")]) 13329 13330(define_insn "*ctrsi_internal4" 13331 [(set (pc) 13332 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") 13333 (const_int 0)) 13334 (pc) 13335 (label_ref (match_operand 0 "" "")))) 13336 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 13337 (plus:SI (match_dup 1) 13338 (const_int -1))) 13339 (clobber (match_scratch:CC 3 "=X,&x,&X")) 13340 (clobber (match_scratch:SI 4 "=X,X,r"))] 13341 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" 13342 "* 13343{ 13344 if (which_alternative != 0) 13345 return \"#\"; 13346 else if (get_attr_length (insn) == 4) 13347 return \"bdz %l0\"; 13348 else 13349 return \"{bdn|bdnz} $+8\;b %l0\"; 13350}" 13351 [(set_attr "type" "branch") 13352 (set_attr "length" "*,12,16")]) 13353 13354(define_insn "*ctrdi_internal3" 13355 [(set (pc) 13356 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") 13357 (const_int 0)) 13358 (label_ref (match_operand 0 "" "")) 13359 (pc))) 13360 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") 13361 (plus:DI (match_dup 1) 13362 (const_int -1))) 13363 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13364 (clobber (match_scratch:DI 4 "=X,X,r"))] 13365 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" 13366 "* 13367{ 13368 if (which_alternative != 0) 13369 return \"#\"; 13370 else if (get_attr_length (insn) == 4) 13371 return \"{bdn|bdnz} %l0\"; 13372 else 13373 return \"bdz $+8\;b %l0\"; 13374}" 13375 [(set_attr "type" "branch") 13376 (set_attr "length" "*,12,16")]) 13377 13378(define_insn "*ctrdi_internal4" 13379 [(set (pc) 13380 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") 13381 (const_int 0)) 13382 (pc) 13383 (label_ref (match_operand 0 "" "")))) 13384 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") 13385 (plus:DI (match_dup 1) 13386 (const_int -1))) 13387 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13388 (clobber (match_scratch:DI 4 "=X,X,r"))] 13389 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" 13390 "* 13391{ 13392 if (which_alternative != 0) 13393 return \"#\"; 13394 else if (get_attr_length (insn) == 4) 13395 return \"bdz %l0\"; 13396 else 13397 return \"{bdn|bdnz} $+8\;b %l0\"; 13398}" 13399 [(set_attr "type" "branch") 13400 (set_attr "length" "*,12,16")]) 13401 13402;; Similar but use EQ 13403 13404(define_insn "*ctrsi_internal5" 13405 [(set (pc) 13406 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") 13407 (const_int 1)) 13408 (label_ref (match_operand 0 "" "")) 13409 (pc))) 13410 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 13411 (plus:SI (match_dup 1) 13412 (const_int -1))) 13413 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13414 (clobber (match_scratch:SI 4 "=X,X,r"))] 13415 "! TARGET_POWERPC64" 13416 "* 13417{ 13418 if (which_alternative != 0) 13419 return \"#\"; 13420 else if (get_attr_length (insn) == 4) 13421 return \"bdz %l0\"; 13422 else 13423 return \"{bdn|bdnz} $+8\;b %l0\"; 13424}" 13425 [(set_attr "type" "branch") 13426 (set_attr "length" "*,12,16")]) 13427 13428(define_insn "*ctrsi_internal6" 13429 [(set (pc) 13430 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") 13431 (const_int 1)) 13432 (pc) 13433 (label_ref (match_operand 0 "" "")))) 13434 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") 13435 (plus:SI (match_dup 1) 13436 (const_int -1))) 13437 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13438 (clobber (match_scratch:SI 4 "=X,X,r"))] 13439 "! TARGET_POWERPC64" 13440 "* 13441{ 13442 if (which_alternative != 0) 13443 return \"#\"; 13444 else if (get_attr_length (insn) == 4) 13445 return \"{bdn|bdnz} %l0\"; 13446 else 13447 return \"bdz $+8\;b %l0\"; 13448}" 13449 [(set_attr "type" "branch") 13450 (set_attr "length" "*,12,16")]) 13451 13452(define_insn "*ctrdi_internal5" 13453 [(set (pc) 13454 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") 13455 (const_int 1)) 13456 (label_ref (match_operand 0 "" "")) 13457 (pc))) 13458 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") 13459 (plus:DI (match_dup 1) 13460 (const_int -1))) 13461 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13462 (clobber (match_scratch:DI 4 "=X,X,r"))] 13463 "TARGET_POWERPC64" 13464 "* 13465{ 13466 if (which_alternative != 0) 13467 return \"#\"; 13468 else if (get_attr_length (insn) == 4) 13469 return \"bdz %l0\"; 13470 else 13471 return \"{bdn|bdnz} $+8\;b %l0\"; 13472}" 13473 [(set_attr "type" "branch") 13474 (set_attr "length" "*,12,16")]) 13475 13476(define_insn "*ctrdi_internal6" 13477 [(set (pc) 13478 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") 13479 (const_int 1)) 13480 (pc) 13481 (label_ref (match_operand 0 "" "")))) 13482 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") 13483 (plus:DI (match_dup 1) 13484 (const_int -1))) 13485 (clobber (match_scratch:CC 3 "=X,&x,&x")) 13486 (clobber (match_scratch:DI 4 "=X,X,r"))] 13487 "TARGET_POWERPC64" 13488 "* 13489{ 13490 if (which_alternative != 0) 13491 return \"#\"; 13492 else if (get_attr_length (insn) == 4) 13493 return \"{bdn|bdnz} %l0\"; 13494 else 13495 return \"bdz $+8\;b %l0\"; 13496}" 13497 [(set_attr "type" "branch") 13498 (set_attr "length" "*,12,16")]) 13499 13500;; Now the splitters if we could not allocate the CTR register 13501 13502(define_split 13503 [(set (pc) 13504 (if_then_else (match_operator 2 "comparison_operator" 13505 [(match_operand:SI 1 "gpc_reg_operand" "") 13506 (const_int 1)]) 13507 (match_operand 5 "" "") 13508 (match_operand 6 "" ""))) 13509 (set (match_operand:SI 0 "gpc_reg_operand" "") 13510 (plus:SI (match_dup 1) 13511 (const_int -1))) 13512 (clobber (match_scratch:CC 3 "")) 13513 (clobber (match_scratch:SI 4 ""))] 13514 "! TARGET_POWERPC64 && reload_completed" 13515 [(parallel [(set (match_dup 3) 13516 (compare:CC (plus:SI (match_dup 1) 13517 (const_int -1)) 13518 (const_int 0))) 13519 (set (match_dup 0) 13520 (plus:SI (match_dup 1) 13521 (const_int -1)))]) 13522 (set (pc) (if_then_else (match_dup 7) 13523 (match_dup 5) 13524 (match_dup 6)))] 13525 " 13526{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 13527 const0_rtx); }") 13528 13529(define_split 13530 [(set (pc) 13531 (if_then_else (match_operator 2 "comparison_operator" 13532 [(match_operand:SI 1 "gpc_reg_operand" "") 13533 (const_int 1)]) 13534 (match_operand 5 "" "") 13535 (match_operand 6 "" ""))) 13536 (set (match_operand:SI 0 "nonimmediate_operand" "") 13537 (plus:SI (match_dup 1) (const_int -1))) 13538 (clobber (match_scratch:CC 3 "")) 13539 (clobber (match_scratch:SI 4 ""))] 13540 "! TARGET_POWERPC64 && reload_completed 13541 && ! gpc_reg_operand (operands[0], SImode)" 13542 [(parallel [(set (match_dup 3) 13543 (compare:CC (plus:SI (match_dup 1) 13544 (const_int -1)) 13545 (const_int 0))) 13546 (set (match_dup 4) 13547 (plus:SI (match_dup 1) 13548 (const_int -1)))]) 13549 (set (match_dup 0) 13550 (match_dup 4)) 13551 (set (pc) (if_then_else (match_dup 7) 13552 (match_dup 5) 13553 (match_dup 6)))] 13554 " 13555{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 13556 const0_rtx); }") 13557(define_split 13558 [(set (pc) 13559 (if_then_else (match_operator 2 "comparison_operator" 13560 [(match_operand:DI 1 "gpc_reg_operand" "") 13561 (const_int 1)]) 13562 (match_operand 5 "" "") 13563 (match_operand 6 "" ""))) 13564 (set (match_operand:DI 0 "gpc_reg_operand" "") 13565 (plus:DI (match_dup 1) 13566 (const_int -1))) 13567 (clobber (match_scratch:CC 3 "")) 13568 (clobber (match_scratch:DI 4 ""))] 13569 "TARGET_POWERPC64 && reload_completed" 13570 [(parallel [(set (match_dup 3) 13571 (compare:CC (plus:DI (match_dup 1) 13572 (const_int -1)) 13573 (const_int 0))) 13574 (set (match_dup 0) 13575 (plus:DI (match_dup 1) 13576 (const_int -1)))]) 13577 (set (pc) (if_then_else (match_dup 7) 13578 (match_dup 5) 13579 (match_dup 6)))] 13580 " 13581{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 13582 const0_rtx); }") 13583 13584(define_split 13585 [(set (pc) 13586 (if_then_else (match_operator 2 "comparison_operator" 13587 [(match_operand:DI 1 "gpc_reg_operand" "") 13588 (const_int 1)]) 13589 (match_operand 5 "" "") 13590 (match_operand 6 "" ""))) 13591 (set (match_operand:DI 0 "nonimmediate_operand" "") 13592 (plus:DI (match_dup 1) (const_int -1))) 13593 (clobber (match_scratch:CC 3 "")) 13594 (clobber (match_scratch:DI 4 ""))] 13595 "TARGET_POWERPC64 && reload_completed 13596 && ! gpc_reg_operand (operands[0], DImode)" 13597 [(parallel [(set (match_dup 3) 13598 (compare:CC (plus:DI (match_dup 1) 13599 (const_int -1)) 13600 (const_int 0))) 13601 (set (match_dup 4) 13602 (plus:DI (match_dup 1) 13603 (const_int -1)))]) 13604 (set (match_dup 0) 13605 (match_dup 4)) 13606 (set (pc) (if_then_else (match_dup 7) 13607 (match_dup 5) 13608 (match_dup 6)))] 13609 " 13610{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], 13611 const0_rtx); }") 13612 13613 13614(define_insn "trap" 13615 [(trap_if (const_int 1) (const_int 0))] 13616 "" 13617 "{t 31,0,0|trap}") 13618 13619(define_expand "conditional_trap" 13620 [(trap_if (match_operator 0 "trap_comparison_operator" 13621 [(match_dup 2) (match_dup 3)]) 13622 (match_operand 1 "const_int_operand" ""))] 13623 "" 13624 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; 13625 operands[2] = rs6000_compare_op0; 13626 operands[3] = rs6000_compare_op1;") 13627 13628(define_insn "" 13629 [(trap_if (match_operator 0 "trap_comparison_operator" 13630 [(match_operand:SI 1 "register_operand" "r") 13631 (match_operand:SI 2 "reg_or_short_operand" "rI")]) 13632 (const_int 0))] 13633 "" 13634 "{t|tw}%V0%I2 %1,%2") 13635 13636(define_insn "" 13637 [(trap_if (match_operator 0 "trap_comparison_operator" 13638 [(match_operand:DI 1 "register_operand" "r") 13639 (match_operand:DI 2 "reg_or_short_operand" "rI")]) 13640 (const_int 0))] 13641 "TARGET_POWERPC64" 13642 "td%V0%I2 %1,%2") 13643 13644;; Insns related to generating the function prologue and epilogue. 13645 13646(define_expand "prologue" 13647 [(use (const_int 0))] 13648 "TARGET_SCHED_PROLOG" 13649 " 13650{ 13651 rs6000_emit_prologue (); 13652 DONE; 13653}") 13654 13655(define_insn "movesi_from_cr" 13656 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13657 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) 13658 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] 13659 "" 13660 "mfcr %0") 13661 13662(define_insn "*stmw" 13663 [(match_parallel 0 "stmw_operation" 13664 [(set (match_operand:SI 1 "memory_operand" "=m") 13665 (match_operand:SI 2 "gpc_reg_operand" "r"))])] 13666 "TARGET_MULTIPLE" 13667 "{stm|stmw} %2,%1") 13668 13669(define_insn "*save_fpregs_si" 13670 [(match_parallel 0 "any_operand" 13671 [(clobber (match_operand:SI 1 "register_operand" "=l")) 13672 (use (match_operand:SI 2 "call_operand" "s")) 13673 (set (match_operand:DF 3 "memory_operand" "=m") 13674 (match_operand:DF 4 "gpc_reg_operand" "f"))])] 13675 "TARGET_32BIT" 13676 "bl %z2") 13677 13678(define_insn "*save_fpregs_di" 13679 [(match_parallel 0 "any_operand" 13680 [(clobber (match_operand:DI 1 "register_operand" "=l")) 13681 (use (match_operand:DI 2 "call_operand" "s")) 13682 (set (match_operand:DF 3 "memory_operand" "=m") 13683 (match_operand:DF 4 "gpc_reg_operand" "f"))])] 13684 "TARGET_64BIT" 13685 "bl %z2") 13686 13687; These are to explain that changes to the stack pointer should 13688; not be moved over stores to stack memory. 13689(define_insn "stack_tie" 13690 [(set (match_operand:BLK 0 "memory_operand" "+m") 13691 (unspec:BLK [(match_dup 0)] 5))] 13692 "" 13693 "" 13694 [(set_attr "length" "0")]) 13695 13696 13697(define_expand "epilogue" 13698 [(use (const_int 0))] 13699 "TARGET_SCHED_PROLOG" 13700 " 13701{ 13702 rs6000_emit_epilogue (FALSE); 13703 DONE; 13704}") 13705 13706; On some processors, doing the mtcrf one CC register at a time is 13707; faster (like on the 604e). On others, doing them all at once is 13708; faster; for instance, on the 601 and 750. 13709 13710(define_expand "movsi_to_cr_one" 13711 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 13712 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 13713 (match_dup 2)] 20))] 13714 "" 13715 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") 13716 13717(define_insn "*movsi_to_cr" 13718 [(match_parallel 0 "mtcrf_operation" 13719 [(set (match_operand:CC 1 "cc_reg_operand" "=y") 13720 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") 13721 (match_operand 3 "immediate_operand" "n")] 13722 20))])] 13723 "" 13724 "* 13725{ 13726 int mask = 0; 13727 int i; 13728 for (i = 0; i < XVECLEN (operands[0], 0); i++) 13729 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); 13730 operands[4] = GEN_INT (mask); 13731 return \"mtcrf %4,%2\"; 13732}") 13733 13734(define_insn "" 13735 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 13736 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 13737 (match_operand 2 "immediate_operand" "n")] 20))] 13738 "GET_CODE (operands[0]) == REG 13739 && CR_REGNO_P (REGNO (operands[0])) 13740 && GET_CODE (operands[2]) == CONST_INT 13741 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" 13742 "mtcrf %R0,%1") 13743 13744; The load-multiple instructions have similar properties. 13745; Note that "load_multiple" is a name known to the machine-independent 13746; code that actually corresponds to the powerpc load-string. 13747 13748(define_insn "*lmw" 13749 [(match_parallel 0 "lmw_operation" 13750 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 13751 (match_operand:SI 2 "memory_operand" "m"))])] 13752 "TARGET_MULTIPLE" 13753 "{lm|lmw} %1,%2") 13754 13755(define_insn "*return_internal_si" 13756 [(return) 13757 (use (match_operand:SI 0 "register_operand" "lc"))] 13758 "TARGET_32BIT" 13759 "b%T0" 13760 [(set_attr "type" "jmpreg")]) 13761 13762(define_insn "*return_internal_di" 13763 [(return) 13764 (use (match_operand:DI 0 "register_operand" "lc"))] 13765 "TARGET_64BIT" 13766 "b%T0" 13767 [(set_attr "type" "jmpreg")]) 13768 13769; FIXME: This would probably be somewhat simpler if the Cygnus sibcall 13770; stuff was in GCC. Oh, and "any_operand" is a bit flexible... 13771 13772(define_insn "*return_and_restore_fpregs_si" 13773 [(match_parallel 0 "any_operand" 13774 [(return) 13775 (use (match_operand:SI 1 "register_operand" "l")) 13776 (use (match_operand:SI 2 "call_operand" "s")) 13777 (set (match_operand:DF 3 "gpc_reg_operand" "=f") 13778 (match_operand:DF 4 "memory_operand" "m"))])] 13779 "TARGET_32BIT" 13780 "b %z2") 13781 13782(define_insn "*return_and_restore_fpregs_di" 13783 [(match_parallel 0 "any_operand" 13784 [(return) 13785 (use (match_operand:DI 1 "register_operand" "l")) 13786 (use (match_operand:DI 2 "call_operand" "s")) 13787 (set (match_operand:DF 3 "gpc_reg_operand" "=f") 13788 (match_operand:DF 4 "memory_operand" "m"))])] 13789 "TARGET_64BIT" 13790 "b %z2") 13791 13792; This is used in compiling the unwind routines. 13793(define_expand "eh_return" 13794 [(use (match_operand 0 "general_operand" "")) 13795 (use (match_operand 1 "general_operand" ""))] 13796 "" 13797 " 13798{ 13799#if TARGET_AIX 13800 rs6000_emit_eh_toc_restore (operands[0]); 13801#endif 13802 if (TARGET_32BIT) 13803 emit_insn (gen_eh_set_lr_si (operands[1])); 13804 else 13805 emit_insn (gen_eh_set_lr_di (operands[1])); 13806 emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); 13807 DONE; 13808}") 13809 13810; We can't expand this before we know where the link register is stored. 13811(define_insn "eh_set_lr_si" 13812 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9) 13813 (clobber (match_scratch:SI 1 "=&b"))] 13814 "TARGET_32BIT" 13815 "#") 13816 13817(define_insn "eh_set_lr_di" 13818 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9) 13819 (clobber (match_scratch:DI 1 "=&b"))] 13820 "TARGET_64BIT" 13821 "#") 13822 13823(define_split 13824 [(unspec_volatile [(match_operand 0 "register_operand" "")] 9) 13825 (clobber (match_scratch 1 ""))] 13826 "reload_completed" 13827 [(const_int 0)] 13828 " 13829{ 13830 rs6000_stack_t *info = rs6000_stack_info (); 13831 13832 if (info->lr_save_p) 13833 { 13834 rtx frame_rtx = stack_pointer_rtx; 13835 int sp_offset = 0; 13836 rtx tmp; 13837 13838 if (frame_pointer_needed 13839 || current_function_calls_alloca 13840 || info->total_size > 32767) 13841 { 13842 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); 13843 frame_rtx = operands[1]; 13844 } 13845 else if (info->push_p) 13846 sp_offset = info->total_size; 13847 13848 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); 13849 tmp = gen_rtx_MEM (Pmode, tmp); 13850 emit_move_insn (tmp, operands[0]); 13851 } 13852 else 13853 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); 13854 DONE; 13855}") 13856 13857(define_insn "prefetch" 13858 [(prefetch (match_operand:V4SI 0 "address_operand" "p") 13859 (match_operand:SI 1 "const_int_operand" "n") 13860 (match_operand:SI 2 "const_int_operand" "n"))] 13861 "TARGET_POWERPC" 13862 "* 13863{ 13864 if (GET_CODE (operands[0]) == REG) 13865 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; 13866 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; 13867}" 13868 [(set_attr "type" "load")]) 13869 13870;; AltiVec patterns 13871 13872;; Generic LVX load instruction. 13873(define_insn "altivec_lvx_4si" 13874 [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") 13875 (match_operand:V4SI 1 "memory_operand" "m"))] 13876 "TARGET_ALTIVEC" 13877 "lvx %0,%y1" 13878 [(set_attr "type" "vecload")]) 13879 13880(define_insn "altivec_lvx_8hi" 13881 [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") 13882 (match_operand:V8HI 1 "memory_operand" "m"))] 13883 "TARGET_ALTIVEC" 13884 "lvx %0,%y1" 13885 [(set_attr "type" "vecload")]) 13886 13887(define_insn "altivec_lvx_16qi" 13888 [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") 13889 (match_operand:V16QI 1 "memory_operand" "m"))] 13890 "TARGET_ALTIVEC" 13891 "lvx %0,%y1" 13892 [(set_attr "type" "vecload")]) 13893 13894(define_insn "altivec_lvx_4sf" 13895 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") 13896 (match_operand:V4SF 1 "memory_operand" "m"))] 13897 "TARGET_ALTIVEC" 13898 "lvx %0,%y1" 13899 [(set_attr "type" "vecload")]) 13900 13901;; Generic STVX store instruction. 13902(define_insn "altivec_stvx_4si" 13903 [(set (match_operand:V4SI 0 "memory_operand" "=m") 13904 (match_operand:V4SI 1 "altivec_register_operand" "v"))] 13905 "TARGET_ALTIVEC" 13906 "stvx %1,%y0" 13907 [(set_attr "type" "vecstore")]) 13908 13909(define_insn "altivec_stvx_8hi" 13910 [(set (match_operand:V8HI 0 "memory_operand" "=m") 13911 (match_operand:V8HI 1 "altivec_register_operand" "v"))] 13912 "TARGET_ALTIVEC" 13913 "stvx %1,%y0" 13914 [(set_attr "type" "vecstore")]) 13915 13916(define_insn "altivec_stvx_16qi" 13917 [(set (match_operand:V16QI 0 "memory_operand" "=m") 13918 (match_operand:V16QI 1 "altivec_register_operand" "v"))] 13919 "TARGET_ALTIVEC" 13920 "stvx %1,%y0" 13921 [(set_attr "type" "vecstore")]) 13922 13923(define_insn "altivec_stvx_4sf" 13924 [(set (match_operand:V4SF 0 "memory_operand" "=m") 13925 (match_operand:V4SF 1 "altivec_register_operand" "v"))] 13926 "TARGET_ALTIVEC" 13927 "stvx %1,%y0" 13928 [(set_attr "type" "vecstore")]) 13929 13930;; Vector move instructions. 13931(define_expand "movv4si" 13932 [(set (match_operand:V4SI 0 "nonimmediate_operand" "") 13933 (match_operand:V4SI 1 "any_operand" ""))] 13934 "TARGET_ALTIVEC" 13935 "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }") 13936 13937(define_insn "*movv4si_internal" 13938 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r") 13939 (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r"))] 13940 "TARGET_ALTIVEC" 13941 "@ 13942 stvx %1,%y0 13943 lvx %0,%y1 13944 vor %0,%1,%1 13945 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 13946 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 13947 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" 13948 [(set_attr "type" "altivec") 13949 (set_attr "length" "*,*,*,16,16,16")]) 13950 13951(define_expand "movv8hi" 13952 [(set (match_operand:V8HI 0 "nonimmediate_operand" "") 13953 (match_operand:V8HI 1 "any_operand" ""))] 13954 "TARGET_ALTIVEC" 13955 "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }") 13956 13957(define_insn "*movv8hi_internal1" 13958 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r") 13959 (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r"))] 13960 "TARGET_ALTIVEC" 13961 "@ 13962 stvx %1,%y0 13963 lvx %0,%y1 13964 vor %0,%1,%1 13965 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 13966 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 13967 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" 13968 [(set_attr "type" "altivec") 13969 (set_attr "length" "*,*,*,16,16,16")]) 13970 13971(define_expand "movv16qi" 13972 [(set (match_operand:V16QI 0 "nonimmediate_operand" "") 13973 (match_operand:V16QI 1 "any_operand" ""))] 13974 "TARGET_ALTIVEC" 13975 "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }") 13976 13977(define_insn "*movv16qi_internal1" 13978 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r") 13979 (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r"))] 13980 "TARGET_ALTIVEC" 13981 "@ 13982 stvx %1,%y0 13983 lvx %0,%y1 13984 vor %0,%1,%1 13985 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 13986 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 13987 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" 13988 [(set_attr "type" "altivec") 13989 (set_attr "length" "*,*,*,16,16,16")]) 13990 13991(define_expand "movv4sf" 13992 [(set (match_operand:V4SF 0 "nonimmediate_operand" "") 13993 (match_operand:V4SF 1 "any_operand" ""))] 13994 "TARGET_ALTIVEC" 13995 "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }") 13996 13997(define_insn "*movv4sf_internal1" 13998 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r") 13999 (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r"))] 14000 "TARGET_ALTIVEC" 14001 "@ 14002 stvx %1,%y0 14003 lvx %0,%y1 14004 vor %0,%1,%1 14005 stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 14006 lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 14007 mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" 14008 [(set_attr "type" "altivec") 14009 (set_attr "length" "*,*,*,16,16,16")]) 14010 14011(define_insn "get_vrsave_internal" 14012 [(set (match_operand:SI 0 "register_operand" "=r") 14013 (unspec:SI [(reg:SI 109)] 214))] 14014 "TARGET_ALTIVEC" 14015 "* 14016{ 14017 if (TARGET_MACHO) 14018 return \"mtspr 256,%0\"; 14019 else 14020 return \"mtvrsave %0\"; 14021}" 14022 [(set_attr "type" "altivec")]) 14023 14024(define_insn "*set_vrsave_internal" 14025 [(match_parallel 0 "vrsave_operation" 14026 [(set (reg:SI 109) 14027 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") 14028 (reg:SI 109)] 30))])] 14029 "TARGET_ALTIVEC" 14030 "* 14031{ 14032 if (TARGET_MACHO) 14033 return \"mfspr %1,256\"; 14034 else 14035 return \"mtvrsave %1\"; 14036}" 14037 [(set_attr "type" "altivec")]) 14038 14039;; Vector clears 14040(define_insn "*movv4si_const0" 14041 [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") 14042 (match_operand:V4SI 1 "zero_constant" ""))] 14043 "TARGET_ALTIVEC" 14044 "vxor %0,%0,%0" 14045 [(set_attr "type" "vecsimple")]) 14046 14047(define_insn "*movv4sf_const0" 14048 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") 14049 (match_operand:V4SF 1 "zero_constant" ""))] 14050 14051 "TARGET_ALTIVEC" 14052 "vxor %0,%0,%0" 14053 [(set_attr "type" "vecsimple")]) 14054 14055(define_insn "*movv8hi_const0" 14056 [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") 14057 (match_operand:V8HI 1 "zero_constant" ""))] 14058 "TARGET_ALTIVEC" 14059 "vxor %0,%0,%0" 14060 [(set_attr "type" "vecsimple")]) 14061 14062(define_insn "*movv16qi_const0" 14063 [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") 14064 (match_operand:V16QI 1 "zero_constant" ""))] 14065 "TARGET_ALTIVEC" 14066 "vxor %0,%0,%0" 14067 [(set_attr "type" "vecsimple")]) 14068 14069;; Simple binary operations. 14070 14071(define_insn "addv16qi3" 14072 [(set (match_operand:V16QI 0 "register_operand" "=v") 14073 (plus:V16QI (match_operand:V16QI 1 "register_operand" "v") 14074 (match_operand:V16QI 2 "register_operand" "v")))] 14075 "TARGET_ALTIVEC" 14076 "vaddubm %0,%1,%2" 14077 [(set_attr "type" "vecsimple")]) 14078 14079(define_insn "addv8hi3" 14080 [(set (match_operand:V8HI 0 "register_operand" "=v") 14081 (plus:V8HI (match_operand:V8HI 1 "register_operand" "v") 14082 (match_operand:V8HI 2 "register_operand" "v")))] 14083 "TARGET_ALTIVEC" 14084 "vadduhm %0,%1,%2" 14085 [(set_attr "type" "vecsimple")]) 14086 14087(define_insn "addv4si3" 14088 [(set (match_operand:V4SI 0 "register_operand" "=v") 14089 (plus:V4SI (match_operand:V4SI 1 "register_operand" "v") 14090 (match_operand:V4SI 2 "register_operand" "v")))] 14091 "TARGET_ALTIVEC" 14092 "vadduwm %0,%1,%2" 14093 [(set_attr "type" "vecsimple")]) 14094 14095(define_insn "addv4sf3" 14096 [(set (match_operand:V4SF 0 "register_operand" "=v") 14097 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v") 14098 (match_operand:V4SF 2 "register_operand" "v")))] 14099 "TARGET_ALTIVEC" 14100 "vaddfp %0,%1,%2" 14101 [(set_attr "type" "vecfloat")]) 14102 14103(define_insn "altivec_vaddcuw" 14104 [(set (match_operand:V4SI 0 "register_operand" "=v") 14105 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14106 (match_operand:V4SI 2 "register_operand" "v")] 35))] 14107 "TARGET_ALTIVEC" 14108 "vaddcuw %0,%1,%2" 14109 [(set_attr "type" "vecsimple")]) 14110 14111(define_insn "altivec_vaddubs" 14112 [(set (match_operand:V16QI 0 "register_operand" "=v") 14113 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14114 (match_operand:V16QI 2 "register_operand" "v")] 36))] 14115 "TARGET_ALTIVEC" 14116 "vaddubs %0,%1,%2" 14117 [(set_attr "type" "vecsimple")]) 14118 14119(define_insn "altivec_vaddsbs" 14120 [(set (match_operand:V16QI 0 "register_operand" "=v") 14121 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14122 (match_operand:V16QI 2 "register_operand" "v")] 37))] 14123 "TARGET_ALTIVEC" 14124 "vaddsbs %0,%1,%2" 14125 [(set_attr "type" "vecsimple")]) 14126 14127(define_insn "altivec_vadduhs" 14128 [(set (match_operand:V8HI 0 "register_operand" "=v") 14129 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14130 (match_operand:V8HI 2 "register_operand" "v")] 38))] 14131 "TARGET_ALTIVEC" 14132 "vadduhs %0,%1,%2" 14133 [(set_attr "type" "vecsimple")]) 14134 14135(define_insn "altivec_vaddshs" 14136 [(set (match_operand:V8HI 0 "register_operand" "=v") 14137 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14138 (match_operand:V8HI 2 "register_operand" "v")] 39))] 14139 "TARGET_ALTIVEC" 14140 "vaddshs %0,%1,%2" 14141 [(set_attr "type" "vecsimple")]) 14142 14143(define_insn "altivec_vadduws" 14144 [(set (match_operand:V4SI 0 "register_operand" "=v") 14145 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14146 (match_operand:V4SI 2 "register_operand" "v")] 40))] 14147 "TARGET_ALTIVEC" 14148 "vadduws %0,%1,%2" 14149 [(set_attr "type" "vecsimple")]) 14150 14151(define_insn "altivec_vaddsws" 14152 [(set (match_operand:V4SI 0 "register_operand" "=v") 14153 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14154 (match_operand:V4SI 2 "register_operand" "v")] 41))] 14155 "TARGET_ALTIVEC" 14156 "vaddsws %0,%1,%2" 14157 [(set_attr "type" "vecsimple")]) 14158 14159(define_insn "andv4si3" 14160 [(set (match_operand:V4SI 0 "register_operand" "=v") 14161 (and:V4SI (match_operand:V4SI 1 "register_operand" "v") 14162 (match_operand:V4SI 2 "register_operand" "v")))] 14163 "TARGET_ALTIVEC" 14164 "vand %0,%1,%2" 14165 [(set_attr "type" "vecsimple")]) 14166 14167(define_insn "altivec_vandc" 14168 [(set (match_operand:V4SI 0 "register_operand" "=v") 14169 (and:V4SI (match_operand:V4SI 1 "register_operand" "v") 14170 (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))] 14171 "TARGET_ALTIVEC" 14172 "vandc %0,%1,%2" 14173 [(set_attr "type" "vecsimple")]) 14174 14175(define_insn "altivec_vavgub" 14176 [(set (match_operand:V16QI 0 "register_operand" "=v") 14177 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14178 (match_operand:V16QI 2 "register_operand" "v")] 44))] 14179 "TARGET_ALTIVEC" 14180 "vavgub %0,%1,%2" 14181 [(set_attr "type" "vecsimple")]) 14182 14183(define_insn "altivec_vavgsb" 14184 [(set (match_operand:V16QI 0 "register_operand" "=v") 14185 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14186 (match_operand:V16QI 2 "register_operand" "v")] 45))] 14187 "TARGET_ALTIVEC" 14188 "vavgsb %0,%1,%2" 14189 [(set_attr "type" "vecsimple")]) 14190 14191(define_insn "altivec_vavguh" 14192 [(set (match_operand:V8HI 0 "register_operand" "=v") 14193 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14194 (match_operand:V8HI 2 "register_operand" "v")] 46))] 14195 "TARGET_ALTIVEC" 14196 "vavguh %0,%1,%2" 14197 [(set_attr "type" "vecsimple")]) 14198 14199(define_insn "altivec_vavgsh" 14200 [(set (match_operand:V8HI 0 "register_operand" "=v") 14201 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14202 (match_operand:V8HI 2 "register_operand" "v")] 47))] 14203 "TARGET_ALTIVEC" 14204 "vavgsh %0,%1,%2" 14205 [(set_attr "type" "vecsimple")]) 14206 14207(define_insn "altivec_vavguw" 14208 [(set (match_operand:V4SI 0 "register_operand" "=v") 14209 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14210 (match_operand:V4SI 2 "register_operand" "v")] 48))] 14211 "TARGET_ALTIVEC" 14212 "vavguw %0,%1,%2" 14213 [(set_attr "type" "vecsimple")]) 14214 14215(define_insn "altivec_vavgsw" 14216 [(set (match_operand:V4SI 0 "register_operand" "=v") 14217 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14218 (match_operand:V4SI 2 "register_operand" "v")] 49))] 14219 "TARGET_ALTIVEC" 14220 "vavgsw %0,%1,%2" 14221 [(set_attr "type" "vecsimple")]) 14222 14223(define_insn "altivec_vcmpbfp" 14224 [(set (match_operand:V4SI 0 "register_operand" "=v") 14225 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 14226 (match_operand:V4SF 2 "register_operand" "v")] 50))] 14227 "TARGET_ALTIVEC" 14228 "vcmpbfp %0,%1,%2" 14229 [(set_attr "type" "veccmp")]) 14230 14231(define_insn "altivec_vcmpequb" 14232 [(set (match_operand:V16QI 0 "register_operand" "=v") 14233 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14234 (match_operand:V16QI 2 "register_operand" "v")] 51))] 14235 "TARGET_ALTIVEC" 14236 "vcmpequb %0,%1,%2" 14237 [(set_attr "type" "vecsimple")]) 14238 14239(define_insn "altivec_vcmpequh" 14240 [(set (match_operand:V8HI 0 "register_operand" "=v") 14241 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14242 (match_operand:V8HI 2 "register_operand" "v")] 52))] 14243 "TARGET_ALTIVEC" 14244 "vcmpequh %0,%1,%2" 14245 [(set_attr "type" "vecsimple")]) 14246 14247(define_insn "altivec_vcmpequw" 14248 [(set (match_operand:V4SI 0 "register_operand" "=v") 14249 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14250 (match_operand:V4SI 2 "register_operand" "v")] 53))] 14251 "TARGET_ALTIVEC" 14252 "vcmpequw %0,%1,%2" 14253 [(set_attr "type" "vecsimple")]) 14254 14255(define_insn "altivec_vcmpeqfp" 14256 [(set (match_operand:V4SI 0 "register_operand" "=v") 14257 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 14258 (match_operand:V4SF 2 "register_operand" "v")] 54))] 14259 "TARGET_ALTIVEC" 14260 "vcmpeqfp %0,%1,%2" 14261 [(set_attr "type" "veccmp")]) 14262 14263(define_insn "altivec_vcmpgefp" 14264 [(set (match_operand:V4SI 0 "register_operand" "=v") 14265 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 14266 (match_operand:V4SF 2 "register_operand" "v")] 55))] 14267 "TARGET_ALTIVEC" 14268 "vcmpgefp %0,%1,%2" 14269 [(set_attr "type" "veccmp")]) 14270 14271(define_insn "altivec_vcmpgtub" 14272 [(set (match_operand:V16QI 0 "register_operand" "=v") 14273 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14274 (match_operand:V16QI 2 "register_operand" "v")] 56))] 14275 "TARGET_ALTIVEC" 14276 "vcmpgtub %0,%1,%2" 14277 [(set_attr "type" "vecsimple")]) 14278 14279(define_insn "altivec_vcmpgtsb" 14280 [(set (match_operand:V16QI 0 "register_operand" "=v") 14281 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14282 (match_operand:V16QI 2 "register_operand" "v")] 57))] 14283 "TARGET_ALTIVEC" 14284 "vcmpgtsb %0,%1,%2" 14285 [(set_attr "type" "vecsimple")]) 14286 14287(define_insn "altivec_vcmpgtuh" 14288 [(set (match_operand:V8HI 0 "register_operand" "=v") 14289 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14290 (match_operand:V8HI 2 "register_operand" "v")] 58))] 14291 "TARGET_ALTIVEC" 14292 "vcmpgtuh %0,%1,%2" 14293 [(set_attr "type" "vecsimple")]) 14294 14295(define_insn "altivec_vcmpgtsh" 14296 [(set (match_operand:V8HI 0 "register_operand" "=v") 14297 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14298 (match_operand:V8HI 2 "register_operand" "v")] 59))] 14299 "TARGET_ALTIVEC" 14300 "vcmpgtsh %0,%1,%2" 14301 [(set_attr "type" "vecsimple")]) 14302 14303(define_insn "altivec_vcmpgtuw" 14304 [(set (match_operand:V4SI 0 "register_operand" "=v") 14305 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14306 (match_operand:V4SI 2 "register_operand" "v")] 60))] 14307 "TARGET_ALTIVEC" 14308 "vcmpgtuw %0,%1,%2" 14309 [(set_attr "type" "vecsimple")]) 14310 14311(define_insn "altivec_vcmpgtsw" 14312 [(set (match_operand:V4SI 0 "register_operand" "=v") 14313 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14314 (match_operand:V4SI 2 "register_operand" "v")] 61))] 14315 "TARGET_ALTIVEC" 14316 "vcmpgtsw %0,%1,%2" 14317 [(set_attr "type" "vecsimple")]) 14318 14319(define_insn "altivec_vcmpgtfp" 14320 [(set (match_operand:V4SI 0 "register_operand" "=v") 14321 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 14322 (match_operand:V4SF 2 "register_operand" "v")] 62))] 14323 "TARGET_ALTIVEC" 14324 "vcmpgtfp %0,%1,%2" 14325 [(set_attr "type" "veccmp")]) 14326 14327;; Fused multiply add 14328(define_insn "altivec_vmaddfp" 14329 [(set (match_operand:V4SF 0 "register_operand" "=v") 14330 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") 14331 (match_operand:V4SF 2 "register_operand" "v")) 14332 (match_operand:V4SF 3 "register_operand" "v")))] 14333 "TARGET_ALTIVEC" 14334 "vmaddfp %0,%1,%2,%3" 14335 [(set_attr "type" "vecfloat")]) 14336 14337;; The unspec here is a vec splat of 0. We do multiply as a fused 14338;; multiply-add with an add of a 0 vector. 14339 14340(define_expand "mulv4sf3" 14341 [(set (match_dup 3) (unspec:V4SF [(const_int 0)] 142)) 14342 (set (match_operand:V4SF 0 "register_operand" "=v") 14343 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") 14344 (match_operand:V4SF 2 "register_operand" "v")) 14345 (match_dup 3)))] 14346 "TARGET_ALTIVEC && TARGET_FUSED_MADD" 14347 " 14348{ operands[3] = gen_reg_rtx (V4SFmode); }") 14349 14350;; Fused multiply subtract 14351(define_insn "altivec_vnmsubfp" 14352 [(set (match_operand:V4SF 0 "register_operand" "=v") 14353 (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") 14354 (match_operand:V4SF 2 "register_operand" "v")) 14355 (match_operand:V4SF 3 "register_operand" "v")))] 14356 "TARGET_ALTIVEC" 14357 "vnmsubfp %0,%1,%2,%3" 14358 [(set_attr "type" "vecfloat")]) 14359 14360 14361(define_insn "altivec_vmsumubm" 14362 [(set (match_operand:V4SI 0 "register_operand" "=v") 14363 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") 14364 (match_operand:V16QI 2 "register_operand" "v") 14365 (match_operand:V4SI 3 "register_operand" "v")] 65))] 14366 "TARGET_ALTIVEC" 14367 "vmsumubm %0, %1, %2, %3" 14368 [(set_attr "type" "veccomplex")]) 14369 14370(define_insn "altivec_vmsummbm" 14371 [(set (match_operand:V4SI 0 "register_operand" "=v") 14372 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") 14373 (match_operand:V16QI 2 "register_operand" "v") 14374 (match_operand:V4SI 3 "register_operand" "v")] 66))] 14375 "TARGET_ALTIVEC" 14376 "vmsumubm %0, %1, %2, %3" 14377 [(set_attr "type" "veccomplex")]) 14378 14379(define_insn "altivec_vmsumuhm" 14380 [(set (match_operand:V4SI 0 "register_operand" "=v") 14381 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 14382 (match_operand:V8HI 2 "register_operand" "v") 14383 (match_operand:V4SI 3 "register_operand" "v")] 67))] 14384 "TARGET_ALTIVEC" 14385 "vmsumuhm %0, %1, %2, %3" 14386 [(set_attr "type" "veccomplex")]) 14387 14388(define_insn "altivec_vmsumshm" 14389 [(set (match_operand:V4SI 0 "register_operand" "=v") 14390 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 14391 (match_operand:V8HI 2 "register_operand" "v") 14392 (match_operand:V4SI 3 "register_operand" "v")] 68))] 14393 "TARGET_ALTIVEC" 14394 "vmsumshm %0, %1, %2, %3" 14395 [(set_attr "type" "veccomplex")]) 14396 14397(define_insn "altivec_vmsumuhs" 14398 [(set (match_operand:V4SI 0 "register_operand" "=v") 14399 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 14400 (match_operand:V8HI 2 "register_operand" "v") 14401 (match_operand:V4SI 3 "register_operand" "v")] 69))] 14402 "TARGET_ALTIVEC" 14403 "vmsumuhs %0, %1, %2, %3" 14404 [(set_attr "type" "veccomplex")]) 14405 14406(define_insn "altivec_vmsumshs" 14407 [(set (match_operand:V4SI 0 "register_operand" "=v") 14408 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 14409 (match_operand:V8HI 2 "register_operand" "v") 14410 (match_operand:V4SI 3 "register_operand" "v")] 70))] 14411 "TARGET_ALTIVEC" 14412 "vmsumshs %0, %1, %2, %3" 14413 [(set_attr "type" "veccomplex")]) 14414 14415(define_insn "umaxv16qi3" 14416 [(set (match_operand:V16QI 0 "register_operand" "=v") 14417 (umax:V16QI (match_operand:V16QI 1 "register_operand" "v") 14418 (match_operand:V16QI 2 "register_operand" "v")))] 14419 "TARGET_ALTIVEC" 14420 "vmaxub %0,%1,%2" 14421 [(set_attr "type" "vecsimple")]) 14422 14423(define_insn "smaxv16qi3" 14424 [(set (match_operand:V16QI 0 "register_operand" "=v") 14425 (smax:V16QI (match_operand:V16QI 1 "register_operand" "v") 14426 (match_operand:V16QI 2 "register_operand" "v")))] 14427 "TARGET_ALTIVEC" 14428 "vmaxsb %0,%1,%2" 14429 [(set_attr "type" "vecsimple")]) 14430 14431(define_insn "umaxv8hi3" 14432 [(set (match_operand:V8HI 0 "register_operand" "=v") 14433 (umax:V8HI (match_operand:V8HI 1 "register_operand" "v") 14434 (match_operand:V8HI 2 "register_operand" "v")))] 14435 "TARGET_ALTIVEC" 14436 "vmaxuh %0,%1,%2" 14437 [(set_attr "type" "vecsimple")]) 14438 14439(define_insn "smaxv8hi3" 14440 [(set (match_operand:V8HI 0 "register_operand" "=v") 14441 (smax:V8HI (match_operand:V8HI 1 "register_operand" "v") 14442 (match_operand:V8HI 2 "register_operand" "v")))] 14443 "TARGET_ALTIVEC" 14444 "vmaxsh %0,%1,%2" 14445 [(set_attr "type" "vecsimple")]) 14446 14447(define_insn "umaxv4si3" 14448 [(set (match_operand:V4SI 0 "register_operand" "=v") 14449 (umax:V4SI (match_operand:V4SI 1 "register_operand" "v") 14450 (match_operand:V4SI 2 "register_operand" "v")))] 14451 "TARGET_ALTIVEC" 14452 "vmaxuw %0,%1,%2" 14453 [(set_attr "type" "vecsimple")]) 14454 14455(define_insn "smaxv4si3" 14456 [(set (match_operand:V4SI 0 "register_operand" "=v") 14457 (smax:V4SI (match_operand:V4SI 1 "register_operand" "v") 14458 (match_operand:V4SI 2 "register_operand" "v")))] 14459 "TARGET_ALTIVEC" 14460 "vmaxsw %0,%1,%2" 14461 [(set_attr "type" "vecsimple")]) 14462 14463(define_insn "smaxv4sf3" 14464 [(set (match_operand:V4SF 0 "register_operand" "=v") 14465 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v") 14466 (match_operand:V4SF 2 "register_operand" "v")))] 14467 "TARGET_ALTIVEC" 14468 "vmaxfp %0,%1,%2" 14469 [(set_attr "type" "veccmp")]) 14470 14471(define_insn "altivec_vmhaddshs" 14472 [(set (match_operand:V8HI 0 "register_operand" "=v") 14473 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14474 (match_operand:V8HI 2 "register_operand" "v") 14475 (match_operand:V8HI 3 "register_operand" "v")] 71))] 14476 "TARGET_ALTIVEC" 14477 "vmhaddshs %0, %1, %2, %3" 14478 [(set_attr "type" "veccomplex")]) 14479(define_insn "altivec_vmhraddshs" 14480 [(set (match_operand:V8HI 0 "register_operand" "=v") 14481 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14482 (match_operand:V8HI 2 "register_operand" "v") 14483 (match_operand:V8HI 3 "register_operand" "v")] 72))] 14484 "TARGET_ALTIVEC" 14485 "vmhraddshs %0, %1, %2, %3" 14486 [(set_attr "type" "veccomplex")]) 14487(define_insn "altivec_vmladduhm" 14488 [(set (match_operand:V8HI 0 "register_operand" "=v") 14489 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14490 (match_operand:V8HI 2 "register_operand" "v") 14491 (match_operand:V8HI 3 "register_operand" "v")] 73))] 14492 "TARGET_ALTIVEC" 14493 "vmladduhm %0, %1, %2, %3" 14494 [(set_attr "type" "veccomplex")]) 14495 14496(define_insn "altivec_vmrghb" 14497 [(set (match_operand:V16QI 0 "register_operand" "=v") 14498 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v") 14499 (parallel [(const_int 8) 14500 (const_int 9) 14501 (const_int 10) 14502 (const_int 11) 14503 (const_int 12) 14504 (const_int 13) 14505 (const_int 14) 14506 (const_int 15) 14507 (const_int 0) 14508 (const_int 1) 14509 (const_int 2) 14510 (const_int 3) 14511 (const_int 4) 14512 (const_int 5) 14513 (const_int 6) 14514 (const_int 7)])) 14515 (match_operand:V16QI 2 "register_operand" "v") 14516 (const_int 255)))] 14517 "TARGET_ALTIVEC" 14518 "vmrghb %0,%1,%2" 14519 [(set_attr "type" "vecperm")]) 14520 14521(define_insn "altivec_vmrghh" 14522 [(set (match_operand:V8HI 0 "register_operand" "=v") 14523 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v") 14524 (parallel [(const_int 4) 14525 (const_int 5) 14526 (const_int 6) 14527 (const_int 7) 14528 (const_int 0) 14529 (const_int 1) 14530 (const_int 2) 14531 (const_int 3)])) 14532 (match_operand:V8HI 2 "register_operand" "v") 14533 (const_int 15)))] 14534 "TARGET_ALTIVEC" 14535 "vmrghh %0,%1,%2" 14536 [(set_attr "type" "vecperm")]) 14537 14538(define_insn "altivec_vmrghw" 14539 [(set (match_operand:V4SI 0 "register_operand" "=v") 14540 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v") 14541 (parallel [(const_int 2) 14542 (const_int 3) 14543 (const_int 0) 14544 (const_int 1)])) 14545 (match_operand:V4SI 2 "register_operand" "v") 14546 (const_int 12)))] 14547 "TARGET_ALTIVEC" 14548 "vmrghw %0,%1,%2" 14549 [(set_attr "type" "vecperm")]) 14550 14551(define_insn "altivec_vmrglb" 14552 [(set (match_operand:V16QI 0 "register_operand" "=v") 14553 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v") 14554 (parallel [(const_int 8) 14555 (const_int 9) 14556 (const_int 10) 14557 (const_int 11) 14558 (const_int 12) 14559 (const_int 13) 14560 (const_int 14) 14561 (const_int 15) 14562 (const_int 0) 14563 (const_int 1) 14564 (const_int 2) 14565 (const_int 3) 14566 (const_int 4) 14567 (const_int 5) 14568 (const_int 6) 14569 (const_int 7)])) 14570 (match_operand:V16QI 1 "register_operand" "v") 14571 (const_int 255)))] 14572 "TARGET_ALTIVEC" 14573 "vmrglb %0,%1,%2" 14574 [(set_attr "type" "vecperm")]) 14575 14576(define_insn "altivec_vmrglh" 14577 [(set (match_operand:V8HI 0 "register_operand" "=v") 14578 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v") 14579 (parallel [(const_int 4) 14580 (const_int 5) 14581 (const_int 6) 14582 (const_int 7) 14583 (const_int 0) 14584 (const_int 1) 14585 (const_int 2) 14586 (const_int 3)])) 14587 (match_operand:V8HI 1 "register_operand" "v") 14588 (const_int 15)))] 14589 "TARGET_ALTIVEC" 14590 "vmrglh %0,%1,%2" 14591 [(set_attr "type" "vecperm")]) 14592 14593(define_insn "altivec_vmrglw" 14594 [(set (match_operand:V4SI 0 "register_operand" "=v") 14595 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v") 14596 (parallel [(const_int 2) 14597 (const_int 3) 14598 (const_int 0) 14599 (const_int 1)])) 14600 (match_operand:V4SI 1 "register_operand" "v") 14601 (const_int 12)))] 14602 "TARGET_ALTIVEC" 14603 "vmrglw %0,%1,%2" 14604 [(set_attr "type" "vecperm")]) 14605 14606(define_insn "uminv16qi3" 14607 [(set (match_operand:V16QI 0 "register_operand" "=v") 14608 (umin:V16QI (match_operand:V16QI 1 "register_operand" "v") 14609 (match_operand:V16QI 2 "register_operand" "v")))] 14610 "TARGET_ALTIVEC" 14611 "vminub %0,%1,%2" 14612 [(set_attr "type" "vecsimple")]) 14613 14614(define_insn "sminv16qi3" 14615 [(set (match_operand:V16QI 0 "register_operand" "=v") 14616 (smin:V16QI (match_operand:V16QI 1 "register_operand" "v") 14617 (match_operand:V16QI 2 "register_operand" "v")))] 14618 "TARGET_ALTIVEC" 14619 "vminsb %0,%1,%2" 14620 [(set_attr "type" "vecsimple")]) 14621 14622(define_insn "uminv8hi3" 14623 [(set (match_operand:V8HI 0 "register_operand" "=v") 14624 (umin:V8HI (match_operand:V8HI 1 "register_operand" "v") 14625 (match_operand:V8HI 2 "register_operand" "v")))] 14626 "TARGET_ALTIVEC" 14627 "vminuh %0,%1,%2" 14628 [(set_attr "type" "vecsimple")]) 14629 14630(define_insn "sminv8hi3" 14631 [(set (match_operand:V8HI 0 "register_operand" "=v") 14632 (smin:V8HI (match_operand:V8HI 1 "register_operand" "v") 14633 (match_operand:V8HI 2 "register_operand" "v")))] 14634 "TARGET_ALTIVEC" 14635 "vminsh %0,%1,%2" 14636 [(set_attr "type" "vecsimple")]) 14637 14638(define_insn "uminv4si3" 14639 [(set (match_operand:V4SI 0 "register_operand" "=v") 14640 (umin:V4SI (match_operand:V4SI 1 "register_operand" "v") 14641 (match_operand:V4SI 2 "register_operand" "v")))] 14642 "TARGET_ALTIVEC" 14643 "vminuw %0,%1,%2" 14644 [(set_attr "type" "vecsimple")]) 14645 14646(define_insn "sminv4si3" 14647 [(set (match_operand:V4SI 0 "register_operand" "=v") 14648 (smin:V4SI (match_operand:V4SI 1 "register_operand" "v") 14649 (match_operand:V4SI 2 "register_operand" "v")))] 14650 "TARGET_ALTIVEC" 14651 "vminsw %0,%1,%2" 14652 [(set_attr "type" "vecsimple")]) 14653 14654(define_insn "sminv4sf3" 14655 [(set (match_operand:V4SF 0 "register_operand" "=v") 14656 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v") 14657 (match_operand:V4SF 2 "register_operand" "v")))] 14658 "TARGET_ALTIVEC" 14659 "vminfp %0,%1,%2" 14660 [(set_attr "type" "veccmp")]) 14661 14662(define_insn "altivec_vmuleub" 14663 [(set (match_operand:V8HI 0 "register_operand" "=v") 14664 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 14665 (match_operand:V16QI 2 "register_operand" "v")] 83))] 14666 "TARGET_ALTIVEC" 14667 "vmuleub %0,%1,%2" 14668 [(set_attr "type" "veccomplex")]) 14669 14670(define_insn "altivec_vmulesb" 14671 [(set (match_operand:V8HI 0 "register_operand" "=v") 14672 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 14673 (match_operand:V16QI 2 "register_operand" "v")] 84))] 14674 "TARGET_ALTIVEC" 14675 "vmulesb %0,%1,%2" 14676 [(set_attr "type" "veccomplex")]) 14677 14678(define_insn "altivec_vmuleuh" 14679 [(set (match_operand:V4SI 0 "register_operand" "=v") 14680 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 14681 (match_operand:V8HI 2 "register_operand" "v")] 85))] 14682 "TARGET_ALTIVEC" 14683 "vmuleuh %0,%1,%2" 14684 [(set_attr "type" "veccomplex")]) 14685 14686(define_insn "altivec_vmulesh" 14687 [(set (match_operand:V4SI 0 "register_operand" "=v") 14688 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 14689 (match_operand:V8HI 2 "register_operand" "v")] 86))] 14690 "TARGET_ALTIVEC" 14691 "vmulesh %0,%1,%2" 14692 [(set_attr "type" "veccomplex")]) 14693 14694(define_insn "altivec_vmuloub" 14695 [(set (match_operand:V8HI 0 "register_operand" "=v") 14696 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 14697 (match_operand:V16QI 2 "register_operand" "v")] 87))] 14698 "TARGET_ALTIVEC" 14699 "vmuloub %0,%1,%2" 14700 [(set_attr "type" "veccomplex")]) 14701 14702(define_insn "altivec_vmulosb" 14703 [(set (match_operand:V8HI 0 "register_operand" "=v") 14704 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") 14705 (match_operand:V16QI 2 "register_operand" "v")] 88))] 14706 "TARGET_ALTIVEC" 14707 "vmulosb %0,%1,%2" 14708 [(set_attr "type" "veccomplex")]) 14709 14710(define_insn "altivec_vmulouh" 14711 [(set (match_operand:V4SI 0 "register_operand" "=v") 14712 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 14713 (match_operand:V8HI 2 "register_operand" "v")] 89))] 14714 "TARGET_ALTIVEC" 14715 "vmulouh %0,%1,%2" 14716 [(set_attr "type" "veccomplex")]) 14717 14718(define_insn "altivec_vmulosh" 14719 [(set (match_operand:V4SI 0 "register_operand" "=v") 14720 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 14721 (match_operand:V8HI 2 "register_operand" "v")] 90))] 14722 "TARGET_ALTIVEC" 14723 "vmulosh %0,%1,%2" 14724 [(set_attr "type" "veccomplex")]) 14725 14726(define_insn "altivec_vnor" 14727 [(set (match_operand:V4SI 0 "register_operand" "=v") 14728 (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") 14729 (match_operand:V4SI 2 "register_operand" "v"))))] 14730 "TARGET_ALTIVEC" 14731 "vnor %0,%1,%2" 14732 [(set_attr "type" "vecsimple")]) 14733 14734(define_insn "iorv4si3" 14735 [(set (match_operand:V4SI 0 "register_operand" "=v") 14736 (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") 14737 (match_operand:V4SI 2 "register_operand" "v")))] 14738 "TARGET_ALTIVEC" 14739 "vor %0,%1,%2" 14740 [(set_attr "type" "vecsimple")]) 14741 14742(define_insn "altivec_vpkuhum" 14743 [(set (match_operand:V16QI 0 "register_operand" "=v") 14744 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 14745 (match_operand:V8HI 2 "register_operand" "v")] 93))] 14746 "TARGET_ALTIVEC" 14747 "vpkuhum %0,%1,%2" 14748 [(set_attr "type" "vecperm")]) 14749 14750(define_insn "altivec_vpkuwum" 14751 [(set (match_operand:V8HI 0 "register_operand" "=v") 14752 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 14753 (match_operand:V4SI 2 "register_operand" "v")] 94))] 14754 "TARGET_ALTIVEC" 14755 "vpkuwum %0,%1,%2" 14756 [(set_attr "type" "vecperm")]) 14757 14758(define_insn "altivec_vpkpx" 14759 [(set (match_operand:V8HI 0 "register_operand" "=v") 14760 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 14761 (match_operand:V4SI 2 "register_operand" "v")] 95))] 14762 "TARGET_ALTIVEC" 14763 "vpkpx %0,%1,%2" 14764 [(set_attr "type" "vecperm")]) 14765 14766(define_insn "altivec_vpkuhss" 14767 [(set (match_operand:V16QI 0 "register_operand" "=v") 14768 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 14769 (match_operand:V8HI 2 "register_operand" "v")] 96))] 14770 "TARGET_ALTIVEC" 14771 "vpkuhss %0,%1,%2" 14772 [(set_attr "type" "vecperm")]) 14773 14774(define_insn "altivec_vpkshss" 14775 [(set (match_operand:V16QI 0 "register_operand" "=v") 14776 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 14777 (match_operand:V8HI 2 "register_operand" "v")] 97))] 14778 "TARGET_ALTIVEC" 14779 "vpkshss %0,%1,%2" 14780 [(set_attr "type" "vecperm")]) 14781 14782(define_insn "altivec_vpkuwss" 14783 [(set (match_operand:V8HI 0 "register_operand" "=v") 14784 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 14785 (match_operand:V4SI 2 "register_operand" "v")] 98))] 14786 "TARGET_ALTIVEC" 14787 "vpkuwss %0,%1,%2" 14788 [(set_attr "type" "vecperm")]) 14789 14790(define_insn "altivec_vpkswss" 14791 [(set (match_operand:V8HI 0 "register_operand" "=v") 14792 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 14793 (match_operand:V4SI 2 "register_operand" "v")] 99))] 14794 "TARGET_ALTIVEC" 14795 "vpkswss %0,%1,%2" 14796 [(set_attr "type" "vecperm")]) 14797 14798(define_insn "altivec_vpkuhus" 14799 [(set (match_operand:V16QI 0 "register_operand" "=v") 14800 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 14801 (match_operand:V8HI 2 "register_operand" "v")] 100))] 14802 "TARGET_ALTIVEC" 14803 "vpkuhus %0,%1,%2" 14804 [(set_attr "type" "vecperm")]) 14805 14806(define_insn "altivec_vpkshus" 14807 [(set (match_operand:V16QI 0 "register_operand" "=v") 14808 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") 14809 (match_operand:V8HI 2 "register_operand" "v")] 101))] 14810 "TARGET_ALTIVEC" 14811 "vpkshus %0,%1,%2" 14812 [(set_attr "type" "vecperm")]) 14813 14814(define_insn "altivec_vpkuwus" 14815 [(set (match_operand:V8HI 0 "register_operand" "=v") 14816 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 14817 (match_operand:V4SI 2 "register_operand" "v")] 102))] 14818 "TARGET_ALTIVEC" 14819 "vpkuwus %0,%1,%2" 14820 [(set_attr "type" "vecperm")]) 14821 14822(define_insn "altivec_vpkswus" 14823 [(set (match_operand:V8HI 0 "register_operand" "=v") 14824 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") 14825 (match_operand:V4SI 2 "register_operand" "v")] 103))] 14826 "TARGET_ALTIVEC" 14827 "vpkswus %0,%1,%2" 14828 [(set_attr "type" "vecperm")]) 14829 14830(define_insn "altivec_vrlb" 14831 [(set (match_operand:V16QI 0 "register_operand" "=v") 14832 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14833 (match_operand:V16QI 2 "register_operand" "v")] 104))] 14834 "TARGET_ALTIVEC" 14835 "vrlb %0,%1,%2" 14836 [(set_attr "type" "vecsimple")]) 14837 14838(define_insn "altivec_vrlh" 14839 [(set (match_operand:V8HI 0 "register_operand" "=v") 14840 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14841 (match_operand:V8HI 2 "register_operand" "v")] 105))] 14842 "TARGET_ALTIVEC" 14843 "vrlh %0,%1,%2" 14844 [(set_attr "type" "vecsimple")]) 14845 14846(define_insn "altivec_vrlw" 14847 [(set (match_operand:V4SI 0 "register_operand" "=v") 14848 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14849 (match_operand:V4SI 2 "register_operand" "v")] 106))] 14850 "TARGET_ALTIVEC" 14851 "vrlw %0,%1,%2" 14852 [(set_attr "type" "vecsimple")]) 14853 14854(define_insn "altivec_vslb" 14855 [(set (match_operand:V16QI 0 "register_operand" "=v") 14856 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14857 (match_operand:V16QI 2 "register_operand" "v")] 107))] 14858 "TARGET_ALTIVEC" 14859 "vslb %0,%1,%2" 14860 [(set_attr "type" "vecsimple")]) 14861 14862(define_insn "altivec_vslh" 14863 [(set (match_operand:V8HI 0 "register_operand" "=v") 14864 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14865 (match_operand:V8HI 2 "register_operand" "v")] 108))] 14866 "TARGET_ALTIVEC" 14867 "vslh %0,%1,%2" 14868 [(set_attr "type" "vecsimple")]) 14869 14870(define_insn "altivec_vslw" 14871 [(set (match_operand:V4SI 0 "register_operand" "=v") 14872 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14873 (match_operand:V4SI 2 "register_operand" "v")] 109))] 14874 "TARGET_ALTIVEC" 14875 "vslw %0,%1,%2" 14876 [(set_attr "type" "vecsimple")]) 14877 14878(define_insn "altivec_vsl" 14879 [(set (match_operand:V4SI 0 "register_operand" "=v") 14880 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14881 (match_operand:V4SI 2 "register_operand" "v")] 110))] 14882 "TARGET_ALTIVEC" 14883 "vsl %0,%1,%2" 14884 [(set_attr "type" "vecperm")]) 14885 14886(define_insn "altivec_vslo" 14887 [(set (match_operand:V4SI 0 "register_operand" "=v") 14888 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14889 (match_operand:V4SI 2 "register_operand" "v")] 111))] 14890 "TARGET_ALTIVEC" 14891 "vslo %0,%1,%2" 14892 [(set_attr "type" "vecperm")]) 14893 14894(define_insn "altivec_vsrb" 14895 [(set (match_operand:V16QI 0 "register_operand" "=v") 14896 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14897 (match_operand:V16QI 2 "register_operand" "v")] 112))] 14898 "TARGET_ALTIVEC" 14899 "vsrb %0,%1,%2" 14900 [(set_attr "type" "vecsimple")]) 14901 14902(define_insn "altivec_vsrh" 14903 [(set (match_operand:V8HI 0 "register_operand" "=v") 14904 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14905 (match_operand:V8HI 2 "register_operand" "v")] 113))] 14906 "TARGET_ALTIVEC" 14907 "vsrh %0,%1,%2" 14908 [(set_attr "type" "vecsimple")]) 14909 14910(define_insn "altivec_vsrw" 14911 [(set (match_operand:V4SI 0 "register_operand" "=v") 14912 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14913 (match_operand:V4SI 2 "register_operand" "v")] 114))] 14914 "TARGET_ALTIVEC" 14915 "vsrw %0,%1,%2" 14916 [(set_attr "type" "vecsimple")]) 14917 14918(define_insn "altivec_vsrab" 14919 [(set (match_operand:V16QI 0 "register_operand" "=v") 14920 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 14921 (match_operand:V16QI 2 "register_operand" "v")] 115))] 14922 "TARGET_ALTIVEC" 14923 "vsrab %0,%1,%2" 14924 [(set_attr "type" "vecsimple")]) 14925 14926(define_insn "altivec_vsrah" 14927 [(set (match_operand:V8HI 0 "register_operand" "=v") 14928 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 14929 (match_operand:V8HI 2 "register_operand" "v")] 116))] 14930 "TARGET_ALTIVEC" 14931 "vsrah %0,%1,%2" 14932 [(set_attr "type" "vecsimple")]) 14933 14934(define_insn "altivec_vsraw" 14935 [(set (match_operand:V4SI 0 "register_operand" "=v") 14936 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14937 (match_operand:V4SI 2 "register_operand" "v")] 117))] 14938 "TARGET_ALTIVEC" 14939 "vsraw %0,%1,%2" 14940 [(set_attr "type" "vecsimple")]) 14941 14942(define_insn "altivec_vsr" 14943 [(set (match_operand:V4SI 0 "register_operand" "=v") 14944 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14945 (match_operand:V4SI 2 "register_operand" "v")] 118))] 14946 "TARGET_ALTIVEC" 14947 "vsr %0,%1,%2" 14948 [(set_attr "type" "vecperm")]) 14949 14950(define_insn "altivec_vsro" 14951 [(set (match_operand:V4SI 0 "register_operand" "=v") 14952 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14953 (match_operand:V4SI 2 "register_operand" "v")] 119))] 14954 "TARGET_ALTIVEC" 14955 "vsro %0,%1,%2" 14956 [(set_attr "type" "vecperm")]) 14957 14958(define_insn "subv16qi3" 14959 [(set (match_operand:V16QI 0 "register_operand" "=v") 14960 (minus:V16QI (match_operand:V16QI 1 "register_operand" "v") 14961 (match_operand:V16QI 2 "register_operand" "v")))] 14962 "TARGET_ALTIVEC" 14963 "vsububm %0,%1,%2" 14964 [(set_attr "type" "vecsimple")]) 14965 14966(define_insn "subv8hi3" 14967 [(set (match_operand:V8HI 0 "register_operand" "=v") 14968 (minus:V8HI (match_operand:V8HI 1 "register_operand" "v") 14969 (match_operand:V8HI 2 "register_operand" "v")))] 14970 "TARGET_ALTIVEC" 14971 "vsubuhm %0,%1,%2" 14972 [(set_attr "type" "vecsimple")]) 14973 14974(define_insn "subv4si3" 14975 [(set (match_operand:V4SI 0 "register_operand" "=v") 14976 (minus:V4SI (match_operand:V4SI 1 "register_operand" "v") 14977 (match_operand:V4SI 2 "register_operand" "v")))] 14978 "TARGET_ALTIVEC" 14979 "vsubuwm %0,%1,%2" 14980 [(set_attr "type" "vecsimple")]) 14981 14982(define_insn "subv4sf3" 14983 [(set (match_operand:V4SF 0 "register_operand" "=v") 14984 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v") 14985 (match_operand:V4SF 2 "register_operand" "v")))] 14986 "TARGET_ALTIVEC" 14987 "vsubfp %0,%1,%2" 14988 [(set_attr "type" "vecfloat")]) 14989 14990(define_insn "altivec_vsubcuw" 14991 [(set (match_operand:V4SI 0 "register_operand" "=v") 14992 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 14993 (match_operand:V4SI 2 "register_operand" "v")] 124))] 14994 "TARGET_ALTIVEC" 14995 "vsubcuw %0,%1,%2" 14996 [(set_attr "type" "vecsimple")]) 14997 14998(define_insn "altivec_vsububs" 14999 [(set (match_operand:V16QI 0 "register_operand" "=v") 15000 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 15001 (match_operand:V16QI 2 "register_operand" "v")] 125))] 15002 "TARGET_ALTIVEC" 15003 "vsububs %0,%1,%2" 15004 [(set_attr "type" "vecsimple")]) 15005 15006(define_insn "altivec_vsubsbs" 15007 [(set (match_operand:V16QI 0 "register_operand" "=v") 15008 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 15009 (match_operand:V16QI 2 "register_operand" "v")] 126))] 15010 "TARGET_ALTIVEC" 15011 "vsubsbs %0,%1,%2" 15012 [(set_attr "type" "vecsimple")]) 15013 15014(define_insn "altivec_vsubuhs" 15015 [(set (match_operand:V8HI 0 "register_operand" "=v") 15016 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 15017 (match_operand:V8HI 2 "register_operand" "v")] 127))] 15018 "TARGET_ALTIVEC" 15019 "vsubuhs %0,%1,%2" 15020 [(set_attr "type" "vecsimple")]) 15021 15022(define_insn "altivec_vsubshs" 15023 [(set (match_operand:V8HI 0 "register_operand" "=v") 15024 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 15025 (match_operand:V8HI 2 "register_operand" "v")] 128))] 15026 "TARGET_ALTIVEC" 15027 "vsubshs %0,%1,%2" 15028 [(set_attr "type" "vecsimple")]) 15029 15030(define_insn "altivec_vsubuws" 15031 [(set (match_operand:V4SI 0 "register_operand" "=v") 15032 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 15033 (match_operand:V4SI 2 "register_operand" "v")] 129))] 15034 "TARGET_ALTIVEC" 15035 "vsubuws %0,%1,%2" 15036 [(set_attr "type" "vecsimple")]) 15037 15038(define_insn "altivec_vsubsws" 15039 [(set (match_operand:V4SI 0 "register_operand" "=v") 15040 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 15041 (match_operand:V4SI 2 "register_operand" "v")] 130))] 15042 "TARGET_ALTIVEC" 15043 "vsubsws %0,%1,%2" 15044 [(set_attr "type" "vecsimple")]) 15045 15046(define_insn "altivec_vsum4ubs" 15047 [(set (match_operand:V4SI 0 "register_operand" "=v") 15048 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") 15049 (match_operand:V4SI 2 "register_operand" "v")] 131))] 15050 "TARGET_ALTIVEC" 15051 "vsum4ubs %0,%1,%2" 15052 [(set_attr "type" "veccomplex")]) 15053 15054(define_insn "altivec_vsum4sbs" 15055 [(set (match_operand:V4SI 0 "register_operand" "=v") 15056 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") 15057 (match_operand:V4SI 2 "register_operand" "v")] 132))] 15058 "TARGET_ALTIVEC" 15059 "vsum4sbs %0,%1,%2" 15060 [(set_attr "type" "veccomplex")]) 15061 15062(define_insn "altivec_vsum4shs" 15063 [(set (match_operand:V4SI 0 "register_operand" "=v") 15064 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") 15065 (match_operand:V4SI 2 "register_operand" "v")] 133))] 15066 "TARGET_ALTIVEC" 15067 "vsum4shs %0,%1,%2" 15068 [(set_attr "type" "veccomplex")]) 15069 15070(define_insn "altivec_vsum2sws" 15071 [(set (match_operand:V4SI 0 "register_operand" "=v") 15072 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 15073 (match_operand:V4SI 2 "register_operand" "v")] 134))] 15074 "TARGET_ALTIVEC" 15075 "vsum2sws %0,%1,%2" 15076 [(set_attr "type" "veccomplex")]) 15077 15078(define_insn "altivec_vsumsws" 15079 [(set (match_operand:V4SI 0 "register_operand" "=v") 15080 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 15081 (match_operand:V4SI 2 "register_operand" "v")] 135))] 15082 "TARGET_ALTIVEC" 15083 "vsumsws %0,%1,%2" 15084 [(set_attr "type" "veccomplex")]) 15085 15086(define_insn "xorv4si3" 15087 [(set (match_operand:V4SI 0 "register_operand" "=v") 15088 (xor:V4SI (match_operand:V4SI 1 "register_operand" "v") 15089 (match_operand:V4SI 2 "register_operand" "v")))] 15090 "TARGET_ALTIVEC" 15091 "vxor %0,%1,%2" 15092 [(set_attr "type" "vecsimple")]) 15093 15094(define_insn "altivec_vspltb" 15095 [(set (match_operand:V16QI 0 "register_operand" "=v") 15096 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 15097 (match_operand:QI 2 "immediate_operand" "i")] 136))] 15098 "TARGET_ALTIVEC" 15099 "vspltb %0,%1,%2" 15100 [(set_attr "type" "vecperm")]) 15101 15102(define_insn "altivec_vsplth" 15103 [(set (match_operand:V8HI 0 "register_operand" "=v") 15104 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 15105 (match_operand:QI 2 "immediate_operand" "i")] 137))] 15106 "TARGET_ALTIVEC" 15107 "vsplth %0,%1,%2" 15108 [(set_attr "type" "vecperm")]) 15109 15110(define_insn "altivec_vspltw" 15111 [(set (match_operand:V4SI 0 "register_operand" "=v") 15112 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 15113 (match_operand:QI 2 "immediate_operand" "i")] 138))] 15114 "TARGET_ALTIVEC" 15115 "vspltw %0,%1,%2" 15116 [(set_attr "type" "vecperm")]) 15117 15118(define_insn "altivec_vspltisb" 15119 [(set (match_operand:V16QI 0 "register_operand" "=v") 15120 (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))] 15121 "TARGET_ALTIVEC" 15122 "vspltisb %0, %1" 15123 [(set_attr "type" "vecsimple")]) 15124 15125 15126(define_insn "altivec_vspltish" 15127 [(set (match_operand:V8HI 0 "register_operand" "=v") 15128 (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))] 15129 "TARGET_ALTIVEC" 15130 "vspltish %0, %1" 15131 [(set_attr "type" "vecsimple")]) 15132 15133(define_insn "altivec_vspltisw" 15134 [(set (match_operand:V4SI 0 "register_operand" "=v") 15135 (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))] 15136 "TARGET_ALTIVEC" 15137 "vspltisw %0, %1" 15138 [(set_attr "type" "vecsimple")]) 15139 15140(define_insn "" 15141 [(set (match_operand:V4SF 0 "register_operand" "=v") 15142 (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))] 15143 "TARGET_ALTIVEC" 15144 "vspltisw %0, %1" 15145 [(set_attr "type" "vecsimple")]) 15146 15147(define_insn "ftruncv4sf2" 15148 [(set (match_operand:V4SF 0 "register_operand" "=v") 15149 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))] 15150 "TARGET_ALTIVEC" 15151 "vrfiz %0, %1" 15152 [(set_attr "type" "vecfloat")]) 15153 15154(define_insn "altivec_vperm_4si" 15155 [(set (match_operand:V4SI 0 "register_operand" "=v") 15156 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 15157 (match_operand:V4SI 2 "register_operand" "v") 15158 (match_operand:V16QI 3 "register_operand" "v")] 144))] 15159 "TARGET_ALTIVEC" 15160 "vperm %0,%1,%2,%3" 15161 [(set_attr "type" "vecperm")]) 15162 15163(define_insn "altivec_vperm_4sf" 15164 [(set (match_operand:V4SF 0 "register_operand" "=v") 15165 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") 15166 (match_operand:V4SF 2 "register_operand" "v") 15167 (match_operand:V16QI 3 "register_operand" "v")] 145))] 15168 "TARGET_ALTIVEC" 15169 "vperm %0,%1,%2,%3" 15170 [(set_attr "type" "vecperm")]) 15171 15172(define_insn "altivec_vperm_8hi" 15173 [(set (match_operand:V8HI 0 "register_operand" "=v") 15174 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 15175 (match_operand:V8HI 2 "register_operand" "v") 15176 (match_operand:V16QI 3 "register_operand" "v")] 146))] 15177 "TARGET_ALTIVEC" 15178 "vperm %0,%1,%2,%3" 15179 [(set_attr "type" "vecperm")]) 15180 15181(define_insn "altivec_vperm_16qi" 15182 [(set (match_operand:V16QI 0 "register_operand" "=v") 15183 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 15184 (match_operand:V16QI 2 "register_operand" "v") 15185 (match_operand:V16QI 3 "register_operand" "v")] 147))] 15186 "TARGET_ALTIVEC" 15187 "vperm %0,%1,%2,%3" 15188 [(set_attr "type" "vecperm")]) 15189 15190(define_insn "altivec_vrfip" 15191 [(set (match_operand:V4SF 0 "register_operand" "=v") 15192 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))] 15193 "TARGET_ALTIVEC" 15194 "vrfip %0, %1" 15195 [(set_attr "type" "vecfloat")]) 15196 15197(define_insn "altivec_vrfin" 15198 [(set (match_operand:V4SF 0 "register_operand" "=v") 15199 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))] 15200 "TARGET_ALTIVEC" 15201 "vrfin %0, %1" 15202 [(set_attr "type" "vecfloat")]) 15203 15204(define_insn "altivec_vrfim" 15205 [(set (match_operand:V4SF 0 "register_operand" "=v") 15206 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))] 15207 "TARGET_ALTIVEC" 15208 "vrfim %0, %1" 15209 [(set_attr "type" "vecfloat")]) 15210 15211(define_insn "altivec_vcfux" 15212 [(set (match_operand:V4SF 0 "register_operand" "=v") 15213 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") 15214 (match_operand:QI 2 "immediate_operand" "i")] 151))] 15215 "TARGET_ALTIVEC" 15216 "vcfux %0, %1, %2" 15217 [(set_attr "type" "vecfloat")]) 15218 15219(define_insn "altivec_vcfsx" 15220 [(set (match_operand:V4SF 0 "register_operand" "=v") 15221 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") 15222 (match_operand:QI 2 "immediate_operand" "i")] 152))] 15223 "TARGET_ALTIVEC" 15224 "vcfsx %0, %1, %2" 15225 [(set_attr "type" "vecfloat")]) 15226 15227(define_insn "altivec_vctuxs" 15228 [(set (match_operand:V4SI 0 "register_operand" "=v") 15229 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 15230 (match_operand:QI 2 "immediate_operand" "i")] 153))] 15231 "TARGET_ALTIVEC" 15232 "vctuxs %0, %1, %2" 15233 [(set_attr "type" "vecfloat")]) 15234 15235(define_insn "altivec_vctsxs" 15236 [(set (match_operand:V4SI 0 "register_operand" "=v") 15237 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") 15238 (match_operand:QI 2 "immediate_operand" "i")] 154))] 15239 "TARGET_ALTIVEC" 15240 "vctsxs %0, %1, %2" 15241 [(set_attr "type" "vecfloat")]) 15242 15243(define_insn "altivec_vlogefp" 15244 [(set (match_operand:V4SF 0 "register_operand" "=v") 15245 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))] 15246 "TARGET_ALTIVEC" 15247 "vlogefp %0, %1" 15248 [(set_attr "type" "vecfloat")]) 15249 15250(define_insn "altivec_vexptefp" 15251 [(set (match_operand:V4SF 0 "register_operand" "=v") 15252 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))] 15253 "TARGET_ALTIVEC" 15254 "vexptefp %0, %1" 15255 [(set_attr "type" "vecfloat")]) 15256 15257(define_insn "altivec_vrsqrtefp" 15258 [(set (match_operand:V4SF 0 "register_operand" "=v") 15259 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))] 15260 "TARGET_ALTIVEC" 15261 "vrsqrtefp %0, %1" 15262 [(set_attr "type" "vecfloat")]) 15263 15264(define_insn "altivec_vrefp" 15265 [(set (match_operand:V4SF 0 "register_operand" "=v") 15266 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))] 15267 "TARGET_ALTIVEC" 15268 "vrefp %0, %1" 15269 [(set_attr "type" "vecfloat")]) 15270 15271(define_insn "altivec_vsel_4si" 15272 [(set (match_operand:V4SI 0 "register_operand" "=v") 15273 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 15274 (match_operand:V4SI 2 "register_operand" "v") 15275 (match_operand:V4SI 3 "register_operand" "v")] 159))] 15276 "TARGET_ALTIVEC" 15277 "vsel %0,%1,%2,%3" 15278 [(set_attr "type" "vecperm")]) 15279 15280(define_insn "altivec_vsel_4sf" 15281 [(set (match_operand:V4SF 0 "register_operand" "=v") 15282 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") 15283 (match_operand:V4SF 2 "register_operand" "v") 15284 (match_operand:V4SI 3 "register_operand" "v")] 160))] 15285 "TARGET_ALTIVEC" 15286 "vsel %0,%1,%2,%3" 15287 [(set_attr "type" "vecperm")]) 15288 15289(define_insn "altivec_vsel_8hi" 15290 [(set (match_operand:V8HI 0 "register_operand" "=v") 15291 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 15292 (match_operand:V8HI 2 "register_operand" "v") 15293 (match_operand:V8HI 3 "register_operand" "v")] 161))] 15294 "TARGET_ALTIVEC" 15295 "vsel %0,%1,%2,%3" 15296 [(set_attr "type" "vecperm")]) 15297 15298(define_insn "altivec_vsel_16qi" 15299 [(set (match_operand:V16QI 0 "register_operand" "=v") 15300 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 15301 (match_operand:V16QI 2 "register_operand" "v") 15302 (match_operand:V16QI 3 "register_operand" "v")] 162))] 15303 "TARGET_ALTIVEC" 15304 "vsel %0,%1,%2,%3" 15305 [(set_attr "type" "vecperm")]) 15306 15307(define_insn "altivec_vsldoi_4si" 15308 [(set (match_operand:V4SI 0 "register_operand" "=v") 15309 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") 15310 (match_operand:V4SI 2 "register_operand" "v") 15311 (match_operand:QI 3 "immediate_operand" "i")] 163))] 15312 "TARGET_ALTIVEC" 15313 "vsldoi %0, %1, %2, %3" 15314 [(set_attr "type" "vecperm")]) 15315 15316(define_insn "altivec_vsldoi_4sf" 15317 [(set (match_operand:V4SF 0 "register_operand" "=v") 15318 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") 15319 (match_operand:V4SF 2 "register_operand" "v") 15320 (match_operand:QI 3 "immediate_operand" "i")] 164))] 15321 "TARGET_ALTIVEC" 15322 "vsldoi %0, %1, %2, %3" 15323 [(set_attr "type" "vecperm")]) 15324 15325(define_insn "altivec_vsldoi_8hi" 15326 [(set (match_operand:V8HI 0 "register_operand" "=v") 15327 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") 15328 (match_operand:V8HI 2 "register_operand" "v") 15329 (match_operand:QI 3 "immediate_operand" "i")] 165))] 15330 "TARGET_ALTIVEC" 15331 "vsldoi %0, %1, %2, %3" 15332 [(set_attr "type" "vecperm")]) 15333 15334(define_insn "altivec_vsldoi_16qi" 15335 [(set (match_operand:V16QI 0 "register_operand" "=v") 15336 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 15337 (match_operand:V16QI 2 "register_operand" "v") 15338 (match_operand:QI 3 "immediate_operand" "i")] 166))] 15339 "TARGET_ALTIVEC" 15340 "vsldoi %0, %1, %2, %3" 15341 [(set_attr "type" "vecperm")]) 15342 15343(define_insn "altivec_vupkhsb" 15344 [(set (match_operand:V8HI 0 "register_operand" "=v") 15345 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))] 15346 "TARGET_ALTIVEC" 15347 "vupkhsb %0, %1" 15348 [(set_attr "type" "vecperm")]) 15349 15350(define_insn "altivec_vupkhpx" 15351 [(set (match_operand:V4SI 0 "register_operand" "=v") 15352 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))] 15353 "TARGET_ALTIVEC" 15354 "vupkhpx %0, %1" 15355 [(set_attr "type" "vecperm")]) 15356 15357(define_insn "altivec_vupkhsh" 15358 [(set (match_operand:V4SI 0 "register_operand" "=v") 15359 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))] 15360 "TARGET_ALTIVEC" 15361 "vupkhsh %0, %1" 15362 [(set_attr "type" "vecperm")]) 15363 15364(define_insn "altivec_vupklsb" 15365 [(set (match_operand:V8HI 0 "register_operand" "=v") 15366 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))] 15367 "TARGET_ALTIVEC" 15368 "vupklsb %0, %1" 15369 [(set_attr "type" "vecperm")]) 15370 15371(define_insn "altivec_vupklpx" 15372 [(set (match_operand:V4SI 0 "register_operand" "=v") 15373 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))] 15374 "TARGET_ALTIVEC" 15375 "vupklpx %0, %1" 15376 [(set_attr "type" "vecperm")]) 15377 15378(define_insn "altivec_vupklsh" 15379 [(set (match_operand:V4SI 0 "register_operand" "=v") 15380 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))] 15381 "TARGET_ALTIVEC" 15382 "vupklsh %0, %1" 15383 [(set_attr "type" "vecperm")]) 15384 15385;; AltiVec predicates. 15386 15387(define_expand "cr6_test_for_zero" 15388 [(set (match_operand:SI 0 "register_operand" "=r") 15389 (eq:SI (reg:CC 74) 15390 (const_int 0)))] 15391 "TARGET_ALTIVEC" 15392 "") 15393 15394(define_expand "cr6_test_for_zero_reverse" 15395 [(set (match_operand:SI 0 "register_operand" "=r") 15396 (eq:SI (reg:CC 74) 15397 (const_int 0))) 15398 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] 15399 "TARGET_ALTIVEC" 15400 "") 15401 15402(define_expand "cr6_test_for_lt" 15403 [(set (match_operand:SI 0 "register_operand" "=r") 15404 (lt:SI (reg:CC 74) 15405 (const_int 0)))] 15406 "TARGET_ALTIVEC" 15407 "") 15408 15409(define_expand "cr6_test_for_lt_reverse" 15410 [(set (match_operand:SI 0 "register_operand" "=r") 15411 (lt:SI (reg:CC 74) 15412 (const_int 0))) 15413 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] 15414 "TARGET_ALTIVEC" 15415 "") 15416 15417;; We can get away with generating the opcode on the fly (%3 below) 15418;; because all the predicates have the same scheduling parameters. 15419 15420(define_insn "altivec_predicate_v4si" 15421 [(set (reg:CC 74) 15422 (unspec:CC [(match_operand:V4SI 1 "register_operand" "v") 15423 (match_operand:V4SI 2 "register_operand" "v") 15424 (match_operand 3 "any_operand" "")] 173)) 15425 (clobber (match_scratch:V4SI 0 "=v"))] 15426 "TARGET_ALTIVEC" 15427 "%3 %0,%1,%2" 15428[(set_attr "type" "veccmp")]) 15429 15430(define_insn "altivec_predicate_v4sf" 15431 [(set (reg:CC 74) 15432 (unspec:CC [(match_operand:V4SF 1 "register_operand" "v") 15433 (match_operand:V4SF 2 "register_operand" "v") 15434 (match_operand 3 "any_operand" "")] 174)) 15435 (clobber (match_scratch:V4SF 0 "=v"))] 15436 "TARGET_ALTIVEC" 15437 "%3 %0,%1,%2" 15438[(set_attr "type" "veccmp")]) 15439 15440(define_insn "altivec_predicate_v8hi" 15441 [(set (reg:CC 74) 15442 (unspec:CC [(match_operand:V8HI 1 "register_operand" "v") 15443 (match_operand:V8HI 2 "register_operand" "v") 15444 (match_operand 3 "any_operand" "")] 175)) 15445 (clobber (match_scratch:V8HI 0 "=v"))] 15446 "TARGET_ALTIVEC" 15447 "%3 %0,%1,%2" 15448[(set_attr "type" "veccmp")]) 15449 15450(define_insn "altivec_predicate_v16qi" 15451 [(set (reg:CC 74) 15452 (unspec:CC [(match_operand:V16QI 1 "register_operand" "v") 15453 (match_operand:V16QI 2 "register_operand" "v") 15454 (match_operand 3 "any_operand" "")] 175)) 15455 (clobber (match_scratch:V16QI 0 "=v"))] 15456 "TARGET_ALTIVEC" 15457 "%3 %0,%1,%2" 15458[(set_attr "type" "veccmp")]) 15459 15460(define_insn "altivec_mtvscr" 15461 [(unspec [(match_operand:V4SI 0 "register_operand" "v")] 186)] 15462 "TARGET_ALTIVEC" 15463 "mtvscr %0" 15464 [(set_attr "type" "vecsimple")]) 15465 15466(define_insn "altivec_mfvscr" 15467 [(set (match_operand:V8HI 0 "register_operand" "=v") 15468 (unspec:V8HI [(const_int 0)] 187))] 15469 "TARGET_ALTIVEC" 15470 "mfvscr %0" 15471 [(set_attr "type" "vecsimple")]) 15472 15473(define_insn "altivec_dssall" 15474 [(unspec [(const_int 0)] 188)] 15475 "TARGET_ALTIVEC" 15476 "dssall" 15477 [(set_attr "type" "vecsimple")]) 15478 15479(define_insn "altivec_dss" 15480 [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)] 15481 "TARGET_ALTIVEC" 15482 "dss %0" 15483 [(set_attr "type" "vecsimple")]) 15484 15485(define_insn "altivec_dst" 15486 [(unspec [(match_operand:SI 0 "register_operand" "b") 15487 (match_operand:SI 1 "register_operand" "r") 15488 (match_operand:QI 2 "immediate_operand" "i")] 190)] 15489 "TARGET_ALTIVEC" 15490 "dst %0,%1,%2" 15491 [(set_attr "type" "vecsimple")]) 15492 15493(define_insn "altivec_dstt" 15494 [(unspec [(match_operand:SI 0 "register_operand" "b") 15495 (match_operand:SI 1 "register_operand" "r") 15496 (match_operand:QI 2 "immediate_operand" "i")] 191)] 15497 "TARGET_ALTIVEC" 15498 "dstt %0,%1,%2" 15499 [(set_attr "type" "vecsimple")]) 15500 15501(define_insn "altivec_dstst" 15502 [(unspec [(match_operand:SI 0 "register_operand" "b") 15503 (match_operand:SI 1 "register_operand" "r") 15504 (match_operand:QI 2 "immediate_operand" "i")] 192)] 15505 "TARGET_ALTIVEC" 15506 "dstst %0,%1,%2" 15507 [(set_attr "type" "vecsimple")]) 15508 15509(define_insn "altivec_dststt" 15510 [(unspec [(match_operand:SI 0 "register_operand" "b") 15511 (match_operand:SI 1 "register_operand" "r") 15512 (match_operand:QI 2 "immediate_operand" "i")] 193)] 15513 "TARGET_ALTIVEC" 15514 "dststt %0,%1,%2" 15515 [(set_attr "type" "vecsimple")]) 15516 15517(define_insn "altivec_lvsl" 15518 [(set (match_operand:V16QI 0 "register_operand" "=v") 15519 (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") 15520 (match_operand:SI 2 "register_operand" "r")] 194))] 15521 "TARGET_ALTIVEC" 15522 "lvsl %0,%1,%2" 15523 [(set_attr "type" "vecload")]) 15524 15525(define_insn "altivec_lvsr" 15526 [(set (match_operand:V16QI 0 "register_operand" "=v") 15527 (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") 15528 (match_operand:SI 2 "register_operand" "r")] 195))] 15529 "TARGET_ALTIVEC" 15530 "lvsr %0,%1,%2" 15531 [(set_attr "type" "vecload")]) 15532 15533;; Parallel some of the LVE* and STV*'s with unspecs because some have 15534;; identical rtl but different instructions-- and gcc gets confused. 15535 15536(define_insn "altivec_lvebx" 15537 [(parallel 15538 [(set (match_operand:V16QI 0 "register_operand" "=v") 15539 (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b") 15540 (match_operand:SI 2 "register_operand" "r")))) 15541 (unspec [(const_int 0)] 196)])] 15542 "TARGET_ALTIVEC" 15543 "lvebx %0,%1,%2" 15544 [(set_attr "type" "vecload")]) 15545 15546(define_insn "altivec_lvehx" 15547 [(parallel 15548 [(set (match_operand:V8HI 0 "register_operand" "=v") 15549 (mem:V8HI 15550 (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") 15551 (match_operand:SI 2 "register_operand" "r")) 15552 (const_int -2)))) 15553 (unspec [(const_int 0)] 197)])] 15554 "TARGET_ALTIVEC" 15555 "lvehx %0,%1,%2" 15556 [(set_attr "type" "vecload")]) 15557 15558(define_insn "altivec_lvewx" 15559 [(parallel 15560 [(set (match_operand:V4SI 0 "register_operand" "=v") 15561 (mem:V4SI 15562 (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") 15563 (match_operand:SI 2 "register_operand" "r")) 15564 (const_int -4)))) 15565 (unspec [(const_int 0)] 198)])] 15566 "TARGET_ALTIVEC" 15567 "lvewx %0,%1,%2" 15568 [(set_attr "type" "vecload")]) 15569 15570(define_insn "altivec_lvxl" 15571 [(parallel 15572 [(set (match_operand:V4SI 0 "register_operand" "=v") 15573 (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") 15574 (match_operand:SI 2 "register_operand" "r")))) 15575 (unspec [(const_int 0)] 213)])] 15576 "TARGET_ALTIVEC" 15577 "lvxl %0,%1,%2" 15578 [(set_attr "type" "vecload")]) 15579 15580(define_insn "altivec_lvx" 15581 [(set (match_operand:V4SI 0 "register_operand" "=v") 15582 (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") 15583 (match_operand:SI 2 "register_operand" "r"))))] 15584 "TARGET_ALTIVEC" 15585 "lvx %0,%1,%2" 15586 [(set_attr "type" "vecload")]) 15587 15588(define_insn "altivec_stvx" 15589 [(parallel 15590 [(set (mem:V4SI 15591 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") 15592 (match_operand:SI 1 "register_operand" "r")) 15593 (const_int -16))) 15594 (match_operand:V4SI 2 "register_operand" "v")) 15595 (unspec [(const_int 0)] 201)])] 15596 "TARGET_ALTIVEC" 15597 "stvx %2,%0,%1" 15598 [(set_attr "type" "vecstore")]) 15599 15600(define_insn "altivec_stvxl" 15601 [(parallel 15602 [(set (mem:V4SI 15603 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") 15604 (match_operand:SI 1 "register_operand" "r")) 15605 (const_int -16))) 15606 (match_operand:V4SI 2 "register_operand" "v")) 15607 (unspec [(const_int 0)] 202)])] 15608 "TARGET_ALTIVEC" 15609 "stvxl %2,%0,%1" 15610 [(set_attr "type" "vecstore")]) 15611 15612(define_insn "altivec_stvebx" 15613 [(parallel 15614 [(set (mem:V16QI 15615 (plus:SI (match_operand:SI 0 "register_operand" "b") 15616 (match_operand:SI 1 "register_operand" "r"))) 15617 (match_operand:V16QI 2 "register_operand" "v")) 15618 (unspec [(const_int 0)] 203)])] 15619 "TARGET_ALTIVEC" 15620 "stvebx %2,%0,%1" 15621 [(set_attr "type" "vecstore")]) 15622 15623(define_insn "altivec_stvehx" 15624 [(parallel 15625 [(set (mem:V8HI 15626 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") 15627 (match_operand:SI 1 "register_operand" "r")) 15628 (const_int -2))) 15629 (match_operand:V8HI 2 "register_operand" "v")) 15630 (unspec [(const_int 0)] 204)])] 15631 "TARGET_ALTIVEC" 15632 "stvehx %2,%0,%1" 15633 [(set_attr "type" "vecstore")]) 15634 15635(define_insn "altivec_stvewx" 15636 [(parallel 15637 [(set (mem:V4SI 15638 (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") 15639 (match_operand:SI 1 "register_operand" "r")) 15640 (const_int -4))) 15641 (match_operand:V4SI 2 "register_operand" "v")) 15642 (unspec [(const_int 0)] 205)])] 15643 "TARGET_ALTIVEC" 15644 "stvewx %2,%0,%1" 15645 [(set_attr "type" "vecstore")]) 15646 15647(define_insn "absv16qi2" 15648 [(set (match_operand:V16QI 0 "register_operand" "=v") 15649 (abs:V16QI (match_operand:V16QI 1 "register_operand" "v"))) 15650 (clobber (match_scratch:V16QI 2 "=v")) 15651 (clobber (match_scratch:V16QI 3 "=v"))] 15652 "TARGET_ALTIVEC" 15653 "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3" 15654 [(set_attr "type" "altivec") 15655 (set_attr "length" "12")]) 15656 15657(define_insn "absv8hi2" 15658 [(set (match_operand:V8HI 0 "register_operand" "=v") 15659 (abs:V8HI (match_operand:V8HI 1 "register_operand" "v"))) 15660 (clobber (match_scratch:V8HI 2 "=v")) 15661 (clobber (match_scratch:V8HI 3 "=v"))] 15662 "TARGET_ALTIVEC" 15663 "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3" 15664 [(set_attr "type" "altivec") 15665 (set_attr "length" "12")]) 15666 15667(define_insn "absv4si2" 15668 [(set (match_operand:V4SI 0 "register_operand" "=v") 15669 (abs:V4SI (match_operand:V4SI 1 "register_operand" "v"))) 15670 (clobber (match_scratch:V4SI 2 "=v")) 15671 (clobber (match_scratch:V4SI 3 "=v"))] 15672 "TARGET_ALTIVEC" 15673 "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3" 15674 [(set_attr "type" "altivec") 15675 (set_attr "length" "12")]) 15676 15677(define_insn "absv4sf2" 15678 [(set (match_operand:V4SF 0 "register_operand" "=v") 15679 (abs:V4SF (match_operand:V4SF 1 "register_operand" "v"))) 15680 (clobber (match_scratch:V4SF 2 "=v")) 15681 (clobber (match_scratch:V4SF 3 "=v"))] 15682 "TARGET_ALTIVEC" 15683 "vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3" 15684 [(set_attr "type" "altivec") 15685 (set_attr "length" "12")]) 15686 15687(define_insn "altivec_abss_v16qi" 15688 [(set (match_operand:V16QI 0 "register_operand" "=v") 15689 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210)) 15690 (clobber (match_scratch:V16QI 2 "=v")) 15691 (clobber (match_scratch:V16QI 3 "=v"))] 15692 "TARGET_ALTIVEC" 15693 "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3" 15694 [(set_attr "type" "altivec") 15695 (set_attr "length" "12")]) 15696 15697(define_insn "altivec_abss_v8hi" 15698 [(set (match_operand:V8HI 0 "register_operand" "=v") 15699 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211)) 15700 (clobber (match_scratch:V8HI 2 "=v")) 15701 (clobber (match_scratch:V8HI 3 "=v"))] 15702 "TARGET_ALTIVEC" 15703 "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3" 15704 [(set_attr "type" "altivec") 15705 (set_attr "length" "12")]) 15706 15707(define_insn "altivec_abss_v4si" 15708 [(set (match_operand:V4SI 0 "register_operand" "=v") 15709 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212)) 15710 (clobber (match_scratch:V4SI 2 "=v")) 15711 (clobber (match_scratch:V4SI 3 "=v"))] 15712 "TARGET_ALTIVEC" 15713 "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3" 15714 [(set_attr "type" "altivec") 15715 (set_attr "length" "12")]) 15716