1;; Predicate definitions for POWER and PowerPC. 2;; Copyright (C) 2005, 2006 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 2, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to 18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19;; Boston, MA 02110-1301, USA. 20 21;; Return 1 for anything except PARALLEL. 22(define_predicate "any_operand" 23 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")) 24 25;; Return 1 for any PARALLEL. 26(define_predicate "any_parallel_operand" 27 (match_code "parallel")) 28 29;; Return 1 if op is COUNT register. 30(define_predicate "count_register_operand" 31 (and (match_code "reg") 32 (match_test "REGNO (op) == COUNT_REGISTER_REGNUM 33 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) 34 35;; Return 1 if op is an Altivec register. 36(define_predicate "altivec_register_operand" 37 (and (match_operand 0 "register_operand") 38 (match_test "GET_CODE (op) != REG 39 || ALTIVEC_REGNO_P (REGNO (op)) 40 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) 41 42;; Return 1 if op is XER register. 43(define_predicate "xer_operand" 44 (and (match_code "reg") 45 (match_test "XER_REGNO_P (REGNO (op))"))) 46 47;; Return 1 if op is a signed 5-bit constant integer. 48(define_predicate "s5bit_cint_operand" 49 (and (match_code "const_int") 50 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) 51 52;; Return 1 if op is a unsigned 5-bit constant integer. 53(define_predicate "u5bit_cint_operand" 54 (and (match_code "const_int") 55 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) 56 57;; Return 1 if op is a signed 8-bit constant integer. 58;; Integer multiplication complete more quickly 59(define_predicate "s8bit_cint_operand" 60 (and (match_code "const_int") 61 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) 62 63;; Return 1 if op is a constant integer that can fit in a D field. 64(define_predicate "short_cint_operand" 65 (and (match_code "const_int") 66 (match_test "satisfies_constraint_I (op)"))) 67 68;; Return 1 if op is a constant integer that can fit in an unsigned D field. 69(define_predicate "u_short_cint_operand" 70 (and (match_code "const_int") 71 (match_test "satisfies_constraint_K (op)"))) 72 73;; Return 1 if op is a constant integer that cannot fit in a signed D field. 74(define_predicate "non_short_cint_operand" 75 (and (match_code "const_int") 76 (match_test "(unsigned HOST_WIDE_INT) 77 (INTVAL (op) + 0x8000) >= 0x10000"))) 78 79;; Return 1 if op is a positive constant integer that is an exact power of 2. 80(define_predicate "exact_log2_cint_operand" 81 (and (match_code "const_int") 82 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) 83 84;; Return 1 if op is a register that is not special. 85(define_predicate "gpc_reg_operand" 86 (and (match_operand 0 "register_operand") 87 (match_test "(GET_CODE (op) != REG 88 || (REGNO (op) >= ARG_POINTER_REGNUM 89 && !XER_REGNO_P (REGNO (op))) 90 || REGNO (op) < MQ_REGNO) 91 && !((TARGET_E500_DOUBLE || TARGET_SPE) 92 && invalid_e500_subreg (op, mode))"))) 93 94;; Return 1 if op is a register that is a condition register field. 95(define_predicate "cc_reg_operand" 96 (and (match_operand 0 "register_operand") 97 (match_test "GET_CODE (op) != REG 98 || REGNO (op) > LAST_VIRTUAL_REGISTER 99 || CR_REGNO_P (REGNO (op))"))) 100 101;; Return 1 if op is a register that is a condition register field not cr0. 102(define_predicate "cc_reg_not_cr0_operand" 103 (and (match_operand 0 "register_operand") 104 (match_test "GET_CODE (op) != REG 105 || REGNO (op) > LAST_VIRTUAL_REGISTER 106 || CR_REGNO_NOT_CR0_P (REGNO (op))"))) 107 108;; Return 1 if op is a constant integer valid for D field 109;; or non-special register register. 110(define_predicate "reg_or_short_operand" 111 (if_then_else (match_code "const_int") 112 (match_operand 0 "short_cint_operand") 113 (match_operand 0 "gpc_reg_operand"))) 114 115;; Return 1 if op is a constant integer valid whose negation is valid for 116;; D field or non-special register register. 117;; Do not allow a constant zero because all patterns that call this 118;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than 119;; or equal to const, which does not work for zero. 120(define_predicate "reg_or_neg_short_operand" 121 (if_then_else (match_code "const_int") 122 (match_test "satisfies_constraint_P (op) 123 && INTVAL (op) != 0") 124 (match_operand 0 "gpc_reg_operand"))) 125 126;; Return 1 if op is a constant integer valid for DS field 127;; or non-special register. 128(define_predicate "reg_or_aligned_short_operand" 129 (if_then_else (match_code "const_int") 130 (and (match_operand 0 "short_cint_operand") 131 (match_test "!(INTVAL (op) & 3)")) 132 (match_operand 0 "gpc_reg_operand"))) 133 134;; Return 1 if op is a constant integer whose high-order 16 bits are zero 135;; or non-special register. 136(define_predicate "reg_or_u_short_operand" 137 (if_then_else (match_code "const_int") 138 (match_operand 0 "u_short_cint_operand") 139 (match_operand 0 "gpc_reg_operand"))) 140 141;; Return 1 if op is any constant integer 142;; or non-special register. 143(define_predicate "reg_or_cint_operand" 144 (ior (match_code "const_int") 145 (match_operand 0 "gpc_reg_operand"))) 146 147;; Return 1 if op is a constant integer valid for addition 148;; or non-special register. 149(define_predicate "reg_or_add_cint_operand" 150 (if_then_else (match_code "const_int") 151 (match_test "(HOST_BITS_PER_WIDE_INT == 32 152 && (mode == SImode || INTVAL (op) < 0x7fff8000)) 153 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) 154 < (unsigned HOST_WIDE_INT) 0x100000000ll)") 155 (match_operand 0 "gpc_reg_operand"))) 156 157;; Return 1 if op is a constant integer valid for subtraction 158;; or non-special register. 159(define_predicate "reg_or_sub_cint_operand" 160 (if_then_else (match_code "const_int") 161 (match_test "(HOST_BITS_PER_WIDE_INT == 32 162 && (mode == SImode || - INTVAL (op) < 0x7fff8000)) 163 || ((unsigned HOST_WIDE_INT) (- INTVAL (op) 164 + (mode == SImode 165 ? 0x80000000 : 0x80008000)) 166 < (unsigned HOST_WIDE_INT) 0x100000000ll)") 167 (match_operand 0 "gpc_reg_operand"))) 168 169;; Return 1 if op is any 32-bit unsigned constant integer 170;; or non-special register. 171(define_predicate "reg_or_logical_cint_operand" 172 (if_then_else (match_code "const_int") 173 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 174 && INTVAL (op) >= 0) 175 || ((INTVAL (op) & GET_MODE_MASK (mode) 176 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") 177 (if_then_else (match_code "const_double") 178 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT 179 && mode == DImode 180 && CONST_DOUBLE_HIGH (op) == 0") 181 (match_operand 0 "gpc_reg_operand")))) 182 183;; Return 1 if operand is a CONST_DOUBLE that can be set in a register 184;; with no more than one instruction per word. 185(define_predicate "easy_fp_constant" 186 (match_code "const_double") 187{ 188 long k[4]; 189 REAL_VALUE_TYPE rv; 190 191 if (GET_MODE (op) != mode 192 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode)) 193 return 0; 194 195 /* Consider all constants with -msoft-float to be easy. */ 196 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) 197 && mode != DImode) 198 return 1; 199 200 if (DECIMAL_FLOAT_MODE_P (mode)) 201 return 0; 202 203 /* If we are using V.4 style PIC, consider all constants to be hard. */ 204 if (flag_pic && DEFAULT_ABI == ABI_V4) 205 return 0; 206 207#ifdef TARGET_RELOCATABLE 208 /* Similarly if we are using -mrelocatable, consider all constants 209 to be hard. */ 210 if (TARGET_RELOCATABLE) 211 return 0; 212#endif 213 214 switch (mode) 215 { 216 case TFmode: 217 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); 218 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); 219 220 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 221 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 222 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 223 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); 224 225 case DFmode: 226 /* Force constants to memory before reload to utilize 227 compress_float_constant. 228 Avoid this when flag_unsafe_math_optimizations is enabled 229 because RDIV division to reciprocal optimization is not able 230 to regenerate the division. */ 231 if (TARGET_E500_DOUBLE 232 || (!reload_in_progress && !reload_completed 233 && !flag_unsafe_math_optimizations)) 234 return 0; 235 236 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); 237 REAL_VALUE_TO_TARGET_DOUBLE (rv, k); 238 239 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 240 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); 241 242 case SFmode: 243 /* The constant 0.f is easy. */ 244 if (op == CONST0_RTX (SFmode)) 245 return 1; 246 247 /* Force constants to memory before reload to utilize 248 compress_float_constant. 249 Avoid this when flag_unsafe_math_optimizations is enabled 250 because RDIV division to reciprocal optimization is not able 251 to regenerate the division. */ 252 if (!reload_in_progress && !reload_completed 253 && !flag_unsafe_math_optimizations) 254 return 0; 255 256 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); 257 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]); 258 259 return num_insns_constant_wide (k[0]) == 1; 260 261 case DImode: 262 return ((TARGET_POWERPC64 263 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) 264 || (num_insns_constant (op, DImode) <= 2)); 265 266 case SImode: 267 return 1; 268 269 default: 270 gcc_unreachable (); 271 } 272}) 273 274;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a 275;; vector register without using memory. 276(define_predicate "easy_vector_constant" 277 (match_code "const_vector") 278{ 279 if (ALTIVEC_VECTOR_MODE (mode)) 280 { 281 if (zero_constant (op, mode)) 282 return true; 283 return easy_altivec_constant (op, mode); 284 } 285 286 if (SPE_VECTOR_MODE (mode)) 287 { 288 int cst, cst2; 289 if (zero_constant (op, mode)) 290 return true; 291 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) 292 return false; 293 294 /* Limit SPE vectors to 15 bits signed. These we can generate with: 295 li r0, CONSTANT1 296 evmergelo r0, r0, r0 297 li r0, CONSTANT2 298 299 I don't know how efficient it would be to allow bigger constants, 300 considering we'll have an extra 'ori' for every 'li'. I doubt 5 301 instructions is better than a 64-bit memory load, but I don't 302 have the e500 timing specs. */ 303 if (mode == V2SImode) 304 { 305 cst = INTVAL (CONST_VECTOR_ELT (op, 0)); 306 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); 307 return cst >= -0x7fff && cst <= 0x7fff 308 && cst2 >= -0x7fff && cst2 <= 0x7fff; 309 } 310 } 311 312 return false; 313}) 314 315;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. 316(define_predicate "easy_vector_constant_add_self" 317 (and (match_code "const_vector") 318 (and (match_test "TARGET_ALTIVEC") 319 (match_test "easy_altivec_constant (op, mode)"))) 320{ 321 rtx last = CONST_VECTOR_ELT (op, GET_MODE_NUNITS (mode) - 1); 322 HOST_WIDE_INT val = ((INTVAL (last) & 0xff) ^ 0x80) - 0x80; 323 return EASY_VECTOR_15_ADD_SELF (val); 324}) 325 326;; Return 1 if operand is constant zero (scalars and vectors). 327(define_predicate "zero_constant" 328 (and (match_code "const_int,const_double,const_vector") 329 (match_test "op == CONST0_RTX (mode)"))) 330 331;; Return 1 if operand is 0.0. 332;; or non-special register register field no cr0 333(define_predicate "zero_fp_constant" 334 (and (match_code "const_double") 335 (match_test "SCALAR_FLOAT_MODE_P (mode) 336 && op == CONST0_RTX (mode)"))) 337 338;; Return 1 if the operand is in volatile memory. Note that during the 339;; RTL generation phase, memory_operand does not return TRUE for volatile 340;; memory references. So this function allows us to recognize volatile 341;; references where it's safe. 342(define_predicate "volatile_mem_operand" 343 (and (and (match_code "mem") 344 (match_test "MEM_VOLATILE_P (op)")) 345 (if_then_else (match_test "reload_completed") 346 (match_operand 0 "memory_operand") 347 (if_then_else (match_test "reload_in_progress") 348 (match_test "strict_memory_address_p (mode, XEXP (op, 0))") 349 (match_test "memory_address_p (mode, XEXP (op, 0))"))))) 350 351;; Return 1 if the operand is an offsettable memory operand. 352(define_predicate "offsettable_mem_operand" 353 (and (match_code "mem") 354 (match_test "offsettable_address_p (reload_completed 355 || reload_in_progress, 356 mode, XEXP (op, 0))"))) 357 358;; Return 1 if the operand is a memory operand with an address divisible by 4 359(define_predicate "word_offset_memref_operand" 360 (and (match_operand 0 "memory_operand") 361 (match_test "GET_CODE (XEXP (op, 0)) != PLUS 362 || ! REG_P (XEXP (XEXP (op, 0), 0)) 363 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT 364 || INTVAL (XEXP (XEXP (op, 0), 1)) % 4 == 0"))) 365 366;; Return 1 if the operand is an indexed or indirect memory operand. 367(define_predicate "indexed_or_indirect_operand" 368 (match_code "mem") 369{ 370 op = XEXP (op, 0); 371 if (TARGET_ALTIVEC 372 && ALTIVEC_VECTOR_MODE (mode) 373 && GET_CODE (op) == AND 374 && GET_CODE (XEXP (op, 1)) == CONST_INT 375 && INTVAL (XEXP (op, 1)) == -16) 376 op = XEXP (op, 0); 377 378 return indexed_or_indirect_address (op, mode); 379}) 380 381;; Return 1 if the operand is an indexed or indirect address. 382(define_special_predicate "indexed_or_indirect_address" 383 (and (match_test "REG_P (op) 384 || (GET_CODE (op) == PLUS 385 /* Omit testing REG_P (XEXP (op, 0)). */ 386 && REG_P (XEXP (op, 1)))") 387 (match_operand 0 "address_operand"))) 388 389;; Used for the destination of the fix_truncdfsi2 expander. 390;; If stfiwx will be used, the result goes to memory; otherwise, 391;; we're going to emit a store and a load of a subreg, so the dest is a 392;; register. 393(define_predicate "fix_trunc_dest_operand" 394 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT") 395 (match_operand 0 "memory_operand") 396 (match_operand 0 "gpc_reg_operand"))) 397 398;; Return 1 if the operand is either a non-special register or can be used 399;; as the operand of a `mode' add insn. 400(define_predicate "add_operand" 401 (if_then_else (match_code "const_int") 402 (match_test "satisfies_constraint_I (op) 403 || satisfies_constraint_L (op)") 404 (match_operand 0 "gpc_reg_operand"))) 405 406;; Return 1 if OP is a constant but not a valid add_operand. 407(define_predicate "non_add_cint_operand" 408 (and (match_code "const_int") 409 (match_test "!satisfies_constraint_I (op) 410 && !satisfies_constraint_L (op)"))) 411 412;; Return 1 if the operand is a constant that can be used as the operand 413;; of an OR or XOR. 414(define_predicate "logical_const_operand" 415 (match_code "const_int,const_double") 416{ 417 HOST_WIDE_INT opl, oph; 418 419 if (GET_CODE (op) == CONST_INT) 420 { 421 opl = INTVAL (op) & GET_MODE_MASK (mode); 422 423 if (HOST_BITS_PER_WIDE_INT <= 32 424 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) 425 return 0; 426 } 427 else if (GET_CODE (op) == CONST_DOUBLE) 428 { 429 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT); 430 431 opl = CONST_DOUBLE_LOW (op); 432 oph = CONST_DOUBLE_HIGH (op); 433 if (oph != 0) 434 return 0; 435 } 436 else 437 return 0; 438 439 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 440 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); 441}) 442 443;; Return 1 if the operand is a non-special register or a constant that 444;; can be used as the operand of an OR or XOR. 445(define_predicate "logical_operand" 446 (ior (match_operand 0 "gpc_reg_operand") 447 (match_operand 0 "logical_const_operand"))) 448 449;; Return 1 if op is a constant that is not a logical operand, but could 450;; be split into one. 451(define_predicate "non_logical_cint_operand" 452 (and (match_code "const_int,const_double") 453 (and (not (match_operand 0 "logical_operand")) 454 (match_operand 0 "reg_or_logical_cint_operand")))) 455 456;; Return 1 if op is a constant that can be encoded in a 32-bit mask, 457;; suitable for use with rlwinm (no more than two 1->0 or 0->1 458;; transitions). Reject all ones and all zeros, since these should have 459;; been optimized away and confuse the making of MB and ME. 460(define_predicate "mask_operand" 461 (match_code "const_int") 462{ 463 HOST_WIDE_INT c, lsb; 464 465 c = INTVAL (op); 466 467 if (TARGET_POWERPC64) 468 { 469 /* Fail if the mask is not 32-bit. */ 470 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0) 471 return 0; 472 473 /* Fail if the mask wraps around because the upper 32-bits of the 474 mask will all be 1s, contrary to GCC's internal view. */ 475 if ((c & 0x80000001) == 0x80000001) 476 return 0; 477 } 478 479 /* We don't change the number of transitions by inverting, 480 so make sure we start with the LS bit zero. */ 481 if (c & 1) 482 c = ~c; 483 484 /* Reject all zeros or all ones. */ 485 if (c == 0) 486 return 0; 487 488 /* Find the first transition. */ 489 lsb = c & -c; 490 491 /* Invert to look for a second transition. */ 492 c = ~c; 493 494 /* Erase first transition. */ 495 c &= -lsb; 496 497 /* Find the second transition (if any). */ 498 lsb = c & -c; 499 500 /* Match if all the bits above are 1's (or c is zero). */ 501 return c == -lsb; 502}) 503 504;; Return 1 for the PowerPC64 rlwinm corner case. 505(define_predicate "mask_operand_wrap" 506 (match_code "const_int") 507{ 508 HOST_WIDE_INT c, lsb; 509 510 c = INTVAL (op); 511 512 if ((c & 0x80000001) != 0x80000001) 513 return 0; 514 515 c = ~c; 516 if (c == 0) 517 return 0; 518 519 lsb = c & -c; 520 c = ~c; 521 c &= -lsb; 522 lsb = c & -c; 523 return c == -lsb; 524}) 525 526;; Return 1 if the operand is a constant that is a PowerPC64 mask 527;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1 528;; transition). Reject all zeros, since zero should have been 529;; optimized away and confuses the making of MB and ME. 530(define_predicate "mask64_operand" 531 (match_code "const_int") 532{ 533 HOST_WIDE_INT c, lsb; 534 535 c = INTVAL (op); 536 537 /* Reject all zeros. */ 538 if (c == 0) 539 return 0; 540 541 /* We don't change the number of transitions by inverting, 542 so make sure we start with the LS bit zero. */ 543 if (c & 1) 544 c = ~c; 545 546 /* Find the first transition. */ 547 lsb = c & -c; 548 549 /* Match if all the bits above are 1's (or c is zero). */ 550 return c == -lsb; 551}) 552 553;; Like mask64_operand, but allow up to three transitions. This 554;; predicate is used by insn patterns that generate two rldicl or 555;; rldicr machine insns. 556(define_predicate "mask64_2_operand" 557 (match_code "const_int") 558{ 559 HOST_WIDE_INT c, lsb; 560 561 c = INTVAL (op); 562 563 /* Disallow all zeros. */ 564 if (c == 0) 565 return 0; 566 567 /* We don't change the number of transitions by inverting, 568 so make sure we start with the LS bit zero. */ 569 if (c & 1) 570 c = ~c; 571 572 /* Find the first transition. */ 573 lsb = c & -c; 574 575 /* Invert to look for a second transition. */ 576 c = ~c; 577 578 /* Erase first transition. */ 579 c &= -lsb; 580 581 /* Find the second transition. */ 582 lsb = c & -c; 583 584 /* Invert to look for a third transition. */ 585 c = ~c; 586 587 /* Erase second transition. */ 588 c &= -lsb; 589 590 /* Find the third transition (if any). */ 591 lsb = c & -c; 592 593 /* Match if all the bits above are 1's (or c is zero). */ 594 return c == -lsb; 595}) 596 597;; Like and_operand, but also match constants that can be implemented 598;; with two rldicl or rldicr insns. 599(define_predicate "and64_2_operand" 600 (ior (match_operand 0 "mask64_2_operand") 601 (if_then_else (match_test "fixed_regs[CR0_REGNO]") 602 (match_operand 0 "gpc_reg_operand") 603 (match_operand 0 "logical_operand")))) 604 605;; Return 1 if the operand is either a non-special register or a 606;; constant that can be used as the operand of a logical AND. 607(define_predicate "and_operand" 608 (ior (match_operand 0 "mask_operand") 609 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode") 610 (match_operand 0 "mask64_operand")) 611 (if_then_else (match_test "fixed_regs[CR0_REGNO]") 612 (match_operand 0 "gpc_reg_operand") 613 (match_operand 0 "logical_operand"))))) 614 615;; Return 1 if the operand is either a logical operand or a short cint operand. 616(define_predicate "scc_eq_operand" 617 (ior (match_operand 0 "logical_operand") 618 (match_operand 0 "short_cint_operand"))) 619 620;; Return 1 if the operand is a general non-special register or memory operand. 621(define_predicate "reg_or_mem_operand" 622 (ior (match_operand 0 "memory_operand") 623 (ior (and (match_code "mem") 624 (match_test "macho_lo_sum_memory_operand (op, mode)")) 625 (ior (match_operand 0 "volatile_mem_operand") 626 (match_operand 0 "gpc_reg_operand"))))) 627 628;; Return 1 if the operand is either an easy FP constant or memory or reg. 629(define_predicate "reg_or_none500mem_operand" 630 (if_then_else (match_code "mem") 631 (and (match_test "!TARGET_E500_DOUBLE") 632 (ior (match_operand 0 "memory_operand") 633 (ior (match_test "macho_lo_sum_memory_operand (op, mode)") 634 (match_operand 0 "volatile_mem_operand")))) 635 (match_operand 0 "gpc_reg_operand"))) 636 637;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand. 638(define_predicate "zero_reg_mem_operand" 639 (ior (match_operand 0 "zero_fp_constant") 640 (match_operand 0 "reg_or_mem_operand"))) 641 642;; Return 1 if the operand is a general register or memory operand without 643;; pre_inc or pre_dec, which produces invalid form of PowerPC lwa 644;; instruction. 645(define_predicate "lwa_operand" 646 (match_code "reg,subreg,mem") 647{ 648 rtx inner = op; 649 650 if (reload_completed && GET_CODE (inner) == SUBREG) 651 inner = SUBREG_REG (inner); 652 653 return gpc_reg_operand (inner, mode) 654 || (memory_operand (inner, mode) 655 && GET_CODE (XEXP (inner, 0)) != PRE_INC 656 && GET_CODE (XEXP (inner, 0)) != PRE_DEC 657 && (GET_CODE (XEXP (inner, 0)) != PLUS 658 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT 659 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); 660}) 661 662;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. 663(define_predicate "symbol_ref_operand" 664 (and (match_code "symbol_ref") 665 (match_test "(mode == VOIDmode || GET_MODE (op) == mode) 666 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))"))) 667 668;; Return 1 if op is an operand that can be loaded via the GOT. 669;; or non-special register register field no cr0 670(define_predicate "got_operand" 671 (match_code "symbol_ref,const,label_ref")) 672 673;; Return 1 if op is a simple reference that can be loaded via the GOT, 674;; excluding labels involving addition. 675(define_predicate "got_no_const_operand" 676 (match_code "symbol_ref,label_ref")) 677 678;; Return 1 if op is a SYMBOL_REF for a TLS symbol. 679(define_predicate "rs6000_tls_symbol_ref" 680 (and (match_code "symbol_ref") 681 (match_test "RS6000_SYMBOL_REF_TLS_P (op)"))) 682 683;; Return 1 if the operand, used inside a MEM, is a valid first argument 684;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. 685(define_predicate "call_operand" 686 (if_then_else (match_code "reg") 687 (match_test "REGNO (op) == LINK_REGISTER_REGNUM 688 || REGNO (op) == COUNT_REGISTER_REGNUM 689 || REGNO (op) >= FIRST_PSEUDO_REGISTER") 690 (match_code "symbol_ref"))) 691 692;; Return 1 if the operand is a SYMBOL_REF for a function known to be in 693;; this file. 694(define_predicate "current_file_function_operand" 695 (and (match_code "symbol_ref") 696 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) 697 && ((SYMBOL_REF_LOCAL_P (op) 698 && (DEFAULT_ABI != ABI_AIX 699 || !SYMBOL_REF_EXTERNAL_P (op))) 700 || (op == XEXP (DECL_RTL (current_function_decl), 701 0)))"))) 702 703;; Return 1 if this operand is a valid input for a move insn. 704(define_predicate "input_operand" 705 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem, 706 const_double,const_vector,const_int,plus") 707{ 708 /* Memory is always valid. */ 709 if (memory_operand (op, mode)) 710 return 1; 711 712 /* For floating-point, easy constants are valid. */ 713 if (SCALAR_FLOAT_MODE_P (mode) 714 && CONSTANT_P (op) 715 && easy_fp_constant (op, mode)) 716 return 1; 717 718 /* Allow any integer constant. */ 719 if (GET_MODE_CLASS (mode) == MODE_INT 720 && (GET_CODE (op) == CONST_INT 721 || GET_CODE (op) == CONST_DOUBLE)) 722 return 1; 723 724 /* Allow easy vector constants. */ 725 if (GET_CODE (op) == CONST_VECTOR 726 && easy_vector_constant (op, mode)) 727 return 1; 728 729 /* Do not allow invalid E500 subregs. */ 730 if ((TARGET_E500_DOUBLE || TARGET_SPE) 731 && GET_CODE (op) == SUBREG 732 && invalid_e500_subreg (op, mode)) 733 return 0; 734 735 /* For floating-point or multi-word mode, the only remaining valid type 736 is a register. */ 737 if (SCALAR_FLOAT_MODE_P (mode) 738 || GET_MODE_SIZE (mode) > UNITS_PER_WORD) 739 return register_operand (op, mode); 740 741 /* The only cases left are integral modes one word or smaller (we 742 do not get called for MODE_CC values). These can be in any 743 register. */ 744 if (register_operand (op, mode)) 745 return 1; 746 747 /* A SYMBOL_REF referring to the TOC is valid. */ 748 if (legitimate_constant_pool_address_p (op)) 749 return 1; 750 751 /* A constant pool expression (relative to the TOC) is valid */ 752 if (toc_relative_expr_p (op)) 753 return 1; 754 755 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region 756 to be valid. */ 757 if (DEFAULT_ABI == ABI_V4 758 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) 759 && small_data_operand (op, Pmode)) 760 return 1; 761 762 return 0; 763}) 764 765;; Return true if OP is an invalid SUBREG operation on the e500. 766(define_predicate "rs6000_nonimmediate_operand" 767 (match_code "reg,subreg,mem") 768{ 769 if ((TARGET_E500_DOUBLE || TARGET_SPE) 770 && GET_CODE (op) == SUBREG 771 && invalid_e500_subreg (op, mode)) 772 return 0; 773 774 return nonimmediate_operand (op, mode); 775}) 776 777;; Return true if operand is boolean operator. 778(define_predicate "boolean_operator" 779 (match_code "and,ior,xor")) 780 781;; Return true if operand is OR-form of boolean operator. 782(define_predicate "boolean_or_operator" 783 (match_code "ior,xor")) 784 785;; Return true if operand is an equality operator. 786(define_special_predicate "equality_operator" 787 (match_code "eq,ne")) 788 789;; Return true if operand is MIN or MAX operator. 790(define_predicate "min_max_operator" 791 (match_code "smin,smax,umin,umax")) 792 793;; Return 1 if OP is a comparison operation that is valid for a branch 794;; instruction. We check the opcode against the mode of the CC value. 795;; validate_condition_mode is an assertion. 796(define_predicate "branch_comparison_operator" 797 (and (match_operand 0 "comparison_operator") 798 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC") 799 (match_test "validate_condition_mode (GET_CODE (op), 800 GET_MODE (XEXP (op, 0))), 801 1")))) 802 803;; Return 1 if OP is a comparison operation that is valid for an SCC insn -- 804;; it must be a positive comparison. 805(define_predicate "scc_comparison_operator" 806 (and (match_operand 0 "branch_comparison_operator") 807 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 808 809;; Return 1 if OP is a comparison operation that is valid for a branch 810;; insn, which is true if the corresponding bit in the CC register is set. 811(define_predicate "branch_positive_comparison_operator" 812 (and (match_operand 0 "branch_comparison_operator") 813 (match_code "eq,lt,gt,ltu,gtu,unordered"))) 814 815;; Return 1 is OP is a comparison operation that is valid for a trap insn. 816(define_predicate "trap_comparison_operator" 817 (and (match_operand 0 "comparison_operator") 818 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu"))) 819 820;; Return 1 if OP is a load multiple operation, known to be a PARALLEL. 821(define_predicate "load_multiple_operation" 822 (match_code "parallel") 823{ 824 int count = XVECLEN (op, 0); 825 unsigned int dest_regno; 826 rtx src_addr; 827 int i; 828 829 /* Perform a quick check so we don't blow up below. */ 830 if (count <= 1 831 || GET_CODE (XVECEXP (op, 0, 0)) != SET 832 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 833 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) 834 return 0; 835 836 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 837 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); 838 839 for (i = 1; i < count; i++) 840 { 841 rtx elt = XVECEXP (op, 0, i); 842 843 if (GET_CODE (elt) != SET 844 || GET_CODE (SET_DEST (elt)) != REG 845 || GET_MODE (SET_DEST (elt)) != SImode 846 || REGNO (SET_DEST (elt)) != dest_regno + i 847 || GET_CODE (SET_SRC (elt)) != MEM 848 || GET_MODE (SET_SRC (elt)) != SImode 849 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS 850 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) 851 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT 852 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) 853 return 0; 854 } 855 856 return 1; 857}) 858 859;; Return 1 if OP is a store multiple operation, known to be a PARALLEL. 860;; The second vector element is a CLOBBER. 861(define_predicate "store_multiple_operation" 862 (match_code "parallel") 863{ 864 int count = XVECLEN (op, 0) - 1; 865 unsigned int src_regno; 866 rtx dest_addr; 867 int i; 868 869 /* Perform a quick check so we don't blow up below. */ 870 if (count <= 1 871 || GET_CODE (XVECEXP (op, 0, 0)) != SET 872 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM 873 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) 874 return 0; 875 876 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 877 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); 878 879 for (i = 1; i < count; i++) 880 { 881 rtx elt = XVECEXP (op, 0, i + 1); 882 883 if (GET_CODE (elt) != SET 884 || GET_CODE (SET_SRC (elt)) != REG 885 || GET_MODE (SET_SRC (elt)) != SImode 886 || REGNO (SET_SRC (elt)) != src_regno + i 887 || GET_CODE (SET_DEST (elt)) != MEM 888 || GET_MODE (SET_DEST (elt)) != SImode 889 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS 890 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) 891 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT 892 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) 893 return 0; 894 } 895 896 return 1; 897}) 898 899;; Return 1 if OP is valid for a save_world call in prologue, known to be 900;; a PARLLEL. 901(define_predicate "save_world_operation" 902 (match_code "parallel") 903{ 904 int index; 905 int i; 906 rtx elt; 907 int count = XVECLEN (op, 0); 908 909 if (count != 55) 910 return 0; 911 912 index = 0; 913 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 914 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 915 return 0; 916 917 for (i=1; i <= 18; i++) 918 { 919 elt = XVECEXP (op, 0, index++); 920 if (GET_CODE (elt) != SET 921 || GET_CODE (SET_DEST (elt)) != MEM 922 || ! memory_operand (SET_DEST (elt), DFmode) 923 || GET_CODE (SET_SRC (elt)) != REG 924 || GET_MODE (SET_SRC (elt)) != DFmode) 925 return 0; 926 } 927 928 for (i=1; i <= 12; i++) 929 { 930 elt = XVECEXP (op, 0, index++); 931 if (GET_CODE (elt) != SET 932 || GET_CODE (SET_DEST (elt)) != MEM 933 || GET_CODE (SET_SRC (elt)) != REG 934 || GET_MODE (SET_SRC (elt)) != V4SImode) 935 return 0; 936 } 937 938 for (i=1; i <= 19; i++) 939 { 940 elt = XVECEXP (op, 0, index++); 941 if (GET_CODE (elt) != SET 942 || GET_CODE (SET_DEST (elt)) != MEM 943 || ! memory_operand (SET_DEST (elt), Pmode) 944 || GET_CODE (SET_SRC (elt)) != REG 945 || GET_MODE (SET_SRC (elt)) != Pmode) 946 return 0; 947 } 948 949 elt = XVECEXP (op, 0, index++); 950 if (GET_CODE (elt) != SET 951 || GET_CODE (SET_DEST (elt)) != MEM 952 || ! memory_operand (SET_DEST (elt), Pmode) 953 || GET_CODE (SET_SRC (elt)) != REG 954 || REGNO (SET_SRC (elt)) != CR2_REGNO 955 || GET_MODE (SET_SRC (elt)) != Pmode) 956 return 0; 957 958 if (GET_CODE (XVECEXP (op, 0, index++)) != USE 959 || GET_CODE (XVECEXP (op, 0, index++)) != USE 960 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) 961 return 0; 962 return 1; 963}) 964 965;; Return 1 if OP is valid for a restore_world call in epilogue, known to be 966;; a PARLLEL. 967(define_predicate "restore_world_operation" 968 (match_code "parallel") 969{ 970 int index; 971 int i; 972 rtx elt; 973 int count = XVECLEN (op, 0); 974 975 if (count != 59) 976 return 0; 977 978 index = 0; 979 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN 980 || GET_CODE (XVECEXP (op, 0, index++)) != USE 981 || GET_CODE (XVECEXP (op, 0, index++)) != USE 982 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) 983 return 0; 984 985 elt = XVECEXP (op, 0, index++); 986 if (GET_CODE (elt) != SET 987 || GET_CODE (SET_SRC (elt)) != MEM 988 || ! memory_operand (SET_SRC (elt), Pmode) 989 || GET_CODE (SET_DEST (elt)) != REG 990 || REGNO (SET_DEST (elt)) != CR2_REGNO 991 || GET_MODE (SET_DEST (elt)) != Pmode) 992 return 0; 993 994 for (i=1; i <= 19; i++) 995 { 996 elt = XVECEXP (op, 0, index++); 997 if (GET_CODE (elt) != SET 998 || GET_CODE (SET_SRC (elt)) != MEM 999 || ! memory_operand (SET_SRC (elt), Pmode) 1000 || GET_CODE (SET_DEST (elt)) != REG 1001 || GET_MODE (SET_DEST (elt)) != Pmode) 1002 return 0; 1003 } 1004 1005 for (i=1; i <= 12; i++) 1006 { 1007 elt = XVECEXP (op, 0, index++); 1008 if (GET_CODE (elt) != SET 1009 || GET_CODE (SET_SRC (elt)) != MEM 1010 || GET_CODE (SET_DEST (elt)) != REG 1011 || GET_MODE (SET_DEST (elt)) != V4SImode) 1012 return 0; 1013 } 1014 1015 for (i=1; i <= 18; i++) 1016 { 1017 elt = XVECEXP (op, 0, index++); 1018 if (GET_CODE (elt) != SET 1019 || GET_CODE (SET_SRC (elt)) != MEM 1020 || ! memory_operand (SET_SRC (elt), DFmode) 1021 || GET_CODE (SET_DEST (elt)) != REG 1022 || GET_MODE (SET_DEST (elt)) != DFmode) 1023 return 0; 1024 } 1025 1026 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1027 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1028 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1029 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER 1030 || GET_CODE (XVECEXP (op, 0, index++)) != USE) 1031 return 0; 1032 return 1; 1033}) 1034 1035;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL. 1036(define_predicate "vrsave_operation" 1037 (match_code "parallel") 1038{ 1039 int count = XVECLEN (op, 0); 1040 unsigned int dest_regno, src_regno; 1041 int i; 1042 1043 if (count <= 1 1044 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1045 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 1046 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE 1047 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE) 1048 return 0; 1049 1050 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1051 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); 1052 1053 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) 1054 return 0; 1055 1056 for (i = 1; i < count; i++) 1057 { 1058 rtx elt = XVECEXP (op, 0, i); 1059 1060 if (GET_CODE (elt) != CLOBBER 1061 && GET_CODE (elt) != SET) 1062 return 0; 1063 } 1064 1065 return 1; 1066}) 1067 1068;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL. 1069(define_predicate "mfcr_operation" 1070 (match_code "parallel") 1071{ 1072 int count = XVECLEN (op, 0); 1073 int i; 1074 1075 /* Perform a quick check so we don't blow up below. */ 1076 if (count < 1 1077 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1078 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1079 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1080 return 0; 1081 1082 for (i = 0; i < count; i++) 1083 { 1084 rtx exp = XVECEXP (op, 0, i); 1085 rtx unspec; 1086 int maskval; 1087 rtx src_reg; 1088 1089 src_reg = XVECEXP (SET_SRC (exp), 0, 0); 1090 1091 if (GET_CODE (src_reg) != REG 1092 || GET_MODE (src_reg) != CCmode 1093 || ! CR_REGNO_P (REGNO (src_reg))) 1094 return 0; 1095 1096 if (GET_CODE (exp) != SET 1097 || GET_CODE (SET_DEST (exp)) != REG 1098 || GET_MODE (SET_DEST (exp)) != SImode 1099 || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) 1100 return 0; 1101 unspec = SET_SRC (exp); 1102 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); 1103 1104 if (GET_CODE (unspec) != UNSPEC 1105 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR 1106 || XVECLEN (unspec, 0) != 2 1107 || XVECEXP (unspec, 0, 0) != src_reg 1108 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT 1109 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1110 return 0; 1111 } 1112 return 1; 1113}) 1114 1115;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL. 1116(define_predicate "mtcrf_operation" 1117 (match_code "parallel") 1118{ 1119 int count = XVECLEN (op, 0); 1120 int i; 1121 rtx src_reg; 1122 1123 /* Perform a quick check so we don't blow up below. */ 1124 if (count < 1 1125 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1126 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC 1127 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) 1128 return 0; 1129 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); 1130 1131 if (GET_CODE (src_reg) != REG 1132 || GET_MODE (src_reg) != SImode 1133 || ! INT_REGNO_P (REGNO (src_reg))) 1134 return 0; 1135 1136 for (i = 0; i < count; i++) 1137 { 1138 rtx exp = XVECEXP (op, 0, i); 1139 rtx unspec; 1140 int maskval; 1141 1142 if (GET_CODE (exp) != SET 1143 || GET_CODE (SET_DEST (exp)) != REG 1144 || GET_MODE (SET_DEST (exp)) != CCmode 1145 || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) 1146 return 0; 1147 unspec = SET_SRC (exp); 1148 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); 1149 1150 if (GET_CODE (unspec) != UNSPEC 1151 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR 1152 || XVECLEN (unspec, 0) != 2 1153 || XVECEXP (unspec, 0, 0) != src_reg 1154 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT 1155 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) 1156 return 0; 1157 } 1158 return 1; 1159}) 1160 1161;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. 1162(define_predicate "lmw_operation" 1163 (match_code "parallel") 1164{ 1165 int count = XVECLEN (op, 0); 1166 unsigned int dest_regno; 1167 rtx src_addr; 1168 unsigned int base_regno; 1169 HOST_WIDE_INT offset; 1170 int i; 1171 1172 /* Perform a quick check so we don't blow up below. */ 1173 if (count <= 1 1174 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1175 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG 1176 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) 1177 return 0; 1178 1179 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); 1180 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); 1181 1182 if (dest_regno > 31 1183 || count != 32 - (int) dest_regno) 1184 return 0; 1185 1186 if (legitimate_indirect_address_p (src_addr, 0)) 1187 { 1188 offset = 0; 1189 base_regno = REGNO (src_addr); 1190 if (base_regno == 0) 1191 return 0; 1192 } 1193 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0)) 1194 { 1195 offset = INTVAL (XEXP (src_addr, 1)); 1196 base_regno = REGNO (XEXP (src_addr, 0)); 1197 } 1198 else 1199 return 0; 1200 1201 for (i = 0; i < count; i++) 1202 { 1203 rtx elt = XVECEXP (op, 0, i); 1204 rtx newaddr; 1205 rtx addr_reg; 1206 HOST_WIDE_INT newoffset; 1207 1208 if (GET_CODE (elt) != SET 1209 || GET_CODE (SET_DEST (elt)) != REG 1210 || GET_MODE (SET_DEST (elt)) != SImode 1211 || REGNO (SET_DEST (elt)) != dest_regno + i 1212 || GET_CODE (SET_SRC (elt)) != MEM 1213 || GET_MODE (SET_SRC (elt)) != SImode) 1214 return 0; 1215 newaddr = XEXP (SET_SRC (elt), 0); 1216 if (legitimate_indirect_address_p (newaddr, 0)) 1217 { 1218 newoffset = 0; 1219 addr_reg = newaddr; 1220 } 1221 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) 1222 { 1223 addr_reg = XEXP (newaddr, 0); 1224 newoffset = INTVAL (XEXP (newaddr, 1)); 1225 } 1226 else 1227 return 0; 1228 if (REGNO (addr_reg) != base_regno 1229 || newoffset != offset + 4 * i) 1230 return 0; 1231 } 1232 1233 return 1; 1234}) 1235 1236;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL. 1237(define_predicate "stmw_operation" 1238 (match_code "parallel") 1239{ 1240 int count = XVECLEN (op, 0); 1241 unsigned int src_regno; 1242 rtx dest_addr; 1243 unsigned int base_regno; 1244 HOST_WIDE_INT offset; 1245 int i; 1246 1247 /* Perform a quick check so we don't blow up below. */ 1248 if (count <= 1 1249 || GET_CODE (XVECEXP (op, 0, 0)) != SET 1250 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM 1251 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) 1252 return 0; 1253 1254 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); 1255 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); 1256 1257 if (src_regno > 31 1258 || count != 32 - (int) src_regno) 1259 return 0; 1260 1261 if (legitimate_indirect_address_p (dest_addr, 0)) 1262 { 1263 offset = 0; 1264 base_regno = REGNO (dest_addr); 1265 if (base_regno == 0) 1266 return 0; 1267 } 1268 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0)) 1269 { 1270 offset = INTVAL (XEXP (dest_addr, 1)); 1271 base_regno = REGNO (XEXP (dest_addr, 0)); 1272 } 1273 else 1274 return 0; 1275 1276 for (i = 0; i < count; i++) 1277 { 1278 rtx elt = XVECEXP (op, 0, i); 1279 rtx newaddr; 1280 rtx addr_reg; 1281 HOST_WIDE_INT newoffset; 1282 1283 if (GET_CODE (elt) != SET 1284 || GET_CODE (SET_SRC (elt)) != REG 1285 || GET_MODE (SET_SRC (elt)) != SImode 1286 || REGNO (SET_SRC (elt)) != src_regno + i 1287 || GET_CODE (SET_DEST (elt)) != MEM 1288 || GET_MODE (SET_DEST (elt)) != SImode) 1289 return 0; 1290 newaddr = XEXP (SET_DEST (elt), 0); 1291 if (legitimate_indirect_address_p (newaddr, 0)) 1292 { 1293 newoffset = 0; 1294 addr_reg = newaddr; 1295 } 1296 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) 1297 { 1298 addr_reg = XEXP (newaddr, 0); 1299 newoffset = INTVAL (XEXP (newaddr, 1)); 1300 } 1301 else 1302 return 0; 1303 if (REGNO (addr_reg) != base_regno 1304 || newoffset != offset + 4 * i) 1305 return 0; 1306 } 1307 1308 return 1; 1309}) 1310