power5.md revision 302408
1145510Sdarrenr;; Scheduling description for IBM POWER5 processor. 2145510Sdarrenr;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 3145510Sdarrenr;; 4145510Sdarrenr;; This file is part of GCC. 5145510Sdarrenr;; 6145510Sdarrenr;; GCC is free software; you can redistribute it and/or modify it 7145510Sdarrenr;; under the terms of the GNU General Public License as published 8145510Sdarrenr;; by the Free Software Foundation; either version 2, or (at your 9145510Sdarrenr;; option) any later version. 10145510Sdarrenr;; 11145510Sdarrenr;; GCC is distributed in the hope that it will be useful, but WITHOUT 12145510Sdarrenr;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13145510Sdarrenr;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14145510Sdarrenr;; License for more details. 15145510Sdarrenr;; 16145510Sdarrenr;; You should have received a copy of the GNU General Public License 17145510Sdarrenr;; along with GCC; see the file COPYING. If not, write to the 18145510Sdarrenr;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19145510Sdarrenr;; MA 02110-1301, USA. 20145510Sdarrenr 21145510Sdarrenr;; Sources: IBM Red Book and White Paper on POWER5 22145510Sdarrenr 23145510Sdarrenr;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). 24145510Sdarrenr;; Instructions that update more than one register get broken into two 25145510Sdarrenr;; (split) or more internal ops. The chip can issue up to 5 26145510Sdarrenr;; internal ops per cycle. 27145510Sdarrenr 28145510Sdarrenr(define_automaton "power5iu,power5fpu,power5misc") 29145510Sdarrenr 30145510Sdarrenr(define_cpu_unit "iu1_power5,iu2_power5" "power5iu") 31145510Sdarrenr(define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc") 32145510Sdarrenr(define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu") 33145510Sdarrenr(define_cpu_unit "bpu_power5,cru_power5" "power5misc") 34145510Sdarrenr(define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5" 35145510Sdarrenr "power5misc") 36145510Sdarrenr 37145510Sdarrenr(define_reservation "lsq_power5" 38145510Sdarrenr "(du1_power5,lsu1_power5)\ 39145510Sdarrenr |(du2_power5,lsu2_power5)\ 40145510Sdarrenr |(du3_power5,lsu2_power5)\ 41145510Sdarrenr |(du4_power5,lsu1_power5)") 42145510Sdarrenr 43145510Sdarrenr(define_reservation "iq_power5" 44145510Sdarrenr "(du1_power5,iu1_power5)\ 45145510Sdarrenr |(du2_power5,iu2_power5)\ 46145510Sdarrenr |(du3_power5,iu2_power5)\ 47145510Sdarrenr |(du4_power5,iu1_power5)") 48145510Sdarrenr 49145510Sdarrenr(define_reservation "fpq_power5" 50145510Sdarrenr "(du1_power5,fpu1_power5)\ 51145510Sdarrenr |(du2_power5,fpu2_power5)\ 52145510Sdarrenr |(du3_power5,fpu2_power5)\ 53145510Sdarrenr |(du4_power5,fpu1_power5)") 54145510Sdarrenr 55145510Sdarrenr; Dispatch slots are allocated in order conforming to program order. 56145510Sdarrenr(absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5") 57145510Sdarrenr(absence_set "du2_power5" "du3_power5,du4_power5,du5_power5") 58145510Sdarrenr(absence_set "du3_power5" "du4_power5,du5_power5") 59145510Sdarrenr(absence_set "du4_power5" "du5_power5") 60145510Sdarrenr 61145510Sdarrenr 62145510Sdarrenr; Load/store 63145510Sdarrenr(define_insn_reservation "power5-load" 4 ; 3 64145510Sdarrenr (and (eq_attr "type" "load") 65145510Sdarrenr (eq_attr "cpu" "power5")) 66145510Sdarrenr "lsq_power5") 67145510Sdarrenr 68145510Sdarrenr(define_insn_reservation "power5-load-ext" 5 69145510Sdarrenr (and (eq_attr "type" "load_ext") 70145510Sdarrenr (eq_attr "cpu" "power5")) 71145510Sdarrenr "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5") 72145510Sdarrenr 73145510Sdarrenr(define_insn_reservation "power5-load-ext-update" 5 74145510Sdarrenr (and (eq_attr "type" "load_ext_u") 75145510Sdarrenr (eq_attr "cpu" "power5")) 76145510Sdarrenr "du1_power5+du2_power5+du3_power5+du4_power5,\ 77145510Sdarrenr lsu1_power5+iu2_power5,nothing,nothing,iu2_power5") 78145510Sdarrenr 79145510Sdarrenr(define_insn_reservation "power5-load-ext-update-indexed" 5 80145510Sdarrenr (and (eq_attr "type" "load_ext_ux") 81145510Sdarrenr (eq_attr "cpu" "power5")) 82145510Sdarrenr "du1_power5+du2_power5+du3_power5+du4_power5,\ 83145510Sdarrenr iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5") 84145510Sdarrenr 85145510Sdarrenr(define_insn_reservation "power5-load-update-indexed" 3 86145510Sdarrenr (and (eq_attr "type" "load_ux") 87145510Sdarrenr (eq_attr "cpu" "power5")) 88145510Sdarrenr "du1_power5+du2_power5+du3_power5+du4_power5,\ 89145510Sdarrenr iu1_power5,lsu2_power5+iu2_power5") 90145510Sdarrenr 91145510Sdarrenr(define_insn_reservation "power5-load-update" 4 ; 3 92145510Sdarrenr (and (eq_attr "type" "load_u") 93145510Sdarrenr (eq_attr "cpu" "power5")) 94145510Sdarrenr "du1_power5+du2_power5,lsu1_power5+iu2_power5") 95145510Sdarrenr 96145510Sdarrenr(define_insn_reservation "power5-fpload" 6 ; 5 97145510Sdarrenr (and (eq_attr "type" "fpload") 98145510Sdarrenr (eq_attr "cpu" "power5")) 99145510Sdarrenr "lsq_power5") 100145510Sdarrenr 101145510Sdarrenr(define_insn_reservation "power5-fpload-update" 6 ; 5 102145510Sdarrenr (and (eq_attr "type" "fpload_u,fpload_ux") 103145510Sdarrenr (eq_attr "cpu" "power5")) 104145510Sdarrenr "du1_power5+du2_power5,lsu1_power5+iu2_power5") 105145510Sdarrenr 106145510Sdarrenr(define_insn_reservation "power5-store" 12 107145510Sdarrenr (and (eq_attr "type" "store") 108145510Sdarrenr (eq_attr "cpu" "power5")) 109145510Sdarrenr "(du1_power5,lsu1_power5,iu1_power5)\ 110145510Sdarrenr |(du2_power5,lsu2_power5,iu2_power5)\ 111145510Sdarrenr |(du3_power5,lsu2_power5,iu2_power5)\ 112145510Sdarrenr |(du4_power5,lsu1_power5,iu1_power5)") 113145510Sdarrenr 114145510Sdarrenr(define_insn_reservation "power5-store-update" 12 115145510Sdarrenr (and (eq_attr "type" "store_u") 116145510Sdarrenr (eq_attr "cpu" "power5")) 117145510Sdarrenr "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") 118145510Sdarrenr 119145510Sdarrenr(define_insn_reservation "power5-store-update-indexed" 12 120145510Sdarrenr (and (eq_attr "type" "store_ux") 121145510Sdarrenr (eq_attr "cpu" "power5")) 122145510Sdarrenr "du1_power5+du2_power5+du3_power5+du4_power5,\ 123145510Sdarrenr iu1_power5,lsu2_power5+iu2_power5,iu2_power5") 124145510Sdarrenr 125145510Sdarrenr(define_insn_reservation "power5-fpstore" 12 126145510Sdarrenr (and (eq_attr "type" "fpstore") 127145510Sdarrenr (eq_attr "cpu" "power5")) 128145510Sdarrenr "(du1_power5,lsu1_power5,fpu1_power5)\ 129145510Sdarrenr |(du2_power5,lsu2_power5,fpu2_power5)\ 130145510Sdarrenr |(du3_power5,lsu2_power5,fpu2_power5)\ 131145510Sdarrenr |(du4_power5,lsu1_power5,fpu1_power5)") 132145510Sdarrenr 133145510Sdarrenr(define_insn_reservation "power5-fpstore-update" 12 134145510Sdarrenr (and (eq_attr "type" "fpstore_u,fpstore_ux") 135145510Sdarrenr (eq_attr "cpu" "power5")) 136145510Sdarrenr "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") 137145510Sdarrenr 138145510Sdarrenr(define_insn_reservation "power5-llsc" 11 139145510Sdarrenr (and (eq_attr "type" "load_l,store_c,sync") 140145510Sdarrenr (eq_attr "cpu" "power5")) 141145510Sdarrenr "du1_power5+du2_power5+du3_power5+du4_power5,\ 142145510Sdarrenr lsu1_power5") 143145510Sdarrenr 144145510Sdarrenr 145145510Sdarrenr; Integer latency is 2 cycles 146145510Sdarrenr(define_insn_reservation "power5-integer" 2 147145510Sdarrenr (and (eq_attr "type" "integer") 148145510Sdarrenr (eq_attr "cpu" "power5")) 149145510Sdarrenr "iq_power5") 150145510Sdarrenr 151145510Sdarrenr(define_insn_reservation "power5-two" 2 152145510Sdarrenr (and (eq_attr "type" "two") 153145510Sdarrenr (eq_attr "cpu" "power5")) 154145510Sdarrenr "(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\ 155145510Sdarrenr |(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\ 156145510Sdarrenr |(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\ 157145510Sdarrenr |(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)") 158145510Sdarrenr 159145510Sdarrenr(define_insn_reservation "power5-three" 2 160145510Sdarrenr (and (eq_attr "type" "three") 161145510Sdarrenr (eq_attr "cpu" "power5")) 162145510Sdarrenr "(du1_power5+du2_power5+du3_power5,\ 163145510Sdarrenr iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\ 164145510Sdarrenr |(du2_power5+du3_power5+du4_power5,\ 165145510Sdarrenr iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\ 166145510Sdarrenr |(du3_power5+du4_power5+du1_power5,\ 167145510Sdarrenr iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\ 168145510Sdarrenr |(du4_power5+du1_power5+du2_power5,\ 169145510Sdarrenr iu1_power5,nothing,iu2_power5,nothing,iu2_power5)") 170145510Sdarrenr 171145510Sdarrenr(define_insn_reservation "power5-insert" 4 172145510Sdarrenr (and (eq_attr "type" "insert_word") 173145510Sdarrenr (eq_attr "cpu" "power5")) 174145510Sdarrenr "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5") 175145510Sdarrenr 176145510Sdarrenr(define_insn_reservation "power5-cmp" 3 177145510Sdarrenr (and (eq_attr "type" "cmp,fast_compare") 178145510Sdarrenr (eq_attr "cpu" "power5")) 179145510Sdarrenr "iq_power5") 180145510Sdarrenr 181145510Sdarrenr(define_insn_reservation "power5-compare" 2 182145510Sdarrenr (and (eq_attr "type" "compare,delayed_compare") 183145510Sdarrenr (eq_attr "cpu" "power5")) 184145510Sdarrenr "du1_power5+du2_power5,iu1_power5,iu2_power5") 185145510Sdarrenr 186145510Sdarrenr(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 187145510Sdarrenr 188145510Sdarrenr(define_insn_reservation "power5-lmul-cmp" 7 189145510Sdarrenr (and (eq_attr "type" "lmul_compare") 190145510Sdarrenr (eq_attr "cpu" "power5")) 191145510Sdarrenr "du1_power5+du2_power5,iu1_power5*6,iu2_power5") 192145510Sdarrenr 193145510Sdarrenr(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 194145510Sdarrenr 195145510Sdarrenr(define_insn_reservation "power5-imul-cmp" 5 196145510Sdarrenr (and (eq_attr "type" "imul_compare") 197145510Sdarrenr (eq_attr "cpu" "power5")) 198145510Sdarrenr "du1_power5+du2_power5,iu1_power5*4,iu2_power5") 199145510Sdarrenr 200145510Sdarrenr(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 201145510Sdarrenr 202145510Sdarrenr(define_insn_reservation "power5-lmul" 7 203145510Sdarrenr (and (eq_attr "type" "lmul") 204145510Sdarrenr (eq_attr "cpu" "power5")) 205145510Sdarrenr "(du1_power5,iu1_power5*6)\ 206145510Sdarrenr |(du2_power5,iu2_power5*6)\ 207145510Sdarrenr |(du3_power5,iu2_power5*6)\ 208145510Sdarrenr |(du4_power5,iu1_power5*6)") 209145510Sdarrenr 210145510Sdarrenr(define_insn_reservation "power5-imul" 5 211145510Sdarrenr (and (eq_attr "type" "imul") 212145510Sdarrenr (eq_attr "cpu" "power5")) 213145510Sdarrenr "(du1_power5,iu1_power5*4)\ 214145510Sdarrenr |(du2_power5,iu2_power5*4)\ 215145510Sdarrenr |(du3_power5,iu2_power5*4)\ 216145510Sdarrenr |(du4_power5,iu1_power5*4)") 217145510Sdarrenr 218145510Sdarrenr(define_insn_reservation "power5-imul3" 4 219145510Sdarrenr (and (eq_attr "type" "imul2,imul3") 220145510Sdarrenr (eq_attr "cpu" "power5")) 221145510Sdarrenr "(du1_power5,iu1_power5*3)\ 222145510Sdarrenr |(du2_power5,iu2_power5*3)\ 223145510Sdarrenr |(du3_power5,iu2_power5*3)\ 224145510Sdarrenr |(du4_power5,iu1_power5*3)") 225145510Sdarrenr 226145510Sdarrenr 227145510Sdarrenr; SPR move only executes in first IU. 228145510Sdarrenr; Integer division only executes in second IU. 229145510Sdarrenr(define_insn_reservation "power5-idiv" 36 230145510Sdarrenr (and (eq_attr "type" "idiv") 231145510Sdarrenr (eq_attr "cpu" "power5")) 232145510Sdarrenr "du1_power5+du2_power5,iu2_power5*35") 233145510Sdarrenr 234145510Sdarrenr(define_insn_reservation "power5-ldiv" 68 235145510Sdarrenr (and (eq_attr "type" "ldiv") 236145510Sdarrenr (eq_attr "cpu" "power5")) 237145510Sdarrenr "du1_power5+du2_power5,iu2_power5*67") 238145510Sdarrenr 239145510Sdarrenr 240145510Sdarrenr(define_insn_reservation "power5-mtjmpr" 3 241145510Sdarrenr (and (eq_attr "type" "mtjmpr,mfjmpr") 242145510Sdarrenr (eq_attr "cpu" "power5")) 243145510Sdarrenr "du1_power5,bpu_power5") 244145510Sdarrenr 245145510Sdarrenr 246145510Sdarrenr; Branches take dispatch Slot 4. The presence_sets prevent other insn from 247145510Sdarrenr; grabbing previous dispatch slots once this is assigned. 248145510Sdarrenr(define_insn_reservation "power5-branch" 2 249145510Sdarrenr (and (eq_attr "type" "jmpreg,branch") 250145510Sdarrenr (eq_attr "cpu" "power5")) 251145510Sdarrenr "(du5_power5\ 252145510Sdarrenr |du4_power5+du5_power5\ 253145510Sdarrenr |du3_power5+du4_power5+du5_power5\ 254145510Sdarrenr |du2_power5+du3_power5+du4_power5+du5_power5\ 255145510Sdarrenr |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5") 256145510Sdarrenr 257145510Sdarrenr 258145510Sdarrenr; Condition Register logical ops are split if non-destructive (RT != RB) 259145510Sdarrenr(define_insn_reservation "power5-crlogical" 2 260145510Sdarrenr (and (eq_attr "type" "cr_logical") 261145510Sdarrenr (eq_attr "cpu" "power5")) 262145510Sdarrenr "du1_power5,cru_power5") 263145510Sdarrenr 264145510Sdarrenr(define_insn_reservation "power5-delayedcr" 4 265145510Sdarrenr (and (eq_attr "type" "delayed_cr") 266145510Sdarrenr (eq_attr "cpu" "power5")) 267145510Sdarrenr "du1_power5+du2_power5,cru_power5,cru_power5") 268145510Sdarrenr 269145510Sdarrenr; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu 270145510Sdarrenr(define_insn_reservation "power5-mfcr" 6 271145510Sdarrenr (and (eq_attr "type" "mfcr") 272145510Sdarrenr (eq_attr "cpu" "power5")) 273145510Sdarrenr "du1_power5+du2_power5+du3_power5+du4_power5,\ 274145510Sdarrenr du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\ 275145510Sdarrenr cru_power5,cru_power5,cru_power5") 276145510Sdarrenr 277145510Sdarrenr; mfcrf (1 field) 278145510Sdarrenr(define_insn_reservation "power5-mfcrf" 3 279145510Sdarrenr (and (eq_attr "type" "mfcrf") 280145510Sdarrenr (eq_attr "cpu" "power5")) 281145510Sdarrenr "du1_power5,cru_power5") 282145510Sdarrenr 283145510Sdarrenr; mtcrf (1 field) 284145510Sdarrenr(define_insn_reservation "power5-mtcr" 4 285145510Sdarrenr (and (eq_attr "type" "mtcr") 286145510Sdarrenr (eq_attr "cpu" "power5")) 287145510Sdarrenr "du1_power5,iu1_power5") 288145510Sdarrenr 289145510Sdarrenr; Basic FP latency is 6 cycles 290145510Sdarrenr(define_insn_reservation "power5-fp" 6 291145510Sdarrenr (and (eq_attr "type" "fp,dmul") 292145510Sdarrenr (eq_attr "cpu" "power5")) 293145510Sdarrenr "fpq_power5") 294145510Sdarrenr 295145510Sdarrenr(define_insn_reservation "power5-fpcompare" 5 296145510Sdarrenr (and (eq_attr "type" "fpcompare") 297145510Sdarrenr (eq_attr "cpu" "power5")) 298145510Sdarrenr "fpq_power5") 299145510Sdarrenr 300145510Sdarrenr(define_insn_reservation "power5-sdiv" 33 301145510Sdarrenr (and (eq_attr "type" "sdiv,ddiv") 302145510Sdarrenr (eq_attr "cpu" "power5")) 303145510Sdarrenr "(du1_power5,fpu1_power5*28)\ 304145510Sdarrenr |(du2_power5,fpu2_power5*28)\ 305145510Sdarrenr |(du3_power5,fpu2_power5*28)\ 306145510Sdarrenr |(du4_power5,fpu1_power5*28)") 307145510Sdarrenr 308145510Sdarrenr(define_insn_reservation "power5-sqrt" 40 309145510Sdarrenr (and (eq_attr "type" "ssqrt,dsqrt") 310145510Sdarrenr (eq_attr "cpu" "power5")) 311145510Sdarrenr "(du1_power5,fpu1_power5*35)\ 312145510Sdarrenr |(du2_power5,fpu2_power5*35)\ 313145510Sdarrenr |(du3_power5,fpu2_power5*35)\ 314145510Sdarrenr |(du4_power5,fpu2_power5*35)") 315145510Sdarrenr 316145510Sdarrenr(define_insn_reservation "power5-isync" 2 317145510Sdarrenr (and (eq_attr "type" "isync") 318145510Sdarrenr (eq_attr "cpu" "power5")) 319145510Sdarrenr "du1_power5+du2_power5+du3_power5+du4_power5,\ 320145510Sdarrenr lsu1_power5") 321145510Sdarrenr 322145510Sdarrenr