1132718Skan;; Scheduling description for IBM POWER5 processor. 2132718Skan;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 3132718Skan;; 4132718Skan;; This file is part of GCC. 5132718Skan;; 6132718Skan;; GCC is free software; you can redistribute it and/or modify it 7132718Skan;; under the terms of the GNU General Public License as published 8132718Skan;; by the Free Software Foundation; either version 2, or (at your 9132718Skan;; option) any later version. 10132718Skan;; 11132718Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT 12132718Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13132718Skan;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14132718Skan;; License for more details. 15132718Skan;; 16132718Skan;; You should have received a copy of the GNU General Public License 17132718Skan;; along with GCC; see the file COPYING. If not, write to the 18169689Skan;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19169689Skan;; MA 02110-1301, USA. 20132718Skan 21132718Skan;; Sources: IBM Red Book and White Paper on POWER5 22132718Skan 23132718Skan;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). 24132718Skan;; Instructions that update more than one register get broken into two 25132718Skan;; (split) or more internal ops. The chip can issue up to 5 26132718Skan;; internal ops per cycle. 27132718Skan 28132718Skan(define_automaton "power5iu,power5fpu,power5misc") 29132718Skan 30132718Skan(define_cpu_unit "iu1_power5,iu2_power5" "power5iu") 31132718Skan(define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc") 32132718Skan(define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu") 33132718Skan(define_cpu_unit "bpu_power5,cru_power5" "power5misc") 34132718Skan(define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5" 35132718Skan "power5misc") 36132718Skan 37132718Skan(define_reservation "lsq_power5" 38132718Skan "(du1_power5,lsu1_power5)\ 39132718Skan |(du2_power5,lsu2_power5)\ 40169689Skan |(du3_power5,lsu2_power5)\ 41169689Skan |(du4_power5,lsu1_power5)") 42132718Skan 43132718Skan(define_reservation "iq_power5" 44132718Skan "(du1_power5,iu1_power5)\ 45132718Skan |(du2_power5,iu2_power5)\ 46169689Skan |(du3_power5,iu2_power5)\ 47169689Skan |(du4_power5,iu1_power5)") 48132718Skan 49132718Skan(define_reservation "fpq_power5" 50132718Skan "(du1_power5,fpu1_power5)\ 51132718Skan |(du2_power5,fpu2_power5)\ 52169689Skan |(du3_power5,fpu2_power5)\ 53169689Skan |(du4_power5,fpu1_power5)") 54132718Skan 55132718Skan; Dispatch slots are allocated in order conforming to program order. 56132718Skan(absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5") 57132718Skan(absence_set "du2_power5" "du3_power5,du4_power5,du5_power5") 58132718Skan(absence_set "du3_power5" "du4_power5,du5_power5") 59132718Skan(absence_set "du4_power5" "du5_power5") 60132718Skan 61132718Skan 62132718Skan; Load/store 63132718Skan(define_insn_reservation "power5-load" 4 ; 3 64132718Skan (and (eq_attr "type" "load") 65132718Skan (eq_attr "cpu" "power5")) 66132718Skan "lsq_power5") 67132718Skan 68132718Skan(define_insn_reservation "power5-load-ext" 5 69132718Skan (and (eq_attr "type" "load_ext") 70132718Skan (eq_attr "cpu" "power5")) 71132718Skan "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5") 72132718Skan 73132718Skan(define_insn_reservation "power5-load-ext-update" 5 74132718Skan (and (eq_attr "type" "load_ext_u") 75132718Skan (eq_attr "cpu" "power5")) 76132718Skan "du1_power5+du2_power5+du3_power5+du4_power5,\ 77132718Skan lsu1_power5+iu2_power5,nothing,nothing,iu2_power5") 78132718Skan 79132718Skan(define_insn_reservation "power5-load-ext-update-indexed" 5 80132718Skan (and (eq_attr "type" "load_ext_ux") 81132718Skan (eq_attr "cpu" "power5")) 82132718Skan "du1_power5+du2_power5+du3_power5+du4_power5,\ 83132718Skan iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5") 84132718Skan 85132718Skan(define_insn_reservation "power5-load-update-indexed" 3 86132718Skan (and (eq_attr "type" "load_ux") 87132718Skan (eq_attr "cpu" "power5")) 88132718Skan "du1_power5+du2_power5+du3_power5+du4_power5,\ 89132718Skan iu1_power5,lsu2_power5+iu2_power5") 90132718Skan 91132718Skan(define_insn_reservation "power5-load-update" 4 ; 3 92132718Skan (and (eq_attr "type" "load_u") 93132718Skan (eq_attr "cpu" "power5")) 94132718Skan "du1_power5+du2_power5,lsu1_power5+iu2_power5") 95132718Skan 96132718Skan(define_insn_reservation "power5-fpload" 6 ; 5 97132718Skan (and (eq_attr "type" "fpload") 98132718Skan (eq_attr "cpu" "power5")) 99132718Skan "lsq_power5") 100132718Skan 101132718Skan(define_insn_reservation "power5-fpload-update" 6 ; 5 102132718Skan (and (eq_attr "type" "fpload_u,fpload_ux") 103132718Skan (eq_attr "cpu" "power5")) 104132718Skan "du1_power5+du2_power5,lsu1_power5+iu2_power5") 105132718Skan 106169689Skan(define_insn_reservation "power5-store" 12 107132718Skan (and (eq_attr "type" "store") 108132718Skan (eq_attr "cpu" "power5")) 109132718Skan "(du1_power5,lsu1_power5,iu1_power5)\ 110132718Skan |(du2_power5,lsu2_power5,iu2_power5)\ 111169689Skan |(du3_power5,lsu2_power5,iu2_power5)\ 112169689Skan |(du4_power5,lsu1_power5,iu1_power5)") 113132718Skan 114169689Skan(define_insn_reservation "power5-store-update" 12 115132718Skan (and (eq_attr "type" "store_u") 116132718Skan (eq_attr "cpu" "power5")) 117132718Skan "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") 118132718Skan 119169689Skan(define_insn_reservation "power5-store-update-indexed" 12 120132718Skan (and (eq_attr "type" "store_ux") 121132718Skan (eq_attr "cpu" "power5")) 122132718Skan "du1_power5+du2_power5+du3_power5+du4_power5,\ 123132718Skan iu1_power5,lsu2_power5+iu2_power5,iu2_power5") 124132718Skan 125169689Skan(define_insn_reservation "power5-fpstore" 12 126132718Skan (and (eq_attr "type" "fpstore") 127132718Skan (eq_attr "cpu" "power5")) 128132718Skan "(du1_power5,lsu1_power5,fpu1_power5)\ 129132718Skan |(du2_power5,lsu2_power5,fpu2_power5)\ 130169689Skan |(du3_power5,lsu2_power5,fpu2_power5)\ 131169689Skan |(du4_power5,lsu1_power5,fpu1_power5)") 132132718Skan 133169689Skan(define_insn_reservation "power5-fpstore-update" 12 134132718Skan (and (eq_attr "type" "fpstore_u,fpstore_ux") 135132718Skan (eq_attr "cpu" "power5")) 136132718Skan "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") 137132718Skan 138169689Skan(define_insn_reservation "power5-llsc" 11 139169689Skan (and (eq_attr "type" "load_l,store_c,sync") 140169689Skan (eq_attr "cpu" "power5")) 141169689Skan "du1_power5+du2_power5+du3_power5+du4_power5,\ 142169689Skan lsu1_power5") 143132718Skan 144169689Skan 145132718Skan; Integer latency is 2 cycles 146132718Skan(define_insn_reservation "power5-integer" 2 147132718Skan (and (eq_attr "type" "integer") 148132718Skan (eq_attr "cpu" "power5")) 149132718Skan "iq_power5") 150132718Skan 151169689Skan(define_insn_reservation "power5-two" 2 152169689Skan (and (eq_attr "type" "two") 153169689Skan (eq_attr "cpu" "power5")) 154169689Skan "(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\ 155169689Skan |(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\ 156169689Skan |(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\ 157169689Skan |(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)") 158169689Skan 159169689Skan(define_insn_reservation "power5-three" 2 160169689Skan (and (eq_attr "type" "three") 161169689Skan (eq_attr "cpu" "power5")) 162169689Skan "(du1_power5+du2_power5+du3_power5,\ 163169689Skan iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\ 164169689Skan |(du2_power5+du3_power5+du4_power5,\ 165169689Skan iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\ 166169689Skan |(du3_power5+du4_power5+du1_power5,\ 167169689Skan iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\ 168169689Skan |(du4_power5+du1_power5+du2_power5,\ 169169689Skan iu1_power5,nothing,iu2_power5,nothing,iu2_power5)") 170169689Skan 171132718Skan(define_insn_reservation "power5-insert" 4 172132718Skan (and (eq_attr "type" "insert_word") 173132718Skan (eq_attr "cpu" "power5")) 174132718Skan "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5") 175132718Skan 176132718Skan(define_insn_reservation "power5-cmp" 3 177132718Skan (and (eq_attr "type" "cmp,fast_compare") 178132718Skan (eq_attr "cpu" "power5")) 179132718Skan "iq_power5") 180132718Skan 181132718Skan(define_insn_reservation "power5-compare" 2 182132718Skan (and (eq_attr "type" "compare,delayed_compare") 183132718Skan (eq_attr "cpu" "power5")) 184132718Skan "du1_power5+du2_power5,iu1_power5,iu2_power5") 185132718Skan 186132718Skan(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 187132718Skan 188132718Skan(define_insn_reservation "power5-lmul-cmp" 7 189132718Skan (and (eq_attr "type" "lmul_compare") 190132718Skan (eq_attr "cpu" "power5")) 191132718Skan "du1_power5+du2_power5,iu1_power5*6,iu2_power5") 192132718Skan 193132718Skan(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 194132718Skan 195132718Skan(define_insn_reservation "power5-imul-cmp" 5 196132718Skan (and (eq_attr "type" "imul_compare") 197132718Skan (eq_attr "cpu" "power5")) 198132718Skan "du1_power5+du2_power5,iu1_power5*4,iu2_power5") 199132718Skan 200132718Skan(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 201132718Skan 202132718Skan(define_insn_reservation "power5-lmul" 7 203132718Skan (and (eq_attr "type" "lmul") 204132718Skan (eq_attr "cpu" "power5")) 205132718Skan "(du1_power5,iu1_power5*6)\ 206132718Skan |(du2_power5,iu2_power5*6)\ 207132718Skan |(du3_power5,iu2_power5*6)\ 208169689Skan |(du4_power5,iu1_power5*6)") 209132718Skan 210132718Skan(define_insn_reservation "power5-imul" 5 211132718Skan (and (eq_attr "type" "imul") 212132718Skan (eq_attr "cpu" "power5")) 213132718Skan "(du1_power5,iu1_power5*4)\ 214132718Skan |(du2_power5,iu2_power5*4)\ 215132718Skan |(du3_power5,iu2_power5*4)\ 216132718Skan |(du4_power5,iu1_power5*4)") 217132718Skan 218132718Skan(define_insn_reservation "power5-imul3" 4 219132718Skan (and (eq_attr "type" "imul2,imul3") 220132718Skan (eq_attr "cpu" "power5")) 221132718Skan "(du1_power5,iu1_power5*3)\ 222132718Skan |(du2_power5,iu2_power5*3)\ 223132718Skan |(du3_power5,iu2_power5*3)\ 224132718Skan |(du4_power5,iu1_power5*3)") 225132718Skan 226132718Skan 227132718Skan; SPR move only executes in first IU. 228132718Skan; Integer division only executes in second IU. 229132718Skan(define_insn_reservation "power5-idiv" 36 230132718Skan (and (eq_attr "type" "idiv") 231132718Skan (eq_attr "cpu" "power5")) 232132718Skan "du1_power5+du2_power5,iu2_power5*35") 233132718Skan 234132718Skan(define_insn_reservation "power5-ldiv" 68 235132718Skan (and (eq_attr "type" "ldiv") 236132718Skan (eq_attr "cpu" "power5")) 237132718Skan "du1_power5+du2_power5,iu2_power5*67") 238132718Skan 239132718Skan 240132718Skan(define_insn_reservation "power5-mtjmpr" 3 241132718Skan (and (eq_attr "type" "mtjmpr,mfjmpr") 242132718Skan (eq_attr "cpu" "power5")) 243132718Skan "du1_power5,bpu_power5") 244132718Skan 245132718Skan 246132718Skan; Branches take dispatch Slot 4. The presence_sets prevent other insn from 247132718Skan; grabbing previous dispatch slots once this is assigned. 248132718Skan(define_insn_reservation "power5-branch" 2 249132718Skan (and (eq_attr "type" "jmpreg,branch") 250132718Skan (eq_attr "cpu" "power5")) 251132718Skan "(du5_power5\ 252132718Skan |du4_power5+du5_power5\ 253132718Skan |du3_power5+du4_power5+du5_power5\ 254132718Skan |du2_power5+du3_power5+du4_power5+du5_power5\ 255132718Skan |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5") 256132718Skan 257132718Skan 258132718Skan; Condition Register logical ops are split if non-destructive (RT != RB) 259132718Skan(define_insn_reservation "power5-crlogical" 2 260132718Skan (and (eq_attr "type" "cr_logical") 261132718Skan (eq_attr "cpu" "power5")) 262132718Skan "du1_power5,cru_power5") 263132718Skan 264132718Skan(define_insn_reservation "power5-delayedcr" 4 265132718Skan (and (eq_attr "type" "delayed_cr") 266132718Skan (eq_attr "cpu" "power5")) 267132718Skan "du1_power5+du2_power5,cru_power5,cru_power5") 268132718Skan 269132718Skan; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu 270132718Skan(define_insn_reservation "power5-mfcr" 6 271132718Skan (and (eq_attr "type" "mfcr") 272132718Skan (eq_attr "cpu" "power5")) 273132718Skan "du1_power5+du2_power5+du3_power5+du4_power5,\ 274132718Skan du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\ 275132718Skan cru_power5,cru_power5,cru_power5") 276132718Skan 277132718Skan; mfcrf (1 field) 278132718Skan(define_insn_reservation "power5-mfcrf" 3 279132718Skan (and (eq_attr "type" "mfcrf") 280132718Skan (eq_attr "cpu" "power5")) 281132718Skan "du1_power5,cru_power5") 282132718Skan 283132718Skan; mtcrf (1 field) 284132718Skan(define_insn_reservation "power5-mtcr" 4 285132718Skan (and (eq_attr "type" "mtcr") 286132718Skan (eq_attr "cpu" "power5")) 287132718Skan "du1_power5,iu1_power5") 288132718Skan 289132718Skan; Basic FP latency is 6 cycles 290132718Skan(define_insn_reservation "power5-fp" 6 291132718Skan (and (eq_attr "type" "fp,dmul") 292132718Skan (eq_attr "cpu" "power5")) 293132718Skan "fpq_power5") 294132718Skan 295132718Skan(define_insn_reservation "power5-fpcompare" 5 296132718Skan (and (eq_attr "type" "fpcompare") 297132718Skan (eq_attr "cpu" "power5")) 298132718Skan "fpq_power5") 299132718Skan 300132718Skan(define_insn_reservation "power5-sdiv" 33 301132718Skan (and (eq_attr "type" "sdiv,ddiv") 302132718Skan (eq_attr "cpu" "power5")) 303132718Skan "(du1_power5,fpu1_power5*28)\ 304132718Skan |(du2_power5,fpu2_power5*28)\ 305132718Skan |(du3_power5,fpu2_power5*28)\ 306132718Skan |(du4_power5,fpu1_power5*28)") 307132718Skan 308132718Skan(define_insn_reservation "power5-sqrt" 40 309132718Skan (and (eq_attr "type" "ssqrt,dsqrt") 310132718Skan (eq_attr "cpu" "power5")) 311132718Skan "(du1_power5,fpu1_power5*35)\ 312132718Skan |(du2_power5,fpu2_power5*35)\ 313132718Skan |(du3_power5,fpu2_power5*35)\ 314132718Skan |(du4_power5,fpu2_power5*35)") 315132718Skan 316169689Skan(define_insn_reservation "power5-isync" 2 317169689Skan (and (eq_attr "type" "isync") 318169689Skan (eq_attr "cpu" "power5")) 319169689Skan "du1_power5+du2_power5+du3_power5+du4_power5,\ 320169689Skan lsu1_power5") 321169689Skan 322