power4.md revision 169690
1139743Simp;; Scheduling description for IBM Power4 and PowerPC 970 processors. 239212Sgibbs;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 339212Sgibbs;; 439212Sgibbs;; This file is part of GCC. 539212Sgibbs;; 639212Sgibbs;; GCC is free software; you can redistribute it and/or modify it 739212Sgibbs;; under the terms of the GNU General Public License as published 839212Sgibbs;; by the Free Software Foundation; either version 2, or (at your 939212Sgibbs;; option) any later version. 1039212Sgibbs;; 1139212Sgibbs;; GCC is distributed in the hope that it will be useful, but WITHOUT 1239212Sgibbs;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 1339212Sgibbs;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 1439212Sgibbs;; License for more details. 1539212Sgibbs;; 1639212Sgibbs;; You should have received a copy of the GNU General Public License 1739212Sgibbs;; along with GCC; see the file COPYING. If not, write to the 1839212Sgibbs;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 1939212Sgibbs;; MA 02110-1301, USA. 2039212Sgibbs 2139212Sgibbs;; Sources: IBM Red Book and White Paper on POWER4 2239212Sgibbs 2339212Sgibbs;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). 2439212Sgibbs;; Instructions that update more than one register get broken into two 2539212Sgibbs;; (split) or more internal ops. The chip can issue up to 5 2639212Sgibbs;; internal ops per cycle. 2739212Sgibbs 28116161Sobrien(define_automaton "power4iu,power4fpu,power4vec,power4misc") 29116161Sobrien 30116161Sobrien(define_cpu_unit "iu1_power4,iu2_power4" "power4iu") 31116161Sobrien(define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc") 3239212Sgibbs(define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu") 3374840Sken(define_cpu_unit "bpu_power4,cru_power4" "power4misc") 3474840Sken(define_cpu_unit "vec_power4,vecperm_power4" "power4vec") 3589114Smsmith(define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4" 3689114Smsmith "power4misc") 3774840Sken 3874840Sken(define_reservation "lsq_power4" 3974840Sken "(du1_power4,lsu1_power4)\ 40216088Sken |(du2_power4,lsu2_power4)\ 41194189Sed |(du3_power4,lsu2_power4)\ 4274840Sken |(du4_power4,lsu1_power4)") 4374840Sken 4439212Sgibbs(define_reservation "lsuq_power4" 4574840Sken "(du1_power4+du2_power4,lsu1_power4+iu2_power4)\ 4674840Sken |(du2_power4+du3_power4,lsu2_power4+iu2_power4)\ 47216088Sken |(du3_power4+du4_power4,lsu2_power4+iu1_power4)") 4874840Sken 4939212Sgibbs(define_reservation "iq_power4" 5074840Sken "(du1_power4,iu1_power4)\ 5174840Sken |(du2_power4,iu2_power4)\ 52195534Sscottl |(du3_power4,iu2_power4)\ 5374840Sken |(du4_power4,iu1_power4)") 54219028Snetchild 55219028Snetchild(define_reservation "fpq_power4" 56219028Snetchild "(du1_power4,fpu1_power4)\ 5774840Sken |(du2_power4,fpu2_power4)\ 5874840Sken |(du3_power4,fpu2_power4)\ 5974840Sken |(du4_power4,fpu1_power4)") 6074840Sken 6174840Sken(define_reservation "vq_power4" 6274840Sken "(du1_power4,vec_power4)\ 6374840Sken |(du2_power4,vec_power4)\ 6474840Sken |(du3_power4,vec_power4)\ 6574840Sken |(du4_power4,vec_power4)") 6674840Sken 67210779Sbcr(define_reservation "vpq_power4" 6874840Sken "(du1_power4,vecperm_power4)\ 6974840Sken |(du2_power4,vecperm_power4)\ 7074840Sken |(du3_power4,vecperm_power4)\ 7174840Sken |(du4_power4,vecperm_power4)") 7274840Sken 7374840Sken 7474840Sken; Dispatch slots are allocated in order conforming to program order. 7574840Sken(absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4") 7674840Sken(absence_set "du2_power4" "du3_power4,du4_power4,du5_power4") 7774840Sken(absence_set "du3_power4" "du4_power4,du5_power4") 7874840Sken(absence_set "du4_power4" "du5_power4") 7974840Sken 8074840Sken 8174840Sken; Load/store 8274840Sken(define_insn_reservation "power4-load" 4 ; 3 8374840Sken (and (eq_attr "type" "load") 8474840Sken (eq_attr "cpu" "power4")) 8574840Sken "lsq_power4") 8674840Sken 8774840Sken(define_insn_reservation "power4-load-ext" 5 8874840Sken (and (eq_attr "type" "load_ext") 8974840Sken (eq_attr "cpu" "power4")) 90195534Sscottl "(du1_power4+du2_power4,lsu1_power4,nothing,nothing,iu2_power4)\ 91216088Sken |(du2_power4+du3_power4,lsu2_power4,nothing,nothing,iu2_power4)\ 92216088Sken |(du3_power4+du4_power4,lsu2_power4,nothing,nothing,iu1_power4)") 9374840Sken 9474840Sken(define_insn_reservation "power4-load-ext-update" 5 9574840Sken (and (eq_attr "type" "load_ext_u") 9674840Sken (eq_attr "cpu" "power4")) 9774840Sken "du1_power4+du2_power4+du3_power4+du4_power4,\ 9874840Sken lsu1_power4+iu2_power4,nothing,nothing,iu2_power4") 9974840Sken 10074840Sken(define_insn_reservation "power4-load-ext-update-indexed" 5 10174840Sken (and (eq_attr "type" "load_ext_ux") 10274840Sken (eq_attr "cpu" "power4")) 10374840Sken "du1_power4+du2_power4+du3_power4+du4_power4,\ 10474840Sken iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4") 10574840Sken 10674840Sken(define_insn_reservation "power4-load-update-indexed" 3 10774840Sken (and (eq_attr "type" "load_ux") 10874840Sken (eq_attr "cpu" "power4")) 10974840Sken "du1_power4+du2_power4+du3_power4+du4_power4,\ 11074840Sken iu1_power4,lsu2_power4+iu2_power4") 11189114Smsmith 11289114Smsmith(define_insn_reservation "power4-load-update" 4 ; 3 113251301Ssmh (and (eq_attr "type" "load_u") 114251301Ssmh (eq_attr "cpu" "power4")) 115251301Ssmh "lsuq_power4") 11689114Smsmith 11789114Smsmith(define_insn_reservation "power4-fpload" 6 ; 5 118251301Ssmh (and (eq_attr "type" "fpload") 119251301Ssmh (eq_attr "cpu" "power4")) 120251301Ssmh "lsq_power4") 121251301Ssmh 122251301Ssmh(define_insn_reservation "power4-fpload-update" 6 ; 5 123251301Ssmh (and (eq_attr "type" "fpload_u,fpload_ux") 12439212Sgibbs (eq_attr "cpu" "power4")) 12539212Sgibbs "lsuq_power4") 12639212Sgibbs 12739212Sgibbs(define_insn_reservation "power4-vecload" 6 ; 5 12839552Sgibbs (and (eq_attr "type" "vecload") 12939212Sgibbs (eq_attr "cpu" "power4")) 13039212Sgibbs "lsq_power4") 13139552Sgibbs 13239552Sgibbs(define_insn_reservation "power4-store" 12 13339212Sgibbs (and (eq_attr "type" "store") 13439212Sgibbs (eq_attr "cpu" "power4")) 13539212Sgibbs "(du1_power4,lsu1_power4,iu1_power4)\ 13639212Sgibbs |(du2_power4,lsu2_power4,iu2_power4)\ 13739212Sgibbs |(du3_power4,lsu2_power4,iu2_power4)\ 13839212Sgibbs |(du4_power4,lsu1_power4,iu1_power4)") 13939212Sgibbs 14039212Sgibbs(define_insn_reservation "power4-store-update" 12 14139212Sgibbs (and (eq_attr "type" "store_u") 14239212Sgibbs (eq_attr "cpu" "power4")) 14339212Sgibbs "(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\ 14439212Sgibbs |(du2_power4+du3_power4,lsu2_power4+iu2_power4,iu2_power4)\ 14539212Sgibbs |(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\ 14639212Sgibbs |(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)") 14739212Sgibbs 14839212Sgibbs(define_insn_reservation "power4-store-update-indexed" 12 14939212Sgibbs (and (eq_attr "type" "store_ux") 15039212Sgibbs (eq_attr "cpu" "power4")) 15139212Sgibbs "du1_power4+du2_power4+du3_power4+du4_power4,\ 15239212Sgibbs iu1_power4,lsu2_power4+iu2_power4,iu2_power4") 15339212Sgibbs 15439212Sgibbs(define_insn_reservation "power4-fpstore" 12 15539212Sgibbs (and (eq_attr "type" "fpstore") 15639212Sgibbs (eq_attr "cpu" "power4")) 15739212Sgibbs "(du1_power4,lsu1_power4,fpu1_power4)\ 15839212Sgibbs |(du2_power4,lsu2_power4,fpu2_power4)\ 15939212Sgibbs |(du3_power4,lsu2_power4,fpu2_power4)\ 16039212Sgibbs |(du4_power4,lsu1_power4,fpu1_power4)") 16139212Sgibbs 16239212Sgibbs(define_insn_reservation "power4-fpstore-update" 12 16339212Sgibbs (and (eq_attr "type" "fpstore_u,fpstore_ux") 16439212Sgibbs (eq_attr "cpu" "power4")) 16539212Sgibbs "(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\ 16639212Sgibbs |(du2_power4+du3_power4,lsu2_power4+iu2_power4,fpu2_power4)\ 16739212Sgibbs |(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)") 16839212Sgibbs 16939212Sgibbs(define_insn_reservation "power4-vecstore" 12 17039212Sgibbs (and (eq_attr "type" "vecstore") 17139212Sgibbs (eq_attr "cpu" "power4")) 17239212Sgibbs "(du1_power4,lsu1_power4,vec_power4)\ 17339212Sgibbs |(du2_power4,lsu2_power4,vec_power4)\ 17439212Sgibbs |(du3_power4,lsu2_power4,vec_power4)\ 17539212Sgibbs |(du4_power4,lsu1_power4,vec_power4)") 17639212Sgibbs 17739212Sgibbs(define_insn_reservation "power4-llsc" 11 17839212Sgibbs (and (eq_attr "type" "load_l,store_c,sync") 17939212Sgibbs (eq_attr "cpu" "power4")) 18039212Sgibbs "du1_power4+du2_power4+du3_power4+du4_power4,\ 18139212Sgibbs lsu1_power4") 18239212Sgibbs 18339212Sgibbs 184199178Smav; Integer latency is 2 cycles 185199178Smav(define_insn_reservation "power4-integer" 2 18639212Sgibbs (and (eq_attr "type" "integer") 187199178Smav (eq_attr "cpu" "power4")) 188199178Smav "iq_power4") 189199178Smav 19039212Sgibbs(define_insn_reservation "power4-two" 2 19139212Sgibbs (and (eq_attr "type" "two") 19239212Sgibbs (eq_attr "cpu" "power4")) 19339212Sgibbs "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\ 19439212Sgibbs |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\ 19539212Sgibbs |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)\ 19639212Sgibbs |(du4_power4+du1_power4,iu1_power4,nothing,iu1_power4)") 19739212Sgibbs 19839212Sgibbs(define_insn_reservation "power4-three" 2 19939212Sgibbs (and (eq_attr "type" "three") 20039212Sgibbs (eq_attr "cpu" "power4")) 20139212Sgibbs "(du1_power4+du2_power4+du3_power4,\ 20239212Sgibbs iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\ 20339212Sgibbs |(du2_power4+du3_power4+du4_power4,\ 20474840Sken iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\ 20574840Sken |(du3_power4+du4_power4+du1_power4,\ 20674840Sken iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\ 20774840Sken |(du4_power4+du1_power4+du2_power4,\ 20874840Sken iu1_power4,nothing,iu2_power4,nothing,iu2_power4)") 20974840Sken 21074840Sken(define_insn_reservation "power4-insert" 4 21174840Sken (and (eq_attr "type" "insert_word") 21274840Sken (eq_attr "cpu" "power4")) 21374840Sken "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\ 21474840Sken |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\ 21574840Sken |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)") 21674840Sken 21774840Sken(define_insn_reservation "power4-cmp" 3 21874840Sken (and (eq_attr "type" "cmp,fast_compare") 21974840Sken (eq_attr "cpu" "power4")) 22074840Sken "iq_power4") 22174840Sken 22274840Sken(define_insn_reservation "power4-compare" 2 22374840Sken (and (eq_attr "type" "compare,delayed_compare") 22474840Sken (eq_attr "cpu" "power4")) 22574840Sken "(du1_power4+du2_power4,iu1_power4,iu2_power4)\ 22674840Sken |(du2_power4+du3_power4,iu2_power4,iu2_power4)\ 22774840Sken |(du3_power4+du4_power4,iu2_power4,iu1_power4)") 22874840Sken 22974840Sken(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 23074840Sken 23174840Sken(define_insn_reservation "power4-lmul-cmp" 7 23274840Sken (and (eq_attr "type" "lmul_compare") 23374840Sken (eq_attr "cpu" "power4")) 23474840Sken "(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\ 23574840Sken |(du2_power4+du3_power4,iu2_power4*6,iu2_power4)\ 23674840Sken |(du3_power4+du4_power4,iu2_power4*6,iu1_power4)") 23774840Sken 23874840Sken(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 23974840Sken 24074840Sken(define_insn_reservation "power4-imul-cmp" 5 24174840Sken (and (eq_attr "type" "imul_compare") 24274840Sken (eq_attr "cpu" "power4")) 24374840Sken "(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\ 24474840Sken |(du2_power4+du3_power4,iu2_power4*4,iu2_power4)\ 24574840Sken |(du3_power4+du4_power4,iu2_power4*4,iu1_power4)") 24674840Sken 24774840Sken(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 24874840Sken 24974840Sken(define_insn_reservation "power4-lmul" 7 25074840Sken (and (eq_attr "type" "lmul") 25174840Sken (eq_attr "cpu" "power4")) 252198849Smav "(du1_power4,iu1_power4*6)\ 253198849Smav |(du2_power4,iu2_power4*6)\ 254198849Smav |(du3_power4,iu2_power4*6)\ 255198849Smav |(du4_power4,iu1_power4*6)") 256198849Smav 257198849Smav(define_insn_reservation "power4-imul" 5 258198849Smav (and (eq_attr "type" "imul") 259198849Smav (eq_attr "cpu" "power4")) 260198849Smav "(du1_power4,iu1_power4*4)\ 261198849Smav |(du2_power4,iu2_power4*4)\ 262198849Smav |(du3_power4,iu2_power4*4)\ 263198849Smav |(du4_power4,iu1_power4*4)") 264198849Smav 265198849Smav(define_insn_reservation "power4-imul3" 4 266198849Smav (and (eq_attr "type" "imul2,imul3") 26774840Sken (eq_attr "cpu" "power4")) 26874840Sken "(du1_power4,iu1_power4*3)\ 26974840Sken |(du2_power4,iu2_power4*3)\ 27074840Sken |(du3_power4,iu2_power4*3)\ 27174840Sken |(du4_power4,iu1_power4*3)") 27274840Sken 27374840Sken 27474840Sken; SPR move only executes in first IU. 27574840Sken; Integer division only executes in second IU. 27674840Sken(define_insn_reservation "power4-idiv" 36 277115562Sphk (and (eq_attr "type" "idiv") 27874840Sken (eq_attr "cpu" "power4")) 27974840Sken "du1_power4+du2_power4,iu2_power4*35") 28074840Sken 28174840Sken(define_insn_reservation "power4-ldiv" 68 282216088Sken (and (eq_attr "type" "ldiv") 283216088Sken (eq_attr "cpu" "power4")) 284216088Sken "du1_power4+du2_power4,iu2_power4*67") 285216088Sken 286216088Sken 287216088Sken(define_insn_reservation "power4-mtjmpr" 3 288216088Sken (and (eq_attr "type" "mtjmpr,mfjmpr") 289216088Sken (eq_attr "cpu" "power4")) 290216088Sken "du1_power4,bpu_power4") 291216088Sken 292216088Sken 293216088Sken; Branches take dispatch Slot 4. The presence_sets prevent other insn from 294216088Sken; grabbing previous dispatch slots once this is assigned. 295216088Sken(define_insn_reservation "power4-branch" 2 296216088Sken (and (eq_attr "type" "jmpreg,branch") 29774840Sken (eq_attr "cpu" "power4")) 29874840Sken "(du5_power4\ 29974840Sken |du4_power4+du5_power4\ 30074840Sken |du3_power4+du4_power4+du5_power4\ 30174840Sken |du2_power4+du3_power4+du4_power4+du5_power4\ 30274840Sken |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4") 30374840Sken 30474840Sken 30574840Sken; Condition Register logical ops are split if non-destructive (RT != RB) 30674840Sken(define_insn_reservation "power4-crlogical" 2 30774840Sken (and (eq_attr "type" "cr_logical") 30874840Sken (eq_attr "cpu" "power4")) 30974840Sken "du1_power4,cru_power4") 31074840Sken 311198849Smav(define_insn_reservation "power4-delayedcr" 4 312198849Smav (and (eq_attr "type" "delayed_cr") 313198849Smav (eq_attr "cpu" "power4")) 314198849Smav "du1_power4+du2_power4,cru_power4,cru_power4") 31574840Sken 31674840Sken; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu 31774840Sken(define_insn_reservation "power4-mfcr" 6 31874840Sken (and (eq_attr "type" "mfcr") 31974840Sken (eq_attr "cpu" "power4")) 32074840Sken "du1_power4+du2_power4+du3_power4+du4_power4,\ 32174840Sken du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\ 32274840Sken cru_power4,cru_power4,cru_power4") 323216088Sken 324216088Sken; mfcrf (1 field) 325216088Sken(define_insn_reservation "power4-mfcrf" 3 326216088Sken (and (eq_attr "type" "mfcrf") 327216088Sken (eq_attr "cpu" "power4")) 328216088Sken "du1_power4,cru_power4") 32974840Sken 33074840Sken; mtcrf (1 field) 33174840Sken(define_insn_reservation "power4-mtcr" 4 33274840Sken (and (eq_attr "type" "mtcr") 33374840Sken (eq_attr "cpu" "power4")) 33474840Sken "du1_power4,iu1_power4") 33574840Sken 33674840Sken; Basic FP latency is 6 cycles 33774840Sken(define_insn_reservation "power4-fp" 6 33874840Sken (and (eq_attr "type" "fp,dmul") 33974840Sken (eq_attr "cpu" "power4")) 34074840Sken "fpq_power4") 34174840Sken 34274840Sken(define_insn_reservation "power4-fpcompare" 5 34374840Sken (and (eq_attr "type" "fpcompare") 34474840Sken (eq_attr "cpu" "power4")) 345203108Smav "fpq_power4") 34674840Sken 34774840Sken(define_insn_reservation "power4-sdiv" 33 348203108Smav (and (eq_attr "type" "sdiv,ddiv") 34974840Sken (eq_attr "cpu" "power4")) 35074840Sken "(du1_power4,fpu1_power4*28)\ 35174840Sken |(du2_power4,fpu2_power4*28)\ 35274840Sken |(du3_power4,fpu2_power4*28)\ 35374840Sken |(du4_power4,fpu1_power4*28)") 35474840Sken 355198849Smav(define_insn_reservation "power4-sqrt" 40 356198849Smav (and (eq_attr "type" "ssqrt,dsqrt") 357198849Smav (eq_attr "cpu" "power4")) 358198849Smav "(du1_power4,fpu1_power4*35)\ 359198849Smav |(du2_power4,fpu2_power4*35)\ 360198849Smav |(du3_power4,fpu2_power4*35)\ 361198849Smav |(du4_power4,fpu2_power4*35)") 362198849Smav 363198849Smav(define_insn_reservation "power4-isync" 2 364198849Smav (and (eq_attr "type" "isync") 365198849Smav (eq_attr "cpu" "power4")) 366198849Smav "du1_power4+du2_power4+du3_power4+du4_power4,\ 367198849Smav lsu1_power4") 368198849Smav 369198849Smav 370198849Smav; VMX 37174840Sken(define_insn_reservation "power4-vecsimple" 2 37274840Sken (and (eq_attr "type" "vecsimple") 37374840Sken (eq_attr "cpu" "power4")) 37474840Sken "vq_power4") 37574840Sken 37674840Sken(define_insn_reservation "power4-veccomplex" 5 37774840Sken (and (eq_attr "type" "veccomplex") 378203108Smav (eq_attr "cpu" "power4")) 37974840Sken "vq_power4") 38074840Sken 38174840Sken; vecfp compare 38274840Sken(define_insn_reservation "power4-veccmp" 8 38374840Sken (and (eq_attr "type" "veccmp") 38474840Sken (eq_attr "cpu" "power4")) 38574840Sken "vq_power4") 38674840Sken 38774840Sken(define_insn_reservation "power4-vecfloat" 8 38874840Sken (and (eq_attr "type" "vecfloat") 38974840Sken (eq_attr "cpu" "power4")) 39074840Sken "vq_power4") 39174840Sken 39274840Sken(define_insn_reservation "power4-vecperm" 2 39374840Sken (and (eq_attr "type" "vecperm") 39474840Sken (eq_attr "cpu" "power4")) 395216088Sken "vpq_power4") 396216088Sken 397216088Sken(define_bypass 4 "power4-vecload" "power4-vecperm") 398216088Sken 399216088Sken(define_bypass 3 "power4-vecsimple" "power4-vecperm") 400216088Sken(define_bypass 6 "power4-veccomplex" "power4-vecperm") 401216088Sken(define_bypass 3 "power4-vecperm" 402216088Sken "power4-vecsimple,power4-veccomplex,power4-vecfloat") 403216088Sken(define_bypass 9 "power4-vecfloat" "power4-vecperm") 404216088Sken 405216088Sken(define_bypass 5 "power4-vecsimple,power4-veccomplex" 406216088Sken "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 407216088Sken 40874840Sken(define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore") 40974840Sken(define_bypass 7 "power4-veccomplex" "power4-vecstore") 41074840Sken(define_bypass 10 "power4-vecfloat" "power4-vecstore") 41174840Sken