mpc.md revision 302408
1;; Scheduling description for Motorola PowerPC processor cores. 2;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 2, or (at your 9;; option) any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to the 18;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19;; MA 02110-1301, USA. 20 21(define_automaton "mpc,mpcfp") 22(define_cpu_unit "iu_mpc,mciu_mpc" "mpc") 23(define_cpu_unit "fpu_mpc" "mpcfp") 24(define_cpu_unit "lsu_mpc,bpu_mpc" "mpc") 25 26;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU 27;; 505/801/821/823 28 29(define_insn_reservation "mpccore-load" 2 30 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ 31 load_l,store_c,sync") 32 (eq_attr "cpu" "mpccore")) 33 "lsu_mpc") 34 35(define_insn_reservation "mpccore-store" 2 36 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") 37 (eq_attr "cpu" "mpccore")) 38 "lsu_mpc") 39 40(define_insn_reservation "mpccore-fpload" 2 41 (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 42 (eq_attr "cpu" "mpccore")) 43 "lsu_mpc") 44 45(define_insn_reservation "mpccore-integer" 1 46 (and (eq_attr "type" "integer,insert_word") 47 (eq_attr "cpu" "mpccore")) 48 "iu_mpc") 49 50(define_insn_reservation "mpccore-two" 1 51 (and (eq_attr "type" "two") 52 (eq_attr "cpu" "mpccore")) 53 "iu_mpc,iu_mpc") 54 55(define_insn_reservation "mpccore-three" 1 56 (and (eq_attr "type" "three") 57 (eq_attr "cpu" "mpccore")) 58 "iu_mpc,iu_mpc,iu_mpc") 59 60(define_insn_reservation "mpccore-imul" 2 61 (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 62 (eq_attr "cpu" "mpccore")) 63 "mciu_mpc") 64 65; Divide latency varies greatly from 2-11, use 6 as average 66(define_insn_reservation "mpccore-idiv" 6 67 (and (eq_attr "type" "idiv") 68 (eq_attr "cpu" "mpccore")) 69 "mciu_mpc*6") 70 71(define_insn_reservation "mpccore-compare" 3 72 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare") 73 (eq_attr "cpu" "mpccore")) 74 "iu_mpc,nothing,bpu_mpc") 75 76(define_insn_reservation "mpccore-fpcompare" 2 77 (and (eq_attr "type" "fpcompare") 78 (eq_attr "cpu" "mpccore")) 79 "fpu_mpc,bpu_mpc") 80 81(define_insn_reservation "mpccore-fp" 4 82 (and (eq_attr "type" "fp") 83 (eq_attr "cpu" "mpccore")) 84 "fpu_mpc*2") 85 86(define_insn_reservation "mpccore-dmul" 5 87 (and (eq_attr "type" "dmul") 88 (eq_attr "cpu" "mpccore")) 89 "fpu_mpc*5") 90 91(define_insn_reservation "mpccore-sdiv" 10 92 (and (eq_attr "type" "sdiv") 93 (eq_attr "cpu" "mpccore")) 94 "fpu_mpc*10") 95 96(define_insn_reservation "mpccore-ddiv" 17 97 (and (eq_attr "type" "ddiv") 98 (eq_attr "cpu" "mpccore")) 99 "fpu_mpc*17") 100 101(define_insn_reservation "mpccore-mtjmpr" 4 102 (and (eq_attr "type" "mtjmpr,mfjmpr") 103 (eq_attr "cpu" "mpccore")) 104 "bpu_mpc") 105 106(define_insn_reservation "mpccore-jmpreg" 1 107 (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync") 108 (eq_attr "cpu" "mpccore")) 109 "bpu_mpc") 110 111