7450.md revision 169690 
1;; Scheduling description for Motorola PowerPC 7450 processor.
2;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5
6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published
8;; by the Free Software Foundation; either version 2, or (at your
9;; option) any later version.
10
11;; GCC is distributed in the hope that it will be useful, but WITHOUT
12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14;; License for more details.
15
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING.  If not, write to the
18;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19;; MA 02110-1301, USA.
20
21(define_automaton "ppc7450,ppc7450mciu,ppc7450fp,ppc7450vec")
22(define_cpu_unit "iu1_7450,iu2_7450,iu3_7450" "ppc7450")
23(define_cpu_unit "mciu_7450" "ppc7450mciu")
24(define_cpu_unit "fpu_7450" "ppc7450fp")
25(define_cpu_unit "lsu_7450,bpu_7450" "ppc7450")
26(define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450")
27(define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec")
28(define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec")
29
30
31;; PPC7450  32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
32;; IU1,IU2,IU3 can perform all integer operations
33;; MCIU performs imul and idiv, cr logical, SPR moves
34;; LSU 2 stage pipelined
35;; FPU 3 stage pipelined
36;; It also has 4 vector units, one for each type of vector instruction.
37;; However, we can only dispatch 2 instructions per cycle. 
38;; Max issue 3 insns/clock cycle (includes 1 branch)
39;; In-order execution
40
41;; Branches go straight to the BPU.  All other insns are handled
42;; by a dispatch unit which can issue a max of 3 insns per cycle.
43(define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450")
44(define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
45
46(define_insn_reservation "ppc7450-load" 3
47  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\
48		        load_ux,load_u,vecload")
49       (eq_attr "cpu" "ppc7450"))
50  "ppc7450_du,lsu_7450")
51
52(define_insn_reservation "ppc7450-store" 3
53  (and (eq_attr "type" "store,store_ux,store_u,vecstore")
54       (eq_attr "cpu" "ppc7450"))
55  "ppc7450_du,lsu_7450")
56
57(define_insn_reservation "ppc7450-fpload" 4
58  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
59       (eq_attr "cpu" "ppc7450"))
60  "ppc7450_du,lsu_7450")
61
62(define_insn_reservation "ppc7450-fpstore" 3
63  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
64       (eq_attr "cpu" "ppc7450"))
65  "ppc7450_du,lsu_7450*3")
66
67(define_insn_reservation "ppc7450-llsc" 3
68  (and (eq_attr "type" "load_l,store_c")
69       (eq_attr "cpu" "ppc7450"))
70  "ppc7450_du,lsu_7450")
71
72(define_insn_reservation "ppc7450-sync" 35
73  (and (eq_attr "type" "sync")
74       (eq_attr "cpu" "ppc7450"))
75  "ppc7450_du,lsu_7450")
76
77(define_insn_reservation "ppc7450-integer" 1
78  (and (eq_attr "type" "integer,insert_word")
79       (eq_attr "cpu" "ppc7450"))
80  "ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
81
82(define_insn_reservation "ppc7450-two" 1
83  (and (eq_attr "type" "two")
84       (eq_attr "cpu" "ppc7450"))
85  "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
86
87(define_insn_reservation "ppc7450-three" 1
88  (and (eq_attr "type" "three")
89       (eq_attr "cpu" "ppc7450"))
90  "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
91   iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
92
93(define_insn_reservation "ppc7450-imul" 4
94  (and (eq_attr "type" "imul,imul_compare")
95       (eq_attr "cpu" "ppc7450"))
96  "ppc7450_du,mciu_7450*2")
97
98(define_insn_reservation "ppc7450-imul2" 3
99  (and (eq_attr "type" "imul2,imul3")
100       (eq_attr "cpu" "ppc7450"))
101  "ppc7450_du,mciu_7450")
102
103(define_insn_reservation "ppc7450-idiv" 23
104  (and (eq_attr "type" "idiv")
105       (eq_attr "cpu" "ppc7450"))
106  "ppc7450_du,mciu_7450*23")
107
108(define_insn_reservation "ppc7450-compare" 2
109  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
110       (eq_attr "cpu" "ppc7450"))
111  "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
112
113(define_insn_reservation "ppc7450-fpcompare" 5
114  (and (eq_attr "type" "fpcompare")
115       (eq_attr "cpu" "ppc7450"))
116  "ppc7450_du,fpu_7450")
117
118(define_insn_reservation "ppc7450-fp" 5
119  (and (eq_attr "type" "fp,dmul")
120       (eq_attr "cpu" "ppc7450"))
121  "ppc7450_du,fpu_7450")
122
123; Divides are not pipelined
124(define_insn_reservation "ppc7450-sdiv" 21
125  (and (eq_attr "type" "sdiv")
126       (eq_attr "cpu" "ppc7450"))
127  "ppc7450_du,fpu_7450*21")
128
129(define_insn_reservation "ppc7450-ddiv" 35
130  (and (eq_attr "type" "ddiv")
131       (eq_attr "cpu" "ppc7450"))
132  "ppc7450_du,fpu_7450*35")
133
134(define_insn_reservation "ppc7450-mfcr" 2
135  (and (eq_attr "type" "mfcr,mtcr")
136       (eq_attr "cpu" "ppc7450"))
137  "ppc7450_du,mciu_7450")
138
139(define_insn_reservation "ppc7450-crlogical" 1
140  (and (eq_attr "type" "cr_logical,delayed_cr")
141       (eq_attr "cpu" "ppc7450"))
142  "ppc7450_du,mciu_7450")
143
144(define_insn_reservation "ppc7450-mtjmpr" 2
145  (and (eq_attr "type" "mtjmpr")
146       (eq_attr "cpu" "ppc7450"))
147  "nothing,mciu_7450*2")
148
149(define_insn_reservation "ppc7450-mfjmpr" 3
150  (and (eq_attr "type" "mfjmpr")
151       (eq_attr "cpu" "ppc7450"))
152  "nothing,mciu_7450*2")
153
154(define_insn_reservation "ppc7450-jmpreg" 1
155  (and (eq_attr "type" "jmpreg,branch,isync")
156       (eq_attr "cpu" "ppc7450"))
157  "nothing,bpu_7450")
158
159;; Altivec
160(define_insn_reservation "ppc7450-vecsimple" 1
161  (and (eq_attr "type" "vecsimple")
162       (eq_attr "cpu" "ppc7450"))
163  "ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
164
165(define_insn_reservation "ppc7450-veccomplex" 4
166  (and (eq_attr "type" "veccomplex")
167       (eq_attr "cpu" "ppc7450"))
168  "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
169
170(define_insn_reservation "ppc7450-veccmp" 2
171  (and (eq_attr "type" "veccmp")
172       (eq_attr "cpu" "ppc7450"))
173  "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
174
175(define_insn_reservation "ppc7450-vecfloat" 4
176  (and (eq_attr "type" "vecfloat")
177       (eq_attr "cpu" "ppc7450"))
178  "ppc7450_du,ppc7450_vec_du,vecflt_7450")
179
180(define_insn_reservation "ppc7450-vecperm" 2
181  (and (eq_attr "type" "vecperm")
182       (eq_attr "cpu" "ppc7450"))
183  "ppc7450_du,ppc7450_vec_du,vecperm_7450")
184
185