7450.md revision 169690
1218885Sdim;; Scheduling description for Motorola PowerPC 7450 processor.
2218885Sdim;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
3218885Sdim;;
4218885Sdim;; This file is part of GCC.
5218885Sdim
6218885Sdim;; GCC is free software; you can redistribute it and/or modify it
7218885Sdim;; under the terms of the GNU General Public License as published
8218885Sdim;; by the Free Software Foundation; either version 2, or (at your
9218885Sdim;; option) any later version.
10218885Sdim
11218885Sdim;; GCC is distributed in the hope that it will be useful, but WITHOUT
12218885Sdim;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13218885Sdim;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14218885Sdim;; License for more details.
15218885Sdim
16218885Sdim;; You should have received a copy of the GNU General Public License
17218885Sdim;; along with GCC; see the file COPYING.  If not, write to the
18218885Sdim;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19218885Sdim;; MA 02110-1301, USA.
20218885Sdim
21218885Sdim(define_automaton "ppc7450,ppc7450mciu,ppc7450fp,ppc7450vec")
22218885Sdim(define_cpu_unit "iu1_7450,iu2_7450,iu3_7450" "ppc7450")
23218885Sdim(define_cpu_unit "mciu_7450" "ppc7450mciu")
24218885Sdim(define_cpu_unit "fpu_7450" "ppc7450fp")
25218885Sdim(define_cpu_unit "lsu_7450,bpu_7450" "ppc7450")
26218885Sdim(define_cpu_unit "du1_7450,du2_7450,du3_7450" "ppc7450")
27218885Sdim(define_cpu_unit "vecsmpl_7450,veccmplx_7450,vecflt_7450,vecperm_7450" "ppc7450vec")
28218885Sdim(define_cpu_unit "vdu1_7450,vdu2_7450" "ppc7450vec")
29218885Sdim
30218885Sdim
31218885Sdim;; PPC7450  32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
32218885Sdim;; IU1,IU2,IU3 can perform all integer operations
33218885Sdim;; MCIU performs imul and idiv, cr logical, SPR moves
34218885Sdim;; LSU 2 stage pipelined
35218885Sdim;; FPU 3 stage pipelined
36218885Sdim;; It also has 4 vector units, one for each type of vector instruction.
37218885Sdim;; However, we can only dispatch 2 instructions per cycle. 
38218885Sdim;; Max issue 3 insns/clock cycle (includes 1 branch)
39218885Sdim;; In-order execution
40218885Sdim
41218885Sdim;; Branches go straight to the BPU.  All other insns are handled
42218885Sdim;; by a dispatch unit which can issue a max of 3 insns per cycle.
43218885Sdim(define_reservation "ppc7450_du" "du1_7450|du2_7450|du3_7450")
44218885Sdim(define_reservation "ppc7450_vec_du" "vdu1_7450|vdu2_7450")
45218885Sdim
46218885Sdim(define_insn_reservation "ppc7450-load" 3
47218885Sdim  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\
48218885Sdim		        load_ux,load_u,vecload")
49218885Sdim       (eq_attr "cpu" "ppc7450"))
50218885Sdim  "ppc7450_du,lsu_7450")
51218885Sdim
52218885Sdim(define_insn_reservation "ppc7450-store" 3
53218885Sdim  (and (eq_attr "type" "store,store_ux,store_u,vecstore")
54218885Sdim       (eq_attr "cpu" "ppc7450"))
55218885Sdim  "ppc7450_du,lsu_7450")
56218885Sdim
57218885Sdim(define_insn_reservation "ppc7450-fpload" 4
58218885Sdim  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
59218885Sdim       (eq_attr "cpu" "ppc7450"))
60218885Sdim  "ppc7450_du,lsu_7450")
61218885Sdim
62218885Sdim(define_insn_reservation "ppc7450-fpstore" 3
63218885Sdim  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
64218885Sdim       (eq_attr "cpu" "ppc7450"))
65218885Sdim  "ppc7450_du,lsu_7450*3")
66218885Sdim
67218885Sdim(define_insn_reservation "ppc7450-llsc" 3
68218885Sdim  (and (eq_attr "type" "load_l,store_c")
69218885Sdim       (eq_attr "cpu" "ppc7450"))
70218885Sdim  "ppc7450_du,lsu_7450")
71218885Sdim
72218885Sdim(define_insn_reservation "ppc7450-sync" 35
73218885Sdim  (and (eq_attr "type" "sync")
74218885Sdim       (eq_attr "cpu" "ppc7450"))
75218885Sdim  "ppc7450_du,lsu_7450")
76218885Sdim
77218885Sdim(define_insn_reservation "ppc7450-integer" 1
78218885Sdim  (and (eq_attr "type" "integer,insert_word")
79218885Sdim       (eq_attr "cpu" "ppc7450"))
80218885Sdim  "ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
81218885Sdim
82218885Sdim(define_insn_reservation "ppc7450-two" 1
83218885Sdim  (and (eq_attr "type" "two")
84218885Sdim       (eq_attr "cpu" "ppc7450"))
85218885Sdim  "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
86218885Sdim
87218885Sdim(define_insn_reservation "ppc7450-three" 1
88218885Sdim  (and (eq_attr "type" "three")
89218885Sdim       (eq_attr "cpu" "ppc7450"))
90218885Sdim  "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
91218885Sdim   iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
92218885Sdim
93218885Sdim(define_insn_reservation "ppc7450-imul" 4
94218885Sdim  (and (eq_attr "type" "imul,imul_compare")
95218885Sdim       (eq_attr "cpu" "ppc7450"))
96218885Sdim  "ppc7450_du,mciu_7450*2")
97218885Sdim
98218885Sdim(define_insn_reservation "ppc7450-imul2" 3
99218885Sdim  (and (eq_attr "type" "imul2,imul3")
100218885Sdim       (eq_attr "cpu" "ppc7450"))
101218885Sdim  "ppc7450_du,mciu_7450")
102218885Sdim
103218885Sdim(define_insn_reservation "ppc7450-idiv" 23
104218885Sdim  (and (eq_attr "type" "idiv")
105218885Sdim       (eq_attr "cpu" "ppc7450"))
106218885Sdim  "ppc7450_du,mciu_7450*23")
107218885Sdim
108218885Sdim(define_insn_reservation "ppc7450-compare" 2
109218885Sdim  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
110218885Sdim       (eq_attr "cpu" "ppc7450"))
111218885Sdim  "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
112218885Sdim
113218885Sdim(define_insn_reservation "ppc7450-fpcompare" 5
114218885Sdim  (and (eq_attr "type" "fpcompare")
115218885Sdim       (eq_attr "cpu" "ppc7450"))
116218885Sdim  "ppc7450_du,fpu_7450")
117218885Sdim
118218885Sdim(define_insn_reservation "ppc7450-fp" 5
119218885Sdim  (and (eq_attr "type" "fp,dmul")
120218885Sdim       (eq_attr "cpu" "ppc7450"))
121218885Sdim  "ppc7450_du,fpu_7450")
122218885Sdim
123218885Sdim; Divides are not pipelined
124218885Sdim(define_insn_reservation "ppc7450-sdiv" 21
125218885Sdim  (and (eq_attr "type" "sdiv")
126218885Sdim       (eq_attr "cpu" "ppc7450"))
127218885Sdim  "ppc7450_du,fpu_7450*21")
128218885Sdim
129218885Sdim(define_insn_reservation "ppc7450-ddiv" 35
130218885Sdim  (and (eq_attr "type" "ddiv")
131218885Sdim       (eq_attr "cpu" "ppc7450"))
132218885Sdim  "ppc7450_du,fpu_7450*35")
133218885Sdim
134218885Sdim(define_insn_reservation "ppc7450-mfcr" 2
135218885Sdim  (and (eq_attr "type" "mfcr,mtcr")
136218885Sdim       (eq_attr "cpu" "ppc7450"))
137218885Sdim  "ppc7450_du,mciu_7450")
138218885Sdim
139218885Sdim(define_insn_reservation "ppc7450-crlogical" 1
140218885Sdim  (and (eq_attr "type" "cr_logical,delayed_cr")
141218885Sdim       (eq_attr "cpu" "ppc7450"))
142218885Sdim  "ppc7450_du,mciu_7450")
143218885Sdim
144218885Sdim(define_insn_reservation "ppc7450-mtjmpr" 2
145218885Sdim  (and (eq_attr "type" "mtjmpr")
146218885Sdim       (eq_attr "cpu" "ppc7450"))
147218885Sdim  "nothing,mciu_7450*2")
148218885Sdim
149218885Sdim(define_insn_reservation "ppc7450-mfjmpr" 3
150218885Sdim  (and (eq_attr "type" "mfjmpr")
151218885Sdim       (eq_attr "cpu" "ppc7450"))
152218885Sdim  "nothing,mciu_7450*2")
153218885Sdim
154218885Sdim(define_insn_reservation "ppc7450-jmpreg" 1
155  (and (eq_attr "type" "jmpreg,branch,isync")
156       (eq_attr "cpu" "ppc7450"))
157  "nothing,bpu_7450")
158
159;; Altivec
160(define_insn_reservation "ppc7450-vecsimple" 1
161  (and (eq_attr "type" "vecsimple")
162       (eq_attr "cpu" "ppc7450"))
163  "ppc7450_du,ppc7450_vec_du,vecsmpl_7450")
164
165(define_insn_reservation "ppc7450-veccomplex" 4
166  (and (eq_attr "type" "veccomplex")
167       (eq_attr "cpu" "ppc7450"))
168  "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
169
170(define_insn_reservation "ppc7450-veccmp" 2
171  (and (eq_attr "type" "veccmp")
172       (eq_attr "cpu" "ppc7450"))
173  "ppc7450_du,ppc7450_vec_du,veccmplx_7450")
174
175(define_insn_reservation "ppc7450-vecfloat" 4
176  (and (eq_attr "type" "vecfloat")
177       (eq_attr "cpu" "ppc7450"))
178  "ppc7450_du,ppc7450_vec_du,vecflt_7450")
179
180(define_insn_reservation "ppc7450-vecperm" 2
181  (and (eq_attr "type" "vecperm")
182       (eq_attr "cpu" "ppc7450"))
183  "ppc7450_du,ppc7450_vec_du,vecperm_7450")
184
185