1;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620,
2;; and PowerPC 630 processors.
3;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
4;;
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 2, or (at your
10;; option) any later version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING.  If not, write to the
19;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20;; MA 02110-1301, USA.
21
22(define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2")
23(define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx")
24(define_cpu_unit "fpu_6xx" "ppc6xxfp")
25(define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2")
26(define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx")
27
28;; PPC604  32-bit 2xSCIU, MCIU, LSU, FPU, BPU
29;; PPC604e  32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
30;; MCIU used for imul/idiv and moves from/to spr
31;; LSU 2 stage pipelined
32;; FPU 3 stage pipelined
33;; Max issue 4 insns/clock cycle
34
35;; PPC604e is PPC604 with larger caches and a CRU.  In the 604
36;; the CR logical operations are handled in the BPU.
37;; In the 604e, the CRU shares bus with BPU so only one condition
38;; register or branch insn can be issued per clock.  Not modelled.
39
40;; PPC620  64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
41;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
42;; Max issue 4 insns/clock cycle
43;; Out-of-order execution, in-order completion
44
45;; No following instruction can dispatch in the same cycle as a branch
46;; instruction.  Not modelled.  This is no problem if RCSP is not
47;; enabled since the scheduler stops a schedule when it gets to a branch.
48
49;; Four insns can be dispatched per cycle.
50
51(define_insn_reservation "ppc604-load" 2
52  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
53       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
54  "lsu_6xx")
55
56(define_insn_reservation "ppc604-fpload" 3
57  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
58       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
59  "lsu_6xx")
60
61(define_insn_reservation "ppc604-store" 3
62  (and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
63       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
64  "lsu_6xx")
65
66(define_insn_reservation "ppc604-llsc" 3
67  (and (eq_attr "type" "load_l,store_c")
68       (eq_attr "cpu" "ppc604,ppc604e"))
69  "lsu_6xx")
70  
71(define_insn_reservation "ppc630-llsc" 4
72  (and (eq_attr "type" "load_l,store_c")
73       (eq_attr "cpu" "ppc620,ppc630"))
74  "lsu_6xx")
75  
76(define_insn_reservation "ppc604-integer" 1
77  (and (eq_attr "type" "integer,insert_word")
78       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
79  "iu1_6xx|iu2_6xx")
80
81(define_insn_reservation "ppc604-two" 1
82  (and (eq_attr "type" "two")
83       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
84  "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
85
86(define_insn_reservation "ppc604-three" 1
87  (and (eq_attr "type" "three")
88       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
89  "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
90
91(define_insn_reservation "ppc604-imul" 4
92  (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
93       (eq_attr "cpu" "ppc604"))
94  "mciu_6xx*2")
95
96(define_insn_reservation "ppc604e-imul" 2
97  (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
98       (eq_attr "cpu" "ppc604e"))
99  "mciu_6xx")
100
101(define_insn_reservation "ppc620-imul" 5
102  (and (eq_attr "type" "imul,imul_compare")
103       (eq_attr "cpu" "ppc620,ppc630"))
104  "mciu_6xx*3")
105
106(define_insn_reservation "ppc620-imul2" 4
107  (and (eq_attr "type" "imul2")
108       (eq_attr "cpu" "ppc620,ppc630"))
109  "mciu_6xx*3")
110
111(define_insn_reservation "ppc620-imul3" 3
112  (and (eq_attr "type" "imul3")
113       (eq_attr "cpu" "ppc620,ppc630"))
114  "mciu_6xx*3")
115
116(define_insn_reservation "ppc620-lmul" 7
117  (and (eq_attr "type" "lmul,lmul_compare")
118       (eq_attr "cpu" "ppc620,ppc630"))
119  "mciu_6xx*5")
120
121(define_insn_reservation "ppc604-idiv" 20
122  (and (eq_attr "type" "idiv")
123       (eq_attr "cpu" "ppc604,ppc604e"))
124  "mciu_6xx*19")
125
126(define_insn_reservation "ppc620-idiv" 37
127  (and (eq_attr "type" "idiv")
128       (eq_attr "cpu" "ppc620"))
129  "mciu_6xx*36")
130
131(define_insn_reservation "ppc630-idiv" 21
132  (and (eq_attr "type" "idiv")
133       (eq_attr "cpu" "ppc630"))
134  "mciu_6xx*20")
135
136(define_insn_reservation "ppc620-ldiv" 37
137  (and (eq_attr "type" "ldiv")
138       (eq_attr "cpu" "ppc620,ppc630"))
139  "mciu_6xx*36")
140
141(define_insn_reservation "ppc604-compare" 3
142  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
143       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
144  "(iu1_6xx|iu2_6xx)")
145
146; FPU PPC604{,e},PPC620
147(define_insn_reservation "ppc604-fpcompare" 5
148  (and (eq_attr "type" "fpcompare")
149       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
150  "fpu_6xx")
151
152(define_insn_reservation "ppc604-fp" 3
153  (and (eq_attr "type" "fp")
154       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
155  "fpu_6xx")
156
157(define_insn_reservation "ppc604-dmul" 3
158  (and (eq_attr "type" "dmul")
159       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
160  "fpu_6xx")
161
162; Divides are not pipelined
163(define_insn_reservation "ppc604-sdiv" 18
164  (and (eq_attr "type" "sdiv")
165       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
166  "fpu_6xx*18")
167
168(define_insn_reservation "ppc604-ddiv" 32
169  (and (eq_attr "type" "ddiv")
170       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
171  "fpu_6xx*32")
172
173(define_insn_reservation "ppc620-ssqrt" 31
174  (and (eq_attr "type" "ssqrt")
175       (eq_attr "cpu" "ppc620"))
176  "fpu_6xx*31")
177
178(define_insn_reservation "ppc620-dsqrt" 31
179  (and (eq_attr "type" "dsqrt")
180       (eq_attr "cpu" "ppc620"))
181  "fpu_6xx*31")
182
183
184; 2xFPU PPC630
185(define_insn_reservation "ppc630-fpcompare" 5
186  (and (eq_attr "type" "fpcompare")
187       (eq_attr "cpu" "ppc630"))
188  "fpu1_6xx|fpu2_6xx")
189
190(define_insn_reservation "ppc630-fp" 3
191  (and (eq_attr "type" "fp,dmul")
192       (eq_attr "cpu" "ppc630"))
193  "fpu1_6xx|fpu2_6xx")
194
195(define_insn_reservation "ppc630-sdiv" 17
196  (and (eq_attr "type" "sdiv")
197       (eq_attr "cpu" "ppc630"))
198  "fpu1_6xx*17|fpu2_6xx*17")
199
200(define_insn_reservation "ppc630-ddiv" 21
201  (and (eq_attr "type" "ddiv")
202       (eq_attr "cpu" "ppc630"))
203  "fpu1_6xx*21|fpu2_6xx*21")
204
205(define_insn_reservation "ppc630-ssqrt" 18
206  (and (eq_attr "type" "ssqrt")
207       (eq_attr "cpu" "ppc630"))
208  "fpu1_6xx*18|fpu2_6xx*18")
209
210(define_insn_reservation "ppc630-dsqrt" 25
211  (and (eq_attr "type" "dsqrt")
212       (eq_attr "cpu" "ppc630"))
213  "fpu1_6xx*25|fpu2_6xx*25")
214
215(define_insn_reservation "ppc604-mfcr" 3
216  (and (eq_attr "type" "mfcr")
217       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
218  "mciu_6xx")
219
220(define_insn_reservation "ppc604-mtcr" 2
221  (and (eq_attr "type" "mtcr")
222       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
223  "iu1_6xx|iu2_6xx")
224
225(define_insn_reservation "ppc604-crlogical" 2
226  (and (eq_attr "type" "cr_logical,delayed_cr")
227       (eq_attr "cpu" "ppc604"))
228  "bpu_6xx")
229
230(define_insn_reservation "ppc604e-crlogical" 2
231  (and (eq_attr "type" "cr_logical,delayed_cr")
232       (eq_attr "cpu" "ppc604e,ppc620,ppc630"))
233  "cru_6xx")
234
235(define_insn_reservation "ppc604-mtjmpr" 2
236  (and (eq_attr "type" "mtjmpr")
237       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
238  "mciu_6xx")
239
240(define_insn_reservation "ppc604-mfjmpr" 3
241  (and (eq_attr "type" "mfjmpr")
242       (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
243  "mciu_6xx")
244
245(define_insn_reservation "ppc630-mfjmpr" 2
246  (and (eq_attr "type" "mfjmpr")
247       (eq_attr "cpu" "ppc630"))
248  "mciu_6xx")
249
250(define_insn_reservation "ppc604-jmpreg" 1
251  (and (eq_attr "type" "jmpreg,branch")
252       (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
253  "bpu_6xx")
254
255(define_insn_reservation "ppc604-isync" 0
256  (and (eq_attr "type" "isync")
257       (eq_attr "cpu" "ppc604,ppc604e"))
258  "bpu_6xx")
259  
260(define_insn_reservation "ppc630-isync" 6
261  (and (eq_attr "type" "isync")
262       (eq_attr "cpu" "ppc620,ppc630"))
263  "bpu_6xx")
264  
265(define_insn_reservation "ppc604-sync" 35
266  (and (eq_attr "type" "sync")
267       (eq_attr "cpu" "ppc604,ppc604e"))
268  "lsu_6xx")
269  
270(define_insn_reservation "ppc630-sync" 26
271  (and (eq_attr "type" "sync")
272       (eq_attr "cpu" "ppc620,ppc630"))
273  "lsu_6xx")
274  
275