1;; Scheduling description for PowerPC 603 processor. 2;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 2, or (at your 9;; option) any later version. 10 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to the 18;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19;; MA 02110-1301, USA. 20 21(define_automaton "ppc603,ppc603fp") 22(define_cpu_unit "iu_603" "ppc603") 23(define_cpu_unit "fpu_603" "ppc603fp") 24(define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603") 25 26;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU 27;; Max issue 3 insns/clock cycle (includes 1 branch) 28 29;; Branches go straight to the BPU. All other insns are handled 30;; by a dispatch unit which can issue a max of 2 insns per cycle. 31 32;; The PPC603e user's manual recommends that to reduce branch mispredictions, 33;; the insn that sets CR bits should be separated from the branch insn 34;; that evaluates them; separation by more than 9 insns ensures that the CR 35;; bits will be immediately available for execution. 36;; This could be artificially achieved by exaggerating the latency of 37;; compare insns but at the expense of a poorer schedule. 38 39;; CR insns get executed in the SRU. Not modelled. 40 41(define_insn_reservation "ppc603-load" 2 42 (and (eq_attr "type" "load,load_ext,load_ux,load_u,load_l") 43 (eq_attr "cpu" "ppc603")) 44 "lsu_603") 45 46(define_insn_reservation "ppc603-store" 2 47 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") 48 (eq_attr "cpu" "ppc603")) 49 "lsu_603*2") 50 51(define_insn_reservation "ppc603-fpload" 2 52 (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 53 (eq_attr "cpu" "ppc603")) 54 "lsu_603") 55 56(define_insn_reservation "ppc603-storec" 8 57 (and (eq_attr "type" "store_c") 58 (eq_attr "cpu" "ppc603")) 59 "lsu_603") 60 61(define_insn_reservation "ppc603-integer" 1 62 (and (eq_attr "type" "integer,insert_word") 63 (eq_attr "cpu" "ppc603")) 64 "iu_603") 65 66(define_insn_reservation "ppc603-two" 1 67 (and (eq_attr "type" "two") 68 (eq_attr "cpu" "ppc603")) 69 "iu_603,iu_603") 70 71(define_insn_reservation "ppc603-three" 1 72 (and (eq_attr "type" "three") 73 (eq_attr "cpu" "ppc603")) 74 "iu_603,iu_603,iu_603") 75 76; This takes 2 or 3 cycles 77(define_insn_reservation "ppc603-imul" 3 78 (and (eq_attr "type" "imul,imul_compare") 79 (eq_attr "cpu" "ppc603")) 80 "iu_603*2") 81 82(define_insn_reservation "ppc603-imul2" 2 83 (and (eq_attr "type" "imul2,imul3") 84 (eq_attr "cpu" "ppc603")) 85 "iu_603*2") 86 87(define_insn_reservation "ppc603-idiv" 37 88 (and (eq_attr "type" "idiv") 89 (eq_attr "cpu" "ppc603")) 90 "iu_603*37") 91 92(define_insn_reservation "ppc603-compare" 3 93 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare") 94 (eq_attr "cpu" "ppc603")) 95 "iu_603,nothing,bpu_603") 96 97(define_insn_reservation "ppc603-fpcompare" 3 98 (and (eq_attr "type" "fpcompare") 99 (eq_attr "cpu" "ppc603")) 100 "(fpu_603+iu_603*2),bpu_603") 101 102(define_insn_reservation "ppc603-fp" 3 103 (and (eq_attr "type" "fp") 104 (eq_attr "cpu" "ppc603")) 105 "fpu_603") 106 107(define_insn_reservation "ppc603-dmul" 4 108 (and (eq_attr "type" "dmul") 109 (eq_attr "cpu" "ppc603")) 110 "fpu_603*2") 111 112; Divides are not pipelined 113(define_insn_reservation "ppc603-sdiv" 18 114 (and (eq_attr "type" "sdiv") 115 (eq_attr "cpu" "ppc603")) 116 "fpu_603*18") 117 118(define_insn_reservation "ppc603-ddiv" 33 119 (and (eq_attr "type" "ddiv") 120 (eq_attr "cpu" "ppc603")) 121 "fpu_603*33") 122 123(define_insn_reservation "ppc603-crlogical" 2 124 (and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr") 125 (eq_attr "cpu" "ppc603")) 126 "sru_603") 127 128(define_insn_reservation "ppc603-mtjmpr" 4 129 (and (eq_attr "type" "mtjmpr") 130 (eq_attr "cpu" "ppc603")) 131 "sru_603") 132 133(define_insn_reservation "ppc603-mfjmpr" 2 134 (and (eq_attr "type" "mfjmpr,isync,sync") 135 (eq_attr "cpu" "ppc603")) 136 "sru_603") 137 138(define_insn_reservation "ppc603-jmpreg" 1 139 (and (eq_attr "type" "jmpreg,branch") 140 (eq_attr "cpu" "ppc603")) 141 "bpu_603") 142 143