1;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors. 2;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 2, or (at your 9;; option) any later version. 10 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to the 18;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19;; MA 02110-1301, USA. 20 21(define_automaton "ppc40x,ppc40xiu") 22(define_cpu_unit "bpu_40x,fpu_405" "ppc40x") 23(define_cpu_unit "iu_40x" "ppc40xiu") 24 25;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU 26;; Embedded PowerPC controller 27;; In-order execution 28;; Max issue two insns/cycle (includes one branch) 29(define_insn_reservation "ppc403-load" 2 30 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ 31 load_l,store_c,sync") 32 (eq_attr "cpu" "ppc403,ppc405")) 33 "iu_40x") 34 35(define_insn_reservation "ppc403-store" 2 36 (and (eq_attr "type" "store,store_ux,store_u") 37 (eq_attr "cpu" "ppc403,ppc405")) 38 "iu_40x") 39 40(define_insn_reservation "ppc403-integer" 1 41 (and (eq_attr "type" "integer,insert_word") 42 (eq_attr "cpu" "ppc403,ppc405")) 43 "iu_40x") 44 45(define_insn_reservation "ppc403-two" 1 46 (and (eq_attr "type" "two") 47 (eq_attr "cpu" "ppc403,ppc405")) 48 "iu_40x,iu_40x") 49 50(define_insn_reservation "ppc403-three" 1 51 (and (eq_attr "type" "three") 52 (eq_attr "cpu" "ppc403,ppc405")) 53 "iu_40x,iu_40x,iu_40x") 54 55(define_insn_reservation "ppc403-compare" 3 56 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare") 57 (eq_attr "cpu" "ppc403,ppc405")) 58 "iu_40x,nothing,bpu_40x") 59 60(define_insn_reservation "ppc403-imul" 4 61 (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 62 (eq_attr "cpu" "ppc403")) 63 "iu_40x*4") 64 65(define_insn_reservation "ppc405-imul" 5 66 (and (eq_attr "type" "imul,imul_compare") 67 (eq_attr "cpu" "ppc405")) 68 "iu_40x*4") 69 70(define_insn_reservation "ppc405-imul2" 3 71 (and (eq_attr "type" "imul2") 72 (eq_attr "cpu" "ppc405")) 73 "iu_40x*2") 74 75(define_insn_reservation "ppc405-imul3" 2 76 (and (eq_attr "type" "imul3") 77 (eq_attr "cpu" "ppc405")) 78 "iu_40x") 79 80(define_insn_reservation "ppc403-idiv" 33 81 (and (eq_attr "type" "idiv") 82 (eq_attr "cpu" "ppc403,ppc405")) 83 "iu_40x*33") 84 85(define_insn_reservation "ppc403-mfcr" 2 86 (and (eq_attr "type" "mfcr") 87 (eq_attr "cpu" "ppc403,ppc405")) 88 "iu_40x") 89 90(define_insn_reservation "ppc403-mtcr" 3 91 (and (eq_attr "type" "mtcr") 92 (eq_attr "cpu" "ppc403,ppc405")) 93 "iu_40x") 94 95(define_insn_reservation "ppc403-mtjmpr" 4 96 (and (eq_attr "type" "mtjmpr") 97 (eq_attr "cpu" "ppc403,ppc405")) 98 "iu_40x") 99 100(define_insn_reservation "ppc403-mfjmpr" 2 101 (and (eq_attr "type" "mfjmpr") 102 (eq_attr "cpu" "ppc403,ppc405")) 103 "iu_40x") 104 105(define_insn_reservation "ppc403-jmpreg" 1 106 (and (eq_attr "type" "jmpreg,branch,isync") 107 (eq_attr "cpu" "ppc403,ppc405")) 108 "bpu_40x") 109 110(define_insn_reservation "ppc403-cr" 2 111 (and (eq_attr "type" "cr_logical,delayed_cr") 112 (eq_attr "cpu" "ppc403,ppc405")) 113 "bpu_40x") 114 115(define_insn_reservation "ppc405-float" 11 116 (and (eq_attr "type" "fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,\ 117 fpcompare,fp,dmul,sdiv,ddiv") 118 (eq_attr "cpu" "ppc405")) 119 "fpu_405*10") 120