sb1.md revision 169689
1282199Sdumbbell;; 2282199Sdumbbell;; DFA-based pipeline description for Broadcom SB-1 3282199Sdumbbell;; 4282199Sdumbbell 5282199Sdumbbell;; The Broadcom SB-1 core is 4-way superscalar, in-order. It has 2 load/store 6282199Sdumbbell;; pipes (one of which can support some ALU operations), 2 alu pipes, 2 FP 7282199Sdumbbell;; pipes, and 1 MDMX pipes. It can issue 2 ls insns and 2 exe/fpu/mdmx insns 8282199Sdumbbell;; each cycle. 9282199Sdumbbell 10235783Skib;; We model the 4-way issue by ordering unit choices. The possible choices are 11235783Skib;; {ex1,fp1}|{ex0,fp0}|ls1|ls0. Instructions issue to the first eligible unit 12235783Skib;; in the list in most cases. Non-indexed load/stores issue to ls0 first. 13235783Skib;; simple alu operations issue to ls1 if it is still available, and their 14235783Skib;; operands are ready (no co-issue with loads), otherwise to the first 15235783Skib;; available ex unit. 16235783Skib 17235783Skib;; When exceptions are enabled, can only issue FP insns to fp1. This is 18235783Skib;; to ensure that instructions complete in order. The -mfp-exceptions option 19235783Skib;; can be used to specify whether the system has FP exceptions enabled or not. 20235783Skib 21235783Skib;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe 22235783Skib;; insn can issue per cycle (fp1). 23235783Skib 24235783Skib;; The A1 MDMX pipe is separate from the FP pipes, but uses the same register 25235783Skib;; file. As a result, once an MDMX insn is issued, no FP insns can be issued 26235783Skib;; for 3 cycles. When an FP insn is issued, no MDMX insn can be issued for 27235783Skib;; 5 cycles. This is currently not handled because there is no MDMX insn 28235783Skib;; support as yet. 29235783Skib 30235783Skib;; 31235783Skib;; We use two automata. sb1_cpu_div is for the integer divides, which are 32235783Skib;; not pipelined. sb1_cpu is for everything else. 33235783Skib;; 34235783Skib(define_automaton "sb1_cpu, sb1_cpu_div") 35235783Skib 36235783Skib;; Load/store function units. 37235783Skib(define_cpu_unit "sb1_ls0" "sb1_cpu") 38235783Skib(define_cpu_unit "sb1_ls1" "sb1_cpu") 39282199Sdumbbell 40235783Skib;; CPU function units. 41282199Sdumbbell(define_cpu_unit "sb1_ex0" "sb1_cpu") 42282199Sdumbbell(define_cpu_unit "sb1_ex1" "sb1_cpu") 43282199Sdumbbell 44282199Sdumbbell;; The divide unit is not pipelined, and blocks hi/lo reads and writes. 45282199Sdumbbell(define_cpu_unit "sb1_div" "sb1_cpu_div") 46282199Sdumbbell;; DMULT block any multiply from issuing in the next cycle. 47282199Sdumbbell(define_cpu_unit "sb1_mul" "sb1_cpu") 48282199Sdumbbell 49282199Sdumbbell;; Floating-point units. 50282199Sdumbbell(define_cpu_unit "sb1_fp0" "sb1_cpu") 51282199Sdumbbell(define_cpu_unit "sb1_fp1" "sb1_cpu") 52282199Sdumbbell 53282199Sdumbbell;; Can only issue to one of the ex and fp pipes at a time. 54235783Skib(exclusion_set "sb1_ex0" "sb1_fp0") 55282199Sdumbbell(exclusion_set "sb1_ex1" "sb1_fp1") 56235783Skib 57235783Skib;; Define an SB-1 specific attribute to simplify some FP descriptions. 58282199Sdumbbell;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are 59235783Skib;; disabled. 60282199Sdumbbell 61282199Sdumbbell(define_attr "sb1_fp_pipes" "one,two" 62235783Skib (cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0)) 63235783Skib (eq (symbol_ref "TARGET_FP_EXCEPTIONS") (const_int 0))) 64235783Skib (const_string "two")] 65235783Skib (const_string "one"))) 66235783Skib 67235783Skib;; Define reservations for common combinations. 68235783Skib 69235783Skib;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats, 70235783Skib;; effectively re-issuing the operation every 4 cycles. This means that we 71235783Skib;; can have at most 4 long-cycle operations per pipe. 72235783Skib 73235783Skib;; ??? The fdiv operations should be e.g. 74235783Skib;; sb1_fp1_4cycles*7" | "sb1_fp0_4cycle*7 75282199Sdumbbell;; but the DFA is too large when we do that. Perhaps have to use scheduler 76282199Sdumbbell;; hooks here. 77235783Skib 78235783Skib;; ??? Try limiting scheduler to 2 long latency operations, and see if this 79235783Skib;; results in a usable DFA, and whether it helps code performance. 80282199Sdumbbell 81235783Skib;;(define_reservation "sb1_fp0_4cycles" "sb1_fp0, nothing*3") 82235783Skib;;(define_reservation "sb1_fp1_4cycles" "sb1_fp1, nothing*3") 83282199Sdumbbell 84282199Sdumbbell;; 85235783Skib;; The ordering of the instruction-execution-path/resource-usage 86235783Skib;; descriptions (also known as reservation RTL) is roughly ordered 87235783Skib;; based on the define attribute RTL for the "type" classification. 88235783Skib;; When modifying, remember that the first test that matches is the 89235783Skib;; reservation used! 90282199Sdumbbell;; 91282199Sdumbbell 92282199Sdumbbell(define_insn_reservation "ir_sb1_unknown" 1 93282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 94282199Sdumbbell (eq_attr "type" "unknown,multi")) 95282199Sdumbbell "sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1") 96282199Sdumbbell 97282199Sdumbbell;; predicted taken branch causes 2 cycle ifetch bubble. predicted not 98282199Sdumbbell;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8 99282199Sdumbbell;; cycle ifetch bubble. We assume all branches predicted not taken. 100235783Skib 101235783Skib;; ??? This assumption that branches are predicated not taken should be 102235783Skib;; investigated. Maybe using 2 here will give better results. 103282199Sdumbbell 104282199Sdumbbell(define_insn_reservation "ir_sb1_branch" 0 105282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 106282199Sdumbbell (eq_attr "type" "branch,jump,call")) 107282199Sdumbbell "sb1_ex0") 108235783Skib 109282199Sdumbbell;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data 110235783Skib;; register as destination. 111235783Skib 112235783Skib;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on 113235783Skib;; an EX unit. Can not co-issue if the dependent insn executes on an LS unit. 114282199Sdumbbell;; SB-1A can always co-issue here. 115282199Sdumbbell 116282199Sdumbbell;; A load normally has a latency of zero cycles. In some cases, dependent 117282199Sdumbbell;; insns can be issued in the same cycle. However, a value of 1 gives 118282199Sdumbbell;; better performance in empirical testing. 119282199Sdumbbell 120282199Sdumbbell(define_insn_reservation "ir_sb1_load" 1 121282199Sdumbbell (and (eq_attr "cpu" "sb1") 122282199Sdumbbell (eq_attr "type" "load,prefetch")) 123282199Sdumbbell "sb1_ls0 | sb1_ls1") 124282199Sdumbbell 125282199Sdumbbell(define_insn_reservation "ir_sb1a_load" 0 126282199Sdumbbell (and (eq_attr "cpu" "sb1a") 127282199Sdumbbell (eq_attr "type" "load,prefetch")) 128282199Sdumbbell "sb1_ls0 | sb1_ls1") 129235783Skib 130235783Skib;; Can not co-issue fpload with fp exe when in 32-bit mode. 131282199Sdumbbell 132235783Skib(define_insn_reservation "ir_sb1_fpload" 0 133235783Skib (and (eq_attr "cpu" "sb1,sb1a") 134282199Sdumbbell (and (eq_attr "type" "fpload") 135282199Sdumbbell (ne (symbol_ref "TARGET_FLOAT64") 136282199Sdumbbell (const_int 0)))) 137282199Sdumbbell "sb1_ls0 | sb1_ls1") 138282199Sdumbbell 139282199Sdumbbell(define_insn_reservation "ir_sb1_fpload_32bitfp" 1 140282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 141282199Sdumbbell (and (eq_attr "type" "fpload") 142235783Skib (eq (symbol_ref "TARGET_FLOAT64") 143235783Skib (const_int 0)))) 144235783Skib "sb1_ls0 | sb1_ls1") 145282199Sdumbbell 146282199Sdumbbell;; Indexed loads can only execute on LS1 pipe. 147235783Skib 148235783Skib(define_insn_reservation "ir_sb1_fpidxload" 0 149235783Skib (and (eq_attr "cpu" "sb1,sb1a") 150282199Sdumbbell (and (eq_attr "type" "fpidxload") 151235783Skib (ne (symbol_ref "TARGET_FLOAT64") 152282199Sdumbbell (const_int 0)))) 153282199Sdumbbell "sb1_ls1") 154235783Skib 155282199Sdumbbell(define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1 156282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 157235783Skib (and (eq_attr "type" "fpidxload") 158282199Sdumbbell (eq (symbol_ref "TARGET_FLOAT64") 159282199Sdumbbell (const_int 0)))) 160282199Sdumbbell "sb1_ls1") 161282199Sdumbbell 162282199Sdumbbell;; prefx can only execute on the ls1 pipe. 163282199Sdumbbell 164282199Sdumbbell(define_insn_reservation "ir_sb1_prefetchx" 0 165282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 166282199Sdumbbell (eq_attr "type" "prefetchx")) 167282199Sdumbbell "sb1_ls1") 168282199Sdumbbell 169282199Sdumbbell;; ??? There is a 4.5 cycle latency if a store is followed by a load, and 170235783Skib;; there is a RAW dependency. 171282199Sdumbbell 172282199Sdumbbell(define_insn_reservation "ir_sb1_store" 1 173282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 174282199Sdumbbell (eq_attr "type" "store")) 175235783Skib "sb1_ls0+sb1_ex1 | sb1_ls0+sb1_ex0 | sb1_ls1+sb1_ex1 | sb1_ls1+sb1_ex0") 176235783Skib 177235783Skib(define_insn_reservation "ir_sb1_fpstore" 1 178235783Skib (and (eq_attr "cpu" "sb1,sb1a") 179282199Sdumbbell (eq_attr "type" "fpstore")) 180282199Sdumbbell "sb1_ls0+sb1_fp1 | sb1_ls0+sb1_fp0 | sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0") 181235783Skib 182235783Skib;; Indexed stores can only execute on LS1 pipe. 183235783Skib 184282199Sdumbbell(define_insn_reservation "ir_sb1_fpidxstore" 1 185235783Skib (and (eq_attr "cpu" "sb1,sb1a") 186282199Sdumbbell (eq_attr "type" "fpidxstore")) 187235783Skib "sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0") 188235783Skib 189282199Sdumbbell;; Load latencies are 3 cycles for one load to another load or store (address 190282199Sdumbbell;; only). This is 0 cycles for one load to a store using it as the data 191282199Sdumbbell;; written. 192282199Sdumbbell 193282199Sdumbbell;; This assumes that if a load is dependent on a previous insn, then it must 194282199Sdumbbell;; be an address dependence. 195282199Sdumbbell 196282199Sdumbbell(define_bypass 3 197282199Sdumbbell "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 198282199Sdumbbell ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp" 199282199Sdumbbell "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 200282199Sdumbbell ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 201235783Skib 202235783Skib(define_bypass 3 203282199Sdumbbell "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 204282199Sdumbbell ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp" 205282199Sdumbbell "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 206282199Sdumbbell "mips_store_data_bypass_p") 207235783Skib 208235783Skib;; On SB-1, simple alu instructions can execute on the LS1 unit. 209235783Skib 210282199Sdumbbell;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX 211282199Sdumbbell;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to 212282199Sdumbbell;; another LS insn (excluding store data). A simple alu insn issued on an EX 213235783Skib;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding 214282199Sdumbbell;; store data), otherwise a latency of 1 cycle. 215235783Skib 216235783Skib;; ??? We cannot handle latencies properly for simple alu instructions 217282199Sdumbbell;; within the DFA pipeline model. Latencies can be defined only from one 218282199Sdumbbell;; insn reservation to another. We can't make them depend on which function 219235783Skib;; unit was used. This isn't a DFA flaw. There is a conflict here, as we 220282199Sdumbbell;; need to know the latency before we can determine which unit will be 221235783Skib;; available, but we need to know which unit it is issued to before we can 222235783Skib;; compute the latency. Perhaps this can be handled via scheduler hooks. 223282199Sdumbbell;; This needs to be investigated. 224282199Sdumbbell 225282199Sdumbbell;; ??? Optimal scheduling taking the LS units into account seems to require 226282199Sdumbbell;; a pre-scheduling pass. We need to determine which instructions feed results 227282199Sdumbbell;; into store/load addresses, and thus benefit most from being issued to the 228235783Skib;; LS unit. Also, we need to prune the list to ensure we don't overschedule 229282199Sdumbbell;; insns to the LS unit, and that we don't conflict with insns that need LS1 230235783Skib;; such as indexed loads. We then need to emit nops to ensure that simple 231282199Sdumbbell;; alu instructions that are not supposed to be scheduled to LS1 don't 232282199Sdumbbell;; accidentally end up there because LS1 is free when they are issued. This 233282199Sdumbbell;; will be a lot of work, and it isn't clear how useful it will be. 234235783Skib 235235783Skib;; Empirical testing shows that 2 gives the best result. 236282199Sdumbbell 237235783Skib(define_insn_reservation "ir_sb1_simple_alu" 2 238282199Sdumbbell (and (eq_attr "cpu" "sb1") 239235783Skib (eq_attr "type" "const,arith")) 240235783Skib "sb1_ls1 | sb1_ex1 | sb1_ex0") 241235783Skib 242282199Sdumbbell;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we 243235783Skib;; have none of the above problems. 244282199Sdumbbell 245235783Skib(define_insn_reservation "ir_sb1a_simple_alu" 1 246235783Skib (and (eq_attr "cpu" "sb1a") 247282199Sdumbbell (eq_attr "type" "const,arith")) 248282199Sdumbbell "sb1_ex1 | sb1_ex0") 249282199Sdumbbell 250282199Sdumbbell;; ??? condmove also includes some FP instructions that execute on the FP 251282199Sdumbbell;; units. This needs to be clarified. 252282199Sdumbbell 253282199Sdumbbell(define_insn_reservation "ir_sb1_alu" 1 254282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 255282199Sdumbbell (eq_attr "type" "condmove,nop,shift")) 256282199Sdumbbell "sb1_ex1 | sb1_ex0") 257282199Sdumbbell 258235783Skib;; These are type arith/darith that only execute on the EX0 unit. 259282199Sdumbbell 260235783Skib(define_insn_reservation "ir_sb1_alu_0" 1 261282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 262282199Sdumbbell (eq_attr "type" "slt,clz,trap")) 263282199Sdumbbell "sb1_ex0") 264235783Skib 265235783Skib;; An alu insn issued on an EX unit has a latency of 5 cycles when the 266235783Skib;; result goes to a LS unit (excluding store data). 267235783Skib 268282199Sdumbbell;; This assumes that if a load is dependent on a previous insn, then it must 269282199Sdumbbell;; be an address dependence. 270282199Sdumbbell 271282199Sdumbbell(define_bypass 5 272282199Sdumbbell "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" 273282199Sdumbbell "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 274282199Sdumbbell ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 275282199Sdumbbell 276282199Sdumbbell(define_bypass 5 277282199Sdumbbell "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" 278282199Sdumbbell "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 279282199Sdumbbell "mips_store_data_bypass_p") 280235783Skib 281235783Skib;; mf{hi,lo} is 1 cycle. 282282199Sdumbbell 283282199Sdumbbell(define_insn_reservation "ir_sb1_mfhi" 1 284235783Skib (and (eq_attr "cpu" "sb1,sb1a") 285235783Skib (and (eq_attr "type" "mfhilo") 286282199Sdumbbell (not (match_operand 1 "lo_operand")))) 287282199Sdumbbell "sb1_ex1") 288282199Sdumbbell 289282199Sdumbbell(define_insn_reservation "ir_sb1_mflo" 1 290282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 291282199Sdumbbell (and (eq_attr "type" "mfhilo") 292282199Sdumbbell (match_operand 1 "lo_operand"))) 293235783Skib "sb1_ex1") 294282199Sdumbbell 295235783Skib;; mt{hi,lo} to mul/div is 4 cycles. 296282199Sdumbbell 297235783Skib(define_insn_reservation "ir_sb1_mthilo" 4 298282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 299235783Skib (eq_attr "type" "mthilo")) 300235783Skib "sb1_ex1") 301235783Skib 302282199Sdumbbell;; mt{hi,lo} to mf{hi,lo} is 3 cycles. 303235783Skib 304282199Sdumbbell(define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo") 305235783Skib 306235783Skib;; multiply latency to an EX operation is 3 cycles. 307282199Sdumbbell 308282199Sdumbbell;; ??? Should check whether we need to make multiply conflict with moves 309282199Sdumbbell;; to/from hilo registers. 310282199Sdumbbell 311282199Sdumbbell(define_insn_reservation "ir_sb1_mulsi" 3 312282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 313282199Sdumbbell (and (eq_attr "type" "imul,imul3,imadd") 314282199Sdumbbell (eq_attr "mode" "SI"))) 315282199Sdumbbell "sb1_ex1+sb1_mul") 316282199Sdumbbell 317282199Sdumbbell;; muldi to mfhi is 4 cycles. 318282199Sdumbbell;; Blocks any other multiply insn issue for 1 cycle. 319282199Sdumbbell 320235783Skib(define_insn_reservation "ir_sb1_muldi" 4 321235783Skib (and (eq_attr "cpu" "sb1,sb1a") 322282199Sdumbbell (and (eq_attr "type" "imul,imul3") 323282199Sdumbbell (eq_attr "mode" "DI"))) 324282199Sdumbbell "sb1_ex1+sb1_mul, sb1_mul") 325282199Sdumbbell 326235783Skib;; muldi to mflo is 3 cycles. 327282199Sdumbbell 328282199Sdumbbell(define_bypass 3 "ir_sb1_muldi" "ir_sb1_mflo") 329282199Sdumbbell 330282199Sdumbbell;; mul latency is 7 cycles if the result is used by any LS insn. 331282199Sdumbbell 332235783Skib;; This assumes that if a load is dependent on a previous insn, then it must 333282199Sdumbbell;; be an address dependence. 334282199Sdumbbell 335282199Sdumbbell(define_bypass 7 336282199Sdumbbell "ir_sb1_mulsi,ir_sb1_muldi" 337282199Sdumbbell "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 338282199Sdumbbell ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 339282199Sdumbbell 340282199Sdumbbell(define_bypass 7 341235783Skib "ir_sb1_mulsi,ir_sb1_muldi" 342235783Skib "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 343235783Skib "mips_store_data_bypass_p") 344235783Skib 345235783Skib;; The divide unit is not pipelined. Divide busy is asserted in the 4th 346282199Sdumbbell;; cycle, and then deasserted on the latency cycle. So only one divide at 347235783Skib;; a time, but the first/last 4 cycles can overlap. 348282199Sdumbbell 349235783Skib;; ??? All divides block writes to hi/lo regs. hi/lo regs are written 4 cycles 350235783Skib;; after the latency cycle for divides (e.g. 40/72). dmult writes lo in 351282199Sdumbbell;; cycle 7, and hi in cycle 8. All other insns write hi/lo regs in cycle 7. 352282199Sdumbbell;; Default for output dependencies is the difference in latencies, which is 353282199Sdumbbell;; only 1 cycle off here, e.g. div to mtlo stalls for 32 cycles, but should 354282199Sdumbbell;; stall for 33 cycles. This does not seem significant enough to worry about. 355282199Sdumbbell 356282199Sdumbbell(define_insn_reservation "ir_sb1_divsi" 36 357282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 358282199Sdumbbell (and (eq_attr "type" "idiv") 359282199Sdumbbell (eq_attr "mode" "SI"))) 360282199Sdumbbell "sb1_ex1, nothing*3, sb1_div*32") 361282199Sdumbbell 362282199Sdumbbell(define_insn_reservation "ir_sb1_divdi" 68 363282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 364282199Sdumbbell (and (eq_attr "type" "idiv") 365235783Skib (eq_attr "mode" "DI"))) 366235783Skib "sb1_ex1, nothing*3, sb1_div*64") 367282199Sdumbbell 368282199Sdumbbell(define_insn_reservation "ir_sb1_fpu_2pipes" 4 369235783Skib (and (eq_attr "cpu" "sb1,sb1a") 370282199Sdumbbell (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1") 371282199Sdumbbell (eq_attr "sb1_fp_pipes" "two"))) 372282199Sdumbbell "sb1_fp1 | sb1_fp0") 373282199Sdumbbell 374282199Sdumbbell(define_insn_reservation "ir_sb1_fpu_1pipe" 4 375235783Skib (and (eq_attr "cpu" "sb1,sb1a") 376282199Sdumbbell (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1") 377235783Skib (eq_attr "sb1_fp_pipes" "one"))) 378282199Sdumbbell "sb1_fp1") 379235783Skib 380235783Skib(define_insn_reservation "ir_sb1_fpu_step2_2pipes" 8 381235783Skib (and (eq_attr "cpu" "sb1,sb1a") 382282199Sdumbbell (and (eq_attr "type" "frdiv2,frsqrt2") 383235783Skib (eq_attr "sb1_fp_pipes" "two"))) 384282199Sdumbbell "sb1_fp1 | sb1_fp0") 385282199Sdumbbell 386235783Skib(define_insn_reservation "ir_sb1_fpu_step2_1pipe" 8 387235783Skib (and (eq_attr "cpu" "sb1,sb1a") 388235783Skib (and (eq_attr "type" "frdiv2,frsqrt2") 389282199Sdumbbell (eq_attr "sb1_fp_pipes" "one"))) 390235783Skib "sb1_fp1") 391282199Sdumbbell 392235783Skib;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency 393235783Skib;; otherwise. 394282199Sdumbbell 395282199Sdumbbell;; ??? Blocks issue of another non-madd/msub after 4 cycles. 396282199Sdumbbell 397282199Sdumbbell(define_insn_reservation "ir_sb1_fmadd_2pipes" 8 398282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 399282199Sdumbbell (and (eq_attr "type" "fmadd") 400282199Sdumbbell (eq_attr "sb1_fp_pipes" "two"))) 401282199Sdumbbell "sb1_fp1 | sb1_fp0") 402282199Sdumbbell 403282199Sdumbbell(define_insn_reservation "ir_sb1_fmadd_1pipe" 8 404235783Skib (and (eq_attr "cpu" "sb1,sb1a") 405282199Sdumbbell (and (eq_attr "type" "fmadd") 406235783Skib (eq_attr "sb1_fp_pipes" "one"))) 407282199Sdumbbell "sb1_fp1") 408282199Sdumbbell 409282199Sdumbbell(define_insn_reservation "ir_sb1_fcmp" 4 410282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 411282199Sdumbbell (eq_attr "type" "fcmp")) 412282199Sdumbbell "sb1_fp1") 413282199Sdumbbell 414282199Sdumbbell;; mtc1 latency 5 cycles. 415282199Sdumbbell 416235783Skib(define_insn_reservation "ir_sb1_mtxfer" 5 417282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 418282199Sdumbbell (and (eq_attr "type" "xfer") 419282199Sdumbbell (match_operand 0 "fpr_operand"))) 420235783Skib "sb1_fp0") 421235783Skib 422235783Skib;; mfc1 latency 1 cycle. 423282199Sdumbbell 424282199Sdumbbell(define_insn_reservation "ir_sb1_mfxfer" 1 425282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 426282199Sdumbbell (and (eq_attr "type" "xfer") 427282199Sdumbbell (not (match_operand 0 "fpr_operand")))) 428282199Sdumbbell "sb1_fp0") 429282199Sdumbbell 430282199Sdumbbell;; ??? Can deliver at most 1 result per every 6 cycles because of issue 431282199Sdumbbell;; restrictions. 432282199Sdumbbell 433282199Sdumbbell(define_insn_reservation "ir_sb1_divsf_2pipes" 24 434282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 435282199Sdumbbell (and (eq_attr "type" "fdiv") 436282199Sdumbbell (and (eq_attr "mode" "SF") 437235783Skib (eq_attr "sb1_fp_pipes" "two")))) 438282199Sdumbbell "sb1_fp1 | sb1_fp0") 439282199Sdumbbell 440235783Skib(define_insn_reservation "ir_sb1_divsf_1pipe" 24 441282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 442282199Sdumbbell (and (eq_attr "type" "fdiv") 443282199Sdumbbell (and (eq_attr "mode" "SF") 444282199Sdumbbell (eq_attr "sb1_fp_pipes" "one")))) 445282199Sdumbbell "sb1_fp1") 446282199Sdumbbell 447282199Sdumbbell;; ??? Can deliver at most 1 result per every 8 cycles because of issue 448235783Skib;; restrictions. 449282199Sdumbbell 450235783Skib(define_insn_reservation "ir_sb1_divdf_2pipes" 32 451282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 452282199Sdumbbell (and (eq_attr "type" "fdiv") 453282199Sdumbbell (and (eq_attr "mode" "DF") 454235783Skib (eq_attr "sb1_fp_pipes" "two")))) 455282199Sdumbbell "sb1_fp1 | sb1_fp0") 456282199Sdumbbell 457282199Sdumbbell(define_insn_reservation "ir_sb1_divdf_1pipe" 32 458282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 459282199Sdumbbell (and (eq_attr "type" "fdiv") 460282199Sdumbbell (and (eq_attr "mode" "DF") 461282199Sdumbbell (eq_attr "sb1_fp_pipes" "one")))) 462235783Skib "sb1_fp1") 463282199Sdumbbell 464235783Skib;; ??? Can deliver at most 1 result per every 3 cycles because of issue 465282199Sdumbbell;; restrictions. 466282199Sdumbbell 467235783Skib(define_insn_reservation "ir_sb1_recipsf_2pipes" 12 468282199Sdumbbell (and (eq_attr "cpu" "sb1,sb1a") 469 (and (eq_attr "type" "frdiv") 470 (and (eq_attr "mode" "SF") 471 (eq_attr "sb1_fp_pipes" "two")))) 472 "sb1_fp1 | sb1_fp0") 473 474(define_insn_reservation "ir_sb1_recipsf_1pipe" 12 475 (and (eq_attr "cpu" "sb1,sb1a") 476 (and (eq_attr "type" "frdiv") 477 (and (eq_attr "mode" "SF") 478 (eq_attr "sb1_fp_pipes" "one")))) 479 "sb1_fp1") 480 481;; ??? Can deliver at most 1 result per every 5 cycles because of issue 482;; restrictions. 483 484(define_insn_reservation "ir_sb1_recipdf_2pipes" 20 485 (and (eq_attr "cpu" "sb1,sb1a") 486 (and (eq_attr "type" "frdiv") 487 (and (eq_attr "mode" "DF") 488 (eq_attr "sb1_fp_pipes" "two")))) 489 "sb1_fp1 | sb1_fp0") 490 491(define_insn_reservation "ir_sb1_recipdf_1pipe" 20 492 (and (eq_attr "cpu" "sb1,sb1a") 493 (and (eq_attr "type" "frdiv") 494 (and (eq_attr "mode" "DF") 495 (eq_attr "sb1_fp_pipes" "one")))) 496 "sb1_fp1") 497 498;; ??? Can deliver at most 1 result per every 7 cycles because of issue 499;; restrictions. 500 501(define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28 502 (and (eq_attr "cpu" "sb1,sb1a") 503 (and (eq_attr "type" "fsqrt") 504 (and (eq_attr "mode" "SF") 505 (eq_attr "sb1_fp_pipes" "two")))) 506 "sb1_fp1 | sb1_fp0") 507 508(define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28 509 (and (eq_attr "cpu" "sb1,sb1a") 510 (and (eq_attr "type" "fsqrt") 511 (and (eq_attr "mode" "SF") 512 (eq_attr "sb1_fp_pipes" "one")))) 513 "sb1_fp1") 514 515;; ??? Can deliver at most 1 result per every 10 cycles because of issue 516;; restrictions. 517 518(define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40 519 (and (eq_attr "cpu" "sb1,sb1a") 520 (and (eq_attr "type" "fsqrt") 521 (and (eq_attr "mode" "DF") 522 (eq_attr "sb1_fp_pipes" "two")))) 523 "sb1_fp1 | sb1_fp0") 524 525(define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40 526 (and (eq_attr "cpu" "sb1,sb1a") 527 (and (eq_attr "type" "fsqrt") 528 (and (eq_attr "mode" "DF") 529 (eq_attr "sb1_fp_pipes" "one")))) 530 "sb1_fp1") 531 532;; ??? Can deliver at most 1 result per every 4 cycles because of issue 533;; restrictions. 534 535(define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16 536 (and (eq_attr "cpu" "sb1,sb1a") 537 (and (eq_attr "type" "frsqrt") 538 (and (eq_attr "mode" "SF") 539 (eq_attr "sb1_fp_pipes" "two")))) 540 "sb1_fp1 | sb1_fp0") 541 542(define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16 543 (and (eq_attr "cpu" "sb1,sb1a") 544 (and (eq_attr "type" "frsqrt") 545 (and (eq_attr "mode" "SF") 546 (eq_attr "sb1_fp_pipes" "one")))) 547 "sb1_fp1") 548 549;; ??? Can deliver at most 1 result per every 7 cycles because of issue 550;; restrictions. 551 552(define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28 553 (and (eq_attr "cpu" "sb1,sb1a") 554 (and (eq_attr "type" "frsqrt") 555 (and (eq_attr "mode" "DF") 556 (eq_attr "sb1_fp_pipes" "two")))) 557 "sb1_fp1 | sb1_fp0") 558 559(define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28 560 (and (eq_attr "cpu" "sb1,sb1a") 561 (and (eq_attr "type" "frsqrt") 562 (and (eq_attr "mode" "DF") 563 (eq_attr "sb1_fp_pipes" "one")))) 564 "sb1_fp1") 565