mips-dsp.md revision 169689
1139823Simp(define_constants 221259Swollman [(CCDSP_PO_REGNUM 182) 321259Swollman (CCDSP_SC_REGNUM 183) 421259Swollman (CCDSP_CA_REGNUM 184) 521259Swollman (CCDSP_OU_REGNUM 185) 621259Swollman (CCDSP_CC_REGNUM 186) 721259Swollman (CCDSP_EF_REGNUM 187)]) 821259Swollman 921259Swollman;; This mode macro allows si, v2hi, v4qi for all possible modes in DSP ASE. 1021259Swollman(define_mode_macro DSP [(SI "TARGET_DSP") 1121259Swollman (V2HI "TARGET_DSP") 1221259Swollman (V4QI "TARGET_DSP")]) 1321259Swollman 1421259Swollman;; This mode macro allows v2hi, v4qi for vector/SIMD data. 1521259Swollman(define_mode_macro DSPV [(V2HI "TARGET_DSP") 1621259Swollman (V4QI "TARGET_DSP")]) 1721259Swollman 1821259Swollman;; This mode macro allows si, v2hi for Q31 and V2Q15 fixed-point data. 1921259Swollman(define_mode_macro DSPQ [(SI "TARGET_DSP") 2021259Swollman (V2HI "TARGET_DSP")]) 2121259Swollman 2221259Swollman;; DSP instructions use q for fixed-point data, and u for integer in the infix. 2321259Swollman(define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")]) 2421259Swollman 2521259Swollman;; DSP instructions use nothing for fixed-point data, and u for integer in 2621259Swollman;; the infix. 2721259Swollman(define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")]) 2821259Swollman 2921259Swollman;; DSP instructions use w, ph, qb in the postfix. 3050477Speter(define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")]) 3121259Swollman 3221259Swollman;; DSP shift masks for SI, V2HI, V4QI. 3321259Swollman(define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")]) 3421259Swollman 3521259Swollman;; MIPS DSP ASE Revision 0.98 3/24/2005 3621259Swollman;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic 3721259Swollman;; ADDQ* 3821259Swollman(define_insn "add<DSPV:mode>3" 3921259Swollman [(parallel 4021259Swollman [(set (match_operand:DSPV 0 "register_operand" "=d") 4121259Swollman (plus:DSPV (match_operand:DSPV 1 "register_operand" "d") 4221259Swollman (match_operand:DSPV 2 "register_operand" "d"))) 4321259Swollman (set (reg:CCDSP CCDSP_OU_REGNUM) 4421259Swollman (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])] 4521259Swollman "" 4621259Swollman "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 4721259Swollman [(set_attr "type" "arith") 4821259Swollman (set_attr "mode" "SI")]) 4921259Swollman 5021259Swollman(define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>" 51108533Sschweikh [(parallel 5221259Swollman [(set (match_operand:DSP 0 "register_operand" "=d") 5321259Swollman (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 5421259Swollman (match_operand:DSP 2 "register_operand" "d")] 5521259Swollman UNSPEC_ADDQ_S)) 56108533Sschweikh (set (reg:CCDSP CCDSP_OU_REGNUM) 5721259Swollman (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] 5821259Swollman "" 5921259Swollman "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 6021259Swollman [(set_attr "type" "arith") 6121259Swollman (set_attr "mode" "SI")]) 6221259Swollman 6321259Swollman;; SUBQ* 6421259Swollman(define_insn "sub<DSPV:mode>3" 6521259Swollman [(parallel 6683366Sjulian [(set (match_operand:DSPV 0 "register_operand" "=d") 6721259Swollman (minus:DSPV (match_operand:DSPV 1 "register_operand" "d") 6885074Sru (match_operand:DSPV 2 "register_operand" "d"))) 6921259Swollman (set (reg:CCDSP CCDSP_OU_REGNUM) 7021259Swollman (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])] 71142215Sglebius "TARGET_DSP" 72155051Sglebius "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 7321259Swollman [(set_attr "type" "arith") 7421259Swollman (set_attr "mode" "SI")]) 7521259Swollman 7621259Swollman(define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>" 7769224Sjlemon [(parallel 7869152Sjlemon [(set (match_operand:DSP 0 "register_operand" "=d") 79126264Smlaier (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 8069224Sjlemon (match_operand:DSP 2 "register_operand" "d")] 8174914Sjhb UNSPEC_SUBQ_S)) 8274914Sjhb (set (reg:CCDSP CCDSP_OU_REGNUM) 8383130Sjlemon (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] 84132712Srwatson "TARGET_DSP" 8569152Sjlemon "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 86121816Sbrooks [(set_attr "type" "arith") 87121816Sbrooks (set_attr "mode" "SI")]) 88130416Smlaier 89130416Smlaier;; ADDSC 9060938Sjake(define_insn "mips_addsc" 9160938Sjake [(parallel 9260938Sjake [(set (match_operand:SI 0 "register_operand" "=d") 9372084Sphk (unspec:SI [(match_operand:SI 1 "register_operand" "d") 94159781Smlaier (match_operand:SI 2 "register_operand" "d")] 9521259Swollman UNSPEC_ADDSC)) 9621259Swollman (set (reg:CCDSP CCDSP_CA_REGNUM) 9721259Swollman (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])] 9821259Swollman "TARGET_DSP" 9921259Swollman "addsc\t%0,%1,%2" 10021259Swollman [(set_attr "type" "arith") 10121259Swollman (set_attr "mode" "SI")]) 10221259Swollman 10321259Swollman;; ADDWC 10421259Swollman(define_insn "mips_addwc" 10569152Sjlemon [(parallel 10621259Swollman [(set (match_operand:SI 0 "register_operand" "=d") 10721259Swollman (unspec:SI [(match_operand:SI 1 "register_operand" "d") 10821259Swollman (match_operand:SI 2 "register_operand" "d") 10921259Swollman (reg:CCDSP CCDSP_CA_REGNUM)] 11021259Swollman UNSPEC_ADDWC)) 11121259Swollman (set (reg:CCDSP CCDSP_OU_REGNUM) 11221259Swollman (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])] 11384380Smjacob "TARGET_DSP" 11421259Swollman "addwc\t%0,%1,%2" 11521259Swollman [(set_attr "type" "arith") 116147256Sbrooks (set_attr "mode" "SI")]) 11760938Sjake 118121816Sbrooks;; MODSUB 119121816Sbrooks(define_insn "mips_modsub" 120121816Sbrooks [(set (match_operand:SI 0 "register_operand" "=d") 12121259Swollman (unspec:SI [(match_operand:SI 1 "register_operand" "d") 122128291Sluigi (match_operand:SI 2 "register_operand" "d")] 123128291Sluigi UNSPEC_MODSUB))] 124128315Sluigi "TARGET_DSP" 125128315Sluigi "modsub\t%0,%1,%2" 126128315Sluigi [(set_attr "type" "arith") 127128315Sluigi (set_attr "mode" "SI")]) 128128291Sluigi 129128315Sluigi;; RADDU* 130152315Sru(define_insn "mips_raddu_w_qb" 131128291Sluigi [(set (match_operand:SI 0 "register_operand" "=d") 132133741Sjmg (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")] 13383130Sjlemon UNSPEC_RADDU_W_QB))] 134142901Sglebius "TARGET_DSP" 13521259Swollman "raddu.w.qb\t%0,%1" 13621259Swollman [(set_attr "type" "arith") 13721259Swollman (set_attr "mode" "SI")]) 138155051Sglebius 139102052Ssobomax;; ABSQ* 140162070Sandre(define_insn "mips_absq_s_<DSPQ:dspfmt2>" 141162070Sandre [(parallel 14221259Swollman [(set (match_operand:DSPQ 0 "register_operand" "=d") 14321259Swollman (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")] 14421259Swollman UNSPEC_ABSQ_S)) 14521404Swollman (set (reg:CCDSP CCDSP_OU_REGNUM) 14621404Swollman (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])] 14721259Swollman "TARGET_DSP" 14821259Swollman "absq_s.<DSPQ:dspfmt2>\t%0,%1" 14992725Salfred [(set_attr "type" "arith") 15092725Salfred (set_attr "mode" "SI")]) 151106931Ssam 152106931Ssam;; PRECRQ* 15321259Swollman(define_insn "mips_precrq_qb_ph" 15492725Salfred [(set (match_operand:V4QI 0 "register_operand" "=d") 15521259Swollman (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 15692725Salfred (match_operand:V2HI 2 "register_operand" "d")] 15721259Swollman UNSPEC_PRECRQ_QB_PH))] 15892725Salfred "TARGET_DSP" 15921259Swollman "precrq.qb.ph\t%0,%1,%2" 16092725Salfred [(set_attr "type" "arith") 16121404Swollman (set_attr "mode" "SI")]) 16292725Salfred 163152315Sru(define_insn "mips_precrq_ph_w" 164174388Skmacy [(set (match_operand:V2HI 0 "register_operand" "=d") 165148265Srwatson (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 166137062Srwatson (match_operand:SI 2 "register_operand" "d")] 167130416Smlaier UNSPEC_PRECRQ_PH_W))] 168123220Simp "TARGET_DSP" 169127828Sluigi "precrq.ph.w\t%0,%1,%2" 170146986Sthompsa [(set_attr "type" "arith") 171146986Sthompsa (set_attr "mode" "SI")]) 172127828Sluigi 173127828Sluigi(define_insn "mips_precrq_rs_ph_w" 174122524Srwatson [(parallel 175121161Sume [(set (match_operand:V2HI 0 "register_operand" "=d") 176127828Sluigi (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 177127828Sluigi (match_operand:SI 2 "register_operand" "d")] 178121161Sume UNSPEC_PRECRQ_RS_PH_W)) 179121470Sume (set (reg:CCDSP CCDSP_OU_REGNUM) 180121470Sume (unspec:CCDSP [(match_dup 1) (match_dup 2)] 181132712Srwatson UNSPEC_PRECRQ_RS_PH_W))])] 182145320Sglebius "TARGET_DSP" 183148640Srwatson "precrq_rs.ph.w\t%0,%1,%2" 184152209Sthompsa [(set_attr "type" "arith") 185159781Smlaier (set_attr "mode" "SI")]) 186159781Smlaier 187159781Smlaier;; PRECRQU* 188168793Sthompsa(define_insn "mips_precrqu_s_qb_ph" 189174388Skmacy [(parallel 190174388Skmacy [(set (match_operand:V4QI 0 "register_operand" "=d") 19121259Swollman (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 19269152Sjlemon (match_operand:V2HI 2 "register_operand" "d")] 19392725Salfred UNSPEC_PRECRQU_S_QB_PH)) 19421259Swollman (set (reg:CCDSP CCDSP_OU_REGNUM) 195128376Sluigi (unspec:CCDSP [(match_dup 1) (match_dup 2)] 196128376Sluigi UNSPEC_PRECRQU_S_QB_PH))])] 197128376Sluigi "TARGET_DSP" 198128376Sluigi "precrqu_s.qb.ph\t%0,%1,%2" 19921259Swollman [(set_attr "type" "arith") 20021259Swollman (set_attr "mode" "SI")]) 20121259Swollman 20221259Swollman;; PRECEQ* 20321259Swollman(define_insn "mips_preceq_w_phl" 20421259Swollman [(set (match_operand:SI 0 "register_operand" "=d") 205128871Sandre (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 20621259Swollman UNSPEC_PRECEQ_W_PHL))] 20758698Sjlemon "TARGET_DSP" 20821259Swollman "preceq.w.phl\t%0,%1" 20921259Swollman [(set_attr "type" "arith") 21021259Swollman (set_attr "mode" "SI")]) 21121259Swollman 21221259Swollman(define_insn "mips_preceq_w_phr" 21321259Swollman [(set (match_operand:SI 0 "register_operand" "=d") 21421259Swollman (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 21521259Swollman UNSPEC_PRECEQ_W_PHR))] 21621259Swollman "TARGET_DSP" 21721259Swollman "preceq.w.phr\t%0,%1" 21821259Swollman [(set_attr "type" "arith") 21921259Swollman (set_attr "mode" "SI")]) 220136950Sjmg 22121259Swollman;; PRECEQU* 22253541Sshin(define_insn "mips_precequ_ph_qbl" 22353541Sshin [(set (match_operand:V2HI 0 "register_operand" "=d") 22453541Sshin (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 225160981Sbrooks UNSPEC_PRECEQU_PH_QBL))] 22653541Sshin "TARGET_DSP" 22721259Swollman "precequ.ph.qbl\t%0,%1" 228148640Srwatson [(set_attr "type" "arith") 229148640Srwatson (set_attr "mode" "SI")]) 230148640Srwatson 231148640Srwatson(define_insn "mips_precequ_ph_qbr" 232148640Srwatson [(set (match_operand:V2HI 0 "register_operand" "=d") 233148640Srwatson (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 234148640Srwatson UNSPEC_PRECEQU_PH_QBR))] 235148640Srwatson "TARGET_DSP" 236148640Srwatson "precequ.ph.qbr\t%0,%1" 237148640Srwatson [(set_attr "type" "arith") 23821259Swollman (set_attr "mode" "SI")]) 23921259Swollman 24021259Swollman(define_insn "mips_precequ_ph_qbla" 24121259Swollman [(set (match_operand:V2HI 0 "register_operand" "=d") 24221259Swollman (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 24372200Sbmilekic UNSPEC_PRECEQU_PH_QBLA))] 24472200Sbmilekic "TARGET_DSP" 245130416Smlaier "precequ.ph.qbla\t%0,%1" 24669152Sjlemon [(set_attr "type" "arith") 24769152Sjlemon (set_attr "mode" "SI")]) 24869152Sjlemon 24921259Swollman(define_insn "mips_precequ_ph_qbra" 25069152Sjlemon [(set (match_operand:V2HI 0 "register_operand" "=d") 25169152Sjlemon (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 25269152Sjlemon UNSPEC_PRECEQU_PH_QBRA))] 25369152Sjlemon "TARGET_DSP" 25469152Sjlemon "precequ.ph.qbra\t%0,%1" 25569152Sjlemon [(set_attr "type" "arith") 25669152Sjlemon (set_attr "mode" "SI")]) 25769152Sjlemon 25869152Sjlemon;; PRECEU* 25969152Sjlemon(define_insn "mips_preceu_ph_qbl" 26069152Sjlemon [(set (match_operand:V2HI 0 "register_operand" "=d") 26169152Sjlemon (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 26269152Sjlemon UNSPEC_PRECEU_PH_QBL))] 26369152Sjlemon "TARGET_DSP" 26469152Sjlemon "preceu.ph.qbl\t%0,%1" 26569152Sjlemon [(set_attr "type" "arith") 26669152Sjlemon (set_attr "mode" "SI")]) 26769152Sjlemon 26869152Sjlemon(define_insn "mips_preceu_ph_qbr" 26969152Sjlemon [(set (match_operand:V2HI 0 "register_operand" "=d") 27069152Sjlemon (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 27169152Sjlemon UNSPEC_PRECEU_PH_QBR))] 27269152Sjlemon "TARGET_DSP" 27369152Sjlemon "preceu.ph.qbr\t%0,%1" 27469152Sjlemon [(set_attr "type" "arith") 27569152Sjlemon (set_attr "mode" "SI")]) 27669152Sjlemon 27769152Sjlemon(define_insn "mips_preceu_ph_qbla" 27869152Sjlemon [(set (match_operand:V2HI 0 "register_operand" "=d") 27969152Sjlemon (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 28069152Sjlemon UNSPEC_PRECEU_PH_QBLA))] 28169152Sjlemon "TARGET_DSP" 28269152Sjlemon "preceu.ph.qbla\t%0,%1" 283136950Sjmg [(set_attr "type" "arith") 28469152Sjlemon (set_attr "mode" "SI")]) 28569152Sjlemon 28669152Sjlemon(define_insn "mips_preceu_ph_qbra" 28769152Sjlemon [(set (match_operand:V2HI 0 "register_operand" "=d") 28869152Sjlemon (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 28969152Sjlemon UNSPEC_PRECEU_PH_QBRA))] 29069152Sjlemon "TARGET_DSP" 29169152Sjlemon "preceu.ph.qbra\t%0,%1" 29269152Sjlemon [(set_attr "type" "arith") 29369152Sjlemon (set_attr "mode" "SI")]) 29469152Sjlemon 29569152Sjlemon;; Table 2-2. MIPS DSP ASE Instructions: Shift 296130416Smlaier;; SHLL* 297130416Smlaier(define_insn "mips_shll_<DSPV:dspfmt2>" 298130416Smlaier [(parallel 299130416Smlaier [(set (match_operand:DSPV 0 "register_operand" "=d,d") 30069152Sjlemon (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d") 30169152Sjlemon (match_operand:SI 2 "arith_operand" "I,d")] 30269152Sjlemon UNSPEC_SHLL)) 30369152Sjlemon (set (reg:CCDSP CCDSP_OU_REGNUM) 30469152Sjlemon (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])] 30569152Sjlemon "TARGET_DSP" 30669152Sjlemon{ 30769152Sjlemon if (which_alternative == 0) 30869152Sjlemon { 309130416Smlaier if (INTVAL (operands[2]) 310130416Smlaier & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>) 311130416Smlaier operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>); 312130416Smlaier return "shll.<DSPV:dspfmt2>\t%0,%1,%2"; 313130416Smlaier } 314130416Smlaier return "shllv.<DSPV:dspfmt2>\t%0,%1,%2"; 31555205Speter} 316126264Smlaier [(set_attr "type" "shift") 317126264Smlaier (set_attr "mode" "SI")]) 318126264Smlaier 319126264Smlaier(define_insn "mips_shll_s_<DSPQ:dspfmt2>" 320126264Smlaier [(parallel 321126264Smlaier [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 322126264Smlaier (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 323126264Smlaier (match_operand:SI 2 "arith_operand" "I,d")] 324126264Smlaier UNSPEC_SHLL_S)) 325126264Smlaier (set (reg:CCDSP CCDSP_OU_REGNUM) 326159781Smlaier (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])] 327159781Smlaier "TARGET_DSP" 328159781Smlaier{ 329159781Smlaier if (which_alternative == 0) 330159781Smlaier { 331159781Smlaier if (INTVAL (operands[2]) 332159781Smlaier & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 333159781Smlaier operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 334159781Smlaier return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 335159781Smlaier } 336159781Smlaier return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 337159781Smlaier} 338159781Smlaier [(set_attr "type" "shift") 339159781Smlaier (set_attr "mode" "SI")]) 340159781Smlaier 341159781Smlaier;; SHRL* 342159781Smlaier(define_insn "mips_shrl_qb" 343159781Smlaier [(set (match_operand:V4QI 0 "register_operand" "=d,d") 344159781Smlaier (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d") 345159781Smlaier (match_operand:SI 2 "arith_operand" "I,d")] 346159781Smlaier UNSPEC_SHRL_QB))] 347159781Smlaier "TARGET_DSP" 348159781Smlaier{ 349159781Smlaier if (which_alternative == 0) 350159781Smlaier { 351159781Smlaier if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7) 352159781Smlaier operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7); 353159781Smlaier return "shrl.qb\t%0,%1,%2"; 354159781Smlaier } 355159781Smlaier return "shrlv.qb\t%0,%1,%2"; 356159781Smlaier} 357121470Sume [(set_attr "type" "shift") 358121470Sume (set_attr "mode" "SI")]) 359121470Sume 360121470Sume;; SHRA* 361121470Sume(define_insn "mips_shra_ph" 362121470Sume [(set (match_operand:V2HI 0 "register_operand" "=d,d") 363121470Sume (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d") 364136704Srwatson (match_operand:SI 2 "arith_operand" "I,d")] 365136704Srwatson UNSPEC_SHRA_PH))] 366136704Srwatson "TARGET_DSP" 367136704Srwatson{ 368136704Srwatson if (which_alternative == 0) 369136704Srwatson { 370136704Srwatson if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf) 371136704Srwatson operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf); 372136704Srwatson return "shra.ph\t%0,%1,%2"; 373136704Srwatson } 374137065Srwatson return "shrav.ph\t%0,%1,%2"; 375137065Srwatson} 376130416Smlaier [(set_attr "type" "shift") 377130416Smlaier (set_attr "mode" "SI")]) 378130416Smlaier 379130416Smlaier(define_insn "mips_shra_r_<DSPQ:dspfmt2>" 38021259Swollman [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 381132712Srwatson (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 382132712Srwatson (match_operand:SI 2 "arith_operand" "I,d")] 383130416Smlaier UNSPEC_SHRA_R))] 384130416Smlaier "TARGET_DSP" 385130416Smlaier{ 386130416Smlaier if (which_alternative == 0) 387130416Smlaier { 388130416Smlaier if (INTVAL (operands[2]) 389130416Smlaier & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 390130416Smlaier operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 391130416Smlaier return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 392130416Smlaier } 393130416Smlaier return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 394130416Smlaier} 395130416Smlaier [(set_attr "type" "shift") 396130416Smlaier (set_attr "mode" "SI")]) 397130416Smlaier 398130416Smlaier;; Table 2-3. MIPS DSP ASE Instructions: Multiply 399130416Smlaier;; MULEU* 400130416Smlaier(define_insn "mips_muleu_s_ph_qbl" 40121259Swollman [(parallel 402130416Smlaier [(set (match_operand:V2HI 0 "register_operand" "=d") 403130416Smlaier (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 404130416Smlaier (match_operand:V2HI 2 "register_operand" "d")] 405130508Smlaier UNSPEC_MULEU_S_PH_QBL)) 406130416Smlaier (set (reg:CCDSP CCDSP_OU_REGNUM) 407130416Smlaier (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL)) 408130416Smlaier (clobber (match_scratch:DI 3 "=x"))])] 409130416Smlaier "TARGET_DSP" 410130416Smlaier "muleu_s.ph.qbl\t%0,%1,%2" 411130416Smlaier [(set_attr "type" "imul3") 412130416Smlaier (set_attr "mode" "SI")]) 413130416Smlaier 414130416Smlaier(define_insn "mips_muleu_s_ph_qbr" 415130416Smlaier [(parallel 416130416Smlaier [(set (match_operand:V2HI 0 "register_operand" "=d") 417130416Smlaier (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 418130416Smlaier (match_operand:V2HI 2 "register_operand" "d")] 419130416Smlaier UNSPEC_MULEU_S_PH_QBR)) 420130416Smlaier (set (reg:CCDSP CCDSP_OU_REGNUM) 421130416Smlaier (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR)) 422130508Smlaier (clobber (match_scratch:DI 3 "=x"))])] 423130416Smlaier "TARGET_DSP" 424130416Smlaier "muleu_s.ph.qbr\t%0,%1,%2" 425130416Smlaier [(set_attr "type" "imul3") 426130416Smlaier (set_attr "mode" "SI")]) 427130416Smlaier 428130416Smlaier;; MULQ* 429130416Smlaier(define_insn "mips_mulq_rs_ph" 430130416Smlaier [(parallel 431130416Smlaier [(set (match_operand:V2HI 0 "register_operand" "=d") 432130416Smlaier (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 433130416Smlaier (match_operand:V2HI 2 "register_operand" "d")] 434130416Smlaier UNSPEC_MULQ_RS_PH)) 435130416Smlaier (set (reg:CCDSP CCDSP_OU_REGNUM) 436130416Smlaier (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) 437130416Smlaier (clobber (match_scratch:DI 3 "=x"))])] 438130416Smlaier "TARGET_DSP" 439130416Smlaier "mulq_rs.ph\t%0,%1,%2" 440130416Smlaier [(set_attr "type" "imul3") 441130416Smlaier (set_attr "mode" "SI")]) 442130416Smlaier 443130416Smlaier;; MULEQ* 444130416Smlaier(define_insn "mips_muleq_s_w_phl" 445130416Smlaier [(parallel 446130416Smlaier [(set (match_operand:SI 0 "register_operand" "=d") 447130416Smlaier (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 448130416Smlaier (match_operand:V2HI 2 "register_operand" "d")] 449130416Smlaier UNSPEC_MULEQ_S_W_PHL)) 450130416Smlaier (set (reg:CCDSP CCDSP_OU_REGNUM) 451130416Smlaier (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL)) 452130416Smlaier (clobber (match_scratch:DI 3 "=x"))])] 453130416Smlaier "TARGET_DSP" 454130416Smlaier "muleq_s.w.phl\t%0,%1,%2" 455130416Smlaier [(set_attr "type" "imul3") 456130416Smlaier (set_attr "mode" "SI")]) 457130416Smlaier 458130416Smlaier(define_insn "mips_muleq_s_w_phr" 459130416Smlaier [(parallel 460130416Smlaier [(set (match_operand:SI 0 "register_operand" "=d") 461130416Smlaier (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 462130416Smlaier (match_operand:V2HI 2 "register_operand" "d")] 463148886Srwatson UNSPEC_MULEQ_S_W_PHR)) 464148886Srwatson (set (reg:CCDSP CCDSP_OU_REGNUM) 465148886Srwatson (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR)) 466148886Srwatson (clobber (match_scratch:DI 3 "=x"))])] 467130416Smlaier "TARGET_DSP" 468130416Smlaier "muleq_s.w.phr\t%0,%1,%2" 469130416Smlaier [(set_attr "type" "imul3") 470130416Smlaier (set_attr "mode" "SI")]) 471130416Smlaier 472130416Smlaier;; DPAU* 473130416Smlaier(define_insn "mips_dpau_h_qbl" 474130416Smlaier [(set (match_operand:DI 0 "register_operand" "=a") 475130416Smlaier (unspec:DI [(match_operand:DI 1 "register_operand" "0") 476130416Smlaier (match_operand:V4QI 2 "register_operand" "d") 477130416Smlaier (match_operand:V4QI 3 "register_operand" "d")] 478130416Smlaier UNSPEC_DPAU_H_QBL))] 479148886Srwatson "TARGET_DSP && !TARGET_64BIT" 480132712Srwatson "dpau.h.qbl\t%q0,%2,%3" 481130416Smlaier [(set_attr "type" "imadd") 482130416Smlaier (set_attr "mode" "SI")]) 483130416Smlaier 484130416Smlaier(define_insn "mips_dpau_h_qbr" 485130512Smlaier [(set (match_operand:DI 0 "register_operand" "=a") 486130416Smlaier (unspec:DI [(match_operand:DI 1 "register_operand" "0") 487130416Smlaier (match_operand:V4QI 2 "register_operand" "d") 488130416Smlaier (match_operand:V4QI 3 "register_operand" "d")] 489130416Smlaier UNSPEC_DPAU_H_QBR))] 490130416Smlaier "TARGET_DSP && !TARGET_64BIT" 491130416Smlaier "dpau.h.qbr\t%q0,%2,%3" 492130416Smlaier [(set_attr "type" "imadd") 493130416Smlaier (set_attr "mode" "SI")]) 494130416Smlaier 495130416Smlaier;; DPSU* 496130416Smlaier(define_insn "mips_dpsu_h_qbl" 497130416Smlaier [(set (match_operand:DI 0 "register_operand" "=a") 498130416Smlaier (unspec:DI [(match_operand:DI 1 "register_operand" "0") 499130416Smlaier (match_operand:V4QI 2 "register_operand" "d") 500130416Smlaier (match_operand:V4QI 3 "register_operand" "d")] 501130416Smlaier UNSPEC_DPSU_H_QBL))] 502130416Smlaier "TARGET_DSP && !TARGET_64BIT" 503130416Smlaier "dpsu.h.qbl\t%q0,%2,%3" 504130416Smlaier [(set_attr "type" "imadd") 505130416Smlaier (set_attr "mode" "SI")]) 506130416Smlaier 507130416Smlaier(define_insn "mips_dpsu_h_qbr" 508130416Smlaier [(set (match_operand:DI 0 "register_operand" "=a") 509130416Smlaier (unspec:DI [(match_operand:DI 1 "register_operand" "0") 510130416Smlaier (match_operand:V4QI 2 "register_operand" "d") 511130416Smlaier (match_operand:V4QI 3 "register_operand" "d")] 512130416Smlaier UNSPEC_DPSU_H_QBR))] 513130416Smlaier "TARGET_DSP && !TARGET_64BIT" 514130416Smlaier "dpsu.h.qbr\t%q0,%2,%3" 515130416Smlaier [(set_attr "type" "imadd") 516130416Smlaier (set_attr "mode" "SI")]) 517130416Smlaier 518132152Smlaier;; DPAQ* 519132152Smlaier(define_insn "mips_dpaq_s_w_ph" 520130416Smlaier [(parallel 521130416Smlaier [(set (match_operand:DI 0 "register_operand" "=a") 522130416Smlaier (unspec:DI [(match_operand:DI 1 "register_operand" "0") 523130416Smlaier (match_operand:V2HI 2 "register_operand" "d") 524130416Smlaier (match_operand:V2HI 3 "register_operand" "d")] 525130416Smlaier UNSPEC_DPAQ_S_W_PH)) 526130416Smlaier (set (reg:CCDSP CCDSP_OU_REGNUM) 527130416Smlaier (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 528130416Smlaier UNSPEC_DPAQ_S_W_PH))])] 529132152Smlaier "TARGET_DSP && !TARGET_64BIT" 530132152Smlaier "dpaq_s.w.ph\t%q0,%2,%3" 531132152Smlaier [(set_attr "type" "imadd") 532130416Smlaier (set_attr "mode" "SI")]) 533130416Smlaier 534130416Smlaier;; DPSQ* 535130416Smlaier(define_insn "mips_dpsq_s_w_ph" 536130416Smlaier [(parallel 537130416Smlaier [(set (match_operand:DI 0 "register_operand" "=a") 538130416Smlaier (unspec:DI [(match_operand:DI 1 "register_operand" "0") 53949459Sbrian (match_operand:V2HI 2 "register_operand" "d") 54049459Sbrian (match_operand:V2HI 3 "register_operand" "d")] 54149459Sbrian UNSPEC_DPSQ_S_W_PH)) 54249459Sbrian (set (reg:CCDSP CCDSP_OU_REGNUM) 54349459Sbrian (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 54449459Sbrian UNSPEC_DPSQ_S_W_PH))])] 54549459Sbrian "TARGET_DSP && !TARGET_64BIT" 54655205Speter "dpsq_s.w.ph\t%q0,%2,%3" 54721259Swollman [(set_attr "type" "imadd") 54821259Swollman (set_attr "mode" "SI")]) 54921259Swollman 55021259Swollman;; MULSAQ* 55121259Swollman(define_insn "mips_mulsaq_s_w_ph" 55221259Swollman [(parallel 553128291Sluigi [(set (match_operand:DI 0 "register_operand" "=a") 554128291Sluigi (unspec:DI [(match_operand:DI 1 "register_operand" "0") 555128291Sluigi (match_operand:V2HI 2 "register_operand" "d") 556128291Sluigi (match_operand:V2HI 3 "register_operand" "d")] 55721259Swollman UNSPEC_MULSAQ_S_W_PH)) 55821259Swollman (set (reg:CCDSP CCDSP_OU_REGNUM) 55921259Swollman (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 56021259Swollman UNSPEC_MULSAQ_S_W_PH))])] 56121259Swollman "TARGET_DSP && !TARGET_64BIT" 56221259Swollman "mulsaq_s.w.ph\t%q0,%2,%3" 56367334Sjoe [(set_attr "type" "imadd") 56421259Swollman (set_attr "mode" "SI")]) 56560938Sjake 56621259Swollman;; DPAQ* 56792725Salfred(define_insn "mips_dpaq_sa_l_w" 56821259Swollman [(parallel 56947254Spb [(set (match_operand:DI 0 "register_operand" "=a") 57021259Swollman (unspec:DI [(match_operand:DI 1 "register_operand" "0") 57128845Sjulian (match_operand:SI 2 "register_operand" "d") 57292725Salfred (match_operand:SI 3 "register_operand" "d")] 573108033Shsu UNSPEC_DPAQ_SA_L_W)) 57421259Swollman (set (reg:CCDSP CCDSP_OU_REGNUM) 57521259Swollman (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 57621259Swollman UNSPEC_DPAQ_SA_L_W))])] 57753541Sshin "TARGET_DSP && !TARGET_64BIT" 57853541Sshin "dpaq_sa.l.w\t%q0,%2,%3" 57953541Sshin [(set_attr "type" "imadd") 580108033Shsu (set_attr "mode" "SI")]) 581108033Shsu 582108033Shsu;; DPSQ* 583108033Shsu(define_insn "mips_dpsq_sa_l_w" 584108033Shsu [(parallel 585108033Shsu [(set (match_operand:DI 0 "register_operand" "=a") 58621404Swollman (unspec:DI [(match_operand:DI 1 "register_operand" "0") 58752904Sshin (match_operand:SI 2 "register_operand" "d") 58852904Sshin (match_operand:SI 3 "register_operand" "d")] 589108470Sschweikh UNSPEC_DPSQ_SA_L_W)) 59053541Sshin (set (reg:CCDSP CCDSP_OU_REGNUM) 59152904Sshin (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 59252904Sshin UNSPEC_DPSQ_SA_L_W))])] 59352904Sshin "TARGET_DSP && !TARGET_64BIT" 59452904Sshin "dpsq_sa.l.w\t%q0,%2,%3" 59560938Sjake [(set_attr "type" "imadd") 59652904Sshin (set_attr "mode" "SI")]) 59752904Sshin 59852904Sshin;; MAQ* 59952904Sshin(define_insn "mips_maq_s_w_phl" 60052904Sshin [(parallel 60121404Swollman [(set (match_operand:DI 0 "register_operand" "=a") 60221404Swollman (unspec:DI [(match_operand:DI 1 "register_operand" "0") 60321404Swollman (match_operand:V2HI 2 "register_operand" "d") 60421404Swollman (match_operand:V2HI 3 "register_operand" "d")] 60572084Sphk UNSPEC_MAQ_S_W_PHL)) 60621434Swollman (set (reg:CCDSP CCDSP_OU_REGNUM) 60721434Swollman (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 60821434Swollman UNSPEC_MAQ_S_W_PHL))])] 60921434Swollman "TARGET_DSP && !TARGET_64BIT" 61021434Swollman "maq_s.w.phl\t%q0,%2,%3" 611167729Sbms [(set_attr "type" "imadd") 61221404Swollman (set_attr "mode" "SI")]) 61321404Swollman 61455205Speter(define_insn "mips_maq_s_w_phr" 615108036Shsu [(parallel 616108036Shsu [(set (match_operand:DI 0 "register_operand" "=a") 617108036Shsu (unspec:DI [(match_operand:DI 1 "register_operand" "0") 618108036Shsu (match_operand:V2HI 2 "register_operand" "d") 619108036Shsu (match_operand:V2HI 3 "register_operand" "d")] 620108036Shsu UNSPEC_MAQ_S_W_PHR)) 621108036Shsu (set (reg:CCDSP CCDSP_OU_REGNUM) 622108036Shsu (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 623108036Shsu UNSPEC_MAQ_S_W_PHR))])] 624108036Shsu "TARGET_DSP && !TARGET_64BIT" 62546568Speter "maq_s.w.phr\t%q0,%2,%3" 62621259Swollman [(set_attr "type" "imadd") 627108036Shsu (set_attr "mode" "SI")]) 628108036Shsu 629108036Shsu;; MAQ_SA* 630108036Shsu(define_insn "mips_maq_sa_w_phl" 631108036Shsu [(parallel 632108033Shsu [(set (match_operand:DI 0 "register_operand" "=a") 633108033Shsu (unspec:DI [(match_operand:DI 1 "register_operand" "0") 634108172Shsu (match_operand:V2HI 2 "register_operand" "d") 635108298Shsu (match_operand:V2HI 3 "register_operand" "d")] 636108298Shsu UNSPEC_MAQ_SA_W_PHL)) 637108172Shsu (set (reg:CCDSP CCDSP_OU_REGNUM) 638108172Shsu (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 639108172Shsu UNSPEC_MAQ_SA_W_PHL))])] 640108172Shsu "TARGET_DSP && !TARGET_64BIT" 641108172Shsu "maq_sa.w.phl\t%q0,%2,%3" 64283130Sjlemon [(set_attr "type" "imadd") 64387914Sjlemon (set_attr "mode" "SI")]) 644130585Sphk 64583130Sjlemon(define_insn "mips_maq_sa_w_phr" 64683130Sjlemon [(parallel 64783130Sjlemon [(set (match_operand:DI 0 "register_operand" "=a") 648128315Sluigi (unspec:DI [(match_operand:DI 1 "register_operand" "0") 649128315Sluigi (match_operand:V2HI 2 "register_operand" "d") 650128315Sluigi (match_operand:V2HI 3 "register_operand" "d")] 651128315Sluigi UNSPEC_MAQ_SA_W_PHR)) 652128315Sluigi (set (reg:CCDSP CCDSP_OU_REGNUM) 653152315Sru (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 65483130Sjlemon UNSPEC_MAQ_SA_W_PHR))])] 65583130Sjlemon "TARGET_DSP && !TARGET_64BIT" 65621259Swollman "maq_sa.w.phr\t%q0,%2,%3" 65783130Sjlemon [(set_attr "type" "imadd") 65821259Swollman (set_attr "mode" "SI")]) 65971791Speter 66021259Swollman;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation 66121259Swollman;; BITREV 662159781Smlaier(define_insn "mips_bitrev" 663159781Smlaier [(set (match_operand:SI 0 "register_operand" "=d") 66492725Salfred (unspec:SI [(match_operand:SI 1 "register_operand" "d")] 66592725Salfred UNSPEC_BITREV))] 666147256Sbrooks "TARGET_DSP" 66792725Salfred "bitrev\t%0,%1" 66892725Salfred [(set_attr "type" "arith") 669167729Sbms (set_attr "mode" "SI")]) 67092725Salfred 671146620Speadar;; INSV 67292725Salfred(define_insn "mips_insv" 673167732Sbms [(set (match_operand:SI 0 "register_operand" "=d") 674167732Sbms (unspec:SI [(match_operand:SI 1 "register_operand" "0") 675147256Sbrooks (match_operand:SI 2 "register_operand" "d") 676147256Sbrooks (reg:CCDSP CCDSP_SC_REGNUM) 677121816Sbrooks (reg:CCDSP CCDSP_PO_REGNUM)] 678138542Ssam UNSPEC_INSV))] 679103900Sbrooks "TARGET_DSP" 68092725Salfred "insv\t%0,%2" 68192725Salfred [(set_attr "type" "arith") 68292725Salfred (set_attr "mode" "SI")]) 68392725Salfred 68492725Salfred;; REPL* 68592725Salfred(define_insn "mips_repl_qb" 68621259Swollman [(set (match_operand:V4QI 0 "register_operand" "=d,d") 68792725Salfred (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")] 688162068Sandre UNSPEC_REPL_QB))] 68992725Salfred "TARGET_DSP" 69092725Salfred{ 69192725Salfred if (which_alternative == 0) 69292725Salfred { 69321259Swollman if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff) 69492725Salfred operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); 69521434Swollman return "repl.qb\t%0,%1"; 696147256Sbrooks } 697147256Sbrooks return "replv.qb\t%0,%1"; 698147256Sbrooks} 699147256Sbrooks [(set_attr "type" "arith") 700147256Sbrooks (set_attr "mode" "SI")]) 70184931Sfjoe 702152315Sru(define_insn "mips_repl_ph" 70384931Sfjoe [(set (match_operand:V2HI 0 "register_operand" "=d,d") 70487902Sluigi (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")] 705150789Sglebius UNSPEC_REPL_PH))] 70687902Sluigi "TARGET_DSP" 70792725Salfred "@ 70892725Salfred repl.ph\t%0,%1 70992725Salfred replv.ph\t%0,%1" 71087902Sluigi [(set_attr "type" "arith") 71187902Sluigi (set_attr "mode" "SI")]) 71255205Speter 71321259Swollman;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick 71421259Swollman;; CMPU.* CMP.* 715(define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>" 716 [(set (reg:CCDSP CCDSP_CC_REGNUM) 717 (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 718 (match_operand:DSPV 1 "register_operand" "d") 719 (reg:CCDSP CCDSP_CC_REGNUM)] 720 UNSPEC_CMP_EQ))] 721 "TARGET_DSP" 722 "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1" 723 [(set_attr "type" "arith") 724 (set_attr "mode" "SI")]) 725 726(define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>" 727 [(set (reg:CCDSP CCDSP_CC_REGNUM) 728 (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 729 (match_operand:DSPV 1 "register_operand" "d") 730 (reg:CCDSP CCDSP_CC_REGNUM)] 731 UNSPEC_CMP_LT))] 732 "TARGET_DSP" 733 "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1" 734 [(set_attr "type" "arith") 735 (set_attr "mode" "SI")]) 736 737(define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>" 738 [(set (reg:CCDSP CCDSP_CC_REGNUM) 739 (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 740 (match_operand:DSPV 1 "register_operand" "d") 741 (reg:CCDSP CCDSP_CC_REGNUM)] 742 UNSPEC_CMP_LE))] 743 "TARGET_DSP" 744 "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1" 745 [(set_attr "type" "arith") 746 (set_attr "mode" "SI")]) 747 748(define_insn "mips_cmpgu_eq_qb" 749 [(set (match_operand:SI 0 "register_operand" "=d") 750 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 751 (match_operand:V4QI 2 "register_operand" "d")] 752 UNSPEC_CMPGU_EQ_QB))] 753 "TARGET_DSP" 754 "cmpgu.eq.qb\t%0,%1,%2" 755 [(set_attr "type" "arith") 756 (set_attr "mode" "SI")]) 757 758(define_insn "mips_cmpgu_lt_qb" 759 [(set (match_operand:SI 0 "register_operand" "=d") 760 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 761 (match_operand:V4QI 2 "register_operand" "d")] 762 UNSPEC_CMPGU_LT_QB))] 763 "TARGET_DSP" 764 "cmpgu.lt.qb\t%0,%1,%2" 765 [(set_attr "type" "arith") 766 (set_attr "mode" "SI")]) 767 768(define_insn "mips_cmpgu_le_qb" 769 [(set (match_operand:SI 0 "register_operand" "=d") 770 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 771 (match_operand:V4QI 2 "register_operand" "d")] 772 UNSPEC_CMPGU_LE_QB))] 773 "TARGET_DSP" 774 "cmpgu.le.qb\t%0,%1,%2" 775 [(set_attr "type" "arith") 776 (set_attr "mode" "SI")]) 777 778;; PICK* 779(define_insn "mips_pick_<DSPV:dspfmt2>" 780 [(set (match_operand:DSPV 0 "register_operand" "=d") 781 (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d") 782 (match_operand:DSPV 2 "register_operand" "d") 783 (reg:CCDSP CCDSP_CC_REGNUM)] 784 UNSPEC_PICK))] 785 "TARGET_DSP" 786 "pick.<DSPV:dspfmt2>\t%0,%1,%2" 787 [(set_attr "type" "arith") 788 (set_attr "mode" "SI")]) 789 790;; PACKRL* 791(define_insn "mips_packrl_ph" 792 [(set (match_operand:V2HI 0 "register_operand" "=d") 793 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 794 (match_operand:V2HI 2 "register_operand" "d")] 795 UNSPEC_PACKRL_PH))] 796 "TARGET_DSP" 797 "packrl.ph\t%0,%1,%2" 798 [(set_attr "type" "arith") 799 (set_attr "mode" "SI")]) 800 801;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access 802;; EXTR* 803(define_insn "mips_extr_w" 804 [(parallel 805 [(set (match_operand:SI 0 "register_operand" "=d,d") 806 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 807 (match_operand:SI 2 "arith_operand" "I,d")] 808 UNSPEC_EXTR_W)) 809 (set (reg:CCDSP CCDSP_OU_REGNUM) 810 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])] 811 "TARGET_DSP && !TARGET_64BIT" 812{ 813 if (which_alternative == 0) 814 { 815 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 816 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 817 return "extr.w\t%0,%q1,%2"; 818 } 819 return "extrv.w\t%0,%q1,%2"; 820} 821 [(set_attr "type" "mfhilo") 822 (set_attr "mode" "SI")]) 823 824(define_insn "mips_extr_r_w" 825 [(parallel 826 [(set (match_operand:SI 0 "register_operand" "=d,d") 827 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 828 (match_operand:SI 2 "arith_operand" "I,d")] 829 UNSPEC_EXTR_R_W)) 830 (set (reg:CCDSP CCDSP_OU_REGNUM) 831 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])] 832 "TARGET_DSP && !TARGET_64BIT" 833{ 834 if (which_alternative == 0) 835 { 836 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 837 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 838 return "extr_r.w\t%0,%q1,%2"; 839 } 840 return "extrv_r.w\t%0,%q1,%2"; 841} 842 [(set_attr "type" "mfhilo") 843 (set_attr "mode" "SI")]) 844 845(define_insn "mips_extr_rs_w" 846 [(parallel 847 [(set (match_operand:SI 0 "register_operand" "=d,d") 848 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 849 (match_operand:SI 2 "arith_operand" "I,d")] 850 UNSPEC_EXTR_RS_W)) 851 (set (reg:CCDSP CCDSP_OU_REGNUM) 852 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])] 853 "TARGET_DSP && !TARGET_64BIT" 854{ 855 if (which_alternative == 0) 856 { 857 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 858 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 859 return "extr_rs.w\t%0,%q1,%2"; 860 } 861 return "extrv_rs.w\t%0,%q1,%2"; 862} 863 [(set_attr "type" "mfhilo") 864 (set_attr "mode" "SI")]) 865 866;; EXTR*_S.H 867(define_insn "mips_extr_s_h" 868 [(parallel 869 [(set (match_operand:SI 0 "register_operand" "=d,d") 870 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 871 (match_operand:SI 2 "arith_operand" "I,d")] 872 UNSPEC_EXTR_S_H)) 873 (set (reg:CCDSP CCDSP_OU_REGNUM) 874 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])] 875 "TARGET_DSP && !TARGET_64BIT" 876{ 877 if (which_alternative == 0) 878 { 879 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 880 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 881 return "extr_s.h\t%0,%q1,%2"; 882 } 883 return "extrv_s.h\t%0,%q1,%2"; 884} 885 [(set_attr "type" "mfhilo") 886 (set_attr "mode" "SI")]) 887 888;; EXTP* 889(define_insn "mips_extp" 890 [(parallel 891 [(set (match_operand:SI 0 "register_operand" "=d,d") 892 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 893 (match_operand:SI 2 "arith_operand" "I,d") 894 (reg:CCDSP CCDSP_PO_REGNUM)] 895 UNSPEC_EXTP)) 896 (set (reg:CCDSP CCDSP_EF_REGNUM) 897 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])] 898 "TARGET_DSP && !TARGET_64BIT" 899{ 900 if (which_alternative == 0) 901 { 902 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 903 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 904 return "extp\t%0,%q1,%2"; 905 } 906 return "extpv\t%0,%q1,%2"; 907} 908 [(set_attr "type" "mfhilo") 909 (set_attr "mode" "SI")]) 910 911(define_insn "mips_extpdp" 912 [(parallel 913 [(set (match_operand:SI 0 "register_operand" "=d,d") 914 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 915 (match_operand:SI 2 "arith_operand" "I,d") 916 (reg:CCDSP CCDSP_PO_REGNUM)] 917 UNSPEC_EXTPDP)) 918 (set (reg:CCDSP CCDSP_PO_REGNUM) 919 (unspec:CCDSP [(match_dup 1) (match_dup 2) 920 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP)) 921 (set (reg:CCDSP CCDSP_EF_REGNUM) 922 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])] 923 "TARGET_DSP && !TARGET_64BIT" 924{ 925 if (which_alternative == 0) 926 { 927 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 928 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 929 return "extpdp\t%0,%q1,%2"; 930 } 931 return "extpdpv\t%0,%q1,%2"; 932} 933 [(set_attr "type" "mfhilo") 934 (set_attr "mode" "SI")]) 935 936;; SHILO* 937(define_insn "mips_shilo" 938 [(set (match_operand:DI 0 "register_operand" "=a,a") 939 (unspec:DI [(match_operand:DI 1 "register_operand" "0,0") 940 (match_operand:SI 2 "arith_operand" "I,d")] 941 UNSPEC_SHILO))] 942 "TARGET_DSP && !TARGET_64BIT" 943{ 944 if (which_alternative == 0) 945 { 946 if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31) 947 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 948 return "shilo\t%q0,%2"; 949 } 950 return "shilov\t%q0,%2"; 951} 952 [(set_attr "type" "mfhilo") 953 (set_attr "mode" "SI")]) 954 955;; MTHLIP* 956(define_insn "mips_mthlip" 957 [(parallel 958 [(set (match_operand:DI 0 "register_operand" "=a") 959 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 960 (match_operand:SI 2 "register_operand" "d") 961 (reg:CCDSP CCDSP_PO_REGNUM)] 962 UNSPEC_MTHLIP)) 963 (set (reg:CCDSP CCDSP_PO_REGNUM) 964 (unspec:CCDSP [(match_dup 1) (match_dup 2) 965 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])] 966 "TARGET_DSP && !TARGET_64BIT" 967 "mthlip\t%2,%q0" 968 [(set_attr "type" "mfhilo") 969 (set_attr "mode" "SI")]) 970 971;; WRDSP 972(define_insn "mips_wrdsp" 973 [(parallel 974 [(set (reg:CCDSP CCDSP_PO_REGNUM) 975 (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d") 976 (match_operand:SI 1 "const_uimm6_operand" "YA")] 977 UNSPEC_WRDSP)) 978 (set (reg:CCDSP CCDSP_SC_REGNUM) 979 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 980 (set (reg:CCDSP CCDSP_CA_REGNUM) 981 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 982 (set (reg:CCDSP CCDSP_OU_REGNUM) 983 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 984 (set (reg:CCDSP CCDSP_CC_REGNUM) 985 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 986 (set (reg:CCDSP CCDSP_EF_REGNUM) 987 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])] 988 "TARGET_DSP" 989 "wrdsp\t%0,%1" 990 [(set_attr "type" "arith") 991 (set_attr "mode" "SI")]) 992 993;; RDDSP 994(define_insn "mips_rddsp" 995 [(set (match_operand:SI 0 "register_operand" "=d") 996 (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA") 997 (reg:CCDSP CCDSP_PO_REGNUM) 998 (reg:CCDSP CCDSP_SC_REGNUM) 999 (reg:CCDSP CCDSP_CA_REGNUM) 1000 (reg:CCDSP CCDSP_OU_REGNUM) 1001 (reg:CCDSP CCDSP_CC_REGNUM) 1002 (reg:CCDSP CCDSP_EF_REGNUM)] 1003 UNSPEC_RDDSP))] 1004 "TARGET_DSP" 1005 "rddsp\t%0,%1" 1006 [(set_attr "type" "arith") 1007 (set_attr "mode" "SI")]) 1008 1009;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load 1010;; L*X 1011(define_insn "mips_lbux" 1012 [(set (match_operand:SI 0 "register_operand" "=d") 1013 (zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1 1014 "register_operand" "d") 1015 (match_operand:SI 2 1016 "register_operand" "d")))))] 1017 "TARGET_DSP" 1018 "lbux\t%0,%2(%1)" 1019 [(set_attr "type" "load") 1020 (set_attr "mode" "SI") 1021 (set_attr "length" "4")]) 1022 1023(define_insn "mips_lhx" 1024 [(set (match_operand:SI 0 "register_operand" "=d") 1025 (sign_extend:SI (mem:HI (plus:SI (match_operand:SI 1 1026 "register_operand" "d") 1027 (match_operand:SI 2 1028 "register_operand" "d")))))] 1029 "TARGET_DSP" 1030 "lhx\t%0,%2(%1)" 1031 [(set_attr "type" "load") 1032 (set_attr "mode" "SI") 1033 (set_attr "length" "4")]) 1034 1035(define_insn "mips_lwx" 1036 [(set (match_operand:SI 0 "register_operand" "=d") 1037 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") 1038 (match_operand:SI 2 "register_operand" "d"))))] 1039 "TARGET_DSP" 1040 "lwx\t%0,%2(%1)" 1041 [(set_attr "type" "load") 1042 (set_attr "mode" "SI") 1043 (set_attr "length" "4")]) 1044 1045;; Table 2-8. MIPS DSP ASE Instructions: Branch 1046;; BPOSGE32 1047(define_insn "mips_bposge" 1048 [(set (pc) 1049 (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM) 1050 (match_operand:SI 0 "immediate_operand" "I")) 1051 (label_ref (match_operand 1 "" "")) 1052 (pc)))] 1053 "TARGET_DSP" 1054 "%*bposge%0\t%1%/" 1055 [(set_attr "type" "branch") 1056 (set_attr "mode" "none")]) 1057 1058