1169689Skan(define_constants 2169689Skan [(CCDSP_PO_REGNUM 182) 3169689Skan (CCDSP_SC_REGNUM 183) 4169689Skan (CCDSP_CA_REGNUM 184) 5169689Skan (CCDSP_OU_REGNUM 185) 6169689Skan (CCDSP_CC_REGNUM 186) 7169689Skan (CCDSP_EF_REGNUM 187)]) 8169689Skan 9169689Skan;; This mode macro allows si, v2hi, v4qi for all possible modes in DSP ASE. 10169689Skan(define_mode_macro DSP [(SI "TARGET_DSP") 11169689Skan (V2HI "TARGET_DSP") 12169689Skan (V4QI "TARGET_DSP")]) 13169689Skan 14169689Skan;; This mode macro allows v2hi, v4qi for vector/SIMD data. 15169689Skan(define_mode_macro DSPV [(V2HI "TARGET_DSP") 16169689Skan (V4QI "TARGET_DSP")]) 17169689Skan 18169689Skan;; This mode macro allows si, v2hi for Q31 and V2Q15 fixed-point data. 19169689Skan(define_mode_macro DSPQ [(SI "TARGET_DSP") 20169689Skan (V2HI "TARGET_DSP")]) 21169689Skan 22169689Skan;; DSP instructions use q for fixed-point data, and u for integer in the infix. 23169689Skan(define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")]) 24169689Skan 25169689Skan;; DSP instructions use nothing for fixed-point data, and u for integer in 26169689Skan;; the infix. 27169689Skan(define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")]) 28169689Skan 29169689Skan;; DSP instructions use w, ph, qb in the postfix. 30169689Skan(define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")]) 31169689Skan 32169689Skan;; DSP shift masks for SI, V2HI, V4QI. 33169689Skan(define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")]) 34169689Skan 35169689Skan;; MIPS DSP ASE Revision 0.98 3/24/2005 36169689Skan;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic 37169689Skan;; ADDQ* 38169689Skan(define_insn "add<DSPV:mode>3" 39169689Skan [(parallel 40169689Skan [(set (match_operand:DSPV 0 "register_operand" "=d") 41169689Skan (plus:DSPV (match_operand:DSPV 1 "register_operand" "d") 42169689Skan (match_operand:DSPV 2 "register_operand" "d"))) 43169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 44169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])] 45169689Skan "" 46169689Skan "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 47169689Skan [(set_attr "type" "arith") 48169689Skan (set_attr "mode" "SI")]) 49169689Skan 50169689Skan(define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>" 51169689Skan [(parallel 52169689Skan [(set (match_operand:DSP 0 "register_operand" "=d") 53169689Skan (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 54169689Skan (match_operand:DSP 2 "register_operand" "d")] 55169689Skan UNSPEC_ADDQ_S)) 56169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 57169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] 58169689Skan "" 59169689Skan "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 60169689Skan [(set_attr "type" "arith") 61169689Skan (set_attr "mode" "SI")]) 62169689Skan 63169689Skan;; SUBQ* 64169689Skan(define_insn "sub<DSPV:mode>3" 65169689Skan [(parallel 66169689Skan [(set (match_operand:DSPV 0 "register_operand" "=d") 67169689Skan (minus:DSPV (match_operand:DSPV 1 "register_operand" "d") 68169689Skan (match_operand:DSPV 2 "register_operand" "d"))) 69169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 70169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])] 71169689Skan "TARGET_DSP" 72169689Skan "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 73169689Skan [(set_attr "type" "arith") 74169689Skan (set_attr "mode" "SI")]) 75169689Skan 76169689Skan(define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>" 77169689Skan [(parallel 78169689Skan [(set (match_operand:DSP 0 "register_operand" "=d") 79169689Skan (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 80169689Skan (match_operand:DSP 2 "register_operand" "d")] 81169689Skan UNSPEC_SUBQ_S)) 82169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 83169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] 84169689Skan "TARGET_DSP" 85169689Skan "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 86169689Skan [(set_attr "type" "arith") 87169689Skan (set_attr "mode" "SI")]) 88169689Skan 89169689Skan;; ADDSC 90169689Skan(define_insn "mips_addsc" 91169689Skan [(parallel 92169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 93169689Skan (unspec:SI [(match_operand:SI 1 "register_operand" "d") 94169689Skan (match_operand:SI 2 "register_operand" "d")] 95169689Skan UNSPEC_ADDSC)) 96169689Skan (set (reg:CCDSP CCDSP_CA_REGNUM) 97169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])] 98169689Skan "TARGET_DSP" 99169689Skan "addsc\t%0,%1,%2" 100169689Skan [(set_attr "type" "arith") 101169689Skan (set_attr "mode" "SI")]) 102169689Skan 103169689Skan;; ADDWC 104169689Skan(define_insn "mips_addwc" 105169689Skan [(parallel 106169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 107169689Skan (unspec:SI [(match_operand:SI 1 "register_operand" "d") 108169689Skan (match_operand:SI 2 "register_operand" "d") 109169689Skan (reg:CCDSP CCDSP_CA_REGNUM)] 110169689Skan UNSPEC_ADDWC)) 111169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 112169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])] 113169689Skan "TARGET_DSP" 114169689Skan "addwc\t%0,%1,%2" 115169689Skan [(set_attr "type" "arith") 116169689Skan (set_attr "mode" "SI")]) 117169689Skan 118169689Skan;; MODSUB 119169689Skan(define_insn "mips_modsub" 120169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 121169689Skan (unspec:SI [(match_operand:SI 1 "register_operand" "d") 122169689Skan (match_operand:SI 2 "register_operand" "d")] 123169689Skan UNSPEC_MODSUB))] 124169689Skan "TARGET_DSP" 125169689Skan "modsub\t%0,%1,%2" 126169689Skan [(set_attr "type" "arith") 127169689Skan (set_attr "mode" "SI")]) 128169689Skan 129169689Skan;; RADDU* 130169689Skan(define_insn "mips_raddu_w_qb" 131169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 132169689Skan (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")] 133169689Skan UNSPEC_RADDU_W_QB))] 134169689Skan "TARGET_DSP" 135169689Skan "raddu.w.qb\t%0,%1" 136169689Skan [(set_attr "type" "arith") 137169689Skan (set_attr "mode" "SI")]) 138169689Skan 139169689Skan;; ABSQ* 140169689Skan(define_insn "mips_absq_s_<DSPQ:dspfmt2>" 141169689Skan [(parallel 142169689Skan [(set (match_operand:DSPQ 0 "register_operand" "=d") 143169689Skan (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")] 144169689Skan UNSPEC_ABSQ_S)) 145169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 146169689Skan (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])] 147169689Skan "TARGET_DSP" 148169689Skan "absq_s.<DSPQ:dspfmt2>\t%0,%1" 149169689Skan [(set_attr "type" "arith") 150169689Skan (set_attr "mode" "SI")]) 151169689Skan 152169689Skan;; PRECRQ* 153169689Skan(define_insn "mips_precrq_qb_ph" 154169689Skan [(set (match_operand:V4QI 0 "register_operand" "=d") 155169689Skan (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 156169689Skan (match_operand:V2HI 2 "register_operand" "d")] 157169689Skan UNSPEC_PRECRQ_QB_PH))] 158169689Skan "TARGET_DSP" 159169689Skan "precrq.qb.ph\t%0,%1,%2" 160169689Skan [(set_attr "type" "arith") 161169689Skan (set_attr "mode" "SI")]) 162169689Skan 163169689Skan(define_insn "mips_precrq_ph_w" 164169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 165169689Skan (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 166169689Skan (match_operand:SI 2 "register_operand" "d")] 167169689Skan UNSPEC_PRECRQ_PH_W))] 168169689Skan "TARGET_DSP" 169169689Skan "precrq.ph.w\t%0,%1,%2" 170169689Skan [(set_attr "type" "arith") 171169689Skan (set_attr "mode" "SI")]) 172169689Skan 173169689Skan(define_insn "mips_precrq_rs_ph_w" 174169689Skan [(parallel 175169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 176169689Skan (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 177169689Skan (match_operand:SI 2 "register_operand" "d")] 178169689Skan UNSPEC_PRECRQ_RS_PH_W)) 179169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 180169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] 181169689Skan UNSPEC_PRECRQ_RS_PH_W))])] 182169689Skan "TARGET_DSP" 183169689Skan "precrq_rs.ph.w\t%0,%1,%2" 184169689Skan [(set_attr "type" "arith") 185169689Skan (set_attr "mode" "SI")]) 186169689Skan 187169689Skan;; PRECRQU* 188169689Skan(define_insn "mips_precrqu_s_qb_ph" 189169689Skan [(parallel 190169689Skan [(set (match_operand:V4QI 0 "register_operand" "=d") 191169689Skan (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 192169689Skan (match_operand:V2HI 2 "register_operand" "d")] 193169689Skan UNSPEC_PRECRQU_S_QB_PH)) 194169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 195169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] 196169689Skan UNSPEC_PRECRQU_S_QB_PH))])] 197169689Skan "TARGET_DSP" 198169689Skan "precrqu_s.qb.ph\t%0,%1,%2" 199169689Skan [(set_attr "type" "arith") 200169689Skan (set_attr "mode" "SI")]) 201169689Skan 202169689Skan;; PRECEQ* 203169689Skan(define_insn "mips_preceq_w_phl" 204169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 205169689Skan (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 206169689Skan UNSPEC_PRECEQ_W_PHL))] 207169689Skan "TARGET_DSP" 208169689Skan "preceq.w.phl\t%0,%1" 209169689Skan [(set_attr "type" "arith") 210169689Skan (set_attr "mode" "SI")]) 211169689Skan 212169689Skan(define_insn "mips_preceq_w_phr" 213169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 214169689Skan (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 215169689Skan UNSPEC_PRECEQ_W_PHR))] 216169689Skan "TARGET_DSP" 217169689Skan "preceq.w.phr\t%0,%1" 218169689Skan [(set_attr "type" "arith") 219169689Skan (set_attr "mode" "SI")]) 220169689Skan 221169689Skan;; PRECEQU* 222169689Skan(define_insn "mips_precequ_ph_qbl" 223169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 224169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 225169689Skan UNSPEC_PRECEQU_PH_QBL))] 226169689Skan "TARGET_DSP" 227169689Skan "precequ.ph.qbl\t%0,%1" 228169689Skan [(set_attr "type" "arith") 229169689Skan (set_attr "mode" "SI")]) 230169689Skan 231169689Skan(define_insn "mips_precequ_ph_qbr" 232169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 233169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 234169689Skan UNSPEC_PRECEQU_PH_QBR))] 235169689Skan "TARGET_DSP" 236169689Skan "precequ.ph.qbr\t%0,%1" 237169689Skan [(set_attr "type" "arith") 238169689Skan (set_attr "mode" "SI")]) 239169689Skan 240169689Skan(define_insn "mips_precequ_ph_qbla" 241169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 242169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 243169689Skan UNSPEC_PRECEQU_PH_QBLA))] 244169689Skan "TARGET_DSP" 245169689Skan "precequ.ph.qbla\t%0,%1" 246169689Skan [(set_attr "type" "arith") 247169689Skan (set_attr "mode" "SI")]) 248169689Skan 249169689Skan(define_insn "mips_precequ_ph_qbra" 250169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 251169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 252169689Skan UNSPEC_PRECEQU_PH_QBRA))] 253169689Skan "TARGET_DSP" 254169689Skan "precequ.ph.qbra\t%0,%1" 255169689Skan [(set_attr "type" "arith") 256169689Skan (set_attr "mode" "SI")]) 257169689Skan 258169689Skan;; PRECEU* 259169689Skan(define_insn "mips_preceu_ph_qbl" 260169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 261169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 262169689Skan UNSPEC_PRECEU_PH_QBL))] 263169689Skan "TARGET_DSP" 264169689Skan "preceu.ph.qbl\t%0,%1" 265169689Skan [(set_attr "type" "arith") 266169689Skan (set_attr "mode" "SI")]) 267169689Skan 268169689Skan(define_insn "mips_preceu_ph_qbr" 269169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 270169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 271169689Skan UNSPEC_PRECEU_PH_QBR))] 272169689Skan "TARGET_DSP" 273169689Skan "preceu.ph.qbr\t%0,%1" 274169689Skan [(set_attr "type" "arith") 275169689Skan (set_attr "mode" "SI")]) 276169689Skan 277169689Skan(define_insn "mips_preceu_ph_qbla" 278169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 279169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 280169689Skan UNSPEC_PRECEU_PH_QBLA))] 281169689Skan "TARGET_DSP" 282169689Skan "preceu.ph.qbla\t%0,%1" 283169689Skan [(set_attr "type" "arith") 284169689Skan (set_attr "mode" "SI")]) 285169689Skan 286169689Skan(define_insn "mips_preceu_ph_qbra" 287169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 288169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 289169689Skan UNSPEC_PRECEU_PH_QBRA))] 290169689Skan "TARGET_DSP" 291169689Skan "preceu.ph.qbra\t%0,%1" 292169689Skan [(set_attr "type" "arith") 293169689Skan (set_attr "mode" "SI")]) 294169689Skan 295169689Skan;; Table 2-2. MIPS DSP ASE Instructions: Shift 296169689Skan;; SHLL* 297169689Skan(define_insn "mips_shll_<DSPV:dspfmt2>" 298169689Skan [(parallel 299169689Skan [(set (match_operand:DSPV 0 "register_operand" "=d,d") 300169689Skan (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d") 301169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 302169689Skan UNSPEC_SHLL)) 303169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 304169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])] 305169689Skan "TARGET_DSP" 306169689Skan{ 307169689Skan if (which_alternative == 0) 308169689Skan { 309169689Skan if (INTVAL (operands[2]) 310169689Skan & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>) 311169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>); 312169689Skan return "shll.<DSPV:dspfmt2>\t%0,%1,%2"; 313169689Skan } 314169689Skan return "shllv.<DSPV:dspfmt2>\t%0,%1,%2"; 315169689Skan} 316169689Skan [(set_attr "type" "shift") 317169689Skan (set_attr "mode" "SI")]) 318169689Skan 319169689Skan(define_insn "mips_shll_s_<DSPQ:dspfmt2>" 320169689Skan [(parallel 321169689Skan [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 322169689Skan (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 323169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 324169689Skan UNSPEC_SHLL_S)) 325169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 326169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])] 327169689Skan "TARGET_DSP" 328169689Skan{ 329169689Skan if (which_alternative == 0) 330169689Skan { 331169689Skan if (INTVAL (operands[2]) 332169689Skan & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 333169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 334169689Skan return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 335169689Skan } 336169689Skan return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 337169689Skan} 338169689Skan [(set_attr "type" "shift") 339169689Skan (set_attr "mode" "SI")]) 340169689Skan 341169689Skan;; SHRL* 342169689Skan(define_insn "mips_shrl_qb" 343169689Skan [(set (match_operand:V4QI 0 "register_operand" "=d,d") 344169689Skan (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d") 345169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 346169689Skan UNSPEC_SHRL_QB))] 347169689Skan "TARGET_DSP" 348169689Skan{ 349169689Skan if (which_alternative == 0) 350169689Skan { 351169689Skan if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7) 352169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7); 353169689Skan return "shrl.qb\t%0,%1,%2"; 354169689Skan } 355169689Skan return "shrlv.qb\t%0,%1,%2"; 356169689Skan} 357169689Skan [(set_attr "type" "shift") 358169689Skan (set_attr "mode" "SI")]) 359169689Skan 360169689Skan;; SHRA* 361169689Skan(define_insn "mips_shra_ph" 362169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d,d") 363169689Skan (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d") 364169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 365169689Skan UNSPEC_SHRA_PH))] 366169689Skan "TARGET_DSP" 367169689Skan{ 368169689Skan if (which_alternative == 0) 369169689Skan { 370169689Skan if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf) 371169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf); 372169689Skan return "shra.ph\t%0,%1,%2"; 373169689Skan } 374169689Skan return "shrav.ph\t%0,%1,%2"; 375169689Skan} 376169689Skan [(set_attr "type" "shift") 377169689Skan (set_attr "mode" "SI")]) 378169689Skan 379169689Skan(define_insn "mips_shra_r_<DSPQ:dspfmt2>" 380169689Skan [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 381169689Skan (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 382169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 383169689Skan UNSPEC_SHRA_R))] 384169689Skan "TARGET_DSP" 385169689Skan{ 386169689Skan if (which_alternative == 0) 387169689Skan { 388169689Skan if (INTVAL (operands[2]) 389169689Skan & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 390169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 391169689Skan return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 392169689Skan } 393169689Skan return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 394169689Skan} 395169689Skan [(set_attr "type" "shift") 396169689Skan (set_attr "mode" "SI")]) 397169689Skan 398169689Skan;; Table 2-3. MIPS DSP ASE Instructions: Multiply 399169689Skan;; MULEU* 400169689Skan(define_insn "mips_muleu_s_ph_qbl" 401169689Skan [(parallel 402169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 403169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 404169689Skan (match_operand:V2HI 2 "register_operand" "d")] 405169689Skan UNSPEC_MULEU_S_PH_QBL)) 406169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 407169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL)) 408169689Skan (clobber (match_scratch:DI 3 "=x"))])] 409169689Skan "TARGET_DSP" 410169689Skan "muleu_s.ph.qbl\t%0,%1,%2" 411169689Skan [(set_attr "type" "imul3") 412169689Skan (set_attr "mode" "SI")]) 413169689Skan 414169689Skan(define_insn "mips_muleu_s_ph_qbr" 415169689Skan [(parallel 416169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 417169689Skan (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 418169689Skan (match_operand:V2HI 2 "register_operand" "d")] 419169689Skan UNSPEC_MULEU_S_PH_QBR)) 420169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 421169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR)) 422169689Skan (clobber (match_scratch:DI 3 "=x"))])] 423169689Skan "TARGET_DSP" 424169689Skan "muleu_s.ph.qbr\t%0,%1,%2" 425169689Skan [(set_attr "type" "imul3") 426169689Skan (set_attr "mode" "SI")]) 427169689Skan 428169689Skan;; MULQ* 429169689Skan(define_insn "mips_mulq_rs_ph" 430169689Skan [(parallel 431169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 432169689Skan (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 433169689Skan (match_operand:V2HI 2 "register_operand" "d")] 434169689Skan UNSPEC_MULQ_RS_PH)) 435169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 436169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) 437169689Skan (clobber (match_scratch:DI 3 "=x"))])] 438169689Skan "TARGET_DSP" 439169689Skan "mulq_rs.ph\t%0,%1,%2" 440169689Skan [(set_attr "type" "imul3") 441169689Skan (set_attr "mode" "SI")]) 442169689Skan 443169689Skan;; MULEQ* 444169689Skan(define_insn "mips_muleq_s_w_phl" 445169689Skan [(parallel 446169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 447169689Skan (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 448169689Skan (match_operand:V2HI 2 "register_operand" "d")] 449169689Skan UNSPEC_MULEQ_S_W_PHL)) 450169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 451169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL)) 452169689Skan (clobber (match_scratch:DI 3 "=x"))])] 453169689Skan "TARGET_DSP" 454169689Skan "muleq_s.w.phl\t%0,%1,%2" 455169689Skan [(set_attr "type" "imul3") 456169689Skan (set_attr "mode" "SI")]) 457169689Skan 458169689Skan(define_insn "mips_muleq_s_w_phr" 459169689Skan [(parallel 460169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 461169689Skan (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 462169689Skan (match_operand:V2HI 2 "register_operand" "d")] 463169689Skan UNSPEC_MULEQ_S_W_PHR)) 464169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 465169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR)) 466169689Skan (clobber (match_scratch:DI 3 "=x"))])] 467169689Skan "TARGET_DSP" 468169689Skan "muleq_s.w.phr\t%0,%1,%2" 469169689Skan [(set_attr "type" "imul3") 470169689Skan (set_attr "mode" "SI")]) 471169689Skan 472169689Skan;; DPAU* 473169689Skan(define_insn "mips_dpau_h_qbl" 474169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 475169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 476169689Skan (match_operand:V4QI 2 "register_operand" "d") 477169689Skan (match_operand:V4QI 3 "register_operand" "d")] 478169689Skan UNSPEC_DPAU_H_QBL))] 479169689Skan "TARGET_DSP && !TARGET_64BIT" 480169689Skan "dpau.h.qbl\t%q0,%2,%3" 481169689Skan [(set_attr "type" "imadd") 482169689Skan (set_attr "mode" "SI")]) 483169689Skan 484169689Skan(define_insn "mips_dpau_h_qbr" 485169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 486169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 487169689Skan (match_operand:V4QI 2 "register_operand" "d") 488169689Skan (match_operand:V4QI 3 "register_operand" "d")] 489169689Skan UNSPEC_DPAU_H_QBR))] 490169689Skan "TARGET_DSP && !TARGET_64BIT" 491169689Skan "dpau.h.qbr\t%q0,%2,%3" 492169689Skan [(set_attr "type" "imadd") 493169689Skan (set_attr "mode" "SI")]) 494169689Skan 495169689Skan;; DPSU* 496169689Skan(define_insn "mips_dpsu_h_qbl" 497169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 498169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 499169689Skan (match_operand:V4QI 2 "register_operand" "d") 500169689Skan (match_operand:V4QI 3 "register_operand" "d")] 501169689Skan UNSPEC_DPSU_H_QBL))] 502169689Skan "TARGET_DSP && !TARGET_64BIT" 503169689Skan "dpsu.h.qbl\t%q0,%2,%3" 504169689Skan [(set_attr "type" "imadd") 505169689Skan (set_attr "mode" "SI")]) 506169689Skan 507169689Skan(define_insn "mips_dpsu_h_qbr" 508169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 509169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 510169689Skan (match_operand:V4QI 2 "register_operand" "d") 511169689Skan (match_operand:V4QI 3 "register_operand" "d")] 512169689Skan UNSPEC_DPSU_H_QBR))] 513169689Skan "TARGET_DSP && !TARGET_64BIT" 514169689Skan "dpsu.h.qbr\t%q0,%2,%3" 515169689Skan [(set_attr "type" "imadd") 516169689Skan (set_attr "mode" "SI")]) 517169689Skan 518169689Skan;; DPAQ* 519169689Skan(define_insn "mips_dpaq_s_w_ph" 520169689Skan [(parallel 521169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 522169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 523169689Skan (match_operand:V2HI 2 "register_operand" "d") 524169689Skan (match_operand:V2HI 3 "register_operand" "d")] 525169689Skan UNSPEC_DPAQ_S_W_PH)) 526169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 527169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 528169689Skan UNSPEC_DPAQ_S_W_PH))])] 529169689Skan "TARGET_DSP && !TARGET_64BIT" 530169689Skan "dpaq_s.w.ph\t%q0,%2,%3" 531169689Skan [(set_attr "type" "imadd") 532169689Skan (set_attr "mode" "SI")]) 533169689Skan 534169689Skan;; DPSQ* 535169689Skan(define_insn "mips_dpsq_s_w_ph" 536169689Skan [(parallel 537169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 538169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 539169689Skan (match_operand:V2HI 2 "register_operand" "d") 540169689Skan (match_operand:V2HI 3 "register_operand" "d")] 541169689Skan UNSPEC_DPSQ_S_W_PH)) 542169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 543169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 544169689Skan UNSPEC_DPSQ_S_W_PH))])] 545169689Skan "TARGET_DSP && !TARGET_64BIT" 546169689Skan "dpsq_s.w.ph\t%q0,%2,%3" 547169689Skan [(set_attr "type" "imadd") 548169689Skan (set_attr "mode" "SI")]) 549169689Skan 550169689Skan;; MULSAQ* 551169689Skan(define_insn "mips_mulsaq_s_w_ph" 552169689Skan [(parallel 553169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 554169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 555169689Skan (match_operand:V2HI 2 "register_operand" "d") 556169689Skan (match_operand:V2HI 3 "register_operand" "d")] 557169689Skan UNSPEC_MULSAQ_S_W_PH)) 558169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 559169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 560169689Skan UNSPEC_MULSAQ_S_W_PH))])] 561169689Skan "TARGET_DSP && !TARGET_64BIT" 562169689Skan "mulsaq_s.w.ph\t%q0,%2,%3" 563169689Skan [(set_attr "type" "imadd") 564169689Skan (set_attr "mode" "SI")]) 565169689Skan 566169689Skan;; DPAQ* 567169689Skan(define_insn "mips_dpaq_sa_l_w" 568169689Skan [(parallel 569169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 570169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 571169689Skan (match_operand:SI 2 "register_operand" "d") 572169689Skan (match_operand:SI 3 "register_operand" "d")] 573169689Skan UNSPEC_DPAQ_SA_L_W)) 574169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 575169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 576169689Skan UNSPEC_DPAQ_SA_L_W))])] 577169689Skan "TARGET_DSP && !TARGET_64BIT" 578169689Skan "dpaq_sa.l.w\t%q0,%2,%3" 579169689Skan [(set_attr "type" "imadd") 580169689Skan (set_attr "mode" "SI")]) 581169689Skan 582169689Skan;; DPSQ* 583169689Skan(define_insn "mips_dpsq_sa_l_w" 584169689Skan [(parallel 585169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 586169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 587169689Skan (match_operand:SI 2 "register_operand" "d") 588169689Skan (match_operand:SI 3 "register_operand" "d")] 589169689Skan UNSPEC_DPSQ_SA_L_W)) 590169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 591169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 592169689Skan UNSPEC_DPSQ_SA_L_W))])] 593169689Skan "TARGET_DSP && !TARGET_64BIT" 594169689Skan "dpsq_sa.l.w\t%q0,%2,%3" 595169689Skan [(set_attr "type" "imadd") 596169689Skan (set_attr "mode" "SI")]) 597169689Skan 598169689Skan;; MAQ* 599169689Skan(define_insn "mips_maq_s_w_phl" 600169689Skan [(parallel 601169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 602169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 603169689Skan (match_operand:V2HI 2 "register_operand" "d") 604169689Skan (match_operand:V2HI 3 "register_operand" "d")] 605169689Skan UNSPEC_MAQ_S_W_PHL)) 606169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 607169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 608169689Skan UNSPEC_MAQ_S_W_PHL))])] 609169689Skan "TARGET_DSP && !TARGET_64BIT" 610169689Skan "maq_s.w.phl\t%q0,%2,%3" 611169689Skan [(set_attr "type" "imadd") 612169689Skan (set_attr "mode" "SI")]) 613169689Skan 614169689Skan(define_insn "mips_maq_s_w_phr" 615169689Skan [(parallel 616169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 617169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 618169689Skan (match_operand:V2HI 2 "register_operand" "d") 619169689Skan (match_operand:V2HI 3 "register_operand" "d")] 620169689Skan UNSPEC_MAQ_S_W_PHR)) 621169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 622169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 623169689Skan UNSPEC_MAQ_S_W_PHR))])] 624169689Skan "TARGET_DSP && !TARGET_64BIT" 625169689Skan "maq_s.w.phr\t%q0,%2,%3" 626169689Skan [(set_attr "type" "imadd") 627169689Skan (set_attr "mode" "SI")]) 628169689Skan 629169689Skan;; MAQ_SA* 630169689Skan(define_insn "mips_maq_sa_w_phl" 631169689Skan [(parallel 632169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 633169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 634169689Skan (match_operand:V2HI 2 "register_operand" "d") 635169689Skan (match_operand:V2HI 3 "register_operand" "d")] 636169689Skan UNSPEC_MAQ_SA_W_PHL)) 637169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 638169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 639169689Skan UNSPEC_MAQ_SA_W_PHL))])] 640169689Skan "TARGET_DSP && !TARGET_64BIT" 641169689Skan "maq_sa.w.phl\t%q0,%2,%3" 642169689Skan [(set_attr "type" "imadd") 643169689Skan (set_attr "mode" "SI")]) 644169689Skan 645169689Skan(define_insn "mips_maq_sa_w_phr" 646169689Skan [(parallel 647169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 648169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 649169689Skan (match_operand:V2HI 2 "register_operand" "d") 650169689Skan (match_operand:V2HI 3 "register_operand" "d")] 651169689Skan UNSPEC_MAQ_SA_W_PHR)) 652169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 653169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 654169689Skan UNSPEC_MAQ_SA_W_PHR))])] 655169689Skan "TARGET_DSP && !TARGET_64BIT" 656169689Skan "maq_sa.w.phr\t%q0,%2,%3" 657169689Skan [(set_attr "type" "imadd") 658169689Skan (set_attr "mode" "SI")]) 659169689Skan 660169689Skan;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation 661169689Skan;; BITREV 662169689Skan(define_insn "mips_bitrev" 663169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 664169689Skan (unspec:SI [(match_operand:SI 1 "register_operand" "d")] 665169689Skan UNSPEC_BITREV))] 666169689Skan "TARGET_DSP" 667169689Skan "bitrev\t%0,%1" 668169689Skan [(set_attr "type" "arith") 669169689Skan (set_attr "mode" "SI")]) 670169689Skan 671169689Skan;; INSV 672169689Skan(define_insn "mips_insv" 673169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 674169689Skan (unspec:SI [(match_operand:SI 1 "register_operand" "0") 675169689Skan (match_operand:SI 2 "register_operand" "d") 676169689Skan (reg:CCDSP CCDSP_SC_REGNUM) 677169689Skan (reg:CCDSP CCDSP_PO_REGNUM)] 678169689Skan UNSPEC_INSV))] 679169689Skan "TARGET_DSP" 680169689Skan "insv\t%0,%2" 681169689Skan [(set_attr "type" "arith") 682169689Skan (set_attr "mode" "SI")]) 683169689Skan 684169689Skan;; REPL* 685169689Skan(define_insn "mips_repl_qb" 686169689Skan [(set (match_operand:V4QI 0 "register_operand" "=d,d") 687169689Skan (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")] 688169689Skan UNSPEC_REPL_QB))] 689169689Skan "TARGET_DSP" 690169689Skan{ 691169689Skan if (which_alternative == 0) 692169689Skan { 693169689Skan if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff) 694169689Skan operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); 695169689Skan return "repl.qb\t%0,%1"; 696169689Skan } 697169689Skan return "replv.qb\t%0,%1"; 698169689Skan} 699169689Skan [(set_attr "type" "arith") 700169689Skan (set_attr "mode" "SI")]) 701169689Skan 702169689Skan(define_insn "mips_repl_ph" 703169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d,d") 704169689Skan (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")] 705169689Skan UNSPEC_REPL_PH))] 706169689Skan "TARGET_DSP" 707169689Skan "@ 708169689Skan repl.ph\t%0,%1 709169689Skan replv.ph\t%0,%1" 710169689Skan [(set_attr "type" "arith") 711169689Skan (set_attr "mode" "SI")]) 712169689Skan 713169689Skan;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick 714169689Skan;; CMPU.* CMP.* 715169689Skan(define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>" 716169689Skan [(set (reg:CCDSP CCDSP_CC_REGNUM) 717169689Skan (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 718169689Skan (match_operand:DSPV 1 "register_operand" "d") 719169689Skan (reg:CCDSP CCDSP_CC_REGNUM)] 720169689Skan UNSPEC_CMP_EQ))] 721169689Skan "TARGET_DSP" 722169689Skan "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1" 723169689Skan [(set_attr "type" "arith") 724169689Skan (set_attr "mode" "SI")]) 725169689Skan 726169689Skan(define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>" 727169689Skan [(set (reg:CCDSP CCDSP_CC_REGNUM) 728169689Skan (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 729169689Skan (match_operand:DSPV 1 "register_operand" "d") 730169689Skan (reg:CCDSP CCDSP_CC_REGNUM)] 731169689Skan UNSPEC_CMP_LT))] 732169689Skan "TARGET_DSP" 733169689Skan "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1" 734169689Skan [(set_attr "type" "arith") 735169689Skan (set_attr "mode" "SI")]) 736169689Skan 737169689Skan(define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>" 738169689Skan [(set (reg:CCDSP CCDSP_CC_REGNUM) 739169689Skan (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 740169689Skan (match_operand:DSPV 1 "register_operand" "d") 741169689Skan (reg:CCDSP CCDSP_CC_REGNUM)] 742169689Skan UNSPEC_CMP_LE))] 743169689Skan "TARGET_DSP" 744169689Skan "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1" 745169689Skan [(set_attr "type" "arith") 746169689Skan (set_attr "mode" "SI")]) 747169689Skan 748169689Skan(define_insn "mips_cmpgu_eq_qb" 749169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 750169689Skan (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 751169689Skan (match_operand:V4QI 2 "register_operand" "d")] 752169689Skan UNSPEC_CMPGU_EQ_QB))] 753169689Skan "TARGET_DSP" 754169689Skan "cmpgu.eq.qb\t%0,%1,%2" 755169689Skan [(set_attr "type" "arith") 756169689Skan (set_attr "mode" "SI")]) 757169689Skan 758169689Skan(define_insn "mips_cmpgu_lt_qb" 759169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 760169689Skan (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 761169689Skan (match_operand:V4QI 2 "register_operand" "d")] 762169689Skan UNSPEC_CMPGU_LT_QB))] 763169689Skan "TARGET_DSP" 764169689Skan "cmpgu.lt.qb\t%0,%1,%2" 765169689Skan [(set_attr "type" "arith") 766169689Skan (set_attr "mode" "SI")]) 767169689Skan 768169689Skan(define_insn "mips_cmpgu_le_qb" 769169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 770169689Skan (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 771169689Skan (match_operand:V4QI 2 "register_operand" "d")] 772169689Skan UNSPEC_CMPGU_LE_QB))] 773169689Skan "TARGET_DSP" 774169689Skan "cmpgu.le.qb\t%0,%1,%2" 775169689Skan [(set_attr "type" "arith") 776169689Skan (set_attr "mode" "SI")]) 777169689Skan 778169689Skan;; PICK* 779169689Skan(define_insn "mips_pick_<DSPV:dspfmt2>" 780169689Skan [(set (match_operand:DSPV 0 "register_operand" "=d") 781169689Skan (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d") 782169689Skan (match_operand:DSPV 2 "register_operand" "d") 783169689Skan (reg:CCDSP CCDSP_CC_REGNUM)] 784169689Skan UNSPEC_PICK))] 785169689Skan "TARGET_DSP" 786169689Skan "pick.<DSPV:dspfmt2>\t%0,%1,%2" 787169689Skan [(set_attr "type" "arith") 788169689Skan (set_attr "mode" "SI")]) 789169689Skan 790169689Skan;; PACKRL* 791169689Skan(define_insn "mips_packrl_ph" 792169689Skan [(set (match_operand:V2HI 0 "register_operand" "=d") 793169689Skan (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 794169689Skan (match_operand:V2HI 2 "register_operand" "d")] 795169689Skan UNSPEC_PACKRL_PH))] 796169689Skan "TARGET_DSP" 797169689Skan "packrl.ph\t%0,%1,%2" 798169689Skan [(set_attr "type" "arith") 799169689Skan (set_attr "mode" "SI")]) 800169689Skan 801169689Skan;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access 802169689Skan;; EXTR* 803169689Skan(define_insn "mips_extr_w" 804169689Skan [(parallel 805169689Skan [(set (match_operand:SI 0 "register_operand" "=d,d") 806169689Skan (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 807169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 808169689Skan UNSPEC_EXTR_W)) 809169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 810169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])] 811169689Skan "TARGET_DSP && !TARGET_64BIT" 812169689Skan{ 813169689Skan if (which_alternative == 0) 814169689Skan { 815169689Skan if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 816169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 817169689Skan return "extr.w\t%0,%q1,%2"; 818169689Skan } 819169689Skan return "extrv.w\t%0,%q1,%2"; 820169689Skan} 821169689Skan [(set_attr "type" "mfhilo") 822169689Skan (set_attr "mode" "SI")]) 823169689Skan 824169689Skan(define_insn "mips_extr_r_w" 825169689Skan [(parallel 826169689Skan [(set (match_operand:SI 0 "register_operand" "=d,d") 827169689Skan (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 828169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 829169689Skan UNSPEC_EXTR_R_W)) 830169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 831169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])] 832169689Skan "TARGET_DSP && !TARGET_64BIT" 833169689Skan{ 834169689Skan if (which_alternative == 0) 835169689Skan { 836169689Skan if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 837169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 838169689Skan return "extr_r.w\t%0,%q1,%2"; 839169689Skan } 840169689Skan return "extrv_r.w\t%0,%q1,%2"; 841169689Skan} 842169689Skan [(set_attr "type" "mfhilo") 843169689Skan (set_attr "mode" "SI")]) 844169689Skan 845169689Skan(define_insn "mips_extr_rs_w" 846169689Skan [(parallel 847169689Skan [(set (match_operand:SI 0 "register_operand" "=d,d") 848169689Skan (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 849169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 850169689Skan UNSPEC_EXTR_RS_W)) 851169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 852169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])] 853169689Skan "TARGET_DSP && !TARGET_64BIT" 854169689Skan{ 855169689Skan if (which_alternative == 0) 856169689Skan { 857169689Skan if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 858169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 859169689Skan return "extr_rs.w\t%0,%q1,%2"; 860169689Skan } 861169689Skan return "extrv_rs.w\t%0,%q1,%2"; 862169689Skan} 863169689Skan [(set_attr "type" "mfhilo") 864169689Skan (set_attr "mode" "SI")]) 865169689Skan 866169689Skan;; EXTR*_S.H 867169689Skan(define_insn "mips_extr_s_h" 868169689Skan [(parallel 869169689Skan [(set (match_operand:SI 0 "register_operand" "=d,d") 870169689Skan (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 871169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 872169689Skan UNSPEC_EXTR_S_H)) 873169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 874169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])] 875169689Skan "TARGET_DSP && !TARGET_64BIT" 876169689Skan{ 877169689Skan if (which_alternative == 0) 878169689Skan { 879169689Skan if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 880169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 881169689Skan return "extr_s.h\t%0,%q1,%2"; 882169689Skan } 883169689Skan return "extrv_s.h\t%0,%q1,%2"; 884169689Skan} 885169689Skan [(set_attr "type" "mfhilo") 886169689Skan (set_attr "mode" "SI")]) 887169689Skan 888169689Skan;; EXTP* 889169689Skan(define_insn "mips_extp" 890169689Skan [(parallel 891169689Skan [(set (match_operand:SI 0 "register_operand" "=d,d") 892169689Skan (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 893169689Skan (match_operand:SI 2 "arith_operand" "I,d") 894169689Skan (reg:CCDSP CCDSP_PO_REGNUM)] 895169689Skan UNSPEC_EXTP)) 896169689Skan (set (reg:CCDSP CCDSP_EF_REGNUM) 897169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])] 898169689Skan "TARGET_DSP && !TARGET_64BIT" 899169689Skan{ 900169689Skan if (which_alternative == 0) 901169689Skan { 902169689Skan if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 903169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 904169689Skan return "extp\t%0,%q1,%2"; 905169689Skan } 906169689Skan return "extpv\t%0,%q1,%2"; 907169689Skan} 908169689Skan [(set_attr "type" "mfhilo") 909169689Skan (set_attr "mode" "SI")]) 910169689Skan 911169689Skan(define_insn "mips_extpdp" 912169689Skan [(parallel 913169689Skan [(set (match_operand:SI 0 "register_operand" "=d,d") 914169689Skan (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 915169689Skan (match_operand:SI 2 "arith_operand" "I,d") 916169689Skan (reg:CCDSP CCDSP_PO_REGNUM)] 917169689Skan UNSPEC_EXTPDP)) 918169689Skan (set (reg:CCDSP CCDSP_PO_REGNUM) 919169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) 920169689Skan (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP)) 921169689Skan (set (reg:CCDSP CCDSP_EF_REGNUM) 922169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])] 923169689Skan "TARGET_DSP && !TARGET_64BIT" 924169689Skan{ 925169689Skan if (which_alternative == 0) 926169689Skan { 927169689Skan if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 928169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 929169689Skan return "extpdp\t%0,%q1,%2"; 930169689Skan } 931169689Skan return "extpdpv\t%0,%q1,%2"; 932169689Skan} 933169689Skan [(set_attr "type" "mfhilo") 934169689Skan (set_attr "mode" "SI")]) 935169689Skan 936169689Skan;; SHILO* 937169689Skan(define_insn "mips_shilo" 938169689Skan [(set (match_operand:DI 0 "register_operand" "=a,a") 939169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0,0") 940169689Skan (match_operand:SI 2 "arith_operand" "I,d")] 941169689Skan UNSPEC_SHILO))] 942169689Skan "TARGET_DSP && !TARGET_64BIT" 943169689Skan{ 944169689Skan if (which_alternative == 0) 945169689Skan { 946169689Skan if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31) 947169689Skan operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 948169689Skan return "shilo\t%q0,%2"; 949169689Skan } 950169689Skan return "shilov\t%q0,%2"; 951169689Skan} 952169689Skan [(set_attr "type" "mfhilo") 953169689Skan (set_attr "mode" "SI")]) 954169689Skan 955169689Skan;; MTHLIP* 956169689Skan(define_insn "mips_mthlip" 957169689Skan [(parallel 958169689Skan [(set (match_operand:DI 0 "register_operand" "=a") 959169689Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 960169689Skan (match_operand:SI 2 "register_operand" "d") 961169689Skan (reg:CCDSP CCDSP_PO_REGNUM)] 962169689Skan UNSPEC_MTHLIP)) 963169689Skan (set (reg:CCDSP CCDSP_PO_REGNUM) 964169689Skan (unspec:CCDSP [(match_dup 1) (match_dup 2) 965169689Skan (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])] 966169689Skan "TARGET_DSP && !TARGET_64BIT" 967169689Skan "mthlip\t%2,%q0" 968169689Skan [(set_attr "type" "mfhilo") 969169689Skan (set_attr "mode" "SI")]) 970169689Skan 971169689Skan;; WRDSP 972169689Skan(define_insn "mips_wrdsp" 973169689Skan [(parallel 974169689Skan [(set (reg:CCDSP CCDSP_PO_REGNUM) 975169689Skan (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d") 976169689Skan (match_operand:SI 1 "const_uimm6_operand" "YA")] 977169689Skan UNSPEC_WRDSP)) 978169689Skan (set (reg:CCDSP CCDSP_SC_REGNUM) 979169689Skan (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 980169689Skan (set (reg:CCDSP CCDSP_CA_REGNUM) 981169689Skan (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 982169689Skan (set (reg:CCDSP CCDSP_OU_REGNUM) 983169689Skan (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 984169689Skan (set (reg:CCDSP CCDSP_CC_REGNUM) 985169689Skan (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 986169689Skan (set (reg:CCDSP CCDSP_EF_REGNUM) 987169689Skan (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])] 988169689Skan "TARGET_DSP" 989169689Skan "wrdsp\t%0,%1" 990169689Skan [(set_attr "type" "arith") 991169689Skan (set_attr "mode" "SI")]) 992169689Skan 993169689Skan;; RDDSP 994169689Skan(define_insn "mips_rddsp" 995169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 996169689Skan (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA") 997169689Skan (reg:CCDSP CCDSP_PO_REGNUM) 998169689Skan (reg:CCDSP CCDSP_SC_REGNUM) 999169689Skan (reg:CCDSP CCDSP_CA_REGNUM) 1000169689Skan (reg:CCDSP CCDSP_OU_REGNUM) 1001169689Skan (reg:CCDSP CCDSP_CC_REGNUM) 1002169689Skan (reg:CCDSP CCDSP_EF_REGNUM)] 1003169689Skan UNSPEC_RDDSP))] 1004169689Skan "TARGET_DSP" 1005169689Skan "rddsp\t%0,%1" 1006169689Skan [(set_attr "type" "arith") 1007169689Skan (set_attr "mode" "SI")]) 1008169689Skan 1009169689Skan;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load 1010169689Skan;; L*X 1011169689Skan(define_insn "mips_lbux" 1012169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 1013169689Skan (zero_extend:SI (mem:QI (plus:SI (match_operand:SI 1 1014169689Skan "register_operand" "d") 1015169689Skan (match_operand:SI 2 1016169689Skan "register_operand" "d")))))] 1017169689Skan "TARGET_DSP" 1018169689Skan "lbux\t%0,%2(%1)" 1019169689Skan [(set_attr "type" "load") 1020169689Skan (set_attr "mode" "SI") 1021169689Skan (set_attr "length" "4")]) 1022169689Skan 1023169689Skan(define_insn "mips_lhx" 1024169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 1025169689Skan (sign_extend:SI (mem:HI (plus:SI (match_operand:SI 1 1026169689Skan "register_operand" "d") 1027169689Skan (match_operand:SI 2 1028169689Skan "register_operand" "d")))))] 1029169689Skan "TARGET_DSP" 1030169689Skan "lhx\t%0,%2(%1)" 1031169689Skan [(set_attr "type" "load") 1032169689Skan (set_attr "mode" "SI") 1033169689Skan (set_attr "length" "4")]) 1034169689Skan 1035169689Skan(define_insn "mips_lwx" 1036169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 1037169689Skan (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") 1038169689Skan (match_operand:SI 2 "register_operand" "d"))))] 1039169689Skan "TARGET_DSP" 1040169689Skan "lwx\t%0,%2(%1)" 1041169689Skan [(set_attr "type" "load") 1042169689Skan (set_attr "mode" "SI") 1043169689Skan (set_attr "length" "4")]) 1044169689Skan 1045169689Skan;; Table 2-8. MIPS DSP ASE Instructions: Branch 1046169689Skan;; BPOSGE32 1047169689Skan(define_insn "mips_bposge" 1048169689Skan [(set (pc) 1049169689Skan (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM) 1050169689Skan (match_operand:SI 0 "immediate_operand" "I")) 1051169689Skan (label_ref (match_operand 1 "" "")) 1052169689Skan (pc)))] 1053169689Skan "TARGET_DSP" 1054169689Skan "%*bposge%0\t%1%/" 1055169689Skan [(set_attr "type" "branch") 1056169689Skan (set_attr "mode" "none")]) 1057169689Skan 1058