5500.md revision 169689
139287Ssos;; DFA-based pipeline description for 5500 239643Syokota(define_automaton "vr55") 3205566Sjkim(define_cpu_unit "vr55_dp0" "vr55") 439287Ssos(define_cpu_unit "vr55_dp1" "vr55") 539287Ssos(define_cpu_unit "vr55_mem" "vr55") 639287Ssos(define_cpu_unit "vr55_mac" "vr55") 739287Ssos(define_cpu_unit "vr55_fp" "vr55") 839287Ssos(define_cpu_unit "vr55_bru" "vr55") 939287Ssos 1039643Syokota;; 1139643Syokota;; The ordering of the instruction-execution-path/resource-usage 1239287Ssos;; descriptions (also known as reservation RTL) is roughly ordered 1339287Ssos;; based on the define attribute RTL for the "type" classification. 1439287Ssos;; When modifying, remember that the first test that matches is the 1539287Ssos;; reservation used! 1639643Syokota;; 1739643Syokota 1839643Syokota(define_insn_reservation "ir_vr55_unknown" 1 1939643Syokota (and (eq_attr "cpu" "r5500") 2039643Syokota (eq_attr "type" "unknown")) 2139643Syokota "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru") 2239643Syokota 2339643Syokota;; Assume prediction fails. 2439643Syokota(define_insn_reservation "ir_vr55_branch" 2 2539643Syokota (and (eq_attr "cpu" "r5500") 2639287Ssos (eq_attr "type" "branch,jump,call")) 2739287Ssos "vr55_bru") 28115703Sobrien 29115703Sobrien(define_insn_reservation "ir_vr55_load" 3 30115703Sobrien (and (eq_attr "cpu" "r5500") 3142504Syokota (eq_attr "type" "load,fpload,fpidxload")) 3266710Sjhb "vr55_mem") 3339287Ssos 3456836Speter(define_bypass 4 3539287Ssos "ir_vr55_load" 3639287Ssos "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, 37198251Sjkim ir_vr55_idiv_si,ir_vr55_idiv_di") 3839287Ssos 3939287Ssos(define_insn_reservation "ir_vr55_store" 0 40210994Sjkim (and (eq_attr "cpu" "r5500") 4142179Syokota (eq_attr "type" "store,fpstore,fpidxstore")) 4239287Ssos "vr55_mem") 43210994Sjkim 4448104Syokota;; This reservation is for conditional move based on integer 4548104Syokota;; or floating point CC. 4639287Ssos(define_insn_reservation "ir_vr55_condmove" 2 4748104Syokota (and (eq_attr "cpu" "r5500") 4848104Syokota (eq_attr "type" "condmove")) 49130312Sjhb "vr55_dp0|vr55_dp1") 5039287Ssos 5139287Ssos;; Move to/from FPU registers 52197383Sdelphij(define_insn_reservation "ir_vr55_xfer" 2 53197025Sdelphij (and (eq_attr "cpu" "r5500") 5439287Ssos (eq_attr "type" "xfer")) 5542504Syokota "vr55_dp0|vr55_dp1") 5642504Syokota 5739287Ssos(define_insn_reservation "ir_vr55_arith" 1 58198251Sjkim (and (eq_attr "cpu" "r5500") 59198251Sjkim (eq_attr "type" "arith,shift,slt,clz,const,nop,trap")) 6042504Syokota "vr55_dp0|vr55_dp1") 6142504Syokota 62197444Sjkim(define_bypass 2 63197025Sdelphij "ir_vr55_arith" 64117710Srobert "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, 65117710Srobert ir_vr55_idiv_si,ir_vr55_idiv_di") 6642504Syokota 6742611Syokota(define_insn_reservation "ir_vr55_mthilo" 1 6842504Syokota (and (eq_attr "cpu" "r5500") 6942504Syokota (eq_attr "type" "mthilo")) 7039287Ssos "vr55_mac") 7139287Ssos 7239287Ssos(define_insn_reservation "ir_vr55_mfhilo" 5 7339287Ssos (and (eq_attr "cpu" "r5500") 7439287Ssos (eq_attr "type" "mfhilo")) 7539287Ssos "vr55_mac") 7639287Ssos 7739287Ssos;; The default latency is for the GPR result of a mul. Bypasses handle the 78210994Sjkim;; latency of {mul,mult}->{mfhi,mflo}. 79210994Sjkim(define_insn_reservation "ir_vr55_imul_si" 5 80210016Sjkim (and (eq_attr "cpu" "r5500") 81210016Sjkim (and (eq_attr "type" "imul,imul3") 82210016Sjkim (eq_attr "mode" "SI"))) 83210016Sjkim "vr55_mac") 84210016Sjkim 85210016Sjkim;; The default latency is for pre-reload scheduling and handles the case 86210016Sjkim;; where a pseudo destination will be stored in a GPR (as it usually is). 87210016Sjkim;; The delay includes the latency of the dmult itself and the anticipated 8839287Ssos;; mflo or mfhi. 8939287Ssos;; 9039287Ssos;; Once the mflo or mfhi has been created, bypasses handle the latency 9139287Ssos;; between it and the dmult. 9248399Speter(define_insn_reservation "ir_vr55_imul_di" 9 9342504Syokota (and (eq_attr "cpu" "r5500") 9448399Speter (and (eq_attr "type" "imul,imul3") 9548104Syokota (eq_attr "mode" "DI"))) 9642504Syokota "vr55_mac*4") 9739287Ssos 9839287Ssos;; The default latency is as for ir_vr55_imul_si. 9939287Ssos(define_insn_reservation "ir_vr55_imadd" 5 10039287Ssos (and (eq_attr "cpu" "r5500") 10139287Ssos (eq_attr "type" "imadd")) 10239287Ssos "vr55_mac") 10339287Ssos 10439287Ssos(define_bypass 1 10539287Ssos "ir_vr55_imul_si,ir_vr55_imadd" 10639287Ssos "ir_vr55_imadd" 10739287Ssos "mips_linked_madd_p") 10839287Ssos 10939287Ssos(define_bypass 2 11039287Ssos "ir_vr55_imul_si,ir_vr55_imadd" 11139287Ssos "ir_vr55_mfhilo") 11242504Syokota 11348104Syokota(define_bypass 4 11442504Syokota "ir_vr55_imul_di" 11548104Syokota "ir_vr55_mfhilo") 11648104Syokota 11748104Syokota;; Divide algorithm is early out with best latency of 7 pcycles. 11848104Syokota;; Use worst case for scheduling purposes. 11939287Ssos(define_insn_reservation "ir_vr55_idiv_si" 42 12048104Syokota (and (eq_attr "cpu" "r5500") 12139287Ssos (and (eq_attr "type" "idiv") 12242504Syokota (eq_attr "mode" "SI"))) 12342504Syokota "vr55_mac") 12442504Syokota 12542504Syokota(define_insn_reservation "ir_vr55_idiv_di" 74 12642504Syokota (and (eq_attr "cpu" "r5500") 12742504Syokota (and (eq_attr "type" "idiv") 12842504Syokota (eq_attr "mode" "DI"))) 12942504Syokota "vr55_mac") 13042504Syokota 13142504Syokota(define_insn_reservation "ir_vr55_fadd" 4 13242504Syokota (and (eq_attr "cpu" "r5500") 13342504Syokota (eq_attr "type" "fadd")) 13442504Syokota "vr55_fp") 13542504Syokota 13642504Syokota(define_insn_reservation "ir_vr55_fmul_sf" 5 13742504Syokota (and (eq_attr "cpu" "r5500") 13842504Syokota (and (eq_attr "type" "fmul") 13942504Syokota (eq_attr "mode" "SF"))) 14048104Syokota "vr55_mac") 14142504Syokota 14248104Syokota(define_insn_reservation "ir_vr55_fmul_df" 6 14348104Syokota (and (eq_attr "cpu" "r5500") 14448104Syokota (and (eq_attr "type" "fmul") 14548104Syokota (eq_attr "mode" "DF"))) 14648104Syokota "vr55_mac") 14748104Syokota 14839287Ssos(define_insn_reservation "ir_vr55_fmadd_sf" 9 14939287Ssos (and (eq_attr "cpu" "r5500") 15039287Ssos (and (eq_attr "type" "fmadd") 15142504Syokota (eq_attr "mode" "SF"))) 15239287Ssos "vr55_mac") 15339287Ssos 15439287Ssos(define_insn_reservation "ir_vr55_fmadd_df" 10 15539287Ssos (and (eq_attr "cpu" "r5500") 15639287Ssos (and (eq_attr "type" "fmadd") 15739287Ssos (eq_attr "mode" "DF"))) 15848104Syokota "vr55_mac") 15939287Ssos 16048104Syokota(define_insn_reservation "ir_vr55_fdiv_sf" 30 16148104Syokota (and (eq_attr "cpu" "r5500") 16248104Syokota (and (eq_attr "type" "fdiv,frdiv,fsqrt") 16348104Syokota (eq_attr "mode" "SF"))) 16439287Ssos "vr55_mac") 16539287Ssos 16639287Ssos(define_insn_reservation "ir_vr55_fdiv_df" 59 16739287Ssos (and (eq_attr "cpu" "r5500") 16839858Syokota (and (eq_attr "type" "fdiv,frdiv,fsqrt") 16939858Syokota (eq_attr "mode" "DF"))) 17039858Syokota "vr55_mac") 17139858Syokota 17239287Ssos(define_insn_reservation "ir_vr55_fabs" 2 17339287Ssos (and (eq_attr "cpu" "r5500") 17439287Ssos (eq_attr "type" "fabs,fneg,fmove")) 17539287Ssos "vr55_fp") 17642504Syokota 177198251Sjkim(define_insn_reservation "ir_vr55_fcmp" 2 178209491Sjkim (and (eq_attr "cpu" "r5500") 17939287Ssos (eq_attr "type" "fcmp")) 180204265Sjkim "vr55_fp") 18145117Syokota 182204265Sjkim(define_insn_reservation "ir_vr55_fcvt_sf" 4 18339287Ssos (and (eq_attr "cpu" "r5500") 18442729Syokota (and (eq_attr "type" "fcvt") 18542729Syokota (eq_attr "mode" "SF"))) 18648104Syokota "vr55_fp") 18748104Syokota 18842729Syokota(define_insn_reservation "ir_vr55_fcvt_df" 6 18942729Syokota (and (eq_attr "cpu" "r5500") 19048104Syokota (and (eq_attr "type" "fcvt") 19148104Syokota (eq_attr "mode" "DF"))) 19239287Ssos "vr55_fp") 19339287Ssos 19439287Ssos(define_insn_reservation "ir_vr55_frsqrt_sf" 60 19539287Ssos (and (eq_attr "cpu" "r5500") 19639287Ssos (and (eq_attr "type" "frsqrt") 19739287Ssos (eq_attr "mode" "SF"))) 19839287Ssos "vr55_mac") 19939287Ssos 20039287Ssos(define_insn_reservation "ir_vr55_frsqrt_df" 118 201198419Sjkim (and (eq_attr "cpu" "r5500") 202210016Sjkim (and (eq_attr "type" "frsqrt") 203205653Sjkim (eq_attr "mode" "DF"))) 20443664Syokota "vr55_mac") 205205653Sjkim 20650446Syokota(define_insn_reservation "ir_vr55_multi" 1 20748399Speter (and (eq_attr "cpu" "r5500") 20848104Syokota (eq_attr "type" "multi")) 20948399Speter "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru") 21048104Syokota