1169689Skan;; DFA-based pipeline description for 5400
2169689Skan(define_automaton "vr54")
3169689Skan(define_cpu_unit "vr54_dp0"     "vr54")
4169689Skan(define_cpu_unit "vr54_dp1"     "vr54")
5169689Skan(define_cpu_unit "vr54_mem"     "vr54")
6169689Skan(define_cpu_unit "vr54_mac"     "vr54")
7169689Skan
8169689Skan;;
9169689Skan;; The ordering of the instruction-execution-path/resource-usage
10169689Skan;; descriptions (also known as reservation RTL) is roughly ordered
11169689Skan;; based on the define attribute RTL for the "type" classification.
12169689Skan;; When modifying, remember that the first test that matches is the
13169689Skan;; reservation used!
14169689Skan;;
15169689Skan
16169689Skan(define_insn_reservation "ir_vr54_unknown" 1
17169689Skan  (and (eq_attr "cpu" "r5400")
18169689Skan       (eq_attr "type" "unknown"))
19169689Skan  "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
20169689Skan
21169689Skan;; Assume prediction fails.
22169689Skan(define_insn_reservation "ir_vr54_branch" 3
23169689Skan  (and (eq_attr "cpu" "r5400")
24169689Skan       (eq_attr "type" "branch,jump,call"))
25169689Skan  "vr54_dp0|vr54_dp1")
26169689Skan
27169689Skan(define_insn_reservation "ir_vr54_load" 2
28169689Skan  (and (eq_attr "cpu" "r5400")
29169689Skan       (eq_attr "type" "load,fpload,fpidxload"))
30169689Skan  "vr54_mem")
31169689Skan
32169689Skan(define_insn_reservation "ir_vr54_store" 1
33169689Skan  (and (eq_attr "cpu" "r5400")
34169689Skan       (eq_attr "type" "store"))
35169689Skan  "vr54_mem")
36169689Skan
37169689Skan(define_insn_reservation "ir_vr54_fstore" 1
38169689Skan  (and (eq_attr "cpu" "r5400")
39169689Skan       (eq_attr "type" "fpstore,fpidxstore"))
40169689Skan  "vr54_mem")
41169689Skan
42169689Skan
43169689Skan;; This reservation is for conditional move based on integer
44169689Skan;; or floating point CC.
45169689Skan(define_insn_reservation "ir_vr54_condmove" 4
46169689Skan  (and (eq_attr "cpu" "r5400")
47169689Skan       (eq_attr "type" "condmove"))
48169689Skan  "vr54_dp0|vr54_dp1")
49169689Skan
50169689Skan;; Move to/from FPU registers
51169689Skan(define_insn_reservation "ir_vr54_xfer" 2
52169689Skan  (and (eq_attr "cpu" "r5400")
53169689Skan       (eq_attr "type" "xfer"))
54169689Skan  "vr54_dp0|vr54_dp1")
55169689Skan
56169689Skan(define_insn_reservation "ir_vr54_hilo" 1
57169689Skan  (and (eq_attr "cpu" "r5400")
58169689Skan       (eq_attr "type" "mthilo,mfhilo"))
59169689Skan  "vr54_dp0|vr54_dp1")
60169689Skan
61169689Skan(define_insn_reservation "ir_vr54_arith" 1
62169689Skan  (and (eq_attr "cpu" "r5400")
63169689Skan       (eq_attr "type" "arith,shift,slt,clz,const,nop,trap"))
64169689Skan  "vr54_dp0|vr54_dp1")
65169689Skan
66169689Skan(define_insn_reservation "ir_vr54_imul_si" 3
67169689Skan  (and (eq_attr "cpu" "r5400")
68169689Skan       (and (eq_attr "type" "imul,imul3")
69169689Skan            (eq_attr "mode" "SI")))
70169689Skan  "vr54_dp0|vr54_dp1")
71169689Skan
72169689Skan(define_insn_reservation "ir_vr54_imul_di" 4
73169689Skan  (and (eq_attr "cpu" "r5400")
74169689Skan       (and (eq_attr "type" "imul,imul3")
75169689Skan            (eq_attr "mode" "DI")))
76169689Skan  "vr54_dp0|vr54_dp1")
77169689Skan
78169689Skan(define_insn_reservation "ir_vr54_imadd_si" 3
79169689Skan  (and (eq_attr "cpu" "r5400")
80169689Skan       (eq_attr "type" "imul,imul3"))
81169689Skan  "vr54_mac")
82169689Skan
83169689Skan(define_insn_reservation "ir_vr54_idiv_si" 42
84169689Skan  (and (eq_attr "cpu" "r5400")
85169689Skan       (and (eq_attr "type" "idiv")
86169689Skan            (eq_attr "mode" "SI")))
87169689Skan  "vr54_dp0|vr54_dp1")
88169689Skan
89169689Skan(define_insn_reservation "ir_vr54_idiv_di" 74
90169689Skan  (and (eq_attr "cpu" "r5400")
91169689Skan       (and (eq_attr "type" "idiv")
92169689Skan            (eq_attr "mode" "DI")))
93169689Skan  "vr54_dp0|vr54_dp1")
94169689Skan
95169689Skan(define_insn_reservation "ir_vr54_fadd" 4
96169689Skan  (and (eq_attr "cpu" "r5400")
97169689Skan       (eq_attr "type" "fadd"))
98169689Skan  "vr54_dp0|vr54_dp1")
99169689Skan
100169689Skan(define_insn_reservation "ir_vr54_fmul_sf" 5
101169689Skan  (and (eq_attr "cpu" "r5400")
102169689Skan       (and (eq_attr "type" "fmul")
103169689Skan            (eq_attr "mode" "SF")))
104169689Skan  "vr54_dp0|vr54_dp1")
105169689Skan
106169689Skan(define_insn_reservation "ir_vr54_fmul_df" 6
107169689Skan  (and (eq_attr "cpu" "r5400")
108169689Skan       (and (eq_attr "type" "fmul")
109169689Skan            (eq_attr "mode" "DF")))
110169689Skan  "vr54_dp0|vr54_dp1")
111169689Skan
112169689Skan(define_insn_reservation "ir_vr54_fmadd_sf" 9
113169689Skan  (and (eq_attr "cpu" "r5400")
114169689Skan       (and (eq_attr "type" "fmadd")
115169689Skan            (eq_attr "mode" "SF")))
116169689Skan  "vr54_dp0|vr54_dp1")
117169689Skan
118169689Skan(define_insn_reservation "ir_vr54_fmadd_df" 10
119169689Skan  (and (eq_attr "cpu" "r5400")
120169689Skan       (and (eq_attr "type" "fmadd")
121169689Skan            (eq_attr "mode" "DF")))
122169689Skan  "vr54_dp0|vr54_dp1")
123169689Skan
124169689Skan(define_insn_reservation "ir_vr54_fdiv_sf" 42
125169689Skan  (and (eq_attr "cpu" "r5400")
126169689Skan       (and (eq_attr "type" "fdiv,frdiv,fsqrt")
127169689Skan            (eq_attr "mode" "SF")))
128169689Skan  "vr54_dp0|vr54_dp1")
129169689Skan
130169689Skan(define_insn_reservation "ir_vr54_fdiv_df" 72
131169689Skan  (and (eq_attr "cpu" "r5400")
132169689Skan       (and (eq_attr "type" "fdiv,frdiv,fsqrt")
133169689Skan            (eq_attr "mode" "DF")))
134169689Skan  "vr54_dp0|vr54_dp1")
135169689Skan
136169689Skan(define_insn_reservation "ir_vr54_fabs" 2
137169689Skan  (and (eq_attr "cpu" "r5400")
138169689Skan       (eq_attr "type" "fabs,fneg,fmove"))
139169689Skan  "vr54_dp0|vr54_dp1")
140169689Skan
141169689Skan(define_insn_reservation "ir_vr54_fcmp" 2
142169689Skan  (and (eq_attr "cpu" "r5400")
143169689Skan       (eq_attr "type" "fcmp"))
144169689Skan  "vr54_dp0|vr54_dp1")
145169689Skan
146169689Skan(define_insn_reservation "ir_vr54_fcvt" 6
147169689Skan  (and (eq_attr "cpu" "r5400")
148169689Skan       (eq_attr "type" "fcvt"))
149169689Skan  "vr54_dp0|vr54_dp1")
150169689Skan
151169689Skan(define_insn_reservation "ir_vr54_frsqrt_sf" 61
152169689Skan  (and (eq_attr "cpu" "r5400")
153169689Skan       (and (eq_attr "type" "frsqrt")
154169689Skan            (eq_attr "mode" "SF")))
155169689Skan  "vr54_dp0|vr54_dp1")
156169689Skan
157169689Skan(define_insn_reservation "ir_vr54_frsqrt_df" 121
158169689Skan  (and (eq_attr "cpu" "r5400")
159169689Skan       (and (eq_attr "type" "frsqrt")
160169689Skan            (eq_attr "mode" "DF")))
161169689Skan  "vr54_dp0|vr54_dp1")
162169689Skan
163169689Skan(define_insn_reservation "ir_vr54_multi" 1
164169689Skan  (and (eq_attr "cpu" "r5400")
165169689Skan       (eq_attr "type" "multi"))
166169689Skan  "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
167