1169689Skan;; DFA-based pipeline descriptions for MIPS Technologies 24K core.
2169689Skan;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com)
3169689Skan;;   and David Ung (davidu@mips.com)
4169689Skan;;
5169689Skan;; The 24K is a single-issue processor with a half-clocked fpu.
6169689Skan;; The 24Kx is 24k with 1:1 clocked fpu.
7169689Skan;;
8169689Skan;; References:
9169689Skan;;   "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
10169689Skan;;
11169689Skan;; Copyright (C) 2005 Free Software Foundation, Inc.
12169689Skan;;
13169689Skan;; This file is part of GCC.
14169689Skan;;
15169689Skan;; GCC is free software; you can redistribute it and/or modify it
16169689Skan;; under the terms of the GNU General Public License as published
17169689Skan;; by the Free Software Foundation; either version 2, or (at your
18169689Skan;; option) any later version.
19169689Skan
20169689Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT
21169689Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
22169689Skan;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
23169689Skan;; License for more details.
24169689Skan
25169689Skan;; You should have received a copy of the GNU General Public License
26169689Skan;; along with GCC; see the file COPYING.  If not, write to the
27169689Skan;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
28169689Skan;; MA 02110-1301, USA.
29169689Skan
30169689Skan(define_automaton "r24k_cpu, r24k_mdu, r24k_fpu")
31169689Skan
32169689Skan;; Integer execution unit.
33169689Skan(define_cpu_unit "r24k_iss"		"r24k_cpu")
34169689Skan(define_cpu_unit "r24k_ixu_arith"	"r24k_cpu")
35169689Skan(define_cpu_unit "r24k_mul3a"	        "r24k_mdu")
36169689Skan(define_cpu_unit "r24k_mul3b"	        "r24k_mdu")
37169689Skan(define_cpu_unit "r24k_mul3c"	        "r24k_mdu")
38169689Skan
39169689Skan;; --------------------------------------------------------------
40169689Skan;; Producers
41169689Skan;; --------------------------------------------------------------
42169689Skan
43169689Skan;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
44169689Skan(define_insn_reservation "r24k_int_load" 2
45169689Skan  (and (eq_attr "cpu" "24k,24kx")
46169689Skan       (eq_attr "type" "load"))
47169689Skan  "r24k_iss+r24k_ixu_arith")
48169689Skan
49169689Skan
50169689Skan;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz,
51169689Skan;;    ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll,
52169689Skan;;    sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
53169689Skan;;    xor, xori
54169689Skan;; (movn/movz is not matched, we'll need to split condmov to
55169689Skan;;  differentiate between integer/float moves)
56169689Skan(define_insn_reservation "r24k_int_arith" 1
57169689Skan  (and (eq_attr "cpu" "24k,24kx")
58169689Skan       (eq_attr "type" "arith,const,nop,shift,slt"))
59169689Skan  "r24k_iss+r24k_ixu_arith")
60169689Skan
61169689Skan
62169689Skan;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx
63169689Skan;; 3a. jr/jalr consumer
64169689Skan(define_insn_reservation "r24k_int_jump" 1
65169689Skan  (and (eq_attr "cpu" "24k,24kx")
66169689Skan       (eq_attr "type" "call,jump"))
67169689Skan  "r24k_iss+r24k_ixu_arith")
68169689Skan
69169689Skan;; 3b. branch consumer
70169689Skan(define_insn_reservation "r24k_int_branch" 1
71169689Skan  (and (eq_attr "cpu" "24k,24kx")
72169689Skan       (eq_attr "type" "branch"))
73169689Skan  "r24k_iss+r24k_ixu_arith")
74169689Skan
75169689Skan
76169689Skan;; 4. MDU: fully pipelined multiplier
77169689Skan;; mult - delivers result to hi/lo in 1 cycle (pipelined)
78169689Skan(define_insn_reservation "r24k_int_mult" 1
79169689Skan  (and (eq_attr "cpu" "24k,24kx")
80169689Skan       (eq_attr "type" "imul"))
81169689Skan  "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
82169689Skan
83169689Skan;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined)
84169689Skan(define_insn_reservation "r24k_int_madd" 1
85169689Skan  (and (eq_attr "cpu" "24k,24kx")
86169689Skan       (eq_attr "type" "imadd"))
87169689Skan  "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
88169689Skan
89169689Skan;; mul - delivers result to gpr in 5 cycles
90169689Skan(define_insn_reservation "r24k_int_mul3" 5
91169689Skan  (and (eq_attr "cpu" "24k,24kx")
92169689Skan       (eq_attr "type" "imul3"))
93169689Skan  "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
94169689Skan
95169689Skan;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
96169689Skan(define_insn_reservation "r24k_int_mfhilo" 5
97169689Skan  (and (eq_attr "cpu" "24k,24kx")
98169689Skan       (eq_attr "type" "mfhilo"))
99169689Skan  "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
100169689Skan
101169689Skan;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
102169689Skan(define_insn_reservation "r24k_int_mthilo" 1
103169689Skan  (and (eq_attr "cpu" "24k,24kx")
104169689Skan       (eq_attr "type" "mthilo"))
105169689Skan  "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
106169689Skan
107169689Skan;; div - default to 36 cycles for 32bit operands.  Faster for 24bit, 16bit and
108169689Skan;; 8bit, but is tricky to identify.
109169689Skan(define_insn_reservation "r24k_int_div" 36
110169689Skan  (and (eq_attr "cpu" "24k,24kx")
111169689Skan       (eq_attr "type" "idiv"))
112169689Skan  "r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36")
113169689Skan
114169689Skan
115169689Skan;; 5. Cop: cfc1, di, ei, mfc0, mtc0
116169689Skan;; (Disabled until we add proper cop0 support)
117169689Skan;;(define_insn_reservation "r24k_int_cop" 3
118169689Skan;;  (and (eq_attr "cpu" "24k,24kx")
119169689Skan;;       (eq_attr "type" "cop0"))
120169689Skan;;  "r24k_iss+r24k_ixu_arith")
121169689Skan
122169689Skan
123169689Skan;; 6. Store
124169689Skan(define_insn_reservation "r24k_int_store" 1
125169689Skan  (and (eq_attr "cpu" "24k,24kx")
126169689Skan       (and (eq_attr "type" "store")
127169689Skan	    (eq_attr "mode" "!unknown")))
128169689Skan  "r24k_iss+r24k_ixu_arith")
129169689Skan
130169689Skan;; 6.1 Special case - matches the cprestore pattern which don't set the mode
131169689Skan;;     attrib. This avoids being set as r24k_int_store and have it checked
132169689Skan;;     against store_data_bypass_p, which would then fail because cprestore
133169689Skan;;     does not have a normal SET pattern.
134169689Skan(define_insn_reservation "r24k_unknown_store" 1
135169689Skan  (and (eq_attr "cpu" "24k,24kx")
136169689Skan       (and (eq_attr "type" "store")
137169689Skan	    (eq_attr "mode" "unknown")))
138169689Skan  "r24k_iss+r24k_ixu_arith")
139169689Skan
140169689Skan
141169689Skan;; 7. Multiple instructions
142169689Skan(define_insn_reservation "r24k_int_multi" 1
143169689Skan  (and (eq_attr "cpu" "24k,24kx")
144169689Skan       (eq_attr "type" "multi"))
145169689Skan  "r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)")
146169689Skan
147169689Skan
148169689Skan;; 8. Unknowns - Currently these include blockage, consttable and alignment
149169689Skan;;    rtls. They do not really affect scheduling latency, (blockage affects
150169689Skan;;    scheduling via log links, but not used here).
151169689Skan(define_insn_reservation "r24k_int_unknown" 0
152169689Skan  (and (eq_attr "cpu" "24k,24kx")
153169689Skan       (eq_attr "type" "unknown"))
154169689Skan  "r24k_iss")
155169689Skan
156169689Skan
157169689Skan;; 9. Prefetch
158169689Skan(define_insn_reservation "r24k_int_prefetch" 1
159169689Skan  (and (eq_attr "cpu" "24k,24kx")
160169689Skan       (eq_attr "type" "prefetch,prefetchx"))
161169689Skan  "r24k_iss+r24k_ixu_arith")
162169689Skan
163169689Skan
164169689Skan;; --------------------------------------------------------------
165169689Skan;; Bypass to Consumer
166169689Skan;; --------------------------------------------------------------
167169689Skan
168169689Skan;; load->next use :  2 cycles (Default)
169169689Skan;; load->load base:  3 cycles
170169689Skan;; load->store base: 3 cycles
171169689Skan;; load->prefetch:   3 cycles
172169689Skan(define_bypass 3 "r24k_int_load" "r24k_int_load")
173169689Skan(define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p")
174169689Skan(define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
175169689Skan
176169689Skan;; arith->next use :  1 cycles (Default)
177169689Skan;; arith->load base:  2 cycles
178169689Skan;; arith->store base: 2 cycles
179169689Skan;; arith->prefetch:   2 cycles
180169689Skan(define_bypass 2 "r24k_int_arith" "r24k_int_load")
181169689Skan(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p")
182169689Skan(define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
183169689Skan
184169689Skan;; mul3->next use : 5 cycles (default)
185169689Skan;; mul3->l/s base : 6 cycles
186169689Skan;; mul3->prefetch : 6 cycles
187169689Skan(define_bypass 6 "r24k_int_mul3" "r24k_int_load")
188169689Skan(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
189169689Skan(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
190169689Skan
191169689Skan;; mfhilo->next use  : 5 cycles (default)
192169689Skan;; mfhilo->l/s base  : 6 cycles
193169689Skan;; mfhilo->prefetch  : 6 cycles
194169689Skan;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
195169689Skan(define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
196169689Skan(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p")
197169689Skan(define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
198169689Skan(define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
199169689Skan
200169689Skan;; cop->next use : 3 cycles (Default)
201169689Skan;; cop->l/s base : 4 cycles
202169689Skan;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
203169689Skan;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p")
204169689Skan
205169689Skan;; multi->next use : 1 cycles (Default)
206169689Skan;; multi->l/s base : 2 cycles
207169689Skan;; multi->prefetch : 2 cycles
208169689Skan(define_bypass 2 "r24k_int_multi" "r24k_int_load")
209169689Skan(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p")
210169689Skan(define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
211169689Skan
212169689Skan
213169689Skan;; --------------------------------------------------------------
214169689Skan;; Floating Point Instructions
215169689Skan;; --------------------------------------------------------------
216169689Skan
217169689Skan(define_cpu_unit "r24k_fpu_arith" "r24k_fpu")
218169689Skan
219169689Skan;; The 24k is a single issue cpu, and the fpu runs at half clock speed,
220169689Skan;; so each fpu instruction ties up the shared instruction scheduler for
221169689Skan;; 1 cycle, and the fpu scheduler for 2 cycles.
222169689Skan;;
223169689Skan;; These timings are therefore twice the values in the 24K manual,
224169689Skan;; which are quoted in fpu clocks.
225169689Skan;;
226169689Skan;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
227169689Skan;; the unscaled timings
228169689Skan
229169689Skan(define_reservation "r24k_fpu_iss"	"r24k_iss+(r24k_fpu_arith*2)")
230169689Skan
231169689Skan;; fadd, fabs, fneg
232169689Skan(define_insn_reservation "r24k_fadd" 8
233169689Skan  (and (eq_attr "cpu" "24k")
234169689Skan       (eq_attr "type" "fadd,fabs,fneg"))
235169689Skan  "r24k_fpu_iss")
236169689Skan
237169689Skan;; fmove, fcmove
238169689Skan(define_insn_reservation "r24k_fmove" 8
239169689Skan  (and (eq_attr "cpu" "24k")
240169689Skan       (eq_attr "type" "fmove,condmove"))
241169689Skan  "r24k_fpu_iss")
242169689Skan
243169689Skan;; fload
244169689Skan(define_insn_reservation "r24k_fload" 6
245169689Skan  (and (eq_attr "cpu" "24k")
246169689Skan       (eq_attr "type" "fpload,fpidxload"))
247169689Skan  "r24k_fpu_iss")
248169689Skan
249169689Skan;; fstore
250169689Skan(define_insn_reservation "r24k_fstore" 2
251169689Skan  (and (eq_attr "cpu" "24k")
252169689Skan       (eq_attr "type" "fpstore"))
253169689Skan  "r24k_fpu_iss")
254169689Skan
255169689Skan;; fmul, fmadd
256169689Skan(define_insn_reservation "r24k_fmul_sf" 8
257169689Skan  (and (eq_attr "cpu" "24k")
258169689Skan       (and (eq_attr "type" "fmul,fmadd")
259169689Skan	    (eq_attr "mode" "SF")))
260169689Skan  "r24k_fpu_iss")
261169689Skan
262169689Skan(define_insn_reservation "r24k_fmul_df" 10
263169689Skan  (and (eq_attr "cpu" "24k")
264169689Skan       (and (eq_attr "type" "fmul,fmadd")
265169689Skan	    (eq_attr "mode" "DF")))
266169689Skan  "r24k_fpu_iss,(r24k_fpu_arith*2)")
267169689Skan
268169689Skan
269169689Skan;; fdiv, fsqrt, frsqrt
270169689Skan(define_insn_reservation "r24k_fdiv_sf" 34
271169689Skan  (and (eq_attr "cpu" "24k")
272169689Skan       (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
273169689Skan	    (eq_attr "mode" "SF")))
274169689Skan  "r24k_fpu_iss,(r24k_fpu_arith*26)")
275169689Skan
276169689Skan(define_insn_reservation "r24k_fdiv_df" 64
277169689Skan  (and (eq_attr "cpu" "24k")
278169689Skan       (and (eq_attr "type" "fdiv,fsqrt")
279169689Skan	    (eq_attr "mode" "DF")))
280169689Skan  "r24k_fpu_iss,(r24k_fpu_arith*56)")
281169689Skan
282169689Skan;; frsqrt
283169689Skan(define_insn_reservation "r24k_frsqrt_df" 70
284169689Skan  (and (eq_attr "cpu" "24k")
285169689Skan       (and (eq_attr "type" "frsqrt")
286169689Skan	    (eq_attr "mode" "DF")))
287169689Skan  "r24k_fpu_iss,(r24k_fpu_arith*60)")
288169689Skan
289169689Skan;; fcmp
290169689Skan(define_insn_reservation "r24k_fcmp" 4
291169689Skan  (and (eq_attr "cpu" "24k")
292169689Skan       (eq_attr "type" "fcmp"))
293169689Skan  "r24k_fpu_iss")
294169689Skan
295169689Skan;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
296169689Skan(define_bypass 2 "r24k_fcmp" "r24k_fmove")
297169689Skan
298169689Skan;; fcvt (cvt.d.s, cvt.[sd].[wl])
299169689Skan(define_insn_reservation "r24k_fcvt_i2f_s2d" 8
300169689Skan  (and (eq_attr "cpu" "24k")
301169689Skan       (and (eq_attr "type" "fcvt")
302169689Skan	    (eq_attr "cnv_mode" "I2S,I2D,S2D")))
303169689Skan  "r24k_fpu_iss")
304169689Skan
305169689Skan;; fcvt (cvt.s.d)
306169689Skan(define_insn_reservation "r24k_fcvt_s2d" 12
307169689Skan  (and (eq_attr "cpu" "24k")
308169689Skan       (and (eq_attr "type" "fcvt")
309169689Skan	    (eq_attr "cnv_mode" "D2S")))
310169689Skan  "r24k_fpu_iss")
311169689Skan
312169689Skan;; fcvt (cvt.[wl].[sd], etc)
313169689Skan(define_insn_reservation "r24k_fcvt_f2i" 10
314169689Skan  (and (eq_attr "cpu" "24k")
315169689Skan       (and (eq_attr "type" "fcvt")
316169689Skan	    (eq_attr "cnv_mode" "S2I,D2I")))
317169689Skan  "r24k_fpu_iss")
318169689Skan
319169689Skan;; fxfer (mfc1, mfhc1, mtc1, mthc1)
320169689Skan(define_insn_reservation "r24k_fxfer" 4
321169689Skan  (and (eq_attr "cpu" "24k")
322169689Skan       (eq_attr "type" "xfer"))
323169689Skan  "r24k_fpu_iss")
324169689Skan
325169689Skan;; --------------------------------------------------------------
326169689Skan;; Bypass to Consumer
327169689Skan;; --------------------------------------------------------------
328169689Skan;; r24k_fcvt_f2i->l/s base : 11 cycles
329169689Skan;; r24k_fcvt_f2i->prefetch : 11 cycles
330169689Skan(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_load")
331169689Skan(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
332169689Skan(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_prefetch")
333169689Skan
334169689Skan;; r24k_fxfer->l/s base : 5 cycles
335169689Skan;; r24k_fxfer->prefetch : 5 cycles
336169689Skan(define_bypass 5 "r24k_fxfer" "r24k_int_load")
337169689Skan(define_bypass 5 "r24k_fxfer" "r24k_int_store" "!store_data_bypass_p")
338169689Skan(define_bypass 5 "r24k_fxfer" "r24k_int_prefetch")
339169689Skan
340169689Skan;; --------------------------------------------------------------
341169689Skan;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use
342169689Skan;; the unscaled timings
343169689Skan;; --------------------------------------------------------------
344169689Skan
345169689Skan(define_reservation "r24kx_fpu_iss"	"r24k_iss+r24k_fpu_arith")
346169689Skan
347169689Skan;; fadd, fabs, fneg
348169689Skan(define_insn_reservation "r24kx_fadd" 4
349169689Skan  (and (eq_attr "cpu" "24kx")
350169689Skan       (eq_attr "type" "fadd,fabs,fneg"))
351169689Skan  "r24kx_fpu_iss")
352169689Skan
353169689Skan;; fmove, fcmove
354169689Skan(define_insn_reservation "r24kx_fmove" 4
355169689Skan  (and (eq_attr "cpu" "24kx")
356169689Skan       (eq_attr "type" "fmove,condmove"))
357169689Skan  "r24kx_fpu_iss")
358169689Skan
359169689Skan;; fload
360169689Skan(define_insn_reservation "r24kx_fload" 3
361169689Skan  (and (eq_attr "cpu" "24kx")
362169689Skan       (eq_attr "type" "fpload,fpidxload"))
363169689Skan  "r24kx_fpu_iss")
364169689Skan
365169689Skan;; fstore
366169689Skan(define_insn_reservation "r24kx_fstore" 1
367169689Skan  (and (eq_attr "cpu" "24kx")
368169689Skan       (eq_attr "type" "fpstore"))
369169689Skan  "r24kx_fpu_iss")
370169689Skan
371169689Skan;; fmul, fmadd
372169689Skan(define_insn_reservation "r24kx_fmul_sf" 4
373169689Skan  (and (eq_attr "cpu" "24kx")
374169689Skan       (and (eq_attr "type" "fmul,fmadd")
375169689Skan	    (eq_attr "mode" "SF")))
376169689Skan  "r24kx_fpu_iss")
377169689Skan
378169689Skan(define_insn_reservation "r24kx_fmul_df" 5
379169689Skan  (and (eq_attr "cpu" "24kx")
380169689Skan       (and (eq_attr "type" "fmul,fmadd")
381169689Skan	    (eq_attr "mode" "DF")))
382169689Skan  "r24kx_fpu_iss,r24k_fpu_arith")
383169689Skan
384169689Skan
385169689Skan;; fdiv, fsqrt, frsqrt
386169689Skan(define_insn_reservation "r24kx_fdiv_sf" 17
387169689Skan  (and (eq_attr "cpu" "24kx")
388169689Skan       (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
389169689Skan	    (eq_attr "mode" "SF")))
390169689Skan  "r24kx_fpu_iss,(r24k_fpu_arith*13)")
391169689Skan
392169689Skan(define_insn_reservation "r24kx_fdiv_df" 32
393169689Skan  (and (eq_attr "cpu" "24kx")
394169689Skan       (and (eq_attr "type" "fdiv,fsqrt")
395169689Skan	    (eq_attr "mode" "DF")))
396169689Skan  "r24kx_fpu_iss,(r24k_fpu_arith*28)")
397169689Skan
398169689Skan;; frsqrt
399169689Skan(define_insn_reservation "r24kx_frsqrt_df" 35
400169689Skan  (and (eq_attr "cpu" "24kx")
401169689Skan       (and (eq_attr "type" "frsqrt")
402169689Skan	    (eq_attr "mode" "DF")))
403169689Skan  "r24kx_fpu_iss,(r24k_fpu_arith*30)")
404169689Skan
405169689Skan;; fcmp
406169689Skan(define_insn_reservation "r24kx_fcmp" 2
407169689Skan  (and (eq_attr "cpu" "24kx")
408169689Skan       (eq_attr "type" "fcmp"))
409169689Skan  "r24kx_fpu_iss")
410169689Skan
411169689Skan;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition)
412169689Skan(define_bypass 1 "r24kx_fcmp" "r24kx_fmove")
413169689Skan
414169689Skan;; fcvt (cvt.d.s, cvt.[sd].[wl])
415169689Skan(define_insn_reservation "r24kx_fcvt_i2f_s2d" 4
416169689Skan  (and (eq_attr "cpu" "24kx")
417169689Skan       (and (eq_attr "type" "fcvt")
418169689Skan	    (eq_attr "cnv_mode" "I2S,I2D,S2D")))
419169689Skan  "r24kx_fpu_iss")
420169689Skan
421169689Skan;; fcvt (cvt.s.d)
422169689Skan(define_insn_reservation "r24kx_fcvt_s2d" 6
423169689Skan  (and (eq_attr "cpu" "24kx")
424169689Skan       (and (eq_attr "type" "fcvt")
425169689Skan	    (eq_attr "cnv_mode" "D2S")))
426169689Skan  "r24kx_fpu_iss")
427169689Skan
428169689Skan;; fcvt (cvt.[wl].[sd], etc)
429169689Skan(define_insn_reservation "r24kx_fcvt_f2i" 5
430169689Skan  (and (eq_attr "cpu" "24kx")
431169689Skan       (and (eq_attr "type" "fcvt")
432169689Skan	    (eq_attr "cnv_mode" "S2I,D2I")))
433169689Skan  "r24kx_fpu_iss")
434169689Skan
435169689Skan;; fxfer (mfc1, mfhc1, mtc1, mthc1)
436169689Skan(define_insn_reservation "r24kx_fxfer" 2
437169689Skan  (and (eq_attr "cpu" "24kx")
438169689Skan       (eq_attr "type" "xfer"))
439169689Skan  "r24kx_fpu_iss")
440169689Skan
441169689Skan;; --------------------------------------------------------------
442169689Skan;; Bypass to Consumer
443169689Skan;; --------------------------------------------------------------
444169689Skan;; r24kx_fcvt_f2i->l/s base : 6 cycles
445169689Skan;; r24kx_fcvt_f2i->prefetch : 6 cycles
446169689Skan(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_load")
447169689Skan(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
448169689Skan(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_prefetch")
449169689Skan
450169689Skan;; r24kx_fxfer->l/s base : 3 cycles
451169689Skan;; r24kx_fxfer->prefetch : 3 cycles
452169689Skan(define_bypass 3 "r24kx_fxfer" "r24k_int_load")
453169689Skan(define_bypass 3 "r24kx_fxfer" "r24k_int_store" "!store_data_bypass_p")
454169689Skan(define_bypass 3 "r24kx_fxfer" "r24k_int_prefetch")
455169689Skan
456