i386.h revision 96294
1/* Definitions of target machine for GNU compiler for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002 Free Software Foundation, Inc. 4 5This file is part of GNU CC. 6 7GNU CC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GNU CC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GNU CC; see the file COPYING. If not, write to 19the Free Software Foundation, 59 Temple Place - Suite 330, 20Boston, MA 02111-1307, USA. */ 21 22/* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37 38/* $FreeBSD: head/contrib/gcc/config/i386/i386.h 96294 2002-05-09 22:44:32Z obrien $ */ 39 40 41/* Stubs for half-pic support if not OSF/1 reference platform. */ 42 43#ifndef HALF_PIC_P 44#define HALF_PIC_P() 0 45#define HALF_PIC_NUMBER_PTRS 0 46#define HALF_PIC_NUMBER_REFS 0 47#define HALF_PIC_ENCODE(DECL) 48#define HALF_PIC_DECLARE(NAME) 49#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it") 50#define HALF_PIC_ADDRESS_P(X) 0 51#define HALF_PIC_PTR(X) (X) 52#define HALF_PIC_FINISH(STREAM) 53#endif 54 55/* Define the specific costs for a given cpu */ 56 57struct processor_costs { 58 const int add; /* cost of an add instruction */ 59 const int lea; /* cost of a lea instruction */ 60 const int shift_var; /* variable shift costs */ 61 const int shift_const; /* constant shift costs */ 62 const int mult_init; /* cost of starting a multiply */ 63 const int mult_bit; /* cost of multiply per each bit set */ 64 const int divide; /* cost of a divide/mod */ 65 int movsx; /* The cost of movsx operation. */ 66 int movzx; /* The cost of movzx operation. */ 67 const int large_insn; /* insns larger than this cost more */ 68 const int move_ratio; /* The threshold of number of scalar 69 memory-to-memory move insns. */ 70 const int movzbl_load; /* cost of loading using movzbl */ 71 const int int_load[3]; /* cost of loading integer registers 72 in QImode, HImode and SImode relative 73 to reg-reg move (2). */ 74 const int int_store[3]; /* cost of storing integer register 75 in QImode, HImode and SImode */ 76 const int fp_move; /* cost of reg,reg fld/fst */ 77 const int fp_load[3]; /* cost of loading FP register 78 in SFmode, DFmode and XFmode */ 79 const int fp_store[3]; /* cost of storing FP register 80 in SFmode, DFmode and XFmode */ 81 const int mmx_move; /* cost of moving MMX register. */ 82 const int mmx_load[2]; /* cost of loading MMX register 83 in SImode and DImode */ 84 const int mmx_store[2]; /* cost of storing MMX register 85 in SImode and DImode */ 86 const int sse_move; /* cost of moving SSE register. */ 87 const int sse_load[3]; /* cost of loading SSE register 88 in SImode, DImode and TImode*/ 89 const int sse_store[3]; /* cost of storing SSE register 90 in SImode, DImode and TImode*/ 91 const int mmxsse_to_integer; /* cost of moving mmxsse register to 92 integer and vice versa. */ 93 const int prefetch_block; /* bytes moved to cache for prefetch. */ 94 const int simultaneous_prefetches; /* number of parallel prefetch 95 operations. */ 96}; 97 98extern const struct processor_costs *ix86_cost; 99 100/* Run-time compilation parameters selecting different hardware subsets. */ 101 102extern int target_flags; 103 104/* Macros used in the machine description to test the flags. */ 105 106/* configure can arrange to make this 2, to force a 486. */ 107 108#ifndef TARGET_CPU_DEFAULT 109#define TARGET_CPU_DEFAULT 0 110#endif 111 112/* Masks for the -m switches */ 113#define MASK_80387 0x00000001 /* Hardware floating point */ 114#define MASK_RTD 0x00000002 /* Use ret that pops args */ 115#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ 116#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ 117#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ 118#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ 119#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ 120#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ 121#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ 122#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ 123#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ 124#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ 125#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ 126#define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000 127#define MASK_MMX 0x00004000 /* Support MMX regs/builtins */ 128#define MASK_MMX_SET 0x00008000 129#define MASK_SSE 0x00010000 /* Support SSE regs/builtins */ 130#define MASK_SSE_SET 0x00020000 131#define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */ 132#define MASK_SSE2_SET 0x00080000 133#define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */ 134#define MASK_3DNOW_SET 0x00200000 135#define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */ 136#define MASK_3DNOW_A_SET 0x00800000 137#define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */ 138#define MASK_64BIT 0x02000000 /* Produce 64bit code */ 139/* ... overlap with subtarget options starts by 0x04000000. */ 140#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ 141 142/* Use the floating point instructions */ 143#define TARGET_80387 (target_flags & MASK_80387) 144 145/* Compile using ret insn that pops args. 146 This will not work unless you use prototypes at least 147 for all functions that can take varying numbers of args. */ 148#define TARGET_RTD (target_flags & MASK_RTD) 149 150/* Align doubles to a two word boundary. This breaks compatibility with 151 the published ABI's for structures containing doubles, but produces 152 faster code on the pentium. */ 153#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) 154 155/* Use push instructions to save outgoing args. */ 156#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) 157 158/* Accumulate stack adjustments to prologue/epilogue. */ 159#define TARGET_ACCUMULATE_OUTGOING_ARGS \ 160 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) 161 162/* Put uninitialized locals into bss, not data. 163 Meaningful only on svr3. */ 164#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) 165 166/* Use IEEE floating point comparisons. These handle correctly the cases 167 where the result of a comparison is unordered. Normally SIGFPE is 168 generated in such cases, in which case this isn't needed. */ 169#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) 170 171/* Functions that return a floating point value may return that value 172 in the 387 FPU or in 386 integer registers. If set, this flag causes 173 the 387 to be used, which is compatible with most calling conventions. */ 174#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) 175 176/* Long double is 128bit instead of 96bit, even when only 80bits are used. 177 This mode wastes cache, but avoid misaligned data accesses and simplifies 178 address calculations. */ 179#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) 180 181/* Disable generation of FP sin, cos and sqrt operations for 387. 182 This is because FreeBSD lacks these in the math-emulator-code */ 183#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) 184 185/* Don't create frame pointers for leaf functions */ 186#define TARGET_OMIT_LEAF_FRAME_POINTER \ 187 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) 188 189/* Debug GO_IF_LEGITIMATE_ADDRESS */ 190#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) 191 192/* Debug FUNCTION_ARG macros */ 193#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) 194 195/* 64bit Sledgehammer mode */ 196#ifdef TARGET_BI_ARCH 197#define TARGET_64BIT (target_flags & MASK_64BIT) 198#else 199#ifdef TARGET_64BIT_DEFAULT 200#define TARGET_64BIT 1 201#else 202#define TARGET_64BIT 0 203#endif 204#endif 205 206#define TARGET_386 (ix86_cpu == PROCESSOR_I386) 207#define TARGET_486 (ix86_cpu == PROCESSOR_I486) 208#define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) 209#define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) 210#define TARGET_K6 (ix86_cpu == PROCESSOR_K6) 211#define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) 212#define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4) 213 214#define CPUMASK (1 << ix86_cpu) 215extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 216extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 217extern const int x86_branch_hints, x86_unroll_strlen; 218extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 219extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; 220extern const int x86_use_cltd, x86_read_modify_write; 221extern const int x86_read_modify, x86_split_long_moves; 222extern const int x86_promote_QImode, x86_single_stringop; 223extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 224extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 225extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 226extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 227extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 228extern const int x86_epilogue_using_move, x86_decompose_lea; 229extern const int x86_arch_always_fancy_math_387; 230extern int x86_prefetch_sse; 231 232#define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) 233#define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) 234#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) 235#define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) 236#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) 237/* For sane SSE instruction set generation we need fcomi instruction. It is 238 safe to enable all CMOVE instructions. */ 239#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 240#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) 241#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK) 242#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) 243#define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT) 244#define TARGET_MOVX (x86_movx & CPUMASK) 245#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) 246#define TARGET_USE_LOOP (x86_use_loop & CPUMASK) 247#define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) 248#define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) 249#define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) 250#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) 251#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) 252#define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) 253#define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) 254#define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) 255#define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) 256#define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) 257#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) 258#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) 259#define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK) 260#define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK) 261#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK) 262#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK) 263#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK) 264#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK) 265#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK) 266#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK) 267#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK) 268#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK) 269#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 270 271#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) 272 273#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) 274#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) 275 276#define ASSEMBLER_DIALECT (ix86_asm_dialect) 277 278#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0) 279#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) 280#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 281#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 282 && (ix86_fpmath & FPMATH_387)) 283#define TARGET_MMX ((target_flags & MASK_MMX) != 0) 284#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) 285#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) 286 287#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) 288 289/* WARNING: Do not mark empty strings for translation, as calling 290 gettext on an empty string does NOT return an empty 291 string. */ 292 293 294#define TARGET_SWITCHES \ 295{ { "80387", MASK_80387, N_("Use hardware fp") }, \ 296 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ 297 { "hard-float", MASK_80387, N_("Use hardware fp") }, \ 298 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ 299 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ 300 { "386", 0, "" /*Deprecated.*/}, \ 301 { "486", 0, "" /*Deprecated.*/}, \ 302 { "pentium", 0, "" /*Deprecated.*/}, \ 303 { "pentiumpro", 0, "" /*Deprecated.*/}, \ 304 { "intel-syntax", 0, "" /*Deprecated.*/}, \ 305 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ 306 { "rtd", MASK_RTD, \ 307 N_("Alternate calling convention") }, \ 308 { "no-rtd", -MASK_RTD, \ 309 N_("Use normal calling convention") }, \ 310 { "align-double", MASK_ALIGN_DOUBLE, \ 311 N_("Align some doubles on dword boundary") }, \ 312 { "no-align-double", -MASK_ALIGN_DOUBLE, \ 313 N_("Align doubles on word boundary") }, \ 314 { "svr3-shlib", MASK_SVR3_SHLIB, \ 315 N_("Uninitialized locals in .bss") }, \ 316 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ 317 N_("Uninitialized locals in .data") }, \ 318 { "ieee-fp", MASK_IEEE_FP, \ 319 N_("Use IEEE math for fp comparisons") }, \ 320 { "no-ieee-fp", -MASK_IEEE_FP, \ 321 N_("Do not use IEEE math for fp comparisons") }, \ 322 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ 323 N_("Return values of functions in FPU registers") }, \ 324 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ 325 N_("Do not return values of functions in FPU registers")}, \ 326 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ 327 N_("Do not generate sin, cos, sqrt for FPU") }, \ 328 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ 329 N_("Generate sin, cos, sqrt for FPU")}, \ 330 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ 331 N_("Omit the frame pointer in leaf functions") }, \ 332 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ 333 { "stack-arg-probe", MASK_STACK_PROBE, \ 334 N_("Enable stack probing") }, \ 335 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ 336 { "windows", 0, 0 /* undocumented */ }, \ 337 { "dll", 0, 0 /* undocumented */ }, \ 338 { "align-stringops", -MASK_NO_ALIGN_STROPS, \ 339 N_("Align destination of the string operations") }, \ 340 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ 341 N_("Do not align destination of the string operations") }, \ 342 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ 343 N_("Inline all known string operations") }, \ 344 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ 345 N_("Do not inline all known string operations") }, \ 346 { "push-args", -MASK_NO_PUSH_ARGS, \ 347 N_("Use push instructions to save outgoing arguments") }, \ 348 { "no-push-args", MASK_NO_PUSH_ARGS, \ 349 N_("Do not use push instructions to save outgoing arguments") }, \ 350 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \ 351 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \ 352 N_("Use push instructions to save outgoing arguments") }, \ 353 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \ 354 N_("Do not use push instructions to save outgoing arguments") }, \ 355 { "mmx", MASK_MMX | MASK_MMX_SET, \ 356 N_("Support MMX built-in functions") }, \ 357 { "no-mmx", -MASK_MMX, \ 358 N_("Do not support MMX built-in functions") }, \ 359 { "no-mmx", MASK_MMX_SET, "" }, \ 360 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \ 361 N_("Support 3DNow! built-in functions") }, \ 362 { "no-3dnow", -MASK_3DNOW, "" }, \ 363 { "no-3dnow", MASK_3DNOW_SET, \ 364 N_("Do not support 3DNow! built-in functions") }, \ 365 { "sse", MASK_SSE | MASK_SSE_SET, \ 366 N_("Support MMX and SSE built-in functions and code generation") }, \ 367 { "no-sse", -MASK_SSE, "" }, \ 368 { "no-sse", MASK_SSE_SET, \ 369 N_("Do not support MMX and SSE built-in functions and code generation") },\ 370 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \ 371 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ 372 { "no-sse2", -MASK_SSE2, "" }, \ 373 { "no-sse2", MASK_SSE2_SET, \ 374 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ 375 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ 376 N_("sizeof(long double) is 16") }, \ 377 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ 378 N_("sizeof(long double) is 12") }, \ 379 { "64", MASK_64BIT, \ 380 N_("Generate 64bit x86-64 code") }, \ 381 { "32", -MASK_64BIT, \ 382 N_("Generate 32bit i386 code") }, \ 383 { "red-zone", -MASK_NO_RED_ZONE, \ 384 N_("Use red-zone in the x86-64 code") }, \ 385 { "no-red-zone", MASK_NO_RED_ZONE, \ 386 N_("Do not use red-zone in the x86-64 code") }, \ 387 SUBTARGET_SWITCHES \ 388 { "", TARGET_DEFAULT, 0 }} 389 390#ifdef TARGET_64BIT_DEFAULT 391#define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT) 392#else 393#define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT 394#endif 395 396/* Which processor to schedule for. The cpu attribute defines a list that 397 mirrors this list, so changes to i386.md must be made at the same time. */ 398 399enum processor_type 400{ 401 PROCESSOR_I386, /* 80386 */ 402 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 403 PROCESSOR_PENTIUM, 404 PROCESSOR_PENTIUMPRO, 405 PROCESSOR_K6, 406 PROCESSOR_ATHLON, 407 PROCESSOR_PENTIUM4, 408 PROCESSOR_max 409}; 410enum fpmath_unit 411{ 412 FPMATH_387 = 1, 413 FPMATH_SSE = 2 414}; 415 416extern enum processor_type ix86_cpu; 417extern enum fpmath_unit ix86_fpmath; 418 419extern int ix86_arch; 420 421/* This macro is similar to `TARGET_SWITCHES' but defines names of 422 command options that have values. Its definition is an 423 initializer with a subgrouping for each command option. 424 425 Each subgrouping contains a string constant, that defines the 426 fixed part of the option name, and the address of a variable. The 427 variable, type `char *', is set to the variable part of the given 428 option if the fixed part matches. The actual option name is made 429 by appending `-m' to the specified name. */ 430#define TARGET_OPTIONS \ 431{ { "cpu=", &ix86_cpu_string, \ 432 N_("Schedule code for given CPU")}, \ 433 { "fpmath=", &ix86_fpmath_string, \ 434 N_("Generate floating point mathematics using given instruction set")},\ 435 { "arch=", &ix86_arch_string, \ 436 N_("Generate code for given CPU")}, \ 437 { "regparm=", &ix86_regparm_string, \ 438 N_("Number of registers used to pass integer arguments") }, \ 439 { "align-loops=", &ix86_align_loops_string, \ 440 N_("Loop code aligned to this power of 2") }, \ 441 { "align-jumps=", &ix86_align_jumps_string, \ 442 N_("Jump targets are aligned to this power of 2") }, \ 443 { "align-functions=", &ix86_align_funcs_string, \ 444 N_("Function starts are aligned to this power of 2") }, \ 445 { "preferred-stack-boundary=", \ 446 &ix86_preferred_stack_boundary_string, \ 447 N_("Attempt to keep stack aligned to this power of 2") }, \ 448 { "branch-cost=", &ix86_branch_cost_string, \ 449 N_("Branches are this expensive (1-5, arbitrary units)") }, \ 450 { "cmodel=", &ix86_cmodel_string, \ 451 N_("Use given x86-64 code model") }, \ 452 { "debug-arg", &ix86_debug_arg_string, \ 453 "" /* Undocumented. */ }, \ 454 { "debug-addr", &ix86_debug_addr_string, \ 455 "" /* Undocumented. */ }, \ 456 { "asm=", &ix86_asm_string, \ 457 N_("Use given assembler dialect") }, \ 458 SUBTARGET_OPTIONS \ 459} 460 461/* Sometimes certain combinations of command options do not make 462 sense on a particular target machine. You can define a macro 463 `OVERRIDE_OPTIONS' to take account of this. This macro, if 464 defined, is executed once just after all the command options have 465 been parsed. 466 467 Don't use this macro to turn on various extra optimizations for 468 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 469 470#define OVERRIDE_OPTIONS override_options () 471 472/* These are meant to be redefined in the host dependent files */ 473#define SUBTARGET_SWITCHES 474#define SUBTARGET_OPTIONS 475 476/* Define this to change the optimizations performed by default. */ 477#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 478 optimization_options ((LEVEL), (SIZE)) 479 480/* Specs for the compiler proper */ 481 482#ifndef CC1_CPU_SPEC 483#define CC1_CPU_SPEC "\ 484%{!mcpu*: \ 485%{m386:-mcpu=i386 \ 486%n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \ 487%{m486:-mcpu=i486 \ 488%n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \ 489%{mpentium:-mcpu=pentium \ 490%n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \ 491%{mpentiumpro:-mcpu=pentiumpro \ 492%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \ 493%{mintel-syntax:-masm=intel \ 494%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 495%{mno-intel-syntax:-masm=att \ 496%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 497#endif 498 499#define TARGET_CPU_DEFAULT_i386 0 500#define TARGET_CPU_DEFAULT_i486 1 501#define TARGET_CPU_DEFAULT_pentium 2 502#define TARGET_CPU_DEFAULT_pentium_mmx 3 503#define TARGET_CPU_DEFAULT_pentiumpro 4 504#define TARGET_CPU_DEFAULT_pentium2 5 505#define TARGET_CPU_DEFAULT_pentium3 6 506#define TARGET_CPU_DEFAULT_pentium4 7 507#define TARGET_CPU_DEFAULT_k6 8 508#define TARGET_CPU_DEFAULT_k6_2 9 509#define TARGET_CPU_DEFAULT_k6_3 10 510#define TARGET_CPU_DEFAULT_athlon 11 511#define TARGET_CPU_DEFAULT_athlon_sse 12 512 513#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 514 "pentiumpro", "pentium2", "pentium3", \ 515 "pentium4", "k6", "k6-2", "k6-3",\ 516 "athlon", "athlon-4"} 517#ifndef CPP_CPU_DEFAULT_SPEC 518#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486 519#define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__" 520#endif 521#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium 522#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__" 523#endif 524#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx 525#define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__" 526#endif 527#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro 528#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__" 529#endif 530#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2 531#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 532-D__tune_pentium2__" 533#endif 534#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3 535#define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\ 536-D__tune_pentium2__ -D__tune_pentium3__" 537#endif 538#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4 539#define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__" 540#endif 541#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6 542#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__" 543#endif 544#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2 545#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__" 546#endif 547#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3 548#define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__" 549#endif 550#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon 551#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__" 552#endif 553#if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse 554#define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__" 555#endif 556#ifndef CPP_CPU_DEFAULT_SPEC 557#define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__" 558#endif 559#endif /* CPP_CPU_DEFAULT_SPEC */ 560 561#ifdef TARGET_BI_ARCH 562#define NO_BUILTIN_SIZE_TYPE 563#define NO_BUILTIN_PTRDIFF_TYPE 564#endif 565 566#ifdef NO_BUILTIN_SIZE_TYPE 567#define CPP_CPU32_SIZE_TYPE_SPEC \ 568 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int" 569#define CPP_CPU64_SIZE_TYPE_SPEC \ 570 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int" 571#else 572#define CPP_CPU32_SIZE_TYPE_SPEC "" 573#define CPP_CPU64_SIZE_TYPE_SPEC "" 574#endif 575 576#define CPP_CPU32_SPEC \ 577 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \ 578-D__i386__ %(cpp_cpu32sizet)" 579 580#define CPP_CPU64_SPEC \ 581 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)" 582 583#define CPP_CPUCOMMON_SPEC "\ 584%{march=i386:%{!mcpu*:-D__tune_i386__ }}\ 585%{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\ 586%{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 587 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\ 588%{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ 589 -D__pentium__mmx__ \ 590 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\ 591%{march=pentiumpro|march=i686:-D__i686 -D__i686__ \ 592 -D__pentiumpro -D__pentiumpro__ \ 593 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\ 594%{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\ 595%{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \ 596 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\ 597%{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \ 598 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\ 599%{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \ 600 %{!mcpu*:-D__tune_athlon__ }}\ 601%{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \ 602 -D__athlon_sse__ \ 603 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\ 604%{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\ 605%{m386|mcpu=i386:-D__tune_i386__ }\ 606%{m486|mcpu=i486:-D__tune_i486__ }\ 607%{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\ 608%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \ 609-D__tune_pentiumpro__ }\ 610%{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\ 611%{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 612-D__tune_athlon__ }\ 613%{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ 614-D__tune_athlon_sse__ }\ 615%{mcpu=pentium4:-D__tune_pentium4__ }\ 616%{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\ 617-D__SSE__ }\ 618%{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\ 619|march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 620|march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\ 621%{march=k6-2|march=k6-3\ 622|march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 623|march=athlon-mp: -D__3dNOW__ }\ 624%{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ 625|march=athlon-mp: -D__3dNOW_A__ }\ 626%{march=pentium4: -D__SSE2__ }\ 627%{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}" 628 629#ifndef CPP_CPU_SPEC 630#ifdef TARGET_BI_ARCH 631#ifdef TARGET_64BIT_DEFAULT 632#define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)" 633#else 634#define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)" 635#endif 636#else 637#ifdef TARGET_64BIT_DEFAULT 638#define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)" 639#else 640#define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)" 641#endif 642#endif 643#endif 644 645#ifndef CC1_SPEC 646#define CC1_SPEC "%(cc1_cpu) " 647#endif 648 649/* This macro defines names of additional specifications to put in the 650 specs that can be used in various specifications like CC1_SPEC. Its 651 definition is an initializer with a subgrouping for each command option. 652 653 Each subgrouping contains a string constant, that defines the 654 specification name, and a string constant that used by the GNU CC driver 655 program. 656 657 Do not define this macro if it does not need to do anything. */ 658 659#ifndef SUBTARGET_EXTRA_SPECS 660#define SUBTARGET_EXTRA_SPECS 661#endif 662 663#define EXTRA_SPECS \ 664 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 665 { "cpp_cpu", CPP_CPU_SPEC }, \ 666 { "cpp_cpu32", CPP_CPU32_SPEC }, \ 667 { "cpp_cpu64", CPP_CPU64_SPEC }, \ 668 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \ 669 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \ 670 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \ 671 { "cc1_cpu", CC1_CPU_SPEC }, \ 672 SUBTARGET_EXTRA_SPECS 673 674/* target machine storage layout */ 675 676/* Define for XFmode or TFmode extended real floating point support. 677 This will automatically cause REAL_ARITHMETIC to be defined. 678 679 The XFmode is specified by i386 ABI, while TFmode may be faster 680 due to alignment and simplifications in the address calculations. 681 */ 682#define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96) 683#define MAX_LONG_DOUBLE_TYPE_SIZE 128 684#ifdef __x86_64__ 685#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 686#else 687#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 688#endif 689/* Tell real.c that this is the 80-bit Intel extended float format 690 packaged in a 128-bit or 96bit entity. */ 691#define INTEL_EXTENDED_IEEE_FORMAT 1 692 693 694#define SHORT_TYPE_SIZE 16 695#define INT_TYPE_SIZE 32 696#define FLOAT_TYPE_SIZE 32 697#define LONG_TYPE_SIZE BITS_PER_WORD 698#define MAX_WCHAR_TYPE_SIZE 32 699#define DOUBLE_TYPE_SIZE 64 700#define LONG_LONG_TYPE_SIZE 64 701 702#if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT) 703#define MAX_BITS_PER_WORD 64 704#define MAX_LONG_TYPE_SIZE 64 705#else 706#define MAX_BITS_PER_WORD 32 707#define MAX_LONG_TYPE_SIZE 32 708#endif 709 710/* Define if you don't want extended real, but do want to use the 711 software floating point emulator for REAL_ARITHMETIC and 712 decimal <-> binary conversion. */ 713/* #define REAL_ARITHMETIC */ 714 715/* Define this if most significant byte of a word is the lowest numbered. */ 716/* That is true on the 80386. */ 717 718#define BITS_BIG_ENDIAN 0 719 720/* Define this if most significant byte of a word is the lowest numbered. */ 721/* That is not true on the 80386. */ 722#define BYTES_BIG_ENDIAN 0 723 724/* Define this if most significant word of a multiword number is the lowest 725 numbered. */ 726/* Not true for 80386 */ 727#define WORDS_BIG_ENDIAN 0 728 729/* number of bits in an addressable storage unit */ 730#define BITS_PER_UNIT 8 731 732/* Width in bits of a "word", which is the contents of a machine register. 733 Note that this is not necessarily the width of data type `int'; 734 if using 16-bit ints on a 80386, this would still be 32. 735 But on a machine with 16-bit registers, this would be 16. */ 736#define BITS_PER_WORD (TARGET_64BIT ? 64 : 32) 737 738/* Width of a word, in units (bytes). */ 739#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 740#define MIN_UNITS_PER_WORD 4 741 742/* Width in bits of a pointer. 743 See also the macro `Pmode' defined below. */ 744#define POINTER_SIZE BITS_PER_WORD 745 746/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 747#define PARM_BOUNDARY BITS_PER_WORD 748 749/* Boundary (in *bits*) on which stack pointer should be aligned. */ 750#define STACK_BOUNDARY BITS_PER_WORD 751 752/* Boundary (in *bits*) on which the stack pointer preferrs to be 753 aligned; the compiler cannot rely on having this alignment. */ 754#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 755 756/* As of July 2001, many runtimes to not align the stack properly when 757 entering main. This causes expand_main_function to forcably align 758 the stack, which results in aligned frames for functions called from 759 main, though it does nothing for the alignment of main itself. */ 760#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 761 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 762 763/* Allocation boundary for the code of a function. */ 764#define FUNCTION_BOUNDARY 16 765 766/* Alignment of field after `int : 0' in a structure. */ 767 768#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 769 770/* Minimum size in bits of the largest boundary to which any 771 and all fundamental data types supported by the hardware 772 might need to be aligned. No data type wants to be aligned 773 rounder than this. 774 775 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary 776 and Pentium Pro XFmode values at 128 bit boundaries. */ 777 778#define BIGGEST_ALIGNMENT 128 779 780/* Decide whether a variable of mode MODE must be 128 bit aligned. */ 781#define ALIGN_MODE_128(MODE) \ 782 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \ 783 || (MODE) == V4SFmode || (MODE) == V4SImode) 784 785/* The published ABIs say that doubles should be aligned on word 786 boundaries, so lower the aligment for structure fields unless 787 -malign-double is set. */ 788/* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be 789 constant. Use the smaller value in that context. */ 790#ifndef IN_TARGET_LIBS 791#define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32)) 792#else 793#define BIGGEST_FIELD_ALIGNMENT 32 794#endif 795 796/* If defined, a C expression to compute the alignment given to a 797 constant that is being placed in memory. EXP is the constant 798 and ALIGN is the alignment that the object would ordinarily have. 799 The value of this macro is used instead of that alignment to align 800 the object. 801 802 If this macro is not defined, then ALIGN is used. 803 804 The typical use of this macro is to increase alignment for string 805 constants to be word aligned so that `strcpy' calls that copy 806 constants can be done inline. */ 807 808#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 809 810/* If defined, a C expression to compute the alignment for a static 811 variable. TYPE is the data type, and ALIGN is the alignment that 812 the object would ordinarily have. The value of this macro is used 813 instead of that alignment to align the object. 814 815 If this macro is not defined, then ALIGN is used. 816 817 One use of this macro is to increase alignment of medium-size 818 data to make it all fit in fewer cache lines. Another is to 819 cause character arrays to be word-aligned so that `strcpy' calls 820 that copy constants to character arrays can be done inline. */ 821 822#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 823 824/* If defined, a C expression to compute the alignment for a local 825 variable. TYPE is the data type, and ALIGN is the alignment that 826 the object would ordinarily have. The value of this macro is used 827 instead of that alignment to align the object. 828 829 If this macro is not defined, then ALIGN is used. 830 831 One use of this macro is to increase alignment of medium-size 832 data to make it all fit in fewer cache lines. */ 833 834#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 835 836/* If defined, a C expression that gives the alignment boundary, in 837 bits, of an argument with the specified mode and type. If it is 838 not defined, `PARM_BOUNDARY' is used for all arguments. */ 839 840#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 841 ix86_function_arg_boundary ((MODE), (TYPE)) 842 843/* Set this non-zero if move instructions will actually fail to work 844 when given unaligned data. */ 845#define STRICT_ALIGNMENT 0 846 847/* If bit field type is int, don't let it cross an int, 848 and give entire struct the alignment of an int. */ 849/* Required on the 386 since it doesn't have bitfield insns. */ 850#define PCC_BITFIELD_TYPE_MATTERS 1 851 852/* Standard register usage. */ 853 854/* This processor has special stack-like registers. See reg-stack.c 855 for details. */ 856 857#define STACK_REGS 858#define IS_STACK_MODE(MODE) \ 859 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ 860 || (MODE) == TFmode) 861 862/* Number of actual hardware registers. 863 The hardware registers are assigned numbers for the compiler 864 from 0 to just below FIRST_PSEUDO_REGISTER. 865 All registers that the compiler knows about must be given numbers, 866 even those that are not normally considered general registers. 867 868 In the 80386 we give the 8 general purpose registers the numbers 0-7. 869 We number the floating point registers 8-15. 870 Note that registers 0-7 can be accessed as a short or int, 871 while only 0-3 may be used with byte `mov' instructions. 872 873 Reg 16 does not correspond to any hardware register, but instead 874 appears in the RTL as an argument pointer prior to reload, and is 875 eliminated during reloading in favor of either the stack or frame 876 pointer. */ 877 878#define FIRST_PSEUDO_REGISTER 53 879 880/* Number of hardware registers that go into the DWARF-2 unwind info. 881 If not defined, equals FIRST_PSEUDO_REGISTER. */ 882 883#define DWARF_FRAME_REGISTERS 17 884 885/* 1 for registers that have pervasive standard uses 886 and are not available for the register allocator. 887 On the 80386, the stack pointer is such, as is the arg pointer. 888 889 The value is an mask - bit 1 is set for fixed registers 890 for 32bit target, while 2 is set for fixed registers for 64bit. 891 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 892 */ 893#define FIXED_REGISTERS \ 894/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 895{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ 896/*arg,flags,fpsr,dir,frame*/ \ 897 3, 3, 3, 3, 3, \ 898/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 899 0, 0, 0, 0, 0, 0, 0, 0, \ 900/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 901 0, 0, 0, 0, 0, 0, 0, 0, \ 902/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 903 1, 1, 1, 1, 1, 1, 1, 1, \ 904/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 905 1, 1, 1, 1, 1, 1, 1, 1} 906 907 908/* 1 for registers not available across function calls. 909 These must include the FIXED_REGISTERS and also any 910 registers that can be used without being saved. 911 The latter must include the registers where values are returned 912 and the register where structure-value addresses are passed. 913 Aside from that, you can include as many other registers as you like. 914 915 The value is an mask - bit 1 is set for call used 916 for 32bit target, while 2 is set for call used for 64bit. 917 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 918*/ 919#define CALL_USED_REGISTERS \ 920/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 921{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 922/*arg,flags,fpsr,dir,frame*/ \ 923 3, 3, 3, 3, 3, \ 924/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 925 3, 3, 3, 3, 3, 3, 3, 3, \ 926/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 927 3, 3, 3, 3, 3, 3, 3, 3, \ 928/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 929 3, 3, 3, 3, 1, 1, 1, 1, \ 930/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 931 3, 3, 3, 3, 3, 3, 3, 3} \ 932 933/* Order in which to allocate registers. Each register must be 934 listed once, even those in FIXED_REGISTERS. List frame pointer 935 late and fixed registers last. Note that, in general, we prefer 936 registers listed in CALL_USED_REGISTERS, keeping the others 937 available for storage of persistent values. 938 939 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 940 so this is just empty initializer for array. */ 941 942#define REG_ALLOC_ORDER \ 943{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 944 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 945 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 946 48, 49, 50, 51, 52 } 947 948/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 949 to be rearranged based on a particular function. When using sse math, 950 we want to allocase SSE before x87 registers and vice vera. */ 951 952#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 953 954 955/* Macro to conditionally modify fixed_regs/call_used_regs. */ 956#define CONDITIONAL_REGISTER_USAGE \ 957do { \ 958 int i; \ 959 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 960 { \ 961 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ 962 call_used_regs[i] = (call_used_regs[i] \ 963 & (TARGET_64BIT ? 2 : 1)) != 0; \ 964 } \ 965 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 966 { \ 967 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 968 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 969 } \ 970 if (! TARGET_MMX) \ 971 { \ 972 int i; \ 973 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 974 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 975 fixed_regs[i] = call_used_regs[i] = 1; \ 976 } \ 977 if (! TARGET_SSE) \ 978 { \ 979 int i; \ 980 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 981 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 982 fixed_regs[i] = call_used_regs[i] = 1; \ 983 } \ 984 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 985 { \ 986 int i; \ 987 HARD_REG_SET x; \ 988 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 989 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 990 if (TEST_HARD_REG_BIT (x, i)) \ 991 fixed_regs[i] = call_used_regs[i] = 1; \ 992 } \ 993 } while (0) 994 995/* Return number of consecutive hard regs needed starting at reg REGNO 996 to hold something of mode MODE. 997 This is ordinarily the length in words of a value of mode MODE 998 but can be less for certain modes in special long registers. 999 1000 Actually there are no two word move instructions for consecutive 1001 registers. And only registers 0-3 may have mov byte instructions 1002 applied to them. 1003 */ 1004 1005#define HARD_REGNO_NREGS(REGNO, MODE) \ 1006 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1007 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1008 : ((MODE) == TFmode \ 1009 ? (TARGET_64BIT ? 2 : 3) \ 1010 : (MODE) == TCmode \ 1011 ? (TARGET_64BIT ? 4 : 6) \ 1012 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1013 1014#define VALID_SSE_REG_MODE(MODE) \ 1015 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1016 || (MODE) == SFmode \ 1017 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) 1018 1019#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1020 ((MODE) == V2SFmode || (MODE) == SFmode) 1021 1022#define VALID_MMX_REG_MODE(MODE) \ 1023 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 1024 || (MODE) == V2SImode || (MODE) == SImode) 1025 1026#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1027 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ 1028 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ 1029 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) 1030 1031#define VALID_FP_MODE_P(MODE) \ 1032 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 1033 || (!TARGET_64BIT && (MODE) == XFmode) \ 1034 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \ 1035 || (!TARGET_64BIT && (MODE) == XCmode)) 1036 1037#define VALID_INT_MODE_P(MODE) \ 1038 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1039 || (MODE) == DImode \ 1040 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1041 || (MODE) == CDImode \ 1042 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) 1043 1044/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1045 1046#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1047 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1048 1049/* Value is 1 if it is a good idea to tie two pseudo registers 1050 when one has mode MODE1 and one has mode MODE2. 1051 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1052 for any hard reg, then this must be 0 for correct output. */ 1053 1054#define MODES_TIEABLE_P(MODE1, MODE2) \ 1055 ((MODE1) == (MODE2) \ 1056 || (((MODE1) == HImode || (MODE1) == SImode \ 1057 || ((MODE1) == QImode \ 1058 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1059 || ((MODE1) == DImode && TARGET_64BIT)) \ 1060 && ((MODE2) == HImode || (MODE2) == SImode \ 1061 || ((MODE1) == QImode \ 1062 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1063 || ((MODE2) == DImode && TARGET_64BIT)))) 1064 1065 1066/* Specify the modes required to caller save a given hard regno. 1067 We do this on i386 to prevent flags from being saved at all. 1068 1069 Kill any attempts to combine saving of modes. */ 1070 1071#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1072 (CC_REGNO_P (REGNO) ? VOIDmode \ 1073 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1074 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \ 1075 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1076 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 1077 : (MODE)) 1078/* Specify the registers used for certain standard purposes. 1079 The values of these macros are register numbers. */ 1080 1081/* on the 386 the pc register is %eip, and is not usable as a general 1082 register. The ordinary mov instructions won't work */ 1083/* #define PC_REGNUM */ 1084 1085/* Register to use for pushing function arguments. */ 1086#define STACK_POINTER_REGNUM 7 1087 1088/* Base register for access to local variables of the function. */ 1089#define HARD_FRAME_POINTER_REGNUM 6 1090 1091/* Base register for access to local variables of the function. */ 1092#define FRAME_POINTER_REGNUM 20 1093 1094/* First floating point reg */ 1095#define FIRST_FLOAT_REG 8 1096 1097/* First & last stack-like regs */ 1098#define FIRST_STACK_REG FIRST_FLOAT_REG 1099#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1100 1101#define FLAGS_REG 17 1102#define FPSR_REG 18 1103#define DIRFLAG_REG 19 1104 1105#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1106#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1107 1108#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1109#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1110 1111#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1112#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1113 1114#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1115#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1116 1117/* Value should be nonzero if functions must have frame pointers. 1118 Zero means the frame pointer need not be set up (and parms 1119 may be accessed via the stack pointer) in functions that seem suitable. 1120 This is computed in `reload', in reload1.c. */ 1121#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1122 1123/* Override this in other tm.h files to cope with various OS losage 1124 requiring a frame pointer. */ 1125#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1126#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1127#endif 1128 1129/* Make sure we can access arbitrary call frames. */ 1130#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1131 1132/* Base register for access to arguments of the function. */ 1133#define ARG_POINTER_REGNUM 16 1134 1135/* Register in which static-chain is passed to a function. 1136 We do use ECX as static chain register for 32 bit ABI. On the 1137 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1138#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1139 1140/* Register to hold the addressing base for position independent 1141 code access to data items. We don't use PIC pointer for 64bit 1142 mode. Define the regnum to dummy value to prevent gcc from 1143 pessimizing code dealing with EBX. */ 1144#define PIC_OFFSET_TABLE_REGNUM \ 1145 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM : 3) 1146 1147/* Register in which address to store a structure value 1148 arrives in the function. On the 386, the prologue 1149 copies this from the stack to register %eax. */ 1150#define STRUCT_VALUE_INCOMING 0 1151 1152/* Place in which caller passes the structure value address. 1153 0 means push the value on the stack like an argument. */ 1154#define STRUCT_VALUE 0 1155 1156/* A C expression which can inhibit the returning of certain function 1157 values in registers, based on the type of value. A nonzero value 1158 says to return the function value in memory, just as large 1159 structures are always returned. Here TYPE will be a C expression 1160 of type `tree', representing the data type of the value. 1161 1162 Note that values of mode `BLKmode' must be explicitly handled by 1163 this macro. Also, the option `-fpcc-struct-return' takes effect 1164 regardless of this macro. On most systems, it is possible to 1165 leave the macro undefined; this causes a default definition to be 1166 used, whose value is the constant 1 for `BLKmode' values, and 0 1167 otherwise. 1168 1169 Do not use this macro to indicate that structures and unions 1170 should always be returned in memory. You should instead use 1171 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1172 1173#define RETURN_IN_MEMORY(TYPE) \ 1174 ix86_return_in_memory (TYPE) 1175 1176 1177/* Define the classes of registers for register constraints in the 1178 machine description. Also define ranges of constants. 1179 1180 One of the classes must always be named ALL_REGS and include all hard regs. 1181 If there is more than one class, another class must be named NO_REGS 1182 and contain no registers. 1183 1184 The name GENERAL_REGS must be the name of a class (or an alias for 1185 another name such as ALL_REGS). This is the class of registers 1186 that is allowed by "g" or "r" in a register constraint. 1187 Also, registers outside this class are allocated only when 1188 instructions express preferences for them. 1189 1190 The classes must be numbered in nondecreasing order; that is, 1191 a larger-numbered class must never be contained completely 1192 in a smaller-numbered class. 1193 1194 For any two classes, it is very desirable that there be another 1195 class that represents their union. 1196 1197 It might seem that class BREG is unnecessary, since no useful 386 1198 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1199 and the "b" register constraint is useful in asms for syscalls. 1200 1201 The flags and fpsr registers are in no class. */ 1202 1203enum reg_class 1204{ 1205 NO_REGS, 1206 AREG, DREG, CREG, BREG, SIREG, DIREG, 1207 AD_REGS, /* %eax/%edx for DImode */ 1208 Q_REGS, /* %eax %ebx %ecx %edx */ 1209 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1210 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1211 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1212 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1213 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1214 FLOAT_REGS, 1215 SSE_REGS, 1216 MMX_REGS, 1217 FP_TOP_SSE_REGS, 1218 FP_SECOND_SSE_REGS, 1219 FLOAT_SSE_REGS, 1220 FLOAT_INT_REGS, 1221 INT_SSE_REGS, 1222 FLOAT_INT_SSE_REGS, 1223 ALL_REGS, LIM_REG_CLASSES 1224}; 1225 1226#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1227 1228#define INTEGER_CLASS_P(CLASS) \ 1229 reg_class_subset_p ((CLASS), GENERAL_REGS) 1230#define FLOAT_CLASS_P(CLASS) \ 1231 reg_class_subset_p ((CLASS), FLOAT_REGS) 1232#define SSE_CLASS_P(CLASS) \ 1233 reg_class_subset_p ((CLASS), SSE_REGS) 1234#define MMX_CLASS_P(CLASS) \ 1235 reg_class_subset_p ((CLASS), MMX_REGS) 1236#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1237 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1238#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1239 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1240#define MAYBE_SSE_CLASS_P(CLASS) \ 1241 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1242#define MAYBE_MMX_CLASS_P(CLASS) \ 1243 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1244 1245#define Q_CLASS_P(CLASS) \ 1246 reg_class_subset_p ((CLASS), Q_REGS) 1247 1248/* Give names of register classes as strings for dump file. */ 1249 1250#define REG_CLASS_NAMES \ 1251{ "NO_REGS", \ 1252 "AREG", "DREG", "CREG", "BREG", \ 1253 "SIREG", "DIREG", \ 1254 "AD_REGS", \ 1255 "Q_REGS", "NON_Q_REGS", \ 1256 "INDEX_REGS", \ 1257 "LEGACY_REGS", \ 1258 "GENERAL_REGS", \ 1259 "FP_TOP_REG", "FP_SECOND_REG", \ 1260 "FLOAT_REGS", \ 1261 "SSE_REGS", \ 1262 "MMX_REGS", \ 1263 "FP_TOP_SSE_REGS", \ 1264 "FP_SECOND_SSE_REGS", \ 1265 "FLOAT_SSE_REGS", \ 1266 "FLOAT_INT_REGS", \ 1267 "INT_SSE_REGS", \ 1268 "FLOAT_INT_SSE_REGS", \ 1269 "ALL_REGS" } 1270 1271/* Define which registers fit in which classes. 1272 This is an initializer for a vector of HARD_REG_SET 1273 of length N_REG_CLASSES. */ 1274 1275#define REG_CLASS_CONTENTS \ 1276{ { 0x00, 0x0 }, \ 1277 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1278 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1279 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1280 { 0x03, 0x0 }, /* AD_REGS */ \ 1281 { 0x0f, 0x0 }, /* Q_REGS */ \ 1282 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1283 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1284 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1285 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1286 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1287 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1288{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1289{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1290{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1291{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1292{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1293 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1294{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1295{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1296{ 0xffffffff,0x1fffff } \ 1297} 1298 1299/* The same information, inverted: 1300 Return the class number of the smallest class containing 1301 reg number REGNO. This could be a conditional expression 1302 or could index an array. */ 1303 1304#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1305 1306/* When defined, the compiler allows registers explicitly used in the 1307 rtl to be used as spill registers but prevents the compiler from 1308 extending the lifetime of these registers. */ 1309 1310#define SMALL_REGISTER_CLASSES 1 1311 1312#define QI_REG_P(X) \ 1313 (REG_P (X) && REGNO (X) < 4) 1314 1315#define GENERAL_REGNO_P(N) \ 1316 ((N) < 8 || REX_INT_REGNO_P (N)) 1317 1318#define GENERAL_REG_P(X) \ 1319 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1320 1321#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1322 1323#define NON_QI_REG_P(X) \ 1324 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1325 1326#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1327#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1328 1329#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1330#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1331#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1332#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1333 1334#define SSE_REGNO_P(N) \ 1335 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1336 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1337 1338#define SSE_REGNO(N) \ 1339 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1340#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1341 1342#define SSE_FLOAT_MODE_P(MODE) \ 1343 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1344 1345#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1346#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1347 1348#define STACK_REG_P(XOP) \ 1349 (REG_P (XOP) && \ 1350 REGNO (XOP) >= FIRST_STACK_REG && \ 1351 REGNO (XOP) <= LAST_STACK_REG) 1352 1353#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1354 1355#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1356 1357#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1358#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1359 1360/* Indicate whether hard register numbered REG_NO should be converted 1361 to SSA form. */ 1362#define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \ 1363 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM) 1364 1365/* The class value for index registers, and the one for base regs. */ 1366 1367#define INDEX_REG_CLASS INDEX_REGS 1368#define BASE_REG_CLASS GENERAL_REGS 1369 1370/* Get reg_class from a letter such as appears in the machine description. */ 1371 1372#define REG_CLASS_FROM_LETTER(C) \ 1373 ((C) == 'r' ? GENERAL_REGS : \ 1374 (C) == 'R' ? LEGACY_REGS : \ 1375 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1376 (C) == 'Q' ? Q_REGS : \ 1377 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1378 ? FLOAT_REGS \ 1379 : NO_REGS) : \ 1380 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1381 ? FP_TOP_REG \ 1382 : NO_REGS) : \ 1383 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1384 ? FP_SECOND_REG \ 1385 : NO_REGS) : \ 1386 (C) == 'a' ? AREG : \ 1387 (C) == 'b' ? BREG : \ 1388 (C) == 'c' ? CREG : \ 1389 (C) == 'd' ? DREG : \ 1390 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1391 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1392 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1393 (C) == 'A' ? AD_REGS : \ 1394 (C) == 'D' ? DIREG : \ 1395 (C) == 'S' ? SIREG : NO_REGS) 1396 1397/* The letters I, J, K, L and M in a register constraint string 1398 can be used to stand for particular ranges of immediate operands. 1399 This macro defines what the ranges are. 1400 C is the letter, and VALUE is a constant value. 1401 Return 1 if VALUE is in the range specified by C. 1402 1403 I is for non-DImode shifts. 1404 J is for DImode shifts. 1405 K is for signed imm8 operands. 1406 L is for andsi as zero-extending move. 1407 M is for shifts that can be executed by the "lea" opcode. 1408 N is for immedaite operands for out/in instructions (0-255) 1409 */ 1410 1411#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1412 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1413 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1414 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1415 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1416 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1417 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1418 : 0) 1419 1420/* Similar, but for floating constants, and defining letters G and H. 1421 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1422 TARGET_387 isn't set, because the stack register converter may need to 1423 load 0.0 into the function value register. */ 1424 1425#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1426 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1427 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0)) 1428 1429/* A C expression that defines the optional machine-dependent 1430 constraint letters that can be used to segregate specific types of 1431 operands, usually memory references, for the target machine. Any 1432 letter that is not elsewhere defined and not matched by 1433 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1434 be defined. 1435 1436 If it is required for a particular target machine, it should 1437 return 1 if VALUE corresponds to the operand type represented by 1438 the constraint letter C. If C is not defined as an extra 1439 constraint, the value returned should be 0 regardless of VALUE. */ 1440 1441#define EXTRA_CONSTRAINT(VALUE, C) \ 1442 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \ 1443 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \ 1444 : 0) 1445 1446/* Place additional restrictions on the register class to use when it 1447 is necessary to be able to hold a value of mode MODE in a reload 1448 register for which class CLASS would ordinarily be used. */ 1449 1450#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1451 ((MODE) == QImode && !TARGET_64BIT \ 1452 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1453 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1454 ? Q_REGS : (CLASS)) 1455 1456/* Given an rtx X being reloaded into a reg required to be 1457 in class CLASS, return the class of reg to actually use. 1458 In general this is just CLASS; but on some machines 1459 in some cases it is preferable to use a more restrictive class. 1460 On the 80386 series, we prevent floating constants from being 1461 reloaded into floating registers (since no move-insn can do that) 1462 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1463 1464/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1465 QImode must go into class Q_REGS. 1466 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1467 movdf to do mem-to-mem moves through integer regs. */ 1468 1469#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1470 ix86_preferred_reload_class ((X), (CLASS)) 1471 1472/* If we are copying between general and FP registers, we need a memory 1473 location. The same is true for SSE and MMX registers. */ 1474#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1475 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1476 1477/* QImode spills from non-QI registers need a scratch. This does not 1478 happen often -- the only example so far requires an uninitialized 1479 pseudo. */ 1480 1481#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1482 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1483 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1484 ? Q_REGS : NO_REGS) 1485 1486/* Return the maximum number of consecutive registers 1487 needed to represent mode MODE in a register of class CLASS. */ 1488/* On the 80386, this is the size of MODE in words, 1489 except in the FP regs, where a single reg is always enough. 1490 The TFmodes are really just 80bit values, so we use only 3 registers 1491 to hold them, instead of 4, as the size would suggest. 1492 */ 1493#define CLASS_MAX_NREGS(CLASS, MODE) \ 1494 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1495 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1496 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ 1497 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1498 1499/* A C expression whose value is nonzero if pseudos that have been 1500 assigned to registers of class CLASS would likely be spilled 1501 because registers of CLASS are needed for spill registers. 1502 1503 The default value of this macro returns 1 if CLASS has exactly one 1504 register and zero otherwise. On most machines, this default 1505 should be used. Only define this macro to some other expression 1506 if pseudo allocated by `local-alloc.c' end up in memory because 1507 their hard registers were needed for spill registers. If this 1508 macro returns nonzero for those classes, those pseudos will only 1509 be allocated by `global.c', which knows how to reallocate the 1510 pseudo to another register. If there would not be another 1511 register available for reallocation, you should not change the 1512 definition of this macro since the only effect of such a 1513 definition would be to slow down register allocation. */ 1514 1515#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1516 (((CLASS) == AREG) \ 1517 || ((CLASS) == DREG) \ 1518 || ((CLASS) == CREG) \ 1519 || ((CLASS) == BREG) \ 1520 || ((CLASS) == AD_REGS) \ 1521 || ((CLASS) == SIREG) \ 1522 || ((CLASS) == DIREG)) 1523 1524/* A C statement that adds to CLOBBERS any hard regs the port wishes 1525 to automatically clobber for all asms. 1526 1527 We do this in the new i386 backend to maintain source compatibility 1528 with the old cc0-based compiler. */ 1529 1530#define MD_ASM_CLOBBERS(CLOBBERS) \ 1531 do { \ 1532 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ 1533 (CLOBBERS)); \ 1534 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ 1535 (CLOBBERS)); \ 1536 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ 1537 (CLOBBERS)); \ 1538 } while (0) 1539 1540/* Stack layout; function entry, exit and calling. */ 1541 1542/* Define this if pushing a word on the stack 1543 makes the stack pointer a smaller address. */ 1544#define STACK_GROWS_DOWNWARD 1545 1546/* Define this if the nominal address of the stack frame 1547 is at the high-address end of the local variables; 1548 that is, each additional local variable allocated 1549 goes at a more negative offset in the frame. */ 1550#define FRAME_GROWS_DOWNWARD 1551 1552/* Offset within stack frame to start allocating local variables at. 1553 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1554 first local allocated. Otherwise, it is the offset to the BEGINNING 1555 of the first local allocated. */ 1556#define STARTING_FRAME_OFFSET 0 1557 1558/* If we generate an insn to push BYTES bytes, 1559 this says how many the stack pointer really advances by. 1560 On 386 pushw decrements by exactly 2 no matter what the position was. 1561 On the 386 there is no pushb; we use pushw instead, and this 1562 has the effect of rounding up to 2. 1563 1564 For 64bit ABI we round up to 8 bytes. 1565 */ 1566 1567#define PUSH_ROUNDING(BYTES) \ 1568 (TARGET_64BIT \ 1569 ? (((BYTES) + 7) & (-8)) \ 1570 : (((BYTES) + 1) & (-2))) 1571 1572/* If defined, the maximum amount of space required for outgoing arguments will 1573 be computed and placed into the variable 1574 `current_function_outgoing_args_size'. No space will be pushed onto the 1575 stack for each call; instead, the function prologue should increase the stack 1576 frame size by this amount. */ 1577 1578#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1579 1580/* If defined, a C expression whose value is nonzero when we want to use PUSH 1581 instructions to pass outgoing arguments. */ 1582 1583#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1584 1585/* Offset of first parameter from the argument pointer register value. */ 1586#define FIRST_PARM_OFFSET(FNDECL) 0 1587 1588/* Define this macro if functions should assume that stack space has been 1589 allocated for arguments even when their values are passed in registers. 1590 1591 The value of this macro is the size, in bytes, of the area reserved for 1592 arguments passed in registers for the function represented by FNDECL. 1593 1594 This space can be allocated by the caller, or be a part of the 1595 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1596 which. */ 1597#define REG_PARM_STACK_SPACE(FNDECL) 0 1598 1599/* Define as a C expression that evaluates to nonzero if we do not know how 1600 to pass TYPE solely in registers. The file expr.h defines a 1601 definition that is usually appropriate, refer to expr.h for additional 1602 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be 1603 computed in the stack and then loaded into a register. */ 1604#define MUST_PASS_IN_STACK(MODE, TYPE) \ 1605 ((TYPE) != 0 \ 1606 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1607 || TREE_ADDRESSABLE (TYPE) \ 1608 || ((MODE) == TImode) \ 1609 || ((MODE) == BLKmode \ 1610 && ! ((TYPE) != 0 \ 1611 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ 1612 && 0 == (int_size_in_bytes (TYPE) \ 1613 % (PARM_BOUNDARY / BITS_PER_UNIT))) \ 1614 && (FUNCTION_ARG_PADDING (MODE, TYPE) \ 1615 == (BYTES_BIG_ENDIAN ? upward : downward))))) 1616 1617/* Value is the number of bytes of arguments automatically 1618 popped when returning from a subroutine call. 1619 FUNDECL is the declaration node of the function (as a tree), 1620 FUNTYPE is the data type of the function (as a tree), 1621 or for a library call it is an identifier node for the subroutine name. 1622 SIZE is the number of bytes of arguments passed on the stack. 1623 1624 On the 80386, the RTD insn may be used to pop them if the number 1625 of args is fixed, but if the number is variable then the caller 1626 must pop them all. RTD can't be used for library calls now 1627 because the library is compiled with the Unix compiler. 1628 Use of RTD is a selectable option, since it is incompatible with 1629 standard Unix calling sequences. If the option is not selected, 1630 the caller must always pop the args. 1631 1632 The attribute stdcall is equivalent to RTD on a per module basis. */ 1633 1634#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1635 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1636 1637/* Define how to find the value returned by a function. 1638 VALTYPE is the data type of the value (as a tree). 1639 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1640 otherwise, FUNC is 0. */ 1641#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1642 ix86_function_value (VALTYPE) 1643 1644#define FUNCTION_VALUE_REGNO_P(N) \ 1645 ix86_function_value_regno_p (N) 1646 1647/* Define how to find the value returned by a library function 1648 assuming the value has mode MODE. */ 1649 1650#define LIBCALL_VALUE(MODE) \ 1651 ix86_libcall_value (MODE) 1652 1653/* Define the size of the result block used for communication between 1654 untyped_call and untyped_return. The block contains a DImode value 1655 followed by the block used by fnsave and frstor. */ 1656 1657#define APPLY_RESULT_SIZE (8+108) 1658 1659/* 1 if N is a possible register number for function argument passing. */ 1660#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1661 1662/* Define a data type for recording info about an argument list 1663 during the scan of that argument list. This data type should 1664 hold all necessary information about the function itself 1665 and about the args processed so far, enough to enable macros 1666 such as FUNCTION_ARG to determine where the next arg should go. */ 1667 1668typedef struct ix86_args { 1669 int words; /* # words passed so far */ 1670 int nregs; /* # registers available for passing */ 1671 int regno; /* next available register number */ 1672 int sse_words; /* # sse words passed so far */ 1673 int sse_nregs; /* # sse registers available for passing */ 1674 int sse_regno; /* next available sse register number */ 1675 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1676} CUMULATIVE_ARGS; 1677 1678/* Initialize a variable CUM of type CUMULATIVE_ARGS 1679 for a call to a function whose data type is FNTYPE. 1680 For a library call, FNTYPE is 0. */ 1681 1682#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1683 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) 1684 1685/* Update the data in CUM to advance over an argument 1686 of mode MODE and data type TYPE. 1687 (TYPE is null for libcalls where that information may not be available.) */ 1688 1689#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1690 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1691 1692/* Define where to put the arguments to a function. 1693 Value is zero to push the argument on the stack, 1694 or a hard register in which to store the argument. 1695 1696 MODE is the argument's machine mode. 1697 TYPE is the data type of the argument (as a tree). 1698 This is null for libcalls where that information may 1699 not be available. 1700 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1701 the preceding args and about the function being called. 1702 NAMED is nonzero if this argument is a named parameter 1703 (otherwise it is an extra parameter matching an ellipsis). */ 1704 1705#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1706 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1707 1708/* For an arg passed partly in registers and partly in memory, 1709 this is the number of registers used. 1710 For args passed entirely in registers or entirely in memory, zero. */ 1711 1712#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1713 1714/* If PIC, we cannot make sibling calls to global functions 1715 because the PLT requires %ebx live. 1716 If we are returning floats on the register stack, we cannot make 1717 sibling calls to functions that return floats. (The stack adjust 1718 instruction will wind up after the sibcall jump, and not be executed.) */ 1719#define FUNCTION_OK_FOR_SIBCALL(DECL) \ 1720 ((DECL) \ 1721 && (! flag_pic || ! TREE_PUBLIC (DECL)) \ 1722 && (! TARGET_FLOAT_RETURNS_IN_80387 \ 1723 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \ 1724 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl)))))) 1725 1726/* Perform any needed actions needed for a function that is receiving a 1727 variable number of arguments. 1728 1729 CUM is as above. 1730 1731 MODE and TYPE are the mode and type of the current parameter. 1732 1733 PRETEND_SIZE is a variable that should be set to the amount of stack 1734 that must be pushed by the prolog to pretend that our caller pushed 1735 it. 1736 1737 Normally, this macro will push all remaining incoming registers on the 1738 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1739 1740#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1741 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ 1742 (NO_RTL)) 1743 1744/* Define the `__builtin_va_list' type for the ABI. */ 1745#define BUILD_VA_LIST_TYPE(VALIST) \ 1746 ((VALIST) = ix86_build_va_list ()) 1747 1748/* Implement `va_start' for varargs and stdarg. */ 1749#define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \ 1750 ix86_va_start ((STDARG), (VALIST), (NEXTARG)) 1751 1752/* Implement `va_arg'. */ 1753#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ 1754 ix86_va_arg ((VALIST), (TYPE)) 1755 1756/* This macro is invoked at the end of compilation. It is used here to 1757 output code for -fpic that will load the return address into %ebx. */ 1758 1759#undef ASM_FILE_END 1760#define ASM_FILE_END(FILE) ix86_asm_file_end (FILE) 1761 1762/* Output assembler code to FILE to increment profiler label # LABELNO 1763 for profiling a function entry. */ 1764 1765#define FUNCTION_PROFILER(FILE, LABELNO) \ 1766do { \ 1767 if (flag_pic) \ 1768 { \ 1769 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \ 1770 LPREFIX, (LABELNO)); \ 1771 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \ 1772 } \ 1773 else \ 1774 { \ 1775 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ 1776 fprintf ((FILE), "\tcall\t_mcount\n"); \ 1777 } \ 1778} while (0) 1779 1780/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1781 the stack pointer does not matter. The value is tested only in 1782 functions that have frame pointers. 1783 No definition is equivalent to always zero. */ 1784/* Note on the 386 it might be more efficient not to define this since 1785 we have to restore it ourselves from the frame pointer, in order to 1786 use pop */ 1787 1788#define EXIT_IGNORE_STACK 1 1789 1790/* Output assembler code for a block containing the constant parts 1791 of a trampoline, leaving space for the variable parts. */ 1792 1793/* On the 386, the trampoline contains two instructions: 1794 mov #STATIC,ecx 1795 jmp FUNCTION 1796 The trampoline is generated entirely at runtime. The operand of JMP 1797 is the address of FUNCTION relative to the instruction following the 1798 JMP (which is 5 bytes long). */ 1799 1800/* Length in units of the trampoline for entering a nested function. */ 1801 1802#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1803 1804/* Emit RTL insns to initialize the variable parts of a trampoline. 1805 FNADDR is an RTX for the address of the function's pure code. 1806 CXT is an RTX for the static chain value for the function. */ 1807 1808#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1809 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1810 1811/* Definitions for register eliminations. 1812 1813 This is an array of structures. Each structure initializes one pair 1814 of eliminable registers. The "from" register number is given first, 1815 followed by "to". Eliminations of the same "from" register are listed 1816 in order of preference. 1817 1818 There are two registers that can always be eliminated on the i386. 1819 The frame pointer and the arg pointer can be replaced by either the 1820 hard frame pointer or to the stack pointer, depending upon the 1821 circumstances. The hard frame pointer is not used before reload and 1822 so it is not eligible for elimination. */ 1823 1824#define ELIMINABLE_REGS \ 1825{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1826 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1827 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1828 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1829 1830/* Given FROM and TO register numbers, say whether this elimination is 1831 allowed. Frame pointer elimination is automatically handled. 1832 1833 All other eliminations are valid. */ 1834 1835#define CAN_ELIMINATE(FROM, TO) \ 1836 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1837 1838/* Define the offset between two registers, one to be eliminated, and the other 1839 its replacement, at the start of a routine. */ 1840 1841#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1842 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1843 1844/* Addressing modes, and classification of registers for them. */ 1845 1846/* #define HAVE_POST_INCREMENT 0 */ 1847/* #define HAVE_POST_DECREMENT 0 */ 1848 1849/* #define HAVE_PRE_DECREMENT 0 */ 1850/* #define HAVE_PRE_INCREMENT 0 */ 1851 1852/* Macros to check register numbers against specific register classes. */ 1853 1854/* These assume that REGNO is a hard or pseudo reg number. 1855 They give nonzero only if REGNO is a hard reg of the suitable class 1856 or a pseudo reg currently allocated to a suitable hard reg. 1857 Since they use reg_renumber, they are safe only once reg_renumber 1858 has been allocated, which happens in local-alloc.c. */ 1859 1860#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1861 ((REGNO) < STACK_POINTER_REGNUM \ 1862 || (REGNO >= FIRST_REX_INT_REG \ 1863 && (REGNO) <= LAST_REX_INT_REG) \ 1864 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1865 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1866 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1867 1868#define REGNO_OK_FOR_BASE_P(REGNO) \ 1869 ((REGNO) <= STACK_POINTER_REGNUM \ 1870 || (REGNO) == ARG_POINTER_REGNUM \ 1871 || (REGNO) == FRAME_POINTER_REGNUM \ 1872 || (REGNO >= FIRST_REX_INT_REG \ 1873 && (REGNO) <= LAST_REX_INT_REG) \ 1874 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1875 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1876 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1877 1878#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1879 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1880#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1881 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1882 1883/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1884 and check its validity for a certain class. 1885 We have two alternate definitions for each of them. 1886 The usual definition accepts all pseudo regs; the other rejects 1887 them unless they have been allocated suitable hard regs. 1888 The symbol REG_OK_STRICT causes the latter definition to be used. 1889 1890 Most source files want to accept pseudo regs in the hope that 1891 they will get allocated to the class that the insn wants them to be in. 1892 Source files for reload pass need to be strict. 1893 After reload, it makes no difference, since pseudo regs have 1894 been eliminated by then. */ 1895 1896 1897/* Non strict versions, pseudos are ok */ 1898#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1899 (REGNO (X) < STACK_POINTER_REGNUM \ 1900 || (REGNO (X) >= FIRST_REX_INT_REG \ 1901 && REGNO (X) <= LAST_REX_INT_REG) \ 1902 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1903 1904#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1905 (REGNO (X) <= STACK_POINTER_REGNUM \ 1906 || REGNO (X) == ARG_POINTER_REGNUM \ 1907 || REGNO (X) == FRAME_POINTER_REGNUM \ 1908 || (REGNO (X) >= FIRST_REX_INT_REG \ 1909 && REGNO (X) <= LAST_REX_INT_REG) \ 1910 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1911 1912/* Strict versions, hard registers only */ 1913#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1914#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1915 1916#ifndef REG_OK_STRICT 1917#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1918#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1919 1920#else 1921#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1922#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1923#endif 1924 1925/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1926 that is a valid memory address for an instruction. 1927 The MODE argument is the machine mode for the MEM expression 1928 that wants to use this address. 1929 1930 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1931 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1932 1933 See legitimize_pic_address in i386.c for details as to what 1934 constitutes a legitimate address when -fpic is used. */ 1935 1936#define MAX_REGS_PER_ADDRESS 2 1937 1938#define CONSTANT_ADDRESS_P(X) \ 1939 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1940 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1941 || GET_CODE (X) == CONST_DOUBLE) 1942 1943/* Nonzero if the constant value X is a legitimate general operand. 1944 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1945 1946#define LEGITIMATE_CONSTANT_P(X) 1 1947 1948#ifdef REG_OK_STRICT 1949#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1950do { \ 1951 if (legitimate_address_p ((MODE), (X), 1)) \ 1952 goto ADDR; \ 1953} while (0) 1954 1955#else 1956#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1957do { \ 1958 if (legitimate_address_p ((MODE), (X), 0)) \ 1959 goto ADDR; \ 1960} while (0) 1961 1962#endif 1963 1964/* If defined, a C expression to determine the base term of address X. 1965 This macro is used in only one place: `find_base_term' in alias.c. 1966 1967 It is always safe for this macro to not be defined. It exists so 1968 that alias analysis can understand machine-dependent addresses. 1969 1970 The typical use of this macro is to handle addresses containing 1971 a label_ref or symbol_ref within an UNSPEC. */ 1972 1973#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1974 1975/* Try machine-dependent ways of modifying an illegitimate address 1976 to be legitimate. If we find one, return the new, valid address. 1977 This macro is used in only one place: `memory_address' in explow.c. 1978 1979 OLDX is the address as it was before break_out_memory_refs was called. 1980 In some cases it is useful to look at this to decide what needs to be done. 1981 1982 MODE and WIN are passed so that this macro can use 1983 GO_IF_LEGITIMATE_ADDRESS. 1984 1985 It is always safe for this macro to do nothing. It exists to recognize 1986 opportunities to optimize the output. 1987 1988 For the 80386, we handle X+REG by loading X into a register R and 1989 using R+REG. R will go in a general reg and indexing will be used. 1990 However, if REG is a broken-out memory address or multiplication, 1991 nothing needs to be done because REG can certainly go in a general reg. 1992 1993 When -fpic is used, special handling is needed for symbolic references. 1994 See comments by legitimize_pic_address in i386.c for details. */ 1995 1996#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1997do { \ 1998 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 1999 if (memory_address_p ((MODE), (X))) \ 2000 goto WIN; \ 2001} while (0) 2002 2003#define REWRITE_ADDRESS(X) rewrite_address (X) 2004 2005/* Nonzero if the constant value X is a legitimate general operand 2006 when generating PIC code. It is given that flag_pic is on and 2007 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2008 2009#define LEGITIMATE_PIC_OPERAND_P(X) \ 2010 (! SYMBOLIC_CONST (X) \ 2011 || legitimate_pic_address_disp_p (X)) 2012 2013#define SYMBOLIC_CONST(X) \ 2014 (GET_CODE (X) == SYMBOL_REF \ 2015 || GET_CODE (X) == LABEL_REF \ 2016 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 2017 2018/* Go to LABEL if ADDR (a legitimate address expression) 2019 has an effect that depends on the machine mode it is used for. 2020 On the 80386, only postdecrement and postincrement address depend thus 2021 (the amount of decrement or increment being the length of the operand). */ 2022#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2023do { \ 2024 if (GET_CODE (ADDR) == POST_INC \ 2025 || GET_CODE (ADDR) == POST_DEC) \ 2026 goto LABEL; \ 2027} while (0) 2028 2029/* Codes for all the SSE/MMX builtins. */ 2030enum ix86_builtins 2031{ 2032 IX86_BUILTIN_ADDPS, 2033 IX86_BUILTIN_ADDSS, 2034 IX86_BUILTIN_DIVPS, 2035 IX86_BUILTIN_DIVSS, 2036 IX86_BUILTIN_MULPS, 2037 IX86_BUILTIN_MULSS, 2038 IX86_BUILTIN_SUBPS, 2039 IX86_BUILTIN_SUBSS, 2040 2041 IX86_BUILTIN_CMPEQPS, 2042 IX86_BUILTIN_CMPLTPS, 2043 IX86_BUILTIN_CMPLEPS, 2044 IX86_BUILTIN_CMPGTPS, 2045 IX86_BUILTIN_CMPGEPS, 2046 IX86_BUILTIN_CMPNEQPS, 2047 IX86_BUILTIN_CMPNLTPS, 2048 IX86_BUILTIN_CMPNLEPS, 2049 IX86_BUILTIN_CMPNGTPS, 2050 IX86_BUILTIN_CMPNGEPS, 2051 IX86_BUILTIN_CMPORDPS, 2052 IX86_BUILTIN_CMPUNORDPS, 2053 IX86_BUILTIN_CMPNEPS, 2054 IX86_BUILTIN_CMPEQSS, 2055 IX86_BUILTIN_CMPLTSS, 2056 IX86_BUILTIN_CMPLESS, 2057 IX86_BUILTIN_CMPGTSS, 2058 IX86_BUILTIN_CMPGESS, 2059 IX86_BUILTIN_CMPNEQSS, 2060 IX86_BUILTIN_CMPNLTSS, 2061 IX86_BUILTIN_CMPNLESS, 2062 IX86_BUILTIN_CMPNGTSS, 2063 IX86_BUILTIN_CMPNGESS, 2064 IX86_BUILTIN_CMPORDSS, 2065 IX86_BUILTIN_CMPUNORDSS, 2066 IX86_BUILTIN_CMPNESS, 2067 2068 IX86_BUILTIN_COMIEQSS, 2069 IX86_BUILTIN_COMILTSS, 2070 IX86_BUILTIN_COMILESS, 2071 IX86_BUILTIN_COMIGTSS, 2072 IX86_BUILTIN_COMIGESS, 2073 IX86_BUILTIN_COMINEQSS, 2074 IX86_BUILTIN_UCOMIEQSS, 2075 IX86_BUILTIN_UCOMILTSS, 2076 IX86_BUILTIN_UCOMILESS, 2077 IX86_BUILTIN_UCOMIGTSS, 2078 IX86_BUILTIN_UCOMIGESS, 2079 IX86_BUILTIN_UCOMINEQSS, 2080 2081 IX86_BUILTIN_CVTPI2PS, 2082 IX86_BUILTIN_CVTPS2PI, 2083 IX86_BUILTIN_CVTSI2SS, 2084 IX86_BUILTIN_CVTSS2SI, 2085 IX86_BUILTIN_CVTTPS2PI, 2086 IX86_BUILTIN_CVTTSS2SI, 2087 2088 IX86_BUILTIN_MAXPS, 2089 IX86_BUILTIN_MAXSS, 2090 IX86_BUILTIN_MINPS, 2091 IX86_BUILTIN_MINSS, 2092 2093 IX86_BUILTIN_LOADAPS, 2094 IX86_BUILTIN_LOADUPS, 2095 IX86_BUILTIN_STOREAPS, 2096 IX86_BUILTIN_STOREUPS, 2097 IX86_BUILTIN_LOADSS, 2098 IX86_BUILTIN_STORESS, 2099 IX86_BUILTIN_MOVSS, 2100 2101 IX86_BUILTIN_MOVHLPS, 2102 IX86_BUILTIN_MOVLHPS, 2103 IX86_BUILTIN_LOADHPS, 2104 IX86_BUILTIN_LOADLPS, 2105 IX86_BUILTIN_STOREHPS, 2106 IX86_BUILTIN_STORELPS, 2107 2108 IX86_BUILTIN_MASKMOVQ, 2109 IX86_BUILTIN_MOVMSKPS, 2110 IX86_BUILTIN_PMOVMSKB, 2111 2112 IX86_BUILTIN_MOVNTPS, 2113 IX86_BUILTIN_MOVNTQ, 2114 2115 IX86_BUILTIN_PACKSSWB, 2116 IX86_BUILTIN_PACKSSDW, 2117 IX86_BUILTIN_PACKUSWB, 2118 2119 IX86_BUILTIN_PADDB, 2120 IX86_BUILTIN_PADDW, 2121 IX86_BUILTIN_PADDD, 2122 IX86_BUILTIN_PADDSB, 2123 IX86_BUILTIN_PADDSW, 2124 IX86_BUILTIN_PADDUSB, 2125 IX86_BUILTIN_PADDUSW, 2126 IX86_BUILTIN_PSUBB, 2127 IX86_BUILTIN_PSUBW, 2128 IX86_BUILTIN_PSUBD, 2129 IX86_BUILTIN_PSUBSB, 2130 IX86_BUILTIN_PSUBSW, 2131 IX86_BUILTIN_PSUBUSB, 2132 IX86_BUILTIN_PSUBUSW, 2133 2134 IX86_BUILTIN_PAND, 2135 IX86_BUILTIN_PANDN, 2136 IX86_BUILTIN_POR, 2137 IX86_BUILTIN_PXOR, 2138 2139 IX86_BUILTIN_PAVGB, 2140 IX86_BUILTIN_PAVGW, 2141 2142 IX86_BUILTIN_PCMPEQB, 2143 IX86_BUILTIN_PCMPEQW, 2144 IX86_BUILTIN_PCMPEQD, 2145 IX86_BUILTIN_PCMPGTB, 2146 IX86_BUILTIN_PCMPGTW, 2147 IX86_BUILTIN_PCMPGTD, 2148 2149 IX86_BUILTIN_PEXTRW, 2150 IX86_BUILTIN_PINSRW, 2151 2152 IX86_BUILTIN_PMADDWD, 2153 2154 IX86_BUILTIN_PMAXSW, 2155 IX86_BUILTIN_PMAXUB, 2156 IX86_BUILTIN_PMINSW, 2157 IX86_BUILTIN_PMINUB, 2158 2159 IX86_BUILTIN_PMULHUW, 2160 IX86_BUILTIN_PMULHW, 2161 IX86_BUILTIN_PMULLW, 2162 2163 IX86_BUILTIN_PSADBW, 2164 IX86_BUILTIN_PSHUFW, 2165 2166 IX86_BUILTIN_PSLLW, 2167 IX86_BUILTIN_PSLLD, 2168 IX86_BUILTIN_PSLLQ, 2169 IX86_BUILTIN_PSRAW, 2170 IX86_BUILTIN_PSRAD, 2171 IX86_BUILTIN_PSRLW, 2172 IX86_BUILTIN_PSRLD, 2173 IX86_BUILTIN_PSRLQ, 2174 IX86_BUILTIN_PSLLWI, 2175 IX86_BUILTIN_PSLLDI, 2176 IX86_BUILTIN_PSLLQI, 2177 IX86_BUILTIN_PSRAWI, 2178 IX86_BUILTIN_PSRADI, 2179 IX86_BUILTIN_PSRLWI, 2180 IX86_BUILTIN_PSRLDI, 2181 IX86_BUILTIN_PSRLQI, 2182 2183 IX86_BUILTIN_PUNPCKHBW, 2184 IX86_BUILTIN_PUNPCKHWD, 2185 IX86_BUILTIN_PUNPCKHDQ, 2186 IX86_BUILTIN_PUNPCKLBW, 2187 IX86_BUILTIN_PUNPCKLWD, 2188 IX86_BUILTIN_PUNPCKLDQ, 2189 2190 IX86_BUILTIN_SHUFPS, 2191 2192 IX86_BUILTIN_RCPPS, 2193 IX86_BUILTIN_RCPSS, 2194 IX86_BUILTIN_RSQRTPS, 2195 IX86_BUILTIN_RSQRTSS, 2196 IX86_BUILTIN_SQRTPS, 2197 IX86_BUILTIN_SQRTSS, 2198 2199 IX86_BUILTIN_UNPCKHPS, 2200 IX86_BUILTIN_UNPCKLPS, 2201 2202 IX86_BUILTIN_ANDPS, 2203 IX86_BUILTIN_ANDNPS, 2204 IX86_BUILTIN_ORPS, 2205 IX86_BUILTIN_XORPS, 2206 2207 IX86_BUILTIN_EMMS, 2208 IX86_BUILTIN_LDMXCSR, 2209 IX86_BUILTIN_STMXCSR, 2210 IX86_BUILTIN_SFENCE, 2211 2212 /* 3DNow! Original */ 2213 IX86_BUILTIN_FEMMS, 2214 IX86_BUILTIN_PAVGUSB, 2215 IX86_BUILTIN_PF2ID, 2216 IX86_BUILTIN_PFACC, 2217 IX86_BUILTIN_PFADD, 2218 IX86_BUILTIN_PFCMPEQ, 2219 IX86_BUILTIN_PFCMPGE, 2220 IX86_BUILTIN_PFCMPGT, 2221 IX86_BUILTIN_PFMAX, 2222 IX86_BUILTIN_PFMIN, 2223 IX86_BUILTIN_PFMUL, 2224 IX86_BUILTIN_PFRCP, 2225 IX86_BUILTIN_PFRCPIT1, 2226 IX86_BUILTIN_PFRCPIT2, 2227 IX86_BUILTIN_PFRSQIT1, 2228 IX86_BUILTIN_PFRSQRT, 2229 IX86_BUILTIN_PFSUB, 2230 IX86_BUILTIN_PFSUBR, 2231 IX86_BUILTIN_PI2FD, 2232 IX86_BUILTIN_PMULHRW, 2233 2234 /* 3DNow! Athlon Extensions */ 2235 IX86_BUILTIN_PF2IW, 2236 IX86_BUILTIN_PFNACC, 2237 IX86_BUILTIN_PFPNACC, 2238 IX86_BUILTIN_PI2FW, 2239 IX86_BUILTIN_PSWAPDSI, 2240 IX86_BUILTIN_PSWAPDSF, 2241 2242 IX86_BUILTIN_SSE_ZERO, 2243 IX86_BUILTIN_MMX_ZERO, 2244 2245 IX86_BUILTIN_MAX 2246}; 2247 2248/* Define this macro if references to a symbol must be treated 2249 differently depending on something about the variable or 2250 function named by the symbol (such as what section it is in). 2251 2252 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol 2253 so that we may access it directly in the GOT. */ 2254 2255#define ENCODE_SECTION_INFO(DECL) \ 2256do { \ 2257 if (flag_pic) \ 2258 { \ 2259 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2260 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ 2261 \ 2262 if (GET_CODE (rtl) == MEM) \ 2263 { \ 2264 if (TARGET_DEBUG_ADDR \ 2265 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \ 2266 { \ 2267 fprintf (stderr, "Encode %s, public = %d\n", \ 2268 IDENTIFIER_POINTER (DECL_NAME (DECL)), \ 2269 TREE_PUBLIC (DECL)); \ 2270 } \ 2271 \ 2272 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ 2273 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ 2274 || ! TREE_PUBLIC (DECL)); \ 2275 } \ 2276 } \ 2277} while (0) 2278 2279/* The `FINALIZE_PIC' macro serves as a hook to emit these special 2280 codes once the function is being compiled into assembly code, but 2281 not before. (It is not done before, because in the case of 2282 compiling an inline function, it would lead to multiple PIC 2283 prologues being included in functions which used inline functions 2284 and were compiled to assembly language.) */ 2285 2286#define FINALIZE_PIC \ 2287 (current_function_uses_pic_offset_table |= current_function_profile) 2288 2289 2290/* Max number of args passed in registers. If this is more than 3, we will 2291 have problems with ebx (register #4), since it is a caller save register and 2292 is also used as the pic register in ELF. So for now, don't allow more than 2293 3 registers to be passed in registers. */ 2294 2295#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 2296 2297#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0) 2298 2299 2300/* Specify the machine mode that this machine uses 2301 for the index in the tablejump instruction. */ 2302#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 2303 2304/* Define as C expression which evaluates to nonzero if the tablejump 2305 instruction expects the table to contain offsets from the address of the 2306 table. 2307 Do not define this if the table should contain absolute addresses. */ 2308/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2309 2310/* Define this as 1 if `char' should by default be signed; else as 0. */ 2311#define DEFAULT_SIGNED_CHAR 1 2312 2313/* Number of bytes moved into a data cache for a single prefetch operation. */ 2314#define PREFETCH_BLOCK ix86_cost->prefetch_block 2315 2316/* Number of prefetch operations that can be done in parallel. */ 2317#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 2318 2319/* Max number of bytes we can move from memory to memory 2320 in one reasonably fast instruction. */ 2321#define MOVE_MAX 16 2322 2323/* MOVE_MAX_PIECES is the number of bytes at a time which we can 2324 move efficiently, as opposed to MOVE_MAX which is the maximum 2325 number of bytes we can move with a single instruction. */ 2326#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 2327 2328/* If a memory-to-memory move would take MOVE_RATIO or more simple 2329 move-instruction pairs, we will do a movstr or libcall instead. 2330 Increasing the value will always make code faster, but eventually 2331 incurs high cost in increased code size. 2332 2333 If you don't define this, a reasonable default is used. */ 2334 2335#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 2336 2337/* Define if shifts truncate the shift count 2338 which implies one can omit a sign-extension or zero-extension 2339 of a shift count. */ 2340/* On i386, shifts do truncate the count. But bit opcodes don't. */ 2341 2342/* #define SHIFT_COUNT_TRUNCATED */ 2343 2344/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2345 is done just by pretending it is already truncated. */ 2346#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2347 2348/* We assume that the store-condition-codes instructions store 0 for false 2349 and some other value for true. This is the value stored for true. */ 2350 2351#define STORE_FLAG_VALUE 1 2352 2353/* When a prototype says `char' or `short', really pass an `int'. 2354 (The 386 can't easily push less than an int.) */ 2355 2356#define PROMOTE_PROTOTYPES (!TARGET_64BIT) 2357 2358/* A macro to update M and UNSIGNEDP when an object whose type is 2359 TYPE and which has the specified mode and signedness is to be 2360 stored in a register. This macro is only called when TYPE is a 2361 scalar type. 2362 2363 On i386 it is sometimes useful to promote HImode and QImode 2364 quantities to SImode. The choice depends on target type. */ 2365 2366#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2367do { \ 2368 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 2369 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 2370 (MODE) = SImode; \ 2371} while (0) 2372 2373/* Specify the machine mode that pointers have. 2374 After generation of rtl, the compiler makes no further distinction 2375 between pointers and any other objects of this machine mode. */ 2376#define Pmode (TARGET_64BIT ? DImode : SImode) 2377 2378/* A function address in a call instruction 2379 is a byte address (for indexing purposes) 2380 so give the MEM rtx a byte's mode. */ 2381#define FUNCTION_MODE QImode 2382 2383/* A part of a C `switch' statement that describes the relative costs 2384 of constant RTL expressions. It must contain `case' labels for 2385 expression codes `const_int', `const', `symbol_ref', `label_ref' 2386 and `const_double'. Each case must ultimately reach a `return' 2387 statement to return the relative cost of the use of that kind of 2388 constant value in an expression. The cost may depend on the 2389 precise value of the constant, which is available for examination 2390 in X, and the rtx code of the expression in which it is contained, 2391 found in OUTER_CODE. 2392 2393 CODE is the expression code--redundant, since it can be obtained 2394 with `GET_CODE (X)'. */ 2395 2396#define CONST_COSTS(RTX, CODE, OUTER_CODE) \ 2397 case CONST_INT: \ 2398 case CONST: \ 2399 case LABEL_REF: \ 2400 case SYMBOL_REF: \ 2401 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \ 2402 return 3; \ 2403 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \ 2404 return 2; \ 2405 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \ 2406 \ 2407 case CONST_DOUBLE: \ 2408 { \ 2409 int code; \ 2410 if (GET_MODE (RTX) == VOIDmode) \ 2411 return 0; \ 2412 \ 2413 code = standard_80387_constant_p (RTX); \ 2414 return code == 1 ? 1 : \ 2415 code == 2 ? 2 : \ 2416 3; \ 2417 } 2418 2419/* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ 2420#define TOPLEVEL_COSTS_N_INSNS(N) \ 2421 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) 2422 2423/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. 2424 This can be used, for example, to indicate how costly a multiply 2425 instruction is. In writing this macro, you can use the construct 2426 `COSTS_N_INSNS (N)' to specify a cost equal to N fast 2427 instructions. OUTER_CODE is the code of the expression in which X 2428 is contained. 2429 2430 This macro is optional; do not define it if the default cost 2431 assumptions are adequate for the target machine. */ 2432 2433#define RTX_COSTS(X, CODE, OUTER_CODE) \ 2434 case ZERO_EXTEND: \ 2435 /* The zero extensions is often completely free on x86_64, so make \ 2436 it as cheap as possible. */ \ 2437 if (TARGET_64BIT && GET_MODE (X) == DImode \ 2438 && GET_MODE (XEXP (X, 0)) == SImode) \ 2439 { \ 2440 total = 1; goto egress_rtx_costs; \ 2441 } \ 2442 else \ 2443 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \ 2444 ix86_cost->add : ix86_cost->movzx); \ 2445 break; \ 2446 case SIGN_EXTEND: \ 2447 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \ 2448 break; \ 2449 case ASHIFT: \ 2450 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 2451 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \ 2452 { \ 2453 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2454 if (value == 1) \ 2455 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2456 if ((value == 2 || value == 3) \ 2457 && !TARGET_DECOMPOSE_LEA \ 2458 && ix86_cost->lea <= ix86_cost->shift_const) \ 2459 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ 2460 } \ 2461 /* fall through */ \ 2462 \ 2463 case ROTATE: \ 2464 case ASHIFTRT: \ 2465 case LSHIFTRT: \ 2466 case ROTATERT: \ 2467 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \ 2468 { \ 2469 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2470 { \ 2471 if (INTVAL (XEXP (X, 1)) > 32) \ 2472 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ 2473 else \ 2474 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ 2475 } \ 2476 else \ 2477 { \ 2478 if (GET_CODE (XEXP (X, 1)) == AND) \ 2479 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ 2480 else \ 2481 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ 2482 } \ 2483 } \ 2484 else \ 2485 { \ 2486 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2487 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ 2488 else \ 2489 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ 2490 } \ 2491 break; \ 2492 \ 2493 case MULT: \ 2494 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2495 { \ 2496 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ 2497 int nbits = 0; \ 2498 \ 2499 while (value != 0) \ 2500 { \ 2501 nbits++; \ 2502 value >>= 1; \ 2503 } \ 2504 \ 2505 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2506 + nbits * ix86_cost->mult_bit); \ 2507 } \ 2508 else /* This is arbitrary */ \ 2509 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ 2510 + 7 * ix86_cost->mult_bit); \ 2511 \ 2512 case DIV: \ 2513 case UDIV: \ 2514 case MOD: \ 2515 case UMOD: \ 2516 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ 2517 \ 2518 case PLUS: \ 2519 if (!TARGET_DECOMPOSE_LEA \ 2520 && INTEGRAL_MODE_P (GET_MODE (X)) \ 2521 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \ 2522 { \ 2523 if (GET_CODE (XEXP (X, 0)) == PLUS \ 2524 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ 2525 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ 2526 && CONSTANT_P (XEXP (X, 1))) \ 2527 { \ 2528 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\ 2529 if (val == 2 || val == 4 || val == 8) \ 2530 { \ 2531 return (COSTS_N_INSNS (ix86_cost->lea) \ 2532 + rtx_cost (XEXP (XEXP (X, 0), 1), \ 2533 (OUTER_CODE)) \ 2534 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \ 2535 (OUTER_CODE)) \ 2536 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2537 } \ 2538 } \ 2539 else if (GET_CODE (XEXP (X, 0)) == MULT \ 2540 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ 2541 { \ 2542 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ 2543 if (val == 2 || val == 4 || val == 8) \ 2544 { \ 2545 return (COSTS_N_INSNS (ix86_cost->lea) \ 2546 + rtx_cost (XEXP (XEXP (X, 0), 0), \ 2547 (OUTER_CODE)) \ 2548 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2549 } \ 2550 } \ 2551 else if (GET_CODE (XEXP (X, 0)) == PLUS) \ 2552 { \ 2553 return (COSTS_N_INSNS (ix86_cost->lea) \ 2554 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \ 2555 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \ 2556 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ 2557 } \ 2558 } \ 2559 \ 2560 /* fall through */ \ 2561 case AND: \ 2562 case IOR: \ 2563 case XOR: \ 2564 case MINUS: \ 2565 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2566 return (COSTS_N_INSNS (ix86_cost->add) * 2 \ 2567 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \ 2568 << (GET_MODE (XEXP (X, 0)) != DImode)) \ 2569 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \ 2570 << (GET_MODE (XEXP (X, 1)) != DImode))); \ 2571 \ 2572 /* fall through */ \ 2573 case NEG: \ 2574 case NOT: \ 2575 if (!TARGET_64BIT && GET_MODE (X) == DImode) \ 2576 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ 2577 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ 2578 \ 2579 egress_rtx_costs: \ 2580 break; 2581 2582 2583/* An expression giving the cost of an addressing mode that contains 2584 ADDRESS. If not defined, the cost is computed from the ADDRESS 2585 expression and the `CONST_COSTS' values. 2586 2587 For most CISC machines, the default cost is a good approximation 2588 of the true cost of the addressing mode. However, on RISC 2589 machines, all instructions normally have the same length and 2590 execution time. Hence all addresses will have equal costs. 2591 2592 In cases where more than one form of an address is known, the form 2593 with the lowest cost will be used. If multiple forms have the 2594 same, lowest, cost, the one that is the most complex will be used. 2595 2596 For example, suppose an address that is equal to the sum of a 2597 register and a constant is used twice in the same basic block. 2598 When this macro is not defined, the address will be computed in a 2599 register and memory references will be indirect through that 2600 register. On machines where the cost of the addressing mode 2601 containing the sum is no higher than that of a simple indirect 2602 reference, this will produce an additional instruction and 2603 possibly require an additional register. Proper specification of 2604 this macro eliminates this overhead for such machines. 2605 2606 Similar use of this macro is made in strength reduction of loops. 2607 2608 ADDRESS need not be valid as an address. In such a case, the cost 2609 is not relevant and can be any value; invalid addresses need not be 2610 assigned a different cost. 2611 2612 On machines where an address involving more than one register is as 2613 cheap as an address computation involving only one register, 2614 defining `ADDRESS_COST' to reflect this can cause two registers to 2615 be live over a region of code where only one would have been if 2616 `ADDRESS_COST' were not defined in that manner. This effect should 2617 be considered in the definition of this macro. Equivalent costs 2618 should probably only be given to addresses with different numbers 2619 of registers on machines with lots of registers. 2620 2621 This macro will normally either not be defined or be defined as a 2622 constant. 2623 2624 For i386, it is better to use a complex address than let gcc copy 2625 the address into a reg and make a new pseudo. But not if the address 2626 requires to two regs - that would mean more pseudos with longer 2627 lifetimes. */ 2628 2629#define ADDRESS_COST(RTX) \ 2630 ix86_address_cost (RTX) 2631 2632/* A C expression for the cost of moving data from a register in class FROM to 2633 one in class TO. The classes are expressed using the enumeration values 2634 such as `GENERAL_REGS'. A value of 2 is the default; other values are 2635 interpreted relative to that. 2636 2637 It is not required that the cost always equal 2 when FROM is the same as TO; 2638 on some machines it is expensive to move between registers if they are not 2639 general registers. */ 2640 2641#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2642 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 2643 2644/* A C expression for the cost of moving data of mode M between a 2645 register and memory. A value of 2 is the default; this cost is 2646 relative to those in `REGISTER_MOVE_COST'. 2647 2648 If moving between registers and memory is more expensive than 2649 between two registers, you should define this macro to express the 2650 relative cost. */ 2651 2652#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 2653 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 2654 2655/* A C expression for the cost of a branch instruction. A value of 1 2656 is the default; other values are interpreted relative to that. */ 2657 2658#define BRANCH_COST ix86_branch_cost 2659 2660/* Define this macro as a C expression which is nonzero if accessing 2661 less than a word of memory (i.e. a `char' or a `short') is no 2662 faster than accessing a word of memory, i.e., if such access 2663 require more than one instruction or if there is no difference in 2664 cost between byte and (aligned) word loads. 2665 2666 When this macro is not defined, the compiler will access a field by 2667 finding the smallest containing object; when it is defined, a 2668 fullword load will be used if alignment permits. Unless bytes 2669 accesses are faster than word accesses, using word accesses is 2670 preferable since it may eliminate subsequent memory access if 2671 subsequent accesses occur to other fields in the same word of the 2672 structure, but to different bytes. */ 2673 2674#define SLOW_BYTE_ACCESS 0 2675 2676/* Nonzero if access to memory by shorts is slow and undesirable. */ 2677#define SLOW_SHORT_ACCESS 0 2678 2679/* Define this macro to be the value 1 if unaligned accesses have a 2680 cost many times greater than aligned accesses, for example if they 2681 are emulated in a trap handler. 2682 2683 When this macro is non-zero, the compiler will act as if 2684 `STRICT_ALIGNMENT' were non-zero when generating code for block 2685 moves. This can cause significantly more instructions to be 2686 produced. Therefore, do not set this macro non-zero if unaligned 2687 accesses only add a cycle or two to the time for a memory access. 2688 2689 If the value of this macro is always zero, it need not be defined. */ 2690 2691/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2692 2693/* Define this macro to inhibit strength reduction of memory 2694 addresses. (On some machines, such strength reduction seems to do 2695 harm rather than good.) */ 2696 2697/* #define DONT_REDUCE_ADDR */ 2698 2699/* Define this macro if it is as good or better to call a constant 2700 function address than to call an address kept in a register. 2701 2702 Desirable on the 386 because a CALL with a constant address is 2703 faster than one with a register address. */ 2704 2705#define NO_FUNCTION_CSE 2706 2707/* Define this macro if it is as good or better for a function to call 2708 itself with an explicit address than to call an address kept in a 2709 register. */ 2710 2711#define NO_RECURSIVE_FUNCTION_CSE 2712 2713/* Add any extra modes needed to represent the condition code. 2714 2715 For the i386, we need separate modes when floating-point 2716 equality comparisons are being done. 2717 2718 Add CCNO to indicate comparisons against zero that requires 2719 Overflow flag to be unset. Sign bit test is used instead and 2720 thus can be used to form "a&b>0" type of tests. 2721 2722 Add CCGC to indicate comparisons agains zero that allows 2723 unspecified garbage in the Carry flag. This mode is used 2724 by inc/dec instructions. 2725 2726 Add CCGOC to indicate comparisons agains zero that allows 2727 unspecified garbage in the Carry and Overflow flag. This 2728 mode is used to simulate comparisons of (a-b) and (a+b) 2729 against zero using sub/cmp/add operations. 2730 2731 Add CCZ to indicate that only the Zero flag is valid. */ 2732 2733#define EXTRA_CC_MODES \ 2734 CC (CCGCmode, "CCGC") \ 2735 CC (CCGOCmode, "CCGOC") \ 2736 CC (CCNOmode, "CCNO") \ 2737 CC (CCZmode, "CCZ") \ 2738 CC (CCFPmode, "CCFP") \ 2739 CC (CCFPUmode, "CCFPU") 2740 2741/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2742 return the mode to be used for the comparison. 2743 2744 For floating-point equality comparisons, CCFPEQmode should be used. 2745 VOIDmode should be used in all other cases. 2746 2747 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2748 possible, to allow for more combinations. */ 2749 2750#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2751 2752/* Return non-zero if MODE implies a floating point inequality can be 2753 reversed. */ 2754 2755#define REVERSIBLE_CC_MODE(MODE) 1 2756 2757/* A C expression whose value is reversed condition code of the CODE for 2758 comparison done in CC_MODE mode. */ 2759#define REVERSE_CONDITION(CODE, MODE) \ 2760 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ 2761 : reverse_condition_maybe_unordered (CODE)) 2762 2763 2764/* Control the assembler format that we output, to the extent 2765 this does not vary between assemblers. */ 2766 2767/* How to refer to registers in assembler output. 2768 This sequence is indexed by compiler's hard-register-number (see above). */ 2769 2770/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" 2771 For non floating point regs, the following are the HImode names. 2772 2773 For float regs, the stack top is sometimes referred to as "%st(0)" 2774 instead of just "%st". PRINT_REG handles this with the "y" code. */ 2775 2776#undef HI_REGISTER_NAMES 2777#define HI_REGISTER_NAMES \ 2778{"ax","dx","cx","bx","si","di","bp","sp", \ 2779 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ 2780 "flags","fpsr", "dirflag", "frame", \ 2781 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2782 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 2783 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2784 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 2785 2786#define REGISTER_NAMES HI_REGISTER_NAMES 2787 2788/* Table of additional register names to use in user input. */ 2789 2790#define ADDITIONAL_REGISTER_NAMES \ 2791{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2792 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2793 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2794 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2795 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2796 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2797 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ 2798 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } 2799 2800/* Note we are omitting these since currently I don't know how 2801to get gcc to use these, since they want the same but different 2802number as al, and ax. 2803*/ 2804 2805#define QI_REGISTER_NAMES \ 2806{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2807 2808/* These parallel the array above, and can be used to access bits 8:15 2809 of regs 0 through 3. */ 2810 2811#define QI_HIGH_REGISTER_NAMES \ 2812{"ah", "dh", "ch", "bh", } 2813 2814/* How to renumber registers for dbx and gdb. */ 2815 2816#define DBX_REGISTER_NUMBER(N) \ 2817 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2818 2819extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2820extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2821extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2822 2823/* Before the prologue, RA is at 0(%esp). */ 2824#define INCOMING_RETURN_ADDR_RTX \ 2825 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2826 2827/* After the prologue, RA is at -4(AP) in the current frame. */ 2828#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2829 ((COUNT) == 0 \ 2830 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2831 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2832 2833/* PC is dbx register 8; let's use that column for RA. */ 2834#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2835 2836/* Before the prologue, the top of the frame is at 4(%esp). */ 2837#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2838 2839/* Describe how we implement __builtin_eh_return. */ 2840#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2841#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2842 2843 2844/* Select a format to encode pointers in exception handling data. CODE 2845 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2846 true if the symbol may be affected by dynamic relocations. 2847 2848 ??? All x86 object file formats are capable of representing this. 2849 After all, the relocation needed is the same as for the call insn. 2850 Whether or not a particular assembler allows us to enter such, I 2851 guess we'll have to see. */ 2852#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2853 (flag_pic \ 2854 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 2855 : DW_EH_PE_absptr) 2856 2857/* This is how to output the definition of a user-level label named NAME, 2858 such as the label on a static function or variable NAME. */ 2859 2860#define ASM_OUTPUT_LABEL(FILE, NAME) \ 2861 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE))) 2862 2863/* Store in OUTPUT a string (made with alloca) containing 2864 an assembler-name for a local static variable named NAME. 2865 LABELNO is an integer which is different for each call. */ 2866 2867#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2868( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2869 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2870 2871/* This is how to output an insn to push a register on the stack. 2872 It need not be very fast code. */ 2873 2874#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2875 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]) 2876 2877/* This is how to output an insn to pop a register from the stack. 2878 It need not be very fast code. */ 2879 2880#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2881 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]) 2882 2883/* This is how to output an element of a case-vector that is absolute. */ 2884 2885#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2886 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2887 2888/* This is how to output an element of a case-vector that is relative. */ 2889 2890#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2891 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2892 2893/* Under some conditions we need jump tables in the text section, because 2894 the assembler cannot handle label differences between sections. */ 2895 2896#define JUMP_TABLES_IN_TEXT_SECTION \ 2897 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 2898 2899/* A C statement that outputs an address constant appropriate to 2900 for DWARF debugging. */ 2901 2902#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ 2903 i386_dwarf_output_addr_const ((FILE), (X)) 2904 2905/* Either simplify a location expression, or return the original. */ 2906 2907#define ASM_SIMPLIFY_DWARF_ADDR(X) \ 2908 i386_simplify_dwarf_addr (X) 2909 2910/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2911 and switch back. For x86 we do this only to save a few bytes that 2912 would otherwise be unused in the text section. */ 2913#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2914 asm (SECTION_OP "\n\t" \ 2915 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2916 TEXT_SECTION_ASM_OP); 2917 2918/* Print operand X (an rtx) in assembler syntax to file FILE. 2919 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2920 Effect of various CODE letters is described in i386.c near 2921 print_operand function. */ 2922 2923#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2924 ((CODE) == '*' || (CODE) == '+') 2925 2926/* Print the name of a register based on its machine mode and number. 2927 If CODE is 'w', pretend the mode is HImode. 2928 If CODE is 'b', pretend the mode is QImode. 2929 If CODE is 'k', pretend the mode is SImode. 2930 If CODE is 'q', pretend the mode is DImode. 2931 If CODE is 'h', pretend the reg is the `high' byte register. 2932 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ 2933 2934#define PRINT_REG(X, CODE, FILE) \ 2935 print_reg ((X), (CODE), (FILE)) 2936 2937#define PRINT_OPERAND(FILE, X, CODE) \ 2938 print_operand ((FILE), (X), (CODE)) 2939 2940#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2941 print_operand_address ((FILE), (ADDR)) 2942 2943/* Print the name of a register for based on its machine mode and number. 2944 This macro is used to print debugging output. 2945 This macro is different from PRINT_REG in that it may be used in 2946 programs that are not linked with aux-output.o. */ 2947 2948#define DEBUG_PRINT_REG(X, CODE, FILE) \ 2949 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ 2950 static const char * const qi_name[] = QI_REGISTER_NAMES; \ 2951 fprintf ((FILE), "%d ", REGNO (X)); \ 2952 if (REGNO (X) == FLAGS_REG) \ 2953 { fputs ("flags", (FILE)); break; } \ 2954 if (REGNO (X) == DIRFLAG_REG) \ 2955 { fputs ("dirflag", (FILE)); break; } \ 2956 if (REGNO (X) == FPSR_REG) \ 2957 { fputs ("fpsr", (FILE)); break; } \ 2958 if (REGNO (X) == ARG_POINTER_REGNUM) \ 2959 { fputs ("argp", (FILE)); break; } \ 2960 if (REGNO (X) == FRAME_POINTER_REGNUM) \ 2961 { fputs ("frame", (FILE)); break; } \ 2962 if (STACK_TOP_P (X)) \ 2963 { fputs ("st(0)", (FILE)); break; } \ 2964 if (FP_REG_P (X)) \ 2965 { fputs (hi_name[REGNO(X)], (FILE)); break; } \ 2966 if (REX_INT_REG_P (X)) \ 2967 { \ 2968 switch (GET_MODE_SIZE (GET_MODE (X))) \ 2969 { \ 2970 default: \ 2971 case 8: \ 2972 fprintf ((FILE), "r%i", REGNO (X) \ 2973 - FIRST_REX_INT_REG + 8); \ 2974 break; \ 2975 case 4: \ 2976 fprintf ((FILE), "r%id", REGNO (X) \ 2977 - FIRST_REX_INT_REG + 8); \ 2978 break; \ 2979 case 2: \ 2980 fprintf ((FILE), "r%iw", REGNO (X) \ 2981 - FIRST_REX_INT_REG + 8); \ 2982 break; \ 2983 case 1: \ 2984 fprintf ((FILE), "r%ib", REGNO (X) \ 2985 - FIRST_REX_INT_REG + 8); \ 2986 break; \ 2987 } \ 2988 break; \ 2989 } \ 2990 switch (GET_MODE_SIZE (GET_MODE (X))) \ 2991 { \ 2992 case 8: \ 2993 fputs ("r", (FILE)); \ 2994 fputs (hi_name[REGNO (X)], (FILE)); \ 2995 break; \ 2996 default: \ 2997 fputs ("e", (FILE)); \ 2998 case 2: \ 2999 fputs (hi_name[REGNO (X)], (FILE)); \ 3000 break; \ 3001 case 1: \ 3002 fputs (qi_name[REGNO (X)], (FILE)); \ 3003 break; \ 3004 } \ 3005 } while (0) 3006 3007/* a letter which is not needed by the normal asm syntax, which 3008 we can use for operand syntax in the extended asm */ 3009 3010#define ASM_OPERAND_LETTER '#' 3011#define RET return "" 3012#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 3013 3014/* Define the codes that are matched by predicates in i386.c. */ 3015 3016#define PREDICATE_CODES \ 3017 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ 3018 SYMBOL_REF, LABEL_REF, CONST}}, \ 3019 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3020 SYMBOL_REF, LABEL_REF, CONST}}, \ 3021 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ 3022 SYMBOL_REF, LABEL_REF, CONST}}, \ 3023 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 3024 SYMBOL_REF, LABEL_REF, CONST}}, \ 3025 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3026 SYMBOL_REF, LABEL_REF, CONST}}, \ 3027 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 3028 SYMBOL_REF, LABEL_REF, CONST}}, \ 3029 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3030 SYMBOL_REF, LABEL_REF}}, \ 3031 {"shiftdi_operand", {SUBREG, REG, MEM}}, \ 3032 {"const_int_1_operand", {CONST_INT}}, \ 3033 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 3034 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3035 LABEL_REF, SUBREG, REG, MEM}}, \ 3036 {"pic_symbolic_operand", {CONST}}, \ 3037 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ 3038 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ 3039 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ 3040 {"const1_operand", {CONST_INT}}, \ 3041 {"const248_operand", {CONST_INT}}, \ 3042 {"incdec_operand", {CONST_INT}}, \ 3043 {"mmx_reg_operand", {REG}}, \ 3044 {"reg_no_sp_operand", {SUBREG, REG}}, \ 3045 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 3046 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ 3047 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ 3048 {"q_regs_operand", {SUBREG, REG}}, \ 3049 {"non_q_regs_operand", {SUBREG, REG}}, \ 3050 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ 3051 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ 3052 GE, UNGE, LTGT, UNEQ}}, \ 3053 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ 3054 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ 3055 }}, \ 3056 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ 3057 GTU, UNORDERED, ORDERED, UNLE, UNLT, \ 3058 UNGE, UNGT, LTGT, UNEQ }}, \ 3059 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ 3060 {"ext_register_operand", {SUBREG, REG}}, \ 3061 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ 3062 {"mult_operator", {MULT}}, \ 3063 {"div_operator", {DIV}}, \ 3064 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ 3065 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ 3066 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ 3067 LSHIFTRT, ROTATERT}}, \ 3068 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ 3069 {"memory_displacement_operand", {MEM}}, \ 3070 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3071 LABEL_REF, SUBREG, REG, MEM, AND}}, \ 3072 {"long_memory_operand", {MEM}}, 3073 3074/* A list of predicates that do special things with modes, and so 3075 should not elicit warnings for VOIDmode match_operand. */ 3076 3077#define SPECIAL_MODE_PREDICATES \ 3078 "ext_register_operand", 3079 3080/* CM_32 is used by 32bit ABI 3081 CM_SMALL is small model assuming that all code and data fits in the first 3082 31bits of address space. 3083 CM_KERNEL is model assuming that all code and data fits in the negative 3084 31bits of address space. 3085 CM_MEDIUM is model assuming that code fits in the first 31bits of address 3086 space. Size of data is unlimited. 3087 CM_LARGE is model making no assumptions about size of particular sections. 3088 3089 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt 3090 tables first in 31bits of address space. 3091 */ 3092enum cmodel { 3093 CM_32, 3094 CM_SMALL, 3095 CM_KERNEL, 3096 CM_MEDIUM, 3097 CM_LARGE, 3098 CM_SMALL_PIC 3099}; 3100 3101/* Size of the RED_ZONE area. */ 3102#define RED_ZONE_SIZE 128 3103/* Reserved area of the red zone for temporaries. */ 3104#define RED_ZONE_RESERVE 8 3105extern const char *ix86_debug_arg_string, *ix86_debug_addr_string; 3106 3107enum asm_dialect { 3108 ASM_ATT, 3109 ASM_INTEL 3110}; 3111extern const char *ix86_asm_string; 3112extern enum asm_dialect ix86_asm_dialect; 3113/* Value of -mcmodel specified by user. */ 3114extern const char *ix86_cmodel_string; 3115extern enum cmodel ix86_cmodel; 3116 3117/* Variables in i386.c */ 3118extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */ 3119extern const char *ix86_arch_string; /* for -march=<xxx> */ 3120extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */ 3121extern const char *ix86_regparm_string; /* # registers to use to pass args */ 3122extern const char *ix86_align_loops_string; /* power of two alignment for loops */ 3123extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */ 3124extern const char *ix86_align_funcs_string; /* power of two alignment for functions */ 3125extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */ 3126extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */ 3127extern int ix86_regparm; /* ix86_regparm_string as a number */ 3128extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */ 3129extern int ix86_branch_cost; /* values 1-5: see jump.c */ 3130extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */ 3131extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 3132extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 3133 3134/* To properly truncate FP values into integers, we need to set i387 control 3135 word. We can't emit proper mode switching code before reload, as spills 3136 generated by reload may truncate values incorrectly, but we still can avoid 3137 redundant computation of new control word by the mode switching pass. 3138 The fldcw instructions are still emitted redundantly, but this is probably 3139 not going to be noticeable problem, as most CPUs do have fast path for 3140 the sequence. 3141 3142 The machinery is to emit simple truncation instructions and split them 3143 before reload to instructions having USEs of two memory locations that 3144 are filled by this code to old and new control word. 3145 3146 Post-reload pass may be later used to eliminate the redundant fildcw if 3147 needed. */ 3148 3149enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; 3150 3151/* Define this macro if the port needs extra instructions inserted 3152 for mode switching in an optimizing compilation. */ 3153 3154#define OPTIMIZE_MODE_SWITCHING(ENTITY) 1 3155 3156/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 3157 initializer for an array of integers. Each initializer element N 3158 refers to an entity that needs mode switching, and specifies the 3159 number of different modes that might need to be set for this 3160 entity. The position of the initializer in the initializer - 3161 starting counting at zero - determines the integer that is used to 3162 refer to the mode-switched entity in question. */ 3163 3164#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } 3165 3166/* ENTITY is an integer specifying a mode-switched entity. If 3167 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 3168 return an integer value not larger than the corresponding element 3169 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 3170 must be switched into prior to the execution of INSN. */ 3171 3172#define MODE_NEEDED(ENTITY, I) \ 3173 (GET_CODE (I) == CALL_INSN \ 3174 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ 3175 || GET_CODE (PATTERN (I)) == ASM_INPUT))\ 3176 ? FP_CW_UNINITIALIZED \ 3177 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ 3178 ? FP_CW_ANY \ 3179 : FP_CW_STORED) 3180 3181/* This macro specifies the order in which modes for ENTITY are 3182 processed. 0 is the highest priority. */ 3183 3184#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 3185 3186/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 3187 is the set of hard registers live at the point where the insn(s) 3188 are to be inserted. */ 3189 3190#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3191 ((MODE) == FP_CW_STORED \ 3192 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ 3193 assign_386_stack_local (HImode, 2)), 0\ 3194 : 0) 3195 3196/* Avoid renaming of stack registers, as doing so in combination with 3197 scheduling just increases amount of live registers at time and in 3198 the turn amount of fxch instructions needed. 3199 3200 ??? Maybe Pentium chips benefits from renaming, someone can try... */ 3201 3202#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 3203 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 3204 3205 3206/* 3207Local variables: 3208version-control: t 3209End: 3210*/ 3211