i386.h revision 255185
1156952Sume/* Definitions of target machine for GCC for IA-32. 2269867Sume Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3269867Sume 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4269867Sume 5269867SumeThis file is part of GCC. 6269867Sume 7269867SumeGCC is free software; you can redistribute it and/or modify 8269867Sumeit under the terms of the GNU General Public License as published by 9269867Sumethe Free Software Foundation; either version 2, or (at your option) 10269867Sumeany later version. 11269867Sume 12269867SumeGCC is distributed in the hope that it will be useful, 13269867Sumebut WITHOUT ANY WARRANTY; without even the implied warranty of 14269867SumeMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15269867SumeGNU General Public License for more details. 16269867Sume 17269867SumeYou should have received a copy of the GNU General Public License 18331722Seadleralong with GCC; see the file COPYING. If not, write to 19156952Sumethe Free Software Foundation, 51 Franklin Street, Fifth Floor, 20156952SumeBoston, MA 02110-1301, USA. */ 21269867Sume 22156952Sume/* The purpose of this file is to define the characteristics of the i386, 23156952Sume independent of assembler syntax or operating system. 24156952Sume 25156952Sume Three other files build on this one to describe a specific assembler syntax: 26156952Sume bsd386.h, att386.h, and sun386.h. 27156952Sume 28156952Sume The actual tm.h file for a particular system should include 29156952Sume this file, and then the file for the appropriate assembler syntax. 30156952Sume 31156952Sume Many macros that specify assembler syntax are omitted entirely from 32156952Sume this file because they really belong in the files for particular 33269867Sume assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34156952Sume ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35156952Sume that start with ASM_ or end in ASM_OP. */ 36156952Sume 37156952Sume/* Define the specific costs for a given cpu */ 38156952Sume 39156952Sumestruct processor_costs { 40156952Sume const int add; /* cost of an add instruction */ 41156952Sume const int lea; /* cost of a lea instruction */ 42156952Sume const int shift_var; /* variable shift costs */ 43156952Sume const int shift_const; /* constant shift costs */ 44156952Sume const int mult_init[5]; /* cost of starting a multiply 45156952Sume in QImode, HImode, SImode, DImode, TImode*/ 46156952Sume const int mult_bit; /* cost of multiply per each bit set */ 47156952Sume const int divide[5]; /* cost of a divide/mod 48156952Sume in QImode, HImode, SImode, DImode, TImode*/ 49269867Sume int movsx; /* The cost of movsx operation. */ 50156952Sume int movzx; /* The cost of movzx operation. */ 51156952Sume const int large_insn; /* insns larger than this cost more */ 52156952Sume const int move_ratio; /* The threshold of number of scalar 53156952Sume memory-to-memory move insns. */ 54156952Sume const int movzbl_load; /* cost of loading using movzbl */ 55156952Sume const int int_load[3]; /* cost of loading integer registers 56269867Sume in QImode, HImode and SImode relative 57156952Sume to reg-reg move (2). */ 58156952Sume const int int_store[3]; /* cost of storing integer register 59156952Sume in QImode, HImode and SImode */ 60156952Sume const int fp_move; /* cost of reg,reg fld/fst */ 61156952Sume const int fp_load[3]; /* cost of loading FP register 62156952Sume in SFmode, DFmode and XFmode */ 63156952Sume const int fp_store[3]; /* cost of storing FP register 64156952Sume in SFmode, DFmode and XFmode */ 65156952Sume const int mmx_move; /* cost of moving MMX register. */ 66156952Sume const int mmx_load[2]; /* cost of loading MMX register 67156952Sume in SImode and DImode */ 68156952Sume const int mmx_store[2]; /* cost of storing MMX register 69156952Sume in SImode and DImode */ 70156952Sume const int sse_move; /* cost of moving SSE register. */ 71156952Sume const int sse_load[3]; /* cost of loading SSE register 72156952Sume in SImode, DImode and TImode*/ 73156952Sume const int sse_store[3]; /* cost of storing SSE register 74156952Sume in SImode, DImode and TImode*/ 75156952Sume const int mmxsse_to_integer; /* cost of moving mmxsse register to 76156952Sume integer and vice versa. */ 77156952Sume const int prefetch_block; /* bytes moved to cache for prefetch. */ 78156952Sume const int simultaneous_prefetches; /* number of parallel prefetch 79156952Sume operations. */ 80156952Sume const int branch_cost; /* Default value for BRANCH_COST. */ 81156952Sume const int fadd; /* cost of FADD and FSUB instructions. */ 82156952Sume const int fmul; /* cost of FMUL instruction. */ 83156952Sume const int fdiv; /* cost of FDIV instruction. */ 84156952Sume const int fabs; /* cost of FABS instruction. */ 85156952Sume const int fchs; /* cost of FCHS instruction. */ 86156952Sume const int fsqrt; /* cost of FSQRT instruction. */ 87156952Sume}; 88156952Sume 89156952Sumeextern const struct processor_costs *ix86_cost; 90156952Sume 91156952Sume/* Macros used in the machine description to test the flags. */ 92156952Sume 93156952Sume/* configure can arrange to make this 2, to force a 486. */ 94269867Sume 95156952Sume#ifndef TARGET_CPU_DEFAULT 96156956Sume#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic 97156956Sume#endif 98156952Sume 99156952Sume#ifndef TARGET_FPMATH_DEFAULT 100156952Sume#define TARGET_FPMATH_DEFAULT \ 101156952Sume (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 102156952Sume#endif 103156952Sume 104156952Sume#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 105156952Sume 106156952Sume/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 107156952Sume compile-time constant. */ 108156952Sume#ifdef IN_LIBGCC2 109156952Sume#undef TARGET_64BIT 110156952Sume#ifdef __x86_64__ 111156952Sume#define TARGET_64BIT 1 112156952Sume#else 113156952Sume#define TARGET_64BIT 0 114156952Sume#endif 115156952Sume#else 116156952Sume#ifndef TARGET_BI_ARCH 117156952Sume#undef TARGET_64BIT 118156952Sume#if TARGET_64BIT_DEFAULT 119156952Sume#define TARGET_64BIT 1 120156952Sume#else 121156952Sume#define TARGET_64BIT 0 122156952Sume#endif 123156952Sume#endif 124156952Sume#endif 125156952Sume 126156952Sume#define HAS_LONG_COND_BRANCH 1 127156952Sume#define HAS_LONG_UNCOND_BRANCH 1 128156952Sume 129156952Sume#define TARGET_386 (ix86_tune == PROCESSOR_I386) 130170244Sume#define TARGET_486 (ix86_tune == PROCESSOR_I486) 131156952Sume#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 132156952Sume#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 133156952Sume#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 134156952Sume#define TARGET_K6 (ix86_tune == PROCESSOR_K6) 135156952Sume#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 136156952Sume#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 137156952Sume#define TARGET_K8 (ix86_tune == PROCESSOR_K8) 138156952Sume#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 139156952Sume#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 140156952Sume#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 141156952Sume#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) 142156952Sume#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) 143156952Sume#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) 144156952Sume#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 145156952Sume 146156952Sume#define TUNEMASK (1 << ix86_tune) 147156952Sumeextern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 148156952Sumeextern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 149156952Sumeextern const int x86_branch_hints, x86_unroll_strlen; 150156952Sumeextern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 151156952Sumeextern const int x86_use_himode_fiop, x86_use_simode_fiop; 152156952Sumeextern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write; 153156952Sumeextern const int x86_read_modify, x86_split_long_moves; 154156952Sumeextern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; 155156952Sumeextern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 156156952Sumeextern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 157156952Sumeextern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 158156952Sumeextern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 159156952Sumeextern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 160156952Sumeextern const int x86_epilogue_using_move, x86_decompose_lea; 161156952Sumeextern const int x86_arch_always_fancy_math_387, x86_shift1; 162156952Sumeextern const int x86_sse_partial_reg_dependency, x86_sse_split_regs; 163156952Sumeextern const int x86_sse_unaligned_move_optimal; 164156952Sumeextern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; 165156952Sumeextern const int x86_use_ffreep; 166156952Sumeextern const int x86_inter_unit_moves, x86_schedule; 167156952Sumeextern const int x86_use_bt; 168156952Sumeextern const int x86_cmpxchg, x86_cmpxchg8b, x86_xadd; 169156952Sumeextern const int x86_use_incdec; 170156952Sumeextern const int x86_pad_returns; 171156952Sumeextern const int x86_partial_flag_reg_stall; 172156952Sumeextern int x86_prefetch_sse, x86_cmpxchg16b; 173156952Sume 174156952Sume#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) 175156952Sume#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) 176156952Sume#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK) 177156952Sume#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK) 178156952Sume#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK) 179156952Sume/* For sane SSE instruction set generation we need fcomi instruction. It is 180156952Sume safe to enable all CMOVE instructions. */ 181156952Sume#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 182156952Sume#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 183156952Sume#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK) 184156952Sume#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK) 185156952Sume#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK) 186156952Sume#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) 187156952Sume#define TARGET_MOVX (x86_movx & TUNEMASK) 188156952Sume#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) 189186090Sume#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK) 190156952Sume#define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK) 191186090Sume#define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK) 192156952Sume#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) 193156952Sume#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK) 194156952Sume#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK) 195186090Sume#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK) 196186090Sume#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK) 197186090Sume#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK) 198186090Sume#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK) 199186090Sume#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK) 200186090Sume#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK) 201186090Sume#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK) 202186090Sume#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK) 203186090Sume#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK) 204186090Sume#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK) 205186090Sume#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK) 206186090Sume#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK) 207186090Sume#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK) 208186090Sume#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK) 209186090Sume#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) 210186090Sume#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 211186090Sume (x86_sse_partial_reg_dependency & TUNEMASK) 212186090Sume#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \ 213186090Sume (x86_sse_unaligned_move_optimal & TUNEMASK) 214186090Sume#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK) 215186090Sume#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) 216186090Sume#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) 217186090Sume#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) 218186090Sume#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK) 219186090Sume#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK) 220186090Sume#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 221186090Sume#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK) 222186090Sume#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK) 223186090Sume#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK) 224186090Sume#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK) 225186090Sume#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK) 226186090Sume#define TARGET_SCHEDULE (x86_schedule & TUNEMASK) 227186090Sume#define TARGET_USE_BT (x86_use_bt & TUNEMASK) 228186090Sume#define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK) 229186090Sume#define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK) 230186090Sume 231186090Sume#define ASSEMBLER_DIALECT (ix86_asm_dialect) 232186090Sume 233186090Sume#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 234186090Sume#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 235186090Sume && (ix86_fpmath & FPMATH_387)) 236186090Sume 237186090Sume#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 238186090Sume#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 239156952Sume#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 240156952Sume#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) 241156952Sume 242156952Sume#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch)) 243156952Sume#define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch)) 244156952Sume#define TARGET_CMPXCHG16B (x86_cmpxchg16b) 245156952Sume#define TARGET_XADD (x86_xadd & (1 << ix86_arch)) 246156952Sume 247156952Sume#ifndef TARGET_64BIT_DEFAULT 248156952Sume#define TARGET_64BIT_DEFAULT 0 249156952Sume#endif 250186090Sume#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 251156952Sume#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 252156952Sume#endif 253156952Sume 254156952Sume/* Once GDB has been enhanced to deal with functions without frame 255156952Sume pointers, we can change this to allow for elimination of 256156952Sume the frame pointer in leaf functions. */ 257156952Sume#define TARGET_DEFAULT 0 258156952Sume 259156952Sume/* This is not really a target flag, but is done this way so that 260156952Sume it's analogous to similar code for Mach-O on PowerPC. darwin.h 261156952Sume redefines this to 1. */ 262156952Sume#define TARGET_MACHO 0 263156952Sume 264156952Sume/* Subtargets may reset this to 1 in order to enable 96-bit long double 265156952Sume with the rounding mode forced to 53 bits. */ 266156952Sume#define TARGET_96_ROUND_53_LONG_DOUBLE 0 267156952Sume 268156952Sume/* Sometimes certain combinations of command options do not make 269170244Sume sense on a particular target machine. You can define a macro 270156952Sume `OVERRIDE_OPTIONS' to take account of this. This macro, if 271156952Sume defined, is executed once just after all the command options have 272156952Sume been parsed. 273156952Sume 274156952Sume Don't use this macro to turn on various extra optimizations for 275156952Sume `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 276156952Sume 277156952Sume#define OVERRIDE_OPTIONS override_options () 278156952Sume 279156952Sume/* Define this to change the optimizations performed by default. */ 280156952Sume#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 281156952Sume optimization_options ((LEVEL), (SIZE)) 282156952Sume 283156952Sume/* -march=native handling only makes sense with compiler running on 284156952Sume an x86 or x86_64 chip. If changing this condition, also change 285156952Sume the condition in driver-i386.c. */ 286156952Sume#if defined(__i386__) || defined(__x86_64__) 287156952Sume/* In driver-i386.c. */ 288156952Sumeextern const char *host_detect_local_cpu (int argc, const char **argv); 289156952Sume#define EXTRA_SPEC_FUNCTIONS \ 290156952Sume { "local_cpu_detect", host_detect_local_cpu }, 291156952Sume#define HAVE_LOCAL_CPU_DETECT 292156952Sume#endif 293156952Sume 294156952Sume/* Support for configure-time defaults of some command line options. 295156952Sume The order here is important so that -march doesn't squash the 296156952Sume tune or cpu values. */ 297156952Sume#define OPTION_DEFAULT_SPECS \ 298156952Sume {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 299156952Sume {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 300156952Sume {"arch", "%{!march=*:-march=%(VALUE)}"} 301156952Sume 302156952Sume/* Specs for the compiler proper */ 303156952Sume 304156952Sume#ifndef CC1_CPU_SPEC 305156952Sume#define CC1_CPU_SPEC_1 "\ 306156952Sume%{!mtune*: \ 307156952Sume%{m386:mtune=i386 \ 308156952Sume%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \ 309156952Sume%{m486:-mtune=i486 \ 310156952Sume%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \ 311156952Sume%{mpentium:-mtune=pentium \ 312156952Sume%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \ 313156952Sume%{mpentiumpro:-mtune=pentiumpro \ 314156952Sume%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \ 315156952Sume%{mcpu=*:-mtune=%* \ 316156952Sume%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \ 317156952Sume%<mcpu=* \ 318156952Sume%{mintel-syntax:-masm=intel \ 319156952Sume%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 320156952Sume%{mno-intel-syntax:-masm=att \ 321156952Sume%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 322156952Sume 323156952Sume#ifndef HAVE_LOCAL_CPU_DETECT 324156952Sume#define CC1_CPU_SPEC CC1_CPU_SPEC_1 325156952Sume#else 326156952Sume#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 327156952Sume"%{march=native:%<march=native %:local_cpu_detect(arch) \ 328156952Sume %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ 329269867Sume%{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 330156952Sume#endif 331156952Sume#endif 332156952Sume 333156952Sume/* Target CPU builtins. */ 334156952Sume#define TARGET_CPU_CPP_BUILTINS() \ 335156952Sume do \ 336156952Sume { \ 337156952Sume size_t arch_len = strlen (ix86_arch_string); \ 338156952Sume size_t tune_len = strlen (ix86_tune_string); \ 339156952Sume int last_arch_char = ix86_arch_string[arch_len - 1]; \ 340156952Sume int last_tune_char = ix86_tune_string[tune_len - 1]; \ 341156952Sume \ 342156952Sume if (TARGET_64BIT) \ 343156952Sume { \ 344156952Sume builtin_assert ("cpu=x86_64"); \ 345156952Sume builtin_assert ("machine=x86_64"); \ 346156952Sume builtin_define ("__amd64"); \ 347156952Sume builtin_define ("__amd64__"); \ 348156952Sume builtin_define ("__x86_64"); \ 349156952Sume builtin_define ("__x86_64__"); \ 350156952Sume } \ 351156952Sume else \ 352156952Sume { \ 353156952Sume builtin_assert ("cpu=i386"); \ 354156952Sume builtin_assert ("machine=i386"); \ 355156952Sume builtin_define_std ("i386"); \ 356156952Sume } \ 357156952Sume \ 358156952Sume /* Built-ins based on -mtune= (or -march= if no \ 359156952Sume -mtune= given). */ \ 360156952Sume if (TARGET_386) \ 361156952Sume builtin_define ("__tune_i386__"); \ 362156952Sume else if (TARGET_486) \ 363156952Sume builtin_define ("__tune_i486__"); \ 364170244Sume else if (TARGET_PENTIUM) \ 365170244Sume { \ 366156952Sume builtin_define ("__tune_i586__"); \ 367156952Sume builtin_define ("__tune_pentium__"); \ 368156952Sume if (last_tune_char == 'x') \ 369288114Srodrigc builtin_define ("__tune_pentium_mmx__"); \ 370288114Srodrigc } \ 371156952Sume else if (TARGET_PENTIUMPRO) \ 372156952Sume { \ 373156952Sume builtin_define ("__tune_i686__"); \ 374156952Sume builtin_define ("__tune_pentiumpro__"); \ 375156952Sume switch (last_tune_char) \ 376156952Sume { \ 377156952Sume case '3': \ 378170244Sume builtin_define ("__tune_pentium3__"); \ 379156952Sume /* FALLTHRU */ \ 380156952Sume case '2': \ 381156952Sume builtin_define ("__tune_pentium2__"); \ 382156952Sume break; \ 383156952Sume } \ 384156952Sume } \ 385156952Sume else if (TARGET_GEODE) \ 386156952Sume { \ 387156952Sume builtin_define ("__tune_geode__"); \ 388156952Sume } \ 389156952Sume else if (TARGET_K6) \ 390156952Sume { \ 391156952Sume builtin_define ("__tune_k6__"); \ 392156952Sume if (last_tune_char == '2') \ 393156952Sume builtin_define ("__tune_k6_2__"); \ 394156952Sume else if (last_tune_char == '3') \ 395156952Sume builtin_define ("__tune_k6_3__"); \ 396156952Sume } \ 397156952Sume else if (TARGET_ATHLON) \ 398156952Sume { \ 399156952Sume builtin_define ("__tune_athlon__"); \ 400170244Sume /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \ 401156952Sume if (last_tune_char != 'n' && last_tune_char != 'd') \ 402156952Sume builtin_define ("__tune_athlon_sse__"); \ 403156952Sume } \ 404156952Sume else if (TARGET_K8) \ 405156952Sume builtin_define ("__tune_k8__"); \ 406156952Sume else if (TARGET_AMDFAM10) \ 407156952Sume builtin_define ("__tune_amdfam10__"); \ 408156952Sume else if (TARGET_PENTIUM4) \ 409156952Sume builtin_define ("__tune_pentium4__"); \ 410156952Sume else if (TARGET_NOCONA) \ 411156952Sume builtin_define ("__tune_nocona__"); \ 412156952Sume else if (TARGET_CORE2) \ 413156952Sume builtin_define ("__tune_core2__"); \ 414156952Sume \ 415156952Sume if (TARGET_MMX) \ 416170244Sume builtin_define ("__MMX__"); \ 417156952Sume if (TARGET_3DNOW) \ 418156952Sume builtin_define ("__3dNOW__"); \ 419156956Sume if (TARGET_3DNOW_A) \ 420156952Sume builtin_define ("__3dNOW_A__"); \ 421156952Sume if (TARGET_SSE) \ 422156952Sume builtin_define ("__SSE__"); \ 423156952Sume if (TARGET_SSE2) \ 424186090Sume builtin_define ("__SSE2__"); \ 425156952Sume if (TARGET_SSE3) \ 426156952Sume builtin_define ("__SSE3__"); \ 427156956Sume if (TARGET_SSSE3) \ 428156952Sume builtin_define ("__SSSE3__"); \ 429156952Sume if (TARGET_SSE4A) \ 430156952Sume builtin_define ("__SSE4A__"); \ 431156952Sume if (TARGET_AES) \ 432186090Sume builtin_define ("__AES__"); \ 433156952Sume if (TARGET_SSE_MATH && TARGET_SSE) \ 434156952Sume builtin_define ("__SSE_MATH__"); \ 435156952Sume if (TARGET_SSE_MATH && TARGET_SSE2) \ 436156952Sume builtin_define ("__SSE2_MATH__"); \ 437156952Sume \ 438156952Sume /* Built-ins based on -march=. */ \ 439156952Sume if (ix86_arch == PROCESSOR_I486) \ 440156952Sume { \ 441156952Sume builtin_define ("__i486"); \ 442156952Sume builtin_define ("__i486__"); \ 443156952Sume } \ 444156952Sume else if (ix86_arch == PROCESSOR_PENTIUM) \ 445156952Sume { \ 446156952Sume builtin_define ("__i586"); \ 447156952Sume builtin_define ("__i586__"); \ 448156952Sume builtin_define ("__pentium"); \ 449156952Sume builtin_define ("__pentium__"); \ 450156952Sume if (last_arch_char == 'x') \ 451156952Sume builtin_define ("__pentium_mmx__"); \ 452156952Sume } \ 453170244Sume else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ 454156952Sume { \ 455156952Sume builtin_define ("__i686"); \ 456156952Sume builtin_define ("__i686__"); \ 457156952Sume builtin_define ("__pentiumpro"); \ 458156952Sume builtin_define ("__pentiumpro__"); \ 459156952Sume } \ 460156952Sume else if (ix86_arch == PROCESSOR_GEODE) \ 461156952Sume { \ 462156952Sume builtin_define ("__geode"); \ 463156952Sume builtin_define ("__geode__"); \ 464156952Sume } \ 465156952Sume else if (ix86_arch == PROCESSOR_K6) \ 466156952Sume { \ 467156952Sume \ 468156952Sume builtin_define ("__k6"); \ 469156952Sume builtin_define ("__k6__"); \ 470156952Sume if (last_arch_char == '2') \ 471156952Sume builtin_define ("__k6_2__"); \ 472156952Sume else if (last_arch_char == '3') \ 473156952Sume builtin_define ("__k6_3__"); \ 474156952Sume } \ 475156952Sume else if (ix86_arch == PROCESSOR_ATHLON) \ 476156952Sume { \ 477156952Sume builtin_define ("__athlon"); \ 478156952Sume builtin_define ("__athlon__"); \ 479156952Sume /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \ 480156952Sume if (last_tune_char != 'n' && last_tune_char != 'd') \ 481156952Sume builtin_define ("__athlon_sse__"); \ 482156952Sume } \ 483156952Sume else if (ix86_arch == PROCESSOR_K8) \ 484156952Sume { \ 485156952Sume builtin_define ("__k8"); \ 486156952Sume builtin_define ("__k8__"); \ 487156952Sume } \ 488156952Sume else if (ix86_arch == PROCESSOR_AMDFAM10) \ 489156952Sume { \ 490156952Sume builtin_define ("__amdfam10"); \ 491156952Sume builtin_define ("__amdfam10__"); \ 492156952Sume } \ 493269867Sume else if (ix86_arch == PROCESSOR_PENTIUM4) \ 494269867Sume { \ 495269867Sume builtin_define ("__pentium4"); \ 496269867Sume builtin_define ("__pentium4__"); \ 497269867Sume } \ 498269867Sume else if (ix86_arch == PROCESSOR_NOCONA) \ 499269867Sume { \ 500269867Sume builtin_define ("__nocona"); \ 501269867Sume builtin_define ("__nocona__"); \ 502269867Sume } \ 503269867Sume else if (ix86_arch == PROCESSOR_CORE2) \ 504269867Sume { \ 505269867Sume builtin_define ("__core2"); \ 506269867Sume builtin_define ("__core2__"); \ 507269867Sume } \ 508269867Sume } \ 509269867Sume while (0) 510269867Sume 511156952Sume#define TARGET_CPU_DEFAULT_i386 0 512156952Sume#define TARGET_CPU_DEFAULT_i486 1 513156952Sume#define TARGET_CPU_DEFAULT_pentium 2 514156952Sume#define TARGET_CPU_DEFAULT_pentium_mmx 3 515156952Sume#define TARGET_CPU_DEFAULT_pentiumpro 4 516156952Sume#define TARGET_CPU_DEFAULT_pentium2 5 517156952Sume#define TARGET_CPU_DEFAULT_pentium3 6 518156952Sume#define TARGET_CPU_DEFAULT_pentium4 7 519156952Sume#define TARGET_CPU_DEFAULT_geode 8 520156952Sume#define TARGET_CPU_DEFAULT_k6 9 521156952Sume#define TARGET_CPU_DEFAULT_k6_2 10 522156952Sume#define TARGET_CPU_DEFAULT_k6_3 11 523156952Sume#define TARGET_CPU_DEFAULT_athlon 12 524156952Sume#define TARGET_CPU_DEFAULT_athlon_sse 13 525156952Sume#define TARGET_CPU_DEFAULT_k8 14 526269867Sume#define TARGET_CPU_DEFAULT_pentium_m 15 527156952Sume#define TARGET_CPU_DEFAULT_prescott 16 528156952Sume#define TARGET_CPU_DEFAULT_nocona 17 529156952Sume#define TARGET_CPU_DEFAULT_core2 18 530170244Sume#define TARGET_CPU_DEFAULT_generic 19 531156952Sume#define TARGET_CPU_DEFAULT_amdfam10 20 532156952Sume 533168441Skan#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 534156952Sume "pentiumpro", "pentium2", "pentium3", \ 535156952Sume "pentium4", "geode", "k6", "k6-2", "k6-3", \ 536156952Sume "athlon", "athlon-4", "k8", \ 537156952Sume "pentium-m", "prescott", "nocona", \ 538156952Sume "core2", "generic", "amdfam10"} 539156952Sume 540156952Sume#ifndef CC1_SPEC 541156952Sume#define CC1_SPEC "%(cc1_cpu) " 542156952Sume#endif 543156952Sume 544156952Sume/* This macro defines names of additional specifications to put in the 545156952Sume specs that can be used in various specifications like CC1_SPEC. Its 546156952Sume definition is an initializer with a subgrouping for each command option. 547156952Sume 548156952Sume Each subgrouping contains a string constant, that defines the 549156952Sume specification name, and a string constant that used by the GCC driver 550156952Sume program. 551156952Sume 552156952Sume Do not define this macro if it does not need to do anything. */ 553156952Sume 554156952Sume#ifndef SUBTARGET_EXTRA_SPECS 555156952Sume#define SUBTARGET_EXTRA_SPECS 556156952Sume#endif 557156952Sume 558156952Sume#define EXTRA_SPECS \ 559156952Sume { "cc1_cpu", CC1_CPU_SPEC }, \ 560156952Sume SUBTARGET_EXTRA_SPECS 561156952Sume 562156952Sume/* target machine storage layout */ 563170244Sume 564156952Sume#define LONG_DOUBLE_TYPE_SIZE 80 565156952Sume 566156952Sume/* Set the value of FLT_EVAL_METHOD in float.h. When using only the 567156952Sume FPU, assume that the fpcw is set to extended precision; when using 568156952Sume only SSE, rounding is correct; when using both SSE and the FPU, 569156952Sume the rounding precision is indeterminate, since either may be chosen 570156952Sume apparently at random. */ 571156952Sume#define TARGET_FLT_EVAL_METHOD \ 572156952Sume (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 573156952Sume 574156952Sume#define SHORT_TYPE_SIZE 16 575156952Sume#define INT_TYPE_SIZE 32 576156952Sume#define FLOAT_TYPE_SIZE 32 577156952Sume#ifndef LONG_TYPE_SIZE 578170244Sume#define LONG_TYPE_SIZE BITS_PER_WORD 579156952Sume#endif 580156952Sume#define DOUBLE_TYPE_SIZE 64 581156952Sume#define LONG_LONG_TYPE_SIZE 64 582156952Sume 583156952Sume#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 584156952Sume#define MAX_BITS_PER_WORD 64 585156952Sume#else 586156952Sume#define MAX_BITS_PER_WORD 32 587156952Sume#endif 588156952Sume 589156952Sume/* Define this if most significant byte of a word is the lowest numbered. */ 590156952Sume/* That is true on the 80386. */ 591156952Sume 592156952Sume#define BITS_BIG_ENDIAN 0 593156952Sume 594156952Sume/* Define this if most significant byte of a word is the lowest numbered. */ 595170244Sume/* That is not true on the 80386. */ 596156952Sume#define BYTES_BIG_ENDIAN 0 597156952Sume 598156952Sume/* Define this if most significant word of a multiword number is the lowest 599156952Sume numbered. */ 600156952Sume/* Not true for 80386 */ 601170244Sume#define WORDS_BIG_ENDIAN 0 602156952Sume 603156952Sume/* Width of a word, in units (bytes). */ 604156952Sume#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 605156952Sume#ifdef IN_LIBGCC2 606156952Sume#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 607156952Sume#else 608156952Sume#define MIN_UNITS_PER_WORD 4 609156952Sume#endif 610156952Sume 611156952Sume/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 612156952Sume#define PARM_BOUNDARY BITS_PER_WORD 613156952Sume 614156952Sume/* Boundary (in *bits*) on which stack pointer should be aligned. */ 615156952Sume#define STACK_BOUNDARY BITS_PER_WORD 616156952Sume 617156952Sume/* Boundary (in *bits*) on which the stack pointer prefers to be 618156952Sume aligned; the compiler cannot rely on having this alignment. */ 619170244Sume#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 620156952Sume 621156952Sume/* As of July 2001, many runtimes do not align the stack properly when 622156952Sume entering main. This causes expand_main_function to forcibly align 623156952Sume the stack, which results in aligned frames for functions called from 624156952Sume main, though it does nothing for the alignment of main itself. */ 625156952Sume#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 626156952Sume (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 627156952Sume 628156952Sume/* Minimum allocation boundary for the code of a function. */ 629156952Sume#define FUNCTION_BOUNDARY 8 630156952Sume 631156952Sume/* C++ stores the virtual bit in the lowest bit of function pointers. */ 632156952Sume#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 633156952Sume 634156952Sume/* Alignment of field after `int : 0' in a structure. */ 635156952Sume 636156952Sume#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 637170244Sume 638156952Sume/* Minimum size in bits of the largest boundary to which any 639156952Sume and all fundamental data types supported by the hardware 640156952Sume might need to be aligned. No data type wants to be aligned 641156952Sume rounder than this. 642156952Sume 643156952Sume Pentium+ prefers DFmode values to be aligned to 64 bit boundary 644156952Sume and Pentium Pro XFmode values at 128 bit boundaries. */ 645156952Sume 646156952Sume#define BIGGEST_ALIGNMENT 128 647156952Sume 648156952Sume/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 649156952Sume#define ALIGN_MODE_128(MODE) \ 650156952Sume ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 651156952Sume 652156952Sume/* The published ABIs say that doubles should be aligned on word 653156952Sume boundaries, so lower the alignment for structure fields unless 654156952Sume -malign-double is set. */ 655170244Sume 656156952Sume/* ??? Blah -- this macro is used directly by libobjc. Since it 657156952Sume supports no vector modes, cut out the complexity and fall back 658156952Sume on BIGGEST_FIELD_ALIGNMENT. */ 659156952Sume#ifdef IN_TARGET_LIBS 660156952Sume#ifdef __x86_64__ 661156952Sume#define BIGGEST_FIELD_ALIGNMENT 128 662156952Sume#else 663156952Sume#define BIGGEST_FIELD_ALIGNMENT 32 664156952Sume#endif 665156952Sume#else 666156952Sume#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 667156952Sume x86_field_alignment (FIELD, COMPUTED) 668156952Sume#endif 669156952Sume 670156952Sume/* If defined, a C expression to compute the alignment given to a 671156952Sume constant that is being placed in memory. EXP is the constant 672156952Sume and ALIGN is the alignment that the object would ordinarily have. 673156952Sume The value of this macro is used instead of that alignment to align 674156952Sume the object. 675156952Sume 676156952Sume If this macro is not defined, then ALIGN is used. 677170244Sume 678156952Sume The typical use of this macro is to increase alignment for string 679186090Sume constants to be word aligned so that `strcpy' calls that copy 680156952Sume constants can be done inline. */ 681156952Sume 682156952Sume#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 683156952Sume 684156952Sume/* If defined, a C expression to compute the alignment for a static 685156952Sume variable. TYPE is the data type, and ALIGN is the alignment that 686156952Sume the object would ordinarily have. The value of this macro is used 687156952Sume instead of that alignment to align the object. 688156952Sume 689156952Sume If this macro is not defined, then ALIGN is used. 690156952Sume 691156952Sume One use of this macro is to increase alignment of medium-size 692156952Sume data to make it all fit in fewer cache lines. Another is to 693156952Sume cause character arrays to be word-aligned so that `strcpy' calls 694156952Sume that copy constants to character arrays can be done inline. */ 695156952Sume 696156952Sume#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 697156952Sume 698156952Sume/* If defined, a C expression to compute the alignment for a local 699170244Sume variable. TYPE is the data type, and ALIGN is the alignment that 700156952Sume the object would ordinarily have. The value of this macro is used 701156952Sume instead of that alignment to align the object. 702156952Sume 703156952Sume If this macro is not defined, then ALIGN is used. 704156952Sume 705156952Sume One use of this macro is to increase alignment of medium-size 706156952Sume data to make it all fit in fewer cache lines. */ 707156952Sume 708156952Sume#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 709156952Sume 710156952Sume/* If defined, a C expression that gives the alignment boundary, in 711170244Sume bits, of an argument with the specified mode and type. If it is 712156952Sume not defined, `PARM_BOUNDARY' is used for all arguments. */ 713156952Sume 714156952Sume#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 715156952Sume ix86_function_arg_boundary ((MODE), (TYPE)) 716156952Sume 717156952Sume/* Set this nonzero if move instructions will actually fail to work 718156952Sume when given unaligned data. */ 719170244Sume#define STRICT_ALIGNMENT 0 720156952Sume 721156952Sume/* If bit field type is int, don't let it cross an int, 722156952Sume and give entire struct the alignment of an int. */ 723156952Sume/* Required on the 386 since it doesn't have bit-field insns. */ 724156952Sume#define PCC_BITFIELD_TYPE_MATTERS 1 725156952Sume 726156952Sume/* Standard register usage. */ 727156952Sume 728156952Sume/* This processor has special stack-like registers. See reg-stack.c 729156952Sume for details. */ 730156952Sume 731156952Sume#define STACK_REGS 732156952Sume#define IS_STACK_MODE(MODE) \ 733156952Sume (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ 734156952Sume || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ 735156952Sume || (MODE) == XFmode) 736156952Sume 737156952Sume/* Number of actual hardware registers. 738156952Sume The hardware registers are assigned numbers for the compiler 739156952Sume from 0 to just below FIRST_PSEUDO_REGISTER. 740156952Sume All registers that the compiler knows about must be given numbers, 741156952Sume even those that are not normally considered general registers. 742156952Sume 743156952Sume In the 80386 we give the 8 general purpose registers the numbers 0-7. 744156952Sume We number the floating point registers 8-15. 745156952Sume Note that registers 0-7 can be accessed as a short or int, 746170244Sume while only 0-3 may be used with byte `mov' instructions. 747156952Sume 748156952Sume Reg 16 does not correspond to any hardware register, but instead 749156952Sume appears in the RTL as an argument pointer prior to reload, and is 750156952Sume eliminated during reloading in favor of either the stack or frame 751156952Sume pointer. */ 752156952Sume 753156952Sume#define FIRST_PSEUDO_REGISTER 53 754156952Sume 755170244Sume/* Number of hardware registers that go into the DWARF-2 unwind info. 756156952Sume If not defined, equals FIRST_PSEUDO_REGISTER. */ 757288114Srodrigc 758156952Sume#define DWARF_FRAME_REGISTERS 17 759156952Sume 760156952Sume/* 1 for registers that have pervasive standard uses 761156952Sume and are not available for the register allocator. 762156952Sume On the 80386, the stack pointer is such, as is the arg pointer. 763156952Sume 764156952Sume The value is zero if the register is not fixed on either 32 or 765156952Sume 64 bit targets, one if the register if fixed on both 32 and 64 766156952Sume bit targets, two if it is only fixed on 32bit targets and three 767156952Sume if its only fixed on 64bit targets. 768156952Sume Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 769156952Sume */ 770156952Sume#define FIXED_REGISTERS \ 771156952Sume/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 772170244Sume{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 773156952Sume/*arg,flags,fpsr,dir,frame*/ \ 774156952Sume 1, 1, 1, 1, 1, \ 775156952Sume/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 776156952Sume 0, 0, 0, 0, 0, 0, 0, 0, \ 777156952Sume/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 778156952Sume 0, 0, 0, 0, 0, 0, 0, 0, \ 779156952Sume/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 780156952Sume 2, 2, 2, 2, 2, 2, 2, 2, \ 781156952Sume/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 782156952Sume 2, 2, 2, 2, 2, 2, 2, 2} 783156952Sume 784156952Sume 785156952Sume/* 1 for registers not available across function calls. 786170244Sume These must include the FIXED_REGISTERS and also any 787156952Sume registers that can be used without being saved. 788156952Sume The latter must include the registers where values are returned 789156952Sume and the register where structure-value addresses are passed. 790156952Sume Aside from that, you can include as many other registers as you like. 791156952Sume 792156952Sume The value is zero if the register is not call used on either 32 or 793156952Sume 64 bit targets, one if the register if call used on both 32 and 64 794156952Sume bit targets, two if it is only call used on 32bit targets and three 795156952Sume if its only call used on 64bit targets. 796156952Sume Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 797156952Sume*/ 798156952Sume#define CALL_USED_REGISTERS \ 799156952Sume/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 800156952Sume{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 801156952Sume/*arg,flags,fpsr,dir,frame*/ \ 802156952Sume 1, 1, 1, 1, 1, \ 803156952Sume/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 804156952Sume 1, 1, 1, 1, 1, 1, 1, 1, \ 805156952Sume/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 806156952Sume 1, 1, 1, 1, 1, 1, 1, 1, \ 807156952Sume/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 808156952Sume 1, 1, 1, 1, 2, 2, 2, 2, \ 809156952Sume/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 810156952Sume 1, 1, 1, 1, 1, 1, 1, 1} \ 811156952Sume 812170244Sume/* Order in which to allocate registers. Each register must be 813156952Sume listed once, even those in FIXED_REGISTERS. List frame pointer 814156952Sume late and fixed registers last. Note that, in general, we prefer 815156952Sume registers listed in CALL_USED_REGISTERS, keeping the others 816156952Sume available for storage of persistent values. 817156952Sume 818156952Sume The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 819156952Sume so this is just empty initializer for array. */ 820156952Sume 821156952Sume#define REG_ALLOC_ORDER \ 822156952Sume{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 823156952Sume 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 824156952Sume 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 825156952Sume 48, 49, 50, 51, 52 } 826156952Sume 827156952Sume/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 828156952Sume to be rearranged based on a particular function. When using sse math, 829156952Sume we want to allocate SSE before x87 registers and vice vera. */ 830156952Sume 831156952Sume#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 832156952Sume 833156952Sume 834156952Sume/* Macro to conditionally modify fixed_regs/call_used_regs. */ 835156952Sume#define CONDITIONAL_REGISTER_USAGE \ 836156952Sumedo { \ 837156952Sume int i; \ 838156952Sume for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 839156952Sume { \ 840156952Sume if (fixed_regs[i] > 1) \ 841156952Sume fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ 842170244Sume if (call_used_regs[i] > 1) \ 843156952Sume call_used_regs[i] = (call_used_regs[i] \ 844156952Sume == (TARGET_64BIT ? 3 : 2)); \ 845156952Sume } \ 846156952Sume if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 847156952Sume { \ 848156952Sume fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 849156952Sume call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 850156952Sume } \ 851156952Sume if (! TARGET_MMX) \ 852156952Sume { \ 853156952Sume int i; \ 854156952Sume for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 855170244Sume if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 856156952Sume fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 857156952Sume } \ 858156952Sume if (! TARGET_SSE) \ 859156952Sume { \ 860156952Sume int i; \ 861156952Sume for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 862156952Sume if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 863156952Sume fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 864156952Sume } \ 865156952Sume if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 866156952Sume { \ 867156952Sume int i; \ 868156952Sume HARD_REG_SET x; \ 869156952Sume COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 870156952Sume for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 871156952Sume if (TEST_HARD_REG_BIT (x, i)) \ 872156952Sume fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 873156952Sume } \ 874156952Sume if (! TARGET_64BIT) \ 875156952Sume { \ 876170244Sume int i; \ 877156952Sume for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ 878156952Sume reg_names[i] = ""; \ 879156952Sume for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ 880156952Sume reg_names[i] = ""; \ 881156952Sume } \ 882156952Sume } while (0) 883170244Sume 884156952Sume/* Return number of consecutive hard regs needed starting at reg REGNO 885156952Sume to hold something of mode MODE. 886156952Sume This is ordinarily the length in words of a value of mode MODE 887170244Sume but can be less for certain modes in special long registers. 888156952Sume 889156952Sume Actually there are no two word move instructions for consecutive 890170244Sume registers. And only registers 0-3 may have mov byte instructions 891156952Sume applied to them. 892156952Sume */ 893156952Sume 894170244Sume#define HARD_REGNO_NREGS(REGNO, MODE) \ 895170244Sume (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 896156952Sume ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 897156952Sume : ((MODE) == XFmode \ 898170244Sume ? (TARGET_64BIT ? 2 : 3) \ 899156952Sume : (MODE) == XCmode \ 900156952Sume ? (TARGET_64BIT ? 4 : 6) \ 901156952Sume : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 902156952Sume 903156952Sume#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 904156952Sume ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 905156952Sume ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 906170244Sume ? 0 \ 907170244Sume : ((MODE) == XFmode || (MODE) == XCmode)) \ 908156952Sume : 0) 909156952Sume 910288114Srodrigc#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 911156952Sume 912156952Sume#define VALID_SSE2_REG_MODE(MODE) \ 913156952Sume ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 914156952Sume || (MODE) == V2DImode || (MODE) == DFmode) 915156952Sume 916156952Sume#define VALID_SSE_REG_MODE(MODE) \ 917156952Sume ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 918170244Sume || (MODE) == SFmode || (MODE) == TFmode) 919170244Sume 920170244Sume#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 921156952Sume ((MODE) == V2SFmode || (MODE) == SFmode) 922156952Sume 923156952Sume#define VALID_MMX_REG_MODE(MODE) \ 924156952Sume ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 925156952Sume || (MODE) == V2SImode || (MODE) == SImode) 926156952Sume 927156952Sume/* ??? No autovectorization into MMX or 3DNOW until we can reliably 928156952Sume place emms and femms instructions. */ 929156952Sume#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD) 930156952Sume 931170244Sume#define VALID_FP_MODE_P(MODE) \ 932170244Sume ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 933156952Sume || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 934156952Sume 935170244Sume#define VALID_INT_MODE_P(MODE) \ 936156952Sume ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 937156952Sume || (MODE) == DImode \ 938170244Sume || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 939156952Sume || (MODE) == CDImode \ 940156952Sume || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 941156952Sume || (MODE) == TFmode || (MODE) == TCmode))) 942170244Sume 943156952Sume/* Return true for modes passed in SSE registers. */ 944156952Sume#define SSE_REG_MODE_P(MODE) \ 945156952Sume ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ 946156952Sume || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ 947156952Sume || (MODE) == V4SFmode || (MODE) == V4SImode) 948156952Sume 949156952Sume/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 950156952Sume 951269867Sume#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 952156952Sume ix86_hard_regno_mode_ok ((REGNO), (MODE)) 953156952Sume 954156952Sume/* Value is 1 if it is a good idea to tie two pseudo registers 955156952Sume when one has mode MODE1 and one has mode MODE2. 956156952Sume If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 957156952Sume for any hard reg, then this must be 0 for correct output. */ 958170244Sume 959156952Sume#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 960156952Sume 961156952Sume/* It is possible to write patterns to move flags; but until someone 962156952Sume does it, */ 963156952Sume#define AVOID_CCMODE_COPIES 964156952Sume 965156952Sume/* Specify the modes required to caller save a given hard regno. 966156952Sume We do this on i386 to prevent flags from being saved at all. 967156952Sume 968156952Sume Kill any attempts to combine saving of modes. */ 969156952Sume 970170244Sume#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 971156952Sume (CC_REGNO_P (REGNO) ? VOIDmode \ 972156952Sume : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 973156952Sume : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\ 974156952Sume : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 975156952Sume : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 976156952Sume : (MODE)) 977156952Sume/* Specify the registers used for certain standard purposes. 978156952Sume The values of these macros are register numbers. */ 979156952Sume 980269867Sume/* on the 386 the pc register is %eip, and is not usable as a general 981170244Sume register. The ordinary mov instructions won't work */ 982156952Sume/* #define PC_REGNUM */ 983156952Sume 984156952Sume/* Register to use for pushing function arguments. */ 985156952Sume#define STACK_POINTER_REGNUM 7 986156952Sume 987156952Sume/* Base register for access to local variables of the function. */ 988156952Sume#define HARD_FRAME_POINTER_REGNUM 6 989156952Sume 990156952Sume/* Base register for access to local variables of the function. */ 991156952Sume#define FRAME_POINTER_REGNUM 20 992170244Sume 993156952Sume/* First floating point reg */ 994156952Sume#define FIRST_FLOAT_REG 8 995156952Sume 996156952Sume/* First & last stack-like regs */ 997156952Sume#define FIRST_STACK_REG FIRST_FLOAT_REG 998156952Sume#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 999156952Sume 1000156952Sume#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1001156952Sume#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1002156952Sume 1003156952Sume#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1004156952Sume#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1005156952Sume 1006170244Sume#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1007156952Sume#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1008156952Sume 1009156952Sume#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1010156952Sume#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1011156952Sume 1012156952Sume/* Value should be nonzero if functions must have frame pointers. 1013269867Sume Zero means the frame pointer need not be set up (and parms 1014170244Sume may be accessed via the stack pointer) in functions that seem suitable. 1015156952Sume This is computed in `reload', in reload1.c. */ 1016156952Sume#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1017170244Sume 1018156952Sume/* Override this in other tm.h files to cope with various OS lossage 1019288114Srodrigc requiring a frame pointer. */ 1020156952Sume#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1021156952Sume#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1022156952Sume#endif 1023156952Sume 1024156952Sume/* Make sure we can access arbitrary call frames. */ 1025156952Sume#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1026156952Sume 1027156952Sume/* Base register for access to arguments of the function. */ 1028156952Sume#define ARG_POINTER_REGNUM 16 1029156952Sume 1030156952Sume/* Register in which static-chain is passed to a function. 1031156952Sume We do use ECX as static chain register for 32 bit ABI. On the 1032156952Sume 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1033156952Sume#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1034156952Sume 1035156952Sume/* Register to hold the addressing base for position independent 1036156952Sume code access to data items. We don't use PIC pointer for 64bit 1037269867Sume mode. Define the regnum to dummy value to prevent gcc from 1038156952Sume pessimizing code dealing with EBX. 1039156952Sume 1040156952Sume To avoid clobbering a call-saved register unnecessarily, we renumber 1041156952Sume the pic register when possible. The change is visible after the 1042156952Sume prologue has been emitted. */ 1043156952Sume 1044156952Sume#define REAL_PIC_OFFSET_TABLE_REGNUM 3 1045156952Sume 1046156952Sume#define PIC_OFFSET_TABLE_REGNUM \ 1047156952Sume ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 1048156952Sume || !flag_pic ? INVALID_REGNUM \ 1049156952Sume : reload_completed ? REGNO (pic_offset_table_rtx) \ 1050156952Sume : REAL_PIC_OFFSET_TABLE_REGNUM) 1051156952Sume 1052156952Sume#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1053156952Sume 1054156952Sume/* A C expression which can inhibit the returning of certain function 1055156952Sume values in registers, based on the type of value. A nonzero value 1056156952Sume says to return the function value in memory, just as large 1057156952Sume structures are always returned. Here TYPE will be a C expression 1058156952Sume of type `tree', representing the data type of the value. 1059156952Sume 1060156952Sume Note that values of mode `BLKmode' must be explicitly handled by 1061156952Sume this macro. Also, the option `-fpcc-struct-return' takes effect 1062170244Sume regardless of this macro. On most systems, it is possible to 1063156952Sume leave the macro undefined; this causes a default definition to be 1064156952Sume used, whose value is the constant 1 for `BLKmode' values, and 0 1065156952Sume otherwise. 1066156952Sume 1067156952Sume Do not use this macro to indicate that structures and unions 1068156952Sume should always be returned in memory. You should instead use 1069156952Sume `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1070156952Sume 1071156952Sume#define RETURN_IN_MEMORY(TYPE) \ 1072156952Sume ix86_return_in_memory (TYPE) 1073156952Sume 1074156952Sume/* This is overridden by <cygwin.h>. */ 1075156952Sume#define MS_AGGREGATE_RETURN 0 1076156952Sume 1077156952Sume/* This is overridden by <netware.h>. */ 1078156952Sume#define KEEP_AGGREGATE_RETURN_POINTER 0 1079156952Sume 1080156952Sume/* Define the classes of registers for register constraints in the 1081156952Sume machine description. Also define ranges of constants. 1082156952Sume 1083156952Sume One of the classes must always be named ALL_REGS and include all hard regs. 1084156952Sume If there is more than one class, another class must be named NO_REGS 1085156952Sume and contain no registers. 1086156952Sume 1087156952Sume The name GENERAL_REGS must be the name of a class (or an alias for 1088156952Sume another name such as ALL_REGS). This is the class of registers 1089156952Sume that is allowed by "g" or "r" in a register constraint. 1090156952Sume Also, registers outside this class are allocated only when 1091156952Sume instructions express preferences for them. 1092156952Sume 1093156952Sume The classes must be numbered in nondecreasing order; that is, 1094156952Sume a larger-numbered class must never be contained completely 1095156952Sume in a smaller-numbered class. 1096156952Sume 1097156952Sume For any two classes, it is very desirable that there be another 1098156952Sume class that represents their union. 1099156952Sume 1100156952Sume It might seem that class BREG is unnecessary, since no useful 386 1101156952Sume opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1102156952Sume and the "b" register constraint is useful in asms for syscalls. 1103156952Sume 1104156952Sume The flags and fpsr registers are in no class. */ 1105156952Sume 1106156952Sumeenum reg_class 1107156952Sume{ 1108156952Sume NO_REGS, 1109156952Sume AREG, DREG, CREG, BREG, SIREG, DIREG, 1110156952Sume AD_REGS, /* %eax/%edx for DImode */ 1111156952Sume Q_REGS, /* %eax %ebx %ecx %edx */ 1112156952Sume NON_Q_REGS, /* %esi %edi %ebp %esp */ 1113156952Sume INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1114156952Sume LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1115156952Sume GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1116156952Sume FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1117156952Sume FLOAT_REGS, 1118156952Sume SSE_REGS, 1119156952Sume MMX_REGS, 1120156952Sume FP_TOP_SSE_REGS, 1121156952Sume FP_SECOND_SSE_REGS, 1122156952Sume FLOAT_SSE_REGS, 1123156952Sume FLOAT_INT_REGS, 1124156952Sume INT_SSE_REGS, 1125170244Sume FLOAT_INT_SSE_REGS, 1126156952Sume ALL_REGS, LIM_REG_CLASSES 1127156952Sume}; 1128156952Sume 1129156952Sume#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1130156952Sume 1131156952Sume#define INTEGER_CLASS_P(CLASS) \ 1132156952Sume reg_class_subset_p ((CLASS), GENERAL_REGS) 1133156952Sume#define FLOAT_CLASS_P(CLASS) \ 1134156952Sume reg_class_subset_p ((CLASS), FLOAT_REGS) 1135156952Sume#define SSE_CLASS_P(CLASS) \ 1136156952Sume ((CLASS) == SSE_REGS) 1137156952Sume#define MMX_CLASS_P(CLASS) \ 1138156952Sume ((CLASS) == MMX_REGS) 1139156952Sume#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1140156952Sume reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1141156952Sume#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1142156952Sume reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1143156952Sume#define MAYBE_SSE_CLASS_P(CLASS) \ 1144156952Sume reg_classes_intersect_p (SSE_REGS, (CLASS)) 1145156952Sume#define MAYBE_MMX_CLASS_P(CLASS) \ 1146156952Sume reg_classes_intersect_p (MMX_REGS, (CLASS)) 1147156952Sume 1148156952Sume#define Q_CLASS_P(CLASS) \ 1149156952Sume reg_class_subset_p ((CLASS), Q_REGS) 1150170244Sume 1151269867Sume/* Give names of register classes as strings for dump file. */ 1152156952Sume 1153156952Sume#define REG_CLASS_NAMES \ 1154156952Sume{ "NO_REGS", \ 1155156952Sume "AREG", "DREG", "CREG", "BREG", \ 1156156952Sume "SIREG", "DIREG", \ 1157156952Sume "AD_REGS", \ 1158156952Sume "Q_REGS", "NON_Q_REGS", \ 1159156952Sume "INDEX_REGS", \ 1160156952Sume "LEGACY_REGS", \ 1161269867Sume "GENERAL_REGS", \ 1162156952Sume "FP_TOP_REG", "FP_SECOND_REG", \ 1163156952Sume "FLOAT_REGS", \ 1164156952Sume "SSE_REGS", \ 1165156952Sume "MMX_REGS", \ 1166156952Sume "FP_TOP_SSE_REGS", \ 1167156952Sume "FP_SECOND_SSE_REGS", \ 1168156952Sume "FLOAT_SSE_REGS", \ 1169156952Sume "FLOAT_INT_REGS", \ 1170156952Sume "INT_SSE_REGS", \ 1171156952Sume "FLOAT_INT_SSE_REGS", \ 1172156952Sume "ALL_REGS" } 1173156952Sume 1174156952Sume/* Define which registers fit in which classes. 1175156952Sume This is an initializer for a vector of HARD_REG_SET 1176156952Sume of length N_REG_CLASSES. */ 1177156952Sume 1178156952Sume#define REG_CLASS_CONTENTS \ 1179156952Sume{ { 0x00, 0x0 }, \ 1180156952Sume { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1181156952Sume { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1182156952Sume { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1183156952Sume { 0x03, 0x0 }, /* AD_REGS */ \ 1184156952Sume { 0x0f, 0x0 }, /* Q_REGS */ \ 1185156952Sume { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1186156952Sume { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1187156952Sume { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1188156952Sume { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1189156952Sume { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1190156952Sume { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1191156952Sume{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1192156952Sume{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1193156952Sume{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1194156952Sume{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1195156952Sume{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1196156952Sume { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1197156952Sume{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1198156952Sume{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1199156952Sume{ 0xffffffff,0x1fffff } \ 1200156952Sume} 1201156952Sume 1202156952Sume/* The same information, inverted: 1203156952Sume Return the class number of the smallest class containing 1204156952Sume reg number REGNO. This could be a conditional expression 1205156952Sume or could index an array. */ 1206156952Sume 1207156952Sume#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1208156952Sume 1209156952Sume/* When defined, the compiler allows registers explicitly used in the 1210156952Sume rtl to be used as spill registers but prevents the compiler from 1211156952Sume extending the lifetime of these registers. */ 1212156952Sume 1213156952Sume#define SMALL_REGISTER_CLASSES 1 1214156952Sume 1215156952Sume#define QI_REG_P(X) \ 1216156952Sume (REG_P (X) && REGNO (X) < 4) 1217156952Sume 1218156952Sume#define GENERAL_REGNO_P(N) \ 1219156956Sume ((N) < 8 || REX_INT_REGNO_P (N)) 1220156956Sume 1221156956Sume#define GENERAL_REG_P(X) \ 1222156956Sume (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1223156956Sume 1224156956Sume#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1225156956Sume 1226156956Sume#define NON_QI_REG_P(X) \ 1227156956Sume (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1228156956Sume 1229156956Sume#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1230156956Sume#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1231156956Sume 1232156956Sume#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1233156956Sume#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1234156956Sume#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1235156956Sume#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1236156956Sume 1237156956Sume#define SSE_REGNO_P(N) \ 1238170244Sume (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1239170244Sume || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1240 1241#define REX_SSE_REGNO_P(N) \ 1242 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG) 1243 1244#define SSE_REGNO(N) \ 1245 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1246#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1247 1248#define SSE_FLOAT_MODE_P(MODE) \ 1249 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1250 1251#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1252#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1253 1254#define STACK_REG_P(XOP) \ 1255 (REG_P (XOP) && \ 1256 REGNO (XOP) >= FIRST_STACK_REG && \ 1257 REGNO (XOP) <= LAST_STACK_REG) 1258 1259#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1260 1261#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1262 1263#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1264#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1265 1266/* The class value for index registers, and the one for base regs. */ 1267 1268#define INDEX_REG_CLASS INDEX_REGS 1269#define BASE_REG_CLASS GENERAL_REGS 1270 1271/* Place additional restrictions on the register class to use when it 1272 is necessary to be able to hold a value of mode MODE in a reload 1273 register for which class CLASS would ordinarily be used. */ 1274 1275#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1276 ((MODE) == QImode && !TARGET_64BIT \ 1277 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1278 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1279 ? Q_REGS : (CLASS)) 1280 1281/* Given an rtx X being reloaded into a reg required to be 1282 in class CLASS, return the class of reg to actually use. 1283 In general this is just CLASS; but on some machines 1284 in some cases it is preferable to use a more restrictive class. 1285 On the 80386 series, we prevent floating constants from being 1286 reloaded into floating registers (since no move-insn can do that) 1287 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1288 1289/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1290 QImode must go into class Q_REGS. 1291 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1292 movdf to do mem-to-mem moves through integer regs. */ 1293 1294#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1295 ix86_preferred_reload_class ((X), (CLASS)) 1296 1297/* Discourage putting floating-point values in SSE registers unless 1298 SSE math is being used, and likewise for the 387 registers. */ 1299 1300#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ 1301 ix86_preferred_output_reload_class ((X), (CLASS)) 1302 1303/* If we are copying between general and FP registers, we need a memory 1304 location. The same is true for SSE and MMX registers. */ 1305#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1306 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1307 1308/* QImode spills from non-QI registers need a scratch. This does not 1309 happen often -- the only example so far requires an uninitialized 1310 pseudo. */ 1311 1312#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1313 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1314 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1315 ? Q_REGS : NO_REGS) 1316 1317/* Return the maximum number of consecutive registers 1318 needed to represent mode MODE in a register of class CLASS. */ 1319/* On the 80386, this is the size of MODE in words, 1320 except in the FP regs, where a single reg is always enough. */ 1321#define CLASS_MAX_NREGS(CLASS, MODE) \ 1322 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1323 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1324 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ 1325 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1326 1327/* A C expression whose value is nonzero if pseudos that have been 1328 assigned to registers of class CLASS would likely be spilled 1329 because registers of CLASS are needed for spill registers. 1330 1331 The default value of this macro returns 1 if CLASS has exactly one 1332 register and zero otherwise. On most machines, this default 1333 should be used. Only define this macro to some other expression 1334 if pseudo allocated by `local-alloc.c' end up in memory because 1335 their hard registers were needed for spill registers. If this 1336 macro returns nonzero for those classes, those pseudos will only 1337 be allocated by `global.c', which knows how to reallocate the 1338 pseudo to another register. If there would not be another 1339 register available for reallocation, you should not change the 1340 definition of this macro since the only effect of such a 1341 definition would be to slow down register allocation. */ 1342 1343#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1344 (((CLASS) == AREG) \ 1345 || ((CLASS) == DREG) \ 1346 || ((CLASS) == CREG) \ 1347 || ((CLASS) == BREG) \ 1348 || ((CLASS) == AD_REGS) \ 1349 || ((CLASS) == SIREG) \ 1350 || ((CLASS) == DIREG) \ 1351 || ((CLASS) == FP_TOP_REG) \ 1352 || ((CLASS) == FP_SECOND_REG)) 1353 1354/* Return a class of registers that cannot change FROM mode to TO mode. */ 1355 1356#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1357 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1358 1359/* Stack layout; function entry, exit and calling. */ 1360 1361/* Define this if pushing a word on the stack 1362 makes the stack pointer a smaller address. */ 1363#define STACK_GROWS_DOWNWARD 1364 1365/* Define this to nonzero if the nominal address of the stack frame 1366 is at the high-address end of the local variables; 1367 that is, each additional local variable allocated 1368 goes at a more negative offset in the frame. */ 1369#define FRAME_GROWS_DOWNWARD 1 1370 1371/* Offset within stack frame to start allocating local variables at. 1372 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1373 first local allocated. Otherwise, it is the offset to the BEGINNING 1374 of the first local allocated. */ 1375#define STARTING_FRAME_OFFSET 0 1376 1377/* If we generate an insn to push BYTES bytes, 1378 this says how many the stack pointer really advances by. 1379 On 386, we have pushw instruction that decrements by exactly 2 no 1380 matter what the position was, there is no pushb. 1381 But as CIE data alignment factor on this arch is -4, we need to make 1382 sure all stack pointer adjustments are in multiple of 4. 1383 1384 For 64bit ABI we round up to 8 bytes. 1385 */ 1386 1387#define PUSH_ROUNDING(BYTES) \ 1388 (TARGET_64BIT \ 1389 ? (((BYTES) + 7) & (-8)) \ 1390 : (((BYTES) + 3) & (-4))) 1391 1392/* If defined, the maximum amount of space required for outgoing arguments will 1393 be computed and placed into the variable 1394 `current_function_outgoing_args_size'. No space will be pushed onto the 1395 stack for each call; instead, the function prologue should increase the stack 1396 frame size by this amount. */ 1397 1398#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1399 1400/* If defined, a C expression whose value is nonzero when we want to use PUSH 1401 instructions to pass outgoing arguments. */ 1402 1403#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1404 1405/* We want the stack and args grow in opposite directions, even if 1406 PUSH_ARGS is 0. */ 1407#define PUSH_ARGS_REVERSED 1 1408 1409/* Offset of first parameter from the argument pointer register value. */ 1410#define FIRST_PARM_OFFSET(FNDECL) 0 1411 1412/* Define this macro if functions should assume that stack space has been 1413 allocated for arguments even when their values are passed in registers. 1414 1415 The value of this macro is the size, in bytes, of the area reserved for 1416 arguments passed in registers for the function represented by FNDECL. 1417 1418 This space can be allocated by the caller, or be a part of the 1419 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1420 which. */ 1421#define REG_PARM_STACK_SPACE(FNDECL) 0 1422 1423/* Value is the number of bytes of arguments automatically 1424 popped when returning from a subroutine call. 1425 FUNDECL is the declaration node of the function (as a tree), 1426 FUNTYPE is the data type of the function (as a tree), 1427 or for a library call it is an identifier node for the subroutine name. 1428 SIZE is the number of bytes of arguments passed on the stack. 1429 1430 On the 80386, the RTD insn may be used to pop them if the number 1431 of args is fixed, but if the number is variable then the caller 1432 must pop them all. RTD can't be used for library calls now 1433 because the library is compiled with the Unix compiler. 1434 Use of RTD is a selectable option, since it is incompatible with 1435 standard Unix calling sequences. If the option is not selected, 1436 the caller must always pop the args. 1437 1438 The attribute stdcall is equivalent to RTD on a per module basis. */ 1439 1440#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1441 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1442 1443#define FUNCTION_VALUE_REGNO_P(N) \ 1444 ix86_function_value_regno_p (N) 1445 1446/* Define how to find the value returned by a library function 1447 assuming the value has mode MODE. */ 1448 1449#define LIBCALL_VALUE(MODE) \ 1450 ix86_libcall_value (MODE) 1451 1452/* Define the size of the result block used for communication between 1453 untyped_call and untyped_return. The block contains a DImode value 1454 followed by the block used by fnsave and frstor. */ 1455 1456#define APPLY_RESULT_SIZE (8+108) 1457 1458/* 1 if N is a possible register number for function argument passing. */ 1459#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1460 1461/* Define a data type for recording info about an argument list 1462 during the scan of that argument list. This data type should 1463 hold all necessary information about the function itself 1464 and about the args processed so far, enough to enable macros 1465 such as FUNCTION_ARG to determine where the next arg should go. */ 1466 1467typedef struct ix86_args { 1468 int words; /* # words passed so far */ 1469 int nregs; /* # registers available for passing */ 1470 int regno; /* next available register number */ 1471 int fastcall; /* fastcall calling convention is used */ 1472 int sse_words; /* # sse words passed so far */ 1473 int sse_nregs; /* # sse registers available for passing */ 1474 int warn_sse; /* True when we want to warn about SSE ABI. */ 1475 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1476 int sse_regno; /* next available sse register number */ 1477 int mmx_words; /* # mmx words passed so far */ 1478 int mmx_nregs; /* # mmx registers available for passing */ 1479 int mmx_regno; /* next available mmx register number */ 1480 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1481 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should 1482 be passed in SSE registers. Otherwise 0. */ 1483} CUMULATIVE_ARGS; 1484 1485/* Initialize a variable CUM of type CUMULATIVE_ARGS 1486 for a call to a function whose data type is FNTYPE. 1487 For a library call, FNTYPE is 0. */ 1488 1489#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1490 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1491 1492/* Update the data in CUM to advance over an argument 1493 of mode MODE and data type TYPE. 1494 (TYPE is null for libcalls where that information may not be available.) */ 1495 1496#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1497 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1498 1499/* Define where to put the arguments to a function. 1500 Value is zero to push the argument on the stack, 1501 or a hard register in which to store the argument. 1502 1503 MODE is the argument's machine mode. 1504 TYPE is the data type of the argument (as a tree). 1505 This is null for libcalls where that information may 1506 not be available. 1507 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1508 the preceding args and about the function being called. 1509 NAMED is nonzero if this argument is a named parameter 1510 (otherwise it is an extra parameter matching an ellipsis). */ 1511 1512#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1513 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1514 1515/* Implement `va_start' for varargs and stdarg. */ 1516#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ 1517 ix86_va_start (VALIST, NEXTARG) 1518 1519#define TARGET_ASM_FILE_END ix86_file_end 1520#define NEED_INDICATE_EXEC_STACK 0 1521 1522/* Output assembler code to FILE to increment profiler label # LABELNO 1523 for profiling a function entry. */ 1524 1525#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1526 1527#define MCOUNT_NAME "_mcount" 1528 1529#define PROFILE_COUNT_REGISTER "edx" 1530 1531/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1532 the stack pointer does not matter. The value is tested only in 1533 functions that have frame pointers. 1534 No definition is equivalent to always zero. */ 1535/* Note on the 386 it might be more efficient not to define this since 1536 we have to restore it ourselves from the frame pointer, in order to 1537 use pop */ 1538 1539#define EXIT_IGNORE_STACK 1 1540 1541/* Output assembler code for a block containing the constant parts 1542 of a trampoline, leaving space for the variable parts. */ 1543 1544/* On the 386, the trampoline contains two instructions: 1545 mov #STATIC,ecx 1546 jmp FUNCTION 1547 The trampoline is generated entirely at runtime. The operand of JMP 1548 is the address of FUNCTION relative to the instruction following the 1549 JMP (which is 5 bytes long). */ 1550 1551/* Length in units of the trampoline for entering a nested function. */ 1552 1553#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1554 1555/* Emit RTL insns to initialize the variable parts of a trampoline. 1556 FNADDR is an RTX for the address of the function's pure code. 1557 CXT is an RTX for the static chain value for the function. */ 1558 1559#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1560 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1561 1562/* Definitions for register eliminations. 1563 1564 This is an array of structures. Each structure initializes one pair 1565 of eliminable registers. The "from" register number is given first, 1566 followed by "to". Eliminations of the same "from" register are listed 1567 in order of preference. 1568 1569 There are two registers that can always be eliminated on the i386. 1570 The frame pointer and the arg pointer can be replaced by either the 1571 hard frame pointer or to the stack pointer, depending upon the 1572 circumstances. The hard frame pointer is not used before reload and 1573 so it is not eligible for elimination. */ 1574 1575#define ELIMINABLE_REGS \ 1576{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1577 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1578 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1579 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1580 1581/* Given FROM and TO register numbers, say whether this elimination is 1582 allowed. Frame pointer elimination is automatically handled. 1583 1584 All other eliminations are valid. */ 1585 1586#define CAN_ELIMINATE(FROM, TO) \ 1587 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1588 1589/* Define the offset between two registers, one to be eliminated, and the other 1590 its replacement, at the start of a routine. */ 1591 1592#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1593 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1594 1595/* Addressing modes, and classification of registers for them. */ 1596 1597/* Macros to check register numbers against specific register classes. */ 1598 1599/* These assume that REGNO is a hard or pseudo reg number. 1600 They give nonzero only if REGNO is a hard reg of the suitable class 1601 or a pseudo reg currently allocated to a suitable hard reg. 1602 Since they use reg_renumber, they are safe only once reg_renumber 1603 has been allocated, which happens in local-alloc.c. */ 1604 1605#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1606 ((REGNO) < STACK_POINTER_REGNUM \ 1607 || (REGNO >= FIRST_REX_INT_REG \ 1608 && (REGNO) <= LAST_REX_INT_REG) \ 1609 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1610 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1611 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1612 1613#define REGNO_OK_FOR_BASE_P(REGNO) \ 1614 ((REGNO) <= STACK_POINTER_REGNUM \ 1615 || (REGNO) == ARG_POINTER_REGNUM \ 1616 || (REGNO) == FRAME_POINTER_REGNUM \ 1617 || (REGNO >= FIRST_REX_INT_REG \ 1618 && (REGNO) <= LAST_REX_INT_REG) \ 1619 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1620 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1621 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1622 1623#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1624 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1625#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1626 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1627 1628/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1629 and check its validity for a certain class. 1630 We have two alternate definitions for each of them. 1631 The usual definition accepts all pseudo regs; the other rejects 1632 them unless they have been allocated suitable hard regs. 1633 The symbol REG_OK_STRICT causes the latter definition to be used. 1634 1635 Most source files want to accept pseudo regs in the hope that 1636 they will get allocated to the class that the insn wants them to be in. 1637 Source files for reload pass need to be strict. 1638 After reload, it makes no difference, since pseudo regs have 1639 been eliminated by then. */ 1640 1641 1642/* Non strict versions, pseudos are ok. */ 1643#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1644 (REGNO (X) < STACK_POINTER_REGNUM \ 1645 || (REGNO (X) >= FIRST_REX_INT_REG \ 1646 && REGNO (X) <= LAST_REX_INT_REG) \ 1647 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1648 1649#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1650 (REGNO (X) <= STACK_POINTER_REGNUM \ 1651 || REGNO (X) == ARG_POINTER_REGNUM \ 1652 || REGNO (X) == FRAME_POINTER_REGNUM \ 1653 || (REGNO (X) >= FIRST_REX_INT_REG \ 1654 && REGNO (X) <= LAST_REX_INT_REG) \ 1655 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1656 1657/* Strict versions, hard registers only */ 1658#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1659#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1660 1661#ifndef REG_OK_STRICT 1662#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1663#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1664 1665#else 1666#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1667#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1668#endif 1669 1670/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1671 that is a valid memory address for an instruction. 1672 The MODE argument is the machine mode for the MEM expression 1673 that wants to use this address. 1674 1675 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1676 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1677 1678 See legitimize_pic_address in i386.c for details as to what 1679 constitutes a legitimate address when -fpic is used. */ 1680 1681#define MAX_REGS_PER_ADDRESS 2 1682 1683#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1684 1685/* Nonzero if the constant value X is a legitimate general operand. 1686 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1687 1688#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1689 1690#ifdef REG_OK_STRICT 1691#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1692do { \ 1693 if (legitimate_address_p ((MODE), (X), 1)) \ 1694 goto ADDR; \ 1695} while (0) 1696 1697#else 1698#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1699do { \ 1700 if (legitimate_address_p ((MODE), (X), 0)) \ 1701 goto ADDR; \ 1702} while (0) 1703 1704#endif 1705 1706/* If defined, a C expression to determine the base term of address X. 1707 This macro is used in only one place: `find_base_term' in alias.c. 1708 1709 It is always safe for this macro to not be defined. It exists so 1710 that alias analysis can understand machine-dependent addresses. 1711 1712 The typical use of this macro is to handle addresses containing 1713 a label_ref or symbol_ref within an UNSPEC. */ 1714 1715#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1716 1717/* Try machine-dependent ways of modifying an illegitimate address 1718 to be legitimate. If we find one, return the new, valid address. 1719 This macro is used in only one place: `memory_address' in explow.c. 1720 1721 OLDX is the address as it was before break_out_memory_refs was called. 1722 In some cases it is useful to look at this to decide what needs to be done. 1723 1724 MODE and WIN are passed so that this macro can use 1725 GO_IF_LEGITIMATE_ADDRESS. 1726 1727 It is always safe for this macro to do nothing. It exists to recognize 1728 opportunities to optimize the output. 1729 1730 For the 80386, we handle X+REG by loading X into a register R and 1731 using R+REG. R will go in a general reg and indexing will be used. 1732 However, if REG is a broken-out memory address or multiplication, 1733 nothing needs to be done because REG can certainly go in a general reg. 1734 1735 When -fpic is used, special handling is needed for symbolic references. 1736 See comments by legitimize_pic_address in i386.c for details. */ 1737 1738#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1739do { \ 1740 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 1741 if (memory_address_p ((MODE), (X))) \ 1742 goto WIN; \ 1743} while (0) 1744 1745#define REWRITE_ADDRESS(X) rewrite_address (X) 1746 1747/* Nonzero if the constant value X is a legitimate general operand 1748 when generating PIC code. It is given that flag_pic is on and 1749 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1750 1751#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1752 1753#define SYMBOLIC_CONST(X) \ 1754 (GET_CODE (X) == SYMBOL_REF \ 1755 || GET_CODE (X) == LABEL_REF \ 1756 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1757 1758/* Go to LABEL if ADDR (a legitimate address expression) 1759 has an effect that depends on the machine mode it is used for. 1760 On the 80386, only postdecrement and postincrement address depend thus 1761 (the amount of decrement or increment being the length of the operand). */ 1762#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1763do { \ 1764 if (GET_CODE (ADDR) == POST_INC \ 1765 || GET_CODE (ADDR) == POST_DEC) \ 1766 goto LABEL; \ 1767} while (0) 1768 1769/* Max number of args passed in registers. If this is more than 3, we will 1770 have problems with ebx (register #4), since it is a caller save register and 1771 is also used as the pic register in ELF. So for now, don't allow more than 1772 3 registers to be passed in registers. */ 1773 1774#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 1775 1776#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) 1777 1778#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1779 1780 1781/* Specify the machine mode that this machine uses 1782 for the index in the tablejump instruction. */ 1783#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 1784 1785/* Define this as 1 if `char' should by default be signed; else as 0. */ 1786#define DEFAULT_SIGNED_CHAR 1 1787 1788/* Number of bytes moved into a data cache for a single prefetch operation. */ 1789#define PREFETCH_BLOCK ix86_cost->prefetch_block 1790 1791/* Number of prefetch operations that can be done in parallel. */ 1792#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 1793 1794/* Max number of bytes we can move from memory to memory 1795 in one reasonably fast instruction. */ 1796#define MOVE_MAX 16 1797 1798/* MOVE_MAX_PIECES is the number of bytes at a time which we can 1799 move efficiently, as opposed to MOVE_MAX which is the maximum 1800 number of bytes we can move with a single instruction. */ 1801#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 1802 1803/* If a memory-to-memory move would take MOVE_RATIO or more simple 1804 move-instruction pairs, we will do a movmem or libcall instead. 1805 Increasing the value will always make code faster, but eventually 1806 incurs high cost in increased code size. 1807 1808 If you don't define this, a reasonable default is used. */ 1809 1810#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 1811 1812/* If a clear memory operation would take CLEAR_RATIO or more simple 1813 move-instruction sequences, we will do a clrmem or libcall instead. */ 1814 1815#define CLEAR_RATIO (optimize_size ? 2 \ 1816 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio) 1817 1818/* Define if shifts truncate the shift count 1819 which implies one can omit a sign-extension or zero-extension 1820 of a shift count. */ 1821/* On i386, shifts do truncate the count. But bit opcodes don't. */ 1822 1823/* #define SHIFT_COUNT_TRUNCATED */ 1824 1825/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1826 is done just by pretending it is already truncated. */ 1827#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1828 1829/* A macro to update M and UNSIGNEDP when an object whose type is 1830 TYPE and which has the specified mode and signedness is to be 1831 stored in a register. This macro is only called when TYPE is a 1832 scalar type. 1833 1834 On i386 it is sometimes useful to promote HImode and QImode 1835 quantities to SImode. The choice depends on target type. */ 1836 1837#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1838do { \ 1839 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1840 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1841 (MODE) = SImode; \ 1842} while (0) 1843 1844/* Specify the machine mode that pointers have. 1845 After generation of rtl, the compiler makes no further distinction 1846 between pointers and any other objects of this machine mode. */ 1847#define Pmode (TARGET_64BIT ? DImode : SImode) 1848 1849/* A function address in a call instruction 1850 is a byte address (for indexing purposes) 1851 so give the MEM rtx a byte's mode. */ 1852#define FUNCTION_MODE QImode 1853 1854/* A C expression for the cost of moving data from a register in class FROM to 1855 one in class TO. The classes are expressed using the enumeration values 1856 such as `GENERAL_REGS'. A value of 2 is the default; other values are 1857 interpreted relative to that. 1858 1859 It is not required that the cost always equal 2 when FROM is the same as TO; 1860 on some machines it is expensive to move between registers if they are not 1861 general registers. */ 1862 1863#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1864 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1865 1866/* A C expression for the cost of moving data of mode M between a 1867 register and memory. A value of 2 is the default; this cost is 1868 relative to those in `REGISTER_MOVE_COST'. 1869 1870 If moving between registers and memory is more expensive than 1871 between two registers, you should define this macro to express the 1872 relative cost. */ 1873 1874#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1875 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 1876 1877/* A C expression for the cost of a branch instruction. A value of 1 1878 is the default; other values are interpreted relative to that. */ 1879 1880#define BRANCH_COST ix86_branch_cost 1881 1882/* Define this macro as a C expression which is nonzero if accessing 1883 less than a word of memory (i.e. a `char' or a `short') is no 1884 faster than accessing a word of memory, i.e., if such access 1885 require more than one instruction or if there is no difference in 1886 cost between byte and (aligned) word loads. 1887 1888 When this macro is not defined, the compiler will access a field by 1889 finding the smallest containing object; when it is defined, a 1890 fullword load will be used if alignment permits. Unless bytes 1891 accesses are faster than word accesses, using word accesses is 1892 preferable since it may eliminate subsequent memory access if 1893 subsequent accesses occur to other fields in the same word of the 1894 structure, but to different bytes. */ 1895 1896#define SLOW_BYTE_ACCESS 0 1897 1898/* Nonzero if access to memory by shorts is slow and undesirable. */ 1899#define SLOW_SHORT_ACCESS 0 1900 1901/* Define this macro to be the value 1 if unaligned accesses have a 1902 cost many times greater than aligned accesses, for example if they 1903 are emulated in a trap handler. 1904 1905 When this macro is nonzero, the compiler will act as if 1906 `STRICT_ALIGNMENT' were nonzero when generating code for block 1907 moves. This can cause significantly more instructions to be 1908 produced. Therefore, do not set this macro nonzero if unaligned 1909 accesses only add a cycle or two to the time for a memory access. 1910 1911 If the value of this macro is always zero, it need not be defined. */ 1912 1913/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1914 1915/* Define this macro if it is as good or better to call a constant 1916 function address than to call an address kept in a register. 1917 1918 Desirable on the 386 because a CALL with a constant address is 1919 faster than one with a register address. */ 1920 1921#define NO_FUNCTION_CSE 1922 1923/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1924 return the mode to be used for the comparison. 1925 1926 For floating-point equality comparisons, CCFPEQmode should be used. 1927 VOIDmode should be used in all other cases. 1928 1929 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1930 possible, to allow for more combinations. */ 1931 1932#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1933 1934/* Return nonzero if MODE implies a floating point inequality can be 1935 reversed. */ 1936 1937#define REVERSIBLE_CC_MODE(MODE) 1 1938 1939/* A C expression whose value is reversed condition code of the CODE for 1940 comparison done in CC_MODE mode. */ 1941#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 1942 1943 1944/* Control the assembler format that we output, to the extent 1945 this does not vary between assemblers. */ 1946 1947/* How to refer to registers in assembler output. 1948 This sequence is indexed by compiler's hard-register-number (see above). */ 1949 1950/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e". 1951 For non floating point regs, the following are the HImode names. 1952 1953 For float regs, the stack top is sometimes referred to as "%st(0)" 1954 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ 1955 1956#define HI_REGISTER_NAMES \ 1957{"ax","dx","cx","bx","si","di","bp","sp", \ 1958 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 1959 "argp", "flags", "fpsr", "dirflag", "frame", \ 1960 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 1961 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 1962 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1963 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 1964 1965#define REGISTER_NAMES HI_REGISTER_NAMES 1966 1967/* Table of additional register names to use in user input. */ 1968 1969#define ADDITIONAL_REGISTER_NAMES \ 1970{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 1971 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 1972 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 1973 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 1974 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 1975 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 1976 1977/* Note we are omitting these since currently I don't know how 1978to get gcc to use these, since they want the same but different 1979number as al, and ax. 1980*/ 1981 1982#define QI_REGISTER_NAMES \ 1983{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 1984 1985/* These parallel the array above, and can be used to access bits 8:15 1986 of regs 0 through 3. */ 1987 1988#define QI_HIGH_REGISTER_NAMES \ 1989{"ah", "dh", "ch", "bh", } 1990 1991/* How to renumber registers for dbx and gdb. */ 1992 1993#define DBX_REGISTER_NUMBER(N) \ 1994 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 1995 1996extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 1997extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 1998extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 1999 2000/* Before the prologue, RA is at 0(%esp). */ 2001#define INCOMING_RETURN_ADDR_RTX \ 2002 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2003 2004/* After the prologue, RA is at -4(AP) in the current frame. */ 2005#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2006 ((COUNT) == 0 \ 2007 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2008 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2009 2010/* PC is dbx register 8; let's use that column for RA. */ 2011#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2012 2013/* Before the prologue, the top of the frame is at 4(%esp). */ 2014#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2015 2016/* Describe how we implement __builtin_eh_return. */ 2017#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2018#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2019 2020 2021/* Select a format to encode pointers in exception handling data. CODE 2022 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2023 true if the symbol may be affected by dynamic relocations. 2024 2025 ??? All x86 object file formats are capable of representing this. 2026 After all, the relocation needed is the same as for the call insn. 2027 Whether or not a particular assembler allows us to enter such, I 2028 guess we'll have to see. */ 2029#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2030 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 2031 2032/* This is how to output an insn to push a register on the stack. 2033 It need not be very fast code. */ 2034 2035#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2036do { \ 2037 if (TARGET_64BIT) \ 2038 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2039 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2040 else \ 2041 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2042} while (0) 2043 2044/* This is how to output an insn to pop a register from the stack. 2045 It need not be very fast code. */ 2046 2047#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2048do { \ 2049 if (TARGET_64BIT) \ 2050 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2051 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2052 else \ 2053 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2054} while (0) 2055 2056/* This is how to output an element of a case-vector that is absolute. */ 2057 2058#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2059 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2060 2061/* This is how to output an element of a case-vector that is relative. */ 2062 2063#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2064 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2065 2066/* Under some conditions we need jump tables in the text section, 2067 because the assembler cannot handle label differences between 2068 sections. This is the case for x86_64 on Mach-O for example. */ 2069 2070#define JUMP_TABLES_IN_TEXT_SECTION \ 2071 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2072 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2073 2074/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2075 and switch back. For x86 we do this only to save a few bytes that 2076 would otherwise be unused in the text section. */ 2077#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2078 asm (SECTION_OP "\n\t" \ 2079 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2080 TEXT_SECTION_ASM_OP); 2081 2082/* Print operand X (an rtx) in assembler syntax to file FILE. 2083 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2084 Effect of various CODE letters is described in i386.c near 2085 print_operand function. */ 2086 2087#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2088 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') 2089 2090#define PRINT_OPERAND(FILE, X, CODE) \ 2091 print_operand ((FILE), (X), (CODE)) 2092 2093#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2094 print_operand_address ((FILE), (ADDR)) 2095 2096#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2097do { \ 2098 if (! output_addr_const_extra (FILE, (X))) \ 2099 goto FAIL; \ 2100} while (0); 2101 2102/* a letter which is not needed by the normal asm syntax, which 2103 we can use for operand syntax in the extended asm */ 2104 2105#define ASM_OPERAND_LETTER '#' 2106#define RET return "" 2107#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 2108 2109/* Which processor to schedule for. The cpu attribute defines a list that 2110 mirrors this list, so changes to i386.md must be made at the same time. */ 2111 2112enum processor_type 2113{ 2114 PROCESSOR_I386, /* 80386 */ 2115 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2116 PROCESSOR_PENTIUM, 2117 PROCESSOR_PENTIUMPRO, 2118 PROCESSOR_GEODE, 2119 PROCESSOR_K6, 2120 PROCESSOR_ATHLON, 2121 PROCESSOR_PENTIUM4, 2122 PROCESSOR_K8, 2123 PROCESSOR_NOCONA, 2124 PROCESSOR_CORE2, 2125 PROCESSOR_GENERIC32, 2126 PROCESSOR_GENERIC64, 2127 PROCESSOR_AMDFAM10, 2128 PROCESSOR_max 2129}; 2130 2131extern enum processor_type ix86_tune; 2132extern enum processor_type ix86_arch; 2133 2134enum fpmath_unit 2135{ 2136 FPMATH_387 = 1, 2137 FPMATH_SSE = 2 2138}; 2139 2140extern enum fpmath_unit ix86_fpmath; 2141 2142enum tls_dialect 2143{ 2144 TLS_DIALECT_GNU, 2145 TLS_DIALECT_GNU2, 2146 TLS_DIALECT_SUN 2147}; 2148 2149extern enum tls_dialect ix86_tls_dialect; 2150 2151enum cmodel { 2152 CM_32, /* The traditional 32-bit ABI. */ 2153 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 2154 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 2155 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 2156 CM_LARGE, /* No assumptions. */ 2157 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ 2158 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */ 2159}; 2160 2161extern enum cmodel ix86_cmodel; 2162 2163/* Size of the RED_ZONE area. */ 2164#define RED_ZONE_SIZE 128 2165/* Reserved area of the red zone for temporaries. */ 2166#define RED_ZONE_RESERVE 8 2167 2168enum asm_dialect { 2169 ASM_ATT, 2170 ASM_INTEL 2171}; 2172 2173extern enum asm_dialect ix86_asm_dialect; 2174extern unsigned int ix86_preferred_stack_boundary; 2175extern int ix86_branch_cost, ix86_section_threshold; 2176 2177/* Smallest class containing REGNO. */ 2178extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2179 2180extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 2181extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 2182extern rtx ix86_compare_emitted; 2183 2184/* To properly truncate FP values into integers, we need to set i387 control 2185 word. We can't emit proper mode switching code before reload, as spills 2186 generated by reload may truncate values incorrectly, but we still can avoid 2187 redundant computation of new control word by the mode switching pass. 2188 The fldcw instructions are still emitted redundantly, but this is probably 2189 not going to be noticeable problem, as most CPUs do have fast path for 2190 the sequence. 2191 2192 The machinery is to emit simple truncation instructions and split them 2193 before reload to instructions having USEs of two memory locations that 2194 are filled by this code to old and new control word. 2195 2196 Post-reload pass may be later used to eliminate the redundant fildcw if 2197 needed. */ 2198 2199enum ix86_entity 2200{ 2201 I387_TRUNC = 0, 2202 I387_FLOOR, 2203 I387_CEIL, 2204 I387_MASK_PM, 2205 MAX_386_ENTITIES 2206}; 2207 2208enum ix86_stack_slot 2209{ 2210 SLOT_VIRTUAL = 0, 2211 SLOT_TEMP, 2212 SLOT_CW_STORED, 2213 SLOT_CW_TRUNC, 2214 SLOT_CW_FLOOR, 2215 SLOT_CW_CEIL, 2216 SLOT_CW_MASK_PM, 2217 MAX_386_STACK_LOCALS 2218}; 2219 2220/* Define this macro if the port needs extra instructions inserted 2221 for mode switching in an optimizing compilation. */ 2222 2223#define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2224 ix86_optimize_mode_switching[(ENTITY)] 2225 2226/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2227 initializer for an array of integers. Each initializer element N 2228 refers to an entity that needs mode switching, and specifies the 2229 number of different modes that might need to be set for this 2230 entity. The position of the initializer in the initializer - 2231 starting counting at zero - determines the integer that is used to 2232 refer to the mode-switched entity in question. */ 2233 2234#define NUM_MODES_FOR_MODE_SWITCHING \ 2235 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2236 2237/* ENTITY is an integer specifying a mode-switched entity. If 2238 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2239 return an integer value not larger than the corresponding element 2240 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2241 must be switched into prior to the execution of INSN. */ 2242 2243#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2244 2245/* This macro specifies the order in which modes for ENTITY are 2246 processed. 0 is the highest priority. */ 2247 2248#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2249 2250/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2251 is the set of hard registers live at the point where the insn(s) 2252 are to be inserted. */ 2253 2254#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2255 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ 2256 ? emit_i387_cw_initialization (MODE), 0 \ 2257 : 0) 2258 2259 2260/* Avoid renaming of stack registers, as doing so in combination with 2261 scheduling just increases amount of live registers at time and in 2262 the turn amount of fxch instructions needed. 2263 2264 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2265 2266#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2267 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 2268 2269 2270#define DLL_IMPORT_EXPORT_PREFIX '#' 2271 2272#define FASTCALL_PREFIX '@' 2273 2274struct machine_function GTY(()) 2275{ 2276 struct stack_local_entry *stack_locals; 2277 const char *some_ld_name; 2278 rtx force_align_arg_pointer; 2279 int save_varrargs_registers; 2280 int accesses_prev_frame; 2281 int optimize_mode_switching[MAX_386_ENTITIES]; 2282 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to 2283 determine the style used. */ 2284 int use_fast_prologue_epilogue; 2285 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed 2286 for. */ 2287 int use_fast_prologue_epilogue_nregs; 2288 /* If true, the current function needs the default PIC register, not 2289 an alternate register (on x86) and must not use the red zone (on 2290 x86_64), even if it's a leaf function. We don't want the 2291 function to be regarded as non-leaf because TLS calls need not 2292 affect register allocation. This flag is set when a TLS call 2293 instruction is expanded within a function, and never reset, even 2294 if all such instructions are optimized away. Use the 2295 ix86_current_function_calls_tls_descriptor macro for a better 2296 approximation. */ 2297 int tls_descriptor_call_expanded_p; 2298}; 2299 2300#define ix86_stack_locals (cfun->machine->stack_locals) 2301#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) 2302#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2303#define ix86_tls_descriptor_calls_expanded_in_cfun \ 2304 (cfun->machine->tls_descriptor_call_expanded_p) 2305/* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2306 calls are optimized away, we try to detect cases in which it was 2307 optimized away. Since such instructions (use (reg REG_SP)), we can 2308 verify whether there's any such instruction live by testing that 2309 REG_SP is live. */ 2310#define ix86_current_function_calls_tls_descriptor \ 2311 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG]) 2312 2313/* Control behavior of x86_file_start. */ 2314#define X86_FILE_START_VERSION_DIRECTIVE false 2315#define X86_FILE_START_FLTUSED false 2316 2317/* Flag to mark data that is in the large address area. */ 2318#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2319#define SYMBOL_REF_FAR_ADDR_P(X) \ 2320 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2321/* 2322Local variables: 2323version-control: t 2324End: 2325*/ 2326