i386.h revision 171836
1/* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GCC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to 19the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20Boston, MA 02110-1301, USA. */ 21 22/* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37/* Define the specific costs for a given cpu */ 38 39struct processor_costs { 40 const int add; /* cost of an add instruction */ 41 const int lea; /* cost of a lea instruction */ 42 const int shift_var; /* variable shift costs */ 43 const int shift_const; /* constant shift costs */ 44 const int mult_init[5]; /* cost of starting a multiply 45 in QImode, HImode, SImode, DImode, TImode*/ 46 const int mult_bit; /* cost of multiply per each bit set */ 47 const int divide[5]; /* cost of a divide/mod 48 in QImode, HImode, SImode, DImode, TImode*/ 49 int movsx; /* The cost of movsx operation. */ 50 int movzx; /* The cost of movzx operation. */ 51 const int large_insn; /* insns larger than this cost more */ 52 const int move_ratio; /* The threshold of number of scalar 53 memory-to-memory move insns. */ 54 const int movzbl_load; /* cost of loading using movzbl */ 55 const int int_load[3]; /* cost of loading integer registers 56 in QImode, HImode and SImode relative 57 to reg-reg move (2). */ 58 const int int_store[3]; /* cost of storing integer register 59 in QImode, HImode and SImode */ 60 const int fp_move; /* cost of reg,reg fld/fst */ 61 const int fp_load[3]; /* cost of loading FP register 62 in SFmode, DFmode and XFmode */ 63 const int fp_store[3]; /* cost of storing FP register 64 in SFmode, DFmode and XFmode */ 65 const int mmx_move; /* cost of moving MMX register. */ 66 const int mmx_load[2]; /* cost of loading MMX register 67 in SImode and DImode */ 68 const int mmx_store[2]; /* cost of storing MMX register 69 in SImode and DImode */ 70 const int sse_move; /* cost of moving SSE register. */ 71 const int sse_load[3]; /* cost of loading SSE register 72 in SImode, DImode and TImode*/ 73 const int sse_store[3]; /* cost of storing SSE register 74 in SImode, DImode and TImode*/ 75 const int mmxsse_to_integer; /* cost of moving mmxsse register to 76 integer and vice versa. */ 77 const int prefetch_block; /* bytes moved to cache for prefetch. */ 78 const int simultaneous_prefetches; /* number of parallel prefetch 79 operations. */ 80 const int branch_cost; /* Default value for BRANCH_COST. */ 81 const int fadd; /* cost of FADD and FSUB instructions. */ 82 const int fmul; /* cost of FMUL instruction. */ 83 const int fdiv; /* cost of FDIV instruction. */ 84 const int fabs; /* cost of FABS instruction. */ 85 const int fchs; /* cost of FCHS instruction. */ 86 const int fsqrt; /* cost of FSQRT instruction. */ 87}; 88 89extern const struct processor_costs *ix86_cost; 90 91/* Macros used in the machine description to test the flags. */ 92 93/* configure can arrange to make this 2, to force a 486. */ 94 95#ifndef TARGET_CPU_DEFAULT 96#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic 97#endif 98 99#ifndef TARGET_FPMATH_DEFAULT 100#define TARGET_FPMATH_DEFAULT \ 101 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 102#endif 103 104#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 105 106/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 107 compile-time constant. */ 108#ifdef IN_LIBGCC2 109#undef TARGET_64BIT 110#ifdef __x86_64__ 111#define TARGET_64BIT 1 112#else 113#define TARGET_64BIT 0 114#endif 115#else 116#ifndef TARGET_BI_ARCH 117#undef TARGET_64BIT 118#if TARGET_64BIT_DEFAULT 119#define TARGET_64BIT 1 120#else 121#define TARGET_64BIT 0 122#endif 123#endif 124#endif 125 126#define HAS_LONG_COND_BRANCH 1 127#define HAS_LONG_UNCOND_BRANCH 1 128 129#define TARGET_386 (ix86_tune == PROCESSOR_I386) 130#define TARGET_486 (ix86_tune == PROCESSOR_I486) 131#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 132#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 133#define TARGET_K6 (ix86_tune == PROCESSOR_K6) 134#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 135#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 136#define TARGET_K8 (ix86_tune == PROCESSOR_K8) 137#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 138#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 139#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) 140#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) 141#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) 142 143#define TUNEMASK (1 << ix86_tune) 144extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 145extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 146extern const int x86_branch_hints, x86_unroll_strlen; 147extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 148extern const int x86_use_himode_fiop, x86_use_simode_fiop; 149extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write; 150extern const int x86_read_modify, x86_split_long_moves; 151extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; 152extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 153extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 154extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 155extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 156extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 157extern const int x86_epilogue_using_move, x86_decompose_lea; 158extern const int x86_arch_always_fancy_math_387, x86_shift1; 159extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs; 160extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; 161extern const int x86_use_ffreep; 162extern const int x86_inter_unit_moves, x86_schedule; 163extern const int x86_use_bt; 164extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd; 165extern const int x86_use_incdec; 166extern const int x86_pad_returns; 167extern const int x86_partial_flag_reg_stall; 168extern int x86_prefetch_sse; 169 170#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) 171#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) 172#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK) 173#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK) 174#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK) 175/* For sane SSE instruction set generation we need fcomi instruction. It is 176 safe to enable all CMOVE instructions. */ 177#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 178#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 179#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK) 180#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK) 181#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK) 182#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) 183#define TARGET_MOVX (x86_movx & TUNEMASK) 184#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) 185#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK) 186#define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK) 187#define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK) 188#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) 189#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK) 190#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK) 191#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK) 192#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK) 193#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK) 194#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK) 195#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK) 196#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK) 197#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK) 198#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK) 199#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK) 200#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK) 201#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK) 202#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK) 203#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK) 204#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK) 205#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) 206#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 207 (x86_sse_partial_reg_dependency & TUNEMASK) 208#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK) 209#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) 210#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) 211#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) 212#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK) 213#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK) 214#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 215#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK) 216#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK) 217#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK) 218#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK) 219#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK) 220#define TARGET_SCHEDULE (x86_schedule & TUNEMASK) 221#define TARGET_USE_BT (x86_use_bt & TUNEMASK) 222#define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK) 223#define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK) 224 225#define ASSEMBLER_DIALECT (ix86_asm_dialect) 226 227#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 228#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 229 && (ix86_fpmath & FPMATH_387)) 230 231#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 232#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 233#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 234#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) 235 236#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch)) 237#define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch)) 238#define TARGET_CMPXCHG16B (x86_cmpxchg16b & (1 << ix86_arch)) 239#define TARGET_XADD (x86_xadd & (1 << ix86_arch)) 240 241#ifndef TARGET_64BIT_DEFAULT 242#define TARGET_64BIT_DEFAULT 0 243#endif 244#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 245#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 246#endif 247 248/* Once GDB has been enhanced to deal with functions without frame 249 pointers, we can change this to allow for elimination of 250 the frame pointer in leaf functions. */ 251#define TARGET_DEFAULT 0 252 253/* This is not really a target flag, but is done this way so that 254 it's analogous to similar code for Mach-O on PowerPC. darwin.h 255 redefines this to 1. */ 256#define TARGET_MACHO 0 257 258/* Subtargets may reset this to 1 in order to enable 96-bit long double 259 with the rounding mode forced to 53 bits. */ 260#define TARGET_96_ROUND_53_LONG_DOUBLE 0 261 262/* Sometimes certain combinations of command options do not make 263 sense on a particular target machine. You can define a macro 264 `OVERRIDE_OPTIONS' to take account of this. This macro, if 265 defined, is executed once just after all the command options have 266 been parsed. 267 268 Don't use this macro to turn on various extra optimizations for 269 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 270 271#define OVERRIDE_OPTIONS override_options () 272 273/* Define this to change the optimizations performed by default. */ 274#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 275 optimization_options ((LEVEL), (SIZE)) 276 277/* -march=native handling only makes sense with compiler running on 278 an x86 or x86_64 chip. If changing this condition, also change 279 the condition in driver-i386.c. */ 280#if defined(__i386__) || defined(__x86_64__) 281/* In driver-i386.c. */ 282extern const char *host_detect_local_cpu (int argc, const char **argv); 283#define EXTRA_SPEC_FUNCTIONS \ 284 { "local_cpu_detect", host_detect_local_cpu }, 285#define HAVE_LOCAL_CPU_DETECT 286#endif 287 288/* Support for configure-time defaults of some command line options. 289 The order here is important so that -march doesn't squash the 290 tune or cpu values. */ 291#define OPTION_DEFAULT_SPECS \ 292 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 293 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 294 {"arch", "%{!march=*:-march=%(VALUE)}"} 295 296/* Specs for the compiler proper */ 297 298#ifndef CC1_CPU_SPEC 299#define CC1_CPU_SPEC_1 "\ 300%{!mtune*: \ 301%{m386:mtune=i386 \ 302%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \ 303%{m486:-mtune=i486 \ 304%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \ 305%{mpentium:-mtune=pentium \ 306%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \ 307%{mpentiumpro:-mtune=pentiumpro \ 308%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \ 309%{mcpu=*:-mtune=%* \ 310%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \ 311%<mcpu=* \ 312%{mintel-syntax:-masm=intel \ 313%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 314%{mno-intel-syntax:-masm=att \ 315%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 316 317#ifndef HAVE_LOCAL_CPU_DETECT 318#define CC1_CPU_SPEC CC1_CPU_SPEC_1 319#else 320#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 321"%{march=native:%<march=native %:local_cpu_detect(arch) \ 322 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ 323%{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 324#endif 325#endif 326 327/* Target CPU builtins. */ 328#define TARGET_CPU_CPP_BUILTINS() \ 329 do \ 330 { \ 331 size_t arch_len = strlen (ix86_arch_string); \ 332 size_t tune_len = strlen (ix86_tune_string); \ 333 int last_arch_char = ix86_arch_string[arch_len - 1]; \ 334 int last_tune_char = ix86_tune_string[tune_len - 1]; \ 335 \ 336 if (TARGET_64BIT) \ 337 { \ 338 builtin_assert ("cpu=x86_64"); \ 339 builtin_assert ("machine=x86_64"); \ 340 builtin_define ("__amd64"); \ 341 builtin_define ("__amd64__"); \ 342 builtin_define ("__x86_64"); \ 343 builtin_define ("__x86_64__"); \ 344 } \ 345 else \ 346 { \ 347 builtin_assert ("cpu=i386"); \ 348 builtin_assert ("machine=i386"); \ 349 builtin_define_std ("i386"); \ 350 } \ 351 \ 352 /* Built-ins based on -mtune= (or -march= if no \ 353 -mtune= given). */ \ 354 if (TARGET_386) \ 355 builtin_define ("__tune_i386__"); \ 356 else if (TARGET_486) \ 357 builtin_define ("__tune_i486__"); \ 358 else if (TARGET_PENTIUM) \ 359 { \ 360 builtin_define ("__tune_i586__"); \ 361 builtin_define ("__tune_pentium__"); \ 362 if (last_tune_char == 'x') \ 363 builtin_define ("__tune_pentium_mmx__"); \ 364 } \ 365 else if (TARGET_PENTIUMPRO) \ 366 { \ 367 builtin_define ("__tune_i686__"); \ 368 builtin_define ("__tune_pentiumpro__"); \ 369 switch (last_tune_char) \ 370 { \ 371 case '3': \ 372 builtin_define ("__tune_pentium3__"); \ 373 /* FALLTHRU */ \ 374 case '2': \ 375 builtin_define ("__tune_pentium2__"); \ 376 break; \ 377 } \ 378 } \ 379 else if (TARGET_K6) \ 380 { \ 381 builtin_define ("__tune_k6__"); \ 382 if (last_tune_char == '2') \ 383 builtin_define ("__tune_k6_2__"); \ 384 else if (last_tune_char == '3') \ 385 builtin_define ("__tune_k6_3__"); \ 386 } \ 387 else if (TARGET_ATHLON) \ 388 { \ 389 builtin_define ("__tune_athlon__"); \ 390 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \ 391 if (last_tune_char != 'n' && last_tune_char != 'd') \ 392 builtin_define ("__tune_athlon_sse__"); \ 393 } \ 394 else if (TARGET_K8) \ 395 builtin_define ("__tune_k8__"); \ 396 else if (TARGET_PENTIUM4) \ 397 builtin_define ("__tune_pentium4__"); \ 398 else if (TARGET_NOCONA) \ 399 builtin_define ("__tune_nocona__"); \ 400 \ 401 if (TARGET_MMX) \ 402 builtin_define ("__MMX__"); \ 403 if (TARGET_3DNOW) \ 404 builtin_define ("__3dNOW__"); \ 405 if (TARGET_3DNOW_A) \ 406 builtin_define ("__3dNOW_A__"); \ 407 if (TARGET_SSE) \ 408 builtin_define ("__SSE__"); \ 409 if (TARGET_SSE2) \ 410 builtin_define ("__SSE2__"); \ 411 if (TARGET_SSE3) \ 412 builtin_define ("__SSE3__"); \ 413 if (TARGET_SSE_MATH && TARGET_SSE) \ 414 builtin_define ("__SSE_MATH__"); \ 415 if (TARGET_SSE_MATH && TARGET_SSE2) \ 416 builtin_define ("__SSE2_MATH__"); \ 417 \ 418 /* Built-ins based on -march=. */ \ 419 if (ix86_arch == PROCESSOR_I486) \ 420 { \ 421 builtin_define ("__i486"); \ 422 builtin_define ("__i486__"); \ 423 } \ 424 else if (ix86_arch == PROCESSOR_PENTIUM) \ 425 { \ 426 builtin_define ("__i586"); \ 427 builtin_define ("__i586__"); \ 428 builtin_define ("__pentium"); \ 429 builtin_define ("__pentium__"); \ 430 if (last_arch_char == 'x') \ 431 builtin_define ("__pentium_mmx__"); \ 432 } \ 433 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ 434 { \ 435 builtin_define ("__i686"); \ 436 builtin_define ("__i686__"); \ 437 builtin_define ("__pentiumpro"); \ 438 builtin_define ("__pentiumpro__"); \ 439 } \ 440 else if (ix86_arch == PROCESSOR_K6) \ 441 { \ 442 \ 443 builtin_define ("__k6"); \ 444 builtin_define ("__k6__"); \ 445 if (last_arch_char == '2') \ 446 builtin_define ("__k6_2__"); \ 447 else if (last_arch_char == '3') \ 448 builtin_define ("__k6_3__"); \ 449 } \ 450 else if (ix86_arch == PROCESSOR_ATHLON) \ 451 { \ 452 builtin_define ("__athlon"); \ 453 builtin_define ("__athlon__"); \ 454 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \ 455 if (last_tune_char != 'n' && last_tune_char != 'd') \ 456 builtin_define ("__athlon_sse__"); \ 457 } \ 458 else if (ix86_arch == PROCESSOR_K8) \ 459 { \ 460 builtin_define ("__k8"); \ 461 builtin_define ("__k8__"); \ 462 } \ 463 else if (ix86_arch == PROCESSOR_PENTIUM4) \ 464 { \ 465 builtin_define ("__pentium4"); \ 466 builtin_define ("__pentium4__"); \ 467 } \ 468 else if (ix86_arch == PROCESSOR_NOCONA) \ 469 { \ 470 builtin_define ("__nocona"); \ 471 builtin_define ("__nocona__"); \ 472 } \ 473 } \ 474 while (0) 475 476#define TARGET_CPU_DEFAULT_i386 0 477#define TARGET_CPU_DEFAULT_i486 1 478#define TARGET_CPU_DEFAULT_pentium 2 479#define TARGET_CPU_DEFAULT_pentium_mmx 3 480#define TARGET_CPU_DEFAULT_pentiumpro 4 481#define TARGET_CPU_DEFAULT_pentium2 5 482#define TARGET_CPU_DEFAULT_pentium3 6 483#define TARGET_CPU_DEFAULT_pentium4 7 484#define TARGET_CPU_DEFAULT_k6 8 485#define TARGET_CPU_DEFAULT_k6_2 9 486#define TARGET_CPU_DEFAULT_k6_3 10 487#define TARGET_CPU_DEFAULT_athlon 11 488#define TARGET_CPU_DEFAULT_athlon_sse 12 489#define TARGET_CPU_DEFAULT_k8 13 490#define TARGET_CPU_DEFAULT_pentium_m 14 491#define TARGET_CPU_DEFAULT_prescott 15 492#define TARGET_CPU_DEFAULT_nocona 16 493#define TARGET_CPU_DEFAULT_generic 17 494 495#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 496 "pentiumpro", "pentium2", "pentium3", \ 497 "pentium4", "k6", "k6-2", "k6-3",\ 498 "athlon", "athlon-4", "k8", \ 499 "pentium-m", "prescott", "nocona", \ 500 "generic"} 501 502#ifndef CC1_SPEC 503#define CC1_SPEC "%(cc1_cpu) " 504#endif 505 506/* This macro defines names of additional specifications to put in the 507 specs that can be used in various specifications like CC1_SPEC. Its 508 definition is an initializer with a subgrouping for each command option. 509 510 Each subgrouping contains a string constant, that defines the 511 specification name, and a string constant that used by the GCC driver 512 program. 513 514 Do not define this macro if it does not need to do anything. */ 515 516#ifndef SUBTARGET_EXTRA_SPECS 517#define SUBTARGET_EXTRA_SPECS 518#endif 519 520#define EXTRA_SPECS \ 521 { "cc1_cpu", CC1_CPU_SPEC }, \ 522 SUBTARGET_EXTRA_SPECS 523 524/* target machine storage layout */ 525 526#define LONG_DOUBLE_TYPE_SIZE 80 527 528/* Set the value of FLT_EVAL_METHOD in float.h. When using only the 529 FPU, assume that the fpcw is set to extended precision; when using 530 only SSE, rounding is correct; when using both SSE and the FPU, 531 the rounding precision is indeterminate, since either may be chosen 532 apparently at random. */ 533#define TARGET_FLT_EVAL_METHOD \ 534 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 535 536#define SHORT_TYPE_SIZE 16 537#define INT_TYPE_SIZE 32 538#define FLOAT_TYPE_SIZE 32 539#ifndef LONG_TYPE_SIZE 540#define LONG_TYPE_SIZE BITS_PER_WORD 541#endif 542#define DOUBLE_TYPE_SIZE 64 543#define LONG_LONG_TYPE_SIZE 64 544 545#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 546#define MAX_BITS_PER_WORD 64 547#else 548#define MAX_BITS_PER_WORD 32 549#endif 550 551/* Define this if most significant byte of a word is the lowest numbered. */ 552/* That is true on the 80386. */ 553 554#define BITS_BIG_ENDIAN 0 555 556/* Define this if most significant byte of a word is the lowest numbered. */ 557/* That is not true on the 80386. */ 558#define BYTES_BIG_ENDIAN 0 559 560/* Define this if most significant word of a multiword number is the lowest 561 numbered. */ 562/* Not true for 80386 */ 563#define WORDS_BIG_ENDIAN 0 564 565/* Width of a word, in units (bytes). */ 566#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 567#ifdef IN_LIBGCC2 568#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 569#else 570#define MIN_UNITS_PER_WORD 4 571#endif 572 573/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 574#define PARM_BOUNDARY BITS_PER_WORD 575 576/* Boundary (in *bits*) on which stack pointer should be aligned. */ 577#define STACK_BOUNDARY BITS_PER_WORD 578 579/* Boundary (in *bits*) on which the stack pointer prefers to be 580 aligned; the compiler cannot rely on having this alignment. */ 581#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 582 583/* As of July 2001, many runtimes do not align the stack properly when 584 entering main. This causes expand_main_function to forcibly align 585 the stack, which results in aligned frames for functions called from 586 main, though it does nothing for the alignment of main itself. */ 587#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 588 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 589 590/* Minimum allocation boundary for the code of a function. */ 591#define FUNCTION_BOUNDARY 8 592 593/* C++ stores the virtual bit in the lowest bit of function pointers. */ 594#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 595 596/* Alignment of field after `int : 0' in a structure. */ 597 598#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 599 600/* Minimum size in bits of the largest boundary to which any 601 and all fundamental data types supported by the hardware 602 might need to be aligned. No data type wants to be aligned 603 rounder than this. 604 605 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 606 and Pentium Pro XFmode values at 128 bit boundaries. */ 607 608#define BIGGEST_ALIGNMENT 128 609 610/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 611#define ALIGN_MODE_128(MODE) \ 612 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 613 614/* The published ABIs say that doubles should be aligned on word 615 boundaries, so lower the alignment for structure fields unless 616 -malign-double is set. */ 617 618/* ??? Blah -- this macro is used directly by libobjc. Since it 619 supports no vector modes, cut out the complexity and fall back 620 on BIGGEST_FIELD_ALIGNMENT. */ 621#ifdef IN_TARGET_LIBS 622#ifdef __x86_64__ 623#define BIGGEST_FIELD_ALIGNMENT 128 624#else 625#define BIGGEST_FIELD_ALIGNMENT 32 626#endif 627#else 628#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 629 x86_field_alignment (FIELD, COMPUTED) 630#endif 631 632/* If defined, a C expression to compute the alignment given to a 633 constant that is being placed in memory. EXP is the constant 634 and ALIGN is the alignment that the object would ordinarily have. 635 The value of this macro is used instead of that alignment to align 636 the object. 637 638 If this macro is not defined, then ALIGN is used. 639 640 The typical use of this macro is to increase alignment for string 641 constants to be word aligned so that `strcpy' calls that copy 642 constants can be done inline. */ 643 644#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 645 646/* If defined, a C expression to compute the alignment for a static 647 variable. TYPE is the data type, and ALIGN is the alignment that 648 the object would ordinarily have. The value of this macro is used 649 instead of that alignment to align the object. 650 651 If this macro is not defined, then ALIGN is used. 652 653 One use of this macro is to increase alignment of medium-size 654 data to make it all fit in fewer cache lines. Another is to 655 cause character arrays to be word-aligned so that `strcpy' calls 656 that copy constants to character arrays can be done inline. */ 657 658#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 659 660/* If defined, a C expression to compute the alignment for a local 661 variable. TYPE is the data type, and ALIGN is the alignment that 662 the object would ordinarily have. The value of this macro is used 663 instead of that alignment to align the object. 664 665 If this macro is not defined, then ALIGN is used. 666 667 One use of this macro is to increase alignment of medium-size 668 data to make it all fit in fewer cache lines. */ 669 670#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 671 672/* If defined, a C expression that gives the alignment boundary, in 673 bits, of an argument with the specified mode and type. If it is 674 not defined, `PARM_BOUNDARY' is used for all arguments. */ 675 676#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 677 ix86_function_arg_boundary ((MODE), (TYPE)) 678 679/* Set this nonzero if move instructions will actually fail to work 680 when given unaligned data. */ 681#define STRICT_ALIGNMENT 0 682 683/* If bit field type is int, don't let it cross an int, 684 and give entire struct the alignment of an int. */ 685/* Required on the 386 since it doesn't have bit-field insns. */ 686#define PCC_BITFIELD_TYPE_MATTERS 1 687 688/* Standard register usage. */ 689 690/* This processor has special stack-like registers. See reg-stack.c 691 for details. */ 692 693#define STACK_REGS 694#define IS_STACK_MODE(MODE) \ 695 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ 696 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ 697 || (MODE) == XFmode) 698 699/* Number of actual hardware registers. 700 The hardware registers are assigned numbers for the compiler 701 from 0 to just below FIRST_PSEUDO_REGISTER. 702 All registers that the compiler knows about must be given numbers, 703 even those that are not normally considered general registers. 704 705 In the 80386 we give the 8 general purpose registers the numbers 0-7. 706 We number the floating point registers 8-15. 707 Note that registers 0-7 can be accessed as a short or int, 708 while only 0-3 may be used with byte `mov' instructions. 709 710 Reg 16 does not correspond to any hardware register, but instead 711 appears in the RTL as an argument pointer prior to reload, and is 712 eliminated during reloading in favor of either the stack or frame 713 pointer. */ 714 715#define FIRST_PSEUDO_REGISTER 53 716 717/* Number of hardware registers that go into the DWARF-2 unwind info. 718 If not defined, equals FIRST_PSEUDO_REGISTER. */ 719 720#define DWARF_FRAME_REGISTERS 17 721 722/* 1 for registers that have pervasive standard uses 723 and are not available for the register allocator. 724 On the 80386, the stack pointer is such, as is the arg pointer. 725 726 The value is zero if the register is not fixed on either 32 or 727 64 bit targets, one if the register if fixed on both 32 and 64 728 bit targets, two if it is only fixed on 32bit targets and three 729 if its only fixed on 64bit targets. 730 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 731 */ 732#define FIXED_REGISTERS \ 733/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 734{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 735/*arg,flags,fpsr,dir,frame*/ \ 736 1, 1, 1, 1, 1, \ 737/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 738 0, 0, 0, 0, 0, 0, 0, 0, \ 739/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 740 0, 0, 0, 0, 0, 0, 0, 0, \ 741/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 742 2, 2, 2, 2, 2, 2, 2, 2, \ 743/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 744 2, 2, 2, 2, 2, 2, 2, 2} 745 746 747/* 1 for registers not available across function calls. 748 These must include the FIXED_REGISTERS and also any 749 registers that can be used without being saved. 750 The latter must include the registers where values are returned 751 and the register where structure-value addresses are passed. 752 Aside from that, you can include as many other registers as you like. 753 754 The value is zero if the register is not call used on either 32 or 755 64 bit targets, one if the register if call used on both 32 and 64 756 bit targets, two if it is only call used on 32bit targets and three 757 if its only call used on 64bit targets. 758 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 759*/ 760#define CALL_USED_REGISTERS \ 761/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 762{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 763/*arg,flags,fpsr,dir,frame*/ \ 764 1, 1, 1, 1, 1, \ 765/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 766 1, 1, 1, 1, 1, 1, 1, 1, \ 767/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 768 1, 1, 1, 1, 1, 1, 1, 1, \ 769/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 770 1, 1, 1, 1, 2, 2, 2, 2, \ 771/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 772 1, 1, 1, 1, 1, 1, 1, 1} \ 773 774/* Order in which to allocate registers. Each register must be 775 listed once, even those in FIXED_REGISTERS. List frame pointer 776 late and fixed registers last. Note that, in general, we prefer 777 registers listed in CALL_USED_REGISTERS, keeping the others 778 available for storage of persistent values. 779 780 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 781 so this is just empty initializer for array. */ 782 783#define REG_ALLOC_ORDER \ 784{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 785 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 786 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 787 48, 49, 50, 51, 52 } 788 789/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 790 to be rearranged based on a particular function. When using sse math, 791 we want to allocate SSE before x87 registers and vice vera. */ 792 793#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 794 795 796/* Macro to conditionally modify fixed_regs/call_used_regs. */ 797#define CONDITIONAL_REGISTER_USAGE \ 798do { \ 799 int i; \ 800 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 801 { \ 802 if (fixed_regs[i] > 1) \ 803 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ 804 if (call_used_regs[i] > 1) \ 805 call_used_regs[i] = (call_used_regs[i] \ 806 == (TARGET_64BIT ? 3 : 2)); \ 807 } \ 808 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 809 { \ 810 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 811 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 812 } \ 813 if (! TARGET_MMX) \ 814 { \ 815 int i; \ 816 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 817 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 818 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 819 } \ 820 if (! TARGET_SSE) \ 821 { \ 822 int i; \ 823 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 824 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 825 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 826 } \ 827 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 828 { \ 829 int i; \ 830 HARD_REG_SET x; \ 831 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 832 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 833 if (TEST_HARD_REG_BIT (x, i)) \ 834 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ 835 } \ 836 if (! TARGET_64BIT) \ 837 { \ 838 int i; \ 839 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ 840 reg_names[i] = ""; \ 841 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ 842 reg_names[i] = ""; \ 843 } \ 844 } while (0) 845 846/* Return number of consecutive hard regs needed starting at reg REGNO 847 to hold something of mode MODE. 848 This is ordinarily the length in words of a value of mode MODE 849 but can be less for certain modes in special long registers. 850 851 Actually there are no two word move instructions for consecutive 852 registers. And only registers 0-3 may have mov byte instructions 853 applied to them. 854 */ 855 856#define HARD_REGNO_NREGS(REGNO, MODE) \ 857 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 858 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 859 : ((MODE) == XFmode \ 860 ? (TARGET_64BIT ? 2 : 3) \ 861 : (MODE) == XCmode \ 862 ? (TARGET_64BIT ? 4 : 6) \ 863 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 864 865#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 866 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 867 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 868 ? 0 \ 869 : ((MODE) == XFmode || (MODE) == XCmode)) \ 870 : 0) 871 872#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 873 874#define VALID_SSE2_REG_MODE(MODE) \ 875 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 876 || (MODE) == V2DImode || (MODE) == DFmode) 877 878#define VALID_SSE_REG_MODE(MODE) \ 879 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 880 || (MODE) == SFmode || (MODE) == TFmode) 881 882#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 883 ((MODE) == V2SFmode || (MODE) == SFmode) 884 885#define VALID_MMX_REG_MODE(MODE) \ 886 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 887 || (MODE) == V2SImode || (MODE) == SImode) 888 889/* ??? No autovectorization into MMX or 3DNOW until we can reliably 890 place emms and femms instructions. */ 891#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD) 892 893#define VALID_FP_MODE_P(MODE) \ 894 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 895 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 896 897#define VALID_INT_MODE_P(MODE) \ 898 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 899 || (MODE) == DImode \ 900 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 901 || (MODE) == CDImode \ 902 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 903 || (MODE) == TFmode || (MODE) == TCmode))) 904 905/* Return true for modes passed in SSE registers. */ 906#define SSE_REG_MODE_P(MODE) \ 907 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ 908 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ 909 || (MODE) == V4SFmode || (MODE) == V4SImode) 910 911/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 912 913#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 914 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 915 916/* Value is 1 if it is a good idea to tie two pseudo registers 917 when one has mode MODE1 and one has mode MODE2. 918 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 919 for any hard reg, then this must be 0 for correct output. */ 920 921#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 922 923/* It is possible to write patterns to move flags; but until someone 924 does it, */ 925#define AVOID_CCMODE_COPIES 926 927/* Specify the modes required to caller save a given hard regno. 928 We do this on i386 to prevent flags from being saved at all. 929 930 Kill any attempts to combine saving of modes. */ 931 932#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 933 (CC_REGNO_P (REGNO) ? VOIDmode \ 934 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 935 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\ 936 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 937 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 938 : (MODE)) 939/* Specify the registers used for certain standard purposes. 940 The values of these macros are register numbers. */ 941 942/* on the 386 the pc register is %eip, and is not usable as a general 943 register. The ordinary mov instructions won't work */ 944/* #define PC_REGNUM */ 945 946/* Register to use for pushing function arguments. */ 947#define STACK_POINTER_REGNUM 7 948 949/* Base register for access to local variables of the function. */ 950#define HARD_FRAME_POINTER_REGNUM 6 951 952/* Base register for access to local variables of the function. */ 953#define FRAME_POINTER_REGNUM 20 954 955/* First floating point reg */ 956#define FIRST_FLOAT_REG 8 957 958/* First & last stack-like regs */ 959#define FIRST_STACK_REG FIRST_FLOAT_REG 960#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 961 962#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 963#define LAST_SSE_REG (FIRST_SSE_REG + 7) 964 965#define FIRST_MMX_REG (LAST_SSE_REG + 1) 966#define LAST_MMX_REG (FIRST_MMX_REG + 7) 967 968#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 969#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 970 971#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 972#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 973 974/* Value should be nonzero if functions must have frame pointers. 975 Zero means the frame pointer need not be set up (and parms 976 may be accessed via the stack pointer) in functions that seem suitable. 977 This is computed in `reload', in reload1.c. */ 978#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 979 980/* Override this in other tm.h files to cope with various OS lossage 981 requiring a frame pointer. */ 982#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 983#define SUBTARGET_FRAME_POINTER_REQUIRED 0 984#endif 985 986/* Make sure we can access arbitrary call frames. */ 987#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 988 989/* Base register for access to arguments of the function. */ 990#define ARG_POINTER_REGNUM 16 991 992/* Register in which static-chain is passed to a function. 993 We do use ECX as static chain register for 32 bit ABI. On the 994 64bit ABI, ECX is an argument register, so we use R10 instead. */ 995#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 996 997/* Register to hold the addressing base for position independent 998 code access to data items. We don't use PIC pointer for 64bit 999 mode. Define the regnum to dummy value to prevent gcc from 1000 pessimizing code dealing with EBX. 1001 1002 To avoid clobbering a call-saved register unnecessarily, we renumber 1003 the pic register when possible. The change is visible after the 1004 prologue has been emitted. */ 1005 1006#define REAL_PIC_OFFSET_TABLE_REGNUM 3 1007 1008#define PIC_OFFSET_TABLE_REGNUM \ 1009 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 1010 || !flag_pic ? INVALID_REGNUM \ 1011 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1012 : REAL_PIC_OFFSET_TABLE_REGNUM) 1013 1014#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1015 1016/* A C expression which can inhibit the returning of certain function 1017 values in registers, based on the type of value. A nonzero value 1018 says to return the function value in memory, just as large 1019 structures are always returned. Here TYPE will be a C expression 1020 of type `tree', representing the data type of the value. 1021 1022 Note that values of mode `BLKmode' must be explicitly handled by 1023 this macro. Also, the option `-fpcc-struct-return' takes effect 1024 regardless of this macro. On most systems, it is possible to 1025 leave the macro undefined; this causes a default definition to be 1026 used, whose value is the constant 1 for `BLKmode' values, and 0 1027 otherwise. 1028 1029 Do not use this macro to indicate that structures and unions 1030 should always be returned in memory. You should instead use 1031 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1032 1033#define RETURN_IN_MEMORY(TYPE) \ 1034 ix86_return_in_memory (TYPE) 1035 1036/* This is overridden by <cygwin.h>. */ 1037#define MS_AGGREGATE_RETURN 0 1038 1039/* This is overridden by <netware.h>. */ 1040#define KEEP_AGGREGATE_RETURN_POINTER 0 1041 1042/* Define the classes of registers for register constraints in the 1043 machine description. Also define ranges of constants. 1044 1045 One of the classes must always be named ALL_REGS and include all hard regs. 1046 If there is more than one class, another class must be named NO_REGS 1047 and contain no registers. 1048 1049 The name GENERAL_REGS must be the name of a class (or an alias for 1050 another name such as ALL_REGS). This is the class of registers 1051 that is allowed by "g" or "r" in a register constraint. 1052 Also, registers outside this class are allocated only when 1053 instructions express preferences for them. 1054 1055 The classes must be numbered in nondecreasing order; that is, 1056 a larger-numbered class must never be contained completely 1057 in a smaller-numbered class. 1058 1059 For any two classes, it is very desirable that there be another 1060 class that represents their union. 1061 1062 It might seem that class BREG is unnecessary, since no useful 386 1063 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1064 and the "b" register constraint is useful in asms for syscalls. 1065 1066 The flags and fpsr registers are in no class. */ 1067 1068enum reg_class 1069{ 1070 NO_REGS, 1071 AREG, DREG, CREG, BREG, SIREG, DIREG, 1072 AD_REGS, /* %eax/%edx for DImode */ 1073 Q_REGS, /* %eax %ebx %ecx %edx */ 1074 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1075 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1076 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1077 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1078 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1079 FLOAT_REGS, 1080 SSE_REGS, 1081 MMX_REGS, 1082 FP_TOP_SSE_REGS, 1083 FP_SECOND_SSE_REGS, 1084 FLOAT_SSE_REGS, 1085 FLOAT_INT_REGS, 1086 INT_SSE_REGS, 1087 FLOAT_INT_SSE_REGS, 1088 ALL_REGS, LIM_REG_CLASSES 1089}; 1090 1091#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1092 1093#define INTEGER_CLASS_P(CLASS) \ 1094 reg_class_subset_p ((CLASS), GENERAL_REGS) 1095#define FLOAT_CLASS_P(CLASS) \ 1096 reg_class_subset_p ((CLASS), FLOAT_REGS) 1097#define SSE_CLASS_P(CLASS) \ 1098 ((CLASS) == SSE_REGS) 1099#define MMX_CLASS_P(CLASS) \ 1100 ((CLASS) == MMX_REGS) 1101#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1102 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1103#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1104 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1105#define MAYBE_SSE_CLASS_P(CLASS) \ 1106 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1107#define MAYBE_MMX_CLASS_P(CLASS) \ 1108 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1109 1110#define Q_CLASS_P(CLASS) \ 1111 reg_class_subset_p ((CLASS), Q_REGS) 1112 1113/* Give names of register classes as strings for dump file. */ 1114 1115#define REG_CLASS_NAMES \ 1116{ "NO_REGS", \ 1117 "AREG", "DREG", "CREG", "BREG", \ 1118 "SIREG", "DIREG", \ 1119 "AD_REGS", \ 1120 "Q_REGS", "NON_Q_REGS", \ 1121 "INDEX_REGS", \ 1122 "LEGACY_REGS", \ 1123 "GENERAL_REGS", \ 1124 "FP_TOP_REG", "FP_SECOND_REG", \ 1125 "FLOAT_REGS", \ 1126 "SSE_REGS", \ 1127 "MMX_REGS", \ 1128 "FP_TOP_SSE_REGS", \ 1129 "FP_SECOND_SSE_REGS", \ 1130 "FLOAT_SSE_REGS", \ 1131 "FLOAT_INT_REGS", \ 1132 "INT_SSE_REGS", \ 1133 "FLOAT_INT_SSE_REGS", \ 1134 "ALL_REGS" } 1135 1136/* Define which registers fit in which classes. 1137 This is an initializer for a vector of HARD_REG_SET 1138 of length N_REG_CLASSES. */ 1139 1140#define REG_CLASS_CONTENTS \ 1141{ { 0x00, 0x0 }, \ 1142 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1143 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1144 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1145 { 0x03, 0x0 }, /* AD_REGS */ \ 1146 { 0x0f, 0x0 }, /* Q_REGS */ \ 1147 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1148 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1149 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1150 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1151 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1152 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1153{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1154{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1155{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1156{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1157{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1158 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1159{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1160{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1161{ 0xffffffff,0x1fffff } \ 1162} 1163 1164/* The same information, inverted: 1165 Return the class number of the smallest class containing 1166 reg number REGNO. This could be a conditional expression 1167 or could index an array. */ 1168 1169#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1170 1171/* When defined, the compiler allows registers explicitly used in the 1172 rtl to be used as spill registers but prevents the compiler from 1173 extending the lifetime of these registers. */ 1174 1175#define SMALL_REGISTER_CLASSES 1 1176 1177#define QI_REG_P(X) \ 1178 (REG_P (X) && REGNO (X) < 4) 1179 1180#define GENERAL_REGNO_P(N) \ 1181 ((N) < 8 || REX_INT_REGNO_P (N)) 1182 1183#define GENERAL_REG_P(X) \ 1184 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1185 1186#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1187 1188#define NON_QI_REG_P(X) \ 1189 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1190 1191#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1192#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1193 1194#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1195#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1196#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1197#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1198 1199#define SSE_REGNO_P(N) \ 1200 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1201 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1202 1203#define REX_SSE_REGNO_P(N) \ 1204 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG) 1205 1206#define SSE_REGNO(N) \ 1207 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1208#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1209 1210#define SSE_FLOAT_MODE_P(MODE) \ 1211 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1212 1213#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1214#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1215 1216#define STACK_REG_P(XOP) \ 1217 (REG_P (XOP) && \ 1218 REGNO (XOP) >= FIRST_STACK_REG && \ 1219 REGNO (XOP) <= LAST_STACK_REG) 1220 1221#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1222 1223#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1224 1225#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1226#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1227 1228/* The class value for index registers, and the one for base regs. */ 1229 1230#define INDEX_REG_CLASS INDEX_REGS 1231#define BASE_REG_CLASS GENERAL_REGS 1232 1233/* Place additional restrictions on the register class to use when it 1234 is necessary to be able to hold a value of mode MODE in a reload 1235 register for which class CLASS would ordinarily be used. */ 1236 1237#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1238 ((MODE) == QImode && !TARGET_64BIT \ 1239 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1240 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1241 ? Q_REGS : (CLASS)) 1242 1243/* Given an rtx X being reloaded into a reg required to be 1244 in class CLASS, return the class of reg to actually use. 1245 In general this is just CLASS; but on some machines 1246 in some cases it is preferable to use a more restrictive class. 1247 On the 80386 series, we prevent floating constants from being 1248 reloaded into floating registers (since no move-insn can do that) 1249 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1250 1251/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1252 QImode must go into class Q_REGS. 1253 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1254 movdf to do mem-to-mem moves through integer regs. */ 1255 1256#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1257 ix86_preferred_reload_class ((X), (CLASS)) 1258 1259/* Discourage putting floating-point values in SSE registers unless 1260 SSE math is being used, and likewise for the 387 registers. */ 1261 1262#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ 1263 ix86_preferred_output_reload_class ((X), (CLASS)) 1264 1265/* If we are copying between general and FP registers, we need a memory 1266 location. The same is true for SSE and MMX registers. */ 1267#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1268 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1269 1270/* QImode spills from non-QI registers need a scratch. This does not 1271 happen often -- the only example so far requires an uninitialized 1272 pseudo. */ 1273 1274#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1275 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1276 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1277 ? Q_REGS : NO_REGS) 1278 1279/* Return the maximum number of consecutive registers 1280 needed to represent mode MODE in a register of class CLASS. */ 1281/* On the 80386, this is the size of MODE in words, 1282 except in the FP regs, where a single reg is always enough. */ 1283#define CLASS_MAX_NREGS(CLASS, MODE) \ 1284 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1285 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1286 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ 1287 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1288 1289/* A C expression whose value is nonzero if pseudos that have been 1290 assigned to registers of class CLASS would likely be spilled 1291 because registers of CLASS are needed for spill registers. 1292 1293 The default value of this macro returns 1 if CLASS has exactly one 1294 register and zero otherwise. On most machines, this default 1295 should be used. Only define this macro to some other expression 1296 if pseudo allocated by `local-alloc.c' end up in memory because 1297 their hard registers were needed for spill registers. If this 1298 macro returns nonzero for those classes, those pseudos will only 1299 be allocated by `global.c', which knows how to reallocate the 1300 pseudo to another register. If there would not be another 1301 register available for reallocation, you should not change the 1302 definition of this macro since the only effect of such a 1303 definition would be to slow down register allocation. */ 1304 1305#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1306 (((CLASS) == AREG) \ 1307 || ((CLASS) == DREG) \ 1308 || ((CLASS) == CREG) \ 1309 || ((CLASS) == BREG) \ 1310 || ((CLASS) == AD_REGS) \ 1311 || ((CLASS) == SIREG) \ 1312 || ((CLASS) == DIREG) \ 1313 || ((CLASS) == FP_TOP_REG) \ 1314 || ((CLASS) == FP_SECOND_REG)) 1315 1316/* Return a class of registers that cannot change FROM mode to TO mode. */ 1317 1318#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1319 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1320 1321/* Stack layout; function entry, exit and calling. */ 1322 1323/* Define this if pushing a word on the stack 1324 makes the stack pointer a smaller address. */ 1325#define STACK_GROWS_DOWNWARD 1326 1327/* Define this to nonzero if the nominal address of the stack frame 1328 is at the high-address end of the local variables; 1329 that is, each additional local variable allocated 1330 goes at a more negative offset in the frame. */ 1331#define FRAME_GROWS_DOWNWARD 1 1332 1333/* Offset within stack frame to start allocating local variables at. 1334 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1335 first local allocated. Otherwise, it is the offset to the BEGINNING 1336 of the first local allocated. */ 1337#define STARTING_FRAME_OFFSET 0 1338 1339/* If we generate an insn to push BYTES bytes, 1340 this says how many the stack pointer really advances by. 1341 On 386, we have pushw instruction that decrements by exactly 2 no 1342 matter what the position was, there is no pushb. 1343 But as CIE data alignment factor on this arch is -4, we need to make 1344 sure all stack pointer adjustments are in multiple of 4. 1345 1346 For 64bit ABI we round up to 8 bytes. 1347 */ 1348 1349#define PUSH_ROUNDING(BYTES) \ 1350 (TARGET_64BIT \ 1351 ? (((BYTES) + 7) & (-8)) \ 1352 : (((BYTES) + 3) & (-4))) 1353 1354/* If defined, the maximum amount of space required for outgoing arguments will 1355 be computed and placed into the variable 1356 `current_function_outgoing_args_size'. No space will be pushed onto the 1357 stack for each call; instead, the function prologue should increase the stack 1358 frame size by this amount. */ 1359 1360#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1361 1362/* If defined, a C expression whose value is nonzero when we want to use PUSH 1363 instructions to pass outgoing arguments. */ 1364 1365#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1366 1367/* We want the stack and args grow in opposite directions, even if 1368 PUSH_ARGS is 0. */ 1369#define PUSH_ARGS_REVERSED 1 1370 1371/* Offset of first parameter from the argument pointer register value. */ 1372#define FIRST_PARM_OFFSET(FNDECL) 0 1373 1374/* Define this macro if functions should assume that stack space has been 1375 allocated for arguments even when their values are passed in registers. 1376 1377 The value of this macro is the size, in bytes, of the area reserved for 1378 arguments passed in registers for the function represented by FNDECL. 1379 1380 This space can be allocated by the caller, or be a part of the 1381 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1382 which. */ 1383#define REG_PARM_STACK_SPACE(FNDECL) 0 1384 1385/* Value is the number of bytes of arguments automatically 1386 popped when returning from a subroutine call. 1387 FUNDECL is the declaration node of the function (as a tree), 1388 FUNTYPE is the data type of the function (as a tree), 1389 or for a library call it is an identifier node for the subroutine name. 1390 SIZE is the number of bytes of arguments passed on the stack. 1391 1392 On the 80386, the RTD insn may be used to pop them if the number 1393 of args is fixed, but if the number is variable then the caller 1394 must pop them all. RTD can't be used for library calls now 1395 because the library is compiled with the Unix compiler. 1396 Use of RTD is a selectable option, since it is incompatible with 1397 standard Unix calling sequences. If the option is not selected, 1398 the caller must always pop the args. 1399 1400 The attribute stdcall is equivalent to RTD on a per module basis. */ 1401 1402#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1403 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1404 1405#define FUNCTION_VALUE_REGNO_P(N) \ 1406 ix86_function_value_regno_p (N) 1407 1408/* Define how to find the value returned by a library function 1409 assuming the value has mode MODE. */ 1410 1411#define LIBCALL_VALUE(MODE) \ 1412 ix86_libcall_value (MODE) 1413 1414/* Define the size of the result block used for communication between 1415 untyped_call and untyped_return. The block contains a DImode value 1416 followed by the block used by fnsave and frstor. */ 1417 1418#define APPLY_RESULT_SIZE (8+108) 1419 1420/* 1 if N is a possible register number for function argument passing. */ 1421#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1422 1423/* Define a data type for recording info about an argument list 1424 during the scan of that argument list. This data type should 1425 hold all necessary information about the function itself 1426 and about the args processed so far, enough to enable macros 1427 such as FUNCTION_ARG to determine where the next arg should go. */ 1428 1429typedef struct ix86_args { 1430 int words; /* # words passed so far */ 1431 int nregs; /* # registers available for passing */ 1432 int regno; /* next available register number */ 1433 int fastcall; /* fastcall calling convention is used */ 1434 int sse_words; /* # sse words passed so far */ 1435 int sse_nregs; /* # sse registers available for passing */ 1436 int warn_sse; /* True when we want to warn about SSE ABI. */ 1437 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1438 int sse_regno; /* next available sse register number */ 1439 int mmx_words; /* # mmx words passed so far */ 1440 int mmx_nregs; /* # mmx registers available for passing */ 1441 int mmx_regno; /* next available mmx register number */ 1442 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1443 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should 1444 be passed in SSE registers. Otherwise 0. */ 1445} CUMULATIVE_ARGS; 1446 1447/* Initialize a variable CUM of type CUMULATIVE_ARGS 1448 for a call to a function whose data type is FNTYPE. 1449 For a library call, FNTYPE is 0. */ 1450 1451#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1452 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1453 1454/* Update the data in CUM to advance over an argument 1455 of mode MODE and data type TYPE. 1456 (TYPE is null for libcalls where that information may not be available.) */ 1457 1458#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1459 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1460 1461/* Define where to put the arguments to a function. 1462 Value is zero to push the argument on the stack, 1463 or a hard register in which to store the argument. 1464 1465 MODE is the argument's machine mode. 1466 TYPE is the data type of the argument (as a tree). 1467 This is null for libcalls where that information may 1468 not be available. 1469 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1470 the preceding args and about the function being called. 1471 NAMED is nonzero if this argument is a named parameter 1472 (otherwise it is an extra parameter matching an ellipsis). */ 1473 1474#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1475 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1476 1477/* Implement `va_start' for varargs and stdarg. */ 1478#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ 1479 ix86_va_start (VALIST, NEXTARG) 1480 1481#define TARGET_ASM_FILE_END ix86_file_end 1482#define NEED_INDICATE_EXEC_STACK 0 1483 1484/* Output assembler code to FILE to increment profiler label # LABELNO 1485 for profiling a function entry. */ 1486 1487#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1488 1489#define MCOUNT_NAME "_mcount" 1490 1491#define PROFILE_COUNT_REGISTER "edx" 1492 1493/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1494 the stack pointer does not matter. The value is tested only in 1495 functions that have frame pointers. 1496 No definition is equivalent to always zero. */ 1497/* Note on the 386 it might be more efficient not to define this since 1498 we have to restore it ourselves from the frame pointer, in order to 1499 use pop */ 1500 1501#define EXIT_IGNORE_STACK 1 1502 1503/* Output assembler code for a block containing the constant parts 1504 of a trampoline, leaving space for the variable parts. */ 1505 1506/* On the 386, the trampoline contains two instructions: 1507 mov #STATIC,ecx 1508 jmp FUNCTION 1509 The trampoline is generated entirely at runtime. The operand of JMP 1510 is the address of FUNCTION relative to the instruction following the 1511 JMP (which is 5 bytes long). */ 1512 1513/* Length in units of the trampoline for entering a nested function. */ 1514 1515#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1516 1517/* Emit RTL insns to initialize the variable parts of a trampoline. 1518 FNADDR is an RTX for the address of the function's pure code. 1519 CXT is an RTX for the static chain value for the function. */ 1520 1521#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1522 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1523 1524/* Definitions for register eliminations. 1525 1526 This is an array of structures. Each structure initializes one pair 1527 of eliminable registers. The "from" register number is given first, 1528 followed by "to". Eliminations of the same "from" register are listed 1529 in order of preference. 1530 1531 There are two registers that can always be eliminated on the i386. 1532 The frame pointer and the arg pointer can be replaced by either the 1533 hard frame pointer or to the stack pointer, depending upon the 1534 circumstances. The hard frame pointer is not used before reload and 1535 so it is not eligible for elimination. */ 1536 1537#define ELIMINABLE_REGS \ 1538{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1539 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1540 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1541 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1542 1543/* Given FROM and TO register numbers, say whether this elimination is 1544 allowed. Frame pointer elimination is automatically handled. 1545 1546 All other eliminations are valid. */ 1547 1548#define CAN_ELIMINATE(FROM, TO) \ 1549 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1550 1551/* Define the offset between two registers, one to be eliminated, and the other 1552 its replacement, at the start of a routine. */ 1553 1554#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1555 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1556 1557/* Addressing modes, and classification of registers for them. */ 1558 1559/* Macros to check register numbers against specific register classes. */ 1560 1561/* These assume that REGNO is a hard or pseudo reg number. 1562 They give nonzero only if REGNO is a hard reg of the suitable class 1563 or a pseudo reg currently allocated to a suitable hard reg. 1564 Since they use reg_renumber, they are safe only once reg_renumber 1565 has been allocated, which happens in local-alloc.c. */ 1566 1567#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1568 ((REGNO) < STACK_POINTER_REGNUM \ 1569 || (REGNO >= FIRST_REX_INT_REG \ 1570 && (REGNO) <= LAST_REX_INT_REG) \ 1571 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1572 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1573 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1574 1575#define REGNO_OK_FOR_BASE_P(REGNO) \ 1576 ((REGNO) <= STACK_POINTER_REGNUM \ 1577 || (REGNO) == ARG_POINTER_REGNUM \ 1578 || (REGNO) == FRAME_POINTER_REGNUM \ 1579 || (REGNO >= FIRST_REX_INT_REG \ 1580 && (REGNO) <= LAST_REX_INT_REG) \ 1581 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1582 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1583 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1584 1585#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1586 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1587#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1588 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1589 1590/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1591 and check its validity for a certain class. 1592 We have two alternate definitions for each of them. 1593 The usual definition accepts all pseudo regs; the other rejects 1594 them unless they have been allocated suitable hard regs. 1595 The symbol REG_OK_STRICT causes the latter definition to be used. 1596 1597 Most source files want to accept pseudo regs in the hope that 1598 they will get allocated to the class that the insn wants them to be in. 1599 Source files for reload pass need to be strict. 1600 After reload, it makes no difference, since pseudo regs have 1601 been eliminated by then. */ 1602 1603 1604/* Non strict versions, pseudos are ok. */ 1605#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1606 (REGNO (X) < STACK_POINTER_REGNUM \ 1607 || (REGNO (X) >= FIRST_REX_INT_REG \ 1608 && REGNO (X) <= LAST_REX_INT_REG) \ 1609 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1610 1611#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1612 (REGNO (X) <= STACK_POINTER_REGNUM \ 1613 || REGNO (X) == ARG_POINTER_REGNUM \ 1614 || REGNO (X) == FRAME_POINTER_REGNUM \ 1615 || (REGNO (X) >= FIRST_REX_INT_REG \ 1616 && REGNO (X) <= LAST_REX_INT_REG) \ 1617 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1618 1619/* Strict versions, hard registers only */ 1620#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1621#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1622 1623#ifndef REG_OK_STRICT 1624#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1625#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1626 1627#else 1628#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1629#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1630#endif 1631 1632/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1633 that is a valid memory address for an instruction. 1634 The MODE argument is the machine mode for the MEM expression 1635 that wants to use this address. 1636 1637 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 1638 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1639 1640 See legitimize_pic_address in i386.c for details as to what 1641 constitutes a legitimate address when -fpic is used. */ 1642 1643#define MAX_REGS_PER_ADDRESS 2 1644 1645#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1646 1647/* Nonzero if the constant value X is a legitimate general operand. 1648 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1649 1650#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1651 1652#ifdef REG_OK_STRICT 1653#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1654do { \ 1655 if (legitimate_address_p ((MODE), (X), 1)) \ 1656 goto ADDR; \ 1657} while (0) 1658 1659#else 1660#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1661do { \ 1662 if (legitimate_address_p ((MODE), (X), 0)) \ 1663 goto ADDR; \ 1664} while (0) 1665 1666#endif 1667 1668/* If defined, a C expression to determine the base term of address X. 1669 This macro is used in only one place: `find_base_term' in alias.c. 1670 1671 It is always safe for this macro to not be defined. It exists so 1672 that alias analysis can understand machine-dependent addresses. 1673 1674 The typical use of this macro is to handle addresses containing 1675 a label_ref or symbol_ref within an UNSPEC. */ 1676 1677#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1678 1679/* Try machine-dependent ways of modifying an illegitimate address 1680 to be legitimate. If we find one, return the new, valid address. 1681 This macro is used in only one place: `memory_address' in explow.c. 1682 1683 OLDX is the address as it was before break_out_memory_refs was called. 1684 In some cases it is useful to look at this to decide what needs to be done. 1685 1686 MODE and WIN are passed so that this macro can use 1687 GO_IF_LEGITIMATE_ADDRESS. 1688 1689 It is always safe for this macro to do nothing. It exists to recognize 1690 opportunities to optimize the output. 1691 1692 For the 80386, we handle X+REG by loading X into a register R and 1693 using R+REG. R will go in a general reg and indexing will be used. 1694 However, if REG is a broken-out memory address or multiplication, 1695 nothing needs to be done because REG can certainly go in a general reg. 1696 1697 When -fpic is used, special handling is needed for symbolic references. 1698 See comments by legitimize_pic_address in i386.c for details. */ 1699 1700#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1701do { \ 1702 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 1703 if (memory_address_p ((MODE), (X))) \ 1704 goto WIN; \ 1705} while (0) 1706 1707#define REWRITE_ADDRESS(X) rewrite_address (X) 1708 1709/* Nonzero if the constant value X is a legitimate general operand 1710 when generating PIC code. It is given that flag_pic is on and 1711 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1712 1713#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1714 1715#define SYMBOLIC_CONST(X) \ 1716 (GET_CODE (X) == SYMBOL_REF \ 1717 || GET_CODE (X) == LABEL_REF \ 1718 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1719 1720/* Go to LABEL if ADDR (a legitimate address expression) 1721 has an effect that depends on the machine mode it is used for. 1722 On the 80386, only postdecrement and postincrement address depend thus 1723 (the amount of decrement or increment being the length of the operand). */ 1724#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1725do { \ 1726 if (GET_CODE (ADDR) == POST_INC \ 1727 || GET_CODE (ADDR) == POST_DEC) \ 1728 goto LABEL; \ 1729} while (0) 1730 1731/* Max number of args passed in registers. If this is more than 3, we will 1732 have problems with ebx (register #4), since it is a caller save register and 1733 is also used as the pic register in ELF. So for now, don't allow more than 1734 3 registers to be passed in registers. */ 1735 1736#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 1737 1738#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) 1739 1740#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1741 1742 1743/* Specify the machine mode that this machine uses 1744 for the index in the tablejump instruction. */ 1745#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 1746 1747/* Define this as 1 if `char' should by default be signed; else as 0. */ 1748#define DEFAULT_SIGNED_CHAR 1 1749 1750/* Number of bytes moved into a data cache for a single prefetch operation. */ 1751#define PREFETCH_BLOCK ix86_cost->prefetch_block 1752 1753/* Number of prefetch operations that can be done in parallel. */ 1754#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 1755 1756/* Max number of bytes we can move from memory to memory 1757 in one reasonably fast instruction. */ 1758#define MOVE_MAX 16 1759 1760/* MOVE_MAX_PIECES is the number of bytes at a time which we can 1761 move efficiently, as opposed to MOVE_MAX which is the maximum 1762 number of bytes we can move with a single instruction. */ 1763#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 1764 1765/* If a memory-to-memory move would take MOVE_RATIO or more simple 1766 move-instruction pairs, we will do a movmem or libcall instead. 1767 Increasing the value will always make code faster, but eventually 1768 incurs high cost in increased code size. 1769 1770 If you don't define this, a reasonable default is used. */ 1771 1772#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 1773 1774/* If a clear memory operation would take CLEAR_RATIO or more simple 1775 move-instruction sequences, we will do a clrmem or libcall instead. */ 1776 1777#define CLEAR_RATIO (optimize_size ? 2 \ 1778 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio) 1779 1780/* Define if shifts truncate the shift count 1781 which implies one can omit a sign-extension or zero-extension 1782 of a shift count. */ 1783/* On i386, shifts do truncate the count. But bit opcodes don't. */ 1784 1785/* #define SHIFT_COUNT_TRUNCATED */ 1786 1787/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1788 is done just by pretending it is already truncated. */ 1789#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1790 1791/* A macro to update M and UNSIGNEDP when an object whose type is 1792 TYPE and which has the specified mode and signedness is to be 1793 stored in a register. This macro is only called when TYPE is a 1794 scalar type. 1795 1796 On i386 it is sometimes useful to promote HImode and QImode 1797 quantities to SImode. The choice depends on target type. */ 1798 1799#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1800do { \ 1801 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1802 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1803 (MODE) = SImode; \ 1804} while (0) 1805 1806/* Specify the machine mode that pointers have. 1807 After generation of rtl, the compiler makes no further distinction 1808 between pointers and any other objects of this machine mode. */ 1809#define Pmode (TARGET_64BIT ? DImode : SImode) 1810 1811/* A function address in a call instruction 1812 is a byte address (for indexing purposes) 1813 so give the MEM rtx a byte's mode. */ 1814#define FUNCTION_MODE QImode 1815 1816/* A C expression for the cost of moving data from a register in class FROM to 1817 one in class TO. The classes are expressed using the enumeration values 1818 such as `GENERAL_REGS'. A value of 2 is the default; other values are 1819 interpreted relative to that. 1820 1821 It is not required that the cost always equal 2 when FROM is the same as TO; 1822 on some machines it is expensive to move between registers if they are not 1823 general registers. */ 1824 1825#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1826 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1827 1828/* A C expression for the cost of moving data of mode M between a 1829 register and memory. A value of 2 is the default; this cost is 1830 relative to those in `REGISTER_MOVE_COST'. 1831 1832 If moving between registers and memory is more expensive than 1833 between two registers, you should define this macro to express the 1834 relative cost. */ 1835 1836#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1837 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 1838 1839/* A C expression for the cost of a branch instruction. A value of 1 1840 is the default; other values are interpreted relative to that. */ 1841 1842#define BRANCH_COST ix86_branch_cost 1843 1844/* Define this macro as a C expression which is nonzero if accessing 1845 less than a word of memory (i.e. a `char' or a `short') is no 1846 faster than accessing a word of memory, i.e., if such access 1847 require more than one instruction or if there is no difference in 1848 cost between byte and (aligned) word loads. 1849 1850 When this macro is not defined, the compiler will access a field by 1851 finding the smallest containing object; when it is defined, a 1852 fullword load will be used if alignment permits. Unless bytes 1853 accesses are faster than word accesses, using word accesses is 1854 preferable since it may eliminate subsequent memory access if 1855 subsequent accesses occur to other fields in the same word of the 1856 structure, but to different bytes. */ 1857 1858#define SLOW_BYTE_ACCESS 0 1859 1860/* Nonzero if access to memory by shorts is slow and undesirable. */ 1861#define SLOW_SHORT_ACCESS 0 1862 1863/* Define this macro to be the value 1 if unaligned accesses have a 1864 cost many times greater than aligned accesses, for example if they 1865 are emulated in a trap handler. 1866 1867 When this macro is nonzero, the compiler will act as if 1868 `STRICT_ALIGNMENT' were nonzero when generating code for block 1869 moves. This can cause significantly more instructions to be 1870 produced. Therefore, do not set this macro nonzero if unaligned 1871 accesses only add a cycle or two to the time for a memory access. 1872 1873 If the value of this macro is always zero, it need not be defined. */ 1874 1875/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1876 1877/* Define this macro if it is as good or better to call a constant 1878 function address than to call an address kept in a register. 1879 1880 Desirable on the 386 because a CALL with a constant address is 1881 faster than one with a register address. */ 1882 1883#define NO_FUNCTION_CSE 1884 1885/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1886 return the mode to be used for the comparison. 1887 1888 For floating-point equality comparisons, CCFPEQmode should be used. 1889 VOIDmode should be used in all other cases. 1890 1891 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1892 possible, to allow for more combinations. */ 1893 1894#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1895 1896/* Return nonzero if MODE implies a floating point inequality can be 1897 reversed. */ 1898 1899#define REVERSIBLE_CC_MODE(MODE) 1 1900 1901/* A C expression whose value is reversed condition code of the CODE for 1902 comparison done in CC_MODE mode. */ 1903#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 1904 1905 1906/* Control the assembler format that we output, to the extent 1907 this does not vary between assemblers. */ 1908 1909/* How to refer to registers in assembler output. 1910 This sequence is indexed by compiler's hard-register-number (see above). */ 1911 1912/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e". 1913 For non floating point regs, the following are the HImode names. 1914 1915 For float regs, the stack top is sometimes referred to as "%st(0)" 1916 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ 1917 1918#define HI_REGISTER_NAMES \ 1919{"ax","dx","cx","bx","si","di","bp","sp", \ 1920 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 1921 "argp", "flags", "fpsr", "dirflag", "frame", \ 1922 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 1923 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 1924 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1925 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 1926 1927#define REGISTER_NAMES HI_REGISTER_NAMES 1928 1929/* Table of additional register names to use in user input. */ 1930 1931#define ADDITIONAL_REGISTER_NAMES \ 1932{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 1933 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 1934 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 1935 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 1936 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 1937 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 1938 1939/* Note we are omitting these since currently I don't know how 1940to get gcc to use these, since they want the same but different 1941number as al, and ax. 1942*/ 1943 1944#define QI_REGISTER_NAMES \ 1945{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 1946 1947/* These parallel the array above, and can be used to access bits 8:15 1948 of regs 0 through 3. */ 1949 1950#define QI_HIGH_REGISTER_NAMES \ 1951{"ah", "dh", "ch", "bh", } 1952 1953/* How to renumber registers for dbx and gdb. */ 1954 1955#define DBX_REGISTER_NUMBER(N) \ 1956 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 1957 1958extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 1959extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 1960extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 1961 1962/* Before the prologue, RA is at 0(%esp). */ 1963#define INCOMING_RETURN_ADDR_RTX \ 1964 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 1965 1966/* After the prologue, RA is at -4(AP) in the current frame. */ 1967#define RETURN_ADDR_RTX(COUNT, FRAME) \ 1968 ((COUNT) == 0 \ 1969 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 1970 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 1971 1972/* PC is dbx register 8; let's use that column for RA. */ 1973#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 1974 1975/* Before the prologue, the top of the frame is at 4(%esp). */ 1976#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 1977 1978/* Describe how we implement __builtin_eh_return. */ 1979#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 1980#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 1981 1982 1983/* Select a format to encode pointers in exception handling data. CODE 1984 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1985 true if the symbol may be affected by dynamic relocations. 1986 1987 ??? All x86 object file formats are capable of representing this. 1988 After all, the relocation needed is the same as for the call insn. 1989 Whether or not a particular assembler allows us to enter such, I 1990 guess we'll have to see. */ 1991#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1992 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 1993 1994/* This is how to output an insn to push a register on the stack. 1995 It need not be very fast code. */ 1996 1997#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 1998do { \ 1999 if (TARGET_64BIT) \ 2000 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2001 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2002 else \ 2003 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2004} while (0) 2005 2006/* This is how to output an insn to pop a register from the stack. 2007 It need not be very fast code. */ 2008 2009#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2010do { \ 2011 if (TARGET_64BIT) \ 2012 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2013 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2014 else \ 2015 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2016} while (0) 2017 2018/* This is how to output an element of a case-vector that is absolute. */ 2019 2020#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2021 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2022 2023/* This is how to output an element of a case-vector that is relative. */ 2024 2025#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2026 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2027 2028/* Under some conditions we need jump tables in the text section, 2029 because the assembler cannot handle label differences between 2030 sections. This is the case for x86_64 on Mach-O for example. */ 2031 2032#define JUMP_TABLES_IN_TEXT_SECTION \ 2033 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2034 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2035 2036/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2037 and switch back. For x86 we do this only to save a few bytes that 2038 would otherwise be unused in the text section. */ 2039#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2040 asm (SECTION_OP "\n\t" \ 2041 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2042 TEXT_SECTION_ASM_OP); 2043 2044/* Print operand X (an rtx) in assembler syntax to file FILE. 2045 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2046 Effect of various CODE letters is described in i386.c near 2047 print_operand function. */ 2048 2049#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2050 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') 2051 2052#define PRINT_OPERAND(FILE, X, CODE) \ 2053 print_operand ((FILE), (X), (CODE)) 2054 2055#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2056 print_operand_address ((FILE), (ADDR)) 2057 2058#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2059do { \ 2060 if (! output_addr_const_extra (FILE, (X))) \ 2061 goto FAIL; \ 2062} while (0); 2063 2064/* a letter which is not needed by the normal asm syntax, which 2065 we can use for operand syntax in the extended asm */ 2066 2067#define ASM_OPERAND_LETTER '#' 2068#define RET return "" 2069#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 2070 2071/* Which processor to schedule for. The cpu attribute defines a list that 2072 mirrors this list, so changes to i386.md must be made at the same time. */ 2073 2074enum processor_type 2075{ 2076 PROCESSOR_I386, /* 80386 */ 2077 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2078 PROCESSOR_PENTIUM, 2079 PROCESSOR_PENTIUMPRO, 2080 PROCESSOR_K6, 2081 PROCESSOR_ATHLON, 2082 PROCESSOR_PENTIUM4, 2083 PROCESSOR_K8, 2084 PROCESSOR_NOCONA, 2085 PROCESSOR_GENERIC32, 2086 PROCESSOR_GENERIC64, 2087 PROCESSOR_max 2088}; 2089 2090extern enum processor_type ix86_tune; 2091extern enum processor_type ix86_arch; 2092 2093enum fpmath_unit 2094{ 2095 FPMATH_387 = 1, 2096 FPMATH_SSE = 2 2097}; 2098 2099extern enum fpmath_unit ix86_fpmath; 2100 2101enum tls_dialect 2102{ 2103 TLS_DIALECT_GNU, 2104 TLS_DIALECT_GNU2, 2105 TLS_DIALECT_SUN 2106}; 2107 2108extern enum tls_dialect ix86_tls_dialect; 2109 2110enum cmodel { 2111 CM_32, /* The traditional 32-bit ABI. */ 2112 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 2113 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 2114 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 2115 CM_LARGE, /* No assumptions. */ 2116 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ 2117 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */ 2118}; 2119 2120extern enum cmodel ix86_cmodel; 2121 2122/* Size of the RED_ZONE area. */ 2123#define RED_ZONE_SIZE 128 2124/* Reserved area of the red zone for temporaries. */ 2125#define RED_ZONE_RESERVE 8 2126 2127enum asm_dialect { 2128 ASM_ATT, 2129 ASM_INTEL 2130}; 2131 2132extern enum asm_dialect ix86_asm_dialect; 2133extern unsigned int ix86_preferred_stack_boundary; 2134extern int ix86_branch_cost, ix86_section_threshold; 2135 2136/* Smallest class containing REGNO. */ 2137extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2138 2139extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 2140extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 2141extern rtx ix86_compare_emitted; 2142 2143/* To properly truncate FP values into integers, we need to set i387 control 2144 word. We can't emit proper mode switching code before reload, as spills 2145 generated by reload may truncate values incorrectly, but we still can avoid 2146 redundant computation of new control word by the mode switching pass. 2147 The fldcw instructions are still emitted redundantly, but this is probably 2148 not going to be noticeable problem, as most CPUs do have fast path for 2149 the sequence. 2150 2151 The machinery is to emit simple truncation instructions and split them 2152 before reload to instructions having USEs of two memory locations that 2153 are filled by this code to old and new control word. 2154 2155 Post-reload pass may be later used to eliminate the redundant fildcw if 2156 needed. */ 2157 2158enum ix86_entity 2159{ 2160 I387_TRUNC = 0, 2161 I387_FLOOR, 2162 I387_CEIL, 2163 I387_MASK_PM, 2164 MAX_386_ENTITIES 2165}; 2166 2167enum ix86_stack_slot 2168{ 2169 SLOT_VIRTUAL = 0, 2170 SLOT_TEMP, 2171 SLOT_CW_STORED, 2172 SLOT_CW_TRUNC, 2173 SLOT_CW_FLOOR, 2174 SLOT_CW_CEIL, 2175 SLOT_CW_MASK_PM, 2176 MAX_386_STACK_LOCALS 2177}; 2178 2179/* Define this macro if the port needs extra instructions inserted 2180 for mode switching in an optimizing compilation. */ 2181 2182#define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2183 ix86_optimize_mode_switching[(ENTITY)] 2184 2185/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2186 initializer for an array of integers. Each initializer element N 2187 refers to an entity that needs mode switching, and specifies the 2188 number of different modes that might need to be set for this 2189 entity. The position of the initializer in the initializer - 2190 starting counting at zero - determines the integer that is used to 2191 refer to the mode-switched entity in question. */ 2192 2193#define NUM_MODES_FOR_MODE_SWITCHING \ 2194 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2195 2196/* ENTITY is an integer specifying a mode-switched entity. If 2197 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2198 return an integer value not larger than the corresponding element 2199 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2200 must be switched into prior to the execution of INSN. */ 2201 2202#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2203 2204/* This macro specifies the order in which modes for ENTITY are 2205 processed. 0 is the highest priority. */ 2206 2207#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2208 2209/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2210 is the set of hard registers live at the point where the insn(s) 2211 are to be inserted. */ 2212 2213#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2214 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ 2215 ? emit_i387_cw_initialization (MODE), 0 \ 2216 : 0) 2217 2218 2219/* Avoid renaming of stack registers, as doing so in combination with 2220 scheduling just increases amount of live registers at time and in 2221 the turn amount of fxch instructions needed. 2222 2223 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2224 2225#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2226 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 2227 2228 2229#define DLL_IMPORT_EXPORT_PREFIX '#' 2230 2231#define FASTCALL_PREFIX '@' 2232 2233struct machine_function GTY(()) 2234{ 2235 struct stack_local_entry *stack_locals; 2236 const char *some_ld_name; 2237 rtx force_align_arg_pointer; 2238 int save_varrargs_registers; 2239 int accesses_prev_frame; 2240 int optimize_mode_switching[MAX_386_ENTITIES]; 2241 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to 2242 determine the style used. */ 2243 int use_fast_prologue_epilogue; 2244 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed 2245 for. */ 2246 int use_fast_prologue_epilogue_nregs; 2247 /* If true, the current function needs the default PIC register, not 2248 an alternate register (on x86) and must not use the red zone (on 2249 x86_64), even if it's a leaf function. We don't want the 2250 function to be regarded as non-leaf because TLS calls need not 2251 affect register allocation. This flag is set when a TLS call 2252 instruction is expanded within a function, and never reset, even 2253 if all such instructions are optimized away. Use the 2254 ix86_current_function_calls_tls_descriptor macro for a better 2255 approximation. */ 2256 int tls_descriptor_call_expanded_p; 2257}; 2258 2259#define ix86_stack_locals (cfun->machine->stack_locals) 2260#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) 2261#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2262#define ix86_tls_descriptor_calls_expanded_in_cfun \ 2263 (cfun->machine->tls_descriptor_call_expanded_p) 2264/* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2265 calls are optimized away, we try to detect cases in which it was 2266 optimized away. Since such instructions (use (reg REG_SP)), we can 2267 verify whether there's any such instruction live by testing that 2268 REG_SP is live. */ 2269#define ix86_current_function_calls_tls_descriptor \ 2270 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG]) 2271 2272/* Control behavior of x86_file_start. */ 2273#define X86_FILE_START_VERSION_DIRECTIVE false 2274#define X86_FILE_START_FLTUSED false 2275 2276/* Flag to mark data that is in the large address area. */ 2277#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2278#define SYMBOL_REF_FAR_ADDR_P(X) \ 2279 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2280/* 2281Local variables: 2282version-control: t 2283End: 2284*/ 2285