i386.h revision 148163
1204076Spjd/* Definitions of target machine for GCC for IA-32. 2204076Spjd Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3204076Spjd 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4204076Spjd 5204076SpjdThis file is part of GCC. 6204076Spjd 7204076SpjdGCC is free software; you can redistribute it and/or modify 8204076Spjdit under the terms of the GNU General Public License as published by 9204076Spjdthe Free Software Foundation; either version 2, or (at your option) 10204076Spjdany later version. 11204076Spjd 12204076SpjdGCC is distributed in the hope that it will be useful, 13204076Spjdbut WITHOUT ANY WARRANTY; without even the implied warranty of 14204076SpjdMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15204076SpjdGNU General Public License for more details. 16204076Spjd 17204076SpjdYou should have received a copy of the GNU General Public License 18204076Spjdalong with GCC; see the file COPYING. If not, write to 19204076Spjdthe Free Software Foundation, 59 Temple Place - Suite 330, 20204076SpjdBoston, MA 02111-1307, USA. */ 21204076Spjd 22204076Spjd/* The purpose of this file is to define the characteristics of the i386, 23204076Spjd independent of assembler syntax or operating system. 24204076Spjd 25204076Spjd Three other files build on this one to describe a specific assembler syntax: 26204076Spjd bsd386.h, att386.h, and sun386.h. 27204076Spjd 28204076Spjd The actual tm.h file for a particular system should include 29204076Spjd this file, and then the file for the appropriate assembler syntax. 30204076Spjd 31204076Spjd Many macros that specify assembler syntax are omitted entirely from 32204076Spjd this file because they really belong in the files for particular 33204076Spjd assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34204076Spjd ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35204076Spjd that start with ASM_ or end in ASM_OP. */ 36204076Spjd 37204076Spjd/* Define the specific costs for a given cpu */ 38204076Spjd 39204076Spjdstruct processor_costs { 40204076Spjd const int add; /* cost of an add instruction */ 41204076Spjd const int lea; /* cost of a lea instruction */ 42204076Spjd const int shift_var; /* variable shift costs */ 43218138Spjd const int shift_const; /* constant shift costs */ 44204076Spjd const int mult_init[5]; /* cost of starting a multiply 45204076Spjd in QImode, HImode, SImode, DImode, TImode*/ 46204076Spjd const int mult_bit; /* cost of multiply per each bit set */ 47204076Spjd const int divide[5]; /* cost of a divide/mod 48204076Spjd in QImode, HImode, SImode, DImode, TImode*/ 49204076Spjd int movsx; /* The cost of movsx operation. */ 50204076Spjd int movzx; /* The cost of movzx operation. */ 51204076Spjd const int large_insn; /* insns larger than this cost more */ 52204076Spjd const int move_ratio; /* The threshold of number of scalar 53204076Spjd memory-to-memory move insns. */ 54204076Spjd const int movzbl_load; /* cost of loading using movzbl */ 55204076Spjd const int int_load[3]; /* cost of loading integer registers 56204076Spjd in QImode, HImode and SImode relative 57204076Spjd to reg-reg move (2). */ 58204076Spjd const int int_store[3]; /* cost of storing integer register 59219818Spjd in QImode, HImode and SImode */ 60204076Spjd const int fp_move; /* cost of reg,reg fld/fst */ 61204076Spjd const int fp_load[3]; /* cost of loading FP register 62204076Spjd in SFmode, DFmode and XFmode */ 63204076Spjd const int fp_store[3]; /* cost of storing FP register 64219818Spjd in SFmode, DFmode and XFmode */ 65204076Spjd const int mmx_move; /* cost of moving MMX register. */ 66204076Spjd const int mmx_load[2]; /* cost of loading MMX register 67219818Spjd in SImode and DImode */ 68219818Spjd const int mmx_store[2]; /* cost of storing MMX register 69204076Spjd in SImode and DImode */ 70204076Spjd const int sse_move; /* cost of moving SSE register. */ 71204076Spjd const int sse_load[3]; /* cost of loading SSE register 72204076Spjd in SImode, DImode and TImode*/ 73231017Strociny const int sse_store[3]; /* cost of storing SSE register 74204076Spjd in SImode, DImode and TImode*/ 75204076Spjd const int mmxsse_to_integer; /* cost of moving mmxsse register to 76204076Spjd integer and vice versa. */ 77204076Spjd const int prefetch_block; /* bytes moved to cache for prefetch. */ 78204076Spjd const int simultaneous_prefetches; /* number of parallel prefetch 79204076Spjd operations. */ 80204076Spjd const int branch_cost; /* Default value for BRANCH_COST. */ 81204076Spjd const int fadd; /* cost of FADD and FSUB instructions. */ 82204076Spjd const int fmul; /* cost of FMUL instruction. */ 83204076Spjd const int fdiv; /* cost of FDIV instruction. */ 84204076Spjd const int fabs; /* cost of FABS instruction. */ 85204076Spjd const int fchs; /* cost of FCHS instruction. */ 86204076Spjd const int fsqrt; /* cost of FSQRT instruction. */ 87218194Spjd}; 88204076Spjd 89204076Spjdextern const struct processor_costs *ix86_cost; 90218194Spjd 91204076Spjd/* Run-time compilation parameters selecting different hardware subsets. */ 92218138Spjd 93218138Spjdextern int target_flags; 94204076Spjd 95204076Spjd/* Macros used in the machine description to test the flags. */ 96204076Spjd 97204076Spjd/* configure can arrange to make this 2, to force a 486. */ 98204076Spjd 99218194Spjd#ifndef TARGET_CPU_DEFAULT 100204076Spjd#ifdef TARGET_64BIT_DEFAULT 101204076Spjd#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8 102204076Spjd#else 103204076Spjd#define TARGET_CPU_DEFAULT 0 104204076Spjd#endif 105218138Spjd#endif 106204076Spjd 107218138Spjd/* Masks for the -m switches */ 108218194Spjd#define MASK_80387 0x00000001 /* Hardware floating point */ 109204076Spjd#define MASK_RTD 0x00000002 /* Use ret that pops args */ 110204076Spjd#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ 111218138Spjd#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ 112218194Spjd#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ 113204076Spjd#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ 114204076Spjd#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ 115218138Spjd#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ 116204076Spjd#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ 117204076Spjd#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ 118212036Spjd#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ 119212036Spjd#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ 120212036Spjd#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ 121212036Spjd#define MASK_MMX 0x00002000 /* Support MMX regs/builtins */ 122218194Spjd#define MASK_SSE 0x00004000 /* Support SSE regs/builtins */ 123204076Spjd#define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */ 124204076Spjd#define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */ 125204076Spjd#define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */ 126218194Spjd#define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */ 127204076Spjd#define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */ 128204076Spjd#define MASK_64BIT 0x00100000 /* Produce 64bit code */ 129204076Spjd#define MASK_MS_BITFIELD_LAYOUT 0x00200000 /* Use native (MS) bitfield layout */ 130204076Spjd#define MASK_TLS_DIRECT_SEG_REFS 0x00400000 /* Avoid adding %gs:0 */ 131218138Spjd 132218138Spjd/* Unused: 0x03e0000 */ 133204076Spjd 134204076Spjd/* ... overlap with subtarget options starts by 0x04000000. */ 135204076Spjd#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ 136204076Spjd#define MASK_NO_ALIGN_LONG_STRINGS 0x08000000 /* Do not align long strings specially */ 137204076Spjd 138218194Spjd/* Use the floating point instructions */ 139204076Spjd#define TARGET_80387 (target_flags & MASK_80387) 140204076Spjd 141204076Spjd/* Compile using ret insn that pops args. 142204076Spjd This will not work unless you use prototypes at least 143204076Spjd for all functions that can take varying numbers of args. */ 144218138Spjd#define TARGET_RTD (target_flags & MASK_RTD) 145204076Spjd 146218138Spjd/* Align doubles to a two word boundary. This breaks compatibility with 147204076Spjd the published ABI's for structures containing doubles, but produces 148204076Spjd faster code on the pentium. */ 149204076Spjd#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) 150218138Spjd 151204076Spjd/* Use push instructions to save outgoing args. */ 152204076Spjd#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) 153204076Spjd 154218138Spjd/* Accumulate stack adjustments to prologue/epilogue. */ 155204076Spjd#define TARGET_ACCUMULATE_OUTGOING_ARGS \ 156204076Spjd (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) 157212036Spjd 158212036Spjd/* Put uninitialized locals into bss, not data. 159212036Spjd Meaningful only on svr3. */ 160212036Spjd#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) 161218194Spjd 162204076Spjd/* Use IEEE floating point comparisons. These handle correctly the cases 163204076Spjd where the result of a comparison is unordered. Normally SIGFPE is 164204076Spjd generated in such cases, in which case this isn't needed. */ 165204076Spjd#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) 166204076Spjd 167204076Spjd/* Functions that return a floating point value may return that value 168204076Spjd in the 387 FPU or in 386 integer registers. If set, this flag causes 169218138Spjd the 387 to be used, which is compatible with most calling conventions. */ 170218138Spjd#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) 171218138Spjd 172204076Spjd/* Long double is 128bit instead of 96bit, even when only 80bits are used. 173204076Spjd This mode wastes cache, but avoid misaligned data accesses and simplifies 174204076Spjd address calculations. */ 175204076Spjd#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) 176218138Spjd 177204076Spjd/* Disable generation of FP sin, cos and sqrt operations for 387. 178204076Spjd This is because FreeBSD lacks these in the math-emulator-code */ 179218138Spjd#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) 180204076Spjd 181204076Spjd/* Don't create frame pointers for leaf functions */ 182204076Spjd#define TARGET_OMIT_LEAF_FRAME_POINTER \ 183218138Spjd (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) 184204076Spjd 185204076Spjd/* Debug GO_IF_LEGITIMATE_ADDRESS */ 186204076Spjd#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) 187204076Spjd 188204076Spjd/* Debug FUNCTION_ARG macros */ 189204076Spjd#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) 190204076Spjd 191218138Spjd/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 192218138Spjd compile-time constant. */ 193204076Spjd#ifdef IN_LIBGCC2 194204076Spjd#ifdef __x86_64__ 195204076Spjd#define TARGET_64BIT 1 196218138Spjd#else 197204076Spjd#define TARGET_64BIT 0 198218138Spjd#endif 199218138Spjd#else 200204076Spjd#ifdef TARGET_BI_ARCH 201218138Spjd#define TARGET_64BIT (target_flags & MASK_64BIT) 202204076Spjd#else 203204076Spjd#if TARGET_64BIT_DEFAULT 204218138Spjd#define TARGET_64BIT 1 205204076Spjd#else 206218138Spjd#define TARGET_64BIT 0 207218138Spjd#endif 208204076Spjd#endif 209204076Spjd#endif 210218138Spjd 211204076Spjd/* Avoid adding %gs:0 in TLS references; use %gs:address directly. */ 212218138Spjd#define TARGET_TLS_DIRECT_SEG_REFS (target_flags & MASK_TLS_DIRECT_SEG_REFS) 213218138Spjd 214204076Spjd#define TARGET_386 (ix86_tune == PROCESSOR_I386) 215204076Spjd#define TARGET_486 (ix86_tune == PROCESSOR_I486) 216218138Spjd#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 217204076Spjd#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 218204076Spjd#define TARGET_K6 (ix86_tune == PROCESSOR_K6) 219204076Spjd#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 220204076Spjd#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 221204076Spjd#define TARGET_K8 (ix86_tune == PROCESSOR_K8) 222204076Spjd#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 223219873Spjd 224219873Spjd#define TUNEMASK (1 << ix86_tune) 225219873Spjdextern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 226219873Spjdextern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 227219873Spjdextern const int x86_branch_hints, x86_unroll_strlen; 228219873Spjdextern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 229219873Spjdextern const int x86_use_loop, x86_use_fiop, x86_use_mov0; 230204076Spjdextern const int x86_use_cltd, x86_read_modify_write; 231204076Spjdextern const int x86_read_modify, x86_split_long_moves; 232204076Spjdextern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; 233204076Spjdextern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 234204076Spjdextern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 235204076Spjdextern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 236210869Spjdextern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 237204076Spjdextern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 238extern const int x86_epilogue_using_move, x86_decompose_lea; 239extern const int x86_arch_always_fancy_math_387, x86_shift1; 240extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs; 241extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; 242extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss; 243extern const int x86_inter_unit_moves; 244extern int x86_prefetch_sse; 245 246#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) 247#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) 248#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK) 249#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK) 250#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK) 251/* For sane SSE instruction set generation we need fcomi instruction. It is 252 safe to enable all CMOVE instructions. */ 253#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 254#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK) 255#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK) 256#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK) 257#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) 258#define TARGET_MOVX (x86_movx & TUNEMASK) 259#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) 260#define TARGET_USE_LOOP (x86_use_loop & TUNEMASK) 261#define TARGET_USE_FIOP (x86_use_fiop & TUNEMASK) 262#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) 263#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK) 264#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK) 265#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK) 266#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK) 267#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK) 268#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK) 269#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK) 270#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK) 271#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK) 272#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK) 273#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK) 274#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK) 275#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK) 276#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK) 277#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK) 278#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK) 279#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) 280#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 281 (x86_sse_partial_reg_dependency & TUNEMASK) 282#define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & TUNEMASK) 283#define TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS \ 284 (x86_sse_partial_regs_for_cvtsd2ss & TUNEMASK) 285#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) 286#define TARGET_SSE_TYPELESS_LOAD0 (x86_sse_typeless_load0 & TUNEMASK) 287#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) 288#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) 289#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK) 290#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK) 291#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK) 292#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 293#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK) 294#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK) 295#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK) 296#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK) 297 298#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) 299 300#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) 301#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) 302 303#define ASSEMBLER_DIALECT (ix86_asm_dialect) 304 305#define TARGET_SSE ((target_flags & MASK_SSE) != 0) 306#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) 307#define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0) 308#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 309#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 310 && (ix86_fpmath & FPMATH_387)) 311#define TARGET_MMX ((target_flags & MASK_MMX) != 0) 312#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) 313#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) 314 315#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) 316 317#define TARGET_NO_ALIGN_LONG_STRINGS (target_flags & MASK_NO_ALIGN_LONG_STRINGS) 318 319#define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT) 320 321#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 322#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) 323 324/* WARNING: Do not mark empty strings for translation, as calling 325 gettext on an empty string does NOT return an empty 326 string. */ 327 328 329#define TARGET_SWITCHES \ 330{ { "80387", MASK_80387, N_("Use hardware fp") }, \ 331 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ 332 { "hard-float", MASK_80387, N_("Use hardware fp") }, \ 333 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ 334 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ 335 { "386", 0, "" /*Deprecated.*/}, \ 336 { "486", 0, "" /*Deprecated.*/}, \ 337 { "pentium", 0, "" /*Deprecated.*/}, \ 338 { "pentiumpro", 0, "" /*Deprecated.*/}, \ 339 { "pni", 0, "" /*Deprecated.*/}, \ 340 { "no-pni", 0, "" /*Deprecated.*/}, \ 341 { "intel-syntax", 0, "" /*Deprecated.*/}, \ 342 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ 343 { "rtd", MASK_RTD, \ 344 N_("Alternate calling convention") }, \ 345 { "no-rtd", -MASK_RTD, \ 346 N_("Use normal calling convention") }, \ 347 { "align-double", MASK_ALIGN_DOUBLE, \ 348 N_("Align some doubles on dword boundary") }, \ 349 { "no-align-double", -MASK_ALIGN_DOUBLE, \ 350 N_("Align doubles on word boundary") }, \ 351 { "svr3-shlib", MASK_SVR3_SHLIB, \ 352 N_("Uninitialized locals in .bss") }, \ 353 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ 354 N_("Uninitialized locals in .data") }, \ 355 { "ieee-fp", MASK_IEEE_FP, \ 356 N_("Use IEEE math for fp comparisons") }, \ 357 { "no-ieee-fp", -MASK_IEEE_FP, \ 358 N_("Do not use IEEE math for fp comparisons") }, \ 359 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ 360 N_("Return values of functions in FPU registers") }, \ 361 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ 362 N_("Do not return values of functions in FPU registers")}, \ 363 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ 364 N_("Do not generate sin, cos, sqrt for FPU") }, \ 365 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ 366 N_("Generate sin, cos, sqrt for FPU")}, \ 367 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ 368 N_("Omit the frame pointer in leaf functions") }, \ 369 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ 370 { "stack-arg-probe", MASK_STACK_PROBE, \ 371 N_("Enable stack probing") }, \ 372 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ 373 { "windows", 0, 0 /* undocumented */ }, \ 374 { "dll", 0, 0 /* undocumented */ }, \ 375 { "align-stringops", -MASK_NO_ALIGN_STROPS, \ 376 N_("Align destination of the string operations") }, \ 377 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ 378 N_("Do not align destination of the string operations") }, \ 379 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ 380 N_("Inline all known string operations") }, \ 381 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ 382 N_("Do not inline all known string operations") }, \ 383 { "push-args", -MASK_NO_PUSH_ARGS, \ 384 N_("Use push instructions to save outgoing arguments") }, \ 385 { "no-push-args", MASK_NO_PUSH_ARGS, \ 386 N_("Do not use push instructions to save outgoing arguments") }, \ 387 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \ 388 N_("Use push instructions to save outgoing arguments") }, \ 389 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \ 390 N_("Do not use push instructions to save outgoing arguments") }, \ 391 { "mmx", MASK_MMX, \ 392 N_("Support MMX built-in functions") }, \ 393 { "no-mmx", -MASK_MMX, \ 394 N_("Do not support MMX built-in functions") }, \ 395 { "3dnow", MASK_3DNOW, \ 396 N_("Support 3DNow! built-in functions") }, \ 397 { "no-3dnow", -MASK_3DNOW, \ 398 N_("Do not support 3DNow! built-in functions") }, \ 399 { "sse", MASK_SSE, \ 400 N_("Support MMX and SSE built-in functions and code generation") }, \ 401 { "no-sse", -MASK_SSE, \ 402 N_("Do not support MMX and SSE built-in functions and code generation") },\ 403 { "sse2", MASK_SSE2, \ 404 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ 405 { "no-sse2", -MASK_SSE2, \ 406 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ 407 { "sse3", MASK_SSE3, \ 408 N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\ 409 { "no-sse3", -MASK_SSE3, \ 410 N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\ 411 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ 412 N_("sizeof(long double) is 16") }, \ 413 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ 414 N_("sizeof(long double) is 12") }, \ 415 { "64", MASK_64BIT, \ 416 N_("Generate 64bit x86-64 code") }, \ 417 { "32", -MASK_64BIT, \ 418 N_("Generate 32bit i386 code") }, \ 419 { "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \ 420 N_("Use native (MS) bitfield layout") }, \ 421 { "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \ 422 N_("Use gcc default bitfield layout") }, \ 423 { "red-zone", -MASK_NO_RED_ZONE, \ 424 N_("Use red-zone in the x86-64 code") }, \ 425 { "no-red-zone", MASK_NO_RED_ZONE, \ 426 N_("Do not use red-zone in the x86-64 code") }, \ 427 { "no-align-long-strings", MASK_NO_ALIGN_LONG_STRINGS, \ 428 N_("Do not align long strings specially") }, \ 429 { "align-long-strings", -MASK_NO_ALIGN_LONG_STRINGS, \ 430 N_("Align strings longer than 30 on a 32-byte boundary") }, \ 431 { "tls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS, \ 432 N_("Use direct references against %gs when accessing tls data") }, \ 433 { "no-tls-direct-seg-refs", -MASK_TLS_DIRECT_SEG_REFS, \ 434 N_("Do not use direct references against %gs when accessing tls data") }, \ 435 SUBTARGET_SWITCHES \ 436 { "", \ 437 TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT \ 438 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT, 0 }} 439 440#ifndef TARGET_64BIT_DEFAULT 441#define TARGET_64BIT_DEFAULT 0 442#endif 443#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 444#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 445#endif 446 447/* Once GDB has been enhanced to deal with functions without frame 448 pointers, we can change this to allow for elimination of 449 the frame pointer in leaf functions. */ 450#define TARGET_DEFAULT 0 451 452/* This is not really a target flag, but is done this way so that 453 it's analogous to similar code for Mach-O on PowerPC. darwin.h 454 redefines this to 1. */ 455#define TARGET_MACHO 0 456 457/* Subtargets may reset this to 1 in order to enable 96-bit long double 458 with the rounding mode forced to 53 bits. */ 459#define TARGET_96_ROUND_53_LONG_DOUBLE 0 460 461/* This macro is similar to `TARGET_SWITCHES' but defines names of 462 command options that have values. Its definition is an 463 initializer with a subgrouping for each command option. 464 465 Each subgrouping contains a string constant, that defines the 466 fixed part of the option name, and the address of a variable. The 467 variable, type `char *', is set to the variable part of the given 468 option if the fixed part matches. The actual option name is made 469 by appending `-m' to the specified name. */ 470#define TARGET_OPTIONS \ 471{ { "tune=", &ix86_tune_string, \ 472 N_("Schedule code for given CPU"), 0}, \ 473 { "fpmath=", &ix86_fpmath_string, \ 474 N_("Generate floating point mathematics using given instruction set"), 0},\ 475 { "arch=", &ix86_arch_string, \ 476 N_("Generate code for given CPU"), 0}, \ 477 { "regparm=", &ix86_regparm_string, \ 478 N_("Number of registers used to pass integer arguments"), 0},\ 479 { "align-loops=", &ix86_align_loops_string, \ 480 N_("Loop code aligned to this power of 2"), 0}, \ 481 { "align-jumps=", &ix86_align_jumps_string, \ 482 N_("Jump targets are aligned to this power of 2"), 0}, \ 483 { "align-functions=", &ix86_align_funcs_string, \ 484 N_("Function starts are aligned to this power of 2"), 0}, \ 485 { "preferred-stack-boundary=", \ 486 &ix86_preferred_stack_boundary_string, \ 487 N_("Attempt to keep stack aligned to this power of 2"), 0}, \ 488 { "branch-cost=", &ix86_branch_cost_string, \ 489 N_("Branches are this expensive (1-5, arbitrary units)"), 0},\ 490 { "cmodel=", &ix86_cmodel_string, \ 491 N_("Use given x86-64 code model"), 0}, \ 492 { "debug-arg", &ix86_debug_arg_string, \ 493 "" /* Undocumented. */, 0}, \ 494 { "debug-addr", &ix86_debug_addr_string, \ 495 "" /* Undocumented. */, 0}, \ 496 { "asm=", &ix86_asm_string, \ 497 N_("Use given assembler dialect"), 0}, \ 498 { "tls-dialect=", &ix86_tls_dialect_string, \ 499 N_("Use given thread-local storage dialect"), 0}, \ 500 SUBTARGET_OPTIONS \ 501} 502 503/* Sometimes certain combinations of command options do not make 504 sense on a particular target machine. You can define a macro 505 `OVERRIDE_OPTIONS' to take account of this. This macro, if 506 defined, is executed once just after all the command options have 507 been parsed. 508 509 Don't use this macro to turn on various extra optimizations for 510 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 511 512#define OVERRIDE_OPTIONS override_options () 513 514/* These are meant to be redefined in the host dependent files */ 515#define SUBTARGET_SWITCHES 516#define SUBTARGET_OPTIONS 517 518/* Define this to change the optimizations performed by default. */ 519#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 520 optimization_options ((LEVEL), (SIZE)) 521 522/* Support for configure-time defaults of some command line options. */ 523#define OPTION_DEFAULT_SPECS \ 524 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 525 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 526 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" } 527 528/* Specs for the compiler proper */ 529 530#ifndef CC1_CPU_SPEC 531#define CC1_CPU_SPEC "\ 532%{!mtune*: \ 533%{m386:mtune=i386 \ 534%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \ 535%{m486:-mtune=i486 \ 536%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \ 537%{mpentium:-mtune=pentium \ 538%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \ 539%{mpentiumpro:-mtune=pentiumpro \ 540%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \ 541%{mcpu=*:-mtune=%* \ 542%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \ 543%<mcpu=* \ 544%{mpni:-msse3 \ 545%n`-mpni' is deprecated. Use `-msse3' instead.\n} \ 546%{mno-pni:-mno-sse3 \ 547%n`-mno-pni' is deprecated. Use `-mno-sse3' instead.\n} \ 548%{mintel-syntax:-masm=intel \ 549%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 550%{mno-intel-syntax:-masm=att \ 551%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 552#endif 553 554/* Target CPU builtins. */ 555#define TARGET_CPU_CPP_BUILTINS() \ 556 do \ 557 { \ 558 size_t arch_len = strlen (ix86_arch_string); \ 559 size_t tune_len = strlen (ix86_tune_string); \ 560 int last_arch_char = ix86_arch_string[arch_len - 1]; \ 561 int last_tune_char = ix86_tune_string[tune_len - 1]; \ 562 \ 563 if (TARGET_64BIT) \ 564 { \ 565 builtin_assert ("cpu=x86_64"); \ 566 builtin_assert ("machine=x86_64"); \ 567 builtin_define ("__amd64"); \ 568 builtin_define ("__amd64__"); \ 569 builtin_define ("__x86_64"); \ 570 builtin_define ("__x86_64__"); \ 571 } \ 572 else \ 573 { \ 574 builtin_assert ("cpu=i386"); \ 575 builtin_assert ("machine=i386"); \ 576 builtin_define_std ("i386"); \ 577 } \ 578 \ 579 /* Built-ins based on -mtune= (or -march= if no \ 580 -mtune= given). */ \ 581 if (TARGET_386) \ 582 builtin_define ("__tune_i386__"); \ 583 else if (TARGET_486) \ 584 builtin_define ("__tune_i486__"); \ 585 else if (TARGET_PENTIUM) \ 586 { \ 587 builtin_define ("__tune_i586__"); \ 588 builtin_define ("__tune_pentium__"); \ 589 if (last_tune_char == 'x') \ 590 builtin_define ("__tune_pentium_mmx__"); \ 591 } \ 592 else if (TARGET_PENTIUMPRO) \ 593 { \ 594 builtin_define ("__tune_i686__"); \ 595 builtin_define ("__tune_pentiumpro__"); \ 596 switch (last_tune_char) \ 597 { \ 598 case '3': \ 599 builtin_define ("__tune_pentium3__"); \ 600 /* FALLTHRU */ \ 601 case '2': \ 602 builtin_define ("__tune_pentium2__"); \ 603 break; \ 604 } \ 605 } \ 606 else if (TARGET_K6) \ 607 { \ 608 builtin_define ("__tune_k6__"); \ 609 if (last_tune_char == '2') \ 610 builtin_define ("__tune_k6_2__"); \ 611 else if (last_tune_char == '3') \ 612 builtin_define ("__tune_k6_3__"); \ 613 } \ 614 else if (TARGET_ATHLON) \ 615 { \ 616 builtin_define ("__tune_athlon__"); \ 617 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \ 618 if (last_tune_char != 'n' && last_tune_char != 'd') \ 619 builtin_define ("__tune_athlon_sse__"); \ 620 } \ 621 else if (TARGET_K8) \ 622 builtin_define ("__tune_k8__"); \ 623 else if (TARGET_PENTIUM4) \ 624 builtin_define ("__tune_pentium4__"); \ 625 \ 626 if (TARGET_MMX) \ 627 builtin_define ("__MMX__"); \ 628 if (TARGET_3DNOW) \ 629 builtin_define ("__3dNOW__"); \ 630 if (TARGET_3DNOW_A) \ 631 builtin_define ("__3dNOW_A__"); \ 632 if (TARGET_SSE) \ 633 builtin_define ("__SSE__"); \ 634 if (TARGET_SSE2) \ 635 builtin_define ("__SSE2__"); \ 636 if (TARGET_SSE3) \ 637 { \ 638 builtin_define ("__SSE3__"); \ 639 builtin_define ("__PNI__"); \ 640 } \ 641 if (TARGET_SSE_MATH && TARGET_SSE) \ 642 builtin_define ("__SSE_MATH__"); \ 643 if (TARGET_SSE_MATH && TARGET_SSE2) \ 644 builtin_define ("__SSE2_MATH__"); \ 645 \ 646 /* Built-ins based on -march=. */ \ 647 if (ix86_arch == PROCESSOR_I486) \ 648 { \ 649 builtin_define ("__i486"); \ 650 builtin_define ("__i486__"); \ 651 } \ 652 else if (ix86_arch == PROCESSOR_PENTIUM) \ 653 { \ 654 builtin_define ("__i586"); \ 655 builtin_define ("__i586__"); \ 656 builtin_define ("__pentium"); \ 657 builtin_define ("__pentium__"); \ 658 if (last_arch_char == 'x') \ 659 builtin_define ("__pentium_mmx__"); \ 660 } \ 661 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ 662 { \ 663 builtin_define ("__i686"); \ 664 builtin_define ("__i686__"); \ 665 builtin_define ("__pentiumpro"); \ 666 builtin_define ("__pentiumpro__"); \ 667 } \ 668 else if (ix86_arch == PROCESSOR_K6) \ 669 { \ 670 \ 671 builtin_define ("__k6"); \ 672 builtin_define ("__k6__"); \ 673 if (last_arch_char == '2') \ 674 builtin_define ("__k6_2__"); \ 675 else if (last_arch_char == '3') \ 676 builtin_define ("__k6_3__"); \ 677 } \ 678 else if (ix86_arch == PROCESSOR_ATHLON) \ 679 { \ 680 builtin_define ("__athlon"); \ 681 builtin_define ("__athlon__"); \ 682 /* Plain "athlon" & "athlon-tbird" lacks SSE. */ \ 683 if (last_tune_char != 'n' && last_tune_char != 'd') \ 684 builtin_define ("__athlon_sse__"); \ 685 } \ 686 else if (ix86_arch == PROCESSOR_K8) \ 687 { \ 688 builtin_define ("__k8"); \ 689 builtin_define ("__k8__"); \ 690 } \ 691 else if (ix86_arch == PROCESSOR_PENTIUM4) \ 692 { \ 693 builtin_define ("__pentium4"); \ 694 builtin_define ("__pentium4__"); \ 695 } \ 696 } \ 697 while (0) 698 699#define TARGET_CPU_DEFAULT_i386 0 700#define TARGET_CPU_DEFAULT_i486 1 701#define TARGET_CPU_DEFAULT_pentium 2 702#define TARGET_CPU_DEFAULT_pentium_mmx 3 703#define TARGET_CPU_DEFAULT_pentiumpro 4 704#define TARGET_CPU_DEFAULT_pentium2 5 705#define TARGET_CPU_DEFAULT_pentium3 6 706#define TARGET_CPU_DEFAULT_pentium4 7 707#define TARGET_CPU_DEFAULT_k6 8 708#define TARGET_CPU_DEFAULT_k6_2 9 709#define TARGET_CPU_DEFAULT_k6_3 10 710#define TARGET_CPU_DEFAULT_athlon 11 711#define TARGET_CPU_DEFAULT_athlon_sse 12 712#define TARGET_CPU_DEFAULT_k8 13 713#define TARGET_CPU_DEFAULT_pentium_m 14 714#define TARGET_CPU_DEFAULT_prescott 15 715#define TARGET_CPU_DEFAULT_nocona 16 716 717#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 718 "pentiumpro", "pentium2", "pentium3", \ 719 "pentium4", "k6", "k6-2", "k6-3",\ 720 "athlon", "athlon-4", "k8", \ 721 "pentium-m", "prescott", "nocona"} 722 723#ifndef CC1_SPEC 724#define CC1_SPEC "%(cc1_cpu) " 725#endif 726 727/* This macro defines names of additional specifications to put in the 728 specs that can be used in various specifications like CC1_SPEC. Its 729 definition is an initializer with a subgrouping for each command option. 730 731 Each subgrouping contains a string constant, that defines the 732 specification name, and a string constant that used by the GCC driver 733 program. 734 735 Do not define this macro if it does not need to do anything. */ 736 737#ifndef SUBTARGET_EXTRA_SPECS 738#define SUBTARGET_EXTRA_SPECS 739#endif 740 741#define EXTRA_SPECS \ 742 { "cc1_cpu", CC1_CPU_SPEC }, \ 743 SUBTARGET_EXTRA_SPECS 744 745/* target machine storage layout */ 746 747#define LONG_DOUBLE_TYPE_SIZE 96 748 749/* Set the value of FLT_EVAL_METHOD in float.h. When using only the 750 FPU, assume that the fpcw is set to extended precision; when using 751 only SSE, rounding is correct; when using both SSE and the FPU, 752 the rounding precision is indeterminate, since either may be chosen 753 apparently at random. */ 754#define TARGET_FLT_EVAL_METHOD \ 755 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 756 757#define SHORT_TYPE_SIZE 16 758#define INT_TYPE_SIZE 32 759#define FLOAT_TYPE_SIZE 32 760#ifndef LONG_TYPE_SIZE 761#define LONG_TYPE_SIZE BITS_PER_WORD 762#endif 763#define MAX_WCHAR_TYPE_SIZE 32 764#define DOUBLE_TYPE_SIZE 64 765#define LONG_LONG_TYPE_SIZE 64 766 767#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 768#define MAX_BITS_PER_WORD 64 769#define MAX_LONG_TYPE_SIZE 64 770#else 771#define MAX_BITS_PER_WORD 32 772#define MAX_LONG_TYPE_SIZE 32 773#endif 774 775/* Define this if most significant byte of a word is the lowest numbered. */ 776/* That is true on the 80386. */ 777 778#define BITS_BIG_ENDIAN 0 779 780/* Define this if most significant byte of a word is the lowest numbered. */ 781/* That is not true on the 80386. */ 782#define BYTES_BIG_ENDIAN 0 783 784/* Define this if most significant word of a multiword number is the lowest 785 numbered. */ 786/* Not true for 80386 */ 787#define WORDS_BIG_ENDIAN 0 788 789/* Width of a word, in units (bytes). */ 790#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 791#ifdef IN_LIBGCC2 792#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 793#else 794#define MIN_UNITS_PER_WORD 4 795#endif 796 797/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 798#define PARM_BOUNDARY BITS_PER_WORD 799 800/* Boundary (in *bits*) on which stack pointer should be aligned. */ 801#define STACK_BOUNDARY BITS_PER_WORD 802 803/* Boundary (in *bits*) on which the stack pointer prefers to be 804 aligned; the compiler cannot rely on having this alignment. */ 805#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 806 807/* As of July 2001, many runtimes to not align the stack properly when 808 entering main. This causes expand_main_function to forcibly align 809 the stack, which results in aligned frames for functions called from 810 main, though it does nothing for the alignment of main itself. */ 811#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 812 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 813 814/* Minimum allocation boundary for the code of a function. */ 815#define FUNCTION_BOUNDARY 8 816 817/* C++ stores the virtual bit in the lowest bit of function pointers. */ 818#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 819 820/* Alignment of field after `int : 0' in a structure. */ 821 822#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 823 824/* Minimum size in bits of the largest boundary to which any 825 and all fundamental data types supported by the hardware 826 might need to be aligned. No data type wants to be aligned 827 rounder than this. 828 829 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 830 and Pentium Pro XFmode values at 128 bit boundaries. */ 831 832#define BIGGEST_ALIGNMENT 128 833 834/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 835#define ALIGN_MODE_128(MODE) \ 836 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE)) 837 838/* The published ABIs say that doubles should be aligned on word 839 boundaries, so lower the alignment for structure fields unless 840 -malign-double is set. */ 841 842/* ??? Blah -- this macro is used directly by libobjc. Since it 843 supports no vector modes, cut out the complexity and fall back 844 on BIGGEST_FIELD_ALIGNMENT. */ 845#ifdef IN_TARGET_LIBS 846#ifdef __x86_64__ 847#define BIGGEST_FIELD_ALIGNMENT 128 848#else 849#define BIGGEST_FIELD_ALIGNMENT 32 850#endif 851#else 852#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 853 x86_field_alignment (FIELD, COMPUTED) 854#endif 855 856/* If defined, a C expression to compute the alignment given to a 857 constant that is being placed in memory. EXP is the constant 858 and ALIGN is the alignment that the object would ordinarily have. 859 The value of this macro is used instead of that alignment to align 860 the object. 861 862 If this macro is not defined, then ALIGN is used. 863 864 The typical use of this macro is to increase alignment for string 865 constants to be word aligned so that `strcpy' calls that copy 866 constants can be done inline. */ 867 868#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 869 870/* If defined, a C expression to compute the alignment for a static 871 variable. TYPE is the data type, and ALIGN is the alignment that 872 the object would ordinarily have. The value of this macro is used 873 instead of that alignment to align the object. 874 875 If this macro is not defined, then ALIGN is used. 876 877 One use of this macro is to increase alignment of medium-size 878 data to make it all fit in fewer cache lines. Another is to 879 cause character arrays to be word-aligned so that `strcpy' calls 880 that copy constants to character arrays can be done inline. */ 881 882#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 883 884/* If defined, a C expression to compute the alignment for a local 885 variable. TYPE is the data type, and ALIGN is the alignment that 886 the object would ordinarily have. The value of this macro is used 887 instead of that alignment to align the object. 888 889 If this macro is not defined, then ALIGN is used. 890 891 One use of this macro is to increase alignment of medium-size 892 data to make it all fit in fewer cache lines. */ 893 894#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 895 896/* If defined, a C expression that gives the alignment boundary, in 897 bits, of an argument with the specified mode and type. If it is 898 not defined, `PARM_BOUNDARY' is used for all arguments. */ 899 900#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 901 ix86_function_arg_boundary ((MODE), (TYPE)) 902 903/* Set this nonzero if move instructions will actually fail to work 904 when given unaligned data. */ 905#define STRICT_ALIGNMENT 0 906 907/* If bit field type is int, don't let it cross an int, 908 and give entire struct the alignment of an int. */ 909/* Required on the 386 since it doesn't have bit-field insns. */ 910#define PCC_BITFIELD_TYPE_MATTERS 1 911 912/* Standard register usage. */ 913 914/* This processor has special stack-like registers. See reg-stack.c 915 for details. */ 916 917#define STACK_REGS 918#define IS_STACK_MODE(MODE) \ 919 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \ 920 921/* Number of actual hardware registers. 922 The hardware registers are assigned numbers for the compiler 923 from 0 to just below FIRST_PSEUDO_REGISTER. 924 All registers that the compiler knows about must be given numbers, 925 even those that are not normally considered general registers. 926 927 In the 80386 we give the 8 general purpose registers the numbers 0-7. 928 We number the floating point registers 8-15. 929 Note that registers 0-7 can be accessed as a short or int, 930 while only 0-3 may be used with byte `mov' instructions. 931 932 Reg 16 does not correspond to any hardware register, but instead 933 appears in the RTL as an argument pointer prior to reload, and is 934 eliminated during reloading in favor of either the stack or frame 935 pointer. */ 936 937#define FIRST_PSEUDO_REGISTER 53 938 939/* Number of hardware registers that go into the DWARF-2 unwind info. 940 If not defined, equals FIRST_PSEUDO_REGISTER. */ 941 942#define DWARF_FRAME_REGISTERS 17 943 944/* 1 for registers that have pervasive standard uses 945 and are not available for the register allocator. 946 On the 80386, the stack pointer is such, as is the arg pointer. 947 948 The value is a mask - bit 1 is set for fixed registers 949 for 32bit target, while 2 is set for fixed registers for 64bit. 950 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 951 */ 952#define FIXED_REGISTERS \ 953/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 954{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ 955/*arg,flags,fpsr,dir,frame*/ \ 956 3, 3, 3, 3, 3, \ 957/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 958 0, 0, 0, 0, 0, 0, 0, 0, \ 959/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 960 0, 0, 0, 0, 0, 0, 0, 0, \ 961/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 962 1, 1, 1, 1, 1, 1, 1, 1, \ 963/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 964 1, 1, 1, 1, 1, 1, 1, 1} 965 966 967/* 1 for registers not available across function calls. 968 These must include the FIXED_REGISTERS and also any 969 registers that can be used without being saved. 970 The latter must include the registers where values are returned 971 and the register where structure-value addresses are passed. 972 Aside from that, you can include as many other registers as you like. 973 974 The value is a mask - bit 1 is set for call used 975 for 32bit target, while 2 is set for call used for 64bit. 976 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 977*/ 978#define CALL_USED_REGISTERS \ 979/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 980{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 981/*arg,flags,fpsr,dir,frame*/ \ 982 3, 3, 3, 3, 3, \ 983/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 984 3, 3, 3, 3, 3, 3, 3, 3, \ 985/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 986 3, 3, 3, 3, 3, 3, 3, 3, \ 987/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 988 3, 3, 3, 3, 1, 1, 1, 1, \ 989/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 990 3, 3, 3, 3, 3, 3, 3, 3} \ 991 992/* Order in which to allocate registers. Each register must be 993 listed once, even those in FIXED_REGISTERS. List frame pointer 994 late and fixed registers last. Note that, in general, we prefer 995 registers listed in CALL_USED_REGISTERS, keeping the others 996 available for storage of persistent values. 997 998 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 999 so this is just empty initializer for array. */ 1000 1001#define REG_ALLOC_ORDER \ 1002{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 1003 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 1004 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1005 48, 49, 50, 51, 52 } 1006 1007/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 1008 to be rearranged based on a particular function. When using sse math, 1009 we want to allocate SSE before x87 registers and vice vera. */ 1010 1011#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 1012 1013 1014/* Macro to conditionally modify fixed_regs/call_used_regs. */ 1015#define CONDITIONAL_REGISTER_USAGE \ 1016do { \ 1017 int i; \ 1018 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1019 { \ 1020 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ 1021 call_used_regs[i] = (call_used_regs[i] \ 1022 & (TARGET_64BIT ? 2 : 1)) != 0; \ 1023 } \ 1024 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 1025 { \ 1026 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 1027 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 1028 } \ 1029 if (! TARGET_MMX) \ 1030 { \ 1031 int i; \ 1032 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1033 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 1034 fixed_regs[i] = call_used_regs[i] = 1; \ 1035 } \ 1036 if (! TARGET_SSE) \ 1037 { \ 1038 int i; \ 1039 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1040 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 1041 fixed_regs[i] = call_used_regs[i] = 1; \ 1042 } \ 1043 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 1044 { \ 1045 int i; \ 1046 HARD_REG_SET x; \ 1047 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 1048 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1049 if (TEST_HARD_REG_BIT (x, i)) \ 1050 fixed_regs[i] = call_used_regs[i] = 1; \ 1051 } \ 1052 } while (0) 1053 1054/* Return number of consecutive hard regs needed starting at reg REGNO 1055 to hold something of mode MODE. 1056 This is ordinarily the length in words of a value of mode MODE 1057 but can be less for certain modes in special long registers. 1058 1059 Actually there are no two word move instructions for consecutive 1060 registers. And only registers 0-3 may have mov byte instructions 1061 applied to them. 1062 */ 1063 1064#define HARD_REGNO_NREGS(REGNO, MODE) \ 1065 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1066 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1067 : ((MODE) == XFmode \ 1068 ? (TARGET_64BIT ? 2 : 3) \ 1069 : (MODE) == XCmode \ 1070 ? (TARGET_64BIT ? 4 : 6) \ 1071 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1072 1073#define VALID_SSE2_REG_MODE(MODE) \ 1074 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1075 || (MODE) == V2DImode || (MODE) == DFmode) 1076 1077#define VALID_SSE_REG_MODE(MODE) \ 1078 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1079 || (MODE) == SFmode || (MODE) == TFmode) 1080 1081#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1082 ((MODE) == V2SFmode || (MODE) == SFmode) 1083 1084#define VALID_MMX_REG_MODE(MODE) \ 1085 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 1086 || (MODE) == V2SImode || (MODE) == SImode) 1087 1088#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1089 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ 1090 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ 1091 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) 1092 1093#define VALID_FP_MODE_P(MODE) \ 1094 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1095 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1096 1097#define VALID_INT_MODE_P(MODE) \ 1098 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1099 || (MODE) == DImode \ 1100 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1101 || (MODE) == CDImode \ 1102 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1103 || (MODE) == TFmode || (MODE) == TCmode))) 1104 1105/* Return true for modes passed in SSE registers. */ 1106#define SSE_REG_MODE_P(MODE) \ 1107 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ 1108 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ 1109 || (MODE) == V4SFmode || (MODE) == V4SImode) 1110 1111/* Return true for modes passed in MMX registers. */ 1112#define MMX_REG_MODE_P(MODE) \ 1113 ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \ 1114 || (MODE) == V2SFmode) 1115 1116/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1117 1118#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1119 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1120 1121/* Value is 1 if it is a good idea to tie two pseudo registers 1122 when one has mode MODE1 and one has mode MODE2. 1123 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1124 for any hard reg, then this must be 0 for correct output. */ 1125 1126#define MODES_TIEABLE_P(MODE1, MODE2) \ 1127 ((MODE1) == (MODE2) \ 1128 || (((MODE1) == HImode || (MODE1) == SImode \ 1129 || ((MODE1) == QImode \ 1130 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1131 || ((MODE1) == DImode && TARGET_64BIT)) \ 1132 && ((MODE2) == HImode || (MODE2) == SImode \ 1133 || ((MODE2) == QImode \ 1134 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1135 || ((MODE2) == DImode && TARGET_64BIT)))) 1136 1137/* It is possible to write patterns to move flags; but until someone 1138 does it, */ 1139#define AVOID_CCMODE_COPIES 1140 1141/* Specify the modes required to caller save a given hard regno. 1142 We do this on i386 to prevent flags from being saved at all. 1143 1144 Kill any attempts to combine saving of modes. */ 1145 1146#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1147 (CC_REGNO_P (REGNO) ? VOIDmode \ 1148 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1149 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\ 1150 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1151 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 1152 : (MODE)) 1153/* Specify the registers used for certain standard purposes. 1154 The values of these macros are register numbers. */ 1155 1156/* on the 386 the pc register is %eip, and is not usable as a general 1157 register. The ordinary mov instructions won't work */ 1158/* #define PC_REGNUM */ 1159 1160/* Register to use for pushing function arguments. */ 1161#define STACK_POINTER_REGNUM 7 1162 1163/* Base register for access to local variables of the function. */ 1164#define HARD_FRAME_POINTER_REGNUM 6 1165 1166/* Base register for access to local variables of the function. */ 1167#define FRAME_POINTER_REGNUM 20 1168 1169/* First floating point reg */ 1170#define FIRST_FLOAT_REG 8 1171 1172/* First & last stack-like regs */ 1173#define FIRST_STACK_REG FIRST_FLOAT_REG 1174#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1175 1176#define FLAGS_REG 17 1177#define FPSR_REG 18 1178#define DIRFLAG_REG 19 1179 1180#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1181#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1182 1183#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1184#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1185 1186#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1187#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1188 1189#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1190#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1191 1192/* Value should be nonzero if functions must have frame pointers. 1193 Zero means the frame pointer need not be set up (and parms 1194 may be accessed via the stack pointer) in functions that seem suitable. 1195 This is computed in `reload', in reload1.c. */ 1196#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1197 1198/* Override this in other tm.h files to cope with various OS losage 1199 requiring a frame pointer. */ 1200#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1201#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1202#endif 1203 1204/* Make sure we can access arbitrary call frames. */ 1205#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1206 1207/* Base register for access to arguments of the function. */ 1208#define ARG_POINTER_REGNUM 16 1209 1210/* Register in which static-chain is passed to a function. 1211 We do use ECX as static chain register for 32 bit ABI. On the 1212 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1213#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1214 1215/* Register to hold the addressing base for position independent 1216 code access to data items. We don't use PIC pointer for 64bit 1217 mode. Define the regnum to dummy value to prevent gcc from 1218 pessimizing code dealing with EBX. 1219 1220 To avoid clobbering a call-saved register unnecessarily, we renumber 1221 the pic register when possible. The change is visible after the 1222 prologue has been emitted. */ 1223 1224#define REAL_PIC_OFFSET_TABLE_REGNUM 3 1225 1226#define PIC_OFFSET_TABLE_REGNUM \ 1227 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \ 1228 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1229 : REAL_PIC_OFFSET_TABLE_REGNUM) 1230 1231#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1232 1233/* Register in which address to store a structure value 1234 arrives in the function. On the 386, the prologue 1235 copies this from the stack to register %eax. */ 1236#define STRUCT_VALUE_INCOMING 0 1237 1238/* Place in which caller passes the structure value address. 1239 0 means push the value on the stack like an argument. */ 1240#define STRUCT_VALUE 0 1241 1242/* A C expression which can inhibit the returning of certain function 1243 values in registers, based on the type of value. A nonzero value 1244 says to return the function value in memory, just as large 1245 structures are always returned. Here TYPE will be a C expression 1246 of type `tree', representing the data type of the value. 1247 1248 Note that values of mode `BLKmode' must be explicitly handled by 1249 this macro. Also, the option `-fpcc-struct-return' takes effect 1250 regardless of this macro. On most systems, it is possible to 1251 leave the macro undefined; this causes a default definition to be 1252 used, whose value is the constant 1 for `BLKmode' values, and 0 1253 otherwise. 1254 1255 Do not use this macro to indicate that structures and unions 1256 should always be returned in memory. You should instead use 1257 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1258 1259#define RETURN_IN_MEMORY(TYPE) \ 1260 ix86_return_in_memory (TYPE) 1261 1262/* This is overridden by <cygwin.h>. */ 1263#define MS_AGGREGATE_RETURN 0 1264 1265 1266/* Define the classes of registers for register constraints in the 1267 machine description. Also define ranges of constants. 1268 1269 One of the classes must always be named ALL_REGS and include all hard regs. 1270 If there is more than one class, another class must be named NO_REGS 1271 and contain no registers. 1272 1273 The name GENERAL_REGS must be the name of a class (or an alias for 1274 another name such as ALL_REGS). This is the class of registers 1275 that is allowed by "g" or "r" in a register constraint. 1276 Also, registers outside this class are allocated only when 1277 instructions express preferences for them. 1278 1279 The classes must be numbered in nondecreasing order; that is, 1280 a larger-numbered class must never be contained completely 1281 in a smaller-numbered class. 1282 1283 For any two classes, it is very desirable that there be another 1284 class that represents their union. 1285 1286 It might seem that class BREG is unnecessary, since no useful 386 1287 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1288 and the "b" register constraint is useful in asms for syscalls. 1289 1290 The flags and fpsr registers are in no class. */ 1291 1292enum reg_class 1293{ 1294 NO_REGS, 1295 AREG, DREG, CREG, BREG, SIREG, DIREG, 1296 AD_REGS, /* %eax/%edx for DImode */ 1297 Q_REGS, /* %eax %ebx %ecx %edx */ 1298 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1299 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1300 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1301 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1302 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1303 FLOAT_REGS, 1304 SSE_REGS, 1305 MMX_REGS, 1306 FP_TOP_SSE_REGS, 1307 FP_SECOND_SSE_REGS, 1308 FLOAT_SSE_REGS, 1309 FLOAT_INT_REGS, 1310 INT_SSE_REGS, 1311 FLOAT_INT_SSE_REGS, 1312 ALL_REGS, LIM_REG_CLASSES 1313}; 1314 1315#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1316 1317#define INTEGER_CLASS_P(CLASS) \ 1318 reg_class_subset_p ((CLASS), GENERAL_REGS) 1319#define FLOAT_CLASS_P(CLASS) \ 1320 reg_class_subset_p ((CLASS), FLOAT_REGS) 1321#define SSE_CLASS_P(CLASS) \ 1322 reg_class_subset_p ((CLASS), SSE_REGS) 1323#define MMX_CLASS_P(CLASS) \ 1324 reg_class_subset_p ((CLASS), MMX_REGS) 1325#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1326 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1327#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1328 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1329#define MAYBE_SSE_CLASS_P(CLASS) \ 1330 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1331#define MAYBE_MMX_CLASS_P(CLASS) \ 1332 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1333 1334#define Q_CLASS_P(CLASS) \ 1335 reg_class_subset_p ((CLASS), Q_REGS) 1336 1337/* Give names of register classes as strings for dump file. */ 1338 1339#define REG_CLASS_NAMES \ 1340{ "NO_REGS", \ 1341 "AREG", "DREG", "CREG", "BREG", \ 1342 "SIREG", "DIREG", \ 1343 "AD_REGS", \ 1344 "Q_REGS", "NON_Q_REGS", \ 1345 "INDEX_REGS", \ 1346 "LEGACY_REGS", \ 1347 "GENERAL_REGS", \ 1348 "FP_TOP_REG", "FP_SECOND_REG", \ 1349 "FLOAT_REGS", \ 1350 "SSE_REGS", \ 1351 "MMX_REGS", \ 1352 "FP_TOP_SSE_REGS", \ 1353 "FP_SECOND_SSE_REGS", \ 1354 "FLOAT_SSE_REGS", \ 1355 "FLOAT_INT_REGS", \ 1356 "INT_SSE_REGS", \ 1357 "FLOAT_INT_SSE_REGS", \ 1358 "ALL_REGS" } 1359 1360/* Define which registers fit in which classes. 1361 This is an initializer for a vector of HARD_REG_SET 1362 of length N_REG_CLASSES. */ 1363 1364#define REG_CLASS_CONTENTS \ 1365{ { 0x00, 0x0 }, \ 1366 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1367 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1368 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1369 { 0x03, 0x0 }, /* AD_REGS */ \ 1370 { 0x0f, 0x0 }, /* Q_REGS */ \ 1371 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1372 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1373 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1374 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1375 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1376 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1377{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1378{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1379{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1380{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1381{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1382 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1383{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1384{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1385{ 0xffffffff,0x1fffff } \ 1386} 1387 1388/* The same information, inverted: 1389 Return the class number of the smallest class containing 1390 reg number REGNO. This could be a conditional expression 1391 or could index an array. */ 1392 1393#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1394 1395/* When defined, the compiler allows registers explicitly used in the 1396 rtl to be used as spill registers but prevents the compiler from 1397 extending the lifetime of these registers. */ 1398 1399#define SMALL_REGISTER_CLASSES 1 1400 1401#define QI_REG_P(X) \ 1402 (REG_P (X) && REGNO (X) < 4) 1403 1404#define GENERAL_REGNO_P(N) \ 1405 ((N) < 8 || REX_INT_REGNO_P (N)) 1406 1407#define GENERAL_REG_P(X) \ 1408 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1409 1410#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1411 1412#define NON_QI_REG_P(X) \ 1413 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1414 1415#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1416#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1417 1418#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1419#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1420#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1421#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1422 1423#define SSE_REGNO_P(N) \ 1424 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1425 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1426 1427#define REX_SSE_REGNO_P(N) \ 1428 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG) 1429 1430#define SSE_REGNO(N) \ 1431 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1432#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1433 1434#define SSE_FLOAT_MODE_P(MODE) \ 1435 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1436 1437#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1438#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1439 1440#define STACK_REG_P(XOP) \ 1441 (REG_P (XOP) && \ 1442 REGNO (XOP) >= FIRST_STACK_REG && \ 1443 REGNO (XOP) <= LAST_STACK_REG) 1444 1445#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1446 1447#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1448 1449#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1450#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1451 1452/* The class value for index registers, and the one for base regs. */ 1453 1454#define INDEX_REG_CLASS INDEX_REGS 1455#define BASE_REG_CLASS GENERAL_REGS 1456 1457/* Get reg_class from a letter such as appears in the machine description. */ 1458 1459#define REG_CLASS_FROM_LETTER(C) \ 1460 ((C) == 'r' ? GENERAL_REGS : \ 1461 (C) == 'R' ? LEGACY_REGS : \ 1462 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1463 (C) == 'Q' ? Q_REGS : \ 1464 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1465 ? FLOAT_REGS \ 1466 : NO_REGS) : \ 1467 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1468 ? FP_TOP_REG \ 1469 : NO_REGS) : \ 1470 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1471 ? FP_SECOND_REG \ 1472 : NO_REGS) : \ 1473 (C) == 'a' ? AREG : \ 1474 (C) == 'b' ? BREG : \ 1475 (C) == 'c' ? CREG : \ 1476 (C) == 'd' ? DREG : \ 1477 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1478 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1479 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1480 (C) == 'A' ? AD_REGS : \ 1481 (C) == 'D' ? DIREG : \ 1482 (C) == 'S' ? SIREG : NO_REGS) 1483 1484/* The letters I, J, K, L and M in a register constraint string 1485 can be used to stand for particular ranges of immediate operands. 1486 This macro defines what the ranges are. 1487 C is the letter, and VALUE is a constant value. 1488 Return 1 if VALUE is in the range specified by C. 1489 1490 I is for non-DImode shifts. 1491 J is for DImode shifts. 1492 K is for signed imm8 operands. 1493 L is for andsi as zero-extending move. 1494 M is for shifts that can be executed by the "lea" opcode. 1495 N is for immediate operands for out/in instructions (0-255) 1496 */ 1497 1498#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1499 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1500 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1501 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1502 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1503 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1504 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1505 : 0) 1506 1507/* Similar, but for floating constants, and defining letters G and H. 1508 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1509 TARGET_387 isn't set, because the stack register converter may need to 1510 load 0.0 into the function value register. */ 1511 1512#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1513 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1514 : 0) 1515 1516/* A C expression that defines the optional machine-dependent 1517 constraint letters that can be used to segregate specific types of 1518 operands, usually memory references, for the target machine. Any 1519 letter that is not elsewhere defined and not matched by 1520 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1521 be defined. 1522 1523 If it is required for a particular target machine, it should 1524 return 1 if VALUE corresponds to the operand type represented by 1525 the constraint letter C. If C is not defined as an extra 1526 constraint, the value returned should be 0 regardless of VALUE. */ 1527 1528#define EXTRA_CONSTRAINT(VALUE, D) \ 1529 ((D) == 'e' ? x86_64_sign_extended_value (VALUE) \ 1530 : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \ 1531 : (D) == 'C' ? standard_sse_constant_p (VALUE) \ 1532 : 0) 1533 1534/* Place additional restrictions on the register class to use when it 1535 is necessary to be able to hold a value of mode MODE in a reload 1536 register for which class CLASS would ordinarily be used. */ 1537 1538#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1539 ((MODE) == QImode && !TARGET_64BIT \ 1540 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1541 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1542 ? Q_REGS : (CLASS)) 1543 1544/* Given an rtx X being reloaded into a reg required to be 1545 in class CLASS, return the class of reg to actually use. 1546 In general this is just CLASS; but on some machines 1547 in some cases it is preferable to use a more restrictive class. 1548 On the 80386 series, we prevent floating constants from being 1549 reloaded into floating registers (since no move-insn can do that) 1550 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1551 1552/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1553 QImode must go into class Q_REGS. 1554 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1555 movdf to do mem-to-mem moves through integer regs. */ 1556 1557#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1558 ix86_preferred_reload_class ((X), (CLASS)) 1559 1560/* If we are copying between general and FP registers, we need a memory 1561 location. The same is true for SSE and MMX registers. */ 1562#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1563 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1564 1565/* QImode spills from non-QI registers need a scratch. This does not 1566 happen often -- the only example so far requires an uninitialized 1567 pseudo. */ 1568 1569#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1570 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1571 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1572 ? Q_REGS : NO_REGS) 1573 1574/* Return the maximum number of consecutive registers 1575 needed to represent mode MODE in a register of class CLASS. */ 1576/* On the 80386, this is the size of MODE in words, 1577 except in the FP regs, where a single reg is always enough. */ 1578#define CLASS_MAX_NREGS(CLASS, MODE) \ 1579 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1580 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1581 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ 1582 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1583 1584/* A C expression whose value is nonzero if pseudos that have been 1585 assigned to registers of class CLASS would likely be spilled 1586 because registers of CLASS are needed for spill registers. 1587 1588 The default value of this macro returns 1 if CLASS has exactly one 1589 register and zero otherwise. On most machines, this default 1590 should be used. Only define this macro to some other expression 1591 if pseudo allocated by `local-alloc.c' end up in memory because 1592 their hard registers were needed for spill registers. If this 1593 macro returns nonzero for those classes, those pseudos will only 1594 be allocated by `global.c', which knows how to reallocate the 1595 pseudo to another register. If there would not be another 1596 register available for reallocation, you should not change the 1597 definition of this macro since the only effect of such a 1598 definition would be to slow down register allocation. */ 1599 1600#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1601 (((CLASS) == AREG) \ 1602 || ((CLASS) == DREG) \ 1603 || ((CLASS) == CREG) \ 1604 || ((CLASS) == BREG) \ 1605 || ((CLASS) == AD_REGS) \ 1606 || ((CLASS) == SIREG) \ 1607 || ((CLASS) == DIREG) \ 1608 || ((CLASS) == FP_TOP_REG) \ 1609 || ((CLASS) == FP_SECOND_REG)) 1610 1611/* Return a class of registers that cannot change FROM mode to TO mode. 1612 1613 x87 registers can't do subreg as all values are reformated to extended 1614 precision. XMM registers does not support with nonzero offsets equal 1615 to 4, 8 and 12 otherwise valid for integer registers. Since we can't 1616 determine these, prohibit all nonparadoxical subregs changing size. */ 1617 1618#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1619 (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \ 1620 ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \ 1621 || MAYBE_MMX_CLASS_P (CLASS) \ 1622 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1623 ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0) 1624 1625/* A C statement that adds to CLOBBERS any hard regs the port wishes 1626 to automatically clobber for all asms. 1627 1628 We do this in the new i386 backend to maintain source compatibility 1629 with the old cc0-based compiler. */ 1630 1631#define MD_ASM_CLOBBERS(CLOBBERS) \ 1632 do { \ 1633 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ 1634 (CLOBBERS)); \ 1635 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ 1636 (CLOBBERS)); \ 1637 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ 1638 (CLOBBERS)); \ 1639 } while (0) 1640 1641/* Stack layout; function entry, exit and calling. */ 1642 1643/* Define this if pushing a word on the stack 1644 makes the stack pointer a smaller address. */ 1645#define STACK_GROWS_DOWNWARD 1646 1647/* Define this if the nominal address of the stack frame 1648 is at the high-address end of the local variables; 1649 that is, each additional local variable allocated 1650 goes at a more negative offset in the frame. */ 1651#define FRAME_GROWS_DOWNWARD 1652 1653/* Offset within stack frame to start allocating local variables at. 1654 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1655 first local allocated. Otherwise, it is the offset to the BEGINNING 1656 of the first local allocated. */ 1657#define STARTING_FRAME_OFFSET 0 1658 1659/* If we generate an insn to push BYTES bytes, 1660 this says how many the stack pointer really advances by. 1661 On 386 pushw decrements by exactly 2 no matter what the position was. 1662 On the 386 there is no pushb; we use pushw instead, and this 1663 has the effect of rounding up to 2. 1664 1665 For 64bit ABI we round up to 8 bytes. 1666 */ 1667 1668#define PUSH_ROUNDING(BYTES) \ 1669 (TARGET_64BIT \ 1670 ? (((BYTES) + 7) & (-8)) \ 1671 : (((BYTES) + 1) & (-2))) 1672 1673/* If defined, the maximum amount of space required for outgoing arguments will 1674 be computed and placed into the variable 1675 `current_function_outgoing_args_size'. No space will be pushed onto the 1676 stack for each call; instead, the function prologue should increase the stack 1677 frame size by this amount. */ 1678 1679#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1680 1681/* If defined, a C expression whose value is nonzero when we want to use PUSH 1682 instructions to pass outgoing arguments. */ 1683 1684#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1685 1686/* We want the stack and args grow in opposite directions, even if 1687 PUSH_ARGS is 0. */ 1688#define PUSH_ARGS_REVERSED 1 1689 1690/* Offset of first parameter from the argument pointer register value. */ 1691#define FIRST_PARM_OFFSET(FNDECL) 0 1692 1693/* Define this macro if functions should assume that stack space has been 1694 allocated for arguments even when their values are passed in registers. 1695 1696 The value of this macro is the size, in bytes, of the area reserved for 1697 arguments passed in registers for the function represented by FNDECL. 1698 1699 This space can be allocated by the caller, or be a part of the 1700 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1701 which. */ 1702#define REG_PARM_STACK_SPACE(FNDECL) 0 1703 1704/* Define as a C expression that evaluates to nonzero if we do not know how 1705 to pass TYPE solely in registers. The file expr.h defines a 1706 definition that is usually appropriate, refer to expr.h for additional 1707 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be 1708 computed in the stack and then loaded into a register. */ 1709#define MUST_PASS_IN_STACK(MODE, TYPE) ix86_must_pass_in_stack ((MODE), (TYPE)) 1710 1711/* Value is the number of bytes of arguments automatically 1712 popped when returning from a subroutine call. 1713 FUNDECL is the declaration node of the function (as a tree), 1714 FUNTYPE is the data type of the function (as a tree), 1715 or for a library call it is an identifier node for the subroutine name. 1716 SIZE is the number of bytes of arguments passed on the stack. 1717 1718 On the 80386, the RTD insn may be used to pop them if the number 1719 of args is fixed, but if the number is variable then the caller 1720 must pop them all. RTD can't be used for library calls now 1721 because the library is compiled with the Unix compiler. 1722 Use of RTD is a selectable option, since it is incompatible with 1723 standard Unix calling sequences. If the option is not selected, 1724 the caller must always pop the args. 1725 1726 The attribute stdcall is equivalent to RTD on a per module basis. */ 1727 1728#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1729 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1730 1731/* Define how to find the value returned by a function. 1732 VALTYPE is the data type of the value (as a tree). 1733 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1734 otherwise, FUNC is 0. */ 1735#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1736 ix86_function_value (VALTYPE) 1737 1738#define FUNCTION_VALUE_REGNO_P(N) \ 1739 ix86_function_value_regno_p (N) 1740 1741/* Define how to find the value returned by a library function 1742 assuming the value has mode MODE. */ 1743 1744#define LIBCALL_VALUE(MODE) \ 1745 ix86_libcall_value (MODE) 1746 1747/* Define the size of the result block used for communication between 1748 untyped_call and untyped_return. The block contains a DImode value 1749 followed by the block used by fnsave and frstor. */ 1750 1751#define APPLY_RESULT_SIZE (8+108) 1752 1753/* 1 if N is a possible register number for function argument passing. */ 1754#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1755 1756/* Define a data type for recording info about an argument list 1757 during the scan of that argument list. This data type should 1758 hold all necessary information about the function itself 1759 and about the args processed so far, enough to enable macros 1760 such as FUNCTION_ARG to determine where the next arg should go. */ 1761 1762typedef struct ix86_args { 1763 int words; /* # words passed so far */ 1764 int nregs; /* # registers available for passing */ 1765 int regno; /* next available register number */ 1766 int fastcall; /* fastcall calling convention is used */ 1767 int sse_words; /* # sse words passed so far */ 1768 int sse_nregs; /* # sse registers available for passing */ 1769 int warn_sse; /* True when we want to warn about SSE ABI. */ 1770 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1771 int sse_regno; /* next available sse register number */ 1772 int mmx_words; /* # mmx words passed so far */ 1773 int mmx_nregs; /* # mmx registers available for passing */ 1774 int mmx_regno; /* next available mmx register number */ 1775 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1776} CUMULATIVE_ARGS; 1777 1778/* Initialize a variable CUM of type CUMULATIVE_ARGS 1779 for a call to a function whose data type is FNTYPE. 1780 For a library call, FNTYPE is 0. */ 1781 1782#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1783 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1784 1785/* Update the data in CUM to advance over an argument 1786 of mode MODE and data type TYPE. 1787 (TYPE is null for libcalls where that information may not be available.) */ 1788 1789#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1790 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1791 1792/* Define where to put the arguments to a function. 1793 Value is zero to push the argument on the stack, 1794 or a hard register in which to store the argument. 1795 1796 MODE is the argument's machine mode. 1797 TYPE is the data type of the argument (as a tree). 1798 This is null for libcalls where that information may 1799 not be available. 1800 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1801 the preceding args and about the function being called. 1802 NAMED is nonzero if this argument is a named parameter 1803 (otherwise it is an extra parameter matching an ellipsis). */ 1804 1805#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1806 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1807 1808/* For an arg passed partly in registers and partly in memory, 1809 this is the number of registers used. 1810 For args passed entirely in registers or entirely in memory, zero. */ 1811 1812#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1813 1814/* A C expression that indicates when an argument must be passed by 1815 reference. If nonzero for an argument, a copy of that argument is 1816 made in memory and a pointer to the argument is passed instead of 1817 the argument itself. The pointer is passed in whatever way is 1818 appropriate for passing a pointer to that type. */ 1819 1820#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1821 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED) 1822 1823/* Perform any needed actions needed for a function that is receiving a 1824 variable number of arguments. 1825 1826 CUM is as above. 1827 1828 MODE and TYPE are the mode and type of the current parameter. 1829 1830 PRETEND_SIZE is a variable that should be set to the amount of stack 1831 that must be pushed by the prolog to pretend that our caller pushed 1832 it. 1833 1834 Normally, this macro will push all remaining incoming registers on the 1835 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1836 1837#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1838 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ 1839 (NO_RTL)) 1840 1841/* Implement `va_start' for varargs and stdarg. */ 1842#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ 1843 ix86_va_start (VALIST, NEXTARG) 1844 1845/* Implement `va_arg'. */ 1846#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ 1847 ix86_va_arg ((VALIST), (TYPE)) 1848 1849#define TARGET_ASM_FILE_END ix86_file_end 1850#define NEED_INDICATE_EXEC_STACK 0 1851 1852/* Output assembler code to FILE to increment profiler label # LABELNO 1853 for profiling a function entry. */ 1854 1855#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1856 1857#define MCOUNT_NAME "_mcount" 1858 1859#define PROFILE_COUNT_REGISTER "edx" 1860 1861/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1862 the stack pointer does not matter. The value is tested only in 1863 functions that have frame pointers. 1864 No definition is equivalent to always zero. */ 1865/* Note on the 386 it might be more efficient not to define this since 1866 we have to restore it ourselves from the frame pointer, in order to 1867 use pop */ 1868 1869#define EXIT_IGNORE_STACK 1 1870 1871/* Output assembler code for a block containing the constant parts 1872 of a trampoline, leaving space for the variable parts. */ 1873 1874/* On the 386, the trampoline contains two instructions: 1875 mov #STATIC,ecx 1876 jmp FUNCTION 1877 The trampoline is generated entirely at runtime. The operand of JMP 1878 is the address of FUNCTION relative to the instruction following the 1879 JMP (which is 5 bytes long). */ 1880 1881/* Length in units of the trampoline for entering a nested function. */ 1882 1883#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1884 1885/* Emit RTL insns to initialize the variable parts of a trampoline. 1886 FNADDR is an RTX for the address of the function's pure code. 1887 CXT is an RTX for the static chain value for the function. */ 1888 1889#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1890 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1891 1892/* Definitions for register eliminations. 1893 1894 This is an array of structures. Each structure initializes one pair 1895 of eliminable registers. The "from" register number is given first, 1896 followed by "to". Eliminations of the same "from" register are listed 1897 in order of preference. 1898 1899 There are two registers that can always be eliminated on the i386. 1900 The frame pointer and the arg pointer can be replaced by either the 1901 hard frame pointer or to the stack pointer, depending upon the 1902 circumstances. The hard frame pointer is not used before reload and 1903 so it is not eligible for elimination. */ 1904 1905#define ELIMINABLE_REGS \ 1906{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1907 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1908 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1909 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1910 1911/* Given FROM and TO register numbers, say whether this elimination is 1912 allowed. Frame pointer elimination is automatically handled. 1913 1914 All other eliminations are valid. */ 1915 1916#define CAN_ELIMINATE(FROM, TO) \ 1917 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1918 1919/* Define the offset between two registers, one to be eliminated, and the other 1920 its replacement, at the start of a routine. */ 1921 1922#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1923 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1924 1925/* Addressing modes, and classification of registers for them. */ 1926 1927/* Macros to check register numbers against specific register classes. */ 1928 1929/* These assume that REGNO is a hard or pseudo reg number. 1930 They give nonzero only if REGNO is a hard reg of the suitable class 1931 or a pseudo reg currently allocated to a suitable hard reg. 1932 Since they use reg_renumber, they are safe only once reg_renumber 1933 has been allocated, which happens in local-alloc.c. */ 1934 1935#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1936 ((REGNO) < STACK_POINTER_REGNUM \ 1937 || (REGNO >= FIRST_REX_INT_REG \ 1938 && (REGNO) <= LAST_REX_INT_REG) \ 1939 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1940 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1941 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1942 1943#define REGNO_OK_FOR_BASE_P(REGNO) \ 1944 ((REGNO) <= STACK_POINTER_REGNUM \ 1945 || (REGNO) == ARG_POINTER_REGNUM \ 1946 || (REGNO) == FRAME_POINTER_REGNUM \ 1947 || (REGNO >= FIRST_REX_INT_REG \ 1948 && (REGNO) <= LAST_REX_INT_REG) \ 1949 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1950 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1951 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1952 1953#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1954 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1955#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1956 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1957 1958/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1959 and check its validity for a certain class. 1960 We have two alternate definitions for each of them. 1961 The usual definition accepts all pseudo regs; the other rejects 1962 them unless they have been allocated suitable hard regs. 1963 The symbol REG_OK_STRICT causes the latter definition to be used. 1964 1965 Most source files want to accept pseudo regs in the hope that 1966 they will get allocated to the class that the insn wants them to be in. 1967 Source files for reload pass need to be strict. 1968 After reload, it makes no difference, since pseudo regs have 1969 been eliminated by then. */ 1970 1971 1972/* Non strict versions, pseudos are ok */ 1973#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1974 (REGNO (X) < STACK_POINTER_REGNUM \ 1975 || (REGNO (X) >= FIRST_REX_INT_REG \ 1976 && REGNO (X) <= LAST_REX_INT_REG) \ 1977 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1978 1979#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1980 (REGNO (X) <= STACK_POINTER_REGNUM \ 1981 || REGNO (X) == ARG_POINTER_REGNUM \ 1982 || REGNO (X) == FRAME_POINTER_REGNUM \ 1983 || (REGNO (X) >= FIRST_REX_INT_REG \ 1984 && REGNO (X) <= LAST_REX_INT_REG) \ 1985 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1986 1987/* Strict versions, hard registers only */ 1988#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1989#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1990 1991#ifndef REG_OK_STRICT 1992#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1993#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1994 1995#else 1996#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1997#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1998#endif 1999 2000/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2001 that is a valid memory address for an instruction. 2002 The MODE argument is the machine mode for the MEM expression 2003 that wants to use this address. 2004 2005 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 2006 except for CONSTANT_ADDRESS_P which is usually machine-independent. 2007 2008 See legitimize_pic_address in i386.c for details as to what 2009 constitutes a legitimate address when -fpic is used. */ 2010 2011#define MAX_REGS_PER_ADDRESS 2 2012 2013#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 2014 2015/* Nonzero if the constant value X is a legitimate general operand. 2016 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2017 2018#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 2019 2020#ifdef REG_OK_STRICT 2021#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2022do { \ 2023 if (legitimate_address_p ((MODE), (X), 1)) \ 2024 goto ADDR; \ 2025} while (0) 2026 2027#else 2028#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2029do { \ 2030 if (legitimate_address_p ((MODE), (X), 0)) \ 2031 goto ADDR; \ 2032} while (0) 2033 2034#endif 2035 2036/* If defined, a C expression to determine the base term of address X. 2037 This macro is used in only one place: `find_base_term' in alias.c. 2038 2039 It is always safe for this macro to not be defined. It exists so 2040 that alias analysis can understand machine-dependent addresses. 2041 2042 The typical use of this macro is to handle addresses containing 2043 a label_ref or symbol_ref within an UNSPEC. */ 2044 2045#define FIND_BASE_TERM(X) ix86_find_base_term (X) 2046 2047/* Try machine-dependent ways of modifying an illegitimate address 2048 to be legitimate. If we find one, return the new, valid address. 2049 This macro is used in only one place: `memory_address' in explow.c. 2050 2051 OLDX is the address as it was before break_out_memory_refs was called. 2052 In some cases it is useful to look at this to decide what needs to be done. 2053 2054 MODE and WIN are passed so that this macro can use 2055 GO_IF_LEGITIMATE_ADDRESS. 2056 2057 It is always safe for this macro to do nothing. It exists to recognize 2058 opportunities to optimize the output. 2059 2060 For the 80386, we handle X+REG by loading X into a register R and 2061 using R+REG. R will go in a general reg and indexing will be used. 2062 However, if REG is a broken-out memory address or multiplication, 2063 nothing needs to be done because REG can certainly go in a general reg. 2064 2065 When -fpic is used, special handling is needed for symbolic references. 2066 See comments by legitimize_pic_address in i386.c for details. */ 2067 2068#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2069do { \ 2070 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 2071 if (memory_address_p ((MODE), (X))) \ 2072 goto WIN; \ 2073} while (0) 2074 2075#define REWRITE_ADDRESS(X) rewrite_address (X) 2076 2077/* Nonzero if the constant value X is a legitimate general operand 2078 when generating PIC code. It is given that flag_pic is on and 2079 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2080 2081#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 2082 2083#define SYMBOLIC_CONST(X) \ 2084 (GET_CODE (X) == SYMBOL_REF \ 2085 || GET_CODE (X) == LABEL_REF \ 2086 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 2087 2088/* Go to LABEL if ADDR (a legitimate address expression) 2089 has an effect that depends on the machine mode it is used for. 2090 On the 80386, only postdecrement and postincrement address depend thus 2091 (the amount of decrement or increment being the length of the operand). */ 2092#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2093do { \ 2094 if (GET_CODE (ADDR) == POST_INC \ 2095 || GET_CODE (ADDR) == POST_DEC) \ 2096 goto LABEL; \ 2097} while (0) 2098 2099/* Codes for all the SSE/MMX builtins. */ 2100enum ix86_builtins 2101{ 2102 IX86_BUILTIN_ADDPS, 2103 IX86_BUILTIN_ADDSS, 2104 IX86_BUILTIN_DIVPS, 2105 IX86_BUILTIN_DIVSS, 2106 IX86_BUILTIN_MULPS, 2107 IX86_BUILTIN_MULSS, 2108 IX86_BUILTIN_SUBPS, 2109 IX86_BUILTIN_SUBSS, 2110 2111 IX86_BUILTIN_CMPEQPS, 2112 IX86_BUILTIN_CMPLTPS, 2113 IX86_BUILTIN_CMPLEPS, 2114 IX86_BUILTIN_CMPGTPS, 2115 IX86_BUILTIN_CMPGEPS, 2116 IX86_BUILTIN_CMPNEQPS, 2117 IX86_BUILTIN_CMPNLTPS, 2118 IX86_BUILTIN_CMPNLEPS, 2119 IX86_BUILTIN_CMPNGTPS, 2120 IX86_BUILTIN_CMPNGEPS, 2121 IX86_BUILTIN_CMPORDPS, 2122 IX86_BUILTIN_CMPUNORDPS, 2123 IX86_BUILTIN_CMPNEPS, 2124 IX86_BUILTIN_CMPEQSS, 2125 IX86_BUILTIN_CMPLTSS, 2126 IX86_BUILTIN_CMPLESS, 2127 IX86_BUILTIN_CMPNEQSS, 2128 IX86_BUILTIN_CMPNLTSS, 2129 IX86_BUILTIN_CMPNLESS, 2130 IX86_BUILTIN_CMPORDSS, 2131 IX86_BUILTIN_CMPUNORDSS, 2132 IX86_BUILTIN_CMPNESS, 2133 2134 IX86_BUILTIN_COMIEQSS, 2135 IX86_BUILTIN_COMILTSS, 2136 IX86_BUILTIN_COMILESS, 2137 IX86_BUILTIN_COMIGTSS, 2138 IX86_BUILTIN_COMIGESS, 2139 IX86_BUILTIN_COMINEQSS, 2140 IX86_BUILTIN_UCOMIEQSS, 2141 IX86_BUILTIN_UCOMILTSS, 2142 IX86_BUILTIN_UCOMILESS, 2143 IX86_BUILTIN_UCOMIGTSS, 2144 IX86_BUILTIN_UCOMIGESS, 2145 IX86_BUILTIN_UCOMINEQSS, 2146 2147 IX86_BUILTIN_CVTPI2PS, 2148 IX86_BUILTIN_CVTPS2PI, 2149 IX86_BUILTIN_CVTSI2SS, 2150 IX86_BUILTIN_CVTSI642SS, 2151 IX86_BUILTIN_CVTSS2SI, 2152 IX86_BUILTIN_CVTSS2SI64, 2153 IX86_BUILTIN_CVTTPS2PI, 2154 IX86_BUILTIN_CVTTSS2SI, 2155 IX86_BUILTIN_CVTTSS2SI64, 2156 2157 IX86_BUILTIN_MAXPS, 2158 IX86_BUILTIN_MAXSS, 2159 IX86_BUILTIN_MINPS, 2160 IX86_BUILTIN_MINSS, 2161 2162 IX86_BUILTIN_LOADAPS, 2163 IX86_BUILTIN_LOADUPS, 2164 IX86_BUILTIN_STOREAPS, 2165 IX86_BUILTIN_STOREUPS, 2166 IX86_BUILTIN_LOADSS, 2167 IX86_BUILTIN_STORESS, 2168 IX86_BUILTIN_MOVSS, 2169 2170 IX86_BUILTIN_MOVHLPS, 2171 IX86_BUILTIN_MOVLHPS, 2172 IX86_BUILTIN_LOADHPS, 2173 IX86_BUILTIN_LOADLPS, 2174 IX86_BUILTIN_STOREHPS, 2175 IX86_BUILTIN_STORELPS, 2176 2177 IX86_BUILTIN_MASKMOVQ, 2178 IX86_BUILTIN_MOVMSKPS, 2179 IX86_BUILTIN_PMOVMSKB, 2180 2181 IX86_BUILTIN_MOVNTPS, 2182 IX86_BUILTIN_MOVNTQ, 2183 2184 IX86_BUILTIN_LOADDQA, 2185 IX86_BUILTIN_LOADDQU, 2186 IX86_BUILTIN_STOREDQA, 2187 IX86_BUILTIN_STOREDQU, 2188 IX86_BUILTIN_MOVQ, 2189 IX86_BUILTIN_LOADD, 2190 IX86_BUILTIN_STORED, 2191 2192 IX86_BUILTIN_CLRTI, 2193 2194 IX86_BUILTIN_PACKSSWB, 2195 IX86_BUILTIN_PACKSSDW, 2196 IX86_BUILTIN_PACKUSWB, 2197 2198 IX86_BUILTIN_PADDB, 2199 IX86_BUILTIN_PADDW, 2200 IX86_BUILTIN_PADDD, 2201 IX86_BUILTIN_PADDQ, 2202 IX86_BUILTIN_PADDSB, 2203 IX86_BUILTIN_PADDSW, 2204 IX86_BUILTIN_PADDUSB, 2205 IX86_BUILTIN_PADDUSW, 2206 IX86_BUILTIN_PSUBB, 2207 IX86_BUILTIN_PSUBW, 2208 IX86_BUILTIN_PSUBD, 2209 IX86_BUILTIN_PSUBQ, 2210 IX86_BUILTIN_PSUBSB, 2211 IX86_BUILTIN_PSUBSW, 2212 IX86_BUILTIN_PSUBUSB, 2213 IX86_BUILTIN_PSUBUSW, 2214 2215 IX86_BUILTIN_PAND, 2216 IX86_BUILTIN_PANDN, 2217 IX86_BUILTIN_POR, 2218 IX86_BUILTIN_PXOR, 2219 2220 IX86_BUILTIN_PAVGB, 2221 IX86_BUILTIN_PAVGW, 2222 2223 IX86_BUILTIN_PCMPEQB, 2224 IX86_BUILTIN_PCMPEQW, 2225 IX86_BUILTIN_PCMPEQD, 2226 IX86_BUILTIN_PCMPGTB, 2227 IX86_BUILTIN_PCMPGTW, 2228 IX86_BUILTIN_PCMPGTD, 2229 2230 IX86_BUILTIN_PEXTRW, 2231 IX86_BUILTIN_PINSRW, 2232 2233 IX86_BUILTIN_PMADDWD, 2234 2235 IX86_BUILTIN_PMAXSW, 2236 IX86_BUILTIN_PMAXUB, 2237 IX86_BUILTIN_PMINSW, 2238 IX86_BUILTIN_PMINUB, 2239 2240 IX86_BUILTIN_PMULHUW, 2241 IX86_BUILTIN_PMULHW, 2242 IX86_BUILTIN_PMULLW, 2243 2244 IX86_BUILTIN_PSADBW, 2245 IX86_BUILTIN_PSHUFW, 2246 2247 IX86_BUILTIN_PSLLW, 2248 IX86_BUILTIN_PSLLD, 2249 IX86_BUILTIN_PSLLQ, 2250 IX86_BUILTIN_PSRAW, 2251 IX86_BUILTIN_PSRAD, 2252 IX86_BUILTIN_PSRLW, 2253 IX86_BUILTIN_PSRLD, 2254 IX86_BUILTIN_PSRLQ, 2255 IX86_BUILTIN_PSLLWI, 2256 IX86_BUILTIN_PSLLDI, 2257 IX86_BUILTIN_PSLLQI, 2258 IX86_BUILTIN_PSRAWI, 2259 IX86_BUILTIN_PSRADI, 2260 IX86_BUILTIN_PSRLWI, 2261 IX86_BUILTIN_PSRLDI, 2262 IX86_BUILTIN_PSRLQI, 2263 2264 IX86_BUILTIN_PUNPCKHBW, 2265 IX86_BUILTIN_PUNPCKHWD, 2266 IX86_BUILTIN_PUNPCKHDQ, 2267 IX86_BUILTIN_PUNPCKLBW, 2268 IX86_BUILTIN_PUNPCKLWD, 2269 IX86_BUILTIN_PUNPCKLDQ, 2270 2271 IX86_BUILTIN_SHUFPS, 2272 2273 IX86_BUILTIN_RCPPS, 2274 IX86_BUILTIN_RCPSS, 2275 IX86_BUILTIN_RSQRTPS, 2276 IX86_BUILTIN_RSQRTSS, 2277 IX86_BUILTIN_SQRTPS, 2278 IX86_BUILTIN_SQRTSS, 2279 2280 IX86_BUILTIN_UNPCKHPS, 2281 IX86_BUILTIN_UNPCKLPS, 2282 2283 IX86_BUILTIN_ANDPS, 2284 IX86_BUILTIN_ANDNPS, 2285 IX86_BUILTIN_ORPS, 2286 IX86_BUILTIN_XORPS, 2287 2288 IX86_BUILTIN_EMMS, 2289 IX86_BUILTIN_LDMXCSR, 2290 IX86_BUILTIN_STMXCSR, 2291 IX86_BUILTIN_SFENCE, 2292 2293 /* 3DNow! Original */ 2294 IX86_BUILTIN_FEMMS, 2295 IX86_BUILTIN_PAVGUSB, 2296 IX86_BUILTIN_PF2ID, 2297 IX86_BUILTIN_PFACC, 2298 IX86_BUILTIN_PFADD, 2299 IX86_BUILTIN_PFCMPEQ, 2300 IX86_BUILTIN_PFCMPGE, 2301 IX86_BUILTIN_PFCMPGT, 2302 IX86_BUILTIN_PFMAX, 2303 IX86_BUILTIN_PFMIN, 2304 IX86_BUILTIN_PFMUL, 2305 IX86_BUILTIN_PFRCP, 2306 IX86_BUILTIN_PFRCPIT1, 2307 IX86_BUILTIN_PFRCPIT2, 2308 IX86_BUILTIN_PFRSQIT1, 2309 IX86_BUILTIN_PFRSQRT, 2310 IX86_BUILTIN_PFSUB, 2311 IX86_BUILTIN_PFSUBR, 2312 IX86_BUILTIN_PI2FD, 2313 IX86_BUILTIN_PMULHRW, 2314 2315 /* 3DNow! Athlon Extensions */ 2316 IX86_BUILTIN_PF2IW, 2317 IX86_BUILTIN_PFNACC, 2318 IX86_BUILTIN_PFPNACC, 2319 IX86_BUILTIN_PI2FW, 2320 IX86_BUILTIN_PSWAPDSI, 2321 IX86_BUILTIN_PSWAPDSF, 2322 2323 IX86_BUILTIN_SSE_ZERO, 2324 IX86_BUILTIN_MMX_ZERO, 2325 2326 /* SSE2 */ 2327 IX86_BUILTIN_ADDPD, 2328 IX86_BUILTIN_ADDSD, 2329 IX86_BUILTIN_DIVPD, 2330 IX86_BUILTIN_DIVSD, 2331 IX86_BUILTIN_MULPD, 2332 IX86_BUILTIN_MULSD, 2333 IX86_BUILTIN_SUBPD, 2334 IX86_BUILTIN_SUBSD, 2335 2336 IX86_BUILTIN_CMPEQPD, 2337 IX86_BUILTIN_CMPLTPD, 2338 IX86_BUILTIN_CMPLEPD, 2339 IX86_BUILTIN_CMPGTPD, 2340 IX86_BUILTIN_CMPGEPD, 2341 IX86_BUILTIN_CMPNEQPD, 2342 IX86_BUILTIN_CMPNLTPD, 2343 IX86_BUILTIN_CMPNLEPD, 2344 IX86_BUILTIN_CMPNGTPD, 2345 IX86_BUILTIN_CMPNGEPD, 2346 IX86_BUILTIN_CMPORDPD, 2347 IX86_BUILTIN_CMPUNORDPD, 2348 IX86_BUILTIN_CMPNEPD, 2349 IX86_BUILTIN_CMPEQSD, 2350 IX86_BUILTIN_CMPLTSD, 2351 IX86_BUILTIN_CMPLESD, 2352 IX86_BUILTIN_CMPNEQSD, 2353 IX86_BUILTIN_CMPNLTSD, 2354 IX86_BUILTIN_CMPNLESD, 2355 IX86_BUILTIN_CMPORDSD, 2356 IX86_BUILTIN_CMPUNORDSD, 2357 IX86_BUILTIN_CMPNESD, 2358 2359 IX86_BUILTIN_COMIEQSD, 2360 IX86_BUILTIN_COMILTSD, 2361 IX86_BUILTIN_COMILESD, 2362 IX86_BUILTIN_COMIGTSD, 2363 IX86_BUILTIN_COMIGESD, 2364 IX86_BUILTIN_COMINEQSD, 2365 IX86_BUILTIN_UCOMIEQSD, 2366 IX86_BUILTIN_UCOMILTSD, 2367 IX86_BUILTIN_UCOMILESD, 2368 IX86_BUILTIN_UCOMIGTSD, 2369 IX86_BUILTIN_UCOMIGESD, 2370 IX86_BUILTIN_UCOMINEQSD, 2371 2372 IX86_BUILTIN_MAXPD, 2373 IX86_BUILTIN_MAXSD, 2374 IX86_BUILTIN_MINPD, 2375 IX86_BUILTIN_MINSD, 2376 2377 IX86_BUILTIN_ANDPD, 2378 IX86_BUILTIN_ANDNPD, 2379 IX86_BUILTIN_ORPD, 2380 IX86_BUILTIN_XORPD, 2381 2382 IX86_BUILTIN_SQRTPD, 2383 IX86_BUILTIN_SQRTSD, 2384 2385 IX86_BUILTIN_UNPCKHPD, 2386 IX86_BUILTIN_UNPCKLPD, 2387 2388 IX86_BUILTIN_SHUFPD, 2389 2390 IX86_BUILTIN_LOADAPD, 2391 IX86_BUILTIN_LOADUPD, 2392 IX86_BUILTIN_STOREAPD, 2393 IX86_BUILTIN_STOREUPD, 2394 IX86_BUILTIN_LOADSD, 2395 IX86_BUILTIN_STORESD, 2396 IX86_BUILTIN_MOVSD, 2397 2398 IX86_BUILTIN_LOADHPD, 2399 IX86_BUILTIN_LOADLPD, 2400 IX86_BUILTIN_STOREHPD, 2401 IX86_BUILTIN_STORELPD, 2402 2403 IX86_BUILTIN_CVTDQ2PD, 2404 IX86_BUILTIN_CVTDQ2PS, 2405 2406 IX86_BUILTIN_CVTPD2DQ, 2407 IX86_BUILTIN_CVTPD2PI, 2408 IX86_BUILTIN_CVTPD2PS, 2409 IX86_BUILTIN_CVTTPD2DQ, 2410 IX86_BUILTIN_CVTTPD2PI, 2411 2412 IX86_BUILTIN_CVTPI2PD, 2413 IX86_BUILTIN_CVTSI2SD, 2414 IX86_BUILTIN_CVTSI642SD, 2415 2416 IX86_BUILTIN_CVTSD2SI, 2417 IX86_BUILTIN_CVTSD2SI64, 2418 IX86_BUILTIN_CVTSD2SS, 2419 IX86_BUILTIN_CVTSS2SD, 2420 IX86_BUILTIN_CVTTSD2SI, 2421 IX86_BUILTIN_CVTTSD2SI64, 2422 2423 IX86_BUILTIN_CVTPS2DQ, 2424 IX86_BUILTIN_CVTPS2PD, 2425 IX86_BUILTIN_CVTTPS2DQ, 2426 2427 IX86_BUILTIN_MOVNTI, 2428 IX86_BUILTIN_MOVNTPD, 2429 IX86_BUILTIN_MOVNTDQ, 2430 2431 IX86_BUILTIN_SETPD1, 2432 IX86_BUILTIN_SETPD, 2433 IX86_BUILTIN_CLRPD, 2434 IX86_BUILTIN_SETRPD, 2435 IX86_BUILTIN_LOADPD1, 2436 IX86_BUILTIN_LOADRPD, 2437 IX86_BUILTIN_STOREPD1, 2438 IX86_BUILTIN_STORERPD, 2439 2440 /* SSE2 MMX */ 2441 IX86_BUILTIN_MASKMOVDQU, 2442 IX86_BUILTIN_MOVMSKPD, 2443 IX86_BUILTIN_PMOVMSKB128, 2444 IX86_BUILTIN_MOVQ2DQ, 2445 IX86_BUILTIN_MOVDQ2Q, 2446 2447 IX86_BUILTIN_PACKSSWB128, 2448 IX86_BUILTIN_PACKSSDW128, 2449 IX86_BUILTIN_PACKUSWB128, 2450 2451 IX86_BUILTIN_PADDB128, 2452 IX86_BUILTIN_PADDW128, 2453 IX86_BUILTIN_PADDD128, 2454 IX86_BUILTIN_PADDQ128, 2455 IX86_BUILTIN_PADDSB128, 2456 IX86_BUILTIN_PADDSW128, 2457 IX86_BUILTIN_PADDUSB128, 2458 IX86_BUILTIN_PADDUSW128, 2459 IX86_BUILTIN_PSUBB128, 2460 IX86_BUILTIN_PSUBW128, 2461 IX86_BUILTIN_PSUBD128, 2462 IX86_BUILTIN_PSUBQ128, 2463 IX86_BUILTIN_PSUBSB128, 2464 IX86_BUILTIN_PSUBSW128, 2465 IX86_BUILTIN_PSUBUSB128, 2466 IX86_BUILTIN_PSUBUSW128, 2467 2468 IX86_BUILTIN_PAND128, 2469 IX86_BUILTIN_PANDN128, 2470 IX86_BUILTIN_POR128, 2471 IX86_BUILTIN_PXOR128, 2472 2473 IX86_BUILTIN_PAVGB128, 2474 IX86_BUILTIN_PAVGW128, 2475 2476 IX86_BUILTIN_PCMPEQB128, 2477 IX86_BUILTIN_PCMPEQW128, 2478 IX86_BUILTIN_PCMPEQD128, 2479 IX86_BUILTIN_PCMPGTB128, 2480 IX86_BUILTIN_PCMPGTW128, 2481 IX86_BUILTIN_PCMPGTD128, 2482 2483 IX86_BUILTIN_PEXTRW128, 2484 IX86_BUILTIN_PINSRW128, 2485 2486 IX86_BUILTIN_PMADDWD128, 2487 2488 IX86_BUILTIN_PMAXSW128, 2489 IX86_BUILTIN_PMAXUB128, 2490 IX86_BUILTIN_PMINSW128, 2491 IX86_BUILTIN_PMINUB128, 2492 2493 IX86_BUILTIN_PMULUDQ, 2494 IX86_BUILTIN_PMULUDQ128, 2495 IX86_BUILTIN_PMULHUW128, 2496 IX86_BUILTIN_PMULHW128, 2497 IX86_BUILTIN_PMULLW128, 2498 2499 IX86_BUILTIN_PSADBW128, 2500 IX86_BUILTIN_PSHUFHW, 2501 IX86_BUILTIN_PSHUFLW, 2502 IX86_BUILTIN_PSHUFD, 2503 2504 IX86_BUILTIN_PSLLW128, 2505 IX86_BUILTIN_PSLLD128, 2506 IX86_BUILTIN_PSLLQ128, 2507 IX86_BUILTIN_PSRAW128, 2508 IX86_BUILTIN_PSRAD128, 2509 IX86_BUILTIN_PSRLW128, 2510 IX86_BUILTIN_PSRLD128, 2511 IX86_BUILTIN_PSRLQ128, 2512 IX86_BUILTIN_PSLLDQI128, 2513 IX86_BUILTIN_PSLLWI128, 2514 IX86_BUILTIN_PSLLDI128, 2515 IX86_BUILTIN_PSLLQI128, 2516 IX86_BUILTIN_PSRAWI128, 2517 IX86_BUILTIN_PSRADI128, 2518 IX86_BUILTIN_PSRLDQI128, 2519 IX86_BUILTIN_PSRLWI128, 2520 IX86_BUILTIN_PSRLDI128, 2521 IX86_BUILTIN_PSRLQI128, 2522 2523 IX86_BUILTIN_PUNPCKHBW128, 2524 IX86_BUILTIN_PUNPCKHWD128, 2525 IX86_BUILTIN_PUNPCKHDQ128, 2526 IX86_BUILTIN_PUNPCKHQDQ128, 2527 IX86_BUILTIN_PUNPCKLBW128, 2528 IX86_BUILTIN_PUNPCKLWD128, 2529 IX86_BUILTIN_PUNPCKLDQ128, 2530 IX86_BUILTIN_PUNPCKLQDQ128, 2531 2532 IX86_BUILTIN_CLFLUSH, 2533 IX86_BUILTIN_MFENCE, 2534 IX86_BUILTIN_LFENCE, 2535 2536 /* Prescott New Instructions. */ 2537 IX86_BUILTIN_ADDSUBPS, 2538 IX86_BUILTIN_HADDPS, 2539 IX86_BUILTIN_HSUBPS, 2540 IX86_BUILTIN_MOVSHDUP, 2541 IX86_BUILTIN_MOVSLDUP, 2542 IX86_BUILTIN_ADDSUBPD, 2543 IX86_BUILTIN_HADDPD, 2544 IX86_BUILTIN_HSUBPD, 2545 IX86_BUILTIN_LOADDDUP, 2546 IX86_BUILTIN_MOVDDUP, 2547 IX86_BUILTIN_LDDQU, 2548 2549 IX86_BUILTIN_MONITOR, 2550 IX86_BUILTIN_MWAIT, 2551 2552 IX86_BUILTIN_MAX 2553}; 2554 2555/* Max number of args passed in registers. If this is more than 3, we will 2556 have problems with ebx (register #4), since it is a caller save register and 2557 is also used as the pic register in ELF. So for now, don't allow more than 2558 3 registers to be passed in registers. */ 2559 2560#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 2561 2562#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) 2563 2564#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 2565 2566 2567/* Specify the machine mode that this machine uses 2568 for the index in the tablejump instruction. */ 2569#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 2570 2571/* Define as C expression which evaluates to nonzero if the tablejump 2572 instruction expects the table to contain offsets from the address of the 2573 table. 2574 Do not define this if the table should contain absolute addresses. */ 2575/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2576 2577/* Define this as 1 if `char' should by default be signed; else as 0. */ 2578#define DEFAULT_SIGNED_CHAR 1 2579 2580/* Number of bytes moved into a data cache for a single prefetch operation. */ 2581#define PREFETCH_BLOCK ix86_cost->prefetch_block 2582 2583/* Number of prefetch operations that can be done in parallel. */ 2584#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 2585 2586/* Max number of bytes we can move from memory to memory 2587 in one reasonably fast instruction. */ 2588#define MOVE_MAX 16 2589 2590/* MOVE_MAX_PIECES is the number of bytes at a time which we can 2591 move efficiently, as opposed to MOVE_MAX which is the maximum 2592 number of bytes we can move with a single instruction. */ 2593#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 2594 2595/* If a memory-to-memory move would take MOVE_RATIO or more simple 2596 move-instruction pairs, we will do a movstr or libcall instead. 2597 Increasing the value will always make code faster, but eventually 2598 incurs high cost in increased code size. 2599 2600 If you don't define this, a reasonable default is used. */ 2601 2602#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 2603 2604/* Define if shifts truncate the shift count 2605 which implies one can omit a sign-extension or zero-extension 2606 of a shift count. */ 2607/* On i386, shifts do truncate the count. But bit opcodes don't. */ 2608 2609/* #define SHIFT_COUNT_TRUNCATED */ 2610 2611/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2612 is done just by pretending it is already truncated. */ 2613#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2614 2615/* When a prototype says `char' or `short', really pass an `int'. 2616 (The 386 can't easily push less than an int.) */ 2617 2618#define PROMOTE_PROTOTYPES 1 2619 2620/* A macro to update M and UNSIGNEDP when an object whose type is 2621 TYPE and which has the specified mode and signedness is to be 2622 stored in a register. This macro is only called when TYPE is a 2623 scalar type. 2624 2625 On i386 it is sometimes useful to promote HImode and QImode 2626 quantities to SImode. The choice depends on target type. */ 2627 2628#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2629do { \ 2630 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 2631 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 2632 (MODE) = SImode; \ 2633} while (0) 2634 2635/* Specify the machine mode that pointers have. 2636 After generation of rtl, the compiler makes no further distinction 2637 between pointers and any other objects of this machine mode. */ 2638#define Pmode (TARGET_64BIT ? DImode : SImode) 2639 2640/* A function address in a call instruction 2641 is a byte address (for indexing purposes) 2642 so give the MEM rtx a byte's mode. */ 2643#define FUNCTION_MODE QImode 2644 2645/* A C expression for the cost of moving data from a register in class FROM to 2646 one in class TO. The classes are expressed using the enumeration values 2647 such as `GENERAL_REGS'. A value of 2 is the default; other values are 2648 interpreted relative to that. 2649 2650 It is not required that the cost always equal 2 when FROM is the same as TO; 2651 on some machines it is expensive to move between registers if they are not 2652 general registers. */ 2653 2654#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2655 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 2656 2657/* A C expression for the cost of moving data of mode M between a 2658 register and memory. A value of 2 is the default; this cost is 2659 relative to those in `REGISTER_MOVE_COST'. 2660 2661 If moving between registers and memory is more expensive than 2662 between two registers, you should define this macro to express the 2663 relative cost. */ 2664 2665#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 2666 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 2667 2668/* A C expression for the cost of a branch instruction. A value of 1 2669 is the default; other values are interpreted relative to that. */ 2670 2671#define BRANCH_COST ix86_branch_cost 2672 2673/* Define this macro as a C expression which is nonzero if accessing 2674 less than a word of memory (i.e. a `char' or a `short') is no 2675 faster than accessing a word of memory, i.e., if such access 2676 require more than one instruction or if there is no difference in 2677 cost between byte and (aligned) word loads. 2678 2679 When this macro is not defined, the compiler will access a field by 2680 finding the smallest containing object; when it is defined, a 2681 fullword load will be used if alignment permits. Unless bytes 2682 accesses are faster than word accesses, using word accesses is 2683 preferable since it may eliminate subsequent memory access if 2684 subsequent accesses occur to other fields in the same word of the 2685 structure, but to different bytes. */ 2686 2687#define SLOW_BYTE_ACCESS 0 2688 2689/* Nonzero if access to memory by shorts is slow and undesirable. */ 2690#define SLOW_SHORT_ACCESS 0 2691 2692/* Define this macro to be the value 1 if unaligned accesses have a 2693 cost many times greater than aligned accesses, for example if they 2694 are emulated in a trap handler. 2695 2696 When this macro is nonzero, the compiler will act as if 2697 `STRICT_ALIGNMENT' were nonzero when generating code for block 2698 moves. This can cause significantly more instructions to be 2699 produced. Therefore, do not set this macro nonzero if unaligned 2700 accesses only add a cycle or two to the time for a memory access. 2701 2702 If the value of this macro is always zero, it need not be defined. */ 2703 2704/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2705 2706/* Define this macro if it is as good or better to call a constant 2707 function address than to call an address kept in a register. 2708 2709 Desirable on the 386 because a CALL with a constant address is 2710 faster than one with a register address. */ 2711 2712#define NO_FUNCTION_CSE 2713 2714/* Define this macro if it is as good or better for a function to call 2715 itself with an explicit address than to call an address kept in a 2716 register. */ 2717 2718#define NO_RECURSIVE_FUNCTION_CSE 2719 2720/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2721 return the mode to be used for the comparison. 2722 2723 For floating-point equality comparisons, CCFPEQmode should be used. 2724 VOIDmode should be used in all other cases. 2725 2726 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2727 possible, to allow for more combinations. */ 2728 2729#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2730 2731/* Return nonzero if MODE implies a floating point inequality can be 2732 reversed. */ 2733 2734#define REVERSIBLE_CC_MODE(MODE) 1 2735 2736/* A C expression whose value is reversed condition code of the CODE for 2737 comparison done in CC_MODE mode. */ 2738#define REVERSE_CONDITION(CODE, MODE) \ 2739 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ 2740 : reverse_condition_maybe_unordered (CODE)) 2741 2742 2743/* Control the assembler format that we output, to the extent 2744 this does not vary between assemblers. */ 2745 2746/* How to refer to registers in assembler output. 2747 This sequence is indexed by compiler's hard-register-number (see above). */ 2748 2749/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" 2750 For non floating point regs, the following are the HImode names. 2751 2752 For float regs, the stack top is sometimes referred to as "%st(0)" 2753 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ 2754 2755#define HI_REGISTER_NAMES \ 2756{"ax","dx","cx","bx","si","di","bp","sp", \ 2757 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 2758 "argp", "flags", "fpsr", "dirflag", "frame", \ 2759 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2760 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 2761 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2762 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 2763 2764#define REGISTER_NAMES HI_REGISTER_NAMES 2765 2766/* Table of additional register names to use in user input. */ 2767 2768#define ADDITIONAL_REGISTER_NAMES \ 2769{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2770 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2771 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2772 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2773 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2774 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2775 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ 2776 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } 2777 2778/* Note we are omitting these since currently I don't know how 2779to get gcc to use these, since they want the same but different 2780number as al, and ax. 2781*/ 2782 2783#define QI_REGISTER_NAMES \ 2784{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2785 2786/* These parallel the array above, and can be used to access bits 8:15 2787 of regs 0 through 3. */ 2788 2789#define QI_HIGH_REGISTER_NAMES \ 2790{"ah", "dh", "ch", "bh", } 2791 2792/* How to renumber registers for dbx and gdb. */ 2793 2794#define DBX_REGISTER_NUMBER(N) \ 2795 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2796 2797extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2798extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2799extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2800 2801/* Before the prologue, RA is at 0(%esp). */ 2802#define INCOMING_RETURN_ADDR_RTX \ 2803 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2804 2805/* After the prologue, RA is at -4(AP) in the current frame. */ 2806#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2807 ((COUNT) == 0 \ 2808 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2809 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2810 2811/* PC is dbx register 8; let's use that column for RA. */ 2812#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2813 2814/* Before the prologue, the top of the frame is at 4(%esp). */ 2815#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2816 2817/* Describe how we implement __builtin_eh_return. */ 2818#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2819#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2820 2821 2822/* Select a format to encode pointers in exception handling data. CODE 2823 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2824 true if the symbol may be affected by dynamic relocations. 2825 2826 ??? All x86 object file formats are capable of representing this. 2827 After all, the relocation needed is the same as for the call insn. 2828 Whether or not a particular assembler allows us to enter such, I 2829 guess we'll have to see. */ 2830#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2831 (flag_pic \ 2832 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 2833 : DW_EH_PE_absptr) 2834 2835/* This is how to output an insn to push a register on the stack. 2836 It need not be very fast code. */ 2837 2838#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2839do { \ 2840 if (TARGET_64BIT) \ 2841 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2842 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2843 else \ 2844 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2845} while (0) 2846 2847/* This is how to output an insn to pop a register from the stack. 2848 It need not be very fast code. */ 2849 2850#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2851do { \ 2852 if (TARGET_64BIT) \ 2853 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2854 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2855 else \ 2856 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2857} while (0) 2858 2859/* This is how to output an element of a case-vector that is absolute. */ 2860 2861#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2862 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2863 2864/* This is how to output an element of a case-vector that is relative. */ 2865 2866#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2867 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2868 2869/* Under some conditions we need jump tables in the text section, because 2870 the assembler cannot handle label differences between sections. */ 2871 2872#define JUMP_TABLES_IN_TEXT_SECTION \ 2873 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 2874 2875/* A C statement that outputs an address constant appropriate to 2876 for DWARF debugging. */ 2877 2878#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ 2879 i386_dwarf_output_addr_const ((FILE), (X)) 2880 2881/* Emit a dtp-relative reference to a TLS variable. */ 2882 2883#ifdef HAVE_AS_TLS 2884#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ 2885 i386_output_dwarf_dtprel (FILE, SIZE, X) 2886#endif 2887 2888/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2889 and switch back. For x86 we do this only to save a few bytes that 2890 would otherwise be unused in the text section. */ 2891#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2892 asm (SECTION_OP "\n\t" \ 2893 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2894 TEXT_SECTION_ASM_OP); 2895 2896/* Print operand X (an rtx) in assembler syntax to file FILE. 2897 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2898 Effect of various CODE letters is described in i386.c near 2899 print_operand function. */ 2900 2901#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2902 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') 2903 2904#define PRINT_OPERAND(FILE, X, CODE) \ 2905 print_operand ((FILE), (X), (CODE)) 2906 2907#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2908 print_operand_address ((FILE), (ADDR)) 2909 2910#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2911do { \ 2912 if (! output_addr_const_extra (FILE, (X))) \ 2913 goto FAIL; \ 2914} while (0); 2915 2916/* a letter which is not needed by the normal asm syntax, which 2917 we can use for operand syntax in the extended asm */ 2918 2919#define ASM_OPERAND_LETTER '#' 2920#define RET return "" 2921#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 2922 2923/* Define the codes that are matched by predicates in i386.c. */ 2924 2925#define PREDICATE_CODES \ 2926 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ 2927 SYMBOL_REF, LABEL_REF, CONST}}, \ 2928 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 2929 SYMBOL_REF, LABEL_REF, CONST}}, \ 2930 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ 2931 SYMBOL_REF, LABEL_REF, CONST}}, \ 2932 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 2933 SYMBOL_REF, LABEL_REF, CONST}}, \ 2934 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 2935 SYMBOL_REF, LABEL_REF, CONST}}, \ 2936 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 2937 SYMBOL_REF, LABEL_REF, CONST}}, \ 2938 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 2939 SYMBOL_REF, LABEL_REF}}, \ 2940 {"shiftdi_operand", {SUBREG, REG, MEM}}, \ 2941 {"const_int_1_31_operand", {CONST_INT}}, \ 2942 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 2943 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 2944 LABEL_REF, SUBREG, REG, MEM}}, \ 2945 {"pic_symbolic_operand", {CONST}}, \ 2946 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ 2947 {"sibcall_insn_operand", {REG, SUBREG, SYMBOL_REF}}, \ 2948 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ 2949 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ 2950 {"const1_operand", {CONST_INT}}, \ 2951 {"const248_operand", {CONST_INT}}, \ 2952 {"const_0_to_3_operand", {CONST_INT}}, \ 2953 {"const_0_to_7_operand", {CONST_INT}}, \ 2954 {"const_0_to_15_operand", {CONST_INT}}, \ 2955 {"const_0_to_255_operand", {CONST_INT}}, \ 2956 {"incdec_operand", {CONST_INT}}, \ 2957 {"mmx_reg_operand", {REG}}, \ 2958 {"reg_no_sp_operand", {SUBREG, REG}}, \ 2959 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 2960 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ 2961 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ 2962 {"index_register_operand", {SUBREG, REG}}, \ 2963 {"flags_reg_operand", {REG}}, \ 2964 {"q_regs_operand", {SUBREG, REG}}, \ 2965 {"non_q_regs_operand", {SUBREG, REG}}, \ 2966 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ 2967 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ 2968 GE, UNGE, LTGT, UNEQ}}, \ 2969 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ 2970 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ 2971 }}, \ 2972 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ 2973 GTU, UNORDERED, ORDERED, UNLE, UNLT, \ 2974 UNGE, UNGT, LTGT, UNEQ }}, \ 2975 {"ix86_carry_flag_operator", {LTU, LT, UNLT, GT, UNGT, LE, UNLE, \ 2976 GE, UNGE, LTGT, UNEQ}}, \ 2977 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ 2978 {"ext_register_operand", {SUBREG, REG}}, \ 2979 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ 2980 {"mult_operator", {MULT}}, \ 2981 {"div_operator", {DIV}}, \ 2982 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ 2983 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ 2984 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ 2985 LSHIFTRT, ROTATERT}}, \ 2986 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ 2987 {"memory_displacement_operand", {MEM}}, \ 2988 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 2989 LABEL_REF, SUBREG, REG, MEM, AND}}, \ 2990 {"long_memory_operand", {MEM}}, \ 2991 {"tls_symbolic_operand", {SYMBOL_REF}}, \ 2992 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \ 2993 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \ 2994 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \ 2995 {"local_exec_symbolic_operand", {SYMBOL_REF}}, \ 2996 {"any_fp_register_operand", {REG}}, \ 2997 {"register_and_not_any_fp_reg_operand", {REG}}, \ 2998 {"fp_register_operand", {REG}}, \ 2999 {"register_and_not_fp_reg_operand", {REG}}, \ 3000 {"zero_extended_scalar_load_operand", {MEM}}, \ 3001 {"vector_move_operand", {CONST_VECTOR, SUBREG, REG, MEM}}, \ 3002 {"no_seg_address_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3003 LABEL_REF, SUBREG, REG, MEM, PLUS, MULT}}, \ 3004 {"compare_operator", {COMPARE}}, 3005 3006/* A list of predicates that do special things with modes, and so 3007 should not elicit warnings for VOIDmode match_operand. */ 3008 3009#define SPECIAL_MODE_PREDICATES \ 3010 "ext_register_operand", 3011 3012/* Which processor to schedule for. The cpu attribute defines a list that 3013 mirrors this list, so changes to i386.md must be made at the same time. */ 3014 3015enum processor_type 3016{ 3017 PROCESSOR_I386, /* 80386 */ 3018 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 3019 PROCESSOR_PENTIUM, 3020 PROCESSOR_PENTIUMPRO, 3021 PROCESSOR_K6, 3022 PROCESSOR_ATHLON, 3023 PROCESSOR_PENTIUM4, 3024 PROCESSOR_K8, 3025 PROCESSOR_max 3026}; 3027 3028extern enum processor_type ix86_tune; 3029extern const char *ix86_tune_string; 3030 3031extern enum processor_type ix86_arch; 3032extern const char *ix86_arch_string; 3033 3034enum fpmath_unit 3035{ 3036 FPMATH_387 = 1, 3037 FPMATH_SSE = 2 3038}; 3039 3040extern enum fpmath_unit ix86_fpmath; 3041extern const char *ix86_fpmath_string; 3042 3043enum tls_dialect 3044{ 3045 TLS_DIALECT_GNU, 3046 TLS_DIALECT_SUN 3047}; 3048 3049extern enum tls_dialect ix86_tls_dialect; 3050extern const char *ix86_tls_dialect_string; 3051 3052enum cmodel { 3053 CM_32, /* The traditional 32-bit ABI. */ 3054 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 3055 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 3056 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 3057 CM_LARGE, /* No assumptions. */ 3058 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */ 3059}; 3060 3061extern enum cmodel ix86_cmodel; 3062extern const char *ix86_cmodel_string; 3063 3064/* Size of the RED_ZONE area. */ 3065#define RED_ZONE_SIZE 128 3066/* Reserved area of the red zone for temporaries. */ 3067#define RED_ZONE_RESERVE 8 3068 3069enum asm_dialect { 3070 ASM_ATT, 3071 ASM_INTEL 3072}; 3073 3074extern const char *ix86_asm_string; 3075extern enum asm_dialect ix86_asm_dialect; 3076 3077extern int ix86_regparm; 3078extern const char *ix86_regparm_string; 3079 3080extern int ix86_preferred_stack_boundary; 3081extern const char *ix86_preferred_stack_boundary_string; 3082 3083extern int ix86_branch_cost; 3084extern const char *ix86_branch_cost_string; 3085 3086extern const char *ix86_debug_arg_string; 3087extern const char *ix86_debug_addr_string; 3088 3089/* Obsoleted by -f options. Remove before 3.2 ships. */ 3090extern const char *ix86_align_loops_string; 3091extern const char *ix86_align_jumps_string; 3092extern const char *ix86_align_funcs_string; 3093 3094/* Smallest class containing REGNO. */ 3095extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 3096 3097extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 3098extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 3099 3100/* To properly truncate FP values into integers, we need to set i387 control 3101 word. We can't emit proper mode switching code before reload, as spills 3102 generated by reload may truncate values incorrectly, but we still can avoid 3103 redundant computation of new control word by the mode switching pass. 3104 The fldcw instructions are still emitted redundantly, but this is probably 3105 not going to be noticeable problem, as most CPUs do have fast path for 3106 the sequence. 3107 3108 The machinery is to emit simple truncation instructions and split them 3109 before reload to instructions having USEs of two memory locations that 3110 are filled by this code to old and new control word. 3111 3112 Post-reload pass may be later used to eliminate the redundant fildcw if 3113 needed. */ 3114 3115enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; 3116 3117/* Define this macro if the port needs extra instructions inserted 3118 for mode switching in an optimizing compilation. */ 3119 3120#define OPTIMIZE_MODE_SWITCHING(ENTITY) ix86_optimize_mode_switching 3121 3122/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 3123 initializer for an array of integers. Each initializer element N 3124 refers to an entity that needs mode switching, and specifies the 3125 number of different modes that might need to be set for this 3126 entity. The position of the initializer in the initializer - 3127 starting counting at zero - determines the integer that is used to 3128 refer to the mode-switched entity in question. */ 3129 3130#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } 3131 3132/* ENTITY is an integer specifying a mode-switched entity. If 3133 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 3134 return an integer value not larger than the corresponding element 3135 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 3136 must be switched into prior to the execution of INSN. */ 3137 3138#define MODE_NEEDED(ENTITY, I) \ 3139 (GET_CODE (I) == CALL_INSN \ 3140 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ 3141 || GET_CODE (PATTERN (I)) == ASM_INPUT))\ 3142 ? FP_CW_UNINITIALIZED \ 3143 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ 3144 ? FP_CW_ANY \ 3145 : FP_CW_STORED) 3146 3147/* This macro specifies the order in which modes for ENTITY are 3148 processed. 0 is the highest priority. */ 3149 3150#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 3151 3152/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 3153 is the set of hard registers live at the point where the insn(s) 3154 are to be inserted. */ 3155 3156#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3157 ((MODE) == FP_CW_STORED \ 3158 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ 3159 assign_386_stack_local (HImode, 2)), 0\ 3160 : 0) 3161 3162/* Avoid renaming of stack registers, as doing so in combination with 3163 scheduling just increases amount of live registers at time and in 3164 the turn amount of fxch instructions needed. 3165 3166 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 3167 3168#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 3169 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 3170 3171 3172#define DLL_IMPORT_EXPORT_PREFIX '#' 3173 3174#define FASTCALL_PREFIX '@' 3175 3176struct machine_function GTY(()) 3177{ 3178 struct stack_local_entry *stack_locals; 3179 const char *some_ld_name; 3180 int save_varrargs_registers; 3181 int accesses_prev_frame; 3182 int optimize_mode_switching; 3183 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to 3184 determine the style used. */ 3185 int use_fast_prologue_epilogue; 3186 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed 3187 for. */ 3188 int use_fast_prologue_epilogue_nregs; 3189}; 3190 3191#define ix86_stack_locals (cfun->machine->stack_locals) 3192#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) 3193#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 3194 3195/* Control behavior of x86_file_start. */ 3196#define X86_FILE_START_VERSION_DIRECTIVE false 3197#define X86_FILE_START_FLTUSED false 3198 3199/* 3200Local variables: 3201version-control: t 3202End: 3203*/ 3204