i386.h revision 132744
1/* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 5This file is part of GCC. 6 7GCC is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2, or (at your option) 10any later version. 11 12GCC is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with GCC; see the file COPYING. If not, write to 19the Free Software Foundation, 59 Temple Place - Suite 330, 20Boston, MA 02111-1307, USA. */ 21 22/* The purpose of this file is to define the characteristics of the i386, 23 independent of assembler syntax or operating system. 24 25 Three other files build on this one to describe a specific assembler syntax: 26 bsd386.h, att386.h, and sun386.h. 27 28 The actual tm.h file for a particular system should include 29 this file, and then the file for the appropriate assembler syntax. 30 31 Many macros that specify assembler syntax are omitted entirely from 32 this file because they really belong in the files for particular 33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 35 that start with ASM_ or end in ASM_OP. */ 36 37/* Define the specific costs for a given cpu */ 38 39struct processor_costs { 40 const int add; /* cost of an add instruction */ 41 const int lea; /* cost of a lea instruction */ 42 const int shift_var; /* variable shift costs */ 43 const int shift_const; /* constant shift costs */ 44 const int mult_init[5]; /* cost of starting a multiply 45 in QImode, HImode, SImode, DImode, TImode*/ 46 const int mult_bit; /* cost of multiply per each bit set */ 47 const int divide[5]; /* cost of a divide/mod 48 in QImode, HImode, SImode, DImode, TImode*/ 49 int movsx; /* The cost of movsx operation. */ 50 int movzx; /* The cost of movzx operation. */ 51 const int large_insn; /* insns larger than this cost more */ 52 const int move_ratio; /* The threshold of number of scalar 53 memory-to-memory move insns. */ 54 const int movzbl_load; /* cost of loading using movzbl */ 55 const int int_load[3]; /* cost of loading integer registers 56 in QImode, HImode and SImode relative 57 to reg-reg move (2). */ 58 const int int_store[3]; /* cost of storing integer register 59 in QImode, HImode and SImode */ 60 const int fp_move; /* cost of reg,reg fld/fst */ 61 const int fp_load[3]; /* cost of loading FP register 62 in SFmode, DFmode and XFmode */ 63 const int fp_store[3]; /* cost of storing FP register 64 in SFmode, DFmode and XFmode */ 65 const int mmx_move; /* cost of moving MMX register. */ 66 const int mmx_load[2]; /* cost of loading MMX register 67 in SImode and DImode */ 68 const int mmx_store[2]; /* cost of storing MMX register 69 in SImode and DImode */ 70 const int sse_move; /* cost of moving SSE register. */ 71 const int sse_load[3]; /* cost of loading SSE register 72 in SImode, DImode and TImode*/ 73 const int sse_store[3]; /* cost of storing SSE register 74 in SImode, DImode and TImode*/ 75 const int mmxsse_to_integer; /* cost of moving mmxsse register to 76 integer and vice versa. */ 77 const int prefetch_block; /* bytes moved to cache for prefetch. */ 78 const int simultaneous_prefetches; /* number of parallel prefetch 79 operations. */ 80 const int branch_cost; /* Default value for BRANCH_COST. */ 81 const int fadd; /* cost of FADD and FSUB instructions. */ 82 const int fmul; /* cost of FMUL instruction. */ 83 const int fdiv; /* cost of FDIV instruction. */ 84 const int fabs; /* cost of FABS instruction. */ 85 const int fchs; /* cost of FCHS instruction. */ 86 const int fsqrt; /* cost of FSQRT instruction. */ 87}; 88 89extern const struct processor_costs *ix86_cost; 90 91/* Run-time compilation parameters selecting different hardware subsets. */ 92 93extern int target_flags; 94 95/* Macros used in the machine description to test the flags. */ 96 97/* configure can arrange to make this 2, to force a 486. */ 98 99#ifndef TARGET_CPU_DEFAULT 100#ifdef TARGET_64BIT_DEFAULT 101#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8 102#else 103#define TARGET_CPU_DEFAULT 0 104#endif 105#endif 106 107/* Masks for the -m switches */ 108#define MASK_80387 0x00000001 /* Hardware floating point */ 109#define MASK_RTD 0x00000002 /* Use ret that pops args */ 110#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ 111#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ 112#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ 113#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ 114#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ 115#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ 116#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ 117#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ 118#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ 119#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ 120#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ 121#define MASK_MMX 0x00002000 /* Support MMX regs/builtins */ 122#define MASK_SSE 0x00004000 /* Support SSE regs/builtins */ 123#define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */ 124#define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */ 125#define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */ 126#define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */ 127#define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */ 128#define MASK_64BIT 0x00100000 /* Produce 64bit code */ 129#define MASK_MS_BITFIELD_LAYOUT 0x00200000 /* Use native (MS) bitfield layout */ 130#define MASK_TLS_DIRECT_SEG_REFS 0x00400000 /* Avoid adding %gs:0 */ 131 132/* Unused: 0x03e0000 */ 133 134/* ... overlap with subtarget options starts by 0x04000000. */ 135#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ 136#define MASK_NO_ALIGN_LONG_STRINGS 0x08000000 /* Do not align long strings specially */ 137 138/* Use the floating point instructions */ 139#define TARGET_80387 (target_flags & MASK_80387) 140 141/* Compile using ret insn that pops args. 142 This will not work unless you use prototypes at least 143 for all functions that can take varying numbers of args. */ 144#define TARGET_RTD (target_flags & MASK_RTD) 145 146/* Align doubles to a two word boundary. This breaks compatibility with 147 the published ABI's for structures containing doubles, but produces 148 faster code on the pentium. */ 149#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) 150 151/* Use push instructions to save outgoing args. */ 152#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) 153 154/* Accumulate stack adjustments to prologue/epilogue. */ 155#define TARGET_ACCUMULATE_OUTGOING_ARGS \ 156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) 157 158/* Put uninitialized locals into bss, not data. 159 Meaningful only on svr3. */ 160#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) 161 162/* Use IEEE floating point comparisons. These handle correctly the cases 163 where the result of a comparison is unordered. Normally SIGFPE is 164 generated in such cases, in which case this isn't needed. */ 165#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) 166 167/* Functions that return a floating point value may return that value 168 in the 387 FPU or in 386 integer registers. If set, this flag causes 169 the 387 to be used, which is compatible with most calling conventions. */ 170#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) 171 172/* Long double is 128bit instead of 96bit, even when only 80bits are used. 173 This mode wastes cache, but avoid misaligned data accesses and simplifies 174 address calculations. */ 175#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) 176 177/* Disable generation of FP sin, cos and sqrt operations for 387. 178 This is because FreeBSD lacks these in the math-emulator-code */ 179#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) 180 181/* Don't create frame pointers for leaf functions */ 182#define TARGET_OMIT_LEAF_FRAME_POINTER \ 183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) 184 185/* Debug GO_IF_LEGITIMATE_ADDRESS */ 186#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) 187 188/* Debug FUNCTION_ARG macros */ 189#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) 190 191/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 192 compile-time constant. */ 193#ifdef IN_LIBGCC2 194#ifdef __x86_64__ 195#define TARGET_64BIT 1 196#else 197#define TARGET_64BIT 0 198#endif 199#else 200#ifdef TARGET_BI_ARCH 201#define TARGET_64BIT (target_flags & MASK_64BIT) 202#else 203#if TARGET_64BIT_DEFAULT 204#define TARGET_64BIT 1 205#else 206#define TARGET_64BIT 0 207#endif 208#endif 209#endif 210 211/* Avoid adding %gs:0 in TLS references; use %gs:address directly. */ 212#define TARGET_TLS_DIRECT_SEG_REFS (target_flags & MASK_TLS_DIRECT_SEG_REFS) 213 214#define TARGET_386 (ix86_tune == PROCESSOR_I386) 215#define TARGET_486 (ix86_tune == PROCESSOR_I486) 216#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 217#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 218#define TARGET_K6 (ix86_tune == PROCESSOR_K6) 219#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 220#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 221#define TARGET_K8 (ix86_tune == PROCESSOR_K8) 222#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 223 224#define TUNEMASK (1 << ix86_tune) 225extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; 226extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; 227extern const int x86_branch_hints, x86_unroll_strlen; 228extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; 229extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; 230extern const int x86_use_cltd, x86_read_modify_write; 231extern const int x86_read_modify, x86_split_long_moves; 232extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; 233extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; 234extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; 235extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; 236extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; 237extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; 238extern const int x86_epilogue_using_move, x86_decompose_lea; 239extern const int x86_arch_always_fancy_math_387, x86_shift1; 240extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs; 241extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; 242extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss; 243extern const int x86_inter_unit_moves; 244extern int x86_prefetch_sse; 245 246#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) 247#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) 248#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK) 249#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK) 250#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK) 251/* For sane SSE instruction set generation we need fcomi instruction. It is 252 safe to enable all CMOVE instructions. */ 253#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) 254#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK) 255#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK) 256#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK) 257#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) 258#define TARGET_MOVX (x86_movx & TUNEMASK) 259#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) 260#define TARGET_USE_LOOP (x86_use_loop & TUNEMASK) 261#define TARGET_USE_FIOP (x86_use_fiop & TUNEMASK) 262#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) 263#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK) 264#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK) 265#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK) 266#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK) 267#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK) 268#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK) 269#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK) 270#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK) 271#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK) 272#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK) 273#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK) 274#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK) 275#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK) 276#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK) 277#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK) 278#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK) 279#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) 280#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 281 (x86_sse_partial_reg_dependency & TUNEMASK) 282#define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & TUNEMASK) 283#define TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS \ 284 (x86_sse_partial_regs_for_cvtsd2ss & TUNEMASK) 285#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) 286#define TARGET_SSE_TYPELESS_LOAD0 (x86_sse_typeless_load0 & TUNEMASK) 287#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) 288#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) 289#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK) 290#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK) 291#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK) 292#define TARGET_PREFETCH_SSE (x86_prefetch_sse) 293#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK) 294#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK) 295#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK) 296#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK) 297 298#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) 299 300#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) 301#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) 302 303#define ASSEMBLER_DIALECT (ix86_asm_dialect) 304 305#define TARGET_SSE ((target_flags & MASK_SSE) != 0) 306#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) 307#define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0) 308#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 309#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ 310 && (ix86_fpmath & FPMATH_387)) 311#define TARGET_MMX ((target_flags & MASK_MMX) != 0) 312#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) 313#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) 314 315#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) 316 317#define TARGET_NO_ALIGN_LONG_STRINGS (target_flags & MASK_NO_ALIGN_LONG_STRINGS) 318 319#define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT) 320 321#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 322#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) 323 324/* WARNING: Do not mark empty strings for translation, as calling 325 gettext on an empty string does NOT return an empty 326 string. */ 327 328 329#define TARGET_SWITCHES \ 330{ { "80387", MASK_80387, N_("Use hardware fp") }, \ 331 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ 332 { "hard-float", MASK_80387, N_("Use hardware fp") }, \ 333 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ 334 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ 335 { "386", 0, "" /*Deprecated.*/}, \ 336 { "486", 0, "" /*Deprecated.*/}, \ 337 { "pentium", 0, "" /*Deprecated.*/}, \ 338 { "pentiumpro", 0, "" /*Deprecated.*/}, \ 339 { "pni", 0, "" /*Deprecated.*/}, \ 340 { "no-pni", 0, "" /*Deprecated.*/}, \ 341 { "intel-syntax", 0, "" /*Deprecated.*/}, \ 342 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ 343 { "rtd", MASK_RTD, \ 344 N_("Alternate calling convention") }, \ 345 { "no-rtd", -MASK_RTD, \ 346 N_("Use normal calling convention") }, \ 347 { "align-double", MASK_ALIGN_DOUBLE, \ 348 N_("Align some doubles on dword boundary") }, \ 349 { "no-align-double", -MASK_ALIGN_DOUBLE, \ 350 N_("Align doubles on word boundary") }, \ 351 { "svr3-shlib", MASK_SVR3_SHLIB, \ 352 N_("Uninitialized locals in .bss") }, \ 353 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ 354 N_("Uninitialized locals in .data") }, \ 355 { "ieee-fp", MASK_IEEE_FP, \ 356 N_("Use IEEE math for fp comparisons") }, \ 357 { "no-ieee-fp", -MASK_IEEE_FP, \ 358 N_("Do not use IEEE math for fp comparisons") }, \ 359 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ 360 N_("Return values of functions in FPU registers") }, \ 361 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ 362 N_("Do not return values of functions in FPU registers")}, \ 363 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ 364 N_("Do not generate sin, cos, sqrt for FPU") }, \ 365 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ 366 N_("Generate sin, cos, sqrt for FPU")}, \ 367 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ 368 N_("Omit the frame pointer in leaf functions") }, \ 369 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ 370 { "stack-arg-probe", MASK_STACK_PROBE, \ 371 N_("Enable stack probing") }, \ 372 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ 373 { "windows", 0, 0 /* undocumented */ }, \ 374 { "dll", 0, 0 /* undocumented */ }, \ 375 { "align-stringops", -MASK_NO_ALIGN_STROPS, \ 376 N_("Align destination of the string operations") }, \ 377 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ 378 N_("Do not align destination of the string operations") }, \ 379 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ 380 N_("Inline all known string operations") }, \ 381 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ 382 N_("Do not inline all known string operations") }, \ 383 { "push-args", -MASK_NO_PUSH_ARGS, \ 384 N_("Use push instructions to save outgoing arguments") }, \ 385 { "no-push-args", MASK_NO_PUSH_ARGS, \ 386 N_("Do not use push instructions to save outgoing arguments") }, \ 387 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \ 388 N_("Use push instructions to save outgoing arguments") }, \ 389 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \ 390 N_("Do not use push instructions to save outgoing arguments") }, \ 391 { "mmx", MASK_MMX, \ 392 N_("Support MMX built-in functions") }, \ 393 { "no-mmx", -MASK_MMX, \ 394 N_("Do not support MMX built-in functions") }, \ 395 { "3dnow", MASK_3DNOW, \ 396 N_("Support 3DNow! built-in functions") }, \ 397 { "no-3dnow", -MASK_3DNOW, \ 398 N_("Do not support 3DNow! built-in functions") }, \ 399 { "sse", MASK_SSE, \ 400 N_("Support MMX and SSE built-in functions and code generation") }, \ 401 { "no-sse", -MASK_SSE, \ 402 N_("Do not support MMX and SSE built-in functions and code generation") },\ 403 { "sse2", MASK_SSE2, \ 404 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ 405 { "no-sse2", -MASK_SSE2, \ 406 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ 407 { "sse3", MASK_SSE3, \ 408 N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\ 409 { "no-sse3", -MASK_SSE3, \ 410 N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\ 411 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ 412 N_("sizeof(long double) is 16") }, \ 413 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ 414 N_("sizeof(long double) is 12") }, \ 415 { "64", MASK_64BIT, \ 416 N_("Generate 64bit x86-64 code") }, \ 417 { "32", -MASK_64BIT, \ 418 N_("Generate 32bit i386 code") }, \ 419 { "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \ 420 N_("Use native (MS) bitfield layout") }, \ 421 { "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \ 422 N_("Use gcc default bitfield layout") }, \ 423 { "red-zone", -MASK_NO_RED_ZONE, \ 424 N_("Use red-zone in the x86-64 code") }, \ 425 { "no-red-zone", MASK_NO_RED_ZONE, \ 426 N_("Do not use red-zone in the x86-64 code") }, \ 427 { "no-align-long-strings", MASK_NO_ALIGN_LONG_STRINGS, \ 428 N_("Do not align long strings specially") }, \ 429 { "align-long-strings", -MASK_NO_ALIGN_LONG_STRINGS, \ 430 N_("Align strings longer than 30 on a 32-byte boundary") }, \ 431 { "tls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS, \ 432 N_("Use direct references against %gs when accessing tls data") }, \ 433 { "no-tls-direct-seg-refs", -MASK_TLS_DIRECT_SEG_REFS, \ 434 N_("Do not use direct references against %gs when accessing tls data") }, \ 435 SUBTARGET_SWITCHES \ 436 { "", \ 437 TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT \ 438 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT, 0 }} 439 440#ifndef TARGET_64BIT_DEFAULT 441#define TARGET_64BIT_DEFAULT 0 442#endif 443#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 444#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 445#endif 446 447/* Once GDB has been enhanced to deal with functions without frame 448 pointers, we can change this to allow for elimination of 449 the frame pointer in leaf functions. */ 450#define TARGET_DEFAULT 0 451 452/* This is not really a target flag, but is done this way so that 453 it's analogous to similar code for Mach-O on PowerPC. darwin.h 454 redefines this to 1. */ 455#define TARGET_MACHO 0 456 457/* This macro is similar to `TARGET_SWITCHES' but defines names of 458 command options that have values. Its definition is an 459 initializer with a subgrouping for each command option. 460 461 Each subgrouping contains a string constant, that defines the 462 fixed part of the option name, and the address of a variable. The 463 variable, type `char *', is set to the variable part of the given 464 option if the fixed part matches. The actual option name is made 465 by appending `-m' to the specified name. */ 466#define TARGET_OPTIONS \ 467{ { "tune=", &ix86_tune_string, \ 468 N_("Schedule code for given CPU"), 0}, \ 469 { "fpmath=", &ix86_fpmath_string, \ 470 N_("Generate floating point mathematics using given instruction set"), 0},\ 471 { "arch=", &ix86_arch_string, \ 472 N_("Generate code for given CPU"), 0}, \ 473 { "regparm=", &ix86_regparm_string, \ 474 N_("Number of registers used to pass integer arguments"), 0},\ 475 { "align-loops=", &ix86_align_loops_string, \ 476 N_("Loop code aligned to this power of 2"), 0}, \ 477 { "align-jumps=", &ix86_align_jumps_string, \ 478 N_("Jump targets are aligned to this power of 2"), 0}, \ 479 { "align-functions=", &ix86_align_funcs_string, \ 480 N_("Function starts are aligned to this power of 2"), 0}, \ 481 { "preferred-stack-boundary=", \ 482 &ix86_preferred_stack_boundary_string, \ 483 N_("Attempt to keep stack aligned to this power of 2"), 0}, \ 484 { "branch-cost=", &ix86_branch_cost_string, \ 485 N_("Branches are this expensive (1-5, arbitrary units)"), 0},\ 486 { "cmodel=", &ix86_cmodel_string, \ 487 N_("Use given x86-64 code model"), 0}, \ 488 { "debug-arg", &ix86_debug_arg_string, \ 489 "" /* Undocumented. */, 0}, \ 490 { "debug-addr", &ix86_debug_addr_string, \ 491 "" /* Undocumented. */, 0}, \ 492 { "asm=", &ix86_asm_string, \ 493 N_("Use given assembler dialect"), 0}, \ 494 { "tls-dialect=", &ix86_tls_dialect_string, \ 495 N_("Use given thread-local storage dialect"), 0}, \ 496 SUBTARGET_OPTIONS \ 497} 498 499/* Sometimes certain combinations of command options do not make 500 sense on a particular target machine. You can define a macro 501 `OVERRIDE_OPTIONS' to take account of this. This macro, if 502 defined, is executed once just after all the command options have 503 been parsed. 504 505 Don't use this macro to turn on various extra optimizations for 506 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 507 508#define OVERRIDE_OPTIONS override_options () 509 510/* These are meant to be redefined in the host dependent files */ 511#define SUBTARGET_SWITCHES 512#define SUBTARGET_OPTIONS 513 514/* Define this to change the optimizations performed by default. */ 515#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 516 optimization_options ((LEVEL), (SIZE)) 517 518/* Support for configure-time defaults of some command line options. */ 519#define OPTION_DEFAULT_SPECS \ 520 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 521 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 522 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" } 523 524/* Specs for the compiler proper */ 525 526#ifndef CC1_CPU_SPEC 527#define CC1_CPU_SPEC "\ 528%{!mtune*: \ 529%{m386:mtune=i386 \ 530%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \ 531%{m486:-mtune=i486 \ 532%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \ 533%{mpentium:-mtune=pentium \ 534%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \ 535%{mpentiumpro:-mtune=pentiumpro \ 536%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \ 537%{mcpu=*:-mtune=%* \ 538%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \ 539%<mcpu=* \ 540%{mpni:-msse3 \ 541%n`-mpni' is deprecated. Use `-msse3' instead.\n} \ 542%{mno-pni:-mno-sse3 \ 543%n`-mno-pni' is deprecated. Use `-mno-sse3' instead.\n} \ 544%{mintel-syntax:-masm=intel \ 545%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 546%{mno-intel-syntax:-masm=att \ 547%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 548#endif 549 550/* Target CPU builtins. */ 551#define TARGET_CPU_CPP_BUILTINS() \ 552 do \ 553 { \ 554 size_t arch_len = strlen (ix86_arch_string); \ 555 size_t tune_len = strlen (ix86_tune_string); \ 556 int last_arch_char = ix86_arch_string[arch_len - 1]; \ 557 int last_tune_char = ix86_tune_string[tune_len - 1]; \ 558 \ 559 if (TARGET_64BIT) \ 560 { \ 561 builtin_assert ("cpu=x86_64"); \ 562 builtin_assert ("machine=x86_64"); \ 563 builtin_define ("__amd64"); \ 564 builtin_define ("__amd64__"); \ 565 builtin_define ("__x86_64"); \ 566 builtin_define ("__x86_64__"); \ 567 } \ 568 else \ 569 { \ 570 builtin_assert ("cpu=i386"); \ 571 builtin_assert ("machine=i386"); \ 572 builtin_define_std ("i386"); \ 573 } \ 574 \ 575 /* Built-ins based on -mtune= (or -march= if no \ 576 -mtune= given). */ \ 577 if (TARGET_386) \ 578 builtin_define ("__tune_i386__"); \ 579 else if (TARGET_486) \ 580 builtin_define ("__tune_i486__"); \ 581 else if (TARGET_PENTIUM) \ 582 { \ 583 builtin_define ("__tune_i586__"); \ 584 builtin_define ("__tune_pentium__"); \ 585 if (last_tune_char == 'x') \ 586 builtin_define ("__tune_pentium_mmx__"); \ 587 } \ 588 else if (TARGET_PENTIUMPRO) \ 589 { \ 590 builtin_define ("__tune_i686__"); \ 591 builtin_define ("__tune_pentiumpro__"); \ 592 switch (last_tune_char) \ 593 { \ 594 case '3': \ 595 builtin_define ("__tune_pentium3__"); \ 596 /* FALLTHRU */ \ 597 case '2': \ 598 builtin_define ("__tune_pentium2__"); \ 599 break; \ 600 } \ 601 } \ 602 else if (TARGET_K6) \ 603 { \ 604 builtin_define ("__tune_k6__"); \ 605 if (last_tune_char == '2') \ 606 builtin_define ("__tune_k6_2__"); \ 607 else if (last_tune_char == '3') \ 608 builtin_define ("__tune_k6_3__"); \ 609 } \ 610 else if (TARGET_ATHLON) \ 611 { \ 612 builtin_define ("__tune_athlon__"); \ 613 /* Only plain "athlon" lacks SSE. */ \ 614 if (last_tune_char != 'n') \ 615 builtin_define ("__tune_athlon_sse__"); \ 616 } \ 617 else if (TARGET_K8) \ 618 builtin_define ("__tune_k8__"); \ 619 else if (TARGET_PENTIUM4) \ 620 builtin_define ("__tune_pentium4__"); \ 621 \ 622 if (TARGET_MMX) \ 623 builtin_define ("__MMX__"); \ 624 if (TARGET_3DNOW) \ 625 builtin_define ("__3dNOW__"); \ 626 if (TARGET_3DNOW_A) \ 627 builtin_define ("__3dNOW_A__"); \ 628 if (TARGET_SSE) \ 629 builtin_define ("__SSE__"); \ 630 if (TARGET_SSE2) \ 631 builtin_define ("__SSE2__"); \ 632 if (TARGET_SSE3) \ 633 { \ 634 builtin_define ("__SSE3__"); \ 635 builtin_define ("__PNI__"); \ 636 } \ 637 if (TARGET_SSE_MATH && TARGET_SSE) \ 638 builtin_define ("__SSE_MATH__"); \ 639 if (TARGET_SSE_MATH && TARGET_SSE2) \ 640 builtin_define ("__SSE2_MATH__"); \ 641 \ 642 /* Built-ins based on -march=. */ \ 643 if (ix86_arch == PROCESSOR_I486) \ 644 { \ 645 builtin_define ("__i486"); \ 646 builtin_define ("__i486__"); \ 647 } \ 648 else if (ix86_arch == PROCESSOR_PENTIUM) \ 649 { \ 650 builtin_define ("__i586"); \ 651 builtin_define ("__i586__"); \ 652 builtin_define ("__pentium"); \ 653 builtin_define ("__pentium__"); \ 654 if (last_arch_char == 'x') \ 655 builtin_define ("__pentium_mmx__"); \ 656 } \ 657 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ 658 { \ 659 builtin_define ("__i686"); \ 660 builtin_define ("__i686__"); \ 661 builtin_define ("__pentiumpro"); \ 662 builtin_define ("__pentiumpro__"); \ 663 } \ 664 else if (ix86_arch == PROCESSOR_K6) \ 665 { \ 666 \ 667 builtin_define ("__k6"); \ 668 builtin_define ("__k6__"); \ 669 if (last_arch_char == '2') \ 670 builtin_define ("__k6_2__"); \ 671 else if (last_arch_char == '3') \ 672 builtin_define ("__k6_3__"); \ 673 } \ 674 else if (ix86_arch == PROCESSOR_ATHLON) \ 675 { \ 676 builtin_define ("__athlon"); \ 677 builtin_define ("__athlon__"); \ 678 /* Only plain "athlon" lacks SSE. */ \ 679 if (last_arch_char != 'n') \ 680 builtin_define ("__athlon_sse__"); \ 681 } \ 682 else if (ix86_arch == PROCESSOR_K8) \ 683 { \ 684 builtin_define ("__k8"); \ 685 builtin_define ("__k8__"); \ 686 } \ 687 else if (ix86_arch == PROCESSOR_PENTIUM4) \ 688 { \ 689 builtin_define ("__pentium4"); \ 690 builtin_define ("__pentium4__"); \ 691 } \ 692 } \ 693 while (0) 694 695#define TARGET_CPU_DEFAULT_i386 0 696#define TARGET_CPU_DEFAULT_i486 1 697#define TARGET_CPU_DEFAULT_pentium 2 698#define TARGET_CPU_DEFAULT_pentium_mmx 3 699#define TARGET_CPU_DEFAULT_pentiumpro 4 700#define TARGET_CPU_DEFAULT_pentium2 5 701#define TARGET_CPU_DEFAULT_pentium3 6 702#define TARGET_CPU_DEFAULT_pentium4 7 703#define TARGET_CPU_DEFAULT_k6 8 704#define TARGET_CPU_DEFAULT_k6_2 9 705#define TARGET_CPU_DEFAULT_k6_3 10 706#define TARGET_CPU_DEFAULT_athlon 11 707#define TARGET_CPU_DEFAULT_athlon_sse 12 708#define TARGET_CPU_DEFAULT_k8 13 709#define TARGET_CPU_DEFAULT_pentium_m 14 710#define TARGET_CPU_DEFAULT_prescott 15 711#define TARGET_CPU_DEFAULT_nocona 16 712 713#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ 714 "pentiumpro", "pentium2", "pentium3", \ 715 "pentium4", "k6", "k6-2", "k6-3",\ 716 "athlon", "athlon-4", "k8", \ 717 "pentium-m", "prescott", "nocona"} 718 719#ifndef CC1_SPEC 720#define CC1_SPEC "%(cc1_cpu) " 721#endif 722 723/* This macro defines names of additional specifications to put in the 724 specs that can be used in various specifications like CC1_SPEC. Its 725 definition is an initializer with a subgrouping for each command option. 726 727 Each subgrouping contains a string constant, that defines the 728 specification name, and a string constant that used by the GCC driver 729 program. 730 731 Do not define this macro if it does not need to do anything. */ 732 733#ifndef SUBTARGET_EXTRA_SPECS 734#define SUBTARGET_EXTRA_SPECS 735#endif 736 737#define EXTRA_SPECS \ 738 { "cc1_cpu", CC1_CPU_SPEC }, \ 739 SUBTARGET_EXTRA_SPECS 740 741/* target machine storage layout */ 742 743#define LONG_DOUBLE_TYPE_SIZE 96 744 745/* Set the value of FLT_EVAL_METHOD in float.h. When using only the 746 FPU, assume that the fpcw is set to extended precision; when using 747 only SSE, rounding is correct; when using both SSE and the FPU, 748 the rounding precision is indeterminate, since either may be chosen 749 apparently at random. */ 750#define TARGET_FLT_EVAL_METHOD \ 751 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 752 753#define SHORT_TYPE_SIZE 16 754#define INT_TYPE_SIZE 32 755#define FLOAT_TYPE_SIZE 32 756#ifndef LONG_TYPE_SIZE 757#define LONG_TYPE_SIZE BITS_PER_WORD 758#endif 759#define MAX_WCHAR_TYPE_SIZE 32 760#define DOUBLE_TYPE_SIZE 64 761#define LONG_LONG_TYPE_SIZE 64 762 763#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 764#define MAX_BITS_PER_WORD 64 765#define MAX_LONG_TYPE_SIZE 64 766#else 767#define MAX_BITS_PER_WORD 32 768#define MAX_LONG_TYPE_SIZE 32 769#endif 770 771/* Define this if most significant byte of a word is the lowest numbered. */ 772/* That is true on the 80386. */ 773 774#define BITS_BIG_ENDIAN 0 775 776/* Define this if most significant byte of a word is the lowest numbered. */ 777/* That is not true on the 80386. */ 778#define BYTES_BIG_ENDIAN 0 779 780/* Define this if most significant word of a multiword number is the lowest 781 numbered. */ 782/* Not true for 80386 */ 783#define WORDS_BIG_ENDIAN 0 784 785/* Width of a word, in units (bytes). */ 786#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 787#ifdef IN_LIBGCC2 788#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 789#else 790#define MIN_UNITS_PER_WORD 4 791#endif 792 793/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 794#define PARM_BOUNDARY BITS_PER_WORD 795 796/* Boundary (in *bits*) on which stack pointer should be aligned. */ 797#define STACK_BOUNDARY BITS_PER_WORD 798 799/* Boundary (in *bits*) on which the stack pointer prefers to be 800 aligned; the compiler cannot rely on having this alignment. */ 801#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 802 803/* As of July 2001, many runtimes to not align the stack properly when 804 entering main. This causes expand_main_function to forcibly align 805 the stack, which results in aligned frames for functions called from 806 main, though it does nothing for the alignment of main itself. */ 807#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ 808 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) 809 810/* Minimum allocation boundary for the code of a function. */ 811#define FUNCTION_BOUNDARY 8 812 813/* C++ stores the virtual bit in the lowest bit of function pointers. */ 814#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 815 816/* Alignment of field after `int : 0' in a structure. */ 817 818#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 819 820/* Minimum size in bits of the largest boundary to which any 821 and all fundamental data types supported by the hardware 822 might need to be aligned. No data type wants to be aligned 823 rounder than this. 824 825 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 826 and Pentium Pro XFmode values at 128 bit boundaries. */ 827 828#define BIGGEST_ALIGNMENT 128 829 830/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 831#define ALIGN_MODE_128(MODE) \ 832 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE)) 833 834/* The published ABIs say that doubles should be aligned on word 835 boundaries, so lower the alignment for structure fields unless 836 -malign-double is set. */ 837 838/* ??? Blah -- this macro is used directly by libobjc. Since it 839 supports no vector modes, cut out the complexity and fall back 840 on BIGGEST_FIELD_ALIGNMENT. */ 841#ifdef IN_TARGET_LIBS 842#ifdef __x86_64__ 843#define BIGGEST_FIELD_ALIGNMENT 128 844#else 845#define BIGGEST_FIELD_ALIGNMENT 32 846#endif 847#else 848#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 849 x86_field_alignment (FIELD, COMPUTED) 850#endif 851 852/* If defined, a C expression to compute the alignment given to a 853 constant that is being placed in memory. EXP is the constant 854 and ALIGN is the alignment that the object would ordinarily have. 855 The value of this macro is used instead of that alignment to align 856 the object. 857 858 If this macro is not defined, then ALIGN is used. 859 860 The typical use of this macro is to increase alignment for string 861 constants to be word aligned so that `strcpy' calls that copy 862 constants can be done inline. */ 863 864#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 865 866/* If defined, a C expression to compute the alignment for a static 867 variable. TYPE is the data type, and ALIGN is the alignment that 868 the object would ordinarily have. The value of this macro is used 869 instead of that alignment to align the object. 870 871 If this macro is not defined, then ALIGN is used. 872 873 One use of this macro is to increase alignment of medium-size 874 data to make it all fit in fewer cache lines. Another is to 875 cause character arrays to be word-aligned so that `strcpy' calls 876 that copy constants to character arrays can be done inline. */ 877 878#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 879 880/* If defined, a C expression to compute the alignment for a local 881 variable. TYPE is the data type, and ALIGN is the alignment that 882 the object would ordinarily have. The value of this macro is used 883 instead of that alignment to align the object. 884 885 If this macro is not defined, then ALIGN is used. 886 887 One use of this macro is to increase alignment of medium-size 888 data to make it all fit in fewer cache lines. */ 889 890#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) 891 892/* If defined, a C expression that gives the alignment boundary, in 893 bits, of an argument with the specified mode and type. If it is 894 not defined, `PARM_BOUNDARY' is used for all arguments. */ 895 896#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 897 ix86_function_arg_boundary ((MODE), (TYPE)) 898 899/* Set this nonzero if move instructions will actually fail to work 900 when given unaligned data. */ 901#define STRICT_ALIGNMENT 0 902 903/* If bit field type is int, don't let it cross an int, 904 and give entire struct the alignment of an int. */ 905/* Required on the 386 since it doesn't have bit-field insns. */ 906#define PCC_BITFIELD_TYPE_MATTERS 1 907 908/* Standard register usage. */ 909 910/* This processor has special stack-like registers. See reg-stack.c 911 for details. */ 912 913#define STACK_REGS 914#define IS_STACK_MODE(MODE) \ 915 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \ 916 917/* Number of actual hardware registers. 918 The hardware registers are assigned numbers for the compiler 919 from 0 to just below FIRST_PSEUDO_REGISTER. 920 All registers that the compiler knows about must be given numbers, 921 even those that are not normally considered general registers. 922 923 In the 80386 we give the 8 general purpose registers the numbers 0-7. 924 We number the floating point registers 8-15. 925 Note that registers 0-7 can be accessed as a short or int, 926 while only 0-3 may be used with byte `mov' instructions. 927 928 Reg 16 does not correspond to any hardware register, but instead 929 appears in the RTL as an argument pointer prior to reload, and is 930 eliminated during reloading in favor of either the stack or frame 931 pointer. */ 932 933#define FIRST_PSEUDO_REGISTER 53 934 935/* Number of hardware registers that go into the DWARF-2 unwind info. 936 If not defined, equals FIRST_PSEUDO_REGISTER. */ 937 938#define DWARF_FRAME_REGISTERS 17 939 940/* 1 for registers that have pervasive standard uses 941 and are not available for the register allocator. 942 On the 80386, the stack pointer is such, as is the arg pointer. 943 944 The value is a mask - bit 1 is set for fixed registers 945 for 32bit target, while 2 is set for fixed registers for 64bit. 946 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 947 */ 948#define FIXED_REGISTERS \ 949/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 950{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ 951/*arg,flags,fpsr,dir,frame*/ \ 952 3, 3, 3, 3, 3, \ 953/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 954 0, 0, 0, 0, 0, 0, 0, 0, \ 955/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 956 0, 0, 0, 0, 0, 0, 0, 0, \ 957/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 958 1, 1, 1, 1, 1, 1, 1, 1, \ 959/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 960 1, 1, 1, 1, 1, 1, 1, 1} 961 962 963/* 1 for registers not available across function calls. 964 These must include the FIXED_REGISTERS and also any 965 registers that can be used without being saved. 966 The latter must include the registers where values are returned 967 and the register where structure-value addresses are passed. 968 Aside from that, you can include as many other registers as you like. 969 970 The value is a mask - bit 1 is set for call used 971 for 32bit target, while 2 is set for call used for 64bit. 972 Proper value is computed in the CONDITIONAL_REGISTER_USAGE. 973*/ 974#define CALL_USED_REGISTERS \ 975/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 976{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ 977/*arg,flags,fpsr,dir,frame*/ \ 978 3, 3, 3, 3, 3, \ 979/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 980 3, 3, 3, 3, 3, 3, 3, 3, \ 981/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ 982 3, 3, 3, 3, 3, 3, 3, 3, \ 983/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 984 3, 3, 3, 3, 1, 1, 1, 1, \ 985/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 986 3, 3, 3, 3, 3, 3, 3, 3} \ 987 988/* Order in which to allocate registers. Each register must be 989 listed once, even those in FIXED_REGISTERS. List frame pointer 990 late and fixed registers last. Note that, in general, we prefer 991 registers listed in CALL_USED_REGISTERS, keeping the others 992 available for storage of persistent values. 993 994 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 995 so this is just empty initializer for array. */ 996 997#define REG_ALLOC_ORDER \ 998{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 999 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 1000 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1001 48, 49, 50, 51, 52 } 1002 1003/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 1004 to be rearranged based on a particular function. When using sse math, 1005 we want to allocate SSE before x87 registers and vice vera. */ 1006 1007#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 1008 1009 1010/* Macro to conditionally modify fixed_regs/call_used_regs. */ 1011#define CONDITIONAL_REGISTER_USAGE \ 1012do { \ 1013 int i; \ 1014 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1015 { \ 1016 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ 1017 call_used_regs[i] = (call_used_regs[i] \ 1018 & (TARGET_64BIT ? 2 : 1)) != 0; \ 1019 } \ 1020 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 1021 { \ 1022 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 1023 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 1024 } \ 1025 if (! TARGET_MMX) \ 1026 { \ 1027 int i; \ 1028 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1029 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ 1030 fixed_regs[i] = call_used_regs[i] = 1; \ 1031 } \ 1032 if (! TARGET_SSE) \ 1033 { \ 1034 int i; \ 1035 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1036 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ 1037 fixed_regs[i] = call_used_regs[i] = 1; \ 1038 } \ 1039 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ 1040 { \ 1041 int i; \ 1042 HARD_REG_SET x; \ 1043 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ 1044 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 1045 if (TEST_HARD_REG_BIT (x, i)) \ 1046 fixed_regs[i] = call_used_regs[i] = 1; \ 1047 } \ 1048 } while (0) 1049 1050/* Return number of consecutive hard regs needed starting at reg REGNO 1051 to hold something of mode MODE. 1052 This is ordinarily the length in words of a value of mode MODE 1053 but can be less for certain modes in special long registers. 1054 1055 Actually there are no two word move instructions for consecutive 1056 registers. And only registers 0-3 may have mov byte instructions 1057 applied to them. 1058 */ 1059 1060#define HARD_REGNO_NREGS(REGNO, MODE) \ 1061 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1062 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1063 : ((MODE) == XFmode \ 1064 ? (TARGET_64BIT ? 2 : 3) \ 1065 : (MODE) == XCmode \ 1066 ? (TARGET_64BIT ? 4 : 6) \ 1067 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1068 1069#define VALID_SSE2_REG_MODE(MODE) \ 1070 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1071 || (MODE) == V2DImode) 1072 1073#define VALID_SSE_REG_MODE(MODE) \ 1074 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1075 || (MODE) == SFmode || (MODE) == TFmode \ 1076 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \ 1077 || VALID_SSE2_REG_MODE (MODE) \ 1078 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) 1079 1080#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1081 ((MODE) == V2SFmode || (MODE) == SFmode) 1082 1083#define VALID_MMX_REG_MODE(MODE) \ 1084 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ 1085 || (MODE) == V2SImode || (MODE) == SImode) 1086 1087#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1088 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ 1089 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ 1090 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) 1091 1092#define VALID_FP_MODE_P(MODE) \ 1093 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1094 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1095 1096#define VALID_INT_MODE_P(MODE) \ 1097 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1098 || (MODE) == DImode \ 1099 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1100 || (MODE) == CDImode \ 1101 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1102 || (MODE) == TFmode || (MODE) == TCmode))) 1103 1104/* Return true for modes passed in SSE registers. */ 1105#define SSE_REG_MODE_P(MODE) \ 1106 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ 1107 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ 1108 || (MODE) == V4SFmode || (MODE) == V4SImode) 1109 1110/* Return true for modes passed in MMX registers. */ 1111#define MMX_REG_MODE_P(MODE) \ 1112 ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \ 1113 || (MODE) == V2SFmode) 1114 1115/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1116 1117#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1118 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1119 1120/* Value is 1 if it is a good idea to tie two pseudo registers 1121 when one has mode MODE1 and one has mode MODE2. 1122 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1123 for any hard reg, then this must be 0 for correct output. */ 1124 1125#define MODES_TIEABLE_P(MODE1, MODE2) \ 1126 ((MODE1) == (MODE2) \ 1127 || (((MODE1) == HImode || (MODE1) == SImode \ 1128 || ((MODE1) == QImode \ 1129 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1130 || ((MODE1) == DImode && TARGET_64BIT)) \ 1131 && ((MODE2) == HImode || (MODE2) == SImode \ 1132 || ((MODE2) == QImode \ 1133 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ 1134 || ((MODE2) == DImode && TARGET_64BIT)))) 1135 1136/* It is possible to write patterns to move flags; but until someone 1137 does it, */ 1138#define AVOID_CCMODE_COPIES 1139 1140/* Specify the modes required to caller save a given hard regno. 1141 We do this on i386 to prevent flags from being saved at all. 1142 1143 Kill any attempts to combine saving of modes. */ 1144 1145#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1146 (CC_REGNO_P (REGNO) ? VOIDmode \ 1147 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1148 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\ 1149 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1150 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ 1151 : (MODE)) 1152/* Specify the registers used for certain standard purposes. 1153 The values of these macros are register numbers. */ 1154 1155/* on the 386 the pc register is %eip, and is not usable as a general 1156 register. The ordinary mov instructions won't work */ 1157/* #define PC_REGNUM */ 1158 1159/* Register to use for pushing function arguments. */ 1160#define STACK_POINTER_REGNUM 7 1161 1162/* Base register for access to local variables of the function. */ 1163#define HARD_FRAME_POINTER_REGNUM 6 1164 1165/* Base register for access to local variables of the function. */ 1166#define FRAME_POINTER_REGNUM 20 1167 1168/* First floating point reg */ 1169#define FIRST_FLOAT_REG 8 1170 1171/* First & last stack-like regs */ 1172#define FIRST_STACK_REG FIRST_FLOAT_REG 1173#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1174 1175#define FLAGS_REG 17 1176#define FPSR_REG 18 1177#define DIRFLAG_REG 19 1178 1179#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1180#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1181 1182#define FIRST_MMX_REG (LAST_SSE_REG + 1) 1183#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1184 1185#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1186#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1187 1188#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1189#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1190 1191/* Value should be nonzero if functions must have frame pointers. 1192 Zero means the frame pointer need not be set up (and parms 1193 may be accessed via the stack pointer) in functions that seem suitable. 1194 This is computed in `reload', in reload1.c. */ 1195#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () 1196 1197/* Override this in other tm.h files to cope with various OS losage 1198 requiring a frame pointer. */ 1199#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1200#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1201#endif 1202 1203/* Make sure we can access arbitrary call frames. */ 1204#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1205 1206/* Base register for access to arguments of the function. */ 1207#define ARG_POINTER_REGNUM 16 1208 1209/* Register in which static-chain is passed to a function. 1210 We do use ECX as static chain register for 32 bit ABI. On the 1211 64bit ABI, ECX is an argument register, so we use R10 instead. */ 1212#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) 1213 1214/* Register to hold the addressing base for position independent 1215 code access to data items. We don't use PIC pointer for 64bit 1216 mode. Define the regnum to dummy value to prevent gcc from 1217 pessimizing code dealing with EBX. 1218 1219 To avoid clobbering a call-saved register unnecessarily, we renumber 1220 the pic register when possible. The change is visible after the 1221 prologue has been emitted. */ 1222 1223#define REAL_PIC_OFFSET_TABLE_REGNUM 3 1224 1225#define PIC_OFFSET_TABLE_REGNUM \ 1226 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \ 1227 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1228 : REAL_PIC_OFFSET_TABLE_REGNUM) 1229 1230#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1231 1232/* Register in which address to store a structure value 1233 arrives in the function. On the 386, the prologue 1234 copies this from the stack to register %eax. */ 1235#define STRUCT_VALUE_INCOMING 0 1236 1237/* Place in which caller passes the structure value address. 1238 0 means push the value on the stack like an argument. */ 1239#define STRUCT_VALUE 0 1240 1241/* A C expression which can inhibit the returning of certain function 1242 values in registers, based on the type of value. A nonzero value 1243 says to return the function value in memory, just as large 1244 structures are always returned. Here TYPE will be a C expression 1245 of type `tree', representing the data type of the value. 1246 1247 Note that values of mode `BLKmode' must be explicitly handled by 1248 this macro. Also, the option `-fpcc-struct-return' takes effect 1249 regardless of this macro. On most systems, it is possible to 1250 leave the macro undefined; this causes a default definition to be 1251 used, whose value is the constant 1 for `BLKmode' values, and 0 1252 otherwise. 1253 1254 Do not use this macro to indicate that structures and unions 1255 should always be returned in memory. You should instead use 1256 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ 1257 1258#define RETURN_IN_MEMORY(TYPE) \ 1259 ix86_return_in_memory (TYPE) 1260 1261/* This is overridden by <cygwin.h>. */ 1262#define MS_AGGREGATE_RETURN 0 1263 1264 1265/* Define the classes of registers for register constraints in the 1266 machine description. Also define ranges of constants. 1267 1268 One of the classes must always be named ALL_REGS and include all hard regs. 1269 If there is more than one class, another class must be named NO_REGS 1270 and contain no registers. 1271 1272 The name GENERAL_REGS must be the name of a class (or an alias for 1273 another name such as ALL_REGS). This is the class of registers 1274 that is allowed by "g" or "r" in a register constraint. 1275 Also, registers outside this class are allocated only when 1276 instructions express preferences for them. 1277 1278 The classes must be numbered in nondecreasing order; that is, 1279 a larger-numbered class must never be contained completely 1280 in a smaller-numbered class. 1281 1282 For any two classes, it is very desirable that there be another 1283 class that represents their union. 1284 1285 It might seem that class BREG is unnecessary, since no useful 386 1286 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1287 and the "b" register constraint is useful in asms for syscalls. 1288 1289 The flags and fpsr registers are in no class. */ 1290 1291enum reg_class 1292{ 1293 NO_REGS, 1294 AREG, DREG, CREG, BREG, SIREG, DIREG, 1295 AD_REGS, /* %eax/%edx for DImode */ 1296 Q_REGS, /* %eax %ebx %ecx %edx */ 1297 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1298 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1299 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1300 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1301 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1302 FLOAT_REGS, 1303 SSE_REGS, 1304 MMX_REGS, 1305 FP_TOP_SSE_REGS, 1306 FP_SECOND_SSE_REGS, 1307 FLOAT_SSE_REGS, 1308 FLOAT_INT_REGS, 1309 INT_SSE_REGS, 1310 FLOAT_INT_SSE_REGS, 1311 ALL_REGS, LIM_REG_CLASSES 1312}; 1313 1314#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1315 1316#define INTEGER_CLASS_P(CLASS) \ 1317 reg_class_subset_p ((CLASS), GENERAL_REGS) 1318#define FLOAT_CLASS_P(CLASS) \ 1319 reg_class_subset_p ((CLASS), FLOAT_REGS) 1320#define SSE_CLASS_P(CLASS) \ 1321 reg_class_subset_p ((CLASS), SSE_REGS) 1322#define MMX_CLASS_P(CLASS) \ 1323 reg_class_subset_p ((CLASS), MMX_REGS) 1324#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1325 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1326#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1327 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1328#define MAYBE_SSE_CLASS_P(CLASS) \ 1329 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1330#define MAYBE_MMX_CLASS_P(CLASS) \ 1331 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1332 1333#define Q_CLASS_P(CLASS) \ 1334 reg_class_subset_p ((CLASS), Q_REGS) 1335 1336/* Give names of register classes as strings for dump file. */ 1337 1338#define REG_CLASS_NAMES \ 1339{ "NO_REGS", \ 1340 "AREG", "DREG", "CREG", "BREG", \ 1341 "SIREG", "DIREG", \ 1342 "AD_REGS", \ 1343 "Q_REGS", "NON_Q_REGS", \ 1344 "INDEX_REGS", \ 1345 "LEGACY_REGS", \ 1346 "GENERAL_REGS", \ 1347 "FP_TOP_REG", "FP_SECOND_REG", \ 1348 "FLOAT_REGS", \ 1349 "SSE_REGS", \ 1350 "MMX_REGS", \ 1351 "FP_TOP_SSE_REGS", \ 1352 "FP_SECOND_SSE_REGS", \ 1353 "FLOAT_SSE_REGS", \ 1354 "FLOAT_INT_REGS", \ 1355 "INT_SSE_REGS", \ 1356 "FLOAT_INT_SSE_REGS", \ 1357 "ALL_REGS" } 1358 1359/* Define which registers fit in which classes. 1360 This is an initializer for a vector of HARD_REG_SET 1361 of length N_REG_CLASSES. */ 1362 1363#define REG_CLASS_CONTENTS \ 1364{ { 0x00, 0x0 }, \ 1365 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1366 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1367 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1368 { 0x03, 0x0 }, /* AD_REGS */ \ 1369 { 0x0f, 0x0 }, /* Q_REGS */ \ 1370 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1371 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1372 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1373 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1374 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1375 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1376{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1377{ 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1378{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1379{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1380{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1381 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1382{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1383{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1384{ 0xffffffff,0x1fffff } \ 1385} 1386 1387/* The same information, inverted: 1388 Return the class number of the smallest class containing 1389 reg number REGNO. This could be a conditional expression 1390 or could index an array. */ 1391 1392#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1393 1394/* When defined, the compiler allows registers explicitly used in the 1395 rtl to be used as spill registers but prevents the compiler from 1396 extending the lifetime of these registers. */ 1397 1398#define SMALL_REGISTER_CLASSES 1 1399 1400#define QI_REG_P(X) \ 1401 (REG_P (X) && REGNO (X) < 4) 1402 1403#define GENERAL_REGNO_P(N) \ 1404 ((N) < 8 || REX_INT_REGNO_P (N)) 1405 1406#define GENERAL_REG_P(X) \ 1407 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1408 1409#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1410 1411#define NON_QI_REG_P(X) \ 1412 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) 1413 1414#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) 1415#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1416 1417#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1418#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) 1419#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1420#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1421 1422#define SSE_REGNO_P(N) \ 1423 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ 1424 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) 1425 1426#define REX_SSE_REGNO_P(N) \ 1427 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG) 1428 1429#define SSE_REGNO(N) \ 1430 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1431#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1432 1433#define SSE_FLOAT_MODE_P(MODE) \ 1434 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1435 1436#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) 1437#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1438 1439#define STACK_REG_P(XOP) \ 1440 (REG_P (XOP) && \ 1441 REGNO (XOP) >= FIRST_STACK_REG && \ 1442 REGNO (XOP) <= LAST_STACK_REG) 1443 1444#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) 1445 1446#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1447 1448#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1449#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1450 1451/* The class value for index registers, and the one for base regs. */ 1452 1453#define INDEX_REG_CLASS INDEX_REGS 1454#define BASE_REG_CLASS GENERAL_REGS 1455 1456/* Get reg_class from a letter such as appears in the machine description. */ 1457 1458#define REG_CLASS_FROM_LETTER(C) \ 1459 ((C) == 'r' ? GENERAL_REGS : \ 1460 (C) == 'R' ? LEGACY_REGS : \ 1461 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ 1462 (C) == 'Q' ? Q_REGS : \ 1463 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1464 ? FLOAT_REGS \ 1465 : NO_REGS) : \ 1466 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1467 ? FP_TOP_REG \ 1468 : NO_REGS) : \ 1469 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ 1470 ? FP_SECOND_REG \ 1471 : NO_REGS) : \ 1472 (C) == 'a' ? AREG : \ 1473 (C) == 'b' ? BREG : \ 1474 (C) == 'c' ? CREG : \ 1475 (C) == 'd' ? DREG : \ 1476 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ 1477 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ 1478 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ 1479 (C) == 'A' ? AD_REGS : \ 1480 (C) == 'D' ? DIREG : \ 1481 (C) == 'S' ? SIREG : NO_REGS) 1482 1483/* The letters I, J, K, L and M in a register constraint string 1484 can be used to stand for particular ranges of immediate operands. 1485 This macro defines what the ranges are. 1486 C is the letter, and VALUE is a constant value. 1487 Return 1 if VALUE is in the range specified by C. 1488 1489 I is for non-DImode shifts. 1490 J is for DImode shifts. 1491 K is for signed imm8 operands. 1492 L is for andsi as zero-extending move. 1493 M is for shifts that can be executed by the "lea" opcode. 1494 N is for immediate operands for out/in instructions (0-255) 1495 */ 1496 1497#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1498 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ 1499 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ 1500 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ 1501 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ 1502 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ 1503 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ 1504 : 0) 1505 1506/* Similar, but for floating constants, and defining letters G and H. 1507 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if 1508 TARGET_387 isn't set, because the stack register converter may need to 1509 load 0.0 into the function value register. */ 1510 1511#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1512 ((C) == 'G' ? standard_80387_constant_p (VALUE) \ 1513 : 0) 1514 1515/* A C expression that defines the optional machine-dependent 1516 constraint letters that can be used to segregate specific types of 1517 operands, usually memory references, for the target machine. Any 1518 letter that is not elsewhere defined and not matched by 1519 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not 1520 be defined. 1521 1522 If it is required for a particular target machine, it should 1523 return 1 if VALUE corresponds to the operand type represented by 1524 the constraint letter C. If C is not defined as an extra 1525 constraint, the value returned should be 0 regardless of VALUE. */ 1526 1527#define EXTRA_CONSTRAINT(VALUE, D) \ 1528 ((D) == 'e' ? x86_64_sign_extended_value (VALUE) \ 1529 : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \ 1530 : (D) == 'C' ? standard_sse_constant_p (VALUE) \ 1531 : 0) 1532 1533/* Place additional restrictions on the register class to use when it 1534 is necessary to be able to hold a value of mode MODE in a reload 1535 register for which class CLASS would ordinarily be used. */ 1536 1537#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1538 ((MODE) == QImode && !TARGET_64BIT \ 1539 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1540 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1541 ? Q_REGS : (CLASS)) 1542 1543/* Given an rtx X being reloaded into a reg required to be 1544 in class CLASS, return the class of reg to actually use. 1545 In general this is just CLASS; but on some machines 1546 in some cases it is preferable to use a more restrictive class. 1547 On the 80386 series, we prevent floating constants from being 1548 reloaded into floating registers (since no move-insn can do that) 1549 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1550 1551/* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1552 QImode must go into class Q_REGS. 1553 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1554 movdf to do mem-to-mem moves through integer regs. */ 1555 1556#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1557 ix86_preferred_reload_class ((X), (CLASS)) 1558 1559/* If we are copying between general and FP registers, we need a memory 1560 location. The same is true for SSE and MMX registers. */ 1561#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1562 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1563 1564/* QImode spills from non-QI registers need a scratch. This does not 1565 happen often -- the only example so far requires an uninitialized 1566 pseudo. */ 1567 1568#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ 1569 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ 1570 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ 1571 ? Q_REGS : NO_REGS) 1572 1573/* Return the maximum number of consecutive registers 1574 needed to represent mode MODE in a register of class CLASS. */ 1575/* On the 80386, this is the size of MODE in words, 1576 except in the FP regs, where a single reg is always enough. */ 1577#define CLASS_MAX_NREGS(CLASS, MODE) \ 1578 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1579 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1580 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ 1581 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1582 1583/* A C expression whose value is nonzero if pseudos that have been 1584 assigned to registers of class CLASS would likely be spilled 1585 because registers of CLASS are needed for spill registers. 1586 1587 The default value of this macro returns 1 if CLASS has exactly one 1588 register and zero otherwise. On most machines, this default 1589 should be used. Only define this macro to some other expression 1590 if pseudo allocated by `local-alloc.c' end up in memory because 1591 their hard registers were needed for spill registers. If this 1592 macro returns nonzero for those classes, those pseudos will only 1593 be allocated by `global.c', which knows how to reallocate the 1594 pseudo to another register. If there would not be another 1595 register available for reallocation, you should not change the 1596 definition of this macro since the only effect of such a 1597 definition would be to slow down register allocation. */ 1598 1599#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1600 (((CLASS) == AREG) \ 1601 || ((CLASS) == DREG) \ 1602 || ((CLASS) == CREG) \ 1603 || ((CLASS) == BREG) \ 1604 || ((CLASS) == AD_REGS) \ 1605 || ((CLASS) == SIREG) \ 1606 || ((CLASS) == DIREG) \ 1607 || ((CLASS) == FP_TOP_REG) \ 1608 || ((CLASS) == FP_SECOND_REG)) 1609 1610/* Return a class of registers that cannot change FROM mode to TO mode. 1611 1612 x87 registers can't do subreg as all values are reformated to extended 1613 precision. XMM registers does not support with nonzero offsets equal 1614 to 4, 8 and 12 otherwise valid for integer registers. Since we can't 1615 determine these, prohibit all nonparadoxical subregs changing size. */ 1616 1617#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1618 (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \ 1619 ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \ 1620 || MAYBE_MMX_CLASS_P (CLASS) \ 1621 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1622 ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0) 1623 1624/* A C statement that adds to CLOBBERS any hard regs the port wishes 1625 to automatically clobber for all asms. 1626 1627 We do this in the new i386 backend to maintain source compatibility 1628 with the old cc0-based compiler. */ 1629 1630#define MD_ASM_CLOBBERS(CLOBBERS) \ 1631 do { \ 1632 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ 1633 (CLOBBERS)); \ 1634 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ 1635 (CLOBBERS)); \ 1636 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ 1637 (CLOBBERS)); \ 1638 } while (0) 1639 1640/* Stack layout; function entry, exit and calling. */ 1641 1642/* Define this if pushing a word on the stack 1643 makes the stack pointer a smaller address. */ 1644#define STACK_GROWS_DOWNWARD 1645 1646/* Define this if the nominal address of the stack frame 1647 is at the high-address end of the local variables; 1648 that is, each additional local variable allocated 1649 goes at a more negative offset in the frame. */ 1650#define FRAME_GROWS_DOWNWARD 1651 1652/* Offset within stack frame to start allocating local variables at. 1653 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1654 first local allocated. Otherwise, it is the offset to the BEGINNING 1655 of the first local allocated. */ 1656#define STARTING_FRAME_OFFSET 0 1657 1658/* If we generate an insn to push BYTES bytes, 1659 this says how many the stack pointer really advances by. 1660 On 386 pushw decrements by exactly 2 no matter what the position was. 1661 On the 386 there is no pushb; we use pushw instead, and this 1662 has the effect of rounding up to 2. 1663 1664 For 64bit ABI we round up to 8 bytes. 1665 */ 1666 1667#define PUSH_ROUNDING(BYTES) \ 1668 (TARGET_64BIT \ 1669 ? (((BYTES) + 7) & (-8)) \ 1670 : (((BYTES) + 1) & (-2))) 1671 1672/* If defined, the maximum amount of space required for outgoing arguments will 1673 be computed and placed into the variable 1674 `current_function_outgoing_args_size'. No space will be pushed onto the 1675 stack for each call; instead, the function prologue should increase the stack 1676 frame size by this amount. */ 1677 1678#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1679 1680/* If defined, a C expression whose value is nonzero when we want to use PUSH 1681 instructions to pass outgoing arguments. */ 1682 1683#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1684 1685/* We want the stack and args grow in opposite directions, even if 1686 PUSH_ARGS is 0. */ 1687#define PUSH_ARGS_REVERSED 1 1688 1689/* Offset of first parameter from the argument pointer register value. */ 1690#define FIRST_PARM_OFFSET(FNDECL) 0 1691 1692/* Define this macro if functions should assume that stack space has been 1693 allocated for arguments even when their values are passed in registers. 1694 1695 The value of this macro is the size, in bytes, of the area reserved for 1696 arguments passed in registers for the function represented by FNDECL. 1697 1698 This space can be allocated by the caller, or be a part of the 1699 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1700 which. */ 1701#define REG_PARM_STACK_SPACE(FNDECL) 0 1702 1703/* Define as a C expression that evaluates to nonzero if we do not know how 1704 to pass TYPE solely in registers. The file expr.h defines a 1705 definition that is usually appropriate, refer to expr.h for additional 1706 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be 1707 computed in the stack and then loaded into a register. */ 1708#define MUST_PASS_IN_STACK(MODE, TYPE) ix86_must_pass_in_stack ((MODE), (TYPE)) 1709 1710/* Value is the number of bytes of arguments automatically 1711 popped when returning from a subroutine call. 1712 FUNDECL is the declaration node of the function (as a tree), 1713 FUNTYPE is the data type of the function (as a tree), 1714 or for a library call it is an identifier node for the subroutine name. 1715 SIZE is the number of bytes of arguments passed on the stack. 1716 1717 On the 80386, the RTD insn may be used to pop them if the number 1718 of args is fixed, but if the number is variable then the caller 1719 must pop them all. RTD can't be used for library calls now 1720 because the library is compiled with the Unix compiler. 1721 Use of RTD is a selectable option, since it is incompatible with 1722 standard Unix calling sequences. If the option is not selected, 1723 the caller must always pop the args. 1724 1725 The attribute stdcall is equivalent to RTD on a per module basis. */ 1726 1727#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1728 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1729 1730/* Define how to find the value returned by a function. 1731 VALTYPE is the data type of the value (as a tree). 1732 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1733 otherwise, FUNC is 0. */ 1734#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1735 ix86_function_value (VALTYPE) 1736 1737#define FUNCTION_VALUE_REGNO_P(N) \ 1738 ix86_function_value_regno_p (N) 1739 1740/* Define how to find the value returned by a library function 1741 assuming the value has mode MODE. */ 1742 1743#define LIBCALL_VALUE(MODE) \ 1744 ix86_libcall_value (MODE) 1745 1746/* Define the size of the result block used for communication between 1747 untyped_call and untyped_return. The block contains a DImode value 1748 followed by the block used by fnsave and frstor. */ 1749 1750#define APPLY_RESULT_SIZE (8+108) 1751 1752/* 1 if N is a possible register number for function argument passing. */ 1753#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1754 1755/* Define a data type for recording info about an argument list 1756 during the scan of that argument list. This data type should 1757 hold all necessary information about the function itself 1758 and about the args processed so far, enough to enable macros 1759 such as FUNCTION_ARG to determine where the next arg should go. */ 1760 1761typedef struct ix86_args { 1762 int words; /* # words passed so far */ 1763 int nregs; /* # registers available for passing */ 1764 int regno; /* next available register number */ 1765 int fastcall; /* fastcall calling convention is used */ 1766 int sse_words; /* # sse words passed so far */ 1767 int sse_nregs; /* # sse registers available for passing */ 1768 int warn_sse; /* True when we want to warn about SSE ABI. */ 1769 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1770 int sse_regno; /* next available sse register number */ 1771 int mmx_words; /* # mmx words passed so far */ 1772 int mmx_nregs; /* # mmx registers available for passing */ 1773 int mmx_regno; /* next available mmx register number */ 1774 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1775} CUMULATIVE_ARGS; 1776 1777/* Initialize a variable CUM of type CUMULATIVE_ARGS 1778 for a call to a function whose data type is FNTYPE. 1779 For a library call, FNTYPE is 0. */ 1780 1781#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1782 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1783 1784/* Update the data in CUM to advance over an argument 1785 of mode MODE and data type TYPE. 1786 (TYPE is null for libcalls where that information may not be available.) */ 1787 1788#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1789 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1790 1791/* Define where to put the arguments to a function. 1792 Value is zero to push the argument on the stack, 1793 or a hard register in which to store the argument. 1794 1795 MODE is the argument's machine mode. 1796 TYPE is the data type of the argument (as a tree). 1797 This is null for libcalls where that information may 1798 not be available. 1799 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1800 the preceding args and about the function being called. 1801 NAMED is nonzero if this argument is a named parameter 1802 (otherwise it is an extra parameter matching an ellipsis). */ 1803 1804#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1805 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1806 1807/* For an arg passed partly in registers and partly in memory, 1808 this is the number of registers used. 1809 For args passed entirely in registers or entirely in memory, zero. */ 1810 1811#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 1812 1813/* A C expression that indicates when an argument must be passed by 1814 reference. If nonzero for an argument, a copy of that argument is 1815 made in memory and a pointer to the argument is passed instead of 1816 the argument itself. The pointer is passed in whatever way is 1817 appropriate for passing a pointer to that type. */ 1818 1819#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1820 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED) 1821 1822/* Perform any needed actions needed for a function that is receiving a 1823 variable number of arguments. 1824 1825 CUM is as above. 1826 1827 MODE and TYPE are the mode and type of the current parameter. 1828 1829 PRETEND_SIZE is a variable that should be set to the amount of stack 1830 that must be pushed by the prolog to pretend that our caller pushed 1831 it. 1832 1833 Normally, this macro will push all remaining incoming registers on the 1834 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1835 1836#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1837 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ 1838 (NO_RTL)) 1839 1840/* Implement `va_start' for varargs and stdarg. */ 1841#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ 1842 ix86_va_start (VALIST, NEXTARG) 1843 1844/* Implement `va_arg'. */ 1845#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ 1846 ix86_va_arg ((VALIST), (TYPE)) 1847 1848#define TARGET_ASM_FILE_END ix86_file_end 1849#define NEED_INDICATE_EXEC_STACK 0 1850 1851/* Output assembler code to FILE to increment profiler label # LABELNO 1852 for profiling a function entry. */ 1853 1854#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1855 1856#define MCOUNT_NAME "_mcount" 1857 1858#define PROFILE_COUNT_REGISTER "edx" 1859 1860/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1861 the stack pointer does not matter. The value is tested only in 1862 functions that have frame pointers. 1863 No definition is equivalent to always zero. */ 1864/* Note on the 386 it might be more efficient not to define this since 1865 we have to restore it ourselves from the frame pointer, in order to 1866 use pop */ 1867 1868#define EXIT_IGNORE_STACK 1 1869 1870/* Output assembler code for a block containing the constant parts 1871 of a trampoline, leaving space for the variable parts. */ 1872 1873/* On the 386, the trampoline contains two instructions: 1874 mov #STATIC,ecx 1875 jmp FUNCTION 1876 The trampoline is generated entirely at runtime. The operand of JMP 1877 is the address of FUNCTION relative to the instruction following the 1878 JMP (which is 5 bytes long). */ 1879 1880/* Length in units of the trampoline for entering a nested function. */ 1881 1882#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) 1883 1884/* Emit RTL insns to initialize the variable parts of a trampoline. 1885 FNADDR is an RTX for the address of the function's pure code. 1886 CXT is an RTX for the static chain value for the function. */ 1887 1888#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1889 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1890 1891/* Definitions for register eliminations. 1892 1893 This is an array of structures. Each structure initializes one pair 1894 of eliminable registers. The "from" register number is given first, 1895 followed by "to". Eliminations of the same "from" register are listed 1896 in order of preference. 1897 1898 There are two registers that can always be eliminated on the i386. 1899 The frame pointer and the arg pointer can be replaced by either the 1900 hard frame pointer or to the stack pointer, depending upon the 1901 circumstances. The hard frame pointer is not used before reload and 1902 so it is not eligible for elimination. */ 1903 1904#define ELIMINABLE_REGS \ 1905{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1906 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1907 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1908 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1909 1910/* Given FROM and TO register numbers, say whether this elimination is 1911 allowed. Frame pointer elimination is automatically handled. 1912 1913 All other eliminations are valid. */ 1914 1915#define CAN_ELIMINATE(FROM, TO) \ 1916 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 1917 1918/* Define the offset between two registers, one to be eliminated, and the other 1919 its replacement, at the start of a routine. */ 1920 1921#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1922 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1923 1924/* Addressing modes, and classification of registers for them. */ 1925 1926/* Macros to check register numbers against specific register classes. */ 1927 1928/* These assume that REGNO is a hard or pseudo reg number. 1929 They give nonzero only if REGNO is a hard reg of the suitable class 1930 or a pseudo reg currently allocated to a suitable hard reg. 1931 Since they use reg_renumber, they are safe only once reg_renumber 1932 has been allocated, which happens in local-alloc.c. */ 1933 1934#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1935 ((REGNO) < STACK_POINTER_REGNUM \ 1936 || (REGNO >= FIRST_REX_INT_REG \ 1937 && (REGNO) <= LAST_REX_INT_REG) \ 1938 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1939 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1940 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) 1941 1942#define REGNO_OK_FOR_BASE_P(REGNO) \ 1943 ((REGNO) <= STACK_POINTER_REGNUM \ 1944 || (REGNO) == ARG_POINTER_REGNUM \ 1945 || (REGNO) == FRAME_POINTER_REGNUM \ 1946 || (REGNO >= FIRST_REX_INT_REG \ 1947 && (REGNO) <= LAST_REX_INT_REG) \ 1948 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ 1949 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ 1950 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) 1951 1952#define REGNO_OK_FOR_SIREG_P(REGNO) \ 1953 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) 1954#define REGNO_OK_FOR_DIREG_P(REGNO) \ 1955 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) 1956 1957/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1958 and check its validity for a certain class. 1959 We have two alternate definitions for each of them. 1960 The usual definition accepts all pseudo regs; the other rejects 1961 them unless they have been allocated suitable hard regs. 1962 The symbol REG_OK_STRICT causes the latter definition to be used. 1963 1964 Most source files want to accept pseudo regs in the hope that 1965 they will get allocated to the class that the insn wants them to be in. 1966 Source files for reload pass need to be strict. 1967 After reload, it makes no difference, since pseudo regs have 1968 been eliminated by then. */ 1969 1970 1971/* Non strict versions, pseudos are ok */ 1972#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1973 (REGNO (X) < STACK_POINTER_REGNUM \ 1974 || (REGNO (X) >= FIRST_REX_INT_REG \ 1975 && REGNO (X) <= LAST_REX_INT_REG) \ 1976 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1977 1978#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1979 (REGNO (X) <= STACK_POINTER_REGNUM \ 1980 || REGNO (X) == ARG_POINTER_REGNUM \ 1981 || REGNO (X) == FRAME_POINTER_REGNUM \ 1982 || (REGNO (X) >= FIRST_REX_INT_REG \ 1983 && REGNO (X) <= LAST_REX_INT_REG) \ 1984 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1985 1986/* Strict versions, hard registers only */ 1987#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1988#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1989 1990#ifndef REG_OK_STRICT 1991#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1992#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1993 1994#else 1995#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1996#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1997#endif 1998 1999/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2000 that is a valid memory address for an instruction. 2001 The MODE argument is the machine mode for the MEM expression 2002 that wants to use this address. 2003 2004 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, 2005 except for CONSTANT_ADDRESS_P which is usually machine-independent. 2006 2007 See legitimize_pic_address in i386.c for details as to what 2008 constitutes a legitimate address when -fpic is used. */ 2009 2010#define MAX_REGS_PER_ADDRESS 2 2011 2012#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 2013 2014/* Nonzero if the constant value X is a legitimate general operand. 2015 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2016 2017#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 2018 2019#ifdef REG_OK_STRICT 2020#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2021do { \ 2022 if (legitimate_address_p ((MODE), (X), 1)) \ 2023 goto ADDR; \ 2024} while (0) 2025 2026#else 2027#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2028do { \ 2029 if (legitimate_address_p ((MODE), (X), 0)) \ 2030 goto ADDR; \ 2031} while (0) 2032 2033#endif 2034 2035/* If defined, a C expression to determine the base term of address X. 2036 This macro is used in only one place: `find_base_term' in alias.c. 2037 2038 It is always safe for this macro to not be defined. It exists so 2039 that alias analysis can understand machine-dependent addresses. 2040 2041 The typical use of this macro is to handle addresses containing 2042 a label_ref or symbol_ref within an UNSPEC. */ 2043 2044#define FIND_BASE_TERM(X) ix86_find_base_term (X) 2045 2046/* Try machine-dependent ways of modifying an illegitimate address 2047 to be legitimate. If we find one, return the new, valid address. 2048 This macro is used in only one place: `memory_address' in explow.c. 2049 2050 OLDX is the address as it was before break_out_memory_refs was called. 2051 In some cases it is useful to look at this to decide what needs to be done. 2052 2053 MODE and WIN are passed so that this macro can use 2054 GO_IF_LEGITIMATE_ADDRESS. 2055 2056 It is always safe for this macro to do nothing. It exists to recognize 2057 opportunities to optimize the output. 2058 2059 For the 80386, we handle X+REG by loading X into a register R and 2060 using R+REG. R will go in a general reg and indexing will be used. 2061 However, if REG is a broken-out memory address or multiplication, 2062 nothing needs to be done because REG can certainly go in a general reg. 2063 2064 When -fpic is used, special handling is needed for symbolic references. 2065 See comments by legitimize_pic_address in i386.c for details. */ 2066 2067#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2068do { \ 2069 (X) = legitimize_address ((X), (OLDX), (MODE)); \ 2070 if (memory_address_p ((MODE), (X))) \ 2071 goto WIN; \ 2072} while (0) 2073 2074#define REWRITE_ADDRESS(X) rewrite_address (X) 2075 2076/* Nonzero if the constant value X is a legitimate general operand 2077 when generating PIC code. It is given that flag_pic is on and 2078 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2079 2080#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 2081 2082#define SYMBOLIC_CONST(X) \ 2083 (GET_CODE (X) == SYMBOL_REF \ 2084 || GET_CODE (X) == LABEL_REF \ 2085 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 2086 2087/* Go to LABEL if ADDR (a legitimate address expression) 2088 has an effect that depends on the machine mode it is used for. 2089 On the 80386, only postdecrement and postincrement address depend thus 2090 (the amount of decrement or increment being the length of the operand). */ 2091#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2092do { \ 2093 if (GET_CODE (ADDR) == POST_INC \ 2094 || GET_CODE (ADDR) == POST_DEC) \ 2095 goto LABEL; \ 2096} while (0) 2097 2098/* Codes for all the SSE/MMX builtins. */ 2099enum ix86_builtins 2100{ 2101 IX86_BUILTIN_ADDPS, 2102 IX86_BUILTIN_ADDSS, 2103 IX86_BUILTIN_DIVPS, 2104 IX86_BUILTIN_DIVSS, 2105 IX86_BUILTIN_MULPS, 2106 IX86_BUILTIN_MULSS, 2107 IX86_BUILTIN_SUBPS, 2108 IX86_BUILTIN_SUBSS, 2109 2110 IX86_BUILTIN_CMPEQPS, 2111 IX86_BUILTIN_CMPLTPS, 2112 IX86_BUILTIN_CMPLEPS, 2113 IX86_BUILTIN_CMPGTPS, 2114 IX86_BUILTIN_CMPGEPS, 2115 IX86_BUILTIN_CMPNEQPS, 2116 IX86_BUILTIN_CMPNLTPS, 2117 IX86_BUILTIN_CMPNLEPS, 2118 IX86_BUILTIN_CMPNGTPS, 2119 IX86_BUILTIN_CMPNGEPS, 2120 IX86_BUILTIN_CMPORDPS, 2121 IX86_BUILTIN_CMPUNORDPS, 2122 IX86_BUILTIN_CMPNEPS, 2123 IX86_BUILTIN_CMPEQSS, 2124 IX86_BUILTIN_CMPLTSS, 2125 IX86_BUILTIN_CMPLESS, 2126 IX86_BUILTIN_CMPNEQSS, 2127 IX86_BUILTIN_CMPNLTSS, 2128 IX86_BUILTIN_CMPNLESS, 2129 IX86_BUILTIN_CMPORDSS, 2130 IX86_BUILTIN_CMPUNORDSS, 2131 IX86_BUILTIN_CMPNESS, 2132 2133 IX86_BUILTIN_COMIEQSS, 2134 IX86_BUILTIN_COMILTSS, 2135 IX86_BUILTIN_COMILESS, 2136 IX86_BUILTIN_COMIGTSS, 2137 IX86_BUILTIN_COMIGESS, 2138 IX86_BUILTIN_COMINEQSS, 2139 IX86_BUILTIN_UCOMIEQSS, 2140 IX86_BUILTIN_UCOMILTSS, 2141 IX86_BUILTIN_UCOMILESS, 2142 IX86_BUILTIN_UCOMIGTSS, 2143 IX86_BUILTIN_UCOMIGESS, 2144 IX86_BUILTIN_UCOMINEQSS, 2145 2146 IX86_BUILTIN_CVTPI2PS, 2147 IX86_BUILTIN_CVTPS2PI, 2148 IX86_BUILTIN_CVTSI2SS, 2149 IX86_BUILTIN_CVTSI642SS, 2150 IX86_BUILTIN_CVTSS2SI, 2151 IX86_BUILTIN_CVTSS2SI64, 2152 IX86_BUILTIN_CVTTPS2PI, 2153 IX86_BUILTIN_CVTTSS2SI, 2154 IX86_BUILTIN_CVTTSS2SI64, 2155 2156 IX86_BUILTIN_MAXPS, 2157 IX86_BUILTIN_MAXSS, 2158 IX86_BUILTIN_MINPS, 2159 IX86_BUILTIN_MINSS, 2160 2161 IX86_BUILTIN_LOADAPS, 2162 IX86_BUILTIN_LOADUPS, 2163 IX86_BUILTIN_STOREAPS, 2164 IX86_BUILTIN_STOREUPS, 2165 IX86_BUILTIN_LOADSS, 2166 IX86_BUILTIN_STORESS, 2167 IX86_BUILTIN_MOVSS, 2168 2169 IX86_BUILTIN_MOVHLPS, 2170 IX86_BUILTIN_MOVLHPS, 2171 IX86_BUILTIN_LOADHPS, 2172 IX86_BUILTIN_LOADLPS, 2173 IX86_BUILTIN_STOREHPS, 2174 IX86_BUILTIN_STORELPS, 2175 2176 IX86_BUILTIN_MASKMOVQ, 2177 IX86_BUILTIN_MOVMSKPS, 2178 IX86_BUILTIN_PMOVMSKB, 2179 2180 IX86_BUILTIN_MOVNTPS, 2181 IX86_BUILTIN_MOVNTQ, 2182 2183 IX86_BUILTIN_LOADDQA, 2184 IX86_BUILTIN_LOADDQU, 2185 IX86_BUILTIN_STOREDQA, 2186 IX86_BUILTIN_STOREDQU, 2187 IX86_BUILTIN_MOVQ, 2188 IX86_BUILTIN_LOADD, 2189 IX86_BUILTIN_STORED, 2190 2191 IX86_BUILTIN_CLRTI, 2192 2193 IX86_BUILTIN_PACKSSWB, 2194 IX86_BUILTIN_PACKSSDW, 2195 IX86_BUILTIN_PACKUSWB, 2196 2197 IX86_BUILTIN_PADDB, 2198 IX86_BUILTIN_PADDW, 2199 IX86_BUILTIN_PADDD, 2200 IX86_BUILTIN_PADDQ, 2201 IX86_BUILTIN_PADDSB, 2202 IX86_BUILTIN_PADDSW, 2203 IX86_BUILTIN_PADDUSB, 2204 IX86_BUILTIN_PADDUSW, 2205 IX86_BUILTIN_PSUBB, 2206 IX86_BUILTIN_PSUBW, 2207 IX86_BUILTIN_PSUBD, 2208 IX86_BUILTIN_PSUBQ, 2209 IX86_BUILTIN_PSUBSB, 2210 IX86_BUILTIN_PSUBSW, 2211 IX86_BUILTIN_PSUBUSB, 2212 IX86_BUILTIN_PSUBUSW, 2213 2214 IX86_BUILTIN_PAND, 2215 IX86_BUILTIN_PANDN, 2216 IX86_BUILTIN_POR, 2217 IX86_BUILTIN_PXOR, 2218 2219 IX86_BUILTIN_PAVGB, 2220 IX86_BUILTIN_PAVGW, 2221 2222 IX86_BUILTIN_PCMPEQB, 2223 IX86_BUILTIN_PCMPEQW, 2224 IX86_BUILTIN_PCMPEQD, 2225 IX86_BUILTIN_PCMPGTB, 2226 IX86_BUILTIN_PCMPGTW, 2227 IX86_BUILTIN_PCMPGTD, 2228 2229 IX86_BUILTIN_PEXTRW, 2230 IX86_BUILTIN_PINSRW, 2231 2232 IX86_BUILTIN_PMADDWD, 2233 2234 IX86_BUILTIN_PMAXSW, 2235 IX86_BUILTIN_PMAXUB, 2236 IX86_BUILTIN_PMINSW, 2237 IX86_BUILTIN_PMINUB, 2238 2239 IX86_BUILTIN_PMULHUW, 2240 IX86_BUILTIN_PMULHW, 2241 IX86_BUILTIN_PMULLW, 2242 2243 IX86_BUILTIN_PSADBW, 2244 IX86_BUILTIN_PSHUFW, 2245 2246 IX86_BUILTIN_PSLLW, 2247 IX86_BUILTIN_PSLLD, 2248 IX86_BUILTIN_PSLLQ, 2249 IX86_BUILTIN_PSRAW, 2250 IX86_BUILTIN_PSRAD, 2251 IX86_BUILTIN_PSRLW, 2252 IX86_BUILTIN_PSRLD, 2253 IX86_BUILTIN_PSRLQ, 2254 IX86_BUILTIN_PSLLWI, 2255 IX86_BUILTIN_PSLLDI, 2256 IX86_BUILTIN_PSLLQI, 2257 IX86_BUILTIN_PSRAWI, 2258 IX86_BUILTIN_PSRADI, 2259 IX86_BUILTIN_PSRLWI, 2260 IX86_BUILTIN_PSRLDI, 2261 IX86_BUILTIN_PSRLQI, 2262 2263 IX86_BUILTIN_PUNPCKHBW, 2264 IX86_BUILTIN_PUNPCKHWD, 2265 IX86_BUILTIN_PUNPCKHDQ, 2266 IX86_BUILTIN_PUNPCKLBW, 2267 IX86_BUILTIN_PUNPCKLWD, 2268 IX86_BUILTIN_PUNPCKLDQ, 2269 2270 IX86_BUILTIN_SHUFPS, 2271 2272 IX86_BUILTIN_RCPPS, 2273 IX86_BUILTIN_RCPSS, 2274 IX86_BUILTIN_RSQRTPS, 2275 IX86_BUILTIN_RSQRTSS, 2276 IX86_BUILTIN_SQRTPS, 2277 IX86_BUILTIN_SQRTSS, 2278 2279 IX86_BUILTIN_UNPCKHPS, 2280 IX86_BUILTIN_UNPCKLPS, 2281 2282 IX86_BUILTIN_ANDPS, 2283 IX86_BUILTIN_ANDNPS, 2284 IX86_BUILTIN_ORPS, 2285 IX86_BUILTIN_XORPS, 2286 2287 IX86_BUILTIN_EMMS, 2288 IX86_BUILTIN_LDMXCSR, 2289 IX86_BUILTIN_STMXCSR, 2290 IX86_BUILTIN_SFENCE, 2291 2292 /* 3DNow! Original */ 2293 IX86_BUILTIN_FEMMS, 2294 IX86_BUILTIN_PAVGUSB, 2295 IX86_BUILTIN_PF2ID, 2296 IX86_BUILTIN_PFACC, 2297 IX86_BUILTIN_PFADD, 2298 IX86_BUILTIN_PFCMPEQ, 2299 IX86_BUILTIN_PFCMPGE, 2300 IX86_BUILTIN_PFCMPGT, 2301 IX86_BUILTIN_PFMAX, 2302 IX86_BUILTIN_PFMIN, 2303 IX86_BUILTIN_PFMUL, 2304 IX86_BUILTIN_PFRCP, 2305 IX86_BUILTIN_PFRCPIT1, 2306 IX86_BUILTIN_PFRCPIT2, 2307 IX86_BUILTIN_PFRSQIT1, 2308 IX86_BUILTIN_PFRSQRT, 2309 IX86_BUILTIN_PFSUB, 2310 IX86_BUILTIN_PFSUBR, 2311 IX86_BUILTIN_PI2FD, 2312 IX86_BUILTIN_PMULHRW, 2313 2314 /* 3DNow! Athlon Extensions */ 2315 IX86_BUILTIN_PF2IW, 2316 IX86_BUILTIN_PFNACC, 2317 IX86_BUILTIN_PFPNACC, 2318 IX86_BUILTIN_PI2FW, 2319 IX86_BUILTIN_PSWAPDSI, 2320 IX86_BUILTIN_PSWAPDSF, 2321 2322 IX86_BUILTIN_SSE_ZERO, 2323 IX86_BUILTIN_MMX_ZERO, 2324 2325 /* SSE2 */ 2326 IX86_BUILTIN_ADDPD, 2327 IX86_BUILTIN_ADDSD, 2328 IX86_BUILTIN_DIVPD, 2329 IX86_BUILTIN_DIVSD, 2330 IX86_BUILTIN_MULPD, 2331 IX86_BUILTIN_MULSD, 2332 IX86_BUILTIN_SUBPD, 2333 IX86_BUILTIN_SUBSD, 2334 2335 IX86_BUILTIN_CMPEQPD, 2336 IX86_BUILTIN_CMPLTPD, 2337 IX86_BUILTIN_CMPLEPD, 2338 IX86_BUILTIN_CMPGTPD, 2339 IX86_BUILTIN_CMPGEPD, 2340 IX86_BUILTIN_CMPNEQPD, 2341 IX86_BUILTIN_CMPNLTPD, 2342 IX86_BUILTIN_CMPNLEPD, 2343 IX86_BUILTIN_CMPNGTPD, 2344 IX86_BUILTIN_CMPNGEPD, 2345 IX86_BUILTIN_CMPORDPD, 2346 IX86_BUILTIN_CMPUNORDPD, 2347 IX86_BUILTIN_CMPNEPD, 2348 IX86_BUILTIN_CMPEQSD, 2349 IX86_BUILTIN_CMPLTSD, 2350 IX86_BUILTIN_CMPLESD, 2351 IX86_BUILTIN_CMPNEQSD, 2352 IX86_BUILTIN_CMPNLTSD, 2353 IX86_BUILTIN_CMPNLESD, 2354 IX86_BUILTIN_CMPORDSD, 2355 IX86_BUILTIN_CMPUNORDSD, 2356 IX86_BUILTIN_CMPNESD, 2357 2358 IX86_BUILTIN_COMIEQSD, 2359 IX86_BUILTIN_COMILTSD, 2360 IX86_BUILTIN_COMILESD, 2361 IX86_BUILTIN_COMIGTSD, 2362 IX86_BUILTIN_COMIGESD, 2363 IX86_BUILTIN_COMINEQSD, 2364 IX86_BUILTIN_UCOMIEQSD, 2365 IX86_BUILTIN_UCOMILTSD, 2366 IX86_BUILTIN_UCOMILESD, 2367 IX86_BUILTIN_UCOMIGTSD, 2368 IX86_BUILTIN_UCOMIGESD, 2369 IX86_BUILTIN_UCOMINEQSD, 2370 2371 IX86_BUILTIN_MAXPD, 2372 IX86_BUILTIN_MAXSD, 2373 IX86_BUILTIN_MINPD, 2374 IX86_BUILTIN_MINSD, 2375 2376 IX86_BUILTIN_ANDPD, 2377 IX86_BUILTIN_ANDNPD, 2378 IX86_BUILTIN_ORPD, 2379 IX86_BUILTIN_XORPD, 2380 2381 IX86_BUILTIN_SQRTPD, 2382 IX86_BUILTIN_SQRTSD, 2383 2384 IX86_BUILTIN_UNPCKHPD, 2385 IX86_BUILTIN_UNPCKLPD, 2386 2387 IX86_BUILTIN_SHUFPD, 2388 2389 IX86_BUILTIN_LOADAPD, 2390 IX86_BUILTIN_LOADUPD, 2391 IX86_BUILTIN_STOREAPD, 2392 IX86_BUILTIN_STOREUPD, 2393 IX86_BUILTIN_LOADSD, 2394 IX86_BUILTIN_STORESD, 2395 IX86_BUILTIN_MOVSD, 2396 2397 IX86_BUILTIN_LOADHPD, 2398 IX86_BUILTIN_LOADLPD, 2399 IX86_BUILTIN_STOREHPD, 2400 IX86_BUILTIN_STORELPD, 2401 2402 IX86_BUILTIN_CVTDQ2PD, 2403 IX86_BUILTIN_CVTDQ2PS, 2404 2405 IX86_BUILTIN_CVTPD2DQ, 2406 IX86_BUILTIN_CVTPD2PI, 2407 IX86_BUILTIN_CVTPD2PS, 2408 IX86_BUILTIN_CVTTPD2DQ, 2409 IX86_BUILTIN_CVTTPD2PI, 2410 2411 IX86_BUILTIN_CVTPI2PD, 2412 IX86_BUILTIN_CVTSI2SD, 2413 IX86_BUILTIN_CVTSI642SD, 2414 2415 IX86_BUILTIN_CVTSD2SI, 2416 IX86_BUILTIN_CVTSD2SI64, 2417 IX86_BUILTIN_CVTSD2SS, 2418 IX86_BUILTIN_CVTSS2SD, 2419 IX86_BUILTIN_CVTTSD2SI, 2420 IX86_BUILTIN_CVTTSD2SI64, 2421 2422 IX86_BUILTIN_CVTPS2DQ, 2423 IX86_BUILTIN_CVTPS2PD, 2424 IX86_BUILTIN_CVTTPS2DQ, 2425 2426 IX86_BUILTIN_MOVNTI, 2427 IX86_BUILTIN_MOVNTPD, 2428 IX86_BUILTIN_MOVNTDQ, 2429 2430 IX86_BUILTIN_SETPD1, 2431 IX86_BUILTIN_SETPD, 2432 IX86_BUILTIN_CLRPD, 2433 IX86_BUILTIN_SETRPD, 2434 IX86_BUILTIN_LOADPD1, 2435 IX86_BUILTIN_LOADRPD, 2436 IX86_BUILTIN_STOREPD1, 2437 IX86_BUILTIN_STORERPD, 2438 2439 /* SSE2 MMX */ 2440 IX86_BUILTIN_MASKMOVDQU, 2441 IX86_BUILTIN_MOVMSKPD, 2442 IX86_BUILTIN_PMOVMSKB128, 2443 IX86_BUILTIN_MOVQ2DQ, 2444 IX86_BUILTIN_MOVDQ2Q, 2445 2446 IX86_BUILTIN_PACKSSWB128, 2447 IX86_BUILTIN_PACKSSDW128, 2448 IX86_BUILTIN_PACKUSWB128, 2449 2450 IX86_BUILTIN_PADDB128, 2451 IX86_BUILTIN_PADDW128, 2452 IX86_BUILTIN_PADDD128, 2453 IX86_BUILTIN_PADDQ128, 2454 IX86_BUILTIN_PADDSB128, 2455 IX86_BUILTIN_PADDSW128, 2456 IX86_BUILTIN_PADDUSB128, 2457 IX86_BUILTIN_PADDUSW128, 2458 IX86_BUILTIN_PSUBB128, 2459 IX86_BUILTIN_PSUBW128, 2460 IX86_BUILTIN_PSUBD128, 2461 IX86_BUILTIN_PSUBQ128, 2462 IX86_BUILTIN_PSUBSB128, 2463 IX86_BUILTIN_PSUBSW128, 2464 IX86_BUILTIN_PSUBUSB128, 2465 IX86_BUILTIN_PSUBUSW128, 2466 2467 IX86_BUILTIN_PAND128, 2468 IX86_BUILTIN_PANDN128, 2469 IX86_BUILTIN_POR128, 2470 IX86_BUILTIN_PXOR128, 2471 2472 IX86_BUILTIN_PAVGB128, 2473 IX86_BUILTIN_PAVGW128, 2474 2475 IX86_BUILTIN_PCMPEQB128, 2476 IX86_BUILTIN_PCMPEQW128, 2477 IX86_BUILTIN_PCMPEQD128, 2478 IX86_BUILTIN_PCMPGTB128, 2479 IX86_BUILTIN_PCMPGTW128, 2480 IX86_BUILTIN_PCMPGTD128, 2481 2482 IX86_BUILTIN_PEXTRW128, 2483 IX86_BUILTIN_PINSRW128, 2484 2485 IX86_BUILTIN_PMADDWD128, 2486 2487 IX86_BUILTIN_PMAXSW128, 2488 IX86_BUILTIN_PMAXUB128, 2489 IX86_BUILTIN_PMINSW128, 2490 IX86_BUILTIN_PMINUB128, 2491 2492 IX86_BUILTIN_PMULUDQ, 2493 IX86_BUILTIN_PMULUDQ128, 2494 IX86_BUILTIN_PMULHUW128, 2495 IX86_BUILTIN_PMULHW128, 2496 IX86_BUILTIN_PMULLW128, 2497 2498 IX86_BUILTIN_PSADBW128, 2499 IX86_BUILTIN_PSHUFHW, 2500 IX86_BUILTIN_PSHUFLW, 2501 IX86_BUILTIN_PSHUFD, 2502 2503 IX86_BUILTIN_PSLLW128, 2504 IX86_BUILTIN_PSLLD128, 2505 IX86_BUILTIN_PSLLQ128, 2506 IX86_BUILTIN_PSRAW128, 2507 IX86_BUILTIN_PSRAD128, 2508 IX86_BUILTIN_PSRLW128, 2509 IX86_BUILTIN_PSRLD128, 2510 IX86_BUILTIN_PSRLQ128, 2511 IX86_BUILTIN_PSLLDQI128, 2512 IX86_BUILTIN_PSLLWI128, 2513 IX86_BUILTIN_PSLLDI128, 2514 IX86_BUILTIN_PSLLQI128, 2515 IX86_BUILTIN_PSRAWI128, 2516 IX86_BUILTIN_PSRADI128, 2517 IX86_BUILTIN_PSRLDQI128, 2518 IX86_BUILTIN_PSRLWI128, 2519 IX86_BUILTIN_PSRLDI128, 2520 IX86_BUILTIN_PSRLQI128, 2521 2522 IX86_BUILTIN_PUNPCKHBW128, 2523 IX86_BUILTIN_PUNPCKHWD128, 2524 IX86_BUILTIN_PUNPCKHDQ128, 2525 IX86_BUILTIN_PUNPCKHQDQ128, 2526 IX86_BUILTIN_PUNPCKLBW128, 2527 IX86_BUILTIN_PUNPCKLWD128, 2528 IX86_BUILTIN_PUNPCKLDQ128, 2529 IX86_BUILTIN_PUNPCKLQDQ128, 2530 2531 IX86_BUILTIN_CLFLUSH, 2532 IX86_BUILTIN_MFENCE, 2533 IX86_BUILTIN_LFENCE, 2534 2535 /* Prescott New Instructions. */ 2536 IX86_BUILTIN_ADDSUBPS, 2537 IX86_BUILTIN_HADDPS, 2538 IX86_BUILTIN_HSUBPS, 2539 IX86_BUILTIN_MOVSHDUP, 2540 IX86_BUILTIN_MOVSLDUP, 2541 IX86_BUILTIN_ADDSUBPD, 2542 IX86_BUILTIN_HADDPD, 2543 IX86_BUILTIN_HSUBPD, 2544 IX86_BUILTIN_LOADDDUP, 2545 IX86_BUILTIN_MOVDDUP, 2546 IX86_BUILTIN_LDDQU, 2547 2548 IX86_BUILTIN_MONITOR, 2549 IX86_BUILTIN_MWAIT, 2550 2551 IX86_BUILTIN_MAX 2552}; 2553 2554/* Max number of args passed in registers. If this is more than 3, we will 2555 have problems with ebx (register #4), since it is a caller save register and 2556 is also used as the pic register in ELF. So for now, don't allow more than 2557 3 registers to be passed in registers. */ 2558 2559#define REGPARM_MAX (TARGET_64BIT ? 6 : 3) 2560 2561#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) 2562 2563#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 2564 2565 2566/* Specify the machine mode that this machine uses 2567 for the index in the tablejump instruction. */ 2568#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) 2569 2570/* Define as C expression which evaluates to nonzero if the tablejump 2571 instruction expects the table to contain offsets from the address of the 2572 table. 2573 Do not define this if the table should contain absolute addresses. */ 2574/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2575 2576/* Define this as 1 if `char' should by default be signed; else as 0. */ 2577#define DEFAULT_SIGNED_CHAR 1 2578 2579/* Number of bytes moved into a data cache for a single prefetch operation. */ 2580#define PREFETCH_BLOCK ix86_cost->prefetch_block 2581 2582/* Number of prefetch operations that can be done in parallel. */ 2583#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches 2584 2585/* Max number of bytes we can move from memory to memory 2586 in one reasonably fast instruction. */ 2587#define MOVE_MAX 16 2588 2589/* MOVE_MAX_PIECES is the number of bytes at a time which we can 2590 move efficiently, as opposed to MOVE_MAX which is the maximum 2591 number of bytes we can move with a single instruction. */ 2592#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 2593 2594/* If a memory-to-memory move would take MOVE_RATIO or more simple 2595 move-instruction pairs, we will do a movstr or libcall instead. 2596 Increasing the value will always make code faster, but eventually 2597 incurs high cost in increased code size. 2598 2599 If you don't define this, a reasonable default is used. */ 2600 2601#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) 2602 2603/* Define if shifts truncate the shift count 2604 which implies one can omit a sign-extension or zero-extension 2605 of a shift count. */ 2606/* On i386, shifts do truncate the count. But bit opcodes don't. */ 2607 2608/* #define SHIFT_COUNT_TRUNCATED */ 2609 2610/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2611 is done just by pretending it is already truncated. */ 2612#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2613 2614/* When a prototype says `char' or `short', really pass an `int'. 2615 (The 386 can't easily push less than an int.) */ 2616 2617#define PROMOTE_PROTOTYPES 1 2618 2619/* A macro to update M and UNSIGNEDP when an object whose type is 2620 TYPE and which has the specified mode and signedness is to be 2621 stored in a register. This macro is only called when TYPE is a 2622 scalar type. 2623 2624 On i386 it is sometimes useful to promote HImode and QImode 2625 quantities to SImode. The choice depends on target type. */ 2626 2627#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 2628do { \ 2629 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 2630 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 2631 (MODE) = SImode; \ 2632} while (0) 2633 2634/* Specify the machine mode that pointers have. 2635 After generation of rtl, the compiler makes no further distinction 2636 between pointers and any other objects of this machine mode. */ 2637#define Pmode (TARGET_64BIT ? DImode : SImode) 2638 2639/* A function address in a call instruction 2640 is a byte address (for indexing purposes) 2641 so give the MEM rtx a byte's mode. */ 2642#define FUNCTION_MODE QImode 2643 2644/* A C expression for the cost of moving data from a register in class FROM to 2645 one in class TO. The classes are expressed using the enumeration values 2646 such as `GENERAL_REGS'. A value of 2 is the default; other values are 2647 interpreted relative to that. 2648 2649 It is not required that the cost always equal 2 when FROM is the same as TO; 2650 on some machines it is expensive to move between registers if they are not 2651 general registers. */ 2652 2653#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2654 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 2655 2656/* A C expression for the cost of moving data of mode M between a 2657 register and memory. A value of 2 is the default; this cost is 2658 relative to those in `REGISTER_MOVE_COST'. 2659 2660 If moving between registers and memory is more expensive than 2661 between two registers, you should define this macro to express the 2662 relative cost. */ 2663 2664#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 2665 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 2666 2667/* A C expression for the cost of a branch instruction. A value of 1 2668 is the default; other values are interpreted relative to that. */ 2669 2670#define BRANCH_COST ix86_branch_cost 2671 2672/* Define this macro as a C expression which is nonzero if accessing 2673 less than a word of memory (i.e. a `char' or a `short') is no 2674 faster than accessing a word of memory, i.e., if such access 2675 require more than one instruction or if there is no difference in 2676 cost between byte and (aligned) word loads. 2677 2678 When this macro is not defined, the compiler will access a field by 2679 finding the smallest containing object; when it is defined, a 2680 fullword load will be used if alignment permits. Unless bytes 2681 accesses are faster than word accesses, using word accesses is 2682 preferable since it may eliminate subsequent memory access if 2683 subsequent accesses occur to other fields in the same word of the 2684 structure, but to different bytes. */ 2685 2686#define SLOW_BYTE_ACCESS 0 2687 2688/* Nonzero if access to memory by shorts is slow and undesirable. */ 2689#define SLOW_SHORT_ACCESS 0 2690 2691/* Define this macro to be the value 1 if unaligned accesses have a 2692 cost many times greater than aligned accesses, for example if they 2693 are emulated in a trap handler. 2694 2695 When this macro is nonzero, the compiler will act as if 2696 `STRICT_ALIGNMENT' were nonzero when generating code for block 2697 moves. This can cause significantly more instructions to be 2698 produced. Therefore, do not set this macro nonzero if unaligned 2699 accesses only add a cycle or two to the time for a memory access. 2700 2701 If the value of this macro is always zero, it need not be defined. */ 2702 2703/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2704 2705/* Define this macro if it is as good or better to call a constant 2706 function address than to call an address kept in a register. 2707 2708 Desirable on the 386 because a CALL with a constant address is 2709 faster than one with a register address. */ 2710 2711#define NO_FUNCTION_CSE 2712 2713/* Define this macro if it is as good or better for a function to call 2714 itself with an explicit address than to call an address kept in a 2715 register. */ 2716 2717#define NO_RECURSIVE_FUNCTION_CSE 2718 2719/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2720 return the mode to be used for the comparison. 2721 2722 For floating-point equality comparisons, CCFPEQmode should be used. 2723 VOIDmode should be used in all other cases. 2724 2725 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2726 possible, to allow for more combinations. */ 2727 2728#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2729 2730/* Return nonzero if MODE implies a floating point inequality can be 2731 reversed. */ 2732 2733#define REVERSIBLE_CC_MODE(MODE) 1 2734 2735/* A C expression whose value is reversed condition code of the CODE for 2736 comparison done in CC_MODE mode. */ 2737#define REVERSE_CONDITION(CODE, MODE) \ 2738 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ 2739 : reverse_condition_maybe_unordered (CODE)) 2740 2741 2742/* Control the assembler format that we output, to the extent 2743 this does not vary between assemblers. */ 2744 2745/* How to refer to registers in assembler output. 2746 This sequence is indexed by compiler's hard-register-number (see above). */ 2747 2748/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" 2749 For non floating point regs, the following are the HImode names. 2750 2751 For float regs, the stack top is sometimes referred to as "%st(0)" 2752 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ 2753 2754#define HI_REGISTER_NAMES \ 2755{"ax","dx","cx","bx","si","di","bp","sp", \ 2756 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 2757 "argp", "flags", "fpsr", "dirflag", "frame", \ 2758 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2759 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ 2760 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2761 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 2762 2763#define REGISTER_NAMES HI_REGISTER_NAMES 2764 2765/* Table of additional register names to use in user input. */ 2766 2767#define ADDITIONAL_REGISTER_NAMES \ 2768{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2769 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2770 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2771 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2772 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2773 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2774 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ 2775 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } 2776 2777/* Note we are omitting these since currently I don't know how 2778to get gcc to use these, since they want the same but different 2779number as al, and ax. 2780*/ 2781 2782#define QI_REGISTER_NAMES \ 2783{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2784 2785/* These parallel the array above, and can be used to access bits 8:15 2786 of regs 0 through 3. */ 2787 2788#define QI_HIGH_REGISTER_NAMES \ 2789{"ah", "dh", "ch", "bh", } 2790 2791/* How to renumber registers for dbx and gdb. */ 2792 2793#define DBX_REGISTER_NUMBER(N) \ 2794 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2795 2796extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2797extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2798extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2799 2800/* Before the prologue, RA is at 0(%esp). */ 2801#define INCOMING_RETURN_ADDR_RTX \ 2802 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2803 2804/* After the prologue, RA is at -4(AP) in the current frame. */ 2805#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2806 ((COUNT) == 0 \ 2807 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2808 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2809 2810/* PC is dbx register 8; let's use that column for RA. */ 2811#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2812 2813/* Before the prologue, the top of the frame is at 4(%esp). */ 2814#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2815 2816/* Describe how we implement __builtin_eh_return. */ 2817#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2818#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2819 2820 2821/* Select a format to encode pointers in exception handling data. CODE 2822 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2823 true if the symbol may be affected by dynamic relocations. 2824 2825 ??? All x86 object file formats are capable of representing this. 2826 After all, the relocation needed is the same as for the call insn. 2827 Whether or not a particular assembler allows us to enter such, I 2828 guess we'll have to see. */ 2829#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2830 (flag_pic \ 2831 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 2832 : DW_EH_PE_absptr) 2833 2834/* This is how to output an insn to push a register on the stack. 2835 It need not be very fast code. */ 2836 2837#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2838do { \ 2839 if (TARGET_64BIT) \ 2840 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2841 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2842 else \ 2843 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2844} while (0) 2845 2846/* This is how to output an insn to pop a register from the stack. 2847 It need not be very fast code. */ 2848 2849#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2850do { \ 2851 if (TARGET_64BIT) \ 2852 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2853 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2854 else \ 2855 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2856} while (0) 2857 2858/* This is how to output an element of a case-vector that is absolute. */ 2859 2860#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2861 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2862 2863/* This is how to output an element of a case-vector that is relative. */ 2864 2865#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2866 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2867 2868/* Under some conditions we need jump tables in the text section, because 2869 the assembler cannot handle label differences between sections. */ 2870 2871#define JUMP_TABLES_IN_TEXT_SECTION \ 2872 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) 2873 2874/* A C statement that outputs an address constant appropriate to 2875 for DWARF debugging. */ 2876 2877#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ 2878 i386_dwarf_output_addr_const ((FILE), (X)) 2879 2880/* Emit a dtp-relative reference to a TLS variable. */ 2881 2882#ifdef HAVE_AS_TLS 2883#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ 2884 i386_output_dwarf_dtprel (FILE, SIZE, X) 2885#endif 2886 2887/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2888 and switch back. For x86 we do this only to save a few bytes that 2889 would otherwise be unused in the text section. */ 2890#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2891 asm (SECTION_OP "\n\t" \ 2892 "call " USER_LABEL_PREFIX #FUNC "\n" \ 2893 TEXT_SECTION_ASM_OP); 2894 2895/* Print operand X (an rtx) in assembler syntax to file FILE. 2896 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2897 Effect of various CODE letters is described in i386.c near 2898 print_operand function. */ 2899 2900#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2901 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') 2902 2903#define PRINT_OPERAND(FILE, X, CODE) \ 2904 print_operand ((FILE), (X), (CODE)) 2905 2906#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2907 print_operand_address ((FILE), (ADDR)) 2908 2909#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2910do { \ 2911 if (! output_addr_const_extra (FILE, (X))) \ 2912 goto FAIL; \ 2913} while (0); 2914 2915/* a letter which is not needed by the normal asm syntax, which 2916 we can use for operand syntax in the extended asm */ 2917 2918#define ASM_OPERAND_LETTER '#' 2919#define RET return "" 2920#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) 2921 2922/* Define the codes that are matched by predicates in i386.c. */ 2923 2924#define PREDICATE_CODES \ 2925 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ 2926 SYMBOL_REF, LABEL_REF, CONST}}, \ 2927 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 2928 SYMBOL_REF, LABEL_REF, CONST}}, \ 2929 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ 2930 SYMBOL_REF, LABEL_REF, CONST}}, \ 2931 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ 2932 SYMBOL_REF, LABEL_REF, CONST}}, \ 2933 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 2934 SYMBOL_REF, LABEL_REF, CONST}}, \ 2935 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ 2936 SYMBOL_REF, LABEL_REF, CONST}}, \ 2937 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 2938 SYMBOL_REF, LABEL_REF}}, \ 2939 {"shiftdi_operand", {SUBREG, REG, MEM}}, \ 2940 {"const_int_1_31_operand", {CONST_INT}}, \ 2941 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 2942 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 2943 LABEL_REF, SUBREG, REG, MEM}}, \ 2944 {"pic_symbolic_operand", {CONST}}, \ 2945 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ 2946 {"sibcall_insn_operand", {REG, SUBREG, SYMBOL_REF}}, \ 2947 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ 2948 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ 2949 {"const1_operand", {CONST_INT}}, \ 2950 {"const248_operand", {CONST_INT}}, \ 2951 {"const_0_to_3_operand", {CONST_INT}}, \ 2952 {"const_0_to_7_operand", {CONST_INT}}, \ 2953 {"const_0_to_15_operand", {CONST_INT}}, \ 2954 {"const_0_to_255_operand", {CONST_INT}}, \ 2955 {"incdec_operand", {CONST_INT}}, \ 2956 {"mmx_reg_operand", {REG}}, \ 2957 {"reg_no_sp_operand", {SUBREG, REG}}, \ 2958 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ 2959 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ 2960 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ 2961 {"index_register_operand", {SUBREG, REG}}, \ 2962 {"flags_reg_operand", {REG}}, \ 2963 {"q_regs_operand", {SUBREG, REG}}, \ 2964 {"non_q_regs_operand", {SUBREG, REG}}, \ 2965 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ 2966 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ 2967 GE, UNGE, LTGT, UNEQ}}, \ 2968 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ 2969 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ 2970 }}, \ 2971 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ 2972 GTU, UNORDERED, ORDERED, UNLE, UNLT, \ 2973 UNGE, UNGT, LTGT, UNEQ }}, \ 2974 {"ix86_carry_flag_operator", {LTU, LT, UNLT, GT, UNGT, LE, UNLE, \ 2975 GE, UNGE, LTGT, UNEQ}}, \ 2976 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ 2977 {"ext_register_operand", {SUBREG, REG}}, \ 2978 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ 2979 {"mult_operator", {MULT}}, \ 2980 {"div_operator", {DIV}}, \ 2981 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ 2982 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ 2983 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ 2984 LSHIFTRT, ROTATERT}}, \ 2985 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ 2986 {"memory_displacement_operand", {MEM}}, \ 2987 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 2988 LABEL_REF, SUBREG, REG, MEM, AND}}, \ 2989 {"long_memory_operand", {MEM}}, \ 2990 {"tls_symbolic_operand", {SYMBOL_REF}}, \ 2991 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \ 2992 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \ 2993 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \ 2994 {"local_exec_symbolic_operand", {SYMBOL_REF}}, \ 2995 {"any_fp_register_operand", {REG}}, \ 2996 {"register_and_not_any_fp_reg_operand", {REG}}, \ 2997 {"fp_register_operand", {REG}}, \ 2998 {"register_and_not_fp_reg_operand", {REG}}, \ 2999 {"zero_extended_scalar_load_operand", {MEM}}, \ 3000 {"vector_move_operand", {CONST_VECTOR, SUBREG, REG, MEM}}, \ 3001 {"no_seg_address_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 3002 LABEL_REF, SUBREG, REG, MEM, PLUS, MULT}}, 3003 3004/* A list of predicates that do special things with modes, and so 3005 should not elicit warnings for VOIDmode match_operand. */ 3006 3007#define SPECIAL_MODE_PREDICATES \ 3008 "ext_register_operand", 3009 3010/* Which processor to schedule for. The cpu attribute defines a list that 3011 mirrors this list, so changes to i386.md must be made at the same time. */ 3012 3013enum processor_type 3014{ 3015 PROCESSOR_I386, /* 80386 */ 3016 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 3017 PROCESSOR_PENTIUM, 3018 PROCESSOR_PENTIUMPRO, 3019 PROCESSOR_K6, 3020 PROCESSOR_ATHLON, 3021 PROCESSOR_PENTIUM4, 3022 PROCESSOR_K8, 3023 PROCESSOR_max 3024}; 3025 3026extern enum processor_type ix86_tune; 3027extern const char *ix86_tune_string; 3028 3029extern enum processor_type ix86_arch; 3030extern const char *ix86_arch_string; 3031 3032enum fpmath_unit 3033{ 3034 FPMATH_387 = 1, 3035 FPMATH_SSE = 2 3036}; 3037 3038extern enum fpmath_unit ix86_fpmath; 3039extern const char *ix86_fpmath_string; 3040 3041enum tls_dialect 3042{ 3043 TLS_DIALECT_GNU, 3044 TLS_DIALECT_SUN 3045}; 3046 3047extern enum tls_dialect ix86_tls_dialect; 3048extern const char *ix86_tls_dialect_string; 3049 3050enum cmodel { 3051 CM_32, /* The traditional 32-bit ABI. */ 3052 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 3053 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 3054 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 3055 CM_LARGE, /* No assumptions. */ 3056 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */ 3057}; 3058 3059extern enum cmodel ix86_cmodel; 3060extern const char *ix86_cmodel_string; 3061 3062/* Size of the RED_ZONE area. */ 3063#define RED_ZONE_SIZE 128 3064/* Reserved area of the red zone for temporaries. */ 3065#define RED_ZONE_RESERVE 8 3066 3067enum asm_dialect { 3068 ASM_ATT, 3069 ASM_INTEL 3070}; 3071 3072extern const char *ix86_asm_string; 3073extern enum asm_dialect ix86_asm_dialect; 3074 3075extern int ix86_regparm; 3076extern const char *ix86_regparm_string; 3077 3078extern int ix86_preferred_stack_boundary; 3079extern const char *ix86_preferred_stack_boundary_string; 3080 3081extern int ix86_branch_cost; 3082extern const char *ix86_branch_cost_string; 3083 3084extern const char *ix86_debug_arg_string; 3085extern const char *ix86_debug_addr_string; 3086 3087/* Obsoleted by -f options. Remove before 3.2 ships. */ 3088extern const char *ix86_align_loops_string; 3089extern const char *ix86_align_jumps_string; 3090extern const char *ix86_align_funcs_string; 3091 3092/* Smallest class containing REGNO. */ 3093extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 3094 3095extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 3096extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 3097 3098/* To properly truncate FP values into integers, we need to set i387 control 3099 word. We can't emit proper mode switching code before reload, as spills 3100 generated by reload may truncate values incorrectly, but we still can avoid 3101 redundant computation of new control word by the mode switching pass. 3102 The fldcw instructions are still emitted redundantly, but this is probably 3103 not going to be noticeable problem, as most CPUs do have fast path for 3104 the sequence. 3105 3106 The machinery is to emit simple truncation instructions and split them 3107 before reload to instructions having USEs of two memory locations that 3108 are filled by this code to old and new control word. 3109 3110 Post-reload pass may be later used to eliminate the redundant fildcw if 3111 needed. */ 3112 3113enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; 3114 3115/* Define this macro if the port needs extra instructions inserted 3116 for mode switching in an optimizing compilation. */ 3117 3118#define OPTIMIZE_MODE_SWITCHING(ENTITY) ix86_optimize_mode_switching 3119 3120/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 3121 initializer for an array of integers. Each initializer element N 3122 refers to an entity that needs mode switching, and specifies the 3123 number of different modes that might need to be set for this 3124 entity. The position of the initializer in the initializer - 3125 starting counting at zero - determines the integer that is used to 3126 refer to the mode-switched entity in question. */ 3127 3128#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } 3129 3130/* ENTITY is an integer specifying a mode-switched entity. If 3131 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 3132 return an integer value not larger than the corresponding element 3133 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 3134 must be switched into prior to the execution of INSN. */ 3135 3136#define MODE_NEEDED(ENTITY, I) \ 3137 (GET_CODE (I) == CALL_INSN \ 3138 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ 3139 || GET_CODE (PATTERN (I)) == ASM_INPUT))\ 3140 ? FP_CW_UNINITIALIZED \ 3141 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ 3142 ? FP_CW_ANY \ 3143 : FP_CW_STORED) 3144 3145/* This macro specifies the order in which modes for ENTITY are 3146 processed. 0 is the highest priority. */ 3147 3148#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 3149 3150/* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 3151 is the set of hard registers live at the point where the insn(s) 3152 are to be inserted. */ 3153 3154#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 3155 ((MODE) == FP_CW_STORED \ 3156 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ 3157 assign_386_stack_local (HImode, 2)), 0\ 3158 : 0) 3159 3160/* Avoid renaming of stack registers, as doing so in combination with 3161 scheduling just increases amount of live registers at time and in 3162 the turn amount of fxch instructions needed. 3163 3164 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 3165 3166#define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 3167 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) 3168 3169 3170#define DLL_IMPORT_EXPORT_PREFIX '#' 3171 3172#define FASTCALL_PREFIX '@' 3173 3174struct machine_function GTY(()) 3175{ 3176 struct stack_local_entry *stack_locals; 3177 const char *some_ld_name; 3178 int save_varrargs_registers; 3179 int accesses_prev_frame; 3180 int optimize_mode_switching; 3181 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to 3182 determine the style used. */ 3183 int use_fast_prologue_epilogue; 3184 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed 3185 for. */ 3186 int use_fast_prologue_epilogue_nregs; 3187}; 3188 3189#define ix86_stack_locals (cfun->machine->stack_locals) 3190#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) 3191#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 3192 3193/* Control behavior of x86_file_start. */ 3194#define X86_FILE_START_VERSION_DIRECTIVE false 3195#define X86_FILE_START_FLTUSED false 3196 3197/* 3198Local variables: 3199version-control: t 3200End: 3201*/ 3202