constraints.md revision 169690 
1;; Constraint definitions for IA-32 and x86-64.
2;; Copyright (C) 2006 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 2, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING.  If not, write to
18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19;; Boston, MA 02110-1301, USA.
20
21;;; Unused letters:
22;;;     B     H           TU W   
23;;;           h jk          vw  z
24
25;; Integer register constraints.
26;; It is not necessary to define 'r' here.
27(define_register_constraint "R" "LEGACY_REGS"
28 "Legacy register---the eight integer registers available on all
29  i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
30  @code{si}, @code{di}, @code{bp}, @code{sp}).")
31
32(define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
33 "Any register accessible as @code{@var{r}l}.  In 32-bit mode, @code{a},
34  @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
35
36(define_register_constraint "Q" "Q_REGS"
37 "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
38  @code{c}, and @code{d}.")
39
40(define_register_constraint "l" "INDEX_REGS"
41 "@internal Any register that can be used as the index in a base+index
42  memory access: that is, any general register except the stack pointer.")
43
44(define_register_constraint "a" "AREG"
45 "The @code{a} register.")
46
47(define_register_constraint "b" "BREG"
48 "The @code{b} register.")
49
50(define_register_constraint "c" "CREG"
51 "The @code{c} register.")
52
53(define_register_constraint "d" "DREG"
54 "The @code{d} register.")
55
56(define_register_constraint "S" "SIREG"
57 "The @code{si} register.")
58
59(define_register_constraint "D" "DIREG"
60 "The @code{di} register.")
61
62(define_register_constraint "A" "AD_REGS"
63 "The @code{a} and @code{d} registers, as a pair (for instructions
64  that return half the result in one and half in the other).")
65
66;; Floating-point register constraints.
67(define_register_constraint "f"
68 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
69 "Any 80387 floating-point (stack) register.")
70
71(define_register_constraint "t"
72 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
73 "Top of 80387 floating-point stack (@code{%st(0)}).")
74
75(define_register_constraint "u"
76 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
77 "Second from top of 80387 floating-point stack (@code{%st(1)}).")
78
79;; Vector registers (also used for plain floating point nowadays).
80(define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
81 "Any MMX register.")
82
83(define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
84 "Any SSE register.")
85
86(define_register_constraint "Y" "TARGET_SSE2? SSE_REGS : NO_REGS"
87 "@internal Any SSE2 register.")
88
89;; Integer constant constraints.
90(define_constraint "I"
91  "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
92  (and (match_code "const_int")
93       (match_test "ival >= 0 && ival <= 31")))
94
95(define_constraint "J"
96  "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
97  (and (match_code "const_int")
98       (match_test "ival >= 0 && ival <= 63")))
99
100(define_constraint "K"
101  "Signed 8-bit integer constant."
102  (and (match_code "const_int")
103       (match_test "ival >= -128 && ival <= 127")))
104
105(define_constraint "L"
106  "@code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move."
107  (and (match_code "const_int")
108       (match_test "ival == 0xFF || ival == 0xFFFF")))
109
110(define_constraint "M"
111  "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
112  (and (match_code "const_int")
113       (match_test "ival >= 0 && ival <= 3")))
114
115(define_constraint "N"
116  "Unsigned 8-bit integer constant (for @code{in} and @code{out} 
117   instructions)."
118  (and (match_code "const_int")
119       (match_test "ival >= 0 && ival <= 255")))
120
121(define_constraint "O"
122  "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
123  (and (match_code "const_int")
124       (match_test "ival >= 0 && ival <= 127")))
125
126;; Floating-point constant constraints.
127;; We allow constants even if TARGET_80387 isn't set, because the
128;; stack register converter may need to load 0.0 into the function
129;; value register (top of stack).
130(define_constraint "G"
131  "Standard 80387 floating point constant."
132  (and (match_code "const_double")
133       (match_test "standard_80387_constant_p (op)")))
134
135;; This can theoretically be any mode's CONST0_RTX.
136(define_constraint "C"
137  "Standard SSE floating point constant."
138  (match_test "standard_sse_constant_p (op)"))
139
140;; Constant-or-symbol-reference constraints.
141
142(define_constraint "e"
143  "32-bit signed integer constant, or a symbolic reference known
144   to fit that range (for immediate operands in sign-extending x86-64
145   instructions)."
146  (match_operand 0 "x86_64_immediate_operand"))
147
148(define_constraint "Z"
149  "32-bit unsigned integer constant, or a symbolic reference known
150   to fit that range (for immediate operands in zero-extending x86-64
151   instructions)."
152  (match_operand 0 "x86_64_zext_immediate_operand"))
153