mips-dis.c revision 208737
1/* Print mips instructions for GDB, the GNU debugger, or for objdump. 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2005 4 Free Software Foundation, Inc. 5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). 6 7 This file is part of GDB, GAS, and the GNU binutils. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; if not, write to the Free Software 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24#include "sysdep.h" 25#include "dis-asm.h" 26#include "libiberty.h" 27#include "opcode/mips.h" 28#include "opintl.h" 29 30/* FIXME: These are needed to figure out if the code is mips16 or 31 not. The low bit of the address is often a good indicator. No 32 symbol table is available when this code runs out in an embedded 33 system as when it is used for disassembler support in a monitor. */ 34 35#if !defined(EMBEDDED_ENV) 36#define SYMTAB_AVAILABLE 1 37#include "elf-bfd.h" 38#include "elf/mips.h" 39#endif 40 41/* Mips instructions are at maximum this many bytes long. */ 42#define INSNLEN 4 43 44/* Generate Octeon/MIPS unaligned load and store instructions. */ 45#ifdef INCLUDE_OCTEON_USEUN 46int octeon_use_unalign = 1; 47#else 48int octeon_use_unalign = 0; 49#endif 50 51 52/* FIXME: These should be shared with gdb somehow. */ 53 54struct mips_cp0sel_name 55{ 56 unsigned int cp0reg; 57 unsigned int sel; 58 const char * const name; 59}; 60 61/* The mips16 register names. */ 62static const char * const mips16_reg_names[] = 63{ 64 "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" 65}; 66 67static const char * const mips_gpr_names_numeric[32] = 68{ 69 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 70 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 71 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 72 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 73}; 74 75static const char * const mips_gpr_names_oldabi[32] = 76{ 77 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 78 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 79 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 80 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 81}; 82 83static const char * const mips_gpr_names_newabi[32] = 84{ 85 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 86 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 87 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 88 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 89}; 90 91static const char * const mips_fpr_names_numeric[32] = 92{ 93 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 94 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 95 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 96 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" 97}; 98 99static const char * const mips_fpr_names_32[32] = 100{ 101 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", 102 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", 103 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", 104 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" 105}; 106 107static const char * const mips_fpr_names_n32[32] = 108{ 109 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", 110 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 111 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", 112 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" 113}; 114 115static const char * const mips_fpr_names_64[32] = 116{ 117 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", 118 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", 119 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", 120 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" 121}; 122 123static const char * const mips_cp0_names_numeric[32] = 124{ 125 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 126 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 127 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 128 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 129}; 130 131static const char * const mips_cp0_names_mips3264[32] = 132{ 133 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 134 "c0_context", "c0_pagemask", "c0_wired", "$7", 135 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 136 "c0_status", "c0_cause", "c0_epc", "c0_prid", 137 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 138 "c0_xcontext", "$21", "$22", "c0_debug", 139 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 140 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 141}; 142 143static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = 144{ 145 { 16, 1, "c0_config1" }, 146 { 16, 2, "c0_config2" }, 147 { 16, 3, "c0_config3" }, 148 { 18, 1, "c0_watchlo,1" }, 149 { 18, 2, "c0_watchlo,2" }, 150 { 18, 3, "c0_watchlo,3" }, 151 { 18, 4, "c0_watchlo,4" }, 152 { 18, 5, "c0_watchlo,5" }, 153 { 18, 6, "c0_watchlo,6" }, 154 { 18, 7, "c0_watchlo,7" }, 155 { 19, 1, "c0_watchhi,1" }, 156 { 19, 2, "c0_watchhi,2" }, 157 { 19, 3, "c0_watchhi,3" }, 158 { 19, 4, "c0_watchhi,4" }, 159 { 19, 5, "c0_watchhi,5" }, 160 { 19, 6, "c0_watchhi,6" }, 161 { 19, 7, "c0_watchhi,7" }, 162 { 25, 1, "c0_perfcnt,1" }, 163 { 25, 2, "c0_perfcnt,2" }, 164 { 25, 3, "c0_perfcnt,3" }, 165 { 25, 4, "c0_perfcnt,4" }, 166 { 25, 5, "c0_perfcnt,5" }, 167 { 25, 6, "c0_perfcnt,6" }, 168 { 25, 7, "c0_perfcnt,7" }, 169 { 27, 1, "c0_cacheerr,1" }, 170 { 27, 2, "c0_cacheerr,2" }, 171 { 27, 3, "c0_cacheerr,3" }, 172 { 28, 1, "c0_datalo" }, 173 { 29, 1, "c0_datahi" } 174}; 175 176static const char * const mips_cp0_names_mips3264r2[32] = 177{ 178 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 179 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 180 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 181 "c0_status", "c0_cause", "c0_epc", "c0_prid", 182 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 183 "c0_xcontext", "$21", "$22", "c0_debug", 184 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", 185 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 186}; 187 188static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = 189{ 190 { 4, 1, "c0_contextconfig" }, 191 { 5, 1, "c0_pagegrain" }, 192 { 12, 1, "c0_intctl" }, 193 { 12, 2, "c0_srsctl" }, 194 { 12, 3, "c0_srsmap" }, 195 { 15, 1, "c0_ebase" }, 196 { 16, 1, "c0_config1" }, 197 { 16, 2, "c0_config2" }, 198 { 16, 3, "c0_config3" }, 199 { 18, 1, "c0_watchlo,1" }, 200 { 18, 2, "c0_watchlo,2" }, 201 { 18, 3, "c0_watchlo,3" }, 202 { 18, 4, "c0_watchlo,4" }, 203 { 18, 5, "c0_watchlo,5" }, 204 { 18, 6, "c0_watchlo,6" }, 205 { 18, 7, "c0_watchlo,7" }, 206 { 19, 1, "c0_watchhi,1" }, 207 { 19, 2, "c0_watchhi,2" }, 208 { 19, 3, "c0_watchhi,3" }, 209 { 19, 4, "c0_watchhi,4" }, 210 { 19, 5, "c0_watchhi,5" }, 211 { 19, 6, "c0_watchhi,6" }, 212 { 19, 7, "c0_watchhi,7" }, 213 { 23, 1, "c0_tracecontrol" }, 214 { 23, 2, "c0_tracecontrol2" }, 215 { 23, 3, "c0_usertracedata" }, 216 { 23, 4, "c0_tracebpc" }, 217 { 25, 1, "c0_perfcnt,1" }, 218 { 25, 2, "c0_perfcnt,2" }, 219 { 25, 3, "c0_perfcnt,3" }, 220 { 25, 4, "c0_perfcnt,4" }, 221 { 25, 5, "c0_perfcnt,5" }, 222 { 25, 6, "c0_perfcnt,6" }, 223 { 25, 7, "c0_perfcnt,7" }, 224 { 27, 1, "c0_cacheerr,1" }, 225 { 27, 2, "c0_cacheerr,2" }, 226 { 27, 3, "c0_cacheerr,3" }, 227 { 28, 1, "c0_datalo" }, 228 { 28, 2, "c0_taglo1" }, 229 { 28, 3, "c0_datalo1" }, 230 { 28, 4, "c0_taglo2" }, 231 { 28, 5, "c0_datalo2" }, 232 { 28, 6, "c0_taglo3" }, 233 { 28, 7, "c0_datalo3" }, 234 { 29, 1, "c0_datahi" }, 235 { 29, 2, "c0_taghi1" }, 236 { 29, 3, "c0_datahi1" }, 237 { 29, 4, "c0_taghi2" }, 238 { 29, 5, "c0_datahi2" }, 239 { 29, 6, "c0_taghi3" }, 240 { 29, 7, "c0_datahi3" }, 241}; 242 243/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ 244static const char * const mips_cp0_names_sb1[32] = 245{ 246 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 247 "c0_context", "c0_pagemask", "c0_wired", "$7", 248 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 249 "c0_status", "c0_cause", "c0_epc", "c0_prid", 250 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", 251 "c0_xcontext", "$21", "$22", "c0_debug", 252 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", 253 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", 254}; 255 256static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = 257{ 258 { 16, 1, "c0_config1" }, 259 { 18, 1, "c0_watchlo,1" }, 260 { 19, 1, "c0_watchhi,1" }, 261 { 22, 0, "c0_perftrace" }, 262 { 23, 3, "c0_edebug" }, 263 { 25, 1, "c0_perfcnt,1" }, 264 { 25, 2, "c0_perfcnt,2" }, 265 { 25, 3, "c0_perfcnt,3" }, 266 { 25, 4, "c0_perfcnt,4" }, 267 { 25, 5, "c0_perfcnt,5" }, 268 { 25, 6, "c0_perfcnt,6" }, 269 { 25, 7, "c0_perfcnt,7" }, 270 { 26, 1, "c0_buserr_pa" }, 271 { 27, 1, "c0_cacheerr_d" }, 272 { 27, 3, "c0_cacheerr_d_pa" }, 273 { 28, 1, "c0_datalo_i" }, 274 { 28, 2, "c0_taglo_d" }, 275 { 28, 3, "c0_datalo_d" }, 276 { 29, 1, "c0_datahi_i" }, 277 { 29, 2, "c0_taghi_d" }, 278 { 29, 3, "c0_datahi_d" }, 279}; 280 281static const char * const mips_cp0_names_octeon[32] = { 282 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", 283 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", 284 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", 285 "c0_status", "c0_cause", "c0_epc", "c0_prid", 286 "c0_config", "$17", "c0_watchlo", "c0_watchhi", 287 "c0_xcontext", "$21", "c0_mdebug", "c0_debug", 288 "c0_depc", "c0_perfcnt", "$26", "c0_cacheerr", 289 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", 290}; 291 292static const struct mips_cp0sel_name mips_cp0sel_names_octeon[] = { 293 { 5, 1, "c0_pagegrain" }, 294 { 9, 6, "c0_cvmcount" }, 295 { 9, 7, "c0_cvmctl" }, 296 { 11, 7, "c0_cvmmemctl" }, 297 { 12, 1, "c0_intctl" }, 298 { 12, 2, "c0_srsctl" }, 299 { 15, 1, "c0_ebase" }, 300 { 16, 1, "c0_config1", }, 301 { 16, 2, "c0_config2", }, 302 { 16, 3, "c0_config3", }, 303 { 18, 1, "c0_watchlo,1" }, 304 { 19, 1, "c0_watchhi,1" }, 305 { 25, 2, "c0_perfcnt,2" }, 306 { 27, 1, "c0_cacheerr,1" }, 307 { 28, 3, "c0_datalo" }, 308 { 29, 3, "c0_datahi" }, 309}; 310 311static const char * const mips_hwr_names_numeric[32] = 312{ 313 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 314 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 315 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 316 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 317}; 318 319static const char * const mips_hwr_names_mips3264r2[32] = 320{ 321 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", 322 "$4", "$5", "$6", "$7", 323 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 324 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 325 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" 326}; 327 328struct mips_abi_choice 329{ 330 const char * name; 331 const char * const *gpr_names; 332 const char * const *fpr_names; 333}; 334 335struct mips_abi_choice mips_abi_choices[] = 336{ 337 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, 338 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, 339 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, 340 { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, 341}; 342 343struct mips_arch_choice 344{ 345 const char *name; 346 int bfd_mach_valid; 347 unsigned long bfd_mach; 348 int processor; 349 int isa; 350 const char * const *cp0_names; 351 const struct mips_cp0sel_name *cp0sel_names; 352 unsigned int cp0sel_names_len; 353 const char * const *hwr_names; 354}; 355 356const struct mips_arch_choice mips_arch_choices[] = 357{ 358 { "numeric", 0, 0, 0, 0, 359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 360 361 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 362 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 363 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 364 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 365 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 366 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 367 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 368 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 369 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 370 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 371 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 372 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 373 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 374 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 375 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 376 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 377 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 378 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 379 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 380 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 381 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 382 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 383 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 384 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 385 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 386 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 387 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 388 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 389 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 390 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 391 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 392 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 393 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 394 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 395 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 396 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 397 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 398 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 399 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 400 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 401 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 402 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 403 404 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. 405 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See 406 _MIPS32 Architecture For Programmers Volume I: Introduction to the 407 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), 408 page 1. */ 409 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, 410 ISA_MIPS32 | INSN_MIPS16 | INSN_DSP, 411 mips_cp0_names_mips3264, 412 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 413 mips_hwr_names_numeric }, 414 415 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, 416 ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT, 417 mips_cp0_names_mips3264r2, 418 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 419 mips_hwr_names_mips3264r2 }, 420 421 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ 422 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, 423 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP, 424 mips_cp0_names_mips3264, 425 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), 426 mips_hwr_names_numeric }, 427 428 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, 429 ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP, 430 mips_cp0_names_mips3264r2, 431 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), 432 mips_hwr_names_mips3264r2 }, 433 434 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, 435 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, 436 mips_cp0_names_sb1, 437 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), 438 mips_hwr_names_numeric }, 439 440 { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, 441 ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_octeon, 442 mips_cp0sel_names_octeon, ARRAY_SIZE (mips_cp0sel_names_octeon), 443 mips_hwr_names_numeric }, 444 445 /* This entry, mips16, is here only for ISA/processor selection; do 446 not print its name. */ 447 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, 448 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, 449}; 450 451/* ISA and processor type to disassemble for, and register names to use. 452 set_default_mips_dis_options and parse_mips_dis_options fill in these 453 values. */ 454static int mips_processor; 455static int mips_isa; 456static const char * const *mips_gpr_names; 457static const char * const *mips_fpr_names; 458static const char * const *mips_cp0_names; 459static const struct mips_cp0sel_name *mips_cp0sel_names; 460static int mips_cp0sel_names_len; 461static const char * const *mips_hwr_names; 462 463/* Other options */ 464static int no_aliases; /* If set disassemble as most general inst. */ 465 466static const struct mips_abi_choice * 467choose_abi_by_name (const char *name, unsigned int namelen) 468{ 469 const struct mips_abi_choice *c; 470 unsigned int i; 471 472 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) 473 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 474 && strlen (mips_abi_choices[i].name) == namelen) 475 c = &mips_abi_choices[i]; 476 477 return c; 478} 479 480static const struct mips_arch_choice * 481choose_arch_by_name (const char *name, unsigned int namelen) 482{ 483 const struct mips_arch_choice *c = NULL; 484 unsigned int i; 485 486 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 487 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 488 && strlen (mips_arch_choices[i].name) == namelen) 489 c = &mips_arch_choices[i]; 490 491 return c; 492} 493 494static const struct mips_arch_choice * 495choose_arch_by_number (unsigned long mach) 496{ 497 static unsigned long hint_bfd_mach; 498 static const struct mips_arch_choice *hint_arch_choice; 499 const struct mips_arch_choice *c; 500 unsigned int i; 501 502 /* We optimize this because even if the user specifies no 503 flags, this will be done for every instruction! */ 504 if (hint_bfd_mach == mach 505 && hint_arch_choice != NULL 506 && hint_arch_choice->bfd_mach == hint_bfd_mach) 507 return hint_arch_choice; 508 509 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) 510 { 511 if (mips_arch_choices[i].bfd_mach_valid 512 && mips_arch_choices[i].bfd_mach == mach) 513 { 514 c = &mips_arch_choices[i]; 515 hint_bfd_mach = mach; 516 hint_arch_choice = c; 517 } 518 } 519 return c; 520} 521 522/* Check if the object uses NewABI conventions. */ 523 524static int 525is_newabi (Elf_Internal_Ehdr *header) 526{ 527 /* There are no old-style ABIs which use 64-bit ELF. */ 528 if (header->e_ident[EI_CLASS] == ELFCLASS64) 529 return 1; 530 531 /* If a 32-bit ELF file, n32 is a new-style ABI. */ 532 if ((header->e_flags & EF_MIPS_ABI2) != 0) 533 return 1; 534 535 return 0; 536} 537 538static void 539set_default_mips_dis_options (struct disassemble_info *info) 540{ 541 const struct mips_arch_choice *chosen_arch; 542 543 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, 544 and numeric FPR, CP0 register, and HWR names. */ 545 mips_isa = ISA_MIPS3; 546 mips_processor = CPU_R3000; 547 mips_gpr_names = mips_gpr_names_oldabi; 548 mips_fpr_names = mips_fpr_names_numeric; 549 mips_cp0_names = mips_cp0_names_numeric; 550 mips_cp0sel_names = NULL; 551 mips_cp0sel_names_len = 0; 552 mips_hwr_names = mips_hwr_names_numeric; 553 no_aliases = 0; 554 555 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ 556 if (info->flavour == bfd_target_elf_flavour && info->section != NULL) 557 { 558 Elf_Internal_Ehdr *header; 559 560 header = elf_elfheader (info->section->owner); 561 if (is_newabi (header)) 562 mips_gpr_names = mips_gpr_names_newabi; 563 } 564 565 /* Set ISA, architecture, and cp0 register names as best we can. */ 566#if ! SYMTAB_AVAILABLE 567 /* This is running out on a target machine, not in a host tool. 568 FIXME: Where does mips_target_info come from? */ 569 target_processor = mips_target_info.processor; 570 mips_isa = mips_target_info.isa; 571#else 572 chosen_arch = choose_arch_by_number (info->mach); 573 if (chosen_arch != NULL) 574 { 575 mips_processor = chosen_arch->processor; 576 mips_isa = chosen_arch->isa; 577 mips_cp0_names = chosen_arch->cp0_names; 578 mips_cp0sel_names = chosen_arch->cp0sel_names; 579 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 580 mips_hwr_names = chosen_arch->hwr_names; 581 } 582#endif 583} 584 585static void 586parse_mips_dis_option (const char *option, unsigned int len) 587{ 588 unsigned int i, optionlen, vallen; 589 const char *val; 590 const struct mips_abi_choice *chosen_abi; 591 const struct mips_arch_choice *chosen_arch; 592 593 if (strcmp ("octeon-useun", option) == 0) 594 { 595 octeon_use_unalign = 1; 596 return; 597 } 598 if (strcmp ("no-octeon-useun", option) == 0) 599 { 600 octeon_use_unalign = 0; 601 return; 602 } 603 604 /* Try to match options that are simple flags */ 605 if (strncmp (option, "no-aliases", 10) == 0) 606 { 607 no_aliases = 1; 608 return; 609 } 610 611 /* Look for the = that delimits the end of the option name. */ 612 for (i = 0; i < len; i++) 613 if (option[i] == '=') 614 break; 615 616 if (i == 0) /* Invalid option: no name before '='. */ 617 return; 618 if (i == len) /* Invalid option: no '='. */ 619 return; 620 if (i == (len - 1)) /* Invalid option: no value after '='. */ 621 return; 622 623 optionlen = i; 624 val = option + (optionlen + 1); 625 vallen = len - (optionlen + 1); 626 627 if (strncmp ("gpr-names", option, optionlen) == 0 628 && strlen ("gpr-names") == optionlen) 629 { 630 chosen_abi = choose_abi_by_name (val, vallen); 631 if (chosen_abi != NULL) 632 mips_gpr_names = chosen_abi->gpr_names; 633 return; 634 } 635 636 if (strncmp ("fpr-names", option, optionlen) == 0 637 && strlen ("fpr-names") == optionlen) 638 { 639 chosen_abi = choose_abi_by_name (val, vallen); 640 if (chosen_abi != NULL) 641 mips_fpr_names = chosen_abi->fpr_names; 642 return; 643 } 644 645 if (strncmp ("cp0-names", option, optionlen) == 0 646 && strlen ("cp0-names") == optionlen) 647 { 648 chosen_arch = choose_arch_by_name (val, vallen); 649 if (chosen_arch != NULL) 650 { 651 mips_cp0_names = chosen_arch->cp0_names; 652 mips_cp0sel_names = chosen_arch->cp0sel_names; 653 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 654 } 655 return; 656 } 657 658 if (strncmp ("hwr-names", option, optionlen) == 0 659 && strlen ("hwr-names") == optionlen) 660 { 661 chosen_arch = choose_arch_by_name (val, vallen); 662 if (chosen_arch != NULL) 663 mips_hwr_names = chosen_arch->hwr_names; 664 return; 665 } 666 667 if (strncmp ("reg-names", option, optionlen) == 0 668 && strlen ("reg-names") == optionlen) 669 { 670 /* We check both ABI and ARCH here unconditionally, so 671 that "numeric" will do the desirable thing: select 672 numeric register names for all registers. Other than 673 that, a given name probably won't match both. */ 674 chosen_abi = choose_abi_by_name (val, vallen); 675 if (chosen_abi != NULL) 676 { 677 mips_gpr_names = chosen_abi->gpr_names; 678 mips_fpr_names = chosen_abi->fpr_names; 679 } 680 chosen_arch = choose_arch_by_name (val, vallen); 681 if (chosen_arch != NULL) 682 { 683 mips_cp0_names = chosen_arch->cp0_names; 684 mips_cp0sel_names = chosen_arch->cp0sel_names; 685 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; 686 mips_hwr_names = chosen_arch->hwr_names; 687 } 688 return; 689 } 690 691 /* Invalid option. */ 692} 693 694static void 695parse_mips_dis_options (const char *options) 696{ 697 const char *option_end; 698 699 if (options == NULL) 700 return; 701 702 while (*options != '\0') 703 { 704 /* Skip empty options. */ 705 if (*options == ',') 706 { 707 options++; 708 continue; 709 } 710 711 /* We know that *options is neither NUL or a comma. */ 712 option_end = options + 1; 713 while (*option_end != ',' && *option_end != '\0') 714 option_end++; 715 716 parse_mips_dis_option (options, option_end - options); 717 718 /* Go on to the next one. If option_end points to a comma, it 719 will be skipped above. */ 720 options = option_end; 721 } 722} 723 724static const struct mips_cp0sel_name * 725lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, 726 unsigned int len, 727 unsigned int cp0reg, 728 unsigned int sel) 729{ 730 unsigned int i; 731 732 for (i = 0; i < len; i++) 733 if (names[i].cp0reg == cp0reg && names[i].sel == sel) 734 return &names[i]; 735 return NULL; 736} 737 738/* Print insn arguments for 32/64-bit code. */ 739 740static void 741print_insn_args (const char *d, 742 register unsigned long int l, 743 bfd_vma pc, 744 struct disassemble_info *info) 745{ 746 int op, delta; 747 unsigned int lsb, msb, msbd; 748 749 lsb = 0; 750 751 for (; *d != '\0'; d++) 752 { 753 switch (*d) 754 { 755 case ',': 756 case '(': 757 case ')': 758 case '[': 759 case ']': 760 (*info->fprintf_func) (info->stream, "%c", *d); 761 break; 762 763 case '+': 764 /* Extension character; switch for second char. */ 765 d++; 766 switch (*d) 767 { 768 case '\0': 769 /* xgettext:c-format */ 770 (*info->fprintf_func) (info->stream, 771 _("# internal error, incomplete extension sequence (+)")); 772 return; 773 774 case 'A': 775 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT; 776 (*info->fprintf_func) (info->stream, "0x%x", lsb); 777 break; 778 779 case 'B': 780 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB; 781 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 782 break; 783 784 case 'C': 785 case 'H': 786 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; 787 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 788 break; 789 790 case 'D': 791 { 792 const struct mips_cp0sel_name *n; 793 unsigned int cp0reg, sel; 794 795 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD; 796 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 797 798 /* CP0 register including 'sel' code for mtcN (et al.), to be 799 printed textually if known. If not known, print both 800 CP0 register name and sel numerically since CP0 register 801 with sel 0 may have a name unrelated to register being 802 printed. */ 803 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 804 mips_cp0sel_names_len, cp0reg, sel); 805 if (n != NULL) 806 (*info->fprintf_func) (info->stream, "%s", n->name); 807 else 808 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 809 break; 810 } 811 812 case 'E': 813 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; 814 (*info->fprintf_func) (info->stream, "0x%x", lsb); 815 break; 816 817 case 'F': 818 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; 819 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); 820 break; 821 822 case 'G': 823 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; 824 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); 825 break; 826 827 case 't': /* Coprocessor 0 reg name */ 828 (*info->fprintf_func) (info->stream, "%s", 829 mips_cp0_names[(l >> OP_SH_RT) & 830 OP_MASK_RT]); 831 break; 832 833 case 'T': /* Coprocessor 0 reg name */ 834 { 835 const struct mips_cp0sel_name *n; 836 unsigned int cp0reg, sel; 837 838 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; 839 sel = (l >> OP_SH_SEL) & OP_MASK_SEL; 840 841 /* CP0 register including 'sel' code for mftc0, to be 842 printed textually if known. If not known, print both 843 CP0 register name and sel numerically since CP0 register 844 with sel 0 may have a name unrelated to register being 845 printed. */ 846 n = lookup_mips_cp0sel_name(mips_cp0sel_names, 847 mips_cp0sel_names_len, cp0reg, sel); 848 if (n != NULL) 849 (*info->fprintf_func) (info->stream, "%s", n->name); 850 else 851 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); 852 break; 853 } 854 855 default: 856 /* xgettext:c-format */ 857 (*info->fprintf_func) (info->stream, 858 _("# internal error, undefined extension sequence (+%c)"), 859 *d); 860 return; 861 } 862 break; 863 864 case '3': 865 (*info->fprintf_func) (info->stream, "0x%lx", 866 (l >> OP_SH_SA3) & OP_MASK_SA3); 867 break; 868 869 case '4': 870 (*info->fprintf_func) (info->stream, "0x%lx", 871 (l >> OP_SH_SA4) & OP_MASK_SA4); 872 break; 873 874 case '5': 875 (*info->fprintf_func) (info->stream, "0x%lx", 876 (l >> OP_SH_IMM8) & OP_MASK_IMM8); 877 break; 878 879 case '6': 880 (*info->fprintf_func) (info->stream, "0x%lx", 881 (l >> OP_SH_RS) & OP_MASK_RS); 882 break; 883 884 case '7': 885 (*info->fprintf_func) (info->stream, "$ac%ld", 886 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC); 887 break; 888 889 case '8': 890 (*info->fprintf_func) (info->stream, "0x%lx", 891 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP); 892 break; 893 894 case '9': 895 (*info->fprintf_func) (info->stream, "$ac%ld", 896 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S); 897 break; 898 899 case '0': /* dsp 6-bit signed immediate in bit 20 */ 900 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT); 901 if (delta & 0x20) /* test sign bit */ 902 delta |= ~OP_MASK_DSPSFT; 903 (*info->fprintf_func) (info->stream, "%d", delta); 904 break; 905 906 case ':': /* dsp 7-bit signed immediate in bit 19 */ 907 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7); 908 if (delta & 0x40) /* test sign bit */ 909 delta |= ~OP_MASK_DSPSFT_7; 910 (*info->fprintf_func) (info->stream, "%d", delta); 911 break; 912 913 case '\'': 914 (*info->fprintf_func) (info->stream, "0x%lx", 915 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP); 916 break; 917 918 case '@': /* dsp 10-bit signed immediate in bit 16 */ 919 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10); 920 if (delta & 0x200) /* test sign bit */ 921 delta |= ~OP_MASK_IMM10; 922 (*info->fprintf_func) (info->stream, "%d", delta); 923 break; 924 925 case '!': 926 (*info->fprintf_func) (info->stream, "%ld", 927 (l >> OP_SH_MT_U) & OP_MASK_MT_U); 928 break; 929 930 case '$': 931 (*info->fprintf_func) (info->stream, "%ld", 932 (l >> OP_SH_MT_H) & OP_MASK_MT_H); 933 break; 934 935 case '*': 936 (*info->fprintf_func) (info->stream, "$ac%ld", 937 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); 938 break; 939 940 case '&': 941 (*info->fprintf_func) (info->stream, "$ac%ld", 942 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); 943 break; 944 945 case 'g': 946 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ 947 (*info->fprintf_func) (info->stream, "$%ld", 948 (l >> OP_SH_RD) & OP_MASK_RD); 949 break; 950 951 case 's': 952 case 'b': 953 case 'r': 954 case 'v': 955 (*info->fprintf_func) (info->stream, "%s", 956 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); 957 break; 958 959 case 't': 960 case 'w': 961 (*info->fprintf_func) (info->stream, "%s", 962 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 963 break; 964 965 case 'i': 966 case 'u': 967 (*info->fprintf_func) (info->stream, "0x%lx", 968 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); 969 break; 970 971 case 'j': /* Same as i, but sign-extended. */ 972 case 'o': 973 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 974 if (delta & 0x8000) 975 delta |= ~0xffff; 976 (*info->fprintf_func) (info->stream, "%d", 977 delta); 978 break; 979 980 case 'h': 981 (*info->fprintf_func) (info->stream, "0x%x", 982 (unsigned int) ((l >> OP_SH_PREFX) 983 & OP_MASK_PREFX)); 984 break; 985 986 case 'k': 987 (*info->fprintf_func) (info->stream, "0x%x", 988 (unsigned int) ((l >> OP_SH_CACHE) 989 & OP_MASK_CACHE)); 990 break; 991 992 case 'a': 993 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) 994 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); 995 (*info->print_address_func) (info->target, info); 996 break; 997 998 case 'p': 999 /* Sign extend the displacement. */ 1000 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; 1001 if (delta & 0x8000) 1002 delta |= ~0xffff; 1003 info->target = (delta << 2) + pc + INSNLEN; 1004 (*info->print_address_func) (info->target, info); 1005 break; 1006 1007 case 'd': 1008 (*info->fprintf_func) (info->stream, "%s", 1009 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 1010 break; 1011 1012 case 'U': 1013 { 1014 /* First check for both rd and rt being equal. */ 1015 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; 1016 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) 1017 (*info->fprintf_func) (info->stream, "%s", 1018 mips_gpr_names[reg]); 1019 else 1020 { 1021 /* If one is zero use the other. */ 1022 if (reg == 0) 1023 (*info->fprintf_func) (info->stream, "%s", 1024 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 1025 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) 1026 (*info->fprintf_func) (info->stream, "%s", 1027 mips_gpr_names[reg]); 1028 else /* Bogus, result depends on processor. */ 1029 (*info->fprintf_func) (info->stream, "%s or %s", 1030 mips_gpr_names[reg], 1031 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); 1032 } 1033 } 1034 break; 1035 1036 case 'z': 1037 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 1038 break; 1039 1040 case '<': 1041 (*info->fprintf_func) (info->stream, "0x%lx", 1042 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); 1043 break; 1044 1045 case 'c': 1046 (*info->fprintf_func) (info->stream, "0x%lx", 1047 (l >> OP_SH_CODE) & OP_MASK_CODE); 1048 break; 1049 1050 case 'q': 1051 (*info->fprintf_func) (info->stream, "0x%lx", 1052 (l >> OP_SH_CODE2) & OP_MASK_CODE2); 1053 break; 1054 1055 /* Display 5 bits of bbit0/1 bit index amount. */ 1056 case '^': 1057 (*info->fprintf_func) (info->stream, "0x%x", 1058 (l >> OP_SH_BITIND) & OP_MASK_BITIND); 1059 break; 1060 1061 /* Display 10 bits signed constant from seqi/snei instruction. */ 1062 case 'y': 1063 { 1064 int imm = (l >> OP_SH_CODE2) & OP_MASK_CODE2; 1065 imm <<= 22; 1066 imm >>= 22; 1067 (*info->fprintf_func) (info->stream, "%d", imm); 1068 } 1069 break; 1070 1071 case 'C': 1072 (*info->fprintf_func) (info->stream, "0x%lx", 1073 (l >> OP_SH_COPZ) & OP_MASK_COPZ); 1074 break; 1075 1076 case 'B': 1077 (*info->fprintf_func) (info->stream, "0x%lx", 1078 1079 (l >> OP_SH_CODE20) & OP_MASK_CODE20); 1080 break; 1081 1082 case 'J': 1083 (*info->fprintf_func) (info->stream, "0x%lx", 1084 (l >> OP_SH_CODE19) & OP_MASK_CODE19); 1085 break; 1086 1087 case 'S': 1088 case 'V': 1089 (*info->fprintf_func) (info->stream, "%s", 1090 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); 1091 break; 1092 1093 case 'T': 1094 case 'W': 1095 (*info->fprintf_func) (info->stream, "%s", 1096 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); 1097 break; 1098 1099 case 'D': 1100 (*info->fprintf_func) (info->stream, "%s", 1101 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); 1102 break; 1103 1104 case 'R': 1105 (*info->fprintf_func) (info->stream, "%s", 1106 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); 1107 break; 1108 1109 case 'E': 1110 /* Coprocessor register for lwcN instructions, et al. 1111 1112 Note that there is no load/store cp0 instructions, and 1113 that FPU (cp1) instructions disassemble this field using 1114 'T' format. Therefore, until we gain understanding of 1115 cp2 register names, we can simply print the register 1116 numbers. */ 1117 (*info->fprintf_func) (info->stream, "$%ld", 1118 (l >> OP_SH_RT) & OP_MASK_RT); 1119 break; 1120 1121 case 'G': 1122 /* Coprocessor register for mtcN instructions, et al. Note 1123 that FPU (cp1) instructions disassemble this field using 1124 'S' format. Therefore, we only need to worry about cp0, 1125 cp2, and cp3. */ 1126 op = (l >> OP_SH_OP) & OP_MASK_OP; 1127 if (op == OP_OP_COP0) 1128 (*info->fprintf_func) (info->stream, "%s", 1129 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); 1130 else 1131 (*info->fprintf_func) (info->stream, "$%ld", 1132 (l >> OP_SH_RD) & OP_MASK_RD); 1133 break; 1134 1135 case 'K': 1136 (*info->fprintf_func) (info->stream, "%s", 1137 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]); 1138 break; 1139 1140 case 'N': 1141 (*info->fprintf_func) (info->stream, "$fcc%ld", 1142 (l >> OP_SH_BCC) & OP_MASK_BCC); 1143 break; 1144 1145 case 'M': 1146 (*info->fprintf_func) (info->stream, "$fcc%ld", 1147 (l >> OP_SH_CCC) & OP_MASK_CCC); 1148 break; 1149 1150 case 'P': 1151 (*info->fprintf_func) (info->stream, "%ld", 1152 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); 1153 break; 1154 1155 case 'e': 1156 (*info->fprintf_func) (info->stream, "%ld", 1157 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); 1158 break; 1159 1160 case '%': 1161 (*info->fprintf_func) (info->stream, "%ld", 1162 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); 1163 break; 1164 1165 case 'H': 1166 (*info->fprintf_func) (info->stream, "%ld", 1167 (l >> OP_SH_SEL) & OP_MASK_SEL); 1168 break; 1169 1170 case 'O': 1171 (*info->fprintf_func) (info->stream, "%ld", 1172 (l >> OP_SH_ALN) & OP_MASK_ALN); 1173 break; 1174 1175 case 'Q': 1176 { 1177 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; 1178 1179 if ((vsel & 0x10) == 0) 1180 { 1181 int fmt; 1182 1183 vsel &= 0x0f; 1184 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) 1185 if ((vsel & 1) == 0) 1186 break; 1187 (*info->fprintf_func) (info->stream, "$v%ld[%d]", 1188 (l >> OP_SH_FT) & OP_MASK_FT, 1189 vsel >> 1); 1190 } 1191 else if ((vsel & 0x08) == 0) 1192 { 1193 (*info->fprintf_func) (info->stream, "$v%ld", 1194 (l >> OP_SH_FT) & OP_MASK_FT); 1195 } 1196 else 1197 { 1198 (*info->fprintf_func) (info->stream, "0x%lx", 1199 (l >> OP_SH_FT) & OP_MASK_FT); 1200 } 1201 } 1202 break; 1203 1204 case 'X': 1205 (*info->fprintf_func) (info->stream, "$v%ld", 1206 (l >> OP_SH_FD) & OP_MASK_FD); 1207 break; 1208 1209 case 'Y': 1210 (*info->fprintf_func) (info->stream, "$v%ld", 1211 (l >> OP_SH_FS) & OP_MASK_FS); 1212 break; 1213 1214 case 'Z': 1215 (*info->fprintf_func) (info->stream, "$v%ld", 1216 (l >> OP_SH_FT) & OP_MASK_FT); 1217 break; 1218 1219 default: 1220 /* xgettext:c-format */ 1221 (*info->fprintf_func) (info->stream, 1222 _("# internal error, undefined modifier(%c)"), 1223 *d); 1224 return; 1225 } 1226 } 1227} 1228 1229/* Print the mips instruction at address MEMADDR in debugged memory, 1230 on using INFO. Returns length of the instruction, in bytes, which is 1231 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if 1232 this is little-endian code. */ 1233 1234static int 1235print_insn_mips (bfd_vma memaddr, 1236 unsigned long int word, 1237 struct disassemble_info *info) 1238{ 1239 const struct mips_opcode *op; 1240 static bfd_boolean init = 0; 1241 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; 1242 1243 /* Build a hash table to shorten the search time. */ 1244 if (! init) 1245 { 1246 unsigned int i; 1247 1248 for (i = 0; i <= OP_MASK_OP; i++) 1249 { 1250 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) 1251 { 1252 if (op->pinfo == INSN_MACRO 1253 || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) 1254 continue; 1255 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) 1256 { 1257 mips_hash[i] = op; 1258 break; 1259 } 1260 } 1261 } 1262 1263 init = 1; 1264 } 1265 1266 info->bytes_per_chunk = INSNLEN; 1267 info->display_endian = info->endian; 1268 info->insn_info_valid = 1; 1269 info->branch_delay_insns = 0; 1270 info->data_size = 0; 1271 info->insn_type = dis_nonbranch; 1272 info->target = 0; 1273 info->target2 = 0; 1274 1275 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; 1276 if (op != NULL) 1277 { 1278 for (; op < &mips_opcodes[NUMOPCODES]; op++) 1279 { 1280 if (op->pinfo != INSN_MACRO 1281 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1282 && (word & op->mask) == op->match) 1283 { 1284 const char *d; 1285 1286 /* We always allow to disassemble the jalx instruction. */ 1287 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) 1288 && strcmp (op->name, "jalx")) 1289 continue; 1290 1291 if (info->mach == CPU_OCTEON && octeon_use_unalign) 1292 { 1293 if (strcmp (op->name, "lwl") == 0 1294 || strcmp (op->name, "ldl") == 0 1295 || strcmp (op->name, "swl") == 0 1296 || strcmp (op->name, "sdl") == 0 1297 || strcmp (op->name, "lcache") == 0 1298 || strcmp (op->name, "scache") == 0 1299 || strcmp (op->name, "flush") == 0) 1300 continue; 1301 1302 if (strcmp (op->name, "ldr") == 0 1303 || strcmp (op->name, "lwr") == 0 1304 || strcmp (op->name, "swr") == 0 1305 || strcmp (op->name, "sdr") == 0) 1306 { 1307 (*info->fprintf_func) (info->stream, "nop"); 1308 return INSNLEN; 1309 } 1310 } 1311 1312 /* Figure out instruction type and branch delay information. */ 1313 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1314 { 1315 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 1316 info->insn_type = dis_jsr; 1317 else 1318 info->insn_type = dis_branch; 1319 info->branch_delay_insns = 1; 1320 } 1321 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY 1322 | INSN_COND_BRANCH_LIKELY)) != 0) 1323 { 1324 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) 1325 info->insn_type = dis_condjsr; 1326 else 1327 info->insn_type = dis_condbranch; 1328 info->branch_delay_insns = 1; 1329 } 1330 else if ((op->pinfo & (INSN_STORE_MEMORY 1331 | INSN_LOAD_MEMORY_DELAY)) != 0) 1332 info->insn_type = dis_dref; 1333 1334 (*info->fprintf_func) (info->stream, "%s", op->name); 1335 1336 d = op->args; 1337 if (d != NULL && *d != '\0') 1338 { 1339 (*info->fprintf_func) (info->stream, "\t"); 1340 print_insn_args (d, word, memaddr, info); 1341 } 1342 1343 return INSNLEN; 1344 } 1345 } 1346 } 1347 1348 /* Handle undefined instructions. */ 1349 info->insn_type = dis_noninsn; 1350 (*info->fprintf_func) (info->stream, "0x%lx", word); 1351 return INSNLEN; 1352} 1353 1354/* Disassemble an operand for a mips16 instruction. */ 1355 1356static void 1357print_mips16_insn_arg (char type, 1358 const struct mips_opcode *op, 1359 int l, 1360 bfd_boolean use_extend, 1361 int extend, 1362 bfd_vma memaddr, 1363 struct disassemble_info *info) 1364{ 1365 switch (type) 1366 { 1367 case ',': 1368 case '(': 1369 case ')': 1370 (*info->fprintf_func) (info->stream, "%c", type); 1371 break; 1372 1373 case 'y': 1374 case 'w': 1375 (*info->fprintf_func) (info->stream, "%s", 1376 mips16_reg_names[((l >> MIPS16OP_SH_RY) 1377 & MIPS16OP_MASK_RY)]); 1378 break; 1379 1380 case 'x': 1381 case 'v': 1382 (*info->fprintf_func) (info->stream, "%s", 1383 mips16_reg_names[((l >> MIPS16OP_SH_RX) 1384 & MIPS16OP_MASK_RX)]); 1385 break; 1386 1387 case 'z': 1388 (*info->fprintf_func) (info->stream, "%s", 1389 mips16_reg_names[((l >> MIPS16OP_SH_RZ) 1390 & MIPS16OP_MASK_RZ)]); 1391 break; 1392 1393 case 'Z': 1394 (*info->fprintf_func) (info->stream, "%s", 1395 mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) 1396 & MIPS16OP_MASK_MOVE32Z)]); 1397 break; 1398 1399 case '0': 1400 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); 1401 break; 1402 1403 case 'S': 1404 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); 1405 break; 1406 1407 case 'P': 1408 (*info->fprintf_func) (info->stream, "$pc"); 1409 break; 1410 1411 case 'R': 1412 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); 1413 break; 1414 1415 case 'X': 1416 (*info->fprintf_func) (info->stream, "%s", 1417 mips_gpr_names[((l >> MIPS16OP_SH_REGR32) 1418 & MIPS16OP_MASK_REGR32)]); 1419 break; 1420 1421 case 'Y': 1422 (*info->fprintf_func) (info->stream, "%s", 1423 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); 1424 break; 1425 1426 case '<': 1427 case '>': 1428 case '[': 1429 case ']': 1430 case '4': 1431 case '5': 1432 case 'H': 1433 case 'W': 1434 case 'D': 1435 case 'j': 1436 case '6': 1437 case '8': 1438 case 'V': 1439 case 'C': 1440 case 'U': 1441 case 'k': 1442 case 'K': 1443 case 'p': 1444 case 'q': 1445 case 'A': 1446 case 'B': 1447 case 'E': 1448 { 1449 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; 1450 1451 shift = 0; 1452 signedp = 0; 1453 extbits = 16; 1454 pcrel = 0; 1455 extu = 0; 1456 branch = 0; 1457 switch (type) 1458 { 1459 case '<': 1460 nbits = 3; 1461 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 1462 extbits = 5; 1463 extu = 1; 1464 break; 1465 case '>': 1466 nbits = 3; 1467 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 1468 extbits = 5; 1469 extu = 1; 1470 break; 1471 case '[': 1472 nbits = 3; 1473 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 1474 extbits = 6; 1475 extu = 1; 1476 break; 1477 case ']': 1478 nbits = 3; 1479 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 1480 extbits = 6; 1481 extu = 1; 1482 break; 1483 case '4': 1484 nbits = 4; 1485 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; 1486 signedp = 1; 1487 extbits = 15; 1488 break; 1489 case '5': 1490 nbits = 5; 1491 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1492 info->insn_type = dis_dref; 1493 info->data_size = 1; 1494 break; 1495 case 'H': 1496 nbits = 5; 1497 shift = 1; 1498 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1499 info->insn_type = dis_dref; 1500 info->data_size = 2; 1501 break; 1502 case 'W': 1503 nbits = 5; 1504 shift = 2; 1505 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1506 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 1507 && (op->pinfo & MIPS16_INSN_READ_SP) == 0) 1508 { 1509 info->insn_type = dis_dref; 1510 info->data_size = 4; 1511 } 1512 break; 1513 case 'D': 1514 nbits = 5; 1515 shift = 3; 1516 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1517 info->insn_type = dis_dref; 1518 info->data_size = 8; 1519 break; 1520 case 'j': 1521 nbits = 5; 1522 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1523 signedp = 1; 1524 break; 1525 case '6': 1526 nbits = 6; 1527 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 1528 break; 1529 case '8': 1530 nbits = 8; 1531 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1532 break; 1533 case 'V': 1534 nbits = 8; 1535 shift = 2; 1536 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1537 /* FIXME: This might be lw, or it might be addiu to $sp or 1538 $pc. We assume it's load. */ 1539 info->insn_type = dis_dref; 1540 info->data_size = 4; 1541 break; 1542 case 'C': 1543 nbits = 8; 1544 shift = 3; 1545 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1546 info->insn_type = dis_dref; 1547 info->data_size = 8; 1548 break; 1549 case 'U': 1550 nbits = 8; 1551 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1552 extu = 1; 1553 break; 1554 case 'k': 1555 nbits = 8; 1556 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1557 signedp = 1; 1558 break; 1559 case 'K': 1560 nbits = 8; 1561 shift = 3; 1562 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1563 signedp = 1; 1564 break; 1565 case 'p': 1566 nbits = 8; 1567 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1568 signedp = 1; 1569 pcrel = 1; 1570 branch = 1; 1571 info->insn_type = dis_condbranch; 1572 break; 1573 case 'q': 1574 nbits = 11; 1575 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; 1576 signedp = 1; 1577 pcrel = 1; 1578 branch = 1; 1579 info->insn_type = dis_branch; 1580 break; 1581 case 'A': 1582 nbits = 8; 1583 shift = 2; 1584 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; 1585 pcrel = 1; 1586 /* FIXME: This can be lw or la. We assume it is lw. */ 1587 info->insn_type = dis_dref; 1588 info->data_size = 4; 1589 break; 1590 case 'B': 1591 nbits = 5; 1592 shift = 3; 1593 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1594 pcrel = 1; 1595 info->insn_type = dis_dref; 1596 info->data_size = 8; 1597 break; 1598 case 'E': 1599 nbits = 5; 1600 shift = 2; 1601 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; 1602 pcrel = 1; 1603 break; 1604 default: 1605 abort (); 1606 } 1607 1608 if (! use_extend) 1609 { 1610 if (signedp && immed >= (1 << (nbits - 1))) 1611 immed -= 1 << nbits; 1612 immed <<= shift; 1613 if ((type == '<' || type == '>' || type == '[' || type == ']') 1614 && immed == 0) 1615 immed = 8; 1616 } 1617 else 1618 { 1619 if (extbits == 16) 1620 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); 1621 else if (extbits == 15) 1622 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); 1623 else 1624 immed = ((extend >> 6) & 0x1f) | (extend & 0x20); 1625 immed &= (1 << extbits) - 1; 1626 if (! extu && immed >= (1 << (extbits - 1))) 1627 immed -= 1 << extbits; 1628 } 1629 1630 if (! pcrel) 1631 (*info->fprintf_func) (info->stream, "%d", immed); 1632 else 1633 { 1634 bfd_vma baseaddr; 1635 1636 if (branch) 1637 { 1638 immed *= 2; 1639 baseaddr = memaddr + 2; 1640 } 1641 else if (use_extend) 1642 baseaddr = memaddr - 2; 1643 else 1644 { 1645 int status; 1646 bfd_byte buffer[2]; 1647 1648 baseaddr = memaddr; 1649 1650 /* If this instruction is in the delay slot of a jr 1651 instruction, the base address is the address of the 1652 jr instruction. If it is in the delay slot of jalr 1653 instruction, the base address is the address of the 1654 jalr instruction. This test is unreliable: we have 1655 no way of knowing whether the previous word is 1656 instruction or data. */ 1657 status = (*info->read_memory_func) (memaddr - 4, buffer, 2, 1658 info); 1659 if (status == 0 1660 && (((info->endian == BFD_ENDIAN_BIG 1661 ? bfd_getb16 (buffer) 1662 : bfd_getl16 (buffer)) 1663 & 0xf800) == 0x1800)) 1664 baseaddr = memaddr - 4; 1665 else 1666 { 1667 status = (*info->read_memory_func) (memaddr - 2, buffer, 1668 2, info); 1669 if (status == 0 1670 && (((info->endian == BFD_ENDIAN_BIG 1671 ? bfd_getb16 (buffer) 1672 : bfd_getl16 (buffer)) 1673 & 0xf81f) == 0xe800)) 1674 baseaddr = memaddr - 2; 1675 } 1676 } 1677 info->target = (baseaddr & ~((1 << shift) - 1)) + immed; 1678 (*info->print_address_func) (info->target, info); 1679 } 1680 } 1681 break; 1682 1683 case 'a': 1684 if (! use_extend) 1685 extend = 0; 1686 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); 1687 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; 1688 (*info->print_address_func) (info->target, info); 1689 info->insn_type = dis_jsr; 1690 info->branch_delay_insns = 1; 1691 break; 1692 1693 case 'l': 1694 case 'L': 1695 { 1696 int need_comma, amask, smask; 1697 1698 need_comma = 0; 1699 1700 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; 1701 1702 amask = (l >> 3) & 7; 1703 1704 if (amask > 0 && amask < 5) 1705 { 1706 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 1707 if (amask > 1) 1708 (*info->fprintf_func) (info->stream, "-%s", 1709 mips_gpr_names[amask + 3]); 1710 need_comma = 1; 1711 } 1712 1713 smask = (l >> 1) & 3; 1714 if (smask == 3) 1715 { 1716 (*info->fprintf_func) (info->stream, "%s??", 1717 need_comma ? "," : ""); 1718 need_comma = 1; 1719 } 1720 else if (smask > 0) 1721 { 1722 (*info->fprintf_func) (info->stream, "%s%s", 1723 need_comma ? "," : "", 1724 mips_gpr_names[16]); 1725 if (smask > 1) 1726 (*info->fprintf_func) (info->stream, "-%s", 1727 mips_gpr_names[smask + 15]); 1728 need_comma = 1; 1729 } 1730 1731 if (l & 1) 1732 { 1733 (*info->fprintf_func) (info->stream, "%s%s", 1734 need_comma ? "," : "", 1735 mips_gpr_names[31]); 1736 need_comma = 1; 1737 } 1738 1739 if (amask == 5 || amask == 6) 1740 { 1741 (*info->fprintf_func) (info->stream, "%s$f0", 1742 need_comma ? "," : ""); 1743 if (amask == 6) 1744 (*info->fprintf_func) (info->stream, "-$f1"); 1745 } 1746 } 1747 break; 1748 1749 case 'm': 1750 case 'M': 1751 /* MIPS16e save/restore. */ 1752 { 1753 int need_comma = 0; 1754 int amask, args, statics; 1755 int nsreg, smask; 1756 int framesz; 1757 int i, j; 1758 1759 l = l & 0x7f; 1760 if (use_extend) 1761 l |= extend << 16; 1762 1763 amask = (l >> 16) & 0xf; 1764 if (amask == MIPS16_ALL_ARGS) 1765 { 1766 args = 4; 1767 statics = 0; 1768 } 1769 else if (amask == MIPS16_ALL_STATICS) 1770 { 1771 args = 0; 1772 statics = 4; 1773 } 1774 else 1775 { 1776 args = amask >> 2; 1777 statics = amask & 3; 1778 } 1779 1780 if (args > 0) { 1781 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); 1782 if (args > 1) 1783 (*info->fprintf_func) (info->stream, "-%s", 1784 mips_gpr_names[4 + args - 1]); 1785 need_comma = 1; 1786 } 1787 1788 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; 1789 if (framesz == 0 && !use_extend) 1790 framesz = 128; 1791 1792 (*info->fprintf_func) (info->stream, "%s%d", 1793 need_comma ? "," : "", 1794 framesz); 1795 1796 if (l & 0x40) /* $ra */ 1797 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); 1798 1799 nsreg = (l >> 24) & 0x7; 1800 smask = 0; 1801 if (l & 0x20) /* $s0 */ 1802 smask |= 1 << 0; 1803 if (l & 0x10) /* $s1 */ 1804 smask |= 1 << 1; 1805 if (nsreg > 0) /* $s2-$s8 */ 1806 smask |= ((1 << nsreg) - 1) << 2; 1807 1808 /* Find first set static reg bit. */ 1809 for (i = 0; i < 9; i++) 1810 { 1811 if (smask & (1 << i)) 1812 { 1813 (*info->fprintf_func) (info->stream, ",%s", 1814 mips_gpr_names[i == 8 ? 30 : (16 + i)]); 1815 /* Skip over string of set bits. */ 1816 for (j = i; smask & (2 << j); j++) 1817 continue; 1818 if (j > i) 1819 (*info->fprintf_func) (info->stream, "-%s", 1820 mips_gpr_names[j == 8 ? 30 : (16 + j)]); 1821 i = j + 1; 1822 } 1823 } 1824 1825 /* Statics $ax - $a3. */ 1826 if (statics == 1) 1827 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); 1828 else if (statics > 0) 1829 (*info->fprintf_func) (info->stream, ",%s-%s", 1830 mips_gpr_names[7 - statics + 1], 1831 mips_gpr_names[7]); 1832 } 1833 break; 1834 1835 default: 1836 /* xgettext:c-format */ 1837 (*info->fprintf_func) 1838 (info->stream, 1839 _("# internal disassembler error, unrecognised modifier (%c)"), 1840 type); 1841 abort (); 1842 } 1843} 1844 1845/* Disassemble mips16 instructions. */ 1846 1847static int 1848print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) 1849{ 1850 int status; 1851 bfd_byte buffer[2]; 1852 int length; 1853 int insn; 1854 bfd_boolean use_extend; 1855 int extend = 0; 1856 const struct mips_opcode *op, *opend; 1857 1858 info->bytes_per_chunk = 2; 1859 info->display_endian = info->endian; 1860 info->insn_info_valid = 1; 1861 info->branch_delay_insns = 0; 1862 info->data_size = 0; 1863 info->insn_type = dis_nonbranch; 1864 info->target = 0; 1865 info->target2 = 0; 1866 1867 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 1868 if (status != 0) 1869 { 1870 (*info->memory_error_func) (status, memaddr, info); 1871 return -1; 1872 } 1873 1874 length = 2; 1875 1876 if (info->endian == BFD_ENDIAN_BIG) 1877 insn = bfd_getb16 (buffer); 1878 else 1879 insn = bfd_getl16 (buffer); 1880 1881 /* Handle the extend opcode specially. */ 1882 use_extend = FALSE; 1883 if ((insn & 0xf800) == 0xf000) 1884 { 1885 use_extend = TRUE; 1886 extend = insn & 0x7ff; 1887 1888 memaddr += 2; 1889 1890 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 1891 if (status != 0) 1892 { 1893 (*info->fprintf_func) (info->stream, "extend 0x%x", 1894 (unsigned int) extend); 1895 (*info->memory_error_func) (status, memaddr, info); 1896 return -1; 1897 } 1898 1899 if (info->endian == BFD_ENDIAN_BIG) 1900 insn = bfd_getb16 (buffer); 1901 else 1902 insn = bfd_getl16 (buffer); 1903 1904 /* Check for an extend opcode followed by an extend opcode. */ 1905 if ((insn & 0xf800) == 0xf000) 1906 { 1907 (*info->fprintf_func) (info->stream, "extend 0x%x", 1908 (unsigned int) extend); 1909 info->insn_type = dis_noninsn; 1910 return length; 1911 } 1912 1913 length += 2; 1914 } 1915 1916 /* FIXME: Should probably use a hash table on the major opcode here. */ 1917 1918 opend = mips16_opcodes + bfd_mips16_num_opcodes; 1919 for (op = mips16_opcodes; op < opend; op++) 1920 { 1921 if (op->pinfo != INSN_MACRO 1922 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) 1923 && (insn & op->mask) == op->match) 1924 { 1925 const char *s; 1926 1927 if (strchr (op->args, 'a') != NULL) 1928 { 1929 if (use_extend) 1930 { 1931 (*info->fprintf_func) (info->stream, "extend 0x%x", 1932 (unsigned int) extend); 1933 info->insn_type = dis_noninsn; 1934 return length - 2; 1935 } 1936 1937 use_extend = FALSE; 1938 1939 memaddr += 2; 1940 1941 status = (*info->read_memory_func) (memaddr, buffer, 2, 1942 info); 1943 if (status == 0) 1944 { 1945 use_extend = TRUE; 1946 if (info->endian == BFD_ENDIAN_BIG) 1947 extend = bfd_getb16 (buffer); 1948 else 1949 extend = bfd_getl16 (buffer); 1950 length += 2; 1951 } 1952 } 1953 1954 (*info->fprintf_func) (info->stream, "%s", op->name); 1955 if (op->args[0] != '\0') 1956 (*info->fprintf_func) (info->stream, "\t"); 1957 1958 for (s = op->args; *s != '\0'; s++) 1959 { 1960 if (*s == ',' 1961 && s[1] == 'w' 1962 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) 1963 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) 1964 { 1965 /* Skip the register and the comma. */ 1966 ++s; 1967 continue; 1968 } 1969 if (*s == ',' 1970 && s[1] == 'v' 1971 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) 1972 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) 1973 { 1974 /* Skip the register and the comma. */ 1975 ++s; 1976 continue; 1977 } 1978 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, 1979 info); 1980 } 1981 1982 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 1983 { 1984 info->branch_delay_insns = 1; 1985 if (info->insn_type != dis_jsr) 1986 info->insn_type = dis_branch; 1987 } 1988 1989 return length; 1990 } 1991 } 1992 1993 if (use_extend) 1994 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); 1995 (*info->fprintf_func) (info->stream, "0x%x", insn); 1996 info->insn_type = dis_noninsn; 1997 1998 return length; 1999} 2000 2001/* In an environment where we do not know the symbol type of the 2002 instruction we are forced to assume that the low order bit of the 2003 instructions' address may mark it as a mips16 instruction. If we 2004 are single stepping, or the pc is within the disassembled function, 2005 this works. Otherwise, we need a clue. Sometimes. */ 2006 2007static int 2008_print_insn_mips (bfd_vma memaddr, 2009 struct disassemble_info *info, 2010 enum bfd_endian endianness) 2011{ 2012 bfd_byte buffer[INSNLEN]; 2013 int status; 2014 2015 set_default_mips_dis_options (info); 2016 parse_mips_dis_options (info->disassembler_options); 2017 2018#if 1 2019 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ 2020 /* Only a few tools will work this way. */ 2021 if (memaddr & 0x01) 2022 return print_insn_mips16 (memaddr, info); 2023#endif 2024 2025#if SYMTAB_AVAILABLE 2026 if (info->mach == bfd_mach_mips16 2027 || (info->flavour == bfd_target_elf_flavour 2028 && info->symbols != NULL 2029 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other 2030 == STO_MIPS16))) 2031 return print_insn_mips16 (memaddr, info); 2032#endif 2033 2034 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); 2035 if (status == 0) 2036 { 2037 unsigned long insn; 2038 2039 if (endianness == BFD_ENDIAN_BIG) 2040 insn = (unsigned long) bfd_getb32 (buffer); 2041 else 2042 insn = (unsigned long) bfd_getl32 (buffer); 2043 2044 return print_insn_mips (memaddr, insn, info); 2045 } 2046 else 2047 { 2048 (*info->memory_error_func) (status, memaddr, info); 2049 return -1; 2050 } 2051} 2052 2053int 2054print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) 2055{ 2056 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); 2057} 2058 2059int 2060print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) 2061{ 2062 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); 2063} 2064 2065void 2066print_mips_disassembler_options (FILE *stream) 2067{ 2068 unsigned int i; 2069 2070 fprintf (stream, _("\n\ 2071The following MIPS specific disassembler options are supported for use\n\ 2072with the -M switch (multiple options should be separated by commas):\n")); 2073 2074 fprintf (stream, _("\n\ 2075 octeon-useun Disassemble Octeon unaligned load/store instructions.\n")); 2076 2077 fprintf (stream, _("\n\ 2078 no-octeon-useun Disassemble mips unaligned load/store instructions.\n")); 2079 2080 fprintf (stream, _("\n\ 2081 gpr-names=ABI Print GPR names according to specified ABI.\n\ 2082 Default: based on binary being disassembled.\n")); 2083 2084 fprintf (stream, _("\n\ 2085 fpr-names=ABI Print FPR names according to specified ABI.\n\ 2086 Default: numeric.\n")); 2087 2088 fprintf (stream, _("\n\ 2089 cp0-names=ARCH Print CP0 register names according to\n\ 2090 specified architecture.\n\ 2091 Default: based on binary being disassembled.\n")); 2092 2093 fprintf (stream, _("\n\ 2094 hwr-names=ARCH Print HWR names according to specified \n\ 2095 architecture.\n\ 2096 Default: based on binary being disassembled.\n")); 2097 2098 fprintf (stream, _("\n\ 2099 reg-names=ABI Print GPR and FPR names according to\n\ 2100 specified ABI.\n")); 2101 2102 fprintf (stream, _("\n\ 2103 reg-names=ARCH Print CP0 register and HWR names according to\n\ 2104 specified architecture.\n")); 2105 2106 fprintf (stream, _("\n\ 2107 For the options above, the following values are supported for \"ABI\":\n\ 2108 ")); 2109 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) 2110 fprintf (stream, " %s", mips_abi_choices[i].name); 2111 fprintf (stream, _("\n")); 2112 2113 fprintf (stream, _("\n\ 2114 For the options above, The following values are supported for \"ARCH\":\n\ 2115 ")); 2116 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) 2117 if (*mips_arch_choices[i].name != '\0') 2118 fprintf (stream, " %s", mips_arch_choices[i].name); 2119 fprintf (stream, _("\n")); 2120 2121 fprintf (stream, _("\n")); 2122} 2123