arc-opc.c revision 89857
1/* Opcode table for the ARC. 2 Copyright 1994, 1995, 1997, 1998, 2000, 2001 3 Free Software Foundation, Inc. 4 Contributed by Doug Evans (dje@cygnus.com). 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software Foundation, 18 Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 19 20#include "sysdep.h" 21#include <stdio.h> 22#include "ansidecl.h" 23#include "opcode/arc.h" 24 25#define INSERT_FN(fn) \ 26static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \ 27 int, const struct arc_operand_value *, long, \ 28 const char **)) 29#define EXTRACT_FN(fn) \ 30static long fn PARAMS ((arc_insn *, const struct arc_operand *, \ 31 int, const struct arc_operand_value **, int *)) 32 33INSERT_FN (insert_reg); 34INSERT_FN (insert_shimmfinish); 35INSERT_FN (insert_limmfinish); 36INSERT_FN (insert_offset); 37INSERT_FN (insert_base); 38INSERT_FN (insert_st_syntax); 39INSERT_FN (insert_ld_syntax); 40INSERT_FN (insert_addr_wb); 41INSERT_FN (insert_flag); 42INSERT_FN (insert_nullify); 43INSERT_FN (insert_flagfinish); 44INSERT_FN (insert_cond); 45INSERT_FN (insert_forcelimm); 46INSERT_FN (insert_reladdr); 47INSERT_FN (insert_absaddr); 48INSERT_FN (insert_jumpflags); 49INSERT_FN (insert_unopmacro); 50 51EXTRACT_FN (extract_reg); 52EXTRACT_FN (extract_ld_offset); 53EXTRACT_FN (extract_ld_syntax); 54EXTRACT_FN (extract_st_offset); 55EXTRACT_FN (extract_st_syntax); 56EXTRACT_FN (extract_flag); 57EXTRACT_FN (extract_cond); 58EXTRACT_FN (extract_reladdr); 59EXTRACT_FN (extract_jumpflags); 60EXTRACT_FN (extract_unopmacro); 61 62enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; 63 64#define OPERANDS 3 65 66enum operand ls_operand[OPERANDS]; 67 68#define LS_VALUE 0 69#define LS_DEST 0 70#define LS_BASE 1 71#define LS_OFFSET 2 72 73/* Various types of ARC operands, including insn suffixes. */ 74 75/* Insn format values: 76 77 'a' REGA register A field 78 'b' REGB register B field 79 'c' REGC register C field 80 'S' SHIMMFINISH finish inserting a shimm value 81 'L' LIMMFINISH finish inserting a limm value 82 'o' OFFSET offset in st insns 83 'O' OFFSET offset in ld insns 84 '0' SYNTAX_ST_NE enforce store insn syntax, no errors 85 '1' SYNTAX_LD_NE enforce load insn syntax, no errors 86 '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only 87 '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only 88 's' BASE base in st insn 89 'f' FLAG F flag 90 'F' FLAGFINISH finish inserting the F flag 91 'G' FLAGINSN insert F flag in "flag" insn 92 'n' DELAY N field (nullify field) 93 'q' COND condition code field 94 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm 95 'B' BRANCH branch address (22 bit pc relative) 96 'J' JUMP jump address (26 bit absolute) 97 'j' JUMPFLAGS optional high order bits of 'J' 98 'z' SIZE1 size field in ld a,[b,c] 99 'Z' SIZE10 size field in ld a,[b,shimm] 100 'y' SIZE22 size field in st c,[b,shimm] 101 'x' SIGN0 sign extend field ld a,[b,c] 102 'X' SIGN9 sign extend field ld a,[b,shimm] 103 'w' ADDRESS3 write-back field in ld a,[b,c] 104 'W' ADDRESS12 write-back field in ld a,[b,shimm] 105 'v' ADDRESS24 write-back field in st c,[b,shimm] 106 'e' CACHEBYPASS5 cache bypass in ld a,[b,c] 107 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm] 108 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm] 109 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros 110 111 The following modifiers may appear between the % and char (eg: %.f): 112 113 '.' MODDOT '.' prefix must be present 114 'r' REG generic register value, for register table 115 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] 116 117 Fields are: 118 119 CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */ 120 121const struct arc_operand arc_operands[] = 122{ 123/* place holder (??? not sure if needed). */ 124#define UNUSED 0 125 { 0, 0, 0, 0, 0, 0 }, 126 127/* register A or shimm/limm indicator. */ 128#define REGA (UNUSED + 1) 129 { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, 130 131/* register B or shimm/limm indicator. */ 132#define REGB (REGA + 1) 133 { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, 134 135/* register C or shimm/limm indicator. */ 136#define REGC (REGB + 1) 137 { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, 138 139/* fake operand used to insert shimm value into most instructions. */ 140#define SHIMMFINISH (REGC + 1) 141 { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, 142 143/* fake operand used to insert limm value into most instructions. */ 144#define LIMMFINISH (SHIMMFINISH + 1) 145 { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, 146 147/* shimm operand when there is no reg indicator (st). */ 148#define ST_OFFSET (LIMMFINISH + 1) 149 { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset }, 150 151/* shimm operand when there is no reg indicator (ld). */ 152#define LD_OFFSET (ST_OFFSET + 1) 153 { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset }, 154 155/* operand for base. */ 156#define BASE (LD_OFFSET + 1) 157 { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg}, 158 159/* 0 enforce syntax for st insns. */ 160#define SYNTAX_ST_NE (BASE + 1) 161 { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax }, 162 163/* 1 enforce syntax for ld insns. */ 164#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1) 165 { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax }, 166 167/* 0 enforce syntax for st insns. */ 168#define SYNTAX_ST (SYNTAX_LD_NE + 1) 169 { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax }, 170 171/* 0 enforce syntax for ld insns. */ 172#define SYNTAX_LD (SYNTAX_ST + 1) 173 { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax }, 174 175/* flag update bit (insertion is defered until we know how). */ 176#define FLAG (SYNTAX_LD + 1) 177 { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, 178 179/* fake utility operand to finish 'f' suffix handling. */ 180#define FLAGFINISH (FLAG + 1) 181 { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, 182 183/* fake utility operand to set the 'f' flag for the "flag" insn. */ 184#define FLAGINSN (FLAGFINISH + 1) 185 { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, 186 187/* branch delay types. */ 188#define DELAY (FLAGINSN + 1) 189 { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 }, 190 191/* conditions. */ 192#define COND (DELAY + 1) 193 { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, 194 195/* set `cond_p' to 1 to ensure a constant is treated as a limm. */ 196#define FORCELIMM (COND + 1) 197 { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 }, 198 199/* branch address; b, bl, and lp insns. */ 200#define BRANCH (FORCELIMM + 1) 201 { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr }, 202 203/* jump address; j insn (this is basically the same as 'L' except that the 204 value is right shifted by 2). */ 205#define JUMP (BRANCH + 1) 206 { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 }, 207 208/* jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */ 209#define JUMPFLAGS (JUMP + 1) 210 { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags }, 211 212/* size field, stored in bit 1,2. */ 213#define SIZE1 (JUMPFLAGS + 1) 214 { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 }, 215 216/* size field, stored in bit 10,11. */ 217#define SIZE10 (SIZE1 + 1) 218 { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 }, 219 220/* size field, stored in bit 22,23. */ 221#define SIZE22 (SIZE10 + 1) 222 { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 }, 223 224/* sign extend field, stored in bit 0. */ 225#define SIGN0 (SIZE22 + 1) 226 { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 }, 227 228/* sign extend field, stored in bit 9. */ 229#define SIGN9 (SIGN0 + 1) 230 { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 }, 231 232/* address write back, stored in bit 3. */ 233#define ADDRESS3 (SIGN9 + 1) 234 { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, 235 236/* address write back, stored in bit 12. */ 237#define ADDRESS12 (ADDRESS3 + 1) 238 { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, 239 240/* address write back, stored in bit 24. */ 241#define ADDRESS24 (ADDRESS12 + 1) 242 { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, 243 244/* cache bypass, stored in bit 5. */ 245#define CACHEBYPASS5 (ADDRESS24 + 1) 246 { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 }, 247 248/* cache bypass, stored in bit 14. */ 249#define CACHEBYPASS14 (CACHEBYPASS5 + 1) 250 { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 }, 251 252/* cache bypass, stored in bit 26. */ 253#define CACHEBYPASS26 (CACHEBYPASS14 + 1) 254 { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 }, 255 256/* unop macro, used to copy REGB to REGC. */ 257#define UNOPMACRO (CACHEBYPASS26 + 1) 258 { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, 259 260/* '.' modifier ('.' required). */ 261#define MODDOT (UNOPMACRO + 1) 262 { '.', 1, 0, ARC_MOD_DOT, 0, 0 }, 263 264/* Dummy 'r' modifier for the register table. 265 It's called a "dummy" because there's no point in inserting an 'r' into all 266 the %a/%b/%c occurrences in the insn table. */ 267#define REG (MODDOT + 1) 268 { 'r', 6, 0, ARC_MOD_REG, 0, 0 }, 269 270/* Known auxiliary register modifier (stored in shimm field). */ 271#define AUXREG (REG + 1) 272 { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 }, 273 274/* end of list place holder. */ 275 { 0, 0, 0, 0, 0, 0 } 276}; 277 278/* Given a format letter, yields the index into `arc_operands'. 279 eg: arc_operand_map['a'] = REGA. */ 280unsigned char arc_operand_map[256]; 281 282/* ARC instructions. 283 284 Longer versions of insns must appear before shorter ones (if gas sees 285 "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is 286 junk). This isn't necessary for `ld' because of the trailing ']'. 287 288 Instructions that are really macros based on other insns must appear 289 before the real insn so they're chosen when disassembling. Eg: The `mov' 290 insn is really the `and' insn. */ 291 292struct arc_opcode arc_opcodes[] = 293{ 294 /* Base case instruction set (core versions 5-8) */ 295 296 /* "mov" is really an "and". */ 297 { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 }, 298 /* "asl" is really an "add". */ 299 { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, 300 /* "lsl" is really an "add". */ 301 { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, 302 /* "nop" is really an "xor". */ 303 { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 }, 304 /* "rlc" is really an "adc". */ 305 { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 }, 306 { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 }, 307 { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 }, 308 { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 }, 309 { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 }, 310 { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 }, 311 { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, 312 { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, 313 { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 }, 314 { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 }, 315 { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 }, 316 { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 }, 317 { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 }, 318 { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 }, 319 /* %Q: force cond_p=1 -> no shimm values. This insn allows an 320 optional flags spec. */ 321 { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, 322 { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, 323 /* This insn allows an optional flags spec. */ 324 { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, 325 { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, 326 /* Put opcode 1 ld insns first so shimm gets prefered over limm. 327 "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ 328 { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 }, 329 { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, 330 { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, 331 { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 }, 332 { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 }, 333 { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 }, 334 { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 }, 335 { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 }, 336 { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 }, 337 { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 }, 338 { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 }, 339 { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 }, 340 { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 }, 341 { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 }, 342 /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ 343 { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, 344 { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, 345 { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 }, 346 { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 } 347}; 348 349const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); 350 351const struct arc_operand_value arc_reg_names[] = 352{ 353 /* Core register set r0-r63. */ 354 355 /* r0-r28 - general purpose registers. */ 356 { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 }, 357 { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 }, 358 { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 }, 359 { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 }, 360 { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 }, 361 { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 }, 362 { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 }, 363 { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 }, 364 { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 }, 365 { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 }, 366 /* Maskable interrupt link register. */ 367 { "ilink1", 29, REG, 0 }, 368 /* Maskable interrupt link register. */ 369 { "ilink2", 30, REG, 0 }, 370 /* Branch-link register. */ 371 { "blink", 31, REG, 0 }, 372 373 /* r32-r59 reserved for extensions. */ 374 { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 }, 375 { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 }, 376 { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 }, 377 { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 }, 378 { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 }, 379 { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 }, 380 { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 }, 381 { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 }, 382 { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 }, 383 { "r59", 59, REG, 0 }, 384 385 /* Loop count register (24 bits). */ 386 { "lp_count", 60, REG, 0 }, 387 /* Short immediate data indicator setting flags. */ 388 { "r61", 61, REG, ARC_REGISTER_READONLY }, 389 /* Long immediate data indicator setting flags. */ 390 { "r62", 62, REG, ARC_REGISTER_READONLY }, 391 /* Short immediate data indicator not setting flags. */ 392 { "r63", 63, REG, ARC_REGISTER_READONLY }, 393 394 /* Small-data base register. */ 395 { "gp", 26, REG, 0 }, 396 /* Frame pointer. */ 397 { "fp", 27, REG, 0 }, 398 /* Stack pointer. */ 399 { "sp", 28, REG, 0 }, 400 401 { "r29", 29, REG, 0 }, 402 { "r30", 30, REG, 0 }, 403 { "r31", 31, REG, 0 }, 404 { "r60", 60, REG, 0 }, 405 406 /* Auxiliary register set. */ 407 408 /* Auxiliary register address map: 409 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation 410 0xfffffeff-0x80000000 - customer limm allocation 411 0x7fffffff-0x00000100 - ARC limm allocation 412 0x000000ff-0x00000000 - ARC shimm allocation */ 413 414 /* Base case auxiliary registers (shimm address). */ 415 { "status", 0x00, AUXREG, 0 }, 416 { "semaphore", 0x01, AUXREG, 0 }, 417 { "lp_start", 0x02, AUXREG, 0 }, 418 { "lp_end", 0x03, AUXREG, 0 }, 419 { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY }, 420 { "debug", 0x05, AUXREG, 0 }, 421}; 422 423const int arc_reg_names_count = 424 sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); 425 426/* The suffix table. 427 Operands with the same name must be stored together. */ 428 429const struct arc_operand_value arc_suffixes[] = 430{ 431 /* Entry 0 is special, default values aren't printed by the disassembler. */ 432 { "", 0, -1, 0 }, 433 434 /* Base case condition codes. */ 435 { "al", 0, COND, 0 }, 436 { "ra", 0, COND, 0 }, 437 { "eq", 1, COND, 0 }, 438 { "z", 1, COND, 0 }, 439 { "ne", 2, COND, 0 }, 440 { "nz", 2, COND, 0 }, 441 { "pl", 3, COND, 0 }, 442 { "p", 3, COND, 0 }, 443 { "mi", 4, COND, 0 }, 444 { "n", 4, COND, 0 }, 445 { "cs", 5, COND, 0 }, 446 { "c", 5, COND, 0 }, 447 { "lo", 5, COND, 0 }, 448 { "cc", 6, COND, 0 }, 449 { "nc", 6, COND, 0 }, 450 { "hs", 6, COND, 0 }, 451 { "vs", 7, COND, 0 }, 452 { "v", 7, COND, 0 }, 453 { "vc", 8, COND, 0 }, 454 { "nv", 8, COND, 0 }, 455 { "gt", 9, COND, 0 }, 456 { "ge", 10, COND, 0 }, 457 { "lt", 11, COND, 0 }, 458 { "le", 12, COND, 0 }, 459 { "hi", 13, COND, 0 }, 460 { "ls", 14, COND, 0 }, 461 { "pnz", 15, COND, 0 }, 462 463 /* Condition codes 16-31 reserved for extensions. */ 464 465 { "f", 1, FLAG, 0 }, 466 467 { "nd", ARC_DELAY_NONE, DELAY, 0 }, 468 { "d", ARC_DELAY_NORMAL, DELAY, 0 }, 469 { "jd", ARC_DELAY_JUMP, DELAY, 0 }, 470 471 { "b", 1, SIZE1, 0 }, 472 { "b", 1, SIZE10, 0 }, 473 { "b", 1, SIZE22, 0 }, 474 { "w", 2, SIZE1, 0 }, 475 { "w", 2, SIZE10, 0 }, 476 { "w", 2, SIZE22, 0 }, 477 { "x", 1, SIGN0, 0 }, 478 { "x", 1, SIGN9, 0 }, 479 { "a", 1, ADDRESS3, 0 }, 480 { "a", 1, ADDRESS12, 0 }, 481 { "a", 1, ADDRESS24, 0 }, 482 483 { "di", 1, CACHEBYPASS5, 0 }, 484 { "di", 1, CACHEBYPASS14, 0 }, 485 { "di", 1, CACHEBYPASS26, 0 }, 486}; 487 488const int arc_suffixes_count = 489 sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); 490 491/* Indexed by first letter of opcode. Points to chain of opcodes with same 492 first letter. */ 493static struct arc_opcode *opcode_map[26 + 1]; 494 495/* Indexed by insn code. Points to chain of opcodes with same insn code. */ 496static struct arc_opcode *icode_map[32]; 497 498/* Configuration flags. */ 499 500/* Various ARC_HAVE_XXX bits. */ 501static int cpu_type; 502 503/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ 504 505int 506arc_get_opcode_mach (bfd_mach, big_p) 507 int bfd_mach, big_p; 508{ 509 static int mach_type_map[] = 510 { 511 ARC_MACH_5, 512 ARC_MACH_6, 513 ARC_MACH_7, 514 ARC_MACH_8 515 }; 516 return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0); 517} 518 519/* Initialize any tables that need it. 520 Must be called once at start up (or when first needed). 521 522 FLAGS is a set of bits that say what version of the cpu we have, 523 and in particular at least (one of) ARC_MACH_XXX. */ 524 525void 526arc_opcode_init_tables (flags) 527 int flags; 528{ 529 static int init_p = 0; 530 531 cpu_type = flags; 532 533 /* We may be intentionally called more than once (for example gdb will call 534 us each time the user switches cpu). These tables only need to be init'd 535 once though. */ 536 if (!init_p) 537 { 538 register int i,n; 539 540 memset (arc_operand_map, 0, sizeof (arc_operand_map)); 541 n = sizeof (arc_operands) / sizeof (arc_operands[0]); 542 for (i = 0; i < n; ++i) 543 arc_operand_map[arc_operands[i].fmt] = i; 544 545 memset (opcode_map, 0, sizeof (opcode_map)); 546 memset (icode_map, 0, sizeof (icode_map)); 547 /* Scan the table backwards so macros appear at the front. */ 548 for (i = arc_opcodes_count - 1; i >= 0; --i) 549 { 550 int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); 551 int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); 552 553 arc_opcodes[i].next_asm = opcode_map[opcode_hash]; 554 opcode_map[opcode_hash] = &arc_opcodes[i]; 555 556 arc_opcodes[i].next_dis = icode_map[icode_hash]; 557 icode_map[icode_hash] = &arc_opcodes[i]; 558 } 559 560 init_p = 1; 561 } 562} 563 564/* Return non-zero if OPCODE is supported on the specified cpu. 565 Cpu selection is made when calling `arc_opcode_init_tables'. */ 566 567int 568arc_opcode_supported (opcode) 569 const struct arc_opcode *opcode; 570{ 571 if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type) 572 return 1; 573 return 0; 574} 575 576/* Return the first insn in the chain for assembling INSN. */ 577 578const struct arc_opcode * 579arc_opcode_lookup_asm (insn) 580 const char *insn; 581{ 582 return opcode_map[ARC_HASH_OPCODE (insn)]; 583} 584 585/* Return the first insn in the chain for disassembling INSN. */ 586 587const struct arc_opcode * 588arc_opcode_lookup_dis (insn) 589 unsigned int insn; 590{ 591 return icode_map[ARC_HASH_ICODE (insn)]; 592} 593 594/* Nonzero if we've seen an 'f' suffix (in certain insns). */ 595static int flag_p; 596 597/* Nonzero if we've finished processing the 'f' suffix. */ 598static int flagshimm_handled_p; 599 600/* Nonzero if we've seen a 'a' suffix (address writeback). */ 601static int addrwb_p; 602 603/* Nonzero if we've seen a 'q' suffix (condition code). */ 604static int cond_p; 605 606/* Nonzero if we've inserted a nullify condition. */ 607static int nullify_p; 608 609/* The value of the a nullify condition we inserted. */ 610static int nullify; 611 612/* Nonzero if we've inserted jumpflags. */ 613static int jumpflags_p; 614 615/* Nonzero if we've inserted a shimm. */ 616static int shimm_p; 617 618/* The value of the shimm we inserted (each insn only gets one but it can 619 appear multiple times). */ 620static int shimm; 621 622/* Nonzero if we've inserted a limm (during assembly) or seen a limm 623 (during disassembly). */ 624static int limm_p; 625 626/* The value of the limm we inserted. Each insn only gets one but it can 627 appear multiple times. */ 628static long limm; 629 630/* Insertion functions. */ 631 632/* Called by the assembler before parsing an instruction. */ 633 634void 635arc_opcode_init_insert () 636{ 637 int i; 638 639 for(i = 0; i < OPERANDS; i++) 640 ls_operand[i] = OP_NONE; 641 642 flag_p = 0; 643 flagshimm_handled_p = 0; 644 cond_p = 0; 645 addrwb_p = 0; 646 shimm_p = 0; 647 limm_p = 0; 648 jumpflags_p = 0; 649 nullify_p = 0; 650 nullify = 0; /* the default is important. */ 651} 652 653/* Called by the assembler to see if the insn has a limm operand. 654 Also called by the disassembler to see if the insn contains a limm. */ 655 656int 657arc_opcode_limm_p (limmp) 658 long *limmp; 659{ 660 if (limmp) 661 *limmp = limm; 662 return limm_p; 663} 664 665/* Insert a value into a register field. 666 If REG is NULL, then this is actually a constant. 667 668 We must also handle auxiliary registers for lr/sr insns. */ 669 670static arc_insn 671insert_reg (insn, operand, mods, reg, value, errmsg) 672 arc_insn insn; 673 const struct arc_operand *operand; 674 int mods; 675 const struct arc_operand_value *reg; 676 long value; 677 const char **errmsg; 678{ 679 static char buf[100]; 680 enum operand op_type = OP_NONE; 681 682 if (reg == NULL) 683 { 684 /* We have a constant that also requires a value stored in a register 685 field. Handle these by updating the register field and saving the 686 value for later handling by either %S (shimm) or %L (limm). */ 687 688 /* Try to use a shimm value before a limm one. */ 689 if (ARC_SHIMM_CONST_P (value) 690 /* If we've seen a conditional suffix we have to use a limm. */ 691 && !cond_p 692 /* If we already have a shimm value that is different than ours 693 we have to use a limm. */ 694 && (!shimm_p || shimm == value)) 695 { 696 int marker; 697 698 op_type = OP_SHIMM; 699 /* forget about shimm as dest mlm. */ 700 701 if ('a' != operand->fmt) 702 { 703 shimm_p = 1; 704 shimm = value; 705 flagshimm_handled_p = 1; 706 marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; 707 } 708 else 709 { 710 /* don't request flag setting on shimm as dest. */ 711 marker = ARC_REG_SHIMM; 712 } 713 insn |= marker << operand->shift; 714 /* insn |= value & 511; - done later. */ 715 } 716 /* We have to use a limm. If we've already seen one they must match. */ 717 else if (!limm_p || limm == value) 718 { 719 op_type = OP_LIMM; 720 limm_p = 1; 721 limm = value; 722 insn |= ARC_REG_LIMM << operand->shift; 723 /* The constant is stored later. */ 724 } 725 else 726 { 727 *errmsg = "unable to fit different valued constants into instruction"; 728 } 729 } 730 else 731 { 732 /* We have to handle both normal and auxiliary registers. */ 733 734 if (reg->type == AUXREG) 735 { 736 if (!(mods & ARC_MOD_AUXREG)) 737 *errmsg = "auxiliary register not allowed here"; 738 else 739 { 740 if ((insn & I(-1)) == I(2)) /* check for use validity. */ 741 { 742 if (reg->flags & ARC_REGISTER_READONLY) 743 *errmsg = "attempt to set readonly register"; 744 } 745 else 746 { 747 if (reg->flags & ARC_REGISTER_WRITEONLY) 748 *errmsg = "attempt to read writeonly register"; 749 } 750 insn |= ARC_REG_SHIMM << operand->shift; 751 insn |= reg->value << arc_operands[reg->type].shift; 752 } 753 } 754 else 755 { 756 /* check for use validity. */ 757 if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) 758 { 759 if (reg->flags & ARC_REGISTER_READONLY) 760 *errmsg = "attempt to set readonly register"; 761 } 762 if ('a' != operand->fmt) 763 { 764 if (reg->flags & ARC_REGISTER_WRITEONLY) 765 *errmsg = "attempt to read writeonly register"; 766 } 767 /* We should never get an invalid register number here. */ 768 if ((unsigned int) reg->value > 60) 769 { 770 sprintf (buf, "invalid register number `%d'", reg->value); 771 *errmsg = buf; 772 } 773 insn |= reg->value << operand->shift; 774 op_type = OP_REG; 775 } 776 } 777 778 switch (operand->fmt) 779 { 780 case 'a': 781 ls_operand[LS_DEST] = op_type; 782 break; 783 case 's': 784 ls_operand[LS_BASE] = op_type; 785 break; 786 case 'c': 787 if ((insn & I(-1)) == I(2)) 788 ls_operand[LS_VALUE] = op_type; 789 else 790 ls_operand[LS_OFFSET] = op_type; 791 break; 792 case 'o': case 'O': 793 ls_operand[LS_OFFSET] = op_type; 794 break; 795 } 796 797 return insn; 798} 799 800/* Called when we see an 'f' flag. */ 801 802static arc_insn 803insert_flag (insn, operand, mods, reg, value, errmsg) 804 arc_insn insn; 805 const struct arc_operand *operand ATTRIBUTE_UNUSED; 806 int mods ATTRIBUTE_UNUSED; 807 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 808 long value ATTRIBUTE_UNUSED; 809 const char **errmsg ATTRIBUTE_UNUSED; 810{ 811 /* We can't store anything in the insn until we've parsed the registers. 812 Just record the fact that we've got this flag. `insert_reg' will use it 813 to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ 814 flag_p = 1; 815 return insn; 816} 817 818/* Called when we see an nullify condition. */ 819 820static arc_insn 821insert_nullify (insn, operand, mods, reg, value, errmsg) 822 arc_insn insn; 823 const struct arc_operand *operand; 824 int mods ATTRIBUTE_UNUSED; 825 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 826 long value; 827 const char **errmsg ATTRIBUTE_UNUSED; 828{ 829 nullify_p = 1; 830 insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; 831 nullify = value; 832 return insn; 833} 834 835/* Called after completely building an insn to ensure the 'f' flag gets set 836 properly. This is needed because we don't know how to set this flag until 837 we've parsed the registers. */ 838 839static arc_insn 840insert_flagfinish (insn, operand, mods, reg, value, errmsg) 841 arc_insn insn; 842 const struct arc_operand *operand; 843 int mods ATTRIBUTE_UNUSED; 844 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 845 long value ATTRIBUTE_UNUSED; 846 const char **errmsg ATTRIBUTE_UNUSED; 847{ 848 if (flag_p && !flagshimm_handled_p) 849 { 850 if (shimm_p) 851 abort (); 852 flagshimm_handled_p = 1; 853 insn |= (1 << operand->shift); 854 } 855 return insn; 856} 857 858/* Called when we see a conditional flag (eg: .eq). */ 859 860static arc_insn 861insert_cond (insn, operand, mods, reg, value, errmsg) 862 arc_insn insn; 863 const struct arc_operand *operand; 864 int mods ATTRIBUTE_UNUSED; 865 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 866 long value; 867 const char **errmsg ATTRIBUTE_UNUSED; 868{ 869 cond_p = 1; 870 insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; 871 return insn; 872} 873 874/* Used in the "j" instruction to prevent constants from being interpreted as 875 shimm values (which the jump insn doesn't accept). This can also be used 876 to force the use of limm values in other situations (eg: ld r0,[foo] uses 877 this). 878 ??? The mechanism is sound. Access to it is a bit klunky right now. */ 879 880static arc_insn 881insert_forcelimm (insn, operand, mods, reg, value, errmsg) 882 arc_insn insn; 883 const struct arc_operand *operand ATTRIBUTE_UNUSED; 884 int mods ATTRIBUTE_UNUSED; 885 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 886 long value ATTRIBUTE_UNUSED; 887 const char **errmsg ATTRIBUTE_UNUSED; 888{ 889 cond_p = 1; 890 return insn; 891} 892 893static arc_insn 894insert_addr_wb (insn, operand, mods, reg, value, errmsg) 895 arc_insn insn; 896 const struct arc_operand *operand; 897 int mods ATTRIBUTE_UNUSED; 898 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 899 long value ATTRIBUTE_UNUSED; 900 const char **errmsg ATTRIBUTE_UNUSED; 901{ 902 addrwb_p = 1 << operand->shift; 903 return insn; 904} 905 906static arc_insn 907insert_base (insn, operand, mods, reg, value, errmsg) 908 arc_insn insn; 909 const struct arc_operand *operand; 910 int mods; 911 const struct arc_operand_value *reg; 912 long value; 913 const char **errmsg; 914{ 915 if (reg != NULL) 916 { 917 arc_insn myinsn; 918 myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift; 919 insn |= B(myinsn); 920 ls_operand[LS_BASE] = OP_REG; 921 } 922 else if (ARC_SHIMM_CONST_P (value) && !cond_p) 923 { 924 if (shimm_p && value != shimm) 925 { 926 /* convert the previous shimm operand to a limm. */ 927 limm_p = 1; 928 limm = shimm; 929 insn &= ~C(-1); /* we know where the value is in insn. */ 930 insn |= C(ARC_REG_LIMM); 931 ls_operand[LS_VALUE] = OP_LIMM; 932 } 933 insn |= ARC_REG_SHIMM << operand->shift; 934 shimm_p = 1; 935 shimm = value; 936 ls_operand[LS_BASE] = OP_SHIMM; 937 } 938 else 939 { 940 if (limm_p && value != limm) 941 { 942 *errmsg = "too many long constants"; 943 return insn; 944 } 945 limm_p = 1; 946 limm = value; 947 insn |= B(ARC_REG_LIMM); 948 ls_operand[LS_BASE] = OP_LIMM; 949 } 950 951 return insn; 952} 953 954/* Used in ld/st insns to handle the offset field. We don't try to 955 match operand syntax here. we catch bad combinations later. */ 956 957static arc_insn 958insert_offset (insn, operand, mods, reg, value, errmsg) 959 arc_insn insn; 960 const struct arc_operand *operand; 961 int mods; 962 const struct arc_operand_value *reg; 963 long value; 964 const char **errmsg; 965{ 966 long minval, maxval; 967 968 if (reg != NULL) 969 { 970 arc_insn myinsn; 971 myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift; 972 ls_operand[LS_OFFSET] = OP_REG; 973 if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later. */ 974 if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later. */ 975 insn |= C(myinsn); 976 } 977 else 978 { 979 /* This is *way* more general than necessary, but maybe some day it'll 980 be useful. */ 981 if (operand->flags & ARC_OPERAND_SIGNED) 982 { 983 minval = -(1 << (operand->bits - 1)); 984 maxval = (1 << (operand->bits - 1)) - 1; 985 } 986 else 987 { 988 minval = 0; 989 maxval = (1 << operand->bits) - 1; 990 } 991 if ((cond_p && !limm_p) || (value < minval || value > maxval)) 992 { 993 if (limm_p && value != limm) 994 { 995 *errmsg = "too many long constants"; 996 } 997 else 998 { 999 limm_p = 1; 1000 limm = value; 1001 if (operand->flags & ARC_OPERAND_STORE) 1002 insn |= B(ARC_REG_LIMM); 1003 if (operand->flags & ARC_OPERAND_LOAD) 1004 insn |= C(ARC_REG_LIMM); 1005 ls_operand[LS_OFFSET] = OP_LIMM; 1006 } 1007 } 1008 else 1009 { 1010 if ((value < minval || value > maxval)) 1011 *errmsg = "need too many limms"; 1012 else if (shimm_p && value != shimm) 1013 { 1014 /* check for bad operand combinations before we lose info about them. */ 1015 if ((insn & I(-1)) == I(1)) 1016 { 1017 *errmsg = "to many shimms in load"; 1018 goto out; 1019 } 1020 if (limm_p && operand->flags & ARC_OPERAND_LOAD) 1021 { 1022 *errmsg = "too many long constants"; 1023 goto out; 1024 } 1025 /* convert what we thought was a shimm to a limm. */ 1026 limm_p = 1; 1027 limm = shimm; 1028 if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) 1029 { 1030 insn &= ~C(-1); 1031 insn |= C(ARC_REG_LIMM); 1032 ls_operand[LS_VALUE] = OP_LIMM; 1033 } 1034 if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) 1035 { 1036 insn &= ~B(-1); 1037 insn |= B(ARC_REG_LIMM); 1038 ls_operand[LS_BASE] = OP_LIMM; 1039 } 1040 } 1041 shimm = value; 1042 shimm_p = 1; 1043 ls_operand[LS_OFFSET] = OP_SHIMM; 1044 } 1045 } 1046 out: 1047 return insn; 1048} 1049 1050/* Used in st insns to do final disasemble syntax check. */ 1051 1052static long 1053extract_st_syntax (insn, operand, mods, opval, invalid) 1054 arc_insn *insn; 1055 const struct arc_operand *operand ATTRIBUTE_UNUSED; 1056 int mods ATTRIBUTE_UNUSED; 1057 const struct arc_operand_value **opval ATTRIBUTE_UNUSED; 1058 int *invalid; 1059{ 1060#define ST_SYNTAX(V,B,O) \ 1061((ls_operand[LS_VALUE] == (V) && \ 1062 ls_operand[LS_BASE] == (B) && \ 1063 ls_operand[LS_OFFSET] == (O))) 1064 1065 if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0) 1066 || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) 1067 || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) 1068 || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0) 1069 || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) 1070 || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM) 1071 || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) 1072 || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) 1073 || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) 1074 || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) 1075 || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) 1076 || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) 1077 || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE) 1078 || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) 1079 *invalid = 1; 1080 return 0; 1081} 1082 1083int 1084arc_limm_fixup_adjust(insn) 1085 arc_insn insn; 1086{ 1087 int retval = 0; 1088 1089 /* check for st shimm,[limm]. */ 1090 if ((insn & (I(-1) | C(-1) | B(-1))) == 1091 (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM))) 1092 { 1093 retval = insn & 0x1ff; 1094 if (retval & 0x100) /* sign extend 9 bit offset. */ 1095 retval |= ~0x1ff; 1096 } 1097 return -retval; /* negate offset for return. */ 1098} 1099 1100/* Used in st insns to do final syntax check. */ 1101 1102static arc_insn 1103insert_st_syntax (insn, operand, mods, reg, value, errmsg) 1104 arc_insn insn; 1105 const struct arc_operand *operand ATTRIBUTE_UNUSED; 1106 int mods ATTRIBUTE_UNUSED; 1107 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 1108 long value ATTRIBUTE_UNUSED; 1109 const char **errmsg; 1110{ 1111 if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0) 1112 { 1113 /* change an illegal insn into a legal one, it's easier to 1114 do it here than to try to handle it during operand scan. */ 1115 limm_p = 1; 1116 limm = shimm; 1117 shimm_p = 0; 1118 shimm = 0; 1119 insn = insn & ~(C(-1) | 511); 1120 insn |= ARC_REG_LIMM << ARC_SHIFT_REGC; 1121 ls_operand[LS_VALUE] = OP_LIMM; 1122 } 1123 1124 if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)) 1125 { 1126 /* try to salvage this syntax. */ 1127 if (shimm & 0x1) /* odd shimms won't work. */ 1128 { 1129 if (limm_p) /* do we have a limm already? */ 1130 { 1131 *errmsg = "impossible store"; 1132 } 1133 limm_p = 1; 1134 limm = shimm; 1135 shimm = 0; 1136 shimm_p = 0; 1137 insn = insn & ~(B(-1) | 511); 1138 insn |= B(ARC_REG_LIMM); 1139 ls_operand[LS_BASE] = OP_LIMM; 1140 } 1141 else 1142 { 1143 shimm >>= 1; 1144 insn = insn & ~511; 1145 insn |= shimm; 1146 ls_operand[LS_OFFSET] = OP_SHIMM; 1147 } 1148 } 1149 if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)) 1150 { 1151 limm += arc_limm_fixup_adjust(insn); 1152 } 1153 if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE) 1154 || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) 1155 || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) 1156 || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) 1157 || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) 1158 || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) 1159 || ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) 1160 || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) 1161 || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) 1162 || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) 1163 || ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) 1164 || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) 1165 *errmsg = "st operand error"; 1166 if (addrwb_p) 1167 { 1168 if (ls_operand[LS_BASE] != OP_REG) 1169 *errmsg = "address writeback not allowed"; 1170 insn |= addrwb_p; 1171 } 1172 if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm) 1173 *errmsg = "store value must be zero"; 1174 return insn; 1175} 1176 1177/* Used in ld insns to do final syntax check. */ 1178 1179static arc_insn 1180insert_ld_syntax (insn, operand, mods, reg, value, errmsg) 1181 arc_insn insn; 1182 const struct arc_operand *operand ATTRIBUTE_UNUSED; 1183 int mods ATTRIBUTE_UNUSED; 1184 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 1185 long value ATTRIBUTE_UNUSED; 1186 const char **errmsg; 1187{ 1188#define LD_SYNTAX(D,B,O) \ 1189((ls_operand[LS_DEST] == (D) && \ 1190 ls_operand[LS_BASE] == (B) && \ 1191 ls_operand[LS_OFFSET] == (O))) 1192 1193 int test = insn & I(-1); 1194 1195 if (!(test == I(1))) 1196 { 1197 if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM 1198 || ls_operand[LS_OFFSET] == OP_SHIMM)) 1199 *errmsg = "invalid load/shimm insn"; 1200 } 1201 if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE) 1202 || LD_SYNTAX(OP_REG,OP_REG,OP_REG) 1203 || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) 1204 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) 1205 || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) 1206 || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) 1207 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) 1208 *errmsg = "ld operand error"; 1209 if (addrwb_p) 1210 { 1211 if (ls_operand[LS_BASE] != OP_REG) 1212 *errmsg = "address writeback not allowed"; 1213 insn |= addrwb_p; 1214 } 1215 return insn; 1216} 1217 1218/* Used in ld insns to do final syntax check. */ 1219 1220static long 1221extract_ld_syntax (insn, operand, mods, opval, invalid) 1222 arc_insn *insn; 1223 const struct arc_operand *operand ATTRIBUTE_UNUSED; 1224 int mods ATTRIBUTE_UNUSED; 1225 const struct arc_operand_value **opval ATTRIBUTE_UNUSED; 1226 int *invalid; 1227{ 1228 int test = insn[0] & I(-1); 1229 1230 if (!(test == I(1))) 1231 { 1232 if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM 1233 || ls_operand[LS_OFFSET] == OP_SHIMM)) 1234 *invalid = 1; 1235 } 1236 if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1))) 1237 || LD_SYNTAX(OP_REG,OP_REG,OP_REG) 1238 || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) 1239 || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) 1240 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) 1241 || (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0)) 1242 || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) 1243 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) 1244 *invalid = 1; 1245 return 0; 1246} 1247 1248/* Called at the end of processing normal insns (eg: add) to insert a shimm 1249 value (if present) into the insn. */ 1250 1251static arc_insn 1252insert_shimmfinish (insn, operand, mods, reg, value, errmsg) 1253 arc_insn insn; 1254 const struct arc_operand *operand; 1255 int mods ATTRIBUTE_UNUSED; 1256 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 1257 long value ATTRIBUTE_UNUSED; 1258 const char **errmsg ATTRIBUTE_UNUSED; 1259{ 1260 if (shimm_p) 1261 insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; 1262 return insn; 1263} 1264 1265/* Called at the end of processing normal insns (eg: add) to insert a limm 1266 value (if present) into the insn. 1267 1268 Note that this function is only intended to handle instructions (with 4 byte 1269 immediate operands). It is not intended to handle data. */ 1270 1271/* ??? Actually, there's nothing for us to do as we can't call frag_more, the 1272 caller must do that. The extract fns take a pointer to two words. The 1273 insert fns could be converted and then we could do something useful, but 1274 then the reloc handlers would have to know to work on the second word of 1275 a 2 word quantity. That's too much so we don't handle them. */ 1276 1277static arc_insn 1278insert_limmfinish (insn, operand, mods, reg, value, errmsg) 1279 arc_insn insn; 1280 const struct arc_operand *operand ATTRIBUTE_UNUSED; 1281 int mods ATTRIBUTE_UNUSED; 1282 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 1283 long value ATTRIBUTE_UNUSED; 1284 const char **errmsg ATTRIBUTE_UNUSED; 1285{ 1286#if 0 1287 if (limm_p) 1288 ; /* nothing to do, gas does it. */ 1289#endif 1290 return insn; 1291} 1292 1293static arc_insn 1294insert_jumpflags (insn, operand, mods, reg, value, errmsg) 1295 arc_insn insn; 1296 const struct arc_operand *operand; 1297 int mods ATTRIBUTE_UNUSED; 1298 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 1299 long value; 1300 const char **errmsg; 1301{ 1302 if (!flag_p) 1303 { 1304 *errmsg = "jump flags, but no .f seen"; 1305 } 1306 if (!limm_p) 1307 { 1308 *errmsg = "jump flags, but no limm addr"; 1309 } 1310 if (limm & 0xfc000000) 1311 { 1312 *errmsg = "flag bits of jump address limm lost"; 1313 } 1314 if (limm & 0x03000000) 1315 { 1316 *errmsg = "attempt to set HR bits"; 1317 } 1318 if ((value & ((1 << operand->bits) - 1)) != value) 1319 { 1320 *errmsg = "bad jump flags value"; 1321 } 1322 jumpflags_p = 1; 1323 limm = ((limm & ((1 << operand->shift) - 1)) 1324 | ((value & ((1 << operand->bits) - 1)) << operand->shift)); 1325 return insn; 1326} 1327 1328/* Called at the end of unary operand macros to copy the B field to C. */ 1329 1330static arc_insn 1331insert_unopmacro (insn, operand, mods, reg, value, errmsg) 1332 arc_insn insn; 1333 const struct arc_operand *operand; 1334 int mods ATTRIBUTE_UNUSED; 1335 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 1336 long value ATTRIBUTE_UNUSED; 1337 const char **errmsg ATTRIBUTE_UNUSED; 1338{ 1339 insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; 1340 return insn; 1341} 1342 1343/* Insert a relative address for a branch insn (b, bl, or lp). */ 1344 1345static arc_insn 1346insert_reladdr (insn, operand, mods, reg, value, errmsg) 1347 arc_insn insn; 1348 const struct arc_operand *operand; 1349 int mods ATTRIBUTE_UNUSED; 1350 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 1351 long value; 1352 const char **errmsg; 1353{ 1354 if (value & 3) 1355 *errmsg = "branch address not on 4 byte boundary"; 1356 insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; 1357 return insn; 1358} 1359 1360/* Insert a limm value as a 26 bit address right shifted 2 into the insn. 1361 1362 Note that this function is only intended to handle instructions (with 4 byte 1363 immediate operands). It is not intended to handle data. */ 1364 1365/* ??? Actually, there's little for us to do as we can't call frag_more, the 1366 caller must do that. The extract fns take a pointer to two words. The 1367 insert fns could be converted and then we could do something useful, but 1368 then the reloc handlers would have to know to work on the second word of 1369 a 2 word quantity. That's too much so we don't handle them. 1370 1371 We do check for correct usage of the nullify suffix, or we 1372 set the default correctly, though. */ 1373 1374static arc_insn 1375insert_absaddr (insn, operand, mods, reg, value, errmsg) 1376 arc_insn insn; 1377 const struct arc_operand *operand ATTRIBUTE_UNUSED; 1378 int mods ATTRIBUTE_UNUSED; 1379 const struct arc_operand_value *reg ATTRIBUTE_UNUSED; 1380 long value ATTRIBUTE_UNUSED; 1381 const char **errmsg; 1382{ 1383 if (limm_p) 1384 { 1385 /* if it is a jump and link, .jd must be specified. */ 1386 if (insn & R(-1,9,1)) 1387 { 1388 if (!nullify_p) 1389 { 1390 insn |= 0x02 << 5; /* default nullify to .jd. */ 1391 } 1392 else 1393 { 1394 if (nullify != 0x02) 1395 { 1396 *errmsg = "must specify .jd or no nullify suffix"; 1397 } 1398 } 1399 } 1400 } 1401 return insn; 1402} 1403 1404/* Extraction functions. 1405 1406 The suffix extraction functions' return value is redundant since it can be 1407 obtained from (*OPVAL)->value. However, the boolean suffixes don't have 1408 a suffix table entry for the "false" case, so values of zero must be 1409 obtained from the return value (*OPVAL == NULL). */ 1410 1411static const struct arc_operand_value *lookup_register (int type, long regno); 1412 1413/* Called by the disassembler before printing an instruction. */ 1414 1415void 1416arc_opcode_init_extract () 1417{ 1418 arc_opcode_init_insert(); 1419} 1420 1421/* As we're extracting registers, keep an eye out for the 'f' indicator 1422 (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, 1423 like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. 1424 1425 We must also handle auxiliary registers for lr/sr insns. They are just 1426 constants with special names. */ 1427 1428static long 1429extract_reg (insn, operand, mods, opval, invalid) 1430 arc_insn *insn; 1431 const struct arc_operand *operand; 1432 int mods; 1433 const struct arc_operand_value **opval; 1434 int *invalid ATTRIBUTE_UNUSED; 1435{ 1436 int regno; 1437 long value; 1438 enum operand op_type; 1439 1440 /* Get the register number. */ 1441 regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1); 1442 1443 /* Is it a constant marker? */ 1444 if (regno == ARC_REG_SHIMM) 1445 { 1446 op_type = OP_SHIMM; 1447 /* always return zero if dest is a shimm mlm. */ 1448 1449 if ('a' != operand->fmt) 1450 { 1451 value = *insn & 511; 1452 if ((operand->flags & ARC_OPERAND_SIGNED) 1453 && (value & 256)) 1454 value -= 512; 1455 if (!flagshimm_handled_p) 1456 flag_p = 0; 1457 flagshimm_handled_p = 1; 1458 } 1459 else 1460 { 1461 value = 0; 1462 } 1463 } 1464 else if (regno == ARC_REG_SHIMM_UPDATE) 1465 { 1466 op_type = OP_SHIMM; 1467 1468 /* always return zero if dest is a shimm mlm. */ 1469 1470 if ('a' != operand->fmt) 1471 { 1472 value = *insn & 511; 1473 if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) 1474 value -= 512; 1475 } 1476 else 1477 { 1478 value = 0; 1479 } 1480 flag_p = 1; 1481 flagshimm_handled_p = 1; 1482 } 1483 else if (regno == ARC_REG_LIMM) 1484 { 1485 op_type = OP_LIMM; 1486 value = insn[1]; 1487 limm_p = 1; 1488 /* if this is a jump instruction (j,jl), show new pc correctly. */ 1489 if (0x07 == ((*insn & I(-1)) >> 27)) 1490 { 1491 value = (value & 0xffffff); 1492 } 1493 } 1494 /* It's a register, set OPVAL (that's the only way we distinguish registers 1495 from constants here). */ 1496 else 1497 { 1498 const struct arc_operand_value *reg = lookup_register (REG, regno); 1499 op_type = OP_REG; 1500 1501 if (reg == NULL) 1502 abort (); 1503 if (opval != NULL) 1504 *opval = reg; 1505 value = regno; 1506 } 1507 1508 /* If this field takes an auxiliary register, see if it's a known one. */ 1509 if ((mods & ARC_MOD_AUXREG) 1510 && ARC_REG_CONSTANT_P (regno)) 1511 { 1512 const struct arc_operand_value *reg = lookup_register (AUXREG, value); 1513 1514 /* This is really a constant, but tell the caller it has a special 1515 name. */ 1516 if (reg != NULL && opval != NULL) 1517 *opval = reg; 1518 } 1519 switch(operand->fmt) 1520 { 1521 case 'a': 1522 ls_operand[LS_DEST] = op_type; 1523 break; 1524 case 's': 1525 ls_operand[LS_BASE] = op_type; 1526 break; 1527 case 'c': 1528 if ((insn[0]& I(-1)) == I(2)) 1529 ls_operand[LS_VALUE] = op_type; 1530 else 1531 ls_operand[LS_OFFSET] = op_type; 1532 break; 1533 case 'o': case 'O': 1534 ls_operand[LS_OFFSET] = op_type; 1535 break; 1536 } 1537 1538 return value; 1539} 1540 1541/* Return the value of the "flag update" field for shimm insns. 1542 This value is actually stored in the register field. */ 1543 1544static long 1545extract_flag (insn, operand, mods, opval, invalid) 1546 arc_insn *insn; 1547 const struct arc_operand *operand; 1548 int mods ATTRIBUTE_UNUSED; 1549 const struct arc_operand_value **opval; 1550 int *invalid ATTRIBUTE_UNUSED; 1551{ 1552 int f; 1553 const struct arc_operand_value *val; 1554 1555 if (flagshimm_handled_p) 1556 f = flag_p != 0; 1557 else 1558 f = (*insn & (1 << operand->shift)) != 0; 1559 1560 /* There is no text for zero values. */ 1561 if (f == 0) 1562 return 0; 1563 flag_p = 1; 1564 val = arc_opcode_lookup_suffix (operand, 1); 1565 if (opval != NULL && val != NULL) 1566 *opval = val; 1567 return val->value; 1568} 1569 1570/* Extract the condition code (if it exists). 1571 If we've seen a shimm value in this insn (meaning that the insn can't have 1572 a condition code field), then we don't store anything in OPVAL and return 1573 zero. */ 1574 1575static long 1576extract_cond (insn, operand, mods, opval, invalid) 1577 arc_insn *insn; 1578 const struct arc_operand *operand; 1579 int mods ATTRIBUTE_UNUSED; 1580 const struct arc_operand_value **opval; 1581 int *invalid ATTRIBUTE_UNUSED; 1582{ 1583 long cond; 1584 const struct arc_operand_value *val; 1585 1586 if (flagshimm_handled_p) 1587 return 0; 1588 1589 cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); 1590 val = arc_opcode_lookup_suffix (operand, cond); 1591 1592 /* Ignore NULL values of `val'. Several condition code values are 1593 reserved for extensions. */ 1594 if (opval != NULL && val != NULL) 1595 *opval = val; 1596 return cond; 1597} 1598 1599/* Extract a branch address. 1600 We return the value as a real address (not right shifted by 2). */ 1601 1602static long 1603extract_reladdr (insn, operand, mods, opval, invalid) 1604 arc_insn *insn; 1605 const struct arc_operand *operand; 1606 int mods ATTRIBUTE_UNUSED; 1607 const struct arc_operand_value **opval ATTRIBUTE_UNUSED; 1608 int *invalid ATTRIBUTE_UNUSED; 1609{ 1610 long addr; 1611 1612 addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); 1613 if ((operand->flags & ARC_OPERAND_SIGNED) 1614 && (addr & (1 << (operand->bits - 1)))) 1615 addr -= 1 << operand->bits; 1616 return addr << 2; 1617} 1618 1619/* extract the flags bits from a j or jl long immediate. */ 1620static long 1621extract_jumpflags(insn, operand, mods, opval, invalid) 1622 arc_insn *insn; 1623 const struct arc_operand *operand; 1624 int mods ATTRIBUTE_UNUSED; 1625 const struct arc_operand_value **opval ATTRIBUTE_UNUSED; 1626 int *invalid; 1627{ 1628 if (!flag_p || !limm_p) 1629 *invalid = 1; 1630 return ((flag_p && limm_p) 1631 ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); 1632} 1633 1634/* extract st insn's offset. */ 1635 1636static long 1637extract_st_offset (insn, operand, mods, opval, invalid) 1638 arc_insn *insn; 1639 const struct arc_operand *operand; 1640 int mods ATTRIBUTE_UNUSED; 1641 const struct arc_operand_value **opval ATTRIBUTE_UNUSED; 1642 int *invalid; 1643{ 1644 int value = 0; 1645 1646 if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) 1647 { 1648 value = insn[0] & 511; 1649 if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) 1650 value -= 512; 1651 if (value) 1652 ls_operand[LS_OFFSET] = OP_SHIMM; 1653 } 1654 else 1655 { 1656 *invalid = 1; 1657 } 1658 return(value); 1659} 1660 1661/* extract ld insn's offset. */ 1662 1663static long 1664extract_ld_offset (insn, operand, mods, opval, invalid) 1665 arc_insn *insn; 1666 const struct arc_operand *operand; 1667 int mods; 1668 const struct arc_operand_value **opval; 1669 int *invalid; 1670{ 1671 int test = insn[0] & I(-1); 1672 int value; 1673 1674 if (test) 1675 { 1676 value = insn[0] & 511; 1677 if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) 1678 value -= 512; 1679 if (value) 1680 ls_operand[LS_OFFSET] = OP_SHIMM; 1681 return(value); 1682 } 1683 /* if it isn't in the insn, it's concealed behind reg 'c'. */ 1684 return extract_reg (insn, &arc_operands[arc_operand_map['c']], 1685 mods, opval, invalid); 1686} 1687 1688/* The only thing this does is set the `invalid' flag if B != C. 1689 This is needed because the "mov" macro appears before it's real insn "and" 1690 and we don't want the disassembler to confuse them. */ 1691 1692static long 1693extract_unopmacro (insn, operand, mods, opval, invalid) 1694 arc_insn *insn; 1695 const struct arc_operand *operand ATTRIBUTE_UNUSED; 1696 int mods ATTRIBUTE_UNUSED; 1697 const struct arc_operand_value **opval ATTRIBUTE_UNUSED; 1698 int *invalid; 1699{ 1700 /* This misses the case where B == ARC_REG_SHIMM_UPDATE && 1701 C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get 1702 printed as "and"s. */ 1703 if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) 1704 != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) 1705 if (invalid != NULL) 1706 *invalid = 1; 1707 return 0; 1708} 1709 1710/* Utility for the extraction functions to return the index into 1711 `arc_suffixes'. */ 1712 1713const struct arc_operand_value * 1714arc_opcode_lookup_suffix (type, value) 1715 const struct arc_operand *type; 1716 int value; 1717{ 1718 register const struct arc_operand_value *v,*end; 1719 struct arc_ext_operand_value *ext_oper = arc_ext_operands; 1720 1721 while (ext_oper) 1722 { 1723 if (type == &arc_operands[ext_oper->operand.type] 1724 && value == ext_oper->operand.value) 1725 return (&ext_oper->operand); 1726 ext_oper = ext_oper->next; 1727 } 1728 1729 /* ??? This is a little slow and can be speeded up. */ 1730 1731 for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) 1732 if (type == &arc_operands[v->type] 1733 && value == v->value) 1734 return v; 1735 return 0; 1736} 1737 1738static const struct arc_operand_value * 1739lookup_register (type, regno) 1740 int type; 1741 long regno; 1742{ 1743 register const struct arc_operand_value *r,*end; 1744 struct arc_ext_operand_value *ext_oper = arc_ext_operands; 1745 1746 while (ext_oper) 1747 { 1748 if (ext_oper->operand.type == type && ext_oper->operand.value == regno) 1749 return (&ext_oper->operand); 1750 ext_oper = ext_oper->next; 1751 } 1752 1753 if (type == REG) 1754 return &arc_reg_names[regno]; 1755 1756 /* ??? This is a little slow and can be speeded up. */ 1757 1758 for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; 1759 r < end; ++r) 1760 if (type == r->type && regno == r->value) 1761 return r; 1762 return 0; 1763} 1764 1765int 1766arc_insn_is_j(insn) 1767 arc_insn insn; 1768{ 1769 return (insn & (I(-1))) == I(0x7); 1770} 1771 1772int 1773arc_insn_not_jl(insn) 1774 arc_insn insn; 1775{ 1776 return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) 1777 != (I(0x7) | R(-1,9,1))); 1778} 1779 1780int 1781arc_operand_type(int opertype) 1782{ 1783 switch (opertype) 1784 { 1785 case 0: 1786 return(COND); 1787 break; 1788 case 1: 1789 return(REG); 1790 break; 1791 case 2: 1792 return(AUXREG); 1793 break; 1794 } 1795 return -1; 1796} 1797 1798struct arc_operand_value * 1799get_ext_suffix(s) 1800 char *s; 1801{ 1802 struct arc_ext_operand_value *suffix = arc_ext_operands; 1803 1804 while (suffix) 1805 { 1806 if ((COND == suffix->operand.type) 1807 && !strcmp(s,suffix->operand.name)) 1808 return(&suffix->operand); 1809 suffix = suffix->next; 1810 } 1811 return NULL; 1812} 1813 1814int 1815arc_get_noshortcut_flag() 1816{ 1817 return ARC_REGISTER_NOSHORT_CUT; 1818} 1819