ChangeLog-2006 revision 214634
12006-12-27 Kazu Hirata <kazu@codesourcery.com> 2 3 * m68k-dis.c (print_insn_arg): Add support for cac and mbb. 4 52006-12-27 Kazu Hirata <kazu@codesourcery.com> 6 7 * m68k-opc.c (m68k_opcodes): Add sleep and trapx. 8 92006-12-15 H.J. Lu <hongjiu.lu@intel.com> 10 11 * i386-dis.c (o_mode): New for 16-byte operand. 12 (intel_operand_size): Generate "OWORD PTR " for o_mode. 13 (CMPXCHG8B_Fixup): Set bytemode to o_mode instead of x_mode. 14 152006-12-14 H.J. Lu <hongjiu.lu@intel.com> 16 17 * i386-dis.c (CMPXCHG8B_Fixup): New. 18 (grps): Use CMPXCHG8B_Fixup for cmpxchg8b. 19 202006-12-11 H.J. Lu <hongjiu.lu@intel.com> 21 22 * i386-dis.c (Eq): Replaced by ... 23 (Mq): New. This. 24 (Ma): Defined with OP_M instead of OP_E. 25 (grps): Updated cmpxchg8b and vmptrst for Eq -> Mq. 26 (OP_M): Added bound, cmpxchg8b and vmptrst to bad modrm list. 27 282006-12-11 Daniel Jacobowitz <dan@codesourcery.com> 29 30 * po/Make-in (.po.gmo): Put gmo files in objdir. 31 322006-12-09 H.J. Lu <hongjiu.lu@intel.com> 33 34 * i386-dis.c (X86_64_1): New. 35 (X86_64_2): Likewise. 36 (X86_64_3): Likewise. 37 (dis386): Replace 0x60, 0x61 and 0x62 entries with x86-64 38 tables. 39 (x86_64_table): Add entries for 0x60, 0x61 and 0x62. 40 412006-12-09 H.J. Lu <hongjiu.lu@intel.com> 42 43 * i386-dis.c: Adjust white spaces. 44 452006-12-04 Jan Beulich <jbeulich@novell.com> 46 47 * i386-dis.c (OP_J): Update used_prefixes in v_mode. 48 492006-11-30 Jan Beulich <jbeulich@novell.com> 50 51 * i386-dis.c (SEG_Fixup): Delete. 52 (Sv): Use OP_SEG. 53 (putop): New suffix character 'D'. 54 (dis386): Use it. 55 (grps): Likewise. 56 (OP_SEG): Handle bytemode other than w_mode. 57 582006-11-30 Jan Beulich <jbeulich@novell.com> 59 60 * i386-dis.c (zAX): New. 61 (Xz): New. 62 (Yzr): New. 63 (z_mode): New. 64 (z_mode_ax_reg): New. 65 (putop): New suffix character 'G'. 66 (dis386): Use it for in, out, ins, and outs. 67 (intel_operand_size): Handle z_mode. 68 (OP_REG): Delete unreachable case indir_dx_reg. 69 (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle 70 z_mode_ax_reg. 71 (OP_ESreg): Fix Intel syntax operand size handling. 72 (OP_DSreg): Likewise. 73 742006-11-30 Jan Beulich <jbeulich@novell.com> 75 76 * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally. 77 (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix 78 used. For 'R' and 'W' suffix, simplify and fix Intel mode. 79 802006-11-29 Paul Brook <paul@codesourcery.com> 81 82 * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd. 83 842006-11-22 Daniel Jacobowitz <dan@codesourcery.com> 85 86 * arm-dis.c (last_is_thumb): Delete. 87 (enum map_type, last_type): New. 88 (print_insn_data): New. 89 (get_sym_code_type): Take MAP_TYPE argument. Check the type of 90 the right symbol. Handle $d. 91 (print_insn): Check for mapping symbols even without a normal 92 symbol. Adjust searching. If $d is found see how much data 93 to print. Handle data. 94 952006-11-16 Nathan Sidwell <nathan@codesourcery.com> 96 97 * m68k-opc.c (m68k_opcodes): Place trap instructions before set 98 conditionals. Add tpf coldfire instruction as alias for trapf. 99 1002006-11-09 H.J. Lu <hongjiu.lu@intel.com> 101 102 * i386-dis.c (print_insn): Check PREFIX_REPNZ before 103 PREFIX_DATA when prefix user table is used. 104 1052006-11-09 H.J. Lu <hongjiu.lu@intel.com> 106 107 * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ... 108 (twobyte_uses_DATA_prefix): This. 109 (twobyte_uses_REPNZ_prefix): New. 110 (twobyte_uses_REPZ_prefix): Likewise. 111 (threebyte_0x38_uses_DATA_prefix): Likewise. 112 (threebyte_0x38_uses_REPNZ_prefix): Likewise. 113 (threebyte_0x38_uses_REPZ_prefix): Likewise. 114 (threebyte_0x3a_uses_DATA_prefix): Likewise. 115 (threebyte_0x3a_uses_REPNZ_prefix): Likewise. 116 (threebyte_0x3a_uses_REPZ_prefix): Likewise. 117 (print_insn): Updated checking usages of DATA/REPNZ/REPZ 118 prefixes. 119 1202006-11-06 Troy Rollo <troy@corvu.com.au> 121 122 * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04. 123 1242006-11-01 Mei Ligang <ligang@sunnorth.com.cn> 125 126 * score-opc.h (score_opcodes): Delete modifier '0x'. 127 1282006-10-30 Paul Brook <paul@codesourcery.com> 129 130 * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New. 131 (get_sym_code_type): New function. 132 (print_insn): Search for mapping symbols. 133 1342006-10-31 Mei Ligang <ligang@sunnorth.com.cn> 135 136 * score-dis.c (print_insn): Correct the error code to print 137 correct PCE instruction disassembly. 138 1392006-10-26 Ben Elliston <bje@au.ibm.com> 140 Anton Blanchard <anton@samba.org> 141 Peter Bergner <bergner@vnet.ibm.com> 142 143 * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH, 144 AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define. 145 (POWER6): Define. 146 (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.", 147 "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.". 148 Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd", 149 "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr", 150 "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix", 151 "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul", 152 "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.", 153 "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc", 154 "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix", 155 "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.", 156 "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.", 157 "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.", 158 "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.", 159 "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.", 160 "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq", 161 "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.", 162 "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.", 163 "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq", 164 "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.", 165 "diexq" and "diexq." opcodes. 166 1672006-10-26 Daniel Jacobowitz <dan@codesourcery.com> 168 169 * h8300-dis.c (bfd_h8_disassemble): Add missing consts. 170 1712006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> 172 Yukishige Shibata <shibata@rd.scei.sony.co.jp> 173 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> 174 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> 175 Alan Modra <amodra@bigpond.net.au> 176 177 * spu-dis.c: New file. 178 * spu-opc.c: New file. 179 * configure.in: Add SPU support. 180 * disassemble.c: Likewise. 181 * Makefile.am: Likewise. Run "make dep-am". 182 * Makefile.in: Regenerate. 183 * configure: Regenerate. 184 * po/POTFILES.in: Regenerate. 185 1862006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> 187 188 * ppc-opc.c (CELL): New define. 189 (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx, 190 cell specific instructions. Add {st,l}x{r,l}{,l} cell specific 191 VMX instructions. 192 * ppc-dis.c (powerpc_dialect): Handle cell. 193 1942006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 195 196 * i386-dis.c (dis386): Add support for the change in POPCNT opcode in 197 amdfam10 architecture. 198 (PREGRP37): NEW. 199 (print_insn): Disallow REP prefix for POPCNT. 200 2012006-10-20 Andrew Stubbs <andrew.stubbs@st.com> 202 203 * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB 204 duplicating it. 205 2062006-10-18 Dave Brolley <brolley@redhat.com> 207 208 * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch. 209 * configure: Regenerated. 210 2112006-09-29 Alan Modra <amodra@bigpond.net.au> 212 213 * po/POTFILES.in: Regenerate. 214 2152006-09-26 Mark Shinwell <shinwell@codesourcery.com> 216 Joseph Myers <joseph@codesourcery.com> 217 Ian Lance Taylor <ian@wasabisystems.com> 218 Ben Elliston <bje@wasabisystems.com> 219 220 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may 221 only be used with the default multiply-add operation, so if N is 222 set, don't bother printing X. Add new iwmmxt instructions. 223 (IWMMXT_INSN_COUNT): Update. 224 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14 225 with a 'c' suffix. 226 (print_insn_coprocessor): Check for iWMMXt2. Handle format 227 specifiers 'r', 'i'. 228 2292006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 230 231 PR binutils/3100 232 * i386-dis.c (prefix_user_table): Fix the second operand of 233 maskmovdqu instruction to allow only %xmm register instead of 234 both %xmm register and memory. 235 2362006-09-23 H.J. Lu <hongjiu.lu@intel.com> 237 238 PR binutils/3235 239 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an 240 address size prefix. 241 2422006-09-17 Mei Ligang <ligang@sunnorth.com.cn> 243 244 * score-dis.c: New file. 245 * score-opc.h: New file. 246 * Makefile.am: Add Score files. 247 * Makefile.in: Regenerate. 248 * configure.in: Add support for Score target. 249 * configure: Regenerate. 250 * disassemble.c: Add support for Score target. 251 2522006-09-16 Nick Clifton <nickc@redhat.com> 253 Pedro Alves <pedro_alves@portugalmail.pt> 254 255 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ 256 macros defined in bfd.h. 257 * cris-dis.c: Likewise. 258 * h8300-dis.c: Likewise. 259 * i386-dis.c: Likewise. 260 * ia64-gen.c: Likewise. 261 * mips-dis: Likewise. 262 2632006-09-04 Paul Brook <paul@codesourcery.com> 264 265 * arm-dis.c (neon_opcode): Fix suffix on VMOVN. 266 2672006-08-23 H.J. Lu <hongjiu.lu@intel.com> 268 269 * i386-dis.c (three_byte_table): Expand to 256 elements. 270 2712006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 272 273 PR binutils/3000 274 * i386-dis.c (MXC,EMC): Define. 275 (OP_MXC): New function to handle cvt* (convert instructions) between 276 %xmm and %mm register correctly. 277 (OP_EMC): ditto. 278 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi 279 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately 280 with EMC/MXC. 281 2822006-07-29 Richard Sandiford <richard@codesourcery.com> 283 284 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire 285 "fdaddl" entry. 286 2872006-07-19 Paul Brook <paul@codesourcery.com> 288 289 * armd-dis.c (arm_opcodes): Fix rbit opcode. 290 2912006-07-18 H.J. Lu <hongjiu.lu@intel.com> 292 293 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to 294 "sldt", "str" and "smsw". 295 2962006-07-15 H.J. Lu <hongjiu.lu@intel.com> 297 298 PR binutils/2829 299 * i386-dis.c (GRP11_C6): NEW. 300 (GRP11_C7): Likewise. 301 (GRP12): Updated. 302 (GRP13): Likewise. 303 (GRP14): Likewise. 304 (GRP15): Likewise. 305 (GRP16): Likewise. 306 (GRPAMD): Likewise. 307 (GRPPADLCK1): Likewise. 308 (GRPPADLCK2): Likewise. 309 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7, 310 respectively. 311 (grps): Add entries for GRP11_C6 and GRP11_C7. 312 3132006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 314 Michael Meissner <michael.meissner@amd.com> 315 316 * i386-dis.c (dis386): Add support for 4 operand instructions. Add 317 support for amdfam10 SSE4a/ABM instructions. Modify all 318 initializer macros to have additional arguments. Disallow REP 319 prefix for non-string instructions. 320 (print_insn): Ditto. 321 3222006-07-05 Julian Brown <julian@codesourcery.com> 323 324 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax. 325 3262006-06-12 H.J. Lu <hongjiu.lu@intel.com> 327 328 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f. 329 (twobyte_has_modrm): Set 1 for 0x1f. 330 3312006-06-12 H.J. Lu <hongjiu.lu@intel.com> 332 333 * i386-dis.c (NOP_Fixup): Removed. 334 (NOP_Fixup1): New. 335 (NOP_Fixup2): Likewise. 336 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90. 337 3382006-06-12 Julian Brown <julian@codesourcery.com> 339 340 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed 341 on 64-bit hosts. 342 3432006-06-10 H.J. Lu <hongjiu.lu@intel.com> 344 345 * i386.c (GRP10): Renamed to ... 346 (GRP12): This. 347 (GRP11): Renamed to ... 348 (GRP13): This. 349 (GRP12): Renamed to ... 350 (GRP14): This. 351 (GRP13): Renamed to ... 352 (GRP15): This. 353 (GRP14): Renamed to ... 354 (GRP16): This. 355 (dis386_twobyte): Updated. 356 (grps): Likewise. 357 3582006-06-09 Nick Clifton <nickc@redhat.com> 359 360 * po/fi.po: Updated Finnish translation. 361 3622006-06-07 Joseph S. Myers <joseph@codesourcery.com> 363 364 * po/Make-in (pdf, ps): New dummy targets. 365 3662006-06-06 Paul Brook <paul@codesourcery.com> 367 368 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm 369 instructions. 370 (neon_opcodes): Add conditional execution specifiers. 371 (thumb_opcodes): Ditto. 372 (thumb32_opcodes): Ditto. 373 (arm_conditional): Change 0xe to "al" and add "" to end. 374 (ifthen_state, ifthen_next_state, ifthen_address): New. 375 (IFTHEN_COND): Define. 376 (print_insn_coprocessor, print_insn_neon): Print thumb conditions. 377 (print_insn_arm): Change %c to use new values of arm_conditional. 378 (print_insn_thumb16): Print thumb conditions. Add %I. 379 (print_insn_thumb32): Print thumb conditions. 380 (find_ifthen_state): New function. 381 (print_insn): Track IT block state. 382 3832006-06-06 Ben Elliston <bje@au.ibm.com> 384 Anton Blanchard <anton@samba.org> 385 Peter Bergner <bergner@vnet.ibm.com> 386 387 * ppc-dis.c (powerpc_dialect): Handle power6 option. 388 (print_ppc_disassembler_options): Mention power6. 389 3902006-06-06 Thiemo Seufer <ths@mips.com> 391 Chao-ying Fu <fu@mips.com> 392 393 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. 394 * mips-opc.c: Add DSP64 instructions. 395 3962006-06-06 Alan Modra <amodra@bigpond.net.au> 397 398 * m68hc11-dis.c (print_insn): Warning fix. 399 4002006-06-05 Daniel Jacobowitz <dan@codesourcery.com> 401 402 * po/Make-in (top_builddir): Define. 403 4042006-06-05 Alan Modra <amodra@bigpond.net.au> 405 406 * Makefile.am: Run "make dep-am". 407 * Makefile.in: Regenerate. 408 * config.in: Regenerate. 409 4102006-05-31 Daniel Jacobowitz <dan@codesourcery.com> 411 412 * Makefile.am (INCLUDES): Use @INCINTL@. 413 * acinclude.m4: Include new gettext macros. 414 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS. 415 Remove local code for po/Makefile. 416 * Makefile.in, aclocal.m4, configure: Regenerated. 417 4182006-05-30 Nick Clifton <nickc@redhat.com> 419 420 * po/es.po: Updated Spanish translation. 421 4222006-05-25 Richard Sandiford <richard@codesourcery.com> 423 424 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd 425 and fmovem entries. Put register list entries before immediate 426 mask entries. Use "l" rather than "L" in the fmovem entries. 427 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it 428 out from INFO. 429 (m68k_scan_mask): New function, split out from... 430 (print_insn_m68k): ...here. If no architecture has been set, 431 first try printing an m680x0 instruction, then try a Coldfire one. 432 4332006-05-24 Nick Clifton <nickc@redhat.com> 434 435 * po/ga.po: Updated Irish translation. 436 4372006-05-22 Nick Clifton <nickc@redhat.com> 438 439 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts. 440 4412006-05-22 Nick Clifton <nickc@redhat.com> 442 443 * po/nl.po: Updated translation. 444 4452006-05-18 Alan Modra <amodra@bigpond.net.au> 446 447 * avr-dis.c: Formatting fix. 448 4492006-05-14 Thiemo Seufer <ths@mips.com> 450 451 * mips16-opc.c (I1, I32, I64): New shortcut defines. 452 (mips16_opcodes): Change membership of instructions to their 453 lowest baseline ISA. 454 4552006-05-09 H.J. Lu <hongjiu.lu@intel.com> 456 457 * i386-dis.c (grps): Update sgdt/sidt for 64bit. 458 4592006-05-05 Julian Brown <julian@codesourcery.com> 460 461 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as 462 vldm/vstm. 463 4642006-05-05 Thiemo Seufer <ths@mips.com> 465 David Ung <davidu@mips.com> 466 467 * mips-opc.c: Add macro for cache instruction. 468 4692006-05-04 Thiemo Seufer <ths@mips.com> 470 Nigel Stephens <nigel@mips.com> 471 David Ung <davidu@mips.com> 472 473 * mips-dis.c (mips_arch_choices): Add smartmips instruction 474 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release 475 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to 476 MIPS64R2. 477 * mips-opc.c: fix random typos in comments. 478 (INSN_SMARTMIPS): New defines. 479 (mips_builtin_opcodes): Add paired single support for MIPS32R2. 480 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd, 481 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the 482 FP_S and FP_D flags to denote single and double register 483 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards. 484 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1 485 for MIPS32R2. Add SmartMIPS instructions. Add two-argument 486 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to 487 release 2 ISAs. 488 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction. 489 4902006-05-03 Thiemo Seufer <ths@mips.com> 491 492 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order. 493 4942006-05-02 Thiemo Seufer <ths@mips.com> 495 Nigel Stephens <nigel@mips.com> 496 David Ung <davidu@mips.com> 497 498 * mips-dis.c (print_insn_args): Force mips16 to odd addresses. 499 (print_mips16_insn_arg): Force mips16 to odd addresses. 500 5012006-04-30 Thiemo Seufer <ths@mips.com> 502 David Ung <davidu@mips.com> 503 504 * mips-opc.c (mips_builtin_opcodes): Add udi instructions 505 "udi0" to "udi15". 506 * mips-dis.c (print_insn_args): Adds udi argument handling. 507 5082006-04-28 James E Wilson <wilson@specifix.com> 509 510 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing 511 error message. 512 5132006-04-28 Thiemo Seufer <ths@mips.com> 514 David Ung <davidu@mips.com> 515 Nigel Stephens <nigel@mips.com> 516 517 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register 518 names. 519 5202006-04-28 Thiemo Seufer <ths@mips.com> 521 Nigel Stephens <nigel@mips.com> 522 David Ung <davidu@mips.com> 523 524 * mips-dis.c (print_insn_args): Add mips_opcode argument. 525 (print_insn_mips): Adjust print_insn_args call. 526 5272006-04-28 Thiemo Seufer <ths@mips.com> 528 Nigel Stephens <nigel@mips.com> 529 530 * mips-dis.c (print_insn_args): Print $fcc only for FP 531 instructions, use $cc elsewise. 532 5332006-04-28 Thiemo Seufer <ths@mips.com> 534 Nigel Stephens <nigel@mips.com> 535 536 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): 537 Map MIPS16 registers to O32 names. 538 (print_mips16_insn_arg): Use mips16_reg_names. 539 5402006-04-26 Julian Brown <julian@codesourcery.com> 541 542 * arm-dis.c (print_insn_neon): Disassemble floating-point constant 543 VMOV. 544 5452006-04-26 Nathan Sidwell <nathan@codesourcery.com> 546 Julian Brown <julian@codesourcery.com> 547 548 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert 549 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?]. 550 Add unified load/store instruction names. 551 (neon_opcode_table): New. 552 (arm_opcodes): Expand meaning of %<bitfield>['`?]. 553 (arm_decode_bitfield): New. 554 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers. 555 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y. 556 (print_insn_neon): New. 557 (print_insn_arm): Adjust print_insn_coprocessor call. Call 558 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers. 559 (print_insn_thumb32): Likewise. 560 5612006-04-19 Alan Modra <amodra@bigpond.net.au> 562 563 * Makefile.am: Run "make dep-am". 564 * Makefile.in: Regenerate. 565 5662006-04-19 Alan Modra <amodra@bigpond.net.au> 567 568 * avr-dis.c (avr_operand): Warning fix. 569 570 * configure: Regenerate. 571 5722006-04-16 Daniel Jacobowitz <dan@codesourcery.com> 573 574 * po/POTFILES.in: Regenerated. 575 5762006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de> 577 578 PR binutils/2454 579 * avr-dis.c (avr_operand): Arrange for a comment to appear before 580 the symolic form of an address, so that the output of objdump -d 581 can be reassembled. 582 5832006-04-10 DJ Delorie <dj@redhat.com> 584 585 * m32c-asm.c: Regenerate. 586 5872006-04-06 Carlos O'Donell <carlos@codesourcery.com> 588 589 * Makefile.am: Add install-html target. 590 * Makefile.in: Regenerate. 591 5922006-04-06 Nick Clifton <nickc@redhat.com> 593 594 * po/vi/po: Updated Vietnamese translation. 595 5962006-03-31 Paul Koning <ni1d@arrl.net> 597 598 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction. 599 6002006-03-16 Bernd Schmidt <bernd.schmidt@analog.com> 601 602 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the 603 logic to identify halfword shifts. 604 6052006-03-16 Paul Brook <paul@codesourcery.com> 606 607 * arm-dis.c (arm_opcodes): Rename swi to svc. 608 (thumb_opcodes): Ditto. 609 6102006-03-13 DJ Delorie <dj@redhat.com> 611 612 * m32c-asm.c: Regenerate. 613 * m32c-desc.c: Likewise. 614 * m32c-desc.h: Likewise. 615 * m32c-dis.c: Likewise. 616 * m32c-ibld.c: Likewise. 617 * m32c-opc.c: Likewise. 618 * m32c-opc.h: Likewise. 619 6202006-03-10 DJ Delorie <dj@redhat.com> 621 622 * m32c-desc.c: Regenerate with mul.l, mulu.l. 623 * m32c-opc.c: Likewise. 624 * m32c-opc.h: Likewise. 625 626 6272006-03-09 Nick Clifton <nickc@redhat.com> 628 629 * po/sv.po: Updated Swedish translation. 630 6312006-03-07 H.J. Lu <hongjiu.lu@intel.com> 632 633 PR binutils/2428 634 * i386-dis.c (REP_Fixup): New function. 635 (AL): Remove duplicate. 636 (Xbr): New. 637 (Xvr): Likewise. 638 (Ybr): Likewise. 639 (Yvr): Likewise. 640 (indirDXr): Likewise. 641 (ALr): Likewise. 642 (eAXr): Likewise. 643 (dis386): Updated entries of ins, outs, movs, lods and stos. 644 6452006-03-05 Nick Clifton <nickc@redhat.com> 646 647 * cgen-ibld.in (insert_normal): Cope with attempts to insert a 648 signed 32-bit value into an unsigned 32-bit field when the host is 649 a 64-bit machine. 650 * fr30-ibld.c: Regenerate. 651 * frv-ibld.c: Regenerate. 652 * ip2k-ibld.c: Regenerate. 653 * iq2000-asm.c: Regenerate. 654 * iq2000-ibld.c: Regenerate. 655 * m32c-ibld.c: Regenerate. 656 * m32r-ibld.c: Regenerate. 657 * openrisc-ibld.c: Regenerate. 658 * xc16x-ibld.c: Regenerate. 659 * xstormy16-ibld.c: Regenerate. 660 6612006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com) 662 663 * xc16x-asm.c: Regenerate. 664 * xc16x-dis.c: Regenerate. 665 6662006-02-27 Carlos O'Donell <carlos@codesourcery.com> 667 668 * po/Make-in: Add html target. 669 6702006-02-27 H.J. Lu <hongjiu.lu@intel.com> 671 672 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by 673 Intel Merom New Instructions. 674 (THREE_BYTE_0): Likewise. 675 (THREE_BYTE_1): Likewise. 676 (three_byte_table): Likewise. 677 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use 678 THREE_BYTE_1 for entry 0x3a. 679 (twobyte_has_modrm): Updated. 680 (twobyte_uses_SSE_prefix): Likewise. 681 (print_insn): Handle 3-byte opcodes used by Intel Merom New 682 Instructions. 683 6842006-02-24 David S. Miller <davem@sunset.davemloft.net> 685 686 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry. 687 (v9_hpriv_reg_names): New table. 688 (print_insn_sparc): Allow values up to 16 for '?' and '!'. 689 New cases '$' and '%' for read/write hyperprivileged register. 690 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005 691 window handling and rdhpr/wrhpr instructions. 692 6932006-02-24 DJ Delorie <dj@redhat.com> 694 695 * m32c-desc.c: Regenerate with linker relaxation attributes. 696 * m32c-desc.h: Likewise. 697 * m32c-dis.c: Likewise. 698 * m32c-opc.c: Likewise. 699 7002006-02-24 Paul Brook <paul@codesourcery.com> 701 702 * arm-dis.c (arm_opcodes): Add V7 instructions. 703 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. 704 (print_arm_address): New function. 705 (print_insn_arm): Use it. Add 'P' and 'U' cases. 706 (psr_name): New function. 707 (print_insn_thumb32): Add 'U', 'C' and 'D' cases. 708 7092006-02-23 H.J. Lu <hongjiu.lu@intel.com> 710 711 * ia64-opc-i.c (bXc): New. 712 (mXc): Likewise. 713 (OpX2TaTbYaXcC): Likewise. 714 (TF). Likewise. 715 (TFCM). Likewise. 716 (ia64_opcodes_i): Add instructions for tf. 717 718 * ia64-opc.h (IMMU5b): New. 719 720 * ia64-asmtab.c: Regenerated. 721 7222006-02-23 H.J. Lu <hongjiu.lu@intel.com> 723 724 * ia64-gen.c: Update copyright years. 725 * ia64-opc-b.c: Likewise. 726 7272006-02-22 H.J. Lu <hongjiu.lu@intel.com> 728 729 * ia64-gen.c (lookup_regindex): Handle ".vm". 730 (print_dependency_table): Handle '\"'. 731 732 * ia64-ic.tbl: Updated from SDM 2.2. 733 * ia64-raw.tbl: Likewise. 734 * ia64-waw.tbl: Likewise. 735 * ia64-asmtab.c: Regenerated. 736 737 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1. 738 7392006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com> 740 Anil Paranjape <anilp1@kpitcummins.com> 741 Shilin Shakti <shilins@kpitcummins.com> 742 743 * xc16x-desc.h: New file 744 * xc16x-desc.c: New file 745 * xc16x-opc.h: New file 746 * xc16x-opc.c: New file 747 * xc16x-ibld.c: New file 748 * xc16x-asm.c: New file 749 * xc16x-dis.c: New file 750 * Makefile.am: Entries for xc16x 751 * Makefile.in: Regenerate 752 * cofigure.in: Add xc16x target information. 753 * configure: Regenerate. 754 * disassemble.c: Add xc16x target information. 755 7562006-02-11 H.J. Lu <hongjiu.lu@intel.com> 757 758 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register 759 moves. 760 7612006-02-11 H.J. Lu <hongjiu.lu@intel.com> 762 763 * i386-dis.c ('Z'): Add a new macro. 764 (dis386_twobyte): Use "movZ" for control register moves. 765 7662006-02-10 Nick Clifton <nickc@redhat.com> 767 768 * iq2000-asm.c: Regenerate. 769 7702006-02-07 Nathan Sidwell <nathan@codesourcery.com> 771 772 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features. 773 7742006-01-26 David Ung <davidu@mips.com> 775 776 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx, 777 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d, 778 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d, 779 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d, 780 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s. 781 7822006-01-18 Arnold Metselaar <arnoldm@sourceware.org> 783 784 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d, 785 ld_d_r, pref_xd_cb): Use signed char to hold data to be 786 disassembled. 787 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes 788 buffer overflows when disassembling instructions like 789 ld (ix+123),0x23 790 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed 791 operand, if the offset is negative. 792 7932006-01-17 Arnold Metselaar <arnoldm@sourceware.org> 794 795 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use 796 unsigned char to hold data to be disassembled. 797 7982006-01-17 Andreas Schwab <schwab@suse.de> 799 800 PR binutils/1486 801 * disassemble.c (disassemble_init_for_target): Set 802 disassembler_needs_relocs for bfd_arch_arm. 803 8042006-01-16 Paul Brook <paul@codesourcery.com> 805 806 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss, 807 f?add?, and f?sub? instructions. 808 8092006-01-16 Nick Clifton <nickc@redhat.com> 810 811 * po/zh_CN.po: New Chinese (simplified) translation. 812 * configure.in (ALL_LINGUAS): Add "zh_CH". 813 * configure: Regenerate. 814 8152006-01-05 Paul Brook <paul@codesourcery.com> 816 817 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry. 818 8192006-01-06 DJ Delorie <dj@redhat.com> 820 821 * m32c-desc.c: Regenerate. 822 * m32c-opc.c: Regenerate. 823 * m32c-opc.h: Regenerate. 824 8252006-01-03 DJ Delorie <dj@redhat.com> 826 827 * cgen-ibld.in (extract_normal): Avoid memory range errors. 828 * m32c-ibld.c: Regenerated. 829 830For older changes see ChangeLog-2005 831 832Local Variables: 833mode: change-log 834left-margin: 8 835fill-column: 74 836version-control: never 837End: 838