184740Sache/* opcode/i386.h -- Intel 80386 opcode macros
284740Sache   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
384740Sache   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
484740Sache   Free Software Foundation, Inc.
584740Sache
684740Sache   This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
784740Sache
884740Sache   This program is free software; you can redistribute it and/or modify
984740Sache   it under the terms of the GNU General Public License as published by
1084740Sache   the Free Software Foundation; either version 2 of the License, or
1184740Sache   (at your option) any later version.
1284740Sache
1384740Sache   This program is distributed in the hope that it will be useful,
1484740Sache   but WITHOUT ANY WARRANTY; without even the implied warranty of
1584740Sache   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1684740Sache   GNU General Public License for more details.
1784740Sache
1884740Sache   You should have received a copy of the GNU General Public License
1984740Sache   along with this program; if not, write to the Free Software
2084740Sache   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
2184740Sache
2284740Sache/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
2384740Sache   ix86 Unix assemblers, generate floating point instructions with
2484740Sache   reversed source and destination registers in certain cases.
2584740Sache   Unfortunately, gcc and possibly many other programs use this
2684740Sache   reversed syntax, so we're stuck with it.
2784740Sache
2884740Sache   eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
2984740Sache   `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
3084740Sache   the expected st(3) = st(3) - st
3184740Sache
3284740Sache   This happens with all the non-commutative arithmetic floating point
3384740Sache   operations with two register operands, where the source register is
3484740Sache   %st, and destination register is %st(i).
3584740Sache
3684740Sache   The affected opcode map is dceX, dcfX, deeX, defX.  */
3786170Sobrien
3886170Sobrien#ifndef SYSV386_COMPAT
3984740Sache/* Set non-zero for broken, compatible instructions.  Set to zero for
4084740Sache   non-broken opcodes at your peril.  gcc generates SystemV/386
4184740Sache   compatible instructions.  */
4284740Sache#define SYSV386_COMPAT 1
4384740Sache#endif
4484740Sache#ifndef OLDGCC_COMPAT
4584740Sache/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
4684740Sache   generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
4784740Sache   reversed.  */
4892889Sobrien#define OLDGCC_COMPAT SYSV386_COMPAT
4984740Sache#endif
5092889Sobrien
5192889Sobrien#define MOV_AX_DISP32 0xa0
5284740Sache#define POP_SEG_SHORT 0x07
5384740Sache#define JUMP_PC_RELATIVE 0xeb
5484740Sache#define INT_OPCODE  0xcd
5584740Sache#define INT3_OPCODE 0xcc
5684740Sache/* The opcode for the fwait instruction, which disassembler treats as a
5784740Sache   prefix when it can.  */
5884740Sache#define FWAIT_OPCODE 0x9b
5984740Sache#define ADDR_PREFIX_OPCODE 0x67
6084740Sache#define DATA_PREFIX_OPCODE 0x66
6184740Sache#define LOCK_PREFIX_OPCODE 0xf0
6284740Sache#define CS_PREFIX_OPCODE 0x2e
6384740Sache#define DS_PREFIX_OPCODE 0x3e
6484740Sache#define ES_PREFIX_OPCODE 0x26
6584740Sache#define FS_PREFIX_OPCODE 0x64
66#define GS_PREFIX_OPCODE 0x65
67#define SS_PREFIX_OPCODE 0x36
68#define REPNE_PREFIX_OPCODE 0xf2
69#define REPE_PREFIX_OPCODE  0xf3
70
71#define TWO_BYTE_OPCODE_ESCAPE 0x0f
72#define NOP_OPCODE (char) 0x90
73
74/* register numbers */
75#define EBP_REG_NUM 5
76#define ESP_REG_NUM 4
77
78/* modrm_byte.regmem for twobyte escape */
79#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
80/* index_base_byte.index for no index register addressing */
81#define NO_INDEX_REGISTER ESP_REG_NUM
82/* index_base_byte.base for no base register addressing */
83#define NO_BASE_REGISTER EBP_REG_NUM
84#define NO_BASE_REGISTER_16 6
85
86/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
87#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
88#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
89
90/* x86-64 extension prefix.  */
91#define REX_OPCODE	0x40
92
93/* Indicates 64 bit operand size.  */
94#define REX_W	8
95/* High extension to reg field of modrm byte.  */
96#define REX_R	4
97/* High extension to SIB index field.  */
98#define REX_X	2
99/* High extension to base field of modrm or SIB, or reg field of opcode.  */
100#define REX_B	1
101
102/* max operands per insn */
103#define MAX_OPERANDS 4
104
105/* max immediates per insn (lcall, ljmp, insertq, extrq) */
106#define MAX_IMMEDIATE_OPERANDS 2
107
108/* max memory refs per insn (string ops) */
109#define MAX_MEMORY_OPERANDS 2
110
111/* max size of insn mnemonics.  */
112#define MAX_MNEM_SIZE 16
113
114/* max size of register name in insn mnemonics.  */
115#define MAX_REG_NAME_SIZE 8
116