itbl-ops.c revision 89857
1228753Smm/* itbl-ops.c 2228753Smm Copyright 1997, 1999, 2000, 2001 Free Software Foundation, Inc. 3228753Smm 4228753Smm This file is part of GAS, the GNU Assembler. 5228753Smm 6228753Smm GAS is free software; you can redistribute it and/or modify 7228753Smm it under the terms of the GNU General Public License as published by 8228753Smm the Free Software Foundation; either version 2, or (at your option) 9228753Smm any later version. 10228753Smm 11228753Smm GAS is distributed in the hope that it will be useful, 12228753Smm but WITHOUT ANY WARRANTY; without even the implied warranty of 13228753Smm MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14228753Smm GNU General Public License for more details. 15228753Smm 16228753Smm You should have received a copy of the GNU General Public License 17228753Smm along with GAS; see the file COPYING. If not, write to the Free 18228753Smm Software Foundation, 59 Temple Place - Suite 330, Boston, MA 19228753Smm 02111-1307, USA. */ 20228753Smm 21228753Smm/*======================================================================*/ 22228753Smm/* 23228753Smm * Herein lies the support for dynamic specification of processor 24228753Smm * instructions and registers. Mnemonics, values, and formats for each 25228763Smm * instruction and register are specified in an ascii file consisting of 26228753Smm * table entries. The grammar for the table is defined in the document 27228753Smm * "Processor instruction table specification". 28358090Smm * 29358090Smm * Instructions use the gnu assembler syntax, with the addition of 30358090Smm * allowing mnemonics for register. 31228753Smm * Eg. "func $2,reg3,0x100,symbol ; comment" 32228753Smm * func - opcode name 33228753Smm * $n - register n 34228753Smm * reg3 - mnemonic for processor's register defined in table 35232153Smm * 0xddd..d - immediate value 36232153Smm * symbol - address of label or external symbol 37232153Smm * 38232153Smm * First, itbl_parse reads in the table of register and instruction 39228753Smm * names and formats, and builds a list of entries for each 40228753Smm * processor/type combination. lex and yacc are used to parse 41228753Smm * the entries in the table and call functions defined here to 42228753Smm * add each entry to our list. 43228753Smm * 44228753Smm * Then, when assembling or disassembling, these functions are called to 45228753Smm * 1) get information on a processor's registers and 46228753Smm * 2) assemble/disassemble an instruction. 47228753Smm * To assemble(disassemble) an instruction, the function 48228753Smm * itbl_assemble(itbl_disassemble) is called to search the list of 49228753Smm * instruction entries, and if a match is found, uses the format 50228753Smm * described in the instruction entry structure to complete the action. 51228753Smm * 52228753Smm * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2" 53238856Smm * and we want to define function "pig" which takes two operands. 54228753Smm * 55228753Smm * Given the table entries: 56228753Smm * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0" 57228753Smm * "p3 dreg d2 0x2" 58228753Smm * and that the instruction encoding for coprocessor pz has encoding: 59228753Smm * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25) 60228753Smm * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum) 61232153Smm * 62228753Smm * a structure to describe the instruction might look something like: 63228753Smm * struct itbl_entry = { 64228753Smm * e_processor processor = e_p3 65228773Smm * e_type type = e_insn 66228753Smm * char *name = "pig" 67228753Smm * uint value = 0x1 68228753Smm * uint flags = 0 69228753Smm * struct itbl_range range = 24-21 70228753Smm * struct itbl_field *field = { 71228753Smm * e_type type = e_dreg 72232153Smm * struct itbl_range range = 20-16 73232153Smm * struct itbl_field *next = { 74232153Smm * e_type type = e_immed 75232153Smm * struct itbl_range range = 15-0 76232153Smm * struct itbl_field *next = 0 77232153Smm * }; 78232153Smm * }; 79232153Smm * struct itbl_entry *next = 0 80232153Smm * }; 81232153Smm * 82232153Smm * And the assembler instructions: 83232153Smm * "pig d2,0x100" 84232153Smm * "pig $2,0x100" 85228753Smm * 86228753Smm * would both assemble to the hex value: 87232153Smm * "0x4e220100" 88232153Smm * 89228753Smm */ 90228753Smm 91228753Smm#include <stdio.h> 92228753Smm#include <stdlib.h> 93228753Smm#include <string.h> 94228753Smm#include "itbl-ops.h" 95228753Smm#include "itbl-parse.h" 96228753Smm 97228753Smm/* #define DEBUG */ 98228753Smm 99228753Smm#ifdef DEBUG 100228753Smm#include <assert.h> 101228753Smm#define ASSERT(x) assert(x) 102228753Smm#define DBG(x) printf x 103228753Smm#else 104228753Smm#define ASSERT(x) 105228753Smm#define DBG(x) 106228753Smm#endif 107228753Smm 108228753Smm#ifndef min 109228753Smm#define min(a,b) (a<b?a:b) 110228753Smm#endif 111228753Smm 112228753Smmint itbl_have_entries = 0; 113228753Smm 114228753Smm/*======================================================================*/ 115228753Smm/* structures for keeping itbl format entries */ 116228753Smm 117232153Smmstruct itbl_range { 118232153Smm int sbit; /* mask starting bit position */ 119232153Smm int ebit; /* mask ending bit position */ 120232153Smm}; 121232153Smm 122302001Smmstruct itbl_field { 123302001Smm e_type type; /* dreg/creg/greg/immed/symb */ 124302001Smm struct itbl_range range; /* field's bitfield range within instruction */ 125302001Smm unsigned long flags; /* field flags */ 126302001Smm struct itbl_field *next; /* next field in list */ 127302001Smm}; 128302001Smm 129302001Smm/* These structures define the instructions and registers for a processor. 130302001Smm * If the type is an instruction, the structure defines the format of an 131302001Smm * instruction where the fields are the list of operands. 132302001Smm * The flags field below uses the same values as those defined in the 133302001Smm * gnu assembler and are machine specific. */ 134302001Smmstruct itbl_entry { 135302001Smm e_processor processor; /* processor number */ 136302001Smm e_type type; /* dreg/creg/greg/insn */ 137302001Smm char *name; /* mnemionic name for insn/register */ 138302001Smm unsigned long value; /* opcode/instruction mask/register number */ 139228753Smm unsigned long flags; /* effects of the instruction */ 140228753Smm struct itbl_range range; /* bit range within instruction for value */ 141232153Smm struct itbl_field *fields; /* list of operand definitions (if any) */ 142232153Smm struct itbl_entry *next; /* next entry */ 143228753Smm}; 144232153Smm 145232153Smm/* local data and structures */ 146232153Smm 147232153Smmstatic int itbl_num_opcodes = 0; 148232153Smm/* Array of entries for each processor and entry type */ 149232153Smmstatic struct itbl_entry *entries[e_nprocs][e_ntypes] = { 150232153Smm {0, 0, 0, 0, 0, 0}, 151228753Smm {0, 0, 0, 0, 0, 0}, 152228753Smm {0, 0, 0, 0, 0, 0}, 153228753Smm {0, 0, 0, 0, 0, 0} 154248616Smm}; 155232153Smm 156358090Smm/* local prototypes */ 157358090Smmstatic unsigned long build_opcode PARAMS ((struct itbl_entry *e)); 158358090Smmstatic e_type get_type PARAMS ((int yytype)); 159358090Smmstatic e_processor get_processor PARAMS ((int yyproc)); 160358090Smmstatic struct itbl_entry **get_entries PARAMS ((e_processor processor, 161228753Smm e_type type)); 162232153Smmstatic struct itbl_entry *find_entry_byname PARAMS ((e_processor processor, 163232153Smm e_type type, char *name)); 164302001Smmstatic struct itbl_entry *find_entry_byval PARAMS ((e_processor processor, 165302001Smm e_type type, unsigned long val, struct itbl_range *r)); 166228753Smmstatic struct itbl_entry *alloc_entry PARAMS ((e_processor processor, 167228753Smm e_type type, char *name, unsigned long value)); 168228753Smmstatic unsigned long apply_range PARAMS ((unsigned long value, 169228753Smm struct itbl_range r)); 170228753Smmstatic unsigned long extract_range PARAMS ((unsigned long value, 171228753Smm struct itbl_range r)); 172228753Smmstatic struct itbl_field *alloc_field PARAMS ((e_type type, int sbit, 173228753Smm int ebit, unsigned long flags)); 174228753Smm 175228753Smm/*======================================================================*/ 176228753Smm/* Interfaces to the parser */ 177 178/* Open the table and use lex and yacc to parse the entries. 179 * Return 1 for failure; 0 for success. */ 180 181int 182itbl_parse (char *insntbl) 183{ 184 extern FILE *yyin; 185 extern int yyparse (void); 186 187 yyin = fopen (insntbl, FOPEN_RT); 188 if (yyin == 0) 189 { 190 printf ("Can't open processor instruction specification file \"%s\"\n", 191 insntbl); 192 return 1; 193 } 194 195 while (yyparse ()) 196 ; 197 198 fclose (yyin); 199 itbl_have_entries = 1; 200 return 0; 201} 202 203/* Add a register entry */ 204 205struct itbl_entry * 206itbl_add_reg (int yyprocessor, int yytype, char *regname, 207 int regnum) 208{ 209#if 0 210#include "as.h" 211#include "symbols.h" 212 /* Since register names don't have a prefix, we put them in the symbol table so 213 they can't be used as symbols. This also simplifies argument parsing as 214 we can let gas parse registers for us. The recorded register number is 215 regnum. */ 216 /* Use symbol_create here instead of symbol_new so we don't try to 217 output registers into the object file's symbol table. */ 218 symbol_table_insert (symbol_create (regname, reg_section, 219 regnum, &zero_address_frag)); 220#endif 221 return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname, 222 (unsigned long) regnum); 223} 224 225/* Add an instruction entry */ 226 227struct itbl_entry * 228itbl_add_insn (int yyprocessor, char *name, unsigned long value, 229 int sbit, int ebit, unsigned long flags) 230{ 231 struct itbl_entry *e; 232 e = alloc_entry (get_processor (yyprocessor), e_insn, name, value); 233 if (e) 234 { 235 e->range.sbit = sbit; 236 e->range.ebit = ebit; 237 e->flags = flags; 238 itbl_num_opcodes++; 239 } 240 return e; 241} 242 243/* Add an operand to an instruction entry */ 244 245struct itbl_field * 246itbl_add_operand (struct itbl_entry *e, int yytype, int sbit, 247 int ebit, unsigned long flags) 248{ 249 struct itbl_field *f, **last_f; 250 if (!e) 251 return 0; 252 /* Add to end of fields' list. */ 253 f = alloc_field (get_type (yytype), sbit, ebit, flags); 254 if (f) 255 { 256 last_f = &e->fields; 257 while (*last_f) 258 last_f = &(*last_f)->next; 259 *last_f = f; 260 f->next = 0; 261 } 262 return f; 263} 264 265/*======================================================================*/ 266/* Interfaces for assembler and disassembler */ 267 268#ifndef STAND_ALONE 269#include "as.h" 270#include "symbols.h" 271static void append_insns_as_macros (void); 272 273/* Initialize for gas. */ 274 275void 276itbl_init (void) 277{ 278 struct itbl_entry *e, **es; 279 e_processor procn; 280 e_type type; 281 282 if (!itbl_have_entries) 283 return; 284 285 /* Since register names don't have a prefix, put them in the symbol table so 286 they can't be used as symbols. This simplifies argument parsing as 287 we can let gas parse registers for us. */ 288 /* Use symbol_create instead of symbol_new so we don't try to 289 output registers into the object file's symbol table. */ 290 291 for (type = e_regtype0; type < e_nregtypes; type++) 292 for (procn = e_p0; procn < e_nprocs; procn++) 293 { 294 es = get_entries (procn, type); 295 for (e = *es; e; e = e->next) 296 { 297 symbol_table_insert (symbol_create (e->name, reg_section, 298 e->value, &zero_address_frag)); 299 } 300 } 301 append_insns_as_macros (); 302} 303 304/* Append insns to opcodes table and increase number of opcodes 305 * Structure of opcodes table: 306 * struct itbl_opcode 307 * { 308 * const char *name; 309 * const char *args; - string describing the arguments. 310 * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO 311 * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO 312 * unsigned long pinfo; - insn flags, or INSN_MACRO 313 * }; 314 * examples: 315 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, 316 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, 317 */ 318 319static char *form_args (struct itbl_entry *e); 320static void 321append_insns_as_macros (void) 322{ 323 struct ITBL_OPCODE_STRUCT *new_opcodes, *o; 324 struct itbl_entry *e, **es; 325 int n, id, size, new_size, new_num_opcodes; 326 327 if (!itbl_have_entries) 328 return; 329 330 if (!itbl_num_opcodes) /* no new instructions to add! */ 331 { 332 return; 333 } 334 DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES)); 335 336 new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes; 337 ASSERT (new_num_opcodes >= itbl_num_opcodes); 338 339 size = sizeof (struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES; 340 ASSERT (size >= 0); 341 DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0]))); 342 343 new_size = sizeof (struct ITBL_OPCODE_STRUCT) * new_num_opcodes; 344 ASSERT (new_size > size); 345 346 /* FIXME since ITBL_OPCODES culd be a static table, 347 we can't realloc or delete the old memory. */ 348 new_opcodes = (struct ITBL_OPCODE_STRUCT *) malloc (new_size); 349 if (!new_opcodes) 350 { 351 printf (_("Unable to allocate memory for new instructions\n")); 352 return; 353 } 354 if (size) /* copy prexisting opcodes table */ 355 memcpy (new_opcodes, ITBL_OPCODES, size); 356 357 /* FIXME! some NUMOPCODES are calculated expressions. 358 These need to be changed before itbls can be supported. */ 359 360 id = ITBL_NUM_MACROS; /* begin the next macro id after the last */ 361 o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */ 362 for (n = e_p0; n < e_nprocs; n++) 363 { 364 es = get_entries (n, e_insn); 365 for (e = *es; e; e = e->next) 366 { 367 /* name, args, mask, match, pinfo 368 * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, 369 * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, 370 * Construct args from itbl_fields. 371 */ 372 o->name = e->name; 373 o->args = strdup (form_args (e)); 374 o->mask = apply_range (e->value, e->range); 375 /* FIXME how to catch durring assembly? */ 376 /* mask to identify this insn */ 377 o->match = apply_range (e->value, e->range); 378 o->pinfo = 0; 379 380#ifdef USE_MACROS 381 o->mask = id++; /* FIXME how to catch durring assembly? */ 382 o->match = 0; /* for macros, the insn_isa number */ 383 o->pinfo = INSN_MACRO; 384#endif 385 386 /* Don't add instructions which caused an error */ 387 if (o->args) 388 o++; 389 else 390 new_num_opcodes--; 391 } 392 } 393 ITBL_OPCODES = new_opcodes; 394 ITBL_NUM_OPCODES = new_num_opcodes; 395 396 /* FIXME 397 At this point, we can free the entries, as they should have 398 been added to the assembler's tables. 399 Don't free name though, since name is being used by the new 400 opcodes table. 401 402 Eventually, we should also free the new opcodes table itself 403 on exit. 404 */ 405} 406 407static char * 408form_args (struct itbl_entry *e) 409{ 410 static char s[31]; 411 char c = 0, *p = s; 412 struct itbl_field *f; 413 414 ASSERT (e); 415 for (f = e->fields; f; f = f->next) 416 { 417 switch (f->type) 418 { 419 case e_dreg: 420 c = 'd'; 421 break; 422 case e_creg: 423 c = 't'; 424 break; 425 case e_greg: 426 c = 's'; 427 break; 428 case e_immed: 429 c = 'i'; 430 break; 431 case e_addr: 432 c = 'a'; 433 break; 434 default: 435 c = 0; /* ignore; unknown field type */ 436 } 437 if (c) 438 { 439 if (p != s) 440 *p++ = ','; 441 *p++ = c; 442 } 443 } 444 *p = 0; 445 return s; 446} 447#endif /* !STAND_ALONE */ 448 449/* Get processor's register name from val */ 450 451int 452itbl_get_reg_val (char *name, unsigned long *pval) 453{ 454 e_type t; 455 e_processor p; 456 457 for (p = e_p0; p < e_nprocs; p++) 458 { 459 for (t = e_regtype0; t < e_nregtypes; t++) 460 { 461 if (itbl_get_val (p, t, name, pval)) 462 return 1; 463 } 464 } 465 return 0; 466} 467 468char * 469itbl_get_name (e_processor processor, e_type type, unsigned long val) 470{ 471 struct itbl_entry *r; 472 /* type depends on instruction passed */ 473 r = find_entry_byval (processor, type, val, 0); 474 if (r) 475 return r->name; 476 else 477 return 0; /* error; invalid operand */ 478} 479 480/* Get processor's register value from name */ 481 482int 483itbl_get_val (e_processor processor, e_type type, char *name, 484 unsigned long *pval) 485{ 486 struct itbl_entry *r; 487 /* type depends on instruction passed */ 488 r = find_entry_byname (processor, type, name); 489 if (r == NULL) 490 return 0; 491 *pval = r->value; 492 return 1; 493} 494 495/* Assemble instruction "name" with operands "s". 496 * name - name of instruction 497 * s - operands 498 * returns - long word for assembled instruction */ 499 500unsigned long 501itbl_assemble (char *name, char *s) 502{ 503 unsigned long opcode; 504 struct itbl_entry *e = NULL; 505 struct itbl_field *f; 506 char *n; 507 int processor; 508 509 if (!name || !*name) 510 return 0; /* error! must have an opcode name/expr */ 511 512 /* find entry in list of instructions for all processors */ 513 for (processor = 0; processor < e_nprocs; processor++) 514 { 515 e = find_entry_byname (processor, e_insn, name); 516 if (e) 517 break; 518 } 519 if (!e) 520 return 0; /* opcode not in table; invalid instruction */ 521 opcode = build_opcode (e); 522 523 /* parse opcode's args (if any) */ 524 for (f = e->fields; f; f = f->next) /* for each arg, ... */ 525 { 526 struct itbl_entry *r; 527 unsigned long value; 528 if (!s || !*s) 529 return 0; /* error - not enough operands */ 530 n = itbl_get_field (&s); 531 /* n should be in form $n or 0xhhh (are symbol names valid?? */ 532 switch (f->type) 533 { 534 case e_dreg: 535 case e_creg: 536 case e_greg: 537 /* Accept either a string name 538 * or '$' followed by the register number */ 539 if (*n == '$') 540 { 541 n++; 542 value = strtol (n, 0, 10); 543 /* FIXME! could have "0l"... then what?? */ 544 if (value == 0 && *n != '0') 545 return 0; /* error; invalid operand */ 546 } 547 else 548 { 549 r = find_entry_byname (e->processor, f->type, n); 550 if (r) 551 value = r->value; 552 else 553 return 0; /* error; invalid operand */ 554 } 555 break; 556 case e_addr: 557 /* use assembler's symbol table to find symbol */ 558 /* FIXME!! Do we need this? 559 if so, what about relocs?? 560 my_getExpression (&imm_expr, s); 561 return 0; /-* error; invalid operand *-/ 562 break; 563 */ 564 /* If not a symbol, fall thru to IMMED */ 565 case e_immed: 566 if (*n == '0' && *(n + 1) == 'x') /* hex begins 0x... */ 567 { 568 n += 2; 569 value = strtol (n, 0, 16); 570 /* FIXME! could have "0xl"... then what?? */ 571 } 572 else 573 { 574 value = strtol (n, 0, 10); 575 /* FIXME! could have "0l"... then what?? */ 576 if (value == 0 && *n != '0') 577 return 0; /* error; invalid operand */ 578 } 579 break; 580 default: 581 return 0; /* error; invalid field spec */ 582 } 583 opcode |= apply_range (value, f->range); 584 } 585 if (s && *s) 586 return 0; /* error - too many operands */ 587 return opcode; /* done! */ 588} 589 590/* Disassemble instruction "insn". 591 * insn - instruction 592 * s - buffer to hold disassembled instruction 593 * returns - 1 if succeeded; 0 if failed 594 */ 595 596int 597itbl_disassemble (char *s, unsigned long insn) 598{ 599 e_processor processor; 600 struct itbl_entry *e; 601 struct itbl_field *f; 602 603 if (!ITBL_IS_INSN (insn)) 604 return 0; /* error */ 605 processor = get_processor (ITBL_DECODE_PNUM (insn)); 606 607 /* find entry in list */ 608 e = find_entry_byval (processor, e_insn, insn, 0); 609 if (!e) 610 return 0; /* opcode not in table; invalid instruction */ 611 strcpy (s, e->name); 612 613 /* Parse insn's args (if any). */ 614 for (f = e->fields; f; f = f->next) /* for each arg, ... */ 615 { 616 struct itbl_entry *r; 617 unsigned long value; 618 619 if (f == e->fields) /* First operand is preceeded by tab. */ 620 strcat (s, "\t"); 621 else /* ','s separate following operands. */ 622 strcat (s, ","); 623 value = extract_range (insn, f->range); 624 /* n should be in form $n or 0xhhh (are symbol names valid?? */ 625 switch (f->type) 626 { 627 case e_dreg: 628 case e_creg: 629 case e_greg: 630 /* Accept either a string name 631 or '$' followed by the register number. */ 632 r = find_entry_byval (e->processor, f->type, value, &f->range); 633 if (r) 634 strcat (s, r->name); 635 else 636 sprintf (s, "%s$%lu", s, value); 637 break; 638 case e_addr: 639 /* Use assembler's symbol table to find symbol. */ 640 /* FIXME!! Do we need this? If so, what about relocs?? */ 641 /* If not a symbol, fall through to IMMED. */ 642 case e_immed: 643 sprintf (s, "%s0x%lx", s, value); 644 break; 645 default: 646 return 0; /* error; invalid field spec */ 647 } 648 } 649 return 1; /* Done! */ 650} 651 652/*======================================================================*/ 653/* 654 * Local functions for manipulating private structures containing 655 * the names and format for the new instructions and registers 656 * for each processor. 657 */ 658 659/* Calculate instruction's opcode and function values from entry */ 660 661static unsigned long 662build_opcode (struct itbl_entry *e) 663{ 664 unsigned long opcode; 665 666 opcode = apply_range (e->value, e->range); 667 opcode |= ITBL_ENCODE_PNUM (e->processor); 668 return opcode; 669} 670 671/* Calculate absolute value given the relative value and bit position range 672 * within the instruction. 673 * The range is inclusive where 0 is least significant bit. 674 * A range of { 24, 20 } will have a mask of 675 * bit 3 2 1 676 * pos: 1098 7654 3210 9876 5432 1098 7654 3210 677 * bin: 0000 0001 1111 0000 0000 0000 0000 0000 678 * hex: 0 1 f 0 0 0 0 0 679 * mask: 0x01f00000. 680 */ 681 682static unsigned long 683apply_range (unsigned long rval, struct itbl_range r) 684{ 685 unsigned long mask; 686 unsigned long aval; 687 int len = MAX_BITPOS - r.sbit; 688 689 ASSERT (r.sbit >= r.ebit); 690 ASSERT (MAX_BITPOS >= r.sbit); 691 ASSERT (r.ebit >= 0); 692 693 /* create mask by truncating 1s by shifting */ 694 mask = 0xffffffff << len; 695 mask = mask >> len; 696 mask = mask >> r.ebit; 697 mask = mask << r.ebit; 698 699 aval = (rval << r.ebit) & mask; 700 return aval; 701} 702 703/* Calculate relative value given the absolute value and bit position range 704 * within the instruction. */ 705 706static unsigned long 707extract_range (unsigned long aval, struct itbl_range r) 708{ 709 unsigned long mask; 710 unsigned long rval; 711 int len = MAX_BITPOS - r.sbit; 712 713 /* create mask by truncating 1s by shifting */ 714 mask = 0xffffffff << len; 715 mask = mask >> len; 716 mask = mask >> r.ebit; 717 mask = mask << r.ebit; 718 719 rval = (aval & mask) >> r.ebit; 720 return rval; 721} 722 723/* Extract processor's assembly instruction field name from s; 724 * forms are "n args" "n,args" or "n" */ 725/* Return next argument from string pointer "s" and advance s. 726 * delimiters are " ,()" */ 727 728char * 729itbl_get_field (char **S) 730{ 731 static char n[128]; 732 char *s; 733 int len; 734 735 s = *S; 736 if (!s || !*s) 737 return 0; 738 /* FIXME: This is a weird set of delimiters. */ 739 len = strcspn (s, " \t,()"); 740 ASSERT (128 > len + 1); 741 strncpy (n, s, len); 742 n[len] = 0; 743 if (s[len] == '\0') 744 s = 0; /* no more args */ 745 else 746 s += len + 1; /* advance to next arg */ 747 748 *S = s; 749 return n; 750} 751 752/* Search entries for a given processor and type 753 * to find one matching the name "n". 754 * Return a pointer to the entry */ 755 756static struct itbl_entry * 757find_entry_byname (e_processor processor, 758 e_type type, char *n) 759{ 760 struct itbl_entry *e, **es; 761 762 es = get_entries (processor, type); 763 for (e = *es; e; e = e->next) /* for each entry, ... */ 764 { 765 if (!strcmp (e->name, n)) 766 return e; 767 } 768 return 0; 769} 770 771/* Search entries for a given processor and type 772 * to find one matching the value "val" for the range "r". 773 * Return a pointer to the entry. 774 * This function is used for disassembling fields of an instruction. 775 */ 776 777static struct itbl_entry * 778find_entry_byval (e_processor processor, e_type type, 779 unsigned long val, struct itbl_range *r) 780{ 781 struct itbl_entry *e, **es; 782 unsigned long eval; 783 784 es = get_entries (processor, type); 785 for (e = *es; e; e = e->next) /* for each entry, ... */ 786 { 787 if (processor != e->processor) 788 continue; 789 /* For insns, we might not know the range of the opcode, 790 * so a range of 0 will allow this routine to match against 791 * the range of the entry to be compared with. 792 * This could cause ambiguities. 793 * For operands, we get an extracted value and a range. 794 */ 795 /* if range is 0, mask val against the range of the compared entry. */ 796 if (r == 0) /* if no range passed, must be whole 32-bits 797 * so create 32-bit value from entry's range */ 798 { 799 eval = apply_range (e->value, e->range); 800 val &= apply_range (0xffffffff, e->range); 801 } 802 else if ((r->sbit == e->range.sbit && r->ebit == e->range.ebit) 803 || (e->range.sbit == 0 && e->range.ebit == 0)) 804 { 805 eval = apply_range (e->value, *r); 806 val = apply_range (val, *r); 807 } 808 else 809 continue; 810 if (val == eval) 811 return e; 812 } 813 return 0; 814} 815 816/* Return a pointer to the list of entries for a given processor and type. */ 817 818static struct itbl_entry ** 819get_entries (e_processor processor, e_type type) 820{ 821 return &entries[processor][type]; 822} 823 824/* Return an integral value for the processor passed from yyparse. */ 825 826static e_processor 827get_processor (int yyproc) 828{ 829 /* translate from yacc's processor to enum */ 830 if (yyproc >= e_p0 && yyproc < e_nprocs) 831 return (e_processor) yyproc; 832 return e_invproc; /* error; invalid processor */ 833} 834 835/* Return an integral value for the entry type passed from yyparse. */ 836 837static e_type 838get_type (int yytype) 839{ 840 switch (yytype) 841 { 842 /* translate from yacc's type to enum */ 843 case INSN: 844 return e_insn; 845 case DREG: 846 return e_dreg; 847 case CREG: 848 return e_creg; 849 case GREG: 850 return e_greg; 851 case ADDR: 852 return e_addr; 853 case IMMED: 854 return e_immed; 855 default: 856 return e_invtype; /* error; invalid type */ 857 } 858} 859 860/* Allocate and initialize an entry */ 861 862static struct itbl_entry * 863alloc_entry (e_processor processor, e_type type, 864 char *name, unsigned long value) 865{ 866 struct itbl_entry *e, **es; 867 if (!name) 868 return 0; 869 e = (struct itbl_entry *) malloc (sizeof (struct itbl_entry)); 870 if (e) 871 { 872 memset (e, 0, sizeof (struct itbl_entry)); 873 e->name = (char *) malloc (sizeof (strlen (name)) + 1); 874 if (e->name) 875 strcpy (e->name, name); 876 e->processor = processor; 877 e->type = type; 878 e->value = value; 879 es = get_entries (e->processor, e->type); 880 e->next = *es; 881 *es = e; 882 } 883 return e; 884} 885 886/* Allocate and initialize an entry's field */ 887 888static struct itbl_field * 889alloc_field (e_type type, int sbit, int ebit, 890 unsigned long flags) 891{ 892 struct itbl_field *f; 893 f = (struct itbl_field *) malloc (sizeof (struct itbl_field)); 894 if (f) 895 { 896 memset (f, 0, sizeof (struct itbl_field)); 897 f->type = type; 898 f->range.sbit = sbit; 899 f->range.ebit = ebit; 900 f->flags = flags; 901 } 902 return f; 903} 904