1218822Sdim@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004, 2005 294536Sobrien@c Free Software Foundation, Inc. 333965Sjdp@c This is part of the GAS manual. 433965Sjdp@c For copying conditions, see the file as.texinfo. 533965Sjdp@page 633965Sjdp@node SH-Dependent 7130561Sobrien@chapter Renesas / SuperH SH Dependent Features 833965Sjdp 933965Sjdp@cindex SH support 1033965Sjdp@menu 1133965Sjdp* SH Options:: Options 1233965Sjdp* SH Syntax:: Syntax 1333965Sjdp* SH Floating Point:: Floating Point 1433965Sjdp* SH Directives:: SH Machine Directives 1533965Sjdp* SH Opcodes:: Opcodes 1633965Sjdp@end menu 1733965Sjdp 1833965Sjdp@node SH Options 1933965Sjdp@section Options 2033965Sjdp 2194536Sobrien@cindex SH options 2294536Sobrien@cindex options, SH 23130561Sobrien@code{@value{AS}} has following command-line options for the Renesas 24130561Sobrien(formerly Hitachi) / SuperH SH family. 2533965Sjdp 2694536Sobrien@table @code 27218822Sdim@kindex --little 28218822Sdim@kindex --big 29218822Sdim@kindex --relax 30218822Sdim@kindex --small 31218822Sdim@kindex --dsp 32218822Sdim@kindex --renesas 33218822Sdim@kindex --allow-reg-prefix 3494536Sobrien 35218822Sdim@item --little 3694536SobrienGenerate little endian code. 3794536Sobrien 38218822Sdim@item --big 3994536SobrienGenerate big endian code. 4094536Sobrien 41218822Sdim@item --relax 4294536SobrienAlter jump instructions for long displacements. 4394536Sobrien 44218822Sdim@item --small 4594536SobrienAlign sections to 4 byte boundaries, not 16. 4694536Sobrien 47218822Sdim@item --dsp 4894536SobrienEnable sh-dsp insns, and disable sh3e / sh4 insns. 4994536Sobrien 50218822Sdim@item --renesas 51130561SobrienDisable optimization with section symbol for compatibility with 52130561SobrienRenesas assembler. 53130561Sobrien 54218822Sdim@item --allow-reg-prefix 55218822SdimAllow '$' as a register name prefix. 56218822Sdim 57218822Sdim@item --isa=sh4 | sh4a 58130561SobrienSpecify the sh4 or sh4a instruction set. 59218822Sdim@item --isa=dsp 60130561SobrienEnable sh-dsp insns, and disable sh3e / sh4 insns. 61218822Sdim@item --isa=fp 62130561SobrienEnable sh2e, sh3e, sh4, and sh4a insn sets. 63218822Sdim@item --isa=all 64130561SobrienEnable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 65130561Sobrien 6694536Sobrien@end table 6794536Sobrien 6833965Sjdp@node SH Syntax 6933965Sjdp@section Syntax 7033965Sjdp 7133965Sjdp@menu 7233965Sjdp* SH-Chars:: Special Characters 7333965Sjdp* SH-Regs:: Register Names 7433965Sjdp* SH-Addressing:: Addressing Modes 7533965Sjdp@end menu 7633965Sjdp 7733965Sjdp@node SH-Chars 7833965Sjdp@subsection Special Characters 7933965Sjdp 8033965Sjdp@cindex line comment character, SH 8133965Sjdp@cindex SH line comment character 8233965Sjdp@samp{!} is the line comment character. 8333965Sjdp 8433965Sjdp@cindex line separator, SH 8533965Sjdp@cindex statement separator, SH 8633965Sjdp@cindex SH line separator 8733965SjdpYou can use @samp{;} instead of a newline to separate statements. 8833965Sjdp 8933965Sjdp@cindex symbol names, @samp{$} in 9033965Sjdp@cindex @code{$} in symbol names 9133965SjdpSince @samp{$} has no special meaning, you may use it in symbol names. 9233965Sjdp 9333965Sjdp@node SH-Regs 9433965Sjdp@subsection Register Names 9533965Sjdp 9633965Sjdp@cindex SH registers 9733965Sjdp@cindex registers, SH 9833965SjdpYou can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2}, 9933965Sjdp@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8}, 10033965Sjdp@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14}, 10133965Sjdpand @samp{r15} to refer to the SH registers. 10233965Sjdp 10333965SjdpThe SH also has these control registers: 10433965Sjdp 10533965Sjdp@table @code 10633965Sjdp@item pr 10733965Sjdpprocedure register (holds return address) 10833965Sjdp 10933965Sjdp@item pc 11033965Sjdpprogram counter 11133965Sjdp 11233965Sjdp@item mach 11333965Sjdp@itemx macl 11433965Sjdphigh and low multiply accumulator registers 11533965Sjdp 11633965Sjdp@item sr 11733965Sjdpstatus register 11833965Sjdp 11933965Sjdp@item gbr 12033965Sjdpglobal base register 12133965Sjdp 12233965Sjdp@item vbr 12333965Sjdpvector base register (for interrupt vectors) 12433965Sjdp@end table 12533965Sjdp 12633965Sjdp@node SH-Addressing 12733965Sjdp@subsection Addressing Modes 12833965Sjdp 12933965Sjdp@cindex addressing modes, SH 13033965Sjdp@cindex SH addressing modes 13133965Sjdp@code{@value{AS}} understands the following addressing modes for the SH. 13233965Sjdp@code{R@var{n}} in the following refers to any of the numbered 13333965Sjdpregisters, but @emph{not} the control registers. 13433965Sjdp 13533965Sjdp@table @code 13633965Sjdp@item R@var{n} 13733965SjdpRegister direct 13833965Sjdp 13933965Sjdp@item @@R@var{n} 14033965SjdpRegister indirect 14133965Sjdp 14233965Sjdp@item @@-R@var{n} 14333965SjdpRegister indirect with pre-decrement 14433965Sjdp 14533965Sjdp@item @@R@var{n}+ 14633965SjdpRegister indirect with post-increment 14733965Sjdp 14833965Sjdp@item @@(@var{disp}, R@var{n}) 14933965SjdpRegister indirect with displacement 15033965Sjdp 15133965Sjdp@item @@(R0, R@var{n}) 15233965SjdpRegister indexed 15333965Sjdp 15433965Sjdp@item @@(@var{disp}, GBR) 15533965Sjdp@code{GBR} offset 15633965Sjdp 15733965Sjdp@item @@(R0, GBR) 15833965SjdpGBR indexed 15933965Sjdp 16033965Sjdp@item @var{addr} 16133965Sjdp@itemx @@(@var{disp}, PC) 16233965SjdpPC relative address (for branch or for addressing memory). The 16333965Sjdp@code{@value{AS}} implementation allows you to use the simpler form 16433965Sjdp@var{addr} anywhere a PC relative address is called for; the alternate 16533965Sjdpform is supported for compatibility with other assemblers. 16633965Sjdp 16733965Sjdp@item #@var{imm} 16833965SjdpImmediate data 16933965Sjdp@end table 17033965Sjdp 17133965Sjdp@node SH Floating Point 17233965Sjdp@section Floating Point 17333965Sjdp 17433965Sjdp@cindex floating point, SH (@sc{ieee}) 17533965Sjdp@cindex SH floating point (@sc{ieee}) 176130561SobrienSH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 177130561SobrienSH groups can use @code{.float} directive to generate @sc{ieee} 178130561Sobrienfloating-point numbers. 17933965Sjdp 180130561SobrienSH2E and SH3E support single-precision floating point calculations as 181130561Sobrienwell as entirely PCAPI compatible emulation of double-precision 182130561Sobrienfloating point calculations. SH2E and SH3E instructions are a subset of 183130561Sobrienthe floating point calculations conforming to the IEEE754 standard. 184130561Sobrien 185130561SobrienIn addition to single-precision and double-precision floating-point 186130561Sobrienoperation capability, the on-chip FPU of SH4 has a 128-bit graphic 187130561Sobrienengine that enables 32-bit floating-point data to be processed 128 188130561Sobrienbits at a time. It also supports 4 * 4 array operations and inner 189130561Sobrienproduct operations. Also, a superscalar architecture is employed that 190130561Sobrienenables simultaneous execution of two instructions (including FPU 191130561Sobrieninstructions), providing performance of up to twice that of 192130561Sobrienconventional architectures at the same frequency. 193130561Sobrien 19433965Sjdp@node SH Directives 19533965Sjdp@section SH Machine Directives 19633965Sjdp 19738889Sjdp@cindex SH machine directives 19838889Sjdp@cindex machine directives, SH 19938889Sjdp@cindex @code{uaword} directive, SH 20038889Sjdp@cindex @code{ualong} directive, SH 20133965Sjdp 20238889Sjdp@table @code 20338889Sjdp@item uaword 20438889Sjdp@itemx ualong 20538889Sjdp@code{@value{AS}} will issue a warning when a misaligned @code{.word} or 20638889Sjdp@code{.long} directive is used. You may use @code{.uaword} or 20738889Sjdp@code{.ualong} to indicate that the value is intentionally misaligned. 20838889Sjdp@end table 20938889Sjdp 21033965Sjdp@node SH Opcodes 21133965Sjdp@section Opcodes 21233965Sjdp 21333965Sjdp@cindex SH opcode summary 21433965Sjdp@cindex opcode summary, SH 21533965Sjdp@cindex mnemonics, SH 21633965Sjdp@cindex instruction summary, SH 21733965SjdpFor detailed information on the SH machine instruction set, see 218130561Sobrien@cite{SH-Microcomputer User's Manual} (Renesas) or 219130561Sobrien@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and 220130561Sobrien@cite{SuperH (SH) 64-Bit RISC Series} (SuperH). 22133965Sjdp 22233965Sjdp@code{@value{AS}} implements all the standard SH opcodes. No additional 22333965Sjdppseudo-instructions are needed on this family. Note, however, that 22433965Sjdpbecause @code{@value{AS}} supports a simpler form of PC-relative 22533965Sjdpaddressing, you may simply write (for example) 22633965Sjdp 22733965Sjdp@example 22833965Sjdpmov.l bar,r0 22933965Sjdp@end example 23033965Sjdp 23133965Sjdp@noindent 23233965Sjdpwhere other assemblers might require an explicit displacement to 23333965Sjdp@code{bar} from the program counter: 23433965Sjdp 23533965Sjdp@example 23633965Sjdpmov.l @@(@var{disp}, PC) 23733965Sjdp@end example 23833965Sjdp 23933965Sjdp@ifset SMALL 24033965Sjdp@c this table, due to the multi-col faking and hardcoded order, looks silly 24133965Sjdp@c except in smallbook. See comments below "@set SMALL" near top of this file. 24233965Sjdp 24333965SjdpHere is a summary of SH opcodes: 24433965Sjdp 24533965Sjdp@page 24633965Sjdp@smallexample 24733965Sjdp@i{Legend:} 24833965SjdpRn @r{a numbered register} 24933965SjdpRm @r{another numbered register} 25033965Sjdp#imm @r{immediate data} 25133965Sjdpdisp @r{displacement} 25233965Sjdpdisp8 @r{8-bit displacement} 25333965Sjdpdisp12 @r{12-bit displacement} 25433965Sjdp 25533965Sjdpadd #imm,Rn lds.l @@Rn+,PR 25633965Sjdpadd Rm,Rn mac.w @@Rm+,@@Rn+ 25733965Sjdpaddc Rm,Rn mov #imm,Rn 25833965Sjdpaddv Rm,Rn mov Rm,Rn 25933965Sjdpand #imm,R0 mov.b Rm,@@(R0,Rn) 26033965Sjdpand Rm,Rn mov.b Rm,@@-Rn 26133965Sjdpand.b #imm,@@(R0,GBR) mov.b Rm,@@Rn 26233965Sjdpbf disp8 mov.b @@(disp,Rm),R0 26333965Sjdpbra disp12 mov.b @@(disp,GBR),R0 26433965Sjdpbsr disp12 mov.b @@(R0,Rm),Rn 26533965Sjdpbt disp8 mov.b @@Rm+,Rn 26633965Sjdpclrmac mov.b @@Rm,Rn 26733965Sjdpclrt mov.b R0,@@(disp,Rm) 26833965Sjdpcmp/eq #imm,R0 mov.b R0,@@(disp,GBR) 26933965Sjdpcmp/eq Rm,Rn mov.l Rm,@@(disp,Rn) 27033965Sjdpcmp/ge Rm,Rn mov.l Rm,@@(R0,Rn) 27133965Sjdpcmp/gt Rm,Rn mov.l Rm,@@-Rn 27233965Sjdpcmp/hi Rm,Rn mov.l Rm,@@Rn 27333965Sjdpcmp/hs Rm,Rn mov.l @@(disp,Rn),Rm 27433965Sjdpcmp/pl Rn mov.l @@(disp,GBR),R0 27533965Sjdpcmp/pz Rn mov.l @@(disp,PC),Rn 27633965Sjdpcmp/str Rm,Rn mov.l @@(R0,Rm),Rn 27733965Sjdpdiv0s Rm,Rn mov.l @@Rm+,Rn 27833965Sjdpdiv0u mov.l @@Rm,Rn 27933965Sjdpdiv1 Rm,Rn mov.l R0,@@(disp,GBR) 28033965Sjdpexts.b Rm,Rn mov.w Rm,@@(R0,Rn) 28133965Sjdpexts.w Rm,Rn mov.w Rm,@@-Rn 28233965Sjdpextu.b Rm,Rn mov.w Rm,@@Rn 28333965Sjdpextu.w Rm,Rn mov.w @@(disp,Rm),R0 28433965Sjdpjmp @@Rn mov.w @@(disp,GBR),R0 28533965Sjdpjsr @@Rn mov.w @@(disp,PC),Rn 28633965Sjdpldc Rn,GBR mov.w @@(R0,Rm),Rn 28733965Sjdpldc Rn,SR mov.w @@Rm+,Rn 28833965Sjdpldc Rn,VBR mov.w @@Rm,Rn 28933965Sjdpldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm) 29033965Sjdpldc.l @@Rn+,SR mov.w R0,@@(disp,GBR) 29133965Sjdpldc.l @@Rn+,VBR mova @@(disp,PC),R0 29233965Sjdplds Rn,MACH movt Rn 29333965Sjdplds Rn,MACL muls Rm,Rn 29433965Sjdplds Rn,PR mulu Rm,Rn 29533965Sjdplds.l @@Rn+,MACH neg Rm,Rn 29633965Sjdplds.l @@Rn+,MACL negc Rm,Rn 29733965Sjdp@page 29833965Sjdpnop stc VBR,Rn 29933965Sjdpnot Rm,Rn stc.l GBR,@@-Rn 30033965Sjdpor #imm,R0 stc.l SR,@@-Rn 30133965Sjdpor Rm,Rn stc.l VBR,@@-Rn 30233965Sjdpor.b #imm,@@(R0,GBR) sts MACH,Rn 30333965Sjdprotcl Rn sts MACL,Rn 30433965Sjdprotcr Rn sts PR,Rn 30533965Sjdprotl Rn sts.l MACH,@@-Rn 30633965Sjdprotr Rn sts.l MACL,@@-Rn 30733965Sjdprte sts.l PR,@@-Rn 30833965Sjdprts sub Rm,Rn 30933965Sjdpsett subc Rm,Rn 31033965Sjdpshal Rn subv Rm,Rn 31133965Sjdpshar Rn swap.b Rm,Rn 31233965Sjdpshll Rn swap.w Rm,Rn 31333965Sjdpshll16 Rn tas.b @@Rn 31433965Sjdpshll2 Rn trapa #imm 31533965Sjdpshll8 Rn tst #imm,R0 31633965Sjdpshlr Rn tst Rm,Rn 31733965Sjdpshlr16 Rn tst.b #imm,@@(R0,GBR) 31833965Sjdpshlr2 Rn xor #imm,R0 31933965Sjdpshlr8 Rn xor Rm,Rn 32033965Sjdpsleep xor.b #imm,@@(R0,GBR) 32133965Sjdpstc GBR,Rn xtrct Rm,Rn 32233965Sjdpstc SR,Rn 32333965Sjdp@end smallexample 32433965Sjdp@end ifset 32533965Sjdp 326130561Sobrien@ifset Renesas-all 32733965Sjdp@ifclear GENERIC 32833965Sjdp@raisesections 32933965Sjdp@end ifclear 33033965Sjdp@end ifset 33133965Sjdp 332