1179404Sobrien@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2179404Sobrien@c 2002, 2003, 2004 3179404Sobrien@c Free Software Foundation, Inc. 4179404Sobrien@c This is part of the GAS manual. 5179404Sobrien@c For copying conditions, see the file as.texinfo. 6179404Sobrien@ifset GENERIC 7179404Sobrien@page 8179404Sobrien@node MIPS-Dependent 9179404Sobrien@chapter MIPS Dependent Features 10179404Sobrien@end ifset 11179404Sobrien@ifclear GENERIC 12179404Sobrien@node Machine Dependencies 13179404Sobrien@chapter MIPS Dependent Features 14179404Sobrien@end ifclear 15179404Sobrien 16179404Sobrien@cindex MIPS processor 17179404Sobrien@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several 18179404Sobriendifferent @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, 19179404Sobrienand MIPS64. For information about the @sc{mips} instruction set, see 20179404Sobrien@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). 21179404SobrienFor an overview of @sc{mips} assembly conventions, see ``Appendix D: 22179404SobrienAssembly Language Programming'' in the same work. 23179404Sobrien 24179404Sobrien@menu 25179404Sobrien* MIPS Opts:: Assembler options 26179404Sobrien* MIPS Object:: ECOFF object code 27179404Sobrien* MIPS Stabs:: Directives for debugging information 28179404Sobrien* MIPS ISA:: Directives to override the ISA level 29218822Sdim* MIPS symbol sizes:: Directives to override the size of symbols 30179404Sobrien* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 31179404Sobrien* MIPS insn:: Directive to mark data as an instruction 32179404Sobrien* MIPS option stack:: Directives to save and restore options 33179404Sobrien* MIPS ASE instruction generation overrides:: Directives to control 34179404Sobrien generation of MIPS ASE instructions 35179404Sobrien@end menu 36179404Sobrien 37179404Sobrien@node MIPS Opts 38179404Sobrien@section Assembler options 39179404Sobrien 40179404SobrienThe @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these 41179404Sobrienspecial options: 42179404Sobrien 43179404Sobrien@table @code 44179404Sobrien@cindex @code{-G} option (MIPS) 45179404Sobrien@item -G @var{num} 46179404SobrienThis option sets the largest size of an object that can be referenced 47179404Sobrienimplicitly with the @code{gp} register. It is only accepted for targets 48179404Sobrienthat use @sc{ecoff} format. The default value is 8. 49179404Sobrien 50179404Sobrien@cindex @code{-EB} option (MIPS) 51179404Sobrien@cindex @code{-EL} option (MIPS) 52179404Sobrien@cindex MIPS big-endian output 53179404Sobrien@cindex MIPS little-endian output 54179404Sobrien@cindex big-endian output, MIPS 55179404Sobrien@cindex little-endian output, MIPS 56179404Sobrien@item -EB 57179404Sobrien@itemx -EL 58179404SobrienAny @sc{mips} configuration of @code{@value{AS}} can select big-endian or 59179404Sobrienlittle-endian output at run time (unlike the other @sc{gnu} development 60179404Sobrientools, which must be configured for one or the other). Use @samp{-EB} 61179404Sobriento select big-endian output, and @samp{-EL} for little-endian. 62179404Sobrien 63218822Sdim@item -KPIC 64218822Sdim@cindex PIC selection, MIPS 65218822Sdim@cindex @option{-KPIC} option, MIPS 66218822SdimGenerate SVR4-style PIC. This option tells the assembler to generate 67218822SdimSVR4-style position-independent macro expansions. It also tells the 68218822Sdimassembler to mark the output file as PIC. 69218822Sdim 70218822Sdim@item -mvxworks-pic 71218822Sdim@cindex @option{-mvxworks-pic} option, MIPS 72218822SdimGenerate VxWorks PIC. This option tells the assembler to generate 73218822SdimVxWorks-style position-independent macro expansions. 74218822Sdim 75179404Sobrien@cindex MIPS architecture options 76179404Sobrien@item -mips1 77179404Sobrien@itemx -mips2 78179404Sobrien@itemx -mips3 79179404Sobrien@itemx -mips4 80179404Sobrien@itemx -mips5 81179404Sobrien@itemx -mips32 82179404Sobrien@itemx -mips32r2 83179404Sobrien@itemx -mips64 84179404Sobrien@itemx -mips64r2 85179404SobrienGenerate code for a particular MIPS Instruction Set Architecture level. 86179404Sobrien@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, 87179404Sobrien@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the 88179404Sobrien@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and 89179404Sobrien@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, 90179404Sobrien@samp{-mips64}, and @samp{-mips64r2} 91179404Sobriencorrespond to generic 92179404Sobrien@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, 93179404Sobrienand @sc{MIPS64 Release 2} 94179404SobrienISA processors, respectively. You can also switch 95179404Sobrieninstruction sets during the assembly; see @ref{MIPS ISA, Directives to 96179404Sobrienoverride the ISA level}. 97179404Sobrien 98179404Sobrien@item -mgp32 99179404Sobrien@itemx -mfp32 100179404SobrienSome macros have different expansions for 32-bit and 64-bit registers. 101179404SobrienThe register sizes are normally inferred from the ISA and ABI, but these 102179404Sobrienflags force a certain group of registers to be treated as 32 bits wide at 103179404Sobrienall times. @samp{-mgp32} controls the size of general-purpose registers 104179404Sobrienand @samp{-mfp32} controls the size of floating-point registers. 105179404Sobrien 106218822SdimThe @code{.set gp=32} and @code{.set fp=32} directives allow the size 107218822Sdimof registers to be changed for parts of an object. The default value is 108218822Sdimrestored by @code{.set gp=default} and @code{.set fp=default}. 109218822Sdim 110179404SobrienOn some MIPS variants there is a 32-bit mode flag; when this flag is 111179404Sobrienset, 64-bit instructions generate a trap. Also, some 32-bit OSes only 112179404Sobriensave the 32-bit registers on a context switch, so it is essential never 113179404Sobriento use the 64-bit registers. 114179404Sobrien 115179404Sobrien@item -mgp64 116218822Sdim@itemx -mfp64 117218822SdimAssume that 64-bit registers are available. This is provided in the 118218822Sdiminterests of symmetry with @samp{-mgp32} and @samp{-mfp32}. 119179404Sobrien 120218822SdimThe @code{.set gp=64} and @code{.set fp=64} directives allow the size 121218822Sdimof registers to be changed for parts of an object. The default value is 122218822Sdimrestored by @code{.set gp=default} and @code{.set fp=default}. 123218822Sdim 124179404Sobrien@item -mips16 125179404Sobrien@itemx -no-mips16 126179404SobrienGenerate code for the MIPS 16 processor. This is equivalent to putting 127218822Sdim@code{.set mips16} at the start of the assembly file. @samp{-no-mips16} 128179404Sobrienturns off this option. 129179404Sobrien 130218822Sdim@item -msmartmips 131218822Sdim@itemx -mno-smartmips 132218822SdimEnables the SmartMIPS extensions to the MIPS32 instruction set, which 133218822Sdimprovides a number of new instructions which target smartcard and 134218822Sdimcryptographic applications. This is equivalent to putting 135218822Sdim@code{.set smartmips} at the start of the assembly file. 136218822Sdim@samp{-mno-smartmips} turns off this option. 137218822Sdim 138179404Sobrien@item -mips3d 139179404Sobrien@itemx -no-mips3d 140179404SobrienGenerate code for the MIPS-3D Application Specific Extension. 141179404SobrienThis tells the assembler to accept MIPS-3D instructions. 142179404Sobrien@samp{-no-mips3d} turns off this option. 143179404Sobrien 144179404Sobrien@item -mdmx 145179404Sobrien@itemx -no-mdmx 146179404SobrienGenerate code for the MDMX Application Specific Extension. 147179404SobrienThis tells the assembler to accept MDMX instructions. 148179404Sobrien@samp{-no-mdmx} turns off this option. 149179404Sobrien 150218822Sdim@item -mdsp 151218822Sdim@itemx -mno-dsp 152218822SdimGenerate code for the DSP Release 1 Application Specific Extension. 153218822SdimThis tells the assembler to accept DSP Release 1 instructions. 154218822Sdim@samp{-mno-dsp} turns off this option. 155218822Sdim 156218822Sdim@item -mdspr2 157218822Sdim@itemx -mno-dspr2 158218822SdimGenerate code for the DSP Release 2 Application Specific Extension. 159218822SdimThis option implies -mdsp. 160218822SdimThis tells the assembler to accept DSP Release 2 instructions. 161218822Sdim@samp{-mno-dspr2} turns off this option. 162218822Sdim 163218822Sdim@item -mmt 164218822Sdim@itemx -mno-mt 165218822SdimGenerate code for the MT Application Specific Extension. 166218822SdimThis tells the assembler to accept MT instructions. 167218822Sdim@samp{-mno-mt} turns off this option. 168218822Sdim 169179404Sobrien@item -mfix7000 170179404Sobrien@itemx -mno-fix7000 171179404SobrienCause nops to be inserted if the read of the destination register 172179404Sobrienof an mfhi or mflo instruction occurs in the following two instructions. 173179404Sobrien 174179404Sobrien@item -mfix-vr4120 175179404Sobrien@itemx -no-mfix-vr4120 176179404SobrienInsert nops to work around certain VR4120 errata. This option is 177179404Sobrienintended to be used on GCC-generated code: it is not designed to catch 178179404Sobrienall problems in hand-written assembler code. 179179404Sobrien 180218822Sdim@item -mfix-vr4130 181218822Sdim@itemx -no-mfix-vr4130 182218822SdimInsert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. 183218822Sdim 184179404Sobrien@item -m4010 185179404Sobrien@itemx -no-m4010 186179404SobrienGenerate code for the LSI @sc{r4010} chip. This tells the assembler to 187179404Sobrienaccept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, 188179404Sobrienetc.), and to not schedule @samp{nop} instructions around accesses to 189179404Sobrienthe @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 190179404Sobrienoption. 191179404Sobrien 192179404Sobrien@item -m4650 193179404Sobrien@itemx -no-m4650 194179404SobrienGenerate code for the MIPS @sc{r4650} chip. This tells the assembler to accept 195179404Sobrienthe @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 196179404Sobrieninstructions around accesses to the @samp{HI} and @samp{LO} registers. 197179404Sobrien@samp{-no-m4650} turns off this option. 198179404Sobrien 199276647Sbapt@item -m3900 200179404Sobrien@itemx -no-m3900 201179404Sobrien@itemx -m4100 202179404Sobrien@itemx -no-m4100 203179404SobrienFor each option @samp{-m@var{nnnn}}, generate code for the MIPS 204179404Sobrien@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions 205179404Sobrienspecific to that chip, and to schedule for that chip's hazards. 206179404Sobrien 207179404Sobrien@item -march=@var{cpu} 208179404SobrienGenerate code for a particular MIPS cpu. It is exactly equivalent to 209179404Sobrien@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 210179404Sobrienunderstood. Valid @var{cpu} value are: 211179404Sobrien 212179404Sobrien@quotation 213179404Sobrien2000, 214179404Sobrien3000, 215179404Sobrien3900, 216179404Sobrien4000, 217179404Sobrien4010, 218179404Sobrien4100, 219179404Sobrien4111, 220179404Sobrienvr4120, 221179404Sobrienvr4130, 222179404Sobrienvr4181, 223179404Sobrien4300, 224179404Sobrien4400, 225179404Sobrien4600, 226179404Sobrien4650, 227179404Sobrien5000, 228179404Sobrienrm5200, 229179404Sobrienrm5230, 230179404Sobrienrm5231, 231179404Sobrienrm5261, 232179404Sobrienrm5721, 233179404Sobrienvr5400, 234179404Sobrienvr5500, 235179404Sobrien6000, 236179404Sobrienrm7000, 237179404Sobrien8000, 238179404Sobrienrm9000, 239179404Sobrien10000, 240179404Sobrien12000, 241218822Sdim4kc, 242218822Sdim4km, 243218822Sdim4kp, 244218822Sdim4ksc, 245218822Sdim4kec, 246218822Sdim4kem, 247218822Sdim4kep, 248218822Sdim4ksd, 249218822Sdimm4k, 250218822Sdimm4kp, 251218822Sdim24kc, 252218822Sdim24kf, 253218822Sdim24kx, 254218822Sdim24kec, 255218822Sdim24kef, 256218822Sdim24kex, 257218822Sdim34kc, 258218822Sdim34kf, 259218822Sdim34kx, 260218822Sdim74kc, 261218822Sdim74kf, 262218822Sdim74kx, 263218822Sdim5kc, 264218822Sdim5kf, 265218822Sdim20kc, 266218822Sdim25kf, 267218822Sdimsb1, 268218822Sdimsb1a 269179404Sobrien@end quotation 270179404Sobrien 271179404Sobrien@item -mtune=@var{cpu} 272179404SobrienSchedule and tune for a particular MIPS cpu. Valid @var{cpu} values are 273179404Sobrienidentical to @samp{-march=@var{cpu}}. 274179404Sobrien 275179404Sobrien@item -mabi=@var{abi} 276179404SobrienRecord which ABI the source code uses. The recognized arguments 277179404Sobrienare: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. 278179404Sobrien 279218822Sdim@item -msym32 280218822Sdim@itemx -mno-sym32 281218822Sdim@cindex -msym32 282218822Sdim@cindex -mno-sym32 283218822SdimEquivalent to adding @code{.set sym32} or @code{.set nosym32} to 284218822Sdimthe beginning of the assembler input. @xref{MIPS symbol sizes}. 285218822Sdim 286179404Sobrien@cindex @code{-nocpp} ignored (MIPS) 287179404Sobrien@item -nocpp 288179404SobrienThis option is ignored. It is accepted for command-line compatibility with 289179404Sobrienother assemblers, which use it to turn off C style preprocessing. With 290179404Sobrien@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 291179404Sobrien@sc{gnu} assembler itself never runs the C preprocessor. 292179404Sobrien 293179404Sobrien@item --construct-floats 294179404Sobrien@itemx --no-construct-floats 295179404Sobrien@cindex --construct-floats 296179404Sobrien@cindex --no-construct-floats 297179404SobrienThe @code{--no-construct-floats} option disables the construction of 298179404Sobriendouble width floating point constants by loading the two halves of the 299179404Sobrienvalue into the two single width floating point registers that make up 300179404Sobrienthe double width register. This feature is useful if the processor 301179404Sobriensupport the FR bit in its status register, and this bit is known (by 302179404Sobrienthe programmer) to be set. This bit prevents the aliasing of the double 303179404Sobrienwidth register by the single width registers. 304179404Sobrien 305179404SobrienBy default @code{--construct-floats} is selected, allowing construction 306179404Sobrienof these floating point constants. 307179404Sobrien 308179404Sobrien@item --trap 309179404Sobrien@itemx --no-break 310179404Sobrien@c FIXME! (1) reflect these options (next item too) in option summaries; 311179404Sobrien@c (2) stop teasing, say _which_ instructions expanded _how_. 312179404Sobrien@code{@value{AS}} automatically macro expands certain division and 313179404Sobrienmultiplication instructions to check for overflow and division by zero. This 314179404Sobrienoption causes @code{@value{AS}} to generate code to take a trap exception 315179404Sobrienrather than a break exception when an error is detected. The trap instructions 316179404Sobrienare only supported at Instruction Set Architecture level 2 and higher. 317179404Sobrien 318179404Sobrien@item --break 319179404Sobrien@itemx --no-trap 320179404SobrienGenerate code to take a break exception rather than a trap exception when an 321179404Sobrienerror is detected. This is the default. 322179404Sobrien 323179404Sobrien@item -mpdr 324179404Sobrien@itemx -mno-pdr 325179404SobrienControl generation of @code{.pdr} sections. Off by default on IRIX, on 326179404Sobrienelsewhere. 327218822Sdim 328218822Sdim@item -mshared 329218822Sdim@itemx -mno-shared 330218822SdimWhen generating code using the Unix calling conventions (selected by 331218822Sdim@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code 332218822Sdimwhich can go into a shared library. The @samp{-mno-shared} option 333218822Sdimtells gas to generate code which uses the calling convention, but can 334218822Sdimnot go into a shared library. The resulting code is slightly more 335218822Sdimefficient. This option only affects the handling of the 336218822Sdim@samp{.cpload} and @samp{.cpsetup} pseudo-ops. 337179404Sobrien@end table 338179404Sobrien 339179404Sobrien@node MIPS Object 340179404Sobrien@section MIPS ECOFF object code 341179404Sobrien 342179404Sobrien@cindex ECOFF sections 343179404Sobrien@cindex MIPS ECOFF sections 344179404SobrienAssembling for a @sc{mips} @sc{ecoff} target supports some additional sections 345179404Sobrienbesides the usual @code{.text}, @code{.data} and @code{.bss}. The 346179404Sobrienadditional sections are @code{.rdata}, used for read-only data, 347179404Sobrien@code{.sdata}, used for small data, and @code{.sbss}, used for small 348179404Sobriencommon objects. 349179404Sobrien 350179404Sobrien@cindex small objects, MIPS ECOFF 351179404Sobrien@cindex @code{gp} register, MIPS 352179404SobrienWhen assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) 353179404Sobrienregister to form the address of a ``small object''. Any object in the 354179404Sobrien@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. 355179404SobrienFor external objects, or for objects in the @code{.bss} section, you can use 356179404Sobrienthe @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via 357179404Sobrien@code{$gp}; the default value is 8, meaning that a reference to any object 358179404Sobrieneight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to 359179404Sobrien@code{@value{AS}} prevents it from using the @code{$gp} register on the basis 360179404Sobrienof object size (but the assembler uses @code{$gp} for objects in @code{.sdata} 361179404Sobrienor @code{sbss} in any case). The size of an object in the @code{.bss} section 362179404Sobrienis set by the @code{.comm} or @code{.lcomm} directive that defines it. The 363179404Sobriensize of an external object may be set with the @code{.extern} directive. For 364179404Sobrienexample, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes 365179404Sobrienin length, whie leaving @code{sym} otherwise undefined. 366179404Sobrien 367179404SobrienUsing small @sc{ecoff} objects requires linker support, and assumes that the 368179404Sobrien@code{$gp} register is correctly initialized (normally done automatically by 369179404Sobrienthe startup code). @sc{mips} @sc{ecoff} assembly code must not modify the 370179404Sobrien@code{$gp} register. 371179404Sobrien 372179404Sobrien@node MIPS Stabs 373179404Sobrien@section Directives for debugging information 374179404Sobrien 375179404Sobrien@cindex MIPS debugging directives 376179404Sobrien@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for 377179404Sobriengenerating debugging information which are not support by traditional @sc{mips} 378179404Sobrienassemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, 379179404Sobrien@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, 380179404Sobrien@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information 381179404Sobriengenerated by the three @code{.stab} directives can only be read by @sc{gdb}, 382179404Sobriennot by traditional @sc{mips} debuggers (this enhancement is required to fully 383179404Sobriensupport C++ debugging). These directives are primarily used by compilers, not 384179404Sobrienassembly language programmers! 385179404Sobrien 386218822Sdim@node MIPS symbol sizes 387218822Sdim@section Directives to override the size of symbols 388218822Sdim 389218822Sdim@cindex @code{.set sym32} 390218822Sdim@cindex @code{.set nosym32} 391218822SdimThe n64 ABI allows symbols to have any 64-bit value. Although this 392218822Sdimprovides a great deal of flexibility, it means that some macros have 393218822Sdimmuch longer expansions than their 32-bit counterparts. For example, 394218822Sdimthe non-PIC expansion of @samp{dla $4,sym} is usually: 395218822Sdim 396218822Sdim@smallexample 397218822Sdimlui $4,%highest(sym) 398218822Sdimlui $1,%hi(sym) 399218822Sdimdaddiu $4,$4,%higher(sym) 400218822Sdimdaddiu $1,$1,%lo(sym) 401218822Sdimdsll32 $4,$4,0 402218822Sdimdaddu $4,$4,$1 403218822Sdim@end smallexample 404218822Sdim 405218822Sdimwhereas the 32-bit expansion is simply: 406218822Sdim 407218822Sdim@smallexample 408218822Sdimlui $4,%hi(sym) 409218822Sdimdaddiu $4,$4,%lo(sym) 410218822Sdim@end smallexample 411218822Sdim 412218822Sdimn64 code is sometimes constructed in such a way that all symbolic 413218822Sdimconstants are known to have 32-bit values, and in such cases, it's 414218822Sdimpreferable to use the 32-bit expansion instead of the 64-bit 415218822Sdimexpansion. 416218822Sdim 417218822SdimYou can use the @code{.set sym32} directive to tell the assembler 418218822Sdimthat, from this point on, all expressions of the form 419218822Sdim@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} 420218822Sdimhave 32-bit values. For example: 421218822Sdim 422218822Sdim@smallexample 423218822Sdim.set sym32 424218822Sdimdla $4,sym 425218822Sdimlw $4,sym+16 426218822Sdimsw $4,sym+0x8000($4) 427218822Sdim@end smallexample 428218822Sdim 429218822Sdimwill cause the assembler to treat @samp{sym}, @code{sym+16} and 430218822Sdim@code{sym+0x8000} as 32-bit values. The handling of non-symbolic 431218822Sdimaddresses is not affected. 432218822Sdim 433218822SdimThe directive @code{.set nosym32} ends a @code{.set sym32} block and 434218822Sdimreverts to the normal behavior. It is also possible to change the 435218822Sdimsymbol size using the command-line options @option{-msym32} and 436218822Sdim@option{-mno-sym32}. 437218822Sdim 438218822SdimThese options and directives are always accepted, but at present, 439218822Sdimthey have no effect for anything other than n64. 440218822Sdim 441179404Sobrien@node MIPS ISA 442179404Sobrien@section Directives to override the ISA level 443179404Sobrien 444179404Sobrien@cindex MIPS ISA override 445179404Sobrien@kindex @code{.set mips@var{n}} 446179404Sobrien@sc{gnu} @code{@value{AS}} supports an additional directive to change 447179404Sobrienthe @sc{mips} Instruction Set Architecture level on the fly: @code{.set 448179404Sobrienmips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 449179404Sobrienor 64r2. 450179404SobrienThe values other than 0 make the assembler accept instructions 451179404Sobrienfor the corresponding @sc{isa} level, from that point on in the 452179404Sobrienassembly. @code{.set mips@var{n}} affects not only which instructions 453179404Sobrienare permitted, but also how certain macros are expanded. @code{.set 454179404Sobrienmips0} restores the @sc{isa} level to its original level: either the 455179404Sobrienlevel you selected with command line options, or the default for your 456218822Sdimconfiguration. You can use this feature to permit specific @sc{mips3} 457179404Sobrieninstructions while assembling in 32 bit mode. Use this directive with 458179404Sobriencare! 459179404Sobrien 460218822Sdim@cindex MIPS CPU override 461218822Sdim@kindex @code{.set arch=@var{cpu}} 462218822SdimThe @code{.set arch=@var{cpu}} directive provides even finer control. 463218822SdimIt changes the effective CPU target and allows the assembler to use 464218822Sdiminstructions specific to a particular CPU. All CPUs supported by the 465218822Sdim@samp{-march} command line option are also selectable by this directive. 466218822SdimThe original value is restored by @code{.set arch=default}. 467218822Sdim 468218822SdimThe directive @code{.set mips16} puts the assembler into MIPS 16 mode, 469179404Sobrienin which it will assemble instructions for the MIPS 16 processor. Use 470218822Sdim@code{.set nomips16} to return to normal 32 bit mode. 471179404Sobrien 472179404SobrienTraditional @sc{mips} assemblers do not support this directive. 473179404Sobrien 474179404Sobrien@node MIPS autoextend 475179404Sobrien@section Directives for extending MIPS 16 bit instructions 476179404Sobrien 477179404Sobrien@kindex @code{.set autoextend} 478179404Sobrien@kindex @code{.set noautoextend} 479179404SobrienBy default, MIPS 16 instructions are automatically extended to 32 bits 480218822Sdimwhen necessary. The directive @code{.set noautoextend} will turn this 481218822Sdimoff. When @code{.set noautoextend} is in effect, any 32 bit instruction 482218822Sdimmust be explicitly extended with the @code{.e} modifier (e.g., 483218822Sdim@code{li.e $4,1000}). The directive @code{.set autoextend} may be used 484179404Sobriento once again automatically extend instructions when necessary. 485179404Sobrien 486179404SobrienThis directive is only meaningful when in MIPS 16 mode. Traditional 487179404Sobrien@sc{mips} assemblers do not support this directive. 488179404Sobrien 489179404Sobrien@node MIPS insn 490179404Sobrien@section Directive to mark data as an instruction 491179404Sobrien 492179404Sobrien@kindex @code{.insn} 493179404SobrienThe @code{.insn} directive tells @code{@value{AS}} that the following 494179404Sobriendata is actually instructions. This makes a difference in MIPS 16 mode: 495179404Sobrienwhen loading the address of a label which precedes instructions, 496179404Sobrien@code{@value{AS}} automatically adds 1 to the value, so that jumping to 497179404Sobrienthe loaded address will do the right thing. 498179404Sobrien 499179404Sobrien@node MIPS option stack 500179404Sobrien@section Directives to save and restore options 501179404Sobrien 502179404Sobrien@cindex MIPS option stack 503179404Sobrien@kindex @code{.set push} 504179404Sobrien@kindex @code{.set pop} 505179404SobrienThe directives @code{.set push} and @code{.set pop} may be used to save 506179404Sobrienand restore the current settings for all the options which are 507179404Sobriencontrolled by @code{.set}. The @code{.set push} directive saves the 508179404Sobriencurrent settings on a stack. The @code{.set pop} directive pops the 509179404Sobrienstack and restores the settings. 510179404Sobrien 511179404SobrienThese directives can be useful inside an macro which must change an 512179404Sobrienoption such as the ISA level or instruction reordering but does not want 513179404Sobriento change the state of the code which invoked the macro. 514179404Sobrien 515179404SobrienTraditional @sc{mips} assemblers do not support these directives. 516179404Sobrien 517179404Sobrien@node MIPS ASE instruction generation overrides 518179404Sobrien@section Directives to control generation of MIPS ASE instructions 519179404Sobrien 520179404Sobrien@cindex MIPS MIPS-3D instruction generation override 521179404Sobrien@kindex @code{.set mips3d} 522179404Sobrien@kindex @code{.set nomips3d} 523179404SobrienThe directive @code{.set mips3d} makes the assembler accept instructions 524179404Sobrienfrom the MIPS-3D Application Specific Extension from that point on 525179404Sobrienin the assembly. The @code{.set nomips3d} directive prevents MIPS-3D 526179404Sobrieninstructions from being accepted. 527179404Sobrien 528218822Sdim@cindex SmartMIPS instruction generation override 529218822Sdim@kindex @code{.set smartmips} 530218822Sdim@kindex @code{.set nosmartmips} 531218822SdimThe directive @code{.set smartmips} makes the assembler accept 532218822Sdiminstructions from the SmartMIPS Application Specific Extension to the 533218822SdimMIPS32 @sc{isa} from that point on in the assembly. The 534218822Sdim@code{.set nosmartmips} directive prevents SmartMIPS instructions from 535218822Sdimbeing accepted. 536218822Sdim 537179404Sobrien@cindex MIPS MDMX instruction generation override 538179404Sobrien@kindex @code{.set mdmx} 539179404Sobrien@kindex @code{.set nomdmx} 540179404SobrienThe directive @code{.set mdmx} makes the assembler accept instructions 541179404Sobrienfrom the MDMX Application Specific Extension from that point on 542179404Sobrienin the assembly. The @code{.set nomdmx} directive prevents MDMX 543179404Sobrieninstructions from being accepted. 544179404Sobrien 545218822Sdim@cindex MIPS DSP Release 1 instruction generation override 546218822Sdim@kindex @code{.set dsp} 547218822Sdim@kindex @code{.set nodsp} 548218822SdimThe directive @code{.set dsp} makes the assembler accept instructions 549218822Sdimfrom the DSP Release 1 Application Specific Extension from that point 550218822Sdimon in the assembly. The @code{.set nodsp} directive prevents DSP 551218822SdimRelease 1 instructions from being accepted. 552218822Sdim 553218822Sdim@cindex MIPS DSP Release 2 instruction generation override 554218822Sdim@kindex @code{.set dspr2} 555218822Sdim@kindex @code{.set nodspr2} 556218822SdimThe directive @code{.set dspr2} makes the assembler accept instructions 557218822Sdimfrom the DSP Release 2 Application Specific Extension from that point 558218822Sdimon in the assembly. This dirctive implies @code{.set dsp}. The 559218822Sdim@code{.set nodspr2} directive prevents DSP Release 2 instructions from 560218822Sdimbeing accepted. 561218822Sdim 562218822Sdim@cindex MIPS MT instruction generation override 563218822Sdim@kindex @code{.set mt} 564218822Sdim@kindex @code{.set nomt} 565218822SdimThe directive @code{.set mt} makes the assembler accept instructions 566218822Sdimfrom the MT Application Specific Extension from that point on 567218822Sdimin the assembly. The @code{.set nomt} directive prevents MT 568218822Sdiminstructions from being accepted. 569218822Sdim 570179404SobrienTraditional @sc{mips} assemblers do not support these directives. 571