tc-mips.c revision 185925
1/* tc-mips.c -- assemble code for a MIPS chip. 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 3 2003, 2004 Free Software Foundation, Inc. 4 Contributed by the OSF and Ralph Campbell. 5 Written by Keith Knowles and Ralph Campbell, working independently. 6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus 7 Support. 8 9 This file is part of GAS. 10 11 GAS is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 2, or (at your option) 14 any later version. 15 16 GAS is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with GAS; see the file COPYING. If not, write to the Free 23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 24 02111-1307, USA. */ 25 26#include "as.h" 27#include "config.h" 28#include "subsegs.h" 29#include "safe-ctype.h" 30 31#include <stdarg.h> 32 33#include "opcode/mips.h" 34#include "itbl-ops.h" 35#include "dwarf2dbg.h" 36 37#ifdef DEBUG 38#define DBG(x) printf x 39#else 40#define DBG(x) 41#endif 42 43#ifdef OBJ_MAYBE_ELF 44/* Clean up namespace so we can include obj-elf.h too. */ 45static int mips_output_flavor (void); 46static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } 47#undef OBJ_PROCESS_STAB 48#undef OUTPUT_FLAVOR 49#undef S_GET_ALIGN 50#undef S_GET_SIZE 51#undef S_SET_ALIGN 52#undef S_SET_SIZE 53#undef obj_frob_file 54#undef obj_frob_file_after_relocs 55#undef obj_frob_symbol 56#undef obj_pop_insert 57#undef obj_sec_sym_ok_for_reloc 58#undef OBJ_COPY_SYMBOL_ATTRIBUTES 59 60#include "obj-elf.h" 61/* Fix any of them that we actually care about. */ 62#undef OUTPUT_FLAVOR 63#define OUTPUT_FLAVOR mips_output_flavor() 64#endif 65 66#if defined (OBJ_ELF) 67#include "elf/mips.h" 68#endif 69 70#ifndef ECOFF_DEBUGGING 71#define NO_ECOFF_DEBUGGING 72#define ECOFF_DEBUGGING 0 73#endif 74 75int mips_flag_mdebug = -1; 76 77/* Control generation of .pdr sections. Off by default on IRIX: the native 78 linker doesn't know about and discards them, but relocations against them 79 remain, leading to rld crashes. */ 80#ifdef TE_IRIX 81int mips_flag_pdr = FALSE; 82#else 83int mips_flag_pdr = TRUE; 84#endif 85 86#include "ecoff.h" 87 88#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 89static char *mips_regmask_frag; 90#endif 91 92#define ZERO 0 93#define AT 1 94#define TREG 24 95#define PIC_CALL_REG 25 96#define KT0 26 97#define KT1 27 98#define GP 28 99#define SP 29 100#define FP 30 101#define RA 31 102 103#define ILLEGAL_REG (32) 104 105/* Allow override of standard little-endian ECOFF format. */ 106 107#ifndef ECOFF_LITTLE_FORMAT 108#define ECOFF_LITTLE_FORMAT "ecoff-littlemips" 109#endif 110 111extern int target_big_endian; 112 113/* The name of the readonly data section. */ 114#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ 115 ? ".data" \ 116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ 117 ? ".rdata" \ 118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \ 119 ? ".rdata" \ 120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \ 121 ? ".rodata" \ 122 : (abort (), "")) 123 124/* The ABI to use. */ 125enum mips_abi_level 126{ 127 NO_ABI = 0, 128 O32_ABI, 129 O64_ABI, 130 N32_ABI, 131 N64_ABI, 132 EABI_ABI 133}; 134 135/* MIPS ABI we are using for this output file. */ 136static enum mips_abi_level mips_abi = NO_ABI; 137 138/* Whether or not we have code that can call pic code. */ 139int mips_abicalls = FALSE; 140 141/* This is the set of options which may be modified by the .set 142 pseudo-op. We use a struct so that .set push and .set pop are more 143 reliable. */ 144 145struct mips_set_options 146{ 147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 148 if it has not been initialized. Changed by `.set mipsN', and the 149 -mipsN command line option, and the default CPU. */ 150 int isa; 151 /* Enabled Application Specific Extensions (ASEs). These are set to -1 152 if they have not been initialized. Changed by `.set <asename>', by 153 command line options, and based on the default architecture. */ 154 int ase_mips3d; 155 int ase_mdmx; 156 /* Whether we are assembling for the mips16 processor. 0 if we are 157 not, 1 if we are, and -1 if the value has not been initialized. 158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and 159 -nomips16 command line options, and the default CPU. */ 160 int mips16; 161 /* Non-zero if we should not reorder instructions. Changed by `.set 162 reorder' and `.set noreorder'. */ 163 int noreorder; 164 /* Non-zero if we should not permit the $at ($1) register to be used 165 in instructions. Changed by `.set at' and `.set noat'. */ 166 int noat; 167 /* Non-zero if we should warn when a macro instruction expands into 168 more than one machine instruction. Changed by `.set nomacro' and 169 `.set macro'. */ 170 int warn_about_macros; 171 /* Non-zero if we should not move instructions. Changed by `.set 172 move', `.set volatile', `.set nomove', and `.set novolatile'. */ 173 int nomove; 174 /* Non-zero if we should not optimize branches by moving the target 175 of the branch into the delay slot. Actually, we don't perform 176 this optimization anyhow. Changed by `.set bopt' and `.set 177 nobopt'. */ 178 int nobopt; 179 /* Non-zero if we should not autoextend mips16 instructions. 180 Changed by `.set autoextend' and `.set noautoextend'. */ 181 int noautoextend; 182 /* Restrict general purpose registers and floating point registers 183 to 32 bit. This is initially determined when -mgp32 or -mfp32 184 is passed but can changed if the assembler code uses .set mipsN. */ 185 int gp32; 186 int fp32; 187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march 188 command line option, and the default CPU. */ 189 int arch; 190}; 191 192/* True if -mgp32 was passed. */ 193static int file_mips_gp32 = -1; 194 195/* True if -mfp32 was passed. */ 196static int file_mips_fp32 = -1; 197 198/* This is the struct we use to hold the current set of options. Note 199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to 200 -1 to indicate that they have not been initialized. */ 201 202static struct mips_set_options mips_opts = 203{ 204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN 205}; 206 207/* These variables are filled in with the masks of registers used. 208 The object format code reads them and puts them in the appropriate 209 place. */ 210unsigned long mips_gprmask; 211unsigned long mips_cprmask[4]; 212 213/* MIPS ISA we are using for this output file. */ 214static int file_mips_isa = ISA_UNKNOWN; 215 216/* True if -mips16 was passed or implied by arguments passed on the 217 command line (e.g., by -march). */ 218static int file_ase_mips16; 219 220/* True if -mips3d was passed or implied by arguments passed on the 221 command line (e.g., by -march). */ 222static int file_ase_mips3d; 223 224/* True if -mdmx was passed or implied by arguments passed on the 225 command line (e.g., by -march). */ 226static int file_ase_mdmx; 227 228/* The argument of the -march= flag. The architecture we are assembling. */ 229static int file_mips_arch = CPU_UNKNOWN; 230static const char *mips_arch_string; 231 232/* The argument of the -mtune= flag. The architecture for which we 233 are optimizing. */ 234static int mips_tune = CPU_UNKNOWN; 235static const char *mips_tune_string; 236 237/* True when generating 32-bit code for a 64-bit processor. */ 238static int mips_32bitmode = 0; 239 240/* True if the given ABI requires 32-bit registers. */ 241#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) 242 243/* Likewise 64-bit registers. */ 244#define ABI_NEEDS_64BIT_REGS(ABI) \ 245 ((ABI) == N32_ABI \ 246 || (ABI) == N64_ABI \ 247 || (ABI) == O64_ABI) 248 249/* Return true if ISA supports 64 bit gp register instructions. */ 250#define ISA_HAS_64BIT_REGS(ISA) ( \ 251 (ISA) == ISA_MIPS3 \ 252 || (ISA) == ISA_MIPS4 \ 253 || (ISA) == ISA_MIPS5 \ 254 || (ISA) == ISA_MIPS64 \ 255 || (ISA) == ISA_MIPS64R2 \ 256 ) 257 258/* Return true if ISA supports 64-bit right rotate (dror et al.) 259 instructions. */ 260#define ISA_HAS_DROR(ISA) ( \ 261 (ISA) == ISA_MIPS64R2 \ 262 ) 263 264/* Return true if ISA supports 32-bit right rotate (ror et al.) 265 instructions. */ 266#define ISA_HAS_ROR(ISA) ( \ 267 (ISA) == ISA_MIPS32R2 \ 268 || (ISA) == ISA_MIPS64R2 \ 269 ) 270 271#define HAVE_32BIT_GPRS \ 272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) 273 274#define HAVE_32BIT_FPRS \ 275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) 276 277#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) 278#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) 279 280#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) 281 282#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) 283 284/* True if relocations are stored in-place. */ 285#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) 286 287/* We can only have 64bit addresses if the object file format 288 supports it. */ 289#define HAVE_32BIT_ADDRESSES \ 290 (HAVE_32BIT_GPRS \ 291 || ((bfd_arch_bits_per_address (stdoutput) == 32 \ 292 || ! HAVE_64BIT_OBJECTS) \ 293 && mips_pic != EMBEDDED_PIC)) 294 295#define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES) 296 297/* Addresses are loaded in different ways, depending on the address size 298 in use. The n32 ABI Documentation also mandates the use of additions 299 with overflow checking, but existing implementations don't follow it. */ 300#define ADDRESS_ADD_INSN \ 301 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") 302 303#define ADDRESS_ADDI_INSN \ 304 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") 305 306#define ADDRESS_LOAD_INSN \ 307 (HAVE_32BIT_ADDRESSES ? "lw" : "ld") 308 309#define ADDRESS_STORE_INSN \ 310 (HAVE_32BIT_ADDRESSES ? "sw" : "sd") 311 312/* Return true if the given CPU supports the MIPS16 ASE. */ 313#define CPU_HAS_MIPS16(cpu) \ 314 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ 315 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) 316 317/* Return true if the given CPU supports the MIPS3D ASE. */ 318#define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \ 319 ) 320 321/* Return true if the given CPU supports the MDMX ASE. */ 322#define CPU_HAS_MDMX(cpu) (FALSE \ 323 ) 324 325/* True if CPU has a dror instruction. */ 326#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) 327 328/* True if CPU has a ror instruction. */ 329#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) 330 331/* True if mflo and mfhi can be immediately followed by instructions 332 which write to the HI and LO registers. 333 334 According to MIPS specifications, MIPS ISAs I, II, and III need 335 (at least) two instructions between the reads of HI/LO and 336 instructions which write them, and later ISAs do not. Contradicting 337 the MIPS specifications, some MIPS IV processor user manuals (e.g. 338 the UM for the NEC Vr5000) document needing the instructions between 339 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, 340 MIPS64 and later ISAs to have the interlocks, plus any specific 341 earlier-ISA CPUs for which CPU documentation declares that the 342 instructions are really interlocked. */ 343#define hilo_interlocks \ 344 (mips_opts.isa == ISA_MIPS32 \ 345 || mips_opts.isa == ISA_MIPS32R2 \ 346 || mips_opts.isa == ISA_MIPS64 \ 347 || mips_opts.isa == ISA_MIPS64R2 \ 348 || mips_opts.arch == CPU_R4010 \ 349 || mips_opts.arch == CPU_R10000 \ 350 || mips_opts.arch == CPU_R12000 \ 351 || mips_opts.arch == CPU_RM7000 \ 352 || mips_opts.arch == CPU_SB1 \ 353 || mips_opts.arch == CPU_VR5500 \ 354 ) 355 356/* Whether the processor uses hardware interlocks to protect reads 357 from the GPRs after they are loaded from memory, and thus does not 358 require nops to be inserted. This applies to instructions marked 359 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA 360 level I. */ 361#define gpr_interlocks \ 362 (mips_opts.isa != ISA_MIPS1 \ 363 || mips_opts.arch == CPU_VR5400 \ 364 || mips_opts.arch == CPU_VR5500 \ 365 || mips_opts.arch == CPU_R3900) 366 367/* Whether the processor uses hardware interlocks to avoid delays 368 required by coprocessor instructions, and thus does not require 369 nops to be inserted. This applies to instructions marked 370 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays 371 between instructions marked INSN_WRITE_COND_CODE and ones marked 372 INSN_READ_COND_CODE. These nops are only required at MIPS ISA 373 levels I, II, and III. */ 374/* Itbl support may require additional care here. */ 375#define cop_interlocks \ 376 ((mips_opts.isa != ISA_MIPS1 \ 377 && mips_opts.isa != ISA_MIPS2 \ 378 && mips_opts.isa != ISA_MIPS3) \ 379 || mips_opts.arch == CPU_R4300 \ 380 || mips_opts.arch == CPU_VR5400 \ 381 || mips_opts.arch == CPU_VR5500 \ 382 || mips_opts.arch == CPU_SB1 \ 383 ) 384 385/* Whether the processor uses hardware interlocks to protect reads 386 from coprocessor registers after they are loaded from memory, and 387 thus does not require nops to be inserted. This applies to 388 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only 389 requires at MIPS ISA level I. */ 390#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1) 391 392/* Is this a mfhi or mflo instruction? */ 393#define MF_HILO_INSN(PINFO) \ 394 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) 395 396/* MIPS PIC level. */ 397 398enum mips_pic_level mips_pic; 399 400/* 1 if we should generate 32 bit offsets from the $gp register in 401 SVR4_PIC mode. Currently has no meaning in other modes. */ 402static int mips_big_got = 0; 403 404/* 1 if trap instructions should used for overflow rather than break 405 instructions. */ 406static int mips_trap = 0; 407 408/* 1 if double width floating point constants should not be constructed 409 by assembling two single width halves into two single width floating 410 point registers which just happen to alias the double width destination 411 register. On some architectures this aliasing can be disabled by a bit 412 in the status register, and the setting of this bit cannot be determined 413 automatically at assemble time. */ 414static int mips_disable_float_construction; 415 416/* Non-zero if any .set noreorder directives were used. */ 417 418static int mips_any_noreorder; 419 420/* Non-zero if nops should be inserted when the register referenced in 421 an mfhi/mflo instruction is read in the next two instructions. */ 422static int mips_7000_hilo_fix; 423 424/* The size of the small data section. */ 425static unsigned int g_switch_value = 8; 426/* Whether the -G option was used. */ 427static int g_switch_seen = 0; 428 429#define N_RMASK 0xc4 430#define N_VFP 0xd4 431 432/* If we can determine in advance that GP optimization won't be 433 possible, we can skip the relaxation stuff that tries to produce 434 GP-relative references. This makes delay slot optimization work 435 better. 436 437 This function can only provide a guess, but it seems to work for 438 gcc output. It needs to guess right for gcc, otherwise gcc 439 will put what it thinks is a GP-relative instruction in a branch 440 delay slot. 441 442 I don't know if a fix is needed for the SVR4_PIC mode. I've only 443 fixed it for the non-PIC mode. KR 95/04/07 */ 444static int nopic_need_relax (symbolS *, int); 445 446/* handle of the OPCODE hash table */ 447static struct hash_control *op_hash = NULL; 448 449/* The opcode hash table we use for the mips16. */ 450static struct hash_control *mips16_op_hash = NULL; 451 452/* This array holds the chars that always start a comment. If the 453 pre-processor is disabled, these aren't very useful */ 454const char comment_chars[] = "#"; 455 456/* This array holds the chars that only start a comment at the beginning of 457 a line. If the line seems to have the form '# 123 filename' 458 .line and .file directives will appear in the pre-processed output */ 459/* Note that input_file.c hand checks for '#' at the beginning of the 460 first line of the input file. This is because the compiler outputs 461 #NO_APP at the beginning of its output. */ 462/* Also note that C style comments are always supported. */ 463const char line_comment_chars[] = "#"; 464 465/* This array holds machine specific line separator characters. */ 466const char line_separator_chars[] = ";"; 467 468/* Chars that can be used to separate mant from exp in floating point nums */ 469const char EXP_CHARS[] = "eE"; 470 471/* Chars that mean this number is a floating point constant */ 472/* As in 0f12.456 */ 473/* or 0d1.2345e12 */ 474const char FLT_CHARS[] = "rRsSfFdDxXpP"; 475 476/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 477 changed in read.c . Ideally it shouldn't have to know about it at all, 478 but nothing is ideal around here. 479 */ 480 481static char *insn_error; 482 483static int auto_align = 1; 484 485/* When outputting SVR4 PIC code, the assembler needs to know the 486 offset in the stack frame from which to restore the $gp register. 487 This is set by the .cprestore pseudo-op, and saved in this 488 variable. */ 489static offsetT mips_cprestore_offset = -1; 490 491/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some 492 more optimizations, it can use a register value instead of a memory-saved 493 offset and even an other register than $gp as global pointer. */ 494static offsetT mips_cpreturn_offset = -1; 495static int mips_cpreturn_register = -1; 496static int mips_gp_register = GP; 497static int mips_gprel_offset = 0; 498 499/* Whether mips_cprestore_offset has been set in the current function 500 (or whether it has already been warned about, if not). */ 501static int mips_cprestore_valid = 0; 502 503/* This is the register which holds the stack frame, as set by the 504 .frame pseudo-op. This is needed to implement .cprestore. */ 505static int mips_frame_reg = SP; 506 507/* Whether mips_frame_reg has been set in the current function 508 (or whether it has already been warned about, if not). */ 509static int mips_frame_reg_valid = 0; 510 511/* To output NOP instructions correctly, we need to keep information 512 about the previous two instructions. */ 513 514/* Whether we are optimizing. The default value of 2 means to remove 515 unneeded NOPs and swap branch instructions when possible. A value 516 of 1 means to not swap branches. A value of 0 means to always 517 insert NOPs. */ 518static int mips_optimize = 2; 519 520/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is 521 equivalent to seeing no -g option at all. */ 522static int mips_debug = 0; 523 524/* The previous instruction. */ 525static struct mips_cl_insn prev_insn; 526 527/* The instruction before prev_insn. */ 528static struct mips_cl_insn prev_prev_insn; 529 530/* If we don't want information for prev_insn or prev_prev_insn, we 531 point the insn_mo field at this dummy integer. */ 532static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; 533 534/* Non-zero if prev_insn is valid. */ 535static int prev_insn_valid; 536 537/* The frag for the previous instruction. */ 538static struct frag *prev_insn_frag; 539 540/* The offset into prev_insn_frag for the previous instruction. */ 541static long prev_insn_where; 542 543/* The reloc type for the previous instruction, if any. */ 544static bfd_reloc_code_real_type prev_insn_reloc_type[3]; 545 546/* The reloc for the previous instruction, if any. */ 547static fixS *prev_insn_fixp[3]; 548 549/* Non-zero if the previous instruction was in a delay slot. */ 550static int prev_insn_is_delay_slot; 551 552/* Non-zero if the previous instruction was in a .set noreorder. */ 553static int prev_insn_unreordered; 554 555/* Non-zero if the previous instruction uses an extend opcode (if 556 mips16). */ 557static int prev_insn_extended; 558 559/* Non-zero if the previous previous instruction was in a .set 560 noreorder. */ 561static int prev_prev_insn_unreordered; 562 563/* If this is set, it points to a frag holding nop instructions which 564 were inserted before the start of a noreorder section. If those 565 nops turn out to be unnecessary, the size of the frag can be 566 decreased. */ 567static fragS *prev_nop_frag; 568 569/* The number of nop instructions we created in prev_nop_frag. */ 570static int prev_nop_frag_holds; 571 572/* The number of nop instructions that we know we need in 573 prev_nop_frag. */ 574static int prev_nop_frag_required; 575 576/* The number of instructions we've seen since prev_nop_frag. */ 577static int prev_nop_frag_since; 578 579/* For ECOFF and ELF, relocations against symbols are done in two 580 parts, with a HI relocation and a LO relocation. Each relocation 581 has only 16 bits of space to store an addend. This means that in 582 order for the linker to handle carries correctly, it must be able 583 to locate both the HI and the LO relocation. This means that the 584 relocations must appear in order in the relocation table. 585 586 In order to implement this, we keep track of each unmatched HI 587 relocation. We then sort them so that they immediately precede the 588 corresponding LO relocation. */ 589 590struct mips_hi_fixup 591{ 592 /* Next HI fixup. */ 593 struct mips_hi_fixup *next; 594 /* This fixup. */ 595 fixS *fixp; 596 /* The section this fixup is in. */ 597 segT seg; 598}; 599 600/* The list of unmatched HI relocs. */ 601 602static struct mips_hi_fixup *mips_hi_fixup_list; 603 604/* The frag containing the last explicit relocation operator. 605 Null if explicit relocations have not been used. */ 606 607static fragS *prev_reloc_op_frag; 608 609/* Map normal MIPS register numbers to mips16 register numbers. */ 610 611#define X ILLEGAL_REG 612static const int mips32_to_16_reg_map[] = 613{ 614 X, X, 2, 3, 4, 5, 6, 7, 615 X, X, X, X, X, X, X, X, 616 0, 1, X, X, X, X, X, X, 617 X, X, X, X, X, X, X, X 618}; 619#undef X 620 621/* Map mips16 register numbers to normal MIPS register numbers. */ 622 623static const unsigned int mips16_to_32_reg_map[] = 624{ 625 16, 17, 2, 3, 4, 5, 6, 7 626}; 627 628static int mips_fix_vr4120; 629 630/* We don't relax branches by default, since this causes us to expand 631 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we 632 fail to compute the offset before expanding the macro to the most 633 efficient expansion. */ 634 635static int mips_relax_branch; 636 637/* The expansion of many macros depends on the type of symbol that 638 they refer to. For example, when generating position-dependent code, 639 a macro that refers to a symbol may have two different expansions, 640 one which uses GP-relative addresses and one which uses absolute 641 addresses. When generating SVR4-style PIC, a macro may have 642 different expansions for local and global symbols. 643 644 We handle these situations by generating both sequences and putting 645 them in variant frags. In position-dependent code, the first sequence 646 will be the GP-relative one and the second sequence will be the 647 absolute one. In SVR4 PIC, the first sequence will be for global 648 symbols and the second will be for local symbols. 649 650 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and 651 SECOND are the lengths of the two sequences in bytes. These fields 652 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, 653 the subtype has the following flags: 654 655 RELAX_USE_SECOND 656 Set if it has been decided that we should use the second 657 sequence instead of the first. 658 659 RELAX_SECOND_LONGER 660 Set in the first variant frag if the macro's second implementation 661 is longer than its first. This refers to the macro as a whole, 662 not an individual relaxation. 663 664 RELAX_NOMACRO 665 Set in the first variant frag if the macro appeared in a .set nomacro 666 block and if one alternative requires a warning but the other does not. 667 668 RELAX_DELAY_SLOT 669 Like RELAX_NOMACRO, but indicates that the macro appears in a branch 670 delay slot. 671 672 The frag's "opcode" points to the first fixup for relaxable code. 673 674 Relaxable macros are generated using a sequence such as: 675 676 relax_start (SYMBOL); 677 ... generate first expansion ... 678 relax_switch (); 679 ... generate second expansion ... 680 relax_end (); 681 682 The code and fixups for the unwanted alternative are discarded 683 by md_convert_frag. */ 684#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) 685 686#define RELAX_FIRST(X) (((X) >> 8) & 0xff) 687#define RELAX_SECOND(X) ((X) & 0xff) 688#define RELAX_USE_SECOND 0x10000 689#define RELAX_SECOND_LONGER 0x20000 690#define RELAX_NOMACRO 0x40000 691#define RELAX_DELAY_SLOT 0x80000 692 693/* Branch without likely bit. If label is out of range, we turn: 694 695 beq reg1, reg2, label 696 delay slot 697 698 into 699 700 bne reg1, reg2, 0f 701 nop 702 j label 703 0: delay slot 704 705 with the following opcode replacements: 706 707 beq <-> bne 708 blez <-> bgtz 709 bltz <-> bgez 710 bc1f <-> bc1t 711 712 bltzal <-> bgezal (with jal label instead of j label) 713 714 Even though keeping the delay slot instruction in the delay slot of 715 the branch would be more efficient, it would be very tricky to do 716 correctly, because we'd have to introduce a variable frag *after* 717 the delay slot instruction, and expand that instead. Let's do it 718 the easy way for now, even if the branch-not-taken case now costs 719 one additional instruction. Out-of-range branches are not supposed 720 to be common, anyway. 721 722 Branch likely. If label is out of range, we turn: 723 724 beql reg1, reg2, label 725 delay slot (annulled if branch not taken) 726 727 into 728 729 beql reg1, reg2, 1f 730 nop 731 beql $0, $0, 2f 732 nop 733 1: j[al] label 734 delay slot (executed only if branch taken) 735 2: 736 737 It would be possible to generate a shorter sequence by losing the 738 likely bit, generating something like: 739 740 bne reg1, reg2, 0f 741 nop 742 j[al] label 743 delay slot (executed only if branch taken) 744 0: 745 746 beql -> bne 747 bnel -> beq 748 blezl -> bgtz 749 bgtzl -> blez 750 bltzl -> bgez 751 bgezl -> bltz 752 bc1fl -> bc1t 753 bc1tl -> bc1f 754 755 bltzall -> bgezal (with jal label instead of j label) 756 bgezall -> bltzal (ditto) 757 758 759 but it's not clear that it would actually improve performance. */ 760#define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \ 761 ((relax_substateT) \ 762 (0xc0000000 \ 763 | ((toofar) ? 1 : 0) \ 764 | ((link) ? 2 : 0) \ 765 | ((likely) ? 4 : 0) \ 766 | ((uncond) ? 8 : 0))) 767#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 768#define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0) 769#define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0) 770#define RELAX_BRANCH_LINK(i) (((i) & 2) != 0) 771#define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0) 772 773/* For mips16 code, we use an entirely different form of relaxation. 774 mips16 supports two versions of most instructions which take 775 immediate values: a small one which takes some small value, and a 776 larger one which takes a 16 bit value. Since branches also follow 777 this pattern, relaxing these values is required. 778 779 We can assemble both mips16 and normal MIPS code in a single 780 object. Therefore, we need to support this type of relaxation at 781 the same time that we support the relaxation described above. We 782 use the high bit of the subtype field to distinguish these cases. 783 784 The information we store for this type of relaxation is the 785 argument code found in the opcode file for this relocation, whether 786 the user explicitly requested a small or extended form, and whether 787 the relocation is in a jump or jal delay slot. That tells us the 788 size of the value, and how it should be stored. We also store 789 whether the fragment is considered to be extended or not. We also 790 store whether this is known to be a branch to a different section, 791 whether we have tried to relax this frag yet, and whether we have 792 ever extended a PC relative fragment because of a shift count. */ 793#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ 794 (0x80000000 \ 795 | ((type) & 0xff) \ 796 | ((small) ? 0x100 : 0) \ 797 | ((ext) ? 0x200 : 0) \ 798 | ((dslot) ? 0x400 : 0) \ 799 | ((jal_dslot) ? 0x800 : 0)) 800#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) 801#define RELAX_MIPS16_TYPE(i) ((i) & 0xff) 802#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) 803#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) 804#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) 805#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) 806#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) 807#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) 808#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) 809#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) 810#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) 811#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) 812 813/* Is the given value a sign-extended 32-bit value? */ 814#define IS_SEXT_32BIT_NUM(x) \ 815 (((x) &~ (offsetT) 0x7fffffff) == 0 \ 816 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 817 818/* Is the given value a sign-extended 16-bit value? */ 819#define IS_SEXT_16BIT_NUM(x) \ 820 (((x) &~ (offsetT) 0x7fff) == 0 \ 821 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) 822 823 824/* Global variables used when generating relaxable macros. See the 825 comment above RELAX_ENCODE for more details about how relaxation 826 is used. */ 827static struct { 828 /* 0 if we're not emitting a relaxable macro. 829 1 if we're emitting the first of the two relaxation alternatives. 830 2 if we're emitting the second alternative. */ 831 int sequence; 832 833 /* The first relaxable fixup in the current frag. (In other words, 834 the first fixup that refers to relaxable code.) */ 835 fixS *first_fixup; 836 837 /* sizes[0] says how many bytes of the first alternative are stored in 838 the current frag. Likewise sizes[1] for the second alternative. */ 839 unsigned int sizes[2]; 840 841 /* The symbol on which the choice of sequence depends. */ 842 symbolS *symbol; 843} mips_relax; 844 845/* Global variables used to decide whether a macro needs a warning. */ 846static struct { 847 /* True if the macro is in a branch delay slot. */ 848 bfd_boolean delay_slot_p; 849 850 /* For relaxable macros, sizes[0] is the length of the first alternative 851 in bytes and sizes[1] is the length of the second alternative. 852 For non-relaxable macros, both elements give the length of the 853 macro in bytes. */ 854 unsigned int sizes[2]; 855 856 /* The first variant frag for this macro. */ 857 fragS *first_frag; 858} mips_macro_warning; 859 860/* Prototypes for static functions. */ 861 862#define internalError() \ 863 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) 864 865enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; 866 867static void append_insn 868 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r); 869static void mips_no_prev_insn (int); 870static void mips16_macro_build 871 (expressionS *, const char *, const char *, va_list); 872static void load_register (int, expressionS *, int); 873static void macro_start (void); 874static void macro_end (void); 875static void macro (struct mips_cl_insn * ip); 876static void mips16_macro (struct mips_cl_insn * ip); 877#ifdef LOSING_COMPILER 878static void macro2 (struct mips_cl_insn * ip); 879#endif 880static void mips_ip (char *str, struct mips_cl_insn * ip); 881static void mips16_ip (char *str, struct mips_cl_insn * ip); 882static void mips16_immed 883 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean, 884 unsigned long *, bfd_boolean *, unsigned short *); 885static size_t my_getSmallExpression 886 (expressionS *, bfd_reloc_code_real_type *, char *); 887static void my_getExpression (expressionS *, char *); 888static void s_align (int); 889static void s_change_sec (int); 890static void s_change_section (int); 891static void s_cons (int); 892static void s_float_cons (int); 893static void s_mips_globl (int); 894static void s_option (int); 895static void s_mipsset (int); 896static void s_abicalls (int); 897static void s_cpload (int); 898static void s_cpsetup (int); 899static void s_cplocal (int); 900static void s_cprestore (int); 901static void s_cpreturn (int); 902static void s_gpvalue (int); 903static void s_gpword (int); 904static void s_gpdword (int); 905static void s_cpadd (int); 906static void s_insn (int); 907static void md_obj_begin (void); 908static void md_obj_end (void); 909static void s_mips_ent (int); 910static void s_mips_end (int); 911static void s_mips_frame (int); 912static void s_mips_mask (int reg_type); 913static void s_mips_stab (int); 914static void s_mips_weakext (int); 915static void s_mips_file (int); 916static void s_mips_loc (int); 917static bfd_boolean pic_need_relax (symbolS *, asection *); 918static int relaxed_branch_length (fragS *, asection *, int); 919static int validate_mips_insn (const struct mips_opcode *); 920 921/* Table and functions used to map between CPU/ISA names, and 922 ISA levels, and CPU numbers. */ 923 924struct mips_cpu_info 925{ 926 const char *name; /* CPU or ISA name. */ 927 int is_isa; /* Is this an ISA? (If 0, a CPU.) */ 928 int isa; /* ISA level. */ 929 int cpu; /* CPU number (default CPU if ISA). */ 930}; 931 932static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); 933static const struct mips_cpu_info *mips_cpu_info_from_isa (int); 934static const struct mips_cpu_info *mips_cpu_info_from_arch (int); 935 936/* Pseudo-op table. 937 938 The following pseudo-ops from the Kane and Heinrich MIPS book 939 should be defined here, but are currently unsupported: .alias, 940 .galive, .gjaldef, .gjrlive, .livereg, .noalias. 941 942 The following pseudo-ops from the Kane and Heinrich MIPS book are 943 specific to the type of debugging information being generated, and 944 should be defined by the object format: .aent, .begin, .bend, 945 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, 946 .vreg. 947 948 The following pseudo-ops from the Kane and Heinrich MIPS book are 949 not MIPS CPU specific, but are also not specific to the object file 950 format. This file is probably the best place to define them, but 951 they are not currently supported: .asm0, .endr, .lab, .repeat, 952 .struct. */ 953 954static const pseudo_typeS mips_pseudo_table[] = 955{ 956 /* MIPS specific pseudo-ops. */ 957 {"option", s_option, 0}, 958 {"set", s_mipsset, 0}, 959 {"rdata", s_change_sec, 'r'}, 960 {"sdata", s_change_sec, 's'}, 961 {"livereg", s_ignore, 0}, 962 {"abicalls", s_abicalls, 0}, 963 {"cpload", s_cpload, 0}, 964 {"cpsetup", s_cpsetup, 0}, 965 {"cplocal", s_cplocal, 0}, 966 {"cprestore", s_cprestore, 0}, 967 {"cpreturn", s_cpreturn, 0}, 968 {"gpvalue", s_gpvalue, 0}, 969 {"gpword", s_gpword, 0}, 970 {"gpdword", s_gpdword, 0}, 971 {"cpadd", s_cpadd, 0}, 972 {"insn", s_insn, 0}, 973 974 /* Relatively generic pseudo-ops that happen to be used on MIPS 975 chips. */ 976 {"asciiz", stringer, 1}, 977 {"bss", s_change_sec, 'b'}, 978 {"err", s_err, 0}, 979 {"half", s_cons, 1}, 980 {"dword", s_cons, 3}, 981 {"weakext", s_mips_weakext, 0}, 982 983 /* These pseudo-ops are defined in read.c, but must be overridden 984 here for one reason or another. */ 985 {"align", s_align, 0}, 986 {"byte", s_cons, 0}, 987 {"data", s_change_sec, 'd'}, 988 {"double", s_float_cons, 'd'}, 989 {"float", s_float_cons, 'f'}, 990 {"globl", s_mips_globl, 0}, 991 {"global", s_mips_globl, 0}, 992 {"hword", s_cons, 1}, 993 {"int", s_cons, 2}, 994 {"long", s_cons, 2}, 995 {"octa", s_cons, 4}, 996 {"quad", s_cons, 3}, 997 {"section", s_change_section, 0}, 998 {"short", s_cons, 1}, 999 {"single", s_float_cons, 'f'}, 1000 {"stabn", s_mips_stab, 'n'}, 1001 {"text", s_change_sec, 't'}, 1002 {"word", s_cons, 2}, 1003 1004 { "extern", ecoff_directive_extern, 0}, 1005 1006 { NULL, NULL, 0 }, 1007}; 1008 1009static const pseudo_typeS mips_nonecoff_pseudo_table[] = 1010{ 1011 /* These pseudo-ops should be defined by the object file format. 1012 However, a.out doesn't support them, so we have versions here. */ 1013 {"aent", s_mips_ent, 1}, 1014 {"bgnb", s_ignore, 0}, 1015 {"end", s_mips_end, 0}, 1016 {"endb", s_ignore, 0}, 1017 {"ent", s_mips_ent, 0}, 1018 {"file", s_mips_file, 0}, 1019 {"fmask", s_mips_mask, 'F'}, 1020 {"frame", s_mips_frame, 0}, 1021 {"loc", s_mips_loc, 0}, 1022 {"mask", s_mips_mask, 'R'}, 1023 {"verstamp", s_ignore, 0}, 1024 { NULL, NULL, 0 }, 1025}; 1026 1027extern void pop_insert (const pseudo_typeS *); 1028 1029void 1030mips_pop_insert (void) 1031{ 1032 pop_insert (mips_pseudo_table); 1033 if (! ECOFF_DEBUGGING) 1034 pop_insert (mips_nonecoff_pseudo_table); 1035} 1036 1037/* Symbols labelling the current insn. */ 1038 1039struct insn_label_list 1040{ 1041 struct insn_label_list *next; 1042 symbolS *label; 1043}; 1044 1045static struct insn_label_list *insn_labels; 1046static struct insn_label_list *free_insn_labels; 1047 1048static void mips_clear_insn_labels (void); 1049 1050static inline void 1051mips_clear_insn_labels (void) 1052{ 1053 register struct insn_label_list **pl; 1054 1055 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 1056 ; 1057 *pl = insn_labels; 1058 insn_labels = NULL; 1059} 1060 1061static char *expr_end; 1062 1063/* Expressions which appear in instructions. These are set by 1064 mips_ip. */ 1065 1066static expressionS imm_expr; 1067static expressionS imm2_expr; 1068static expressionS offset_expr; 1069 1070/* Relocs associated with imm_expr and offset_expr. */ 1071 1072static bfd_reloc_code_real_type imm_reloc[3] 1073 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1074static bfd_reloc_code_real_type offset_reloc[3] 1075 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1076 1077/* These are set by mips16_ip if an explicit extension is used. */ 1078 1079static bfd_boolean mips16_small, mips16_ext; 1080 1081#ifdef OBJ_ELF 1082/* The pdr segment for per procedure frame/regmask info. Not used for 1083 ECOFF debugging. */ 1084 1085static segT pdr_seg; 1086#endif 1087 1088/* The default target format to use. */ 1089 1090const char * 1091mips_target_format (void) 1092{ 1093 switch (OUTPUT_FLAVOR) 1094 { 1095 case bfd_target_aout_flavour: 1096 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; 1097 case bfd_target_ecoff_flavour: 1098 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; 1099 case bfd_target_coff_flavour: 1100 return "pe-mips"; 1101 case bfd_target_elf_flavour: 1102#ifdef TE_TMIPS 1103 /* This is traditional mips. */ 1104 return (target_big_endian 1105 ? (HAVE_64BIT_OBJECTS 1106 ? "elf64-tradbigmips" 1107 : (HAVE_NEWABI 1108 ? "elf32-ntradbigmips" : "elf32-tradbigmips")) 1109 : (HAVE_64BIT_OBJECTS 1110 ? "elf64-tradlittlemips" 1111 : (HAVE_NEWABI 1112 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips"))); 1113#else 1114 return (target_big_endian 1115 ? (HAVE_64BIT_OBJECTS 1116 ? "elf64-bigmips" 1117 : (HAVE_NEWABI 1118 ? "elf32-nbigmips" : "elf32-bigmips")) 1119 : (HAVE_64BIT_OBJECTS 1120 ? "elf64-littlemips" 1121 : (HAVE_NEWABI 1122 ? "elf32-nlittlemips" : "elf32-littlemips"))); 1123#endif 1124 default: 1125 abort (); 1126 return NULL; 1127 } 1128} 1129 1130/* This function is called once, at assembler startup time. It should 1131 set up all the tables, etc. that the MD part of the assembler will need. */ 1132 1133void 1134md_begin (void) 1135{ 1136 register const char *retval = NULL; 1137 int i = 0; 1138 int broken = 0; 1139 1140 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) 1141 as_warn (_("Could not set architecture and machine")); 1142 1143 op_hash = hash_new (); 1144 1145 for (i = 0; i < NUMOPCODES;) 1146 { 1147 const char *name = mips_opcodes[i].name; 1148 1149 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); 1150 if (retval != NULL) 1151 { 1152 fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 1153 mips_opcodes[i].name, retval); 1154 /* Probably a memory allocation problem? Give up now. */ 1155 as_fatal (_("Broken assembler. No assembly attempted.")); 1156 } 1157 do 1158 { 1159 if (mips_opcodes[i].pinfo != INSN_MACRO) 1160 { 1161 if (!validate_mips_insn (&mips_opcodes[i])) 1162 broken = 1; 1163 } 1164 ++i; 1165 } 1166 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); 1167 } 1168 1169 mips16_op_hash = hash_new (); 1170 1171 i = 0; 1172 while (i < bfd_mips16_num_opcodes) 1173 { 1174 const char *name = mips16_opcodes[i].name; 1175 1176 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); 1177 if (retval != NULL) 1178 as_fatal (_("internal: can't hash `%s': %s"), 1179 mips16_opcodes[i].name, retval); 1180 do 1181 { 1182 if (mips16_opcodes[i].pinfo != INSN_MACRO 1183 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) 1184 != mips16_opcodes[i].match)) 1185 { 1186 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), 1187 mips16_opcodes[i].name, mips16_opcodes[i].args); 1188 broken = 1; 1189 } 1190 ++i; 1191 } 1192 while (i < bfd_mips16_num_opcodes 1193 && strcmp (mips16_opcodes[i].name, name) == 0); 1194 } 1195 1196 if (broken) 1197 as_fatal (_("Broken assembler. No assembly attempted.")); 1198 1199 /* We add all the general register names to the symbol table. This 1200 helps us detect invalid uses of them. */ 1201 for (i = 0; i < 32; i++) 1202 { 1203 char buf[5]; 1204 1205 sprintf (buf, "$%d", i); 1206 symbol_table_insert (symbol_new (buf, reg_section, i, 1207 &zero_address_frag)); 1208 } 1209 symbol_table_insert (symbol_new ("$ra", reg_section, RA, 1210 &zero_address_frag)); 1211 symbol_table_insert (symbol_new ("$fp", reg_section, FP, 1212 &zero_address_frag)); 1213 symbol_table_insert (symbol_new ("$sp", reg_section, SP, 1214 &zero_address_frag)); 1215 symbol_table_insert (symbol_new ("$gp", reg_section, GP, 1216 &zero_address_frag)); 1217 symbol_table_insert (symbol_new ("$at", reg_section, AT, 1218 &zero_address_frag)); 1219 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, 1220 &zero_address_frag)); 1221 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, 1222 &zero_address_frag)); 1223 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO, 1224 &zero_address_frag)); 1225 symbol_table_insert (symbol_new ("$pc", reg_section, -1, 1226 &zero_address_frag)); 1227 1228 /* If we don't add these register names to the symbol table, they 1229 may end up being added as regular symbols by operand(), and then 1230 make it to the object file as undefined in case they're not 1231 regarded as local symbols. They're local in o32, since `$' is a 1232 local symbol prefix, but not in n32 or n64. */ 1233 for (i = 0; i < 8; i++) 1234 { 1235 char buf[6]; 1236 1237 sprintf (buf, "$fcc%i", i); 1238 symbol_table_insert (symbol_new (buf, reg_section, -1, 1239 &zero_address_frag)); 1240 } 1241 1242 mips_no_prev_insn (FALSE); 1243 1244 mips_gprmask = 0; 1245 mips_cprmask[0] = 0; 1246 mips_cprmask[1] = 0; 1247 mips_cprmask[2] = 0; 1248 mips_cprmask[3] = 0; 1249 1250 /* set the default alignment for the text section (2**2) */ 1251 record_alignment (text_section, 2); 1252 1253 if (USE_GLOBAL_POINTER_OPT) 1254 bfd_set_gp_size (stdoutput, g_switch_value); 1255 1256 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 1257 { 1258 /* On a native system, sections must be aligned to 16 byte 1259 boundaries. When configured for an embedded ELF target, we 1260 don't bother. */ 1261 if (strcmp (TARGET_OS, "elf") != 0) 1262 { 1263 (void) bfd_set_section_alignment (stdoutput, text_section, 4); 1264 (void) bfd_set_section_alignment (stdoutput, data_section, 4); 1265 (void) bfd_set_section_alignment (stdoutput, bss_section, 4); 1266 } 1267 1268 /* Create a .reginfo section for register masks and a .mdebug 1269 section for debugging information. */ 1270 { 1271 segT seg; 1272 subsegT subseg; 1273 flagword flags; 1274 segT sec; 1275 1276 seg = now_seg; 1277 subseg = now_subseg; 1278 1279 /* The ABI says this section should be loaded so that the 1280 running program can access it. However, we don't load it 1281 if we are configured for an embedded target */ 1282 flags = SEC_READONLY | SEC_DATA; 1283 if (strcmp (TARGET_OS, "elf") != 0) 1284 flags |= SEC_ALLOC | SEC_LOAD; 1285 1286 if (mips_abi != N64_ABI) 1287 { 1288 sec = subseg_new (".reginfo", (subsegT) 0); 1289 1290 bfd_set_section_flags (stdoutput, sec, flags); 1291 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); 1292 1293#ifdef OBJ_ELF 1294 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); 1295#endif 1296 } 1297 else 1298 { 1299 /* The 64-bit ABI uses a .MIPS.options section rather than 1300 .reginfo section. */ 1301 sec = subseg_new (".MIPS.options", (subsegT) 0); 1302 bfd_set_section_flags (stdoutput, sec, flags); 1303 bfd_set_section_alignment (stdoutput, sec, 3); 1304 1305#ifdef OBJ_ELF 1306 /* Set up the option header. */ 1307 { 1308 Elf_Internal_Options opthdr; 1309 char *f; 1310 1311 opthdr.kind = ODK_REGINFO; 1312 opthdr.size = (sizeof (Elf_External_Options) 1313 + sizeof (Elf64_External_RegInfo)); 1314 opthdr.section = 0; 1315 opthdr.info = 0; 1316 f = frag_more (sizeof (Elf_External_Options)); 1317 bfd_mips_elf_swap_options_out (stdoutput, &opthdr, 1318 (Elf_External_Options *) f); 1319 1320 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); 1321 } 1322#endif 1323 } 1324 1325 if (ECOFF_DEBUGGING) 1326 { 1327 sec = subseg_new (".mdebug", (subsegT) 0); 1328 (void) bfd_set_section_flags (stdoutput, sec, 1329 SEC_HAS_CONTENTS | SEC_READONLY); 1330 (void) bfd_set_section_alignment (stdoutput, sec, 2); 1331 } 1332#ifdef OBJ_ELF 1333 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr) 1334 { 1335 pdr_seg = subseg_new (".pdr", (subsegT) 0); 1336 (void) bfd_set_section_flags (stdoutput, pdr_seg, 1337 SEC_READONLY | SEC_RELOC 1338 | SEC_DEBUGGING); 1339 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); 1340 } 1341#endif 1342 1343 subseg_set (seg, subseg); 1344 } 1345 } 1346 1347 if (! ECOFF_DEBUGGING) 1348 md_obj_begin (); 1349} 1350 1351void 1352md_mips_end (void) 1353{ 1354 if (! ECOFF_DEBUGGING) 1355 md_obj_end (); 1356} 1357 1358void 1359md_assemble (char *str) 1360{ 1361 struct mips_cl_insn insn; 1362 bfd_reloc_code_real_type unused_reloc[3] 1363 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 1364 1365 imm_expr.X_op = O_absent; 1366 imm2_expr.X_op = O_absent; 1367 offset_expr.X_op = O_absent; 1368 imm_reloc[0] = BFD_RELOC_UNUSED; 1369 imm_reloc[1] = BFD_RELOC_UNUSED; 1370 imm_reloc[2] = BFD_RELOC_UNUSED; 1371 offset_reloc[0] = BFD_RELOC_UNUSED; 1372 offset_reloc[1] = BFD_RELOC_UNUSED; 1373 offset_reloc[2] = BFD_RELOC_UNUSED; 1374 1375 if (mips_opts.mips16) 1376 mips16_ip (str, &insn); 1377 else 1378 { 1379 mips_ip (str, &insn); 1380 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), 1381 str, insn.insn_opcode)); 1382 } 1383 1384 if (insn_error) 1385 { 1386 as_bad ("%s `%s'", insn_error, str); 1387 return; 1388 } 1389 1390 if (insn.insn_mo->pinfo == INSN_MACRO) 1391 { 1392 macro_start (); 1393 if (mips_opts.mips16) 1394 mips16_macro (&insn); 1395 else 1396 macro (&insn); 1397 macro_end (); 1398 } 1399 else 1400 { 1401 if (imm_expr.X_op != O_absent) 1402 append_insn (&insn, &imm_expr, imm_reloc); 1403 else if (offset_expr.X_op != O_absent) 1404 append_insn (&insn, &offset_expr, offset_reloc); 1405 else 1406 append_insn (&insn, NULL, unused_reloc); 1407 } 1408} 1409 1410/* Return true if the given relocation might need a matching %lo(). 1411 Note that R_MIPS_GOT16 relocations only need a matching %lo() when 1412 applied to local symbols. */ 1413 1414static inline bfd_boolean 1415reloc_needs_lo_p (bfd_reloc_code_real_type reloc) 1416{ 1417 return (reloc == BFD_RELOC_HI16_S 1418 || reloc == BFD_RELOC_MIPS_GOT16); 1419} 1420 1421/* Return true if the given fixup is followed by a matching R_MIPS_LO16 1422 relocation. */ 1423 1424static inline bfd_boolean 1425fixup_has_matching_lo_p (fixS *fixp) 1426{ 1427 return (fixp->fx_next != NULL 1428 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16 1429 && fixp->fx_addsy == fixp->fx_next->fx_addsy 1430 && fixp->fx_offset == fixp->fx_next->fx_offset); 1431} 1432 1433/* See whether instruction IP reads register REG. CLASS is the type 1434 of register. */ 1435 1436static int 1437insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg, 1438 enum mips_regclass class) 1439{ 1440 if (class == MIPS16_REG) 1441 { 1442 assert (mips_opts.mips16); 1443 reg = mips16_to_32_reg_map[reg]; 1444 class = MIPS_GR_REG; 1445 } 1446 1447 /* Don't report on general register ZERO, since it never changes. */ 1448 if (class == MIPS_GR_REG && reg == ZERO) 1449 return 0; 1450 1451 if (class == MIPS_FP_REG) 1452 { 1453 assert (! mips_opts.mips16); 1454 /* If we are called with either $f0 or $f1, we must check $f0. 1455 This is not optimal, because it will introduce an unnecessary 1456 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would 1457 need to distinguish reading both $f0 and $f1 or just one of 1458 them. Note that we don't have to check the other way, 1459 because there is no instruction that sets both $f0 and $f1 1460 and requires a delay. */ 1461 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) 1462 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) 1463 == (reg &~ (unsigned) 1))) 1464 return 1; 1465 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) 1466 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) 1467 == (reg &~ (unsigned) 1))) 1468 return 1; 1469 } 1470 else if (! mips_opts.mips16) 1471 { 1472 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) 1473 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) 1474 return 1; 1475 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) 1476 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) 1477 return 1; 1478 } 1479 else 1480 { 1481 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) 1482 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) 1483 & MIPS16OP_MASK_RX)] 1484 == reg)) 1485 return 1; 1486 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) 1487 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) 1488 & MIPS16OP_MASK_RY)] 1489 == reg)) 1490 return 1; 1491 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) 1492 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) 1493 & MIPS16OP_MASK_MOVE32Z)] 1494 == reg)) 1495 return 1; 1496 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) 1497 return 1; 1498 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) 1499 return 1; 1500 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) 1501 return 1; 1502 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) 1503 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) 1504 & MIPS16OP_MASK_REGR32) == reg) 1505 return 1; 1506 } 1507 1508 return 0; 1509} 1510 1511/* This function returns true if modifying a register requires a 1512 delay. */ 1513 1514static int 1515reg_needs_delay (unsigned int reg) 1516{ 1517 unsigned long prev_pinfo; 1518 1519 prev_pinfo = prev_insn.insn_mo->pinfo; 1520 if (! mips_opts.noreorder 1521 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) 1522 && ! gpr_interlocks) 1523 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) 1524 && ! cop_interlocks))) 1525 { 1526 /* A load from a coprocessor or from memory. All load delays 1527 delay the use of general register rt for one instruction. */ 1528 /* Itbl support may require additional care here. */ 1529 know (prev_pinfo & INSN_WRITE_GPR_T); 1530 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) 1531 return 1; 1532 } 1533 1534 return 0; 1535} 1536 1537/* Mark instruction labels in mips16 mode. This permits the linker to 1538 handle them specially, such as generating jalx instructions when 1539 needed. We also make them odd for the duration of the assembly, in 1540 order to generate the right sort of code. We will make them even 1541 in the adjust_symtab routine, while leaving them marked. This is 1542 convenient for the debugger and the disassembler. The linker knows 1543 to make them odd again. */ 1544 1545static void 1546mips16_mark_labels (void) 1547{ 1548 if (mips_opts.mips16) 1549 { 1550 struct insn_label_list *l; 1551 valueT val; 1552 1553 for (l = insn_labels; l != NULL; l = l->next) 1554 { 1555#ifdef OBJ_ELF 1556 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 1557 S_SET_OTHER (l->label, STO_MIPS16); 1558#endif 1559 val = S_GET_VALUE (l->label); 1560 if ((val & 1) == 0) 1561 S_SET_VALUE (l->label, val + 1); 1562 } 1563 } 1564} 1565 1566/* End the current frag. Make it a variant frag and record the 1567 relaxation info. */ 1568 1569static void 1570relax_close_frag (void) 1571{ 1572 mips_macro_warning.first_frag = frag_now; 1573 frag_var (rs_machine_dependent, 0, 0, 1574 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]), 1575 mips_relax.symbol, 0, (char *) mips_relax.first_fixup); 1576 1577 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); 1578 mips_relax.first_fixup = 0; 1579} 1580 1581/* Start a new relaxation sequence whose expansion depends on SYMBOL. 1582 See the comment above RELAX_ENCODE for more details. */ 1583 1584static void 1585relax_start (symbolS *symbol) 1586{ 1587 assert (mips_relax.sequence == 0); 1588 mips_relax.sequence = 1; 1589 mips_relax.symbol = symbol; 1590} 1591 1592/* Start generating the second version of a relaxable sequence. 1593 See the comment above RELAX_ENCODE for more details. */ 1594 1595static void 1596relax_switch (void) 1597{ 1598 assert (mips_relax.sequence == 1); 1599 mips_relax.sequence = 2; 1600} 1601 1602/* End the current relaxable sequence. */ 1603 1604static void 1605relax_end (void) 1606{ 1607 assert (mips_relax.sequence == 2); 1608 relax_close_frag (); 1609 mips_relax.sequence = 0; 1610} 1611 1612/* Output an instruction. IP is the instruction information. 1613 ADDRESS_EXPR is an operand of the instruction to be used with 1614 RELOC_TYPE. */ 1615 1616static void 1617append_insn (struct mips_cl_insn *ip, expressionS *address_expr, 1618 bfd_reloc_code_real_type *reloc_type) 1619{ 1620 register unsigned long prev_pinfo, pinfo; 1621 char *f; 1622 fixS *fixp[3]; 1623 int nops = 0; 1624 relax_stateT prev_insn_frag_type = 0; 1625 bfd_boolean relaxed_branch = FALSE; 1626 bfd_boolean force_new_frag = FALSE; 1627 1628 /* Mark instruction labels in mips16 mode. */ 1629 mips16_mark_labels (); 1630 1631 prev_pinfo = prev_insn.insn_mo->pinfo; 1632 pinfo = ip->insn_mo->pinfo; 1633 1634 if (mips_relax.sequence != 2 1635 && (!mips_opts.noreorder || prev_nop_frag != NULL)) 1636 { 1637 int prev_prev_nop; 1638 1639 /* If the previous insn required any delay slots, see if we need 1640 to insert a NOP or two. There are eight kinds of possible 1641 hazards, of which an instruction can have at most one type. 1642 (1) a load from memory delay 1643 (2) a load from a coprocessor delay 1644 (3) an unconditional branch delay 1645 (4) a conditional branch delay 1646 (5) a move to coprocessor register delay 1647 (6) a load coprocessor register from memory delay 1648 (7) a coprocessor condition code delay 1649 (8) a HI/LO special register delay 1650 1651 There are a lot of optimizations we could do that we don't. 1652 In particular, we do not, in general, reorder instructions. 1653 If you use gcc with optimization, it will reorder 1654 instructions and generally do much more optimization then we 1655 do here; repeating all that work in the assembler would only 1656 benefit hand written assembly code, and does not seem worth 1657 it. */ 1658 1659 /* This is how a NOP is emitted. */ 1660#define emit_nop() \ 1661 (mips_opts.mips16 \ 1662 ? md_number_to_chars (frag_more (2), 0x6500, 2) \ 1663 : md_number_to_chars (frag_more (4), 0, 4)) 1664 1665 /* The previous insn might require a delay slot, depending upon 1666 the contents of the current insn. */ 1667 if (! mips_opts.mips16 1668 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) 1669 && ! gpr_interlocks) 1670 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) 1671 && ! cop_interlocks))) 1672 { 1673 /* A load from a coprocessor or from memory. All load 1674 delays delay the use of general register rt for one 1675 instruction. */ 1676 /* Itbl support may require additional care here. */ 1677 know (prev_pinfo & INSN_WRITE_GPR_T); 1678 if (mips_optimize == 0 1679 || insn_uses_reg (ip, 1680 ((prev_insn.insn_opcode >> OP_SH_RT) 1681 & OP_MASK_RT), 1682 MIPS_GR_REG)) 1683 ++nops; 1684 } 1685 else if (! mips_opts.mips16 1686 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) 1687 && ! cop_interlocks) 1688 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY) 1689 && ! cop_mem_interlocks))) 1690 { 1691 /* A generic coprocessor delay. The previous instruction 1692 modified a coprocessor general or control register. If 1693 it modified a control register, we need to avoid any 1694 coprocessor instruction (this is probably not always 1695 required, but it sometimes is). If it modified a general 1696 register, we avoid using that register. 1697 1698 This case is not handled very well. There is no special 1699 knowledge of CP0 handling, and the coprocessors other 1700 than the floating point unit are not distinguished at 1701 all. */ 1702 /* Itbl support may require additional care here. FIXME! 1703 Need to modify this to include knowledge about 1704 user specified delays! */ 1705 if (prev_pinfo & INSN_WRITE_FPR_T) 1706 { 1707 if (mips_optimize == 0 1708 || insn_uses_reg (ip, 1709 ((prev_insn.insn_opcode >> OP_SH_FT) 1710 & OP_MASK_FT), 1711 MIPS_FP_REG)) 1712 ++nops; 1713 } 1714 else if (prev_pinfo & INSN_WRITE_FPR_S) 1715 { 1716 if (mips_optimize == 0 1717 || insn_uses_reg (ip, 1718 ((prev_insn.insn_opcode >> OP_SH_FS) 1719 & OP_MASK_FS), 1720 MIPS_FP_REG)) 1721 ++nops; 1722 } 1723 else 1724 { 1725 /* We don't know exactly what the previous instruction 1726 does. If the current instruction uses a coprocessor 1727 register, we must insert a NOP. If previous 1728 instruction may set the condition codes, and the 1729 current instruction uses them, we must insert two 1730 NOPS. */ 1731 /* Itbl support may require additional care here. */ 1732 if (mips_optimize == 0 1733 || ((prev_pinfo & INSN_WRITE_COND_CODE) 1734 && (pinfo & INSN_READ_COND_CODE))) 1735 nops += 2; 1736 else if (pinfo & INSN_COP) 1737 ++nops; 1738 } 1739 } 1740 else if (! mips_opts.mips16 1741 && (prev_pinfo & INSN_WRITE_COND_CODE) 1742 && ! cop_interlocks) 1743 { 1744 /* The previous instruction sets the coprocessor condition 1745 codes, but does not require a general coprocessor delay 1746 (this means it is a floating point comparison 1747 instruction). If this instruction uses the condition 1748 codes, we need to insert a single NOP. */ 1749 /* Itbl support may require additional care here. */ 1750 if (mips_optimize == 0 1751 || (pinfo & INSN_READ_COND_CODE)) 1752 ++nops; 1753 } 1754 1755 /* If we're fixing up mfhi/mflo for the r7000 and the 1756 previous insn was an mfhi/mflo and the current insn 1757 reads the register that the mfhi/mflo wrote to, then 1758 insert two nops. */ 1759 1760 else if (mips_7000_hilo_fix 1761 && MF_HILO_INSN (prev_pinfo) 1762 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) 1763 & OP_MASK_RD), 1764 MIPS_GR_REG)) 1765 { 1766 nops += 2; 1767 } 1768 1769 /* If we're fixing up mfhi/mflo for the r7000 and the 1770 2nd previous insn was an mfhi/mflo and the current insn 1771 reads the register that the mfhi/mflo wrote to, then 1772 insert one nop. */ 1773 1774 else if (mips_7000_hilo_fix 1775 && MF_HILO_INSN (prev_prev_insn.insn_opcode) 1776 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) 1777 & OP_MASK_RD), 1778 MIPS_GR_REG)) 1779 1780 { 1781 ++nops; 1782 } 1783 1784 else if (prev_pinfo & INSN_READ_LO) 1785 { 1786 /* The previous instruction reads the LO register; if the 1787 current instruction writes to the LO register, we must 1788 insert two NOPS. Some newer processors have interlocks. 1789 Also the tx39's multiply instructions can be executed 1790 immediately after a read from HI/LO (without the delay), 1791 though the tx39's divide insns still do require the 1792 delay. */ 1793 if (! (hilo_interlocks 1794 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) 1795 && (mips_optimize == 0 1796 || (pinfo & INSN_WRITE_LO))) 1797 nops += 2; 1798 /* Most mips16 branch insns don't have a delay slot. 1799 If a read from LO is immediately followed by a branch 1800 to a write to LO we have a read followed by a write 1801 less than 2 insns away. We assume the target of 1802 a branch might be a write to LO, and insert a nop 1803 between a read and an immediately following branch. */ 1804 else if (mips_opts.mips16 1805 && (mips_optimize == 0 1806 || (pinfo & MIPS16_INSN_BRANCH))) 1807 ++nops; 1808 } 1809 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) 1810 { 1811 /* The previous instruction reads the HI register; if the 1812 current instruction writes to the HI register, we must 1813 insert a NOP. Some newer processors have interlocks. 1814 Also the note tx39's multiply above. */ 1815 if (! (hilo_interlocks 1816 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) 1817 && (mips_optimize == 0 1818 || (pinfo & INSN_WRITE_HI))) 1819 nops += 2; 1820 /* Most mips16 branch insns don't have a delay slot. 1821 If a read from HI is immediately followed by a branch 1822 to a write to HI we have a read followed by a write 1823 less than 2 insns away. We assume the target of 1824 a branch might be a write to HI, and insert a nop 1825 between a read and an immediately following branch. */ 1826 else if (mips_opts.mips16 1827 && (mips_optimize == 0 1828 || (pinfo & MIPS16_INSN_BRANCH))) 1829 ++nops; 1830 } 1831 1832 /* If the previous instruction was in a noreorder section, then 1833 we don't want to insert the nop after all. */ 1834 /* Itbl support may require additional care here. */ 1835 if (prev_insn_unreordered) 1836 nops = 0; 1837 1838 /* There are two cases which require two intervening 1839 instructions: 1) setting the condition codes using a move to 1840 coprocessor instruction which requires a general coprocessor 1841 delay and then reading the condition codes 2) reading the HI 1842 or LO register and then writing to it (except on processors 1843 which have interlocks). If we are not already emitting a NOP 1844 instruction, we must check for these cases compared to the 1845 instruction previous to the previous instruction. */ 1846 if ((! mips_opts.mips16 1847 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) 1848 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) 1849 && (pinfo & INSN_READ_COND_CODE) 1850 && ! cop_interlocks) 1851 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) 1852 && (pinfo & INSN_WRITE_LO) 1853 && ! (hilo_interlocks 1854 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))) 1855 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) 1856 && (pinfo & INSN_WRITE_HI) 1857 && ! (hilo_interlocks 1858 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))) 1859 prev_prev_nop = 1; 1860 else 1861 prev_prev_nop = 0; 1862 1863 if (prev_prev_insn_unreordered) 1864 prev_prev_nop = 0; 1865 1866 if (prev_prev_nop && nops == 0) 1867 ++nops; 1868 1869 if (mips_fix_vr4120 && prev_insn.insn_mo->name) 1870 { 1871 /* We're out of bits in pinfo, so we must resort to string 1872 ops here. Shortcuts are selected based on opcodes being 1873 limited to the VR4120 instruction set. */ 1874 int min_nops = 0; 1875 const char *pn = prev_insn.insn_mo->name; 1876 const char *tn = ip->insn_mo->name; 1877 if (strncmp(pn, "macc", 4) == 0 1878 || strncmp(pn, "dmacc", 5) == 0) 1879 { 1880 /* Errata 21 - [D]DIV[U] after [D]MACC */ 1881 if (strstr (tn, "div")) 1882 { 1883 min_nops = 1; 1884 } 1885 1886 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */ 1887 if (pn[0] == 'd' /* dmacc */ 1888 && (strncmp(tn, "dmult", 5) == 0 1889 || strncmp(tn, "dmacc", 5) == 0)) 1890 { 1891 min_nops = 1; 1892 } 1893 1894 /* Errata 24 - MT{LO,HI} after [D]MACC */ 1895 if (strcmp (tn, "mtlo") == 0 1896 || strcmp (tn, "mthi") == 0) 1897 { 1898 min_nops = 1; 1899 } 1900 1901 } 1902 else if (strncmp(pn, "dmult", 5) == 0 1903 && (strncmp(tn, "dmult", 5) == 0 1904 || strncmp(tn, "dmacc", 5) == 0)) 1905 { 1906 /* Here is the rest of errata 23. */ 1907 min_nops = 1; 1908 } 1909 if (nops < min_nops) 1910 nops = min_nops; 1911 } 1912 1913 /* If we are being given a nop instruction, don't bother with 1914 one of the nops we would otherwise output. This will only 1915 happen when a nop instruction is used with mips_optimize set 1916 to 0. */ 1917 if (nops > 0 1918 && ! mips_opts.noreorder 1919 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) 1920 --nops; 1921 1922 /* Now emit the right number of NOP instructions. */ 1923 if (nops > 0 && ! mips_opts.noreorder) 1924 { 1925 fragS *old_frag; 1926 unsigned long old_frag_offset; 1927 int i; 1928 struct insn_label_list *l; 1929 1930 old_frag = frag_now; 1931 old_frag_offset = frag_now_fix (); 1932 1933 for (i = 0; i < nops; i++) 1934 emit_nop (); 1935 1936 if (listing) 1937 { 1938 listing_prev_line (); 1939 /* We may be at the start of a variant frag. In case we 1940 are, make sure there is enough space for the frag 1941 after the frags created by listing_prev_line. The 1942 argument to frag_grow here must be at least as large 1943 as the argument to all other calls to frag_grow in 1944 this file. We don't have to worry about being in the 1945 middle of a variant frag, because the variants insert 1946 all needed nop instructions themselves. */ 1947 frag_grow (40); 1948 } 1949 1950 for (l = insn_labels; l != NULL; l = l->next) 1951 { 1952 valueT val; 1953 1954 assert (S_GET_SEGMENT (l->label) == now_seg); 1955 symbol_set_frag (l->label, frag_now); 1956 val = (valueT) frag_now_fix (); 1957 /* mips16 text labels are stored as odd. */ 1958 if (mips_opts.mips16) 1959 ++val; 1960 S_SET_VALUE (l->label, val); 1961 } 1962 1963#ifndef NO_ECOFF_DEBUGGING 1964 if (ECOFF_DEBUGGING) 1965 ecoff_fix_loc (old_frag, old_frag_offset); 1966#endif 1967 } 1968 else if (prev_nop_frag != NULL) 1969 { 1970 /* We have a frag holding nops we may be able to remove. If 1971 we don't need any nops, we can decrease the size of 1972 prev_nop_frag by the size of one instruction. If we do 1973 need some nops, we count them in prev_nops_required. */ 1974 if (prev_nop_frag_since == 0) 1975 { 1976 if (nops == 0) 1977 { 1978 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; 1979 --prev_nop_frag_holds; 1980 } 1981 else 1982 prev_nop_frag_required += nops; 1983 } 1984 else 1985 { 1986 if (prev_prev_nop == 0) 1987 { 1988 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; 1989 --prev_nop_frag_holds; 1990 } 1991 else 1992 ++prev_nop_frag_required; 1993 } 1994 1995 if (prev_nop_frag_holds <= prev_nop_frag_required) 1996 prev_nop_frag = NULL; 1997 1998 ++prev_nop_frag_since; 1999 2000 /* Sanity check: by the time we reach the second instruction 2001 after prev_nop_frag, we should have used up all the nops 2002 one way or another. */ 2003 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); 2004 } 2005 } 2006 2007 /* Record the frag type before frag_var. */ 2008 if (prev_insn_frag) 2009 prev_insn_frag_type = prev_insn_frag->fr_type; 2010 2011 if (address_expr 2012 && *reloc_type == BFD_RELOC_16_PCREL_S2 2013 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY 2014 || pinfo & INSN_COND_BRANCH_LIKELY) 2015 && mips_relax_branch 2016 /* Don't try branch relaxation within .set nomacro, or within 2017 .set noat if we use $at for PIC computations. If it turns 2018 out that the branch was out-of-range, we'll get an error. */ 2019 && !mips_opts.warn_about_macros 2020 && !(mips_opts.noat && mips_pic != NO_PIC) 2021 && !mips_opts.mips16) 2022 { 2023 relaxed_branch = TRUE; 2024 f = frag_var (rs_machine_dependent, 2025 relaxed_branch_length 2026 (NULL, NULL, 2027 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1 2028 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4, 2029 RELAX_BRANCH_ENCODE 2030 (pinfo & INSN_UNCOND_BRANCH_DELAY, 2031 pinfo & INSN_COND_BRANCH_LIKELY, 2032 pinfo & INSN_WRITE_GPR_31, 2033 0), 2034 address_expr->X_add_symbol, 2035 address_expr->X_add_number, 2036 0); 2037 *reloc_type = BFD_RELOC_UNUSED; 2038 } 2039 else if (*reloc_type > BFD_RELOC_UNUSED) 2040 { 2041 /* We need to set up a variant frag. */ 2042 assert (mips_opts.mips16 && address_expr != NULL); 2043 f = frag_var (rs_machine_dependent, 4, 0, 2044 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED, 2045 mips16_small, mips16_ext, 2046 (prev_pinfo 2047 & INSN_UNCOND_BRANCH_DELAY), 2048 (*prev_insn_reloc_type 2049 == BFD_RELOC_MIPS16_JMP)), 2050 make_expr_symbol (address_expr), 0, NULL); 2051 } 2052 else if (mips_opts.mips16 2053 && ! ip->use_extend 2054 && *reloc_type != BFD_RELOC_MIPS16_JMP) 2055 { 2056 /* Make sure there is enough room to swap this instruction with 2057 a following jump instruction. */ 2058 frag_grow (6); 2059 f = frag_more (2); 2060 } 2061 else 2062 { 2063 if (mips_opts.mips16 2064 && mips_opts.noreorder 2065 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) 2066 as_warn (_("extended instruction in delay slot")); 2067 2068 if (mips_relax.sequence) 2069 { 2070 /* If we've reached the end of this frag, turn it into a variant 2071 frag and record the information for the instructions we've 2072 written so far. */ 2073 if (frag_room () < 4) 2074 relax_close_frag (); 2075 mips_relax.sizes[mips_relax.sequence - 1] += 4; 2076 } 2077 2078 if (mips_relax.sequence != 2) 2079 mips_macro_warning.sizes[0] += 4; 2080 if (mips_relax.sequence != 1) 2081 mips_macro_warning.sizes[1] += 4; 2082 2083 f = frag_more (4); 2084 } 2085 2086 fixp[0] = fixp[1] = fixp[2] = NULL; 2087 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED) 2088 { 2089 if (address_expr->X_op == O_constant) 2090 { 2091 valueT tmp; 2092 2093 switch (*reloc_type) 2094 { 2095 case BFD_RELOC_32: 2096 ip->insn_opcode |= address_expr->X_add_number; 2097 break; 2098 2099 case BFD_RELOC_MIPS_HIGHEST: 2100 tmp = (address_expr->X_add_number 2101 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16; 2102 tmp >>= 16; 2103 ip->insn_opcode |= (tmp >> 16) & 0xffff; 2104 break; 2105 2106 case BFD_RELOC_MIPS_HIGHER: 2107 tmp = (address_expr->X_add_number + 0x80008000) >> 16; 2108 ip->insn_opcode |= (tmp >> 16) & 0xffff; 2109 break; 2110 2111 case BFD_RELOC_HI16_S: 2112 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000) 2113 >> 16) & 0xffff; 2114 break; 2115 2116 case BFD_RELOC_HI16: 2117 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff; 2118 break; 2119 2120 case BFD_RELOC_LO16: 2121 case BFD_RELOC_MIPS_GOT_DISP: 2122 ip->insn_opcode |= address_expr->X_add_number & 0xffff; 2123 break; 2124 2125 case BFD_RELOC_MIPS_JMP: 2126 if ((address_expr->X_add_number & 3) != 0) 2127 as_bad (_("jump to misaligned address (0x%lx)"), 2128 (unsigned long) address_expr->X_add_number); 2129 if (address_expr->X_add_number & ~0xfffffff) 2130 as_bad (_("jump address range overflow (0x%lx)"), 2131 (unsigned long) address_expr->X_add_number); 2132 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; 2133 break; 2134 2135 case BFD_RELOC_MIPS16_JMP: 2136 if ((address_expr->X_add_number & 3) != 0) 2137 as_bad (_("jump to misaligned address (0x%lx)"), 2138 (unsigned long) address_expr->X_add_number); 2139 if (address_expr->X_add_number & ~0xfffffff) 2140 as_bad (_("jump address range overflow (0x%lx)"), 2141 (unsigned long) address_expr->X_add_number); 2142 ip->insn_opcode |= 2143 (((address_expr->X_add_number & 0x7c0000) << 3) 2144 | ((address_expr->X_add_number & 0xf800000) >> 7) 2145 | ((address_expr->X_add_number & 0x3fffc) >> 2)); 2146 break; 2147 2148 case BFD_RELOC_16_PCREL_S2: 2149 goto need_reloc; 2150 2151 default: 2152 internalError (); 2153 } 2154 } 2155 else 2156 need_reloc: 2157 { 2158 reloc_howto_type *howto; 2159 int i; 2160 2161 /* In a compound relocation, it is the final (outermost) 2162 operator that determines the relocated field. */ 2163 for (i = 1; i < 3; i++) 2164 if (reloc_type[i] == BFD_RELOC_UNUSED) 2165 break; 2166 2167 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]); 2168 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal, 2169 bfd_get_reloc_size(howto), 2170 address_expr, 2171 reloc_type[0] == BFD_RELOC_16_PCREL_S2, 2172 reloc_type[0]); 2173 2174 /* These relocations can have an addend that won't fit in 2175 4 octets for 64bit assembly. */ 2176 if (HAVE_64BIT_GPRS 2177 && ! howto->partial_inplace 2178 && (reloc_type[0] == BFD_RELOC_16 2179 || reloc_type[0] == BFD_RELOC_32 2180 || reloc_type[0] == BFD_RELOC_MIPS_JMP 2181 || reloc_type[0] == BFD_RELOC_HI16_S 2182 || reloc_type[0] == BFD_RELOC_LO16 2183 || reloc_type[0] == BFD_RELOC_GPREL16 2184 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL 2185 || reloc_type[0] == BFD_RELOC_GPREL32 2186 || reloc_type[0] == BFD_RELOC_64 2187 || reloc_type[0] == BFD_RELOC_CTOR 2188 || reloc_type[0] == BFD_RELOC_MIPS_SUB 2189 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST 2190 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER 2191 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP 2192 || reloc_type[0] == BFD_RELOC_MIPS_REL16 2193 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT)) 2194 fixp[0]->fx_no_overflow = 1; 2195 2196 if (mips_relax.sequence) 2197 { 2198 if (mips_relax.first_fixup == 0) 2199 mips_relax.first_fixup = fixp[0]; 2200 } 2201 else if (reloc_needs_lo_p (*reloc_type)) 2202 { 2203 struct mips_hi_fixup *hi_fixup; 2204 2205 /* Reuse the last entry if it already has a matching %lo. */ 2206 hi_fixup = mips_hi_fixup_list; 2207 if (hi_fixup == 0 2208 || !fixup_has_matching_lo_p (hi_fixup->fixp)) 2209 { 2210 hi_fixup = ((struct mips_hi_fixup *) 2211 xmalloc (sizeof (struct mips_hi_fixup))); 2212 hi_fixup->next = mips_hi_fixup_list; 2213 mips_hi_fixup_list = hi_fixup; 2214 } 2215 hi_fixup->fixp = fixp[0]; 2216 hi_fixup->seg = now_seg; 2217 } 2218 2219 /* Add fixups for the second and third relocations, if given. 2220 Note that the ABI allows the second relocation to be 2221 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the 2222 moment we only use RSS_UNDEF, but we could add support 2223 for the others if it ever becomes necessary. */ 2224 for (i = 1; i < 3; i++) 2225 if (reloc_type[i] != BFD_RELOC_UNUSED) 2226 { 2227 address_expr->X_op = O_absent; 2228 address_expr->X_add_symbol = 0; 2229 address_expr->X_add_number = 0; 2230 2231 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where, 2232 fixp[0]->fx_size, address_expr, 2233 FALSE, reloc_type[i]); 2234 } 2235 } 2236 } 2237 2238 if (! mips_opts.mips16) 2239 { 2240 md_number_to_chars (f, ip->insn_opcode, 4); 2241#ifdef OBJ_ELF 2242 dwarf2_emit_insn (4); 2243#endif 2244 } 2245 else if (*reloc_type == BFD_RELOC_MIPS16_JMP) 2246 { 2247 md_number_to_chars (f, ip->insn_opcode >> 16, 2); 2248 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); 2249#ifdef OBJ_ELF 2250 dwarf2_emit_insn (4); 2251#endif 2252 } 2253 else 2254 { 2255 if (ip->use_extend) 2256 { 2257 md_number_to_chars (f, 0xf000 | ip->extend, 2); 2258 f += 2; 2259 } 2260 md_number_to_chars (f, ip->insn_opcode, 2); 2261#ifdef OBJ_ELF 2262 dwarf2_emit_insn (ip->use_extend ? 4 : 2); 2263#endif 2264 } 2265 2266 /* Update the register mask information. */ 2267 if (! mips_opts.mips16) 2268 { 2269 if (pinfo & INSN_WRITE_GPR_D) 2270 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); 2271 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) 2272 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); 2273 if (pinfo & INSN_READ_GPR_S) 2274 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); 2275 if (pinfo & INSN_WRITE_GPR_31) 2276 mips_gprmask |= 1 << RA; 2277 if (pinfo & INSN_WRITE_FPR_D) 2278 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); 2279 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) 2280 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); 2281 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) 2282 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); 2283 if ((pinfo & INSN_READ_FPR_R) != 0) 2284 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); 2285 if (pinfo & INSN_COP) 2286 { 2287 /* We don't keep enough information to sort these cases out. 2288 The itbl support does keep this information however, although 2289 we currently don't support itbl fprmats as part of the cop 2290 instruction. May want to add this support in the future. */ 2291 } 2292 /* Never set the bit for $0, which is always zero. */ 2293 mips_gprmask &= ~1 << 0; 2294 } 2295 else 2296 { 2297 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) 2298 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) 2299 & MIPS16OP_MASK_RX); 2300 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) 2301 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) 2302 & MIPS16OP_MASK_RY); 2303 if (pinfo & MIPS16_INSN_WRITE_Z) 2304 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) 2305 & MIPS16OP_MASK_RZ); 2306 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) 2307 mips_gprmask |= 1 << TREG; 2308 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) 2309 mips_gprmask |= 1 << SP; 2310 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) 2311 mips_gprmask |= 1 << RA; 2312 if (pinfo & MIPS16_INSN_WRITE_GPR_Y) 2313 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); 2314 if (pinfo & MIPS16_INSN_READ_Z) 2315 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) 2316 & MIPS16OP_MASK_MOVE32Z); 2317 if (pinfo & MIPS16_INSN_READ_GPR_X) 2318 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) 2319 & MIPS16OP_MASK_REGR32); 2320 } 2321 2322 if (mips_relax.sequence != 2 && !mips_opts.noreorder) 2323 { 2324 /* Filling the branch delay slot is more complex. We try to 2325 switch the branch with the previous instruction, which we can 2326 do if the previous instruction does not set up a condition 2327 that the branch tests and if the branch is not itself the 2328 target of any branch. */ 2329 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) 2330 || (pinfo & INSN_COND_BRANCH_DELAY)) 2331 { 2332 if (mips_optimize < 2 2333 /* If we have seen .set volatile or .set nomove, don't 2334 optimize. */ 2335 || mips_opts.nomove != 0 2336 /* If we had to emit any NOP instructions, then we 2337 already know we can not swap. */ 2338 || nops != 0 2339 /* If we don't even know the previous insn, we can not 2340 swap. */ 2341 || ! prev_insn_valid 2342 /* If the previous insn is already in a branch delay 2343 slot, then we can not swap. */ 2344 || prev_insn_is_delay_slot 2345 /* If the previous previous insn was in a .set 2346 noreorder, we can't swap. Actually, the MIPS 2347 assembler will swap in this situation. However, gcc 2348 configured -with-gnu-as will generate code like 2349 .set noreorder 2350 lw $4,XXX 2351 .set reorder 2352 INSN 2353 bne $4,$0,foo 2354 in which we can not swap the bne and INSN. If gcc is 2355 not configured -with-gnu-as, it does not output the 2356 .set pseudo-ops. We don't have to check 2357 prev_insn_unreordered, because prev_insn_valid will 2358 be 0 in that case. We don't want to use 2359 prev_prev_insn_valid, because we do want to be able 2360 to swap at the start of a function. */ 2361 || prev_prev_insn_unreordered 2362 /* If the branch is itself the target of a branch, we 2363 can not swap. We cheat on this; all we check for is 2364 whether there is a label on this instruction. If 2365 there are any branches to anything other than a 2366 label, users must use .set noreorder. */ 2367 || insn_labels != NULL 2368 /* If the previous instruction is in a variant frag 2369 other than this branch's one, we cannot do the swap. 2370 This does not apply to the mips16, which uses variant 2371 frags for different purposes. */ 2372 || (! mips_opts.mips16 2373 && prev_insn_frag_type == rs_machine_dependent) 2374 /* If the branch reads the condition codes, we don't 2375 even try to swap, because in the sequence 2376 ctc1 $X,$31 2377 INSN 2378 INSN 2379 bc1t LABEL 2380 we can not swap, and I don't feel like handling that 2381 case. */ 2382 || (! mips_opts.mips16 2383 && (pinfo & INSN_READ_COND_CODE) 2384 && ! cop_interlocks) 2385 /* We can not swap with an instruction that requires a 2386 delay slot, because the target of the branch might 2387 interfere with that instruction. */ 2388 || (! mips_opts.mips16 2389 && (prev_pinfo 2390 /* Itbl support may require additional care here. */ 2391 & (INSN_LOAD_COPROC_DELAY 2392 | INSN_COPROC_MOVE_DELAY 2393 | INSN_WRITE_COND_CODE)) 2394 && ! cop_interlocks) 2395 || (! (hilo_interlocks 2396 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))) 2397 && (prev_pinfo 2398 & (INSN_READ_LO 2399 | INSN_READ_HI))) 2400 || (! mips_opts.mips16 2401 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY) 2402 && ! gpr_interlocks) 2403 || (! mips_opts.mips16 2404 /* Itbl support may require additional care here. */ 2405 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY) 2406 && ! cop_mem_interlocks) 2407 /* We can not swap with a branch instruction. */ 2408 || (prev_pinfo 2409 & (INSN_UNCOND_BRANCH_DELAY 2410 | INSN_COND_BRANCH_DELAY 2411 | INSN_COND_BRANCH_LIKELY)) 2412 /* We do not swap with a trap instruction, since it 2413 complicates trap handlers to have the trap 2414 instruction be in a delay slot. */ 2415 || (prev_pinfo & INSN_TRAP) 2416 /* If the branch reads a register that the previous 2417 instruction sets, we can not swap. */ 2418 || (! mips_opts.mips16 2419 && (prev_pinfo & INSN_WRITE_GPR_T) 2420 && insn_uses_reg (ip, 2421 ((prev_insn.insn_opcode >> OP_SH_RT) 2422 & OP_MASK_RT), 2423 MIPS_GR_REG)) 2424 || (! mips_opts.mips16 2425 && (prev_pinfo & INSN_WRITE_GPR_D) 2426 && insn_uses_reg (ip, 2427 ((prev_insn.insn_opcode >> OP_SH_RD) 2428 & OP_MASK_RD), 2429 MIPS_GR_REG)) 2430 || (mips_opts.mips16 2431 && (((prev_pinfo & MIPS16_INSN_WRITE_X) 2432 && insn_uses_reg (ip, 2433 ((prev_insn.insn_opcode 2434 >> MIPS16OP_SH_RX) 2435 & MIPS16OP_MASK_RX), 2436 MIPS16_REG)) 2437 || ((prev_pinfo & MIPS16_INSN_WRITE_Y) 2438 && insn_uses_reg (ip, 2439 ((prev_insn.insn_opcode 2440 >> MIPS16OP_SH_RY) 2441 & MIPS16OP_MASK_RY), 2442 MIPS16_REG)) 2443 || ((prev_pinfo & MIPS16_INSN_WRITE_Z) 2444 && insn_uses_reg (ip, 2445 ((prev_insn.insn_opcode 2446 >> MIPS16OP_SH_RZ) 2447 & MIPS16OP_MASK_RZ), 2448 MIPS16_REG)) 2449 || ((prev_pinfo & MIPS16_INSN_WRITE_T) 2450 && insn_uses_reg (ip, TREG, MIPS_GR_REG)) 2451 || ((prev_pinfo & MIPS16_INSN_WRITE_31) 2452 && insn_uses_reg (ip, RA, MIPS_GR_REG)) 2453 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) 2454 && insn_uses_reg (ip, 2455 MIPS16OP_EXTRACT_REG32R (prev_insn. 2456 insn_opcode), 2457 MIPS_GR_REG)))) 2458 /* If the branch writes a register that the previous 2459 instruction sets, we can not swap (we know that 2460 branches write only to RD or to $31). */ 2461 || (! mips_opts.mips16 2462 && (prev_pinfo & INSN_WRITE_GPR_T) 2463 && (((pinfo & INSN_WRITE_GPR_D) 2464 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) 2465 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) 2466 || ((pinfo & INSN_WRITE_GPR_31) 2467 && (((prev_insn.insn_opcode >> OP_SH_RT) 2468 & OP_MASK_RT) 2469 == RA)))) 2470 || (! mips_opts.mips16 2471 && (prev_pinfo & INSN_WRITE_GPR_D) 2472 && (((pinfo & INSN_WRITE_GPR_D) 2473 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) 2474 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) 2475 || ((pinfo & INSN_WRITE_GPR_31) 2476 && (((prev_insn.insn_opcode >> OP_SH_RD) 2477 & OP_MASK_RD) 2478 == RA)))) 2479 || (mips_opts.mips16 2480 && (pinfo & MIPS16_INSN_WRITE_31) 2481 && ((prev_pinfo & MIPS16_INSN_WRITE_31) 2482 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) 2483 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) 2484 == RA)))) 2485 /* If the branch writes a register that the previous 2486 instruction reads, we can not swap (we know that 2487 branches only write to RD or to $31). */ 2488 || (! mips_opts.mips16 2489 && (pinfo & INSN_WRITE_GPR_D) 2490 && insn_uses_reg (&prev_insn, 2491 ((ip->insn_opcode >> OP_SH_RD) 2492 & OP_MASK_RD), 2493 MIPS_GR_REG)) 2494 || (! mips_opts.mips16 2495 && (pinfo & INSN_WRITE_GPR_31) 2496 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) 2497 || (mips_opts.mips16 2498 && (pinfo & MIPS16_INSN_WRITE_31) 2499 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) 2500 /* If we are generating embedded PIC code, the branch 2501 might be expanded into a sequence which uses $at, so 2502 we can't swap with an instruction which reads it. */ 2503 || (mips_pic == EMBEDDED_PIC 2504 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) 2505 /* If the previous previous instruction has a load 2506 delay, and sets a register that the branch reads, we 2507 can not swap. */ 2508 || (! mips_opts.mips16 2509 /* Itbl support may require additional care here. */ 2510 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) 2511 && ! cop_interlocks) 2512 || ((prev_prev_insn.insn_mo->pinfo 2513 & INSN_LOAD_MEMORY_DELAY) 2514 && ! gpr_interlocks)) 2515 && insn_uses_reg (ip, 2516 ((prev_prev_insn.insn_opcode >> OP_SH_RT) 2517 & OP_MASK_RT), 2518 MIPS_GR_REG)) 2519 /* If one instruction sets a condition code and the 2520 other one uses a condition code, we can not swap. */ 2521 || ((pinfo & INSN_READ_COND_CODE) 2522 && (prev_pinfo & INSN_WRITE_COND_CODE)) 2523 || ((pinfo & INSN_WRITE_COND_CODE) 2524 && (prev_pinfo & INSN_READ_COND_CODE)) 2525 /* If the previous instruction uses the PC, we can not 2526 swap. */ 2527 || (mips_opts.mips16 2528 && (prev_pinfo & MIPS16_INSN_READ_PC)) 2529 /* If the previous instruction was extended, we can not 2530 swap. */ 2531 || (mips_opts.mips16 && prev_insn_extended) 2532 /* If the previous instruction had a fixup in mips16 2533 mode, we can not swap. This normally means that the 2534 previous instruction was a 4 byte branch anyhow. */ 2535 || (mips_opts.mips16 && prev_insn_fixp[0]) 2536 /* If the previous instruction is a sync, sync.l, or 2537 sync.p, we can not swap. */ 2538 || (prev_pinfo & INSN_SYNC)) 2539 { 2540 /* We could do even better for unconditional branches to 2541 portions of this object file; we could pick up the 2542 instruction at the destination, put it in the delay 2543 slot, and bump the destination address. */ 2544 emit_nop (); 2545 /* Update the previous insn information. */ 2546 prev_prev_insn = *ip; 2547 prev_insn.insn_mo = &dummy_opcode; 2548 } 2549 else 2550 { 2551 /* It looks like we can actually do the swap. */ 2552 if (! mips_opts.mips16) 2553 { 2554 char *prev_f; 2555 char temp[4]; 2556 2557 prev_f = prev_insn_frag->fr_literal + prev_insn_where; 2558 if (!relaxed_branch) 2559 { 2560 /* If this is not a relaxed branch, then just 2561 swap the instructions. */ 2562 memcpy (temp, prev_f, 4); 2563 memcpy (prev_f, f, 4); 2564 memcpy (f, temp, 4); 2565 } 2566 else 2567 { 2568 /* If this is a relaxed branch, then we move the 2569 instruction to be placed in the delay slot to 2570 the current frag, shrinking the fixed part of 2571 the originating frag. If the branch occupies 2572 the tail of the latter, we move it backwards, 2573 into the space freed by the moved instruction. */ 2574 f = frag_more (4); 2575 memcpy (f, prev_f, 4); 2576 prev_insn_frag->fr_fix -= 4; 2577 if (prev_insn_frag->fr_type == rs_machine_dependent) 2578 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var); 2579 } 2580 2581 if (prev_insn_fixp[0]) 2582 { 2583 prev_insn_fixp[0]->fx_frag = frag_now; 2584 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal; 2585 } 2586 if (prev_insn_fixp[1]) 2587 { 2588 prev_insn_fixp[1]->fx_frag = frag_now; 2589 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal; 2590 } 2591 if (prev_insn_fixp[2]) 2592 { 2593 prev_insn_fixp[2]->fx_frag = frag_now; 2594 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal; 2595 } 2596 if (prev_insn_fixp[0] && HAVE_NEWABI 2597 && prev_insn_frag != frag_now 2598 && (prev_insn_fixp[0]->fx_r_type 2599 == BFD_RELOC_MIPS_GOT_DISP 2600 || (prev_insn_fixp[0]->fx_r_type 2601 == BFD_RELOC_MIPS_CALL16))) 2602 { 2603 /* To avoid confusion in tc_gen_reloc, we must 2604 ensure that this does not become a variant 2605 frag. */ 2606 force_new_frag = TRUE; 2607 } 2608 2609 if (!relaxed_branch) 2610 { 2611 if (fixp[0]) 2612 { 2613 fixp[0]->fx_frag = prev_insn_frag; 2614 fixp[0]->fx_where = prev_insn_where; 2615 } 2616 if (fixp[1]) 2617 { 2618 fixp[1]->fx_frag = prev_insn_frag; 2619 fixp[1]->fx_where = prev_insn_where; 2620 } 2621 if (fixp[2]) 2622 { 2623 fixp[2]->fx_frag = prev_insn_frag; 2624 fixp[2]->fx_where = prev_insn_where; 2625 } 2626 } 2627 else if (prev_insn_frag->fr_type == rs_machine_dependent) 2628 { 2629 if (fixp[0]) 2630 fixp[0]->fx_where -= 4; 2631 if (fixp[1]) 2632 fixp[1]->fx_where -= 4; 2633 if (fixp[2]) 2634 fixp[2]->fx_where -= 4; 2635 } 2636 } 2637 else 2638 { 2639 char *prev_f; 2640 char temp[2]; 2641 2642 assert (prev_insn_fixp[0] == NULL); 2643 assert (prev_insn_fixp[1] == NULL); 2644 assert (prev_insn_fixp[2] == NULL); 2645 prev_f = prev_insn_frag->fr_literal + prev_insn_where; 2646 memcpy (temp, prev_f, 2); 2647 memcpy (prev_f, f, 2); 2648 if (*reloc_type != BFD_RELOC_MIPS16_JMP) 2649 { 2650 assert (*reloc_type == BFD_RELOC_UNUSED); 2651 memcpy (f, temp, 2); 2652 } 2653 else 2654 { 2655 memcpy (f, f + 2, 2); 2656 memcpy (f + 2, temp, 2); 2657 } 2658 if (fixp[0]) 2659 { 2660 fixp[0]->fx_frag = prev_insn_frag; 2661 fixp[0]->fx_where = prev_insn_where; 2662 } 2663 if (fixp[1]) 2664 { 2665 fixp[1]->fx_frag = prev_insn_frag; 2666 fixp[1]->fx_where = prev_insn_where; 2667 } 2668 if (fixp[2]) 2669 { 2670 fixp[2]->fx_frag = prev_insn_frag; 2671 fixp[2]->fx_where = prev_insn_where; 2672 } 2673 } 2674 2675 /* Update the previous insn information; leave prev_insn 2676 unchanged. */ 2677 prev_prev_insn = *ip; 2678 } 2679 prev_insn_is_delay_slot = 1; 2680 2681 /* If that was an unconditional branch, forget the previous 2682 insn information. */ 2683 if (pinfo & INSN_UNCOND_BRANCH_DELAY) 2684 { 2685 prev_prev_insn.insn_mo = &dummy_opcode; 2686 prev_insn.insn_mo = &dummy_opcode; 2687 } 2688 2689 prev_insn_fixp[0] = NULL; 2690 prev_insn_fixp[1] = NULL; 2691 prev_insn_fixp[2] = NULL; 2692 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; 2693 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; 2694 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; 2695 prev_insn_extended = 0; 2696 } 2697 else if (pinfo & INSN_COND_BRANCH_LIKELY) 2698 { 2699 /* We don't yet optimize a branch likely. What we should do 2700 is look at the target, copy the instruction found there 2701 into the delay slot, and increment the branch to jump to 2702 the next instruction. */ 2703 emit_nop (); 2704 /* Update the previous insn information. */ 2705 prev_prev_insn = *ip; 2706 prev_insn.insn_mo = &dummy_opcode; 2707 prev_insn_fixp[0] = NULL; 2708 prev_insn_fixp[1] = NULL; 2709 prev_insn_fixp[2] = NULL; 2710 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; 2711 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; 2712 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; 2713 prev_insn_extended = 0; 2714 } 2715 else 2716 { 2717 /* Update the previous insn information. */ 2718 if (nops > 0) 2719 prev_prev_insn.insn_mo = &dummy_opcode; 2720 else 2721 prev_prev_insn = prev_insn; 2722 prev_insn = *ip; 2723 2724 /* Any time we see a branch, we always fill the delay slot 2725 immediately; since this insn is not a branch, we know it 2726 is not in a delay slot. */ 2727 prev_insn_is_delay_slot = 0; 2728 2729 prev_insn_fixp[0] = fixp[0]; 2730 prev_insn_fixp[1] = fixp[1]; 2731 prev_insn_fixp[2] = fixp[2]; 2732 prev_insn_reloc_type[0] = reloc_type[0]; 2733 prev_insn_reloc_type[1] = reloc_type[1]; 2734 prev_insn_reloc_type[2] = reloc_type[2]; 2735 if (mips_opts.mips16) 2736 prev_insn_extended = (ip->use_extend 2737 || *reloc_type > BFD_RELOC_UNUSED); 2738 } 2739 2740 prev_prev_insn_unreordered = prev_insn_unreordered; 2741 prev_insn_unreordered = 0; 2742 prev_insn_frag = frag_now; 2743 prev_insn_where = f - frag_now->fr_literal; 2744 prev_insn_valid = 1; 2745 } 2746 else if (mips_relax.sequence != 2) 2747 { 2748 /* We need to record a bit of information even when we are not 2749 reordering, in order to determine the base address for mips16 2750 PC relative relocs. */ 2751 prev_prev_insn = prev_insn; 2752 prev_insn = *ip; 2753 prev_insn_reloc_type[0] = reloc_type[0]; 2754 prev_insn_reloc_type[1] = reloc_type[1]; 2755 prev_insn_reloc_type[2] = reloc_type[2]; 2756 prev_prev_insn_unreordered = prev_insn_unreordered; 2757 prev_insn_unreordered = 1; 2758 } 2759 2760 /* We just output an insn, so the next one doesn't have a label. */ 2761 mips_clear_insn_labels (); 2762} 2763 2764/* This function forgets that there was any previous instruction or 2765 label. If PRESERVE is non-zero, it remembers enough information to 2766 know whether nops are needed before a noreorder section. */ 2767 2768static void 2769mips_no_prev_insn (int preserve) 2770{ 2771 if (! preserve) 2772 { 2773 prev_insn.insn_mo = &dummy_opcode; 2774 prev_prev_insn.insn_mo = &dummy_opcode; 2775 prev_nop_frag = NULL; 2776 prev_nop_frag_holds = 0; 2777 prev_nop_frag_required = 0; 2778 prev_nop_frag_since = 0; 2779 } 2780 prev_insn_valid = 0; 2781 prev_insn_is_delay_slot = 0; 2782 prev_insn_unreordered = 0; 2783 prev_insn_extended = 0; 2784 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED; 2785 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED; 2786 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED; 2787 prev_prev_insn_unreordered = 0; 2788 mips_clear_insn_labels (); 2789} 2790 2791/* This function must be called whenever we turn on noreorder or emit 2792 something other than instructions. It inserts any NOPS which might 2793 be needed by the previous instruction, and clears the information 2794 kept for the previous instructions. The INSNS parameter is true if 2795 instructions are to follow. */ 2796 2797static void 2798mips_emit_delays (bfd_boolean insns) 2799{ 2800 if (! mips_opts.noreorder) 2801 { 2802 int nops; 2803 2804 nops = 0; 2805 if ((! mips_opts.mips16 2806 && ((prev_insn.insn_mo->pinfo 2807 & (INSN_LOAD_COPROC_DELAY 2808 | INSN_COPROC_MOVE_DELAY 2809 | INSN_WRITE_COND_CODE)) 2810 && ! cop_interlocks)) 2811 || (! hilo_interlocks 2812 && (prev_insn.insn_mo->pinfo 2813 & (INSN_READ_LO 2814 | INSN_READ_HI))) 2815 || (! mips_opts.mips16 2816 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY) 2817 && ! gpr_interlocks) 2818 || (! mips_opts.mips16 2819 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY) 2820 && ! cop_mem_interlocks)) 2821 { 2822 /* Itbl support may require additional care here. */ 2823 ++nops; 2824 if ((! mips_opts.mips16 2825 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) 2826 && ! cop_interlocks)) 2827 || (! hilo_interlocks 2828 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) 2829 || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) 2830 ++nops; 2831 2832 if (prev_insn_unreordered) 2833 nops = 0; 2834 } 2835 else if ((! mips_opts.mips16 2836 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) 2837 && ! cop_interlocks)) 2838 || (! hilo_interlocks 2839 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) 2840 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) 2841 { 2842 /* Itbl support may require additional care here. */ 2843 if (! prev_prev_insn_unreordered) 2844 ++nops; 2845 } 2846 2847 if (mips_fix_vr4120 && prev_insn.insn_mo->name) 2848 { 2849 int min_nops = 0; 2850 const char *pn = prev_insn.insn_mo->name; 2851 if (strncmp(pn, "macc", 4) == 0 2852 || strncmp(pn, "dmacc", 5) == 0 2853 || strncmp(pn, "dmult", 5) == 0) 2854 { 2855 min_nops = 1; 2856 } 2857 if (nops < min_nops) 2858 nops = min_nops; 2859 } 2860 2861 if (nops > 0) 2862 { 2863 struct insn_label_list *l; 2864 2865 if (insns) 2866 { 2867 /* Record the frag which holds the nop instructions, so 2868 that we can remove them if we don't need them. */ 2869 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); 2870 prev_nop_frag = frag_now; 2871 prev_nop_frag_holds = nops; 2872 prev_nop_frag_required = 0; 2873 prev_nop_frag_since = 0; 2874 } 2875 2876 for (; nops > 0; --nops) 2877 emit_nop (); 2878 2879 if (insns) 2880 { 2881 /* Move on to a new frag, so that it is safe to simply 2882 decrease the size of prev_nop_frag. */ 2883 frag_wane (frag_now); 2884 frag_new (0); 2885 } 2886 2887 for (l = insn_labels; l != NULL; l = l->next) 2888 { 2889 valueT val; 2890 2891 assert (S_GET_SEGMENT (l->label) == now_seg); 2892 symbol_set_frag (l->label, frag_now); 2893 val = (valueT) frag_now_fix (); 2894 /* mips16 text labels are stored as odd. */ 2895 if (mips_opts.mips16) 2896 ++val; 2897 S_SET_VALUE (l->label, val); 2898 } 2899 } 2900 } 2901 2902 /* Mark instruction labels in mips16 mode. */ 2903 if (insns) 2904 mips16_mark_labels (); 2905 2906 mips_no_prev_insn (insns); 2907} 2908 2909/* Set up global variables for the start of a new macro. */ 2910 2911static void 2912macro_start (void) 2913{ 2914 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); 2915 mips_macro_warning.delay_slot_p = (mips_opts.noreorder 2916 && (prev_insn.insn_mo->pinfo 2917 & (INSN_UNCOND_BRANCH_DELAY 2918 | INSN_COND_BRANCH_DELAY 2919 | INSN_COND_BRANCH_LIKELY)) != 0); 2920} 2921 2922/* Given that a macro is longer than 4 bytes, return the appropriate warning 2923 for it. Return null if no warning is needed. SUBTYPE is a bitmask of 2924 RELAX_DELAY_SLOT and RELAX_NOMACRO. */ 2925 2926static const char * 2927macro_warning (relax_substateT subtype) 2928{ 2929 if (subtype & RELAX_DELAY_SLOT) 2930 return _("Macro instruction expanded into multiple instructions" 2931 " in a branch delay slot"); 2932 else if (subtype & RELAX_NOMACRO) 2933 return _("Macro instruction expanded into multiple instructions"); 2934 else 2935 return 0; 2936} 2937 2938/* Finish up a macro. Emit warnings as appropriate. */ 2939 2940static void 2941macro_end (void) 2942{ 2943 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4) 2944 { 2945 relax_substateT subtype; 2946 2947 /* Set up the relaxation warning flags. */ 2948 subtype = 0; 2949 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0]) 2950 subtype |= RELAX_SECOND_LONGER; 2951 if (mips_opts.warn_about_macros) 2952 subtype |= RELAX_NOMACRO; 2953 if (mips_macro_warning.delay_slot_p) 2954 subtype |= RELAX_DELAY_SLOT; 2955 2956 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4) 2957 { 2958 /* Either the macro has a single implementation or both 2959 implementations are longer than 4 bytes. Emit the 2960 warning now. */ 2961 const char *msg = macro_warning (subtype); 2962 if (msg != 0) 2963 as_warn (msg); 2964 } 2965 else 2966 { 2967 /* One implementation might need a warning but the other 2968 definitely doesn't. */ 2969 mips_macro_warning.first_frag->fr_subtype |= subtype; 2970 } 2971 } 2972} 2973 2974/* Build an instruction created by a macro expansion. This is passed 2975 a pointer to the count of instructions created so far, an 2976 expression, the name of the instruction to build, an operand format 2977 string, and corresponding arguments. */ 2978 2979static void 2980macro_build (expressionS *ep, const char *name, const char *fmt, ...) 2981{ 2982 struct mips_cl_insn insn; 2983 bfd_reloc_code_real_type r[3]; 2984 va_list args; 2985 2986 va_start (args, fmt); 2987 2988 if (mips_opts.mips16) 2989 { 2990 mips16_macro_build (ep, name, fmt, args); 2991 va_end (args); 2992 return; 2993 } 2994 2995 r[0] = BFD_RELOC_UNUSED; 2996 r[1] = BFD_RELOC_UNUSED; 2997 r[2] = BFD_RELOC_UNUSED; 2998 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); 2999 assert (insn.insn_mo); 3000 assert (strcmp (name, insn.insn_mo->name) == 0); 3001 3002 /* Search until we get a match for NAME. */ 3003 while (1) 3004 { 3005 /* It is assumed here that macros will never generate 3006 MDMX or MIPS-3D instructions. */ 3007 if (strcmp (fmt, insn.insn_mo->args) == 0 3008 && insn.insn_mo->pinfo != INSN_MACRO 3009 && OPCODE_IS_MEMBER (insn.insn_mo, 3010 (mips_opts.isa 3011 | (file_ase_mips16 ? INSN_MIPS16 : 0)), 3012 mips_opts.arch) 3013 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) 3014 break; 3015 3016 ++insn.insn_mo; 3017 assert (insn.insn_mo->name); 3018 assert (strcmp (name, insn.insn_mo->name) == 0); 3019 } 3020 3021 insn.insn_opcode = insn.insn_mo->match; 3022 for (;;) 3023 { 3024 switch (*fmt++) 3025 { 3026 case '\0': 3027 break; 3028 3029 case ',': 3030 case '(': 3031 case ')': 3032 continue; 3033 3034 case '+': 3035 switch (*fmt++) 3036 { 3037 case 'A': 3038 case 'E': 3039 insn.insn_opcode |= (va_arg (args, int) 3040 & OP_MASK_SHAMT) << OP_SH_SHAMT; 3041 continue; 3042 3043 case 'B': 3044 case 'F': 3045 /* Note that in the macro case, these arguments are already 3046 in MSB form. (When handling the instruction in the 3047 non-macro case, these arguments are sizes from which 3048 MSB values must be calculated.) */ 3049 insn.insn_opcode |= (va_arg (args, int) 3050 & OP_MASK_INSMSB) << OP_SH_INSMSB; 3051 continue; 3052 3053 case 'C': 3054 case 'G': 3055 case 'H': 3056 /* Note that in the macro case, these arguments are already 3057 in MSBD form. (When handling the instruction in the 3058 non-macro case, these arguments are sizes from which 3059 MSBD values must be calculated.) */ 3060 insn.insn_opcode |= (va_arg (args, int) 3061 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; 3062 continue; 3063 3064 default: 3065 internalError (); 3066 } 3067 continue; 3068 3069 case 't': 3070 case 'w': 3071 case 'E': 3072 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; 3073 continue; 3074 3075 case 'c': 3076 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; 3077 continue; 3078 3079 case 'T': 3080 case 'W': 3081 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; 3082 continue; 3083 3084 case 'd': 3085 case 'G': 3086 case 'K': 3087 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; 3088 continue; 3089 3090 case 'U': 3091 { 3092 int tmp = va_arg (args, int); 3093 3094 insn.insn_opcode |= tmp << OP_SH_RT; 3095 insn.insn_opcode |= tmp << OP_SH_RD; 3096 continue; 3097 } 3098 3099 case 'V': 3100 case 'S': 3101 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; 3102 continue; 3103 3104 case 'z': 3105 continue; 3106 3107 case '<': 3108 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; 3109 continue; 3110 3111 case 'D': 3112 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; 3113 continue; 3114 3115 case 'B': 3116 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; 3117 continue; 3118 3119 case 'J': 3120 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; 3121 continue; 3122 3123 case 'q': 3124 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; 3125 continue; 3126 3127 case 'b': 3128 case 's': 3129 case 'r': 3130 case 'v': 3131 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; 3132 continue; 3133 3134 case 'i': 3135 case 'j': 3136 case 'o': 3137 *r = (bfd_reloc_code_real_type) va_arg (args, int); 3138 assert (*r == BFD_RELOC_GPREL16 3139 || *r == BFD_RELOC_MIPS_LITERAL 3140 || *r == BFD_RELOC_MIPS_HIGHER 3141 || *r == BFD_RELOC_HI16_S 3142 || *r == BFD_RELOC_LO16 3143 || *r == BFD_RELOC_MIPS_GOT16 3144 || *r == BFD_RELOC_MIPS_CALL16 3145 || *r == BFD_RELOC_MIPS_GOT_DISP 3146 || *r == BFD_RELOC_MIPS_GOT_PAGE 3147 || *r == BFD_RELOC_MIPS_GOT_OFST 3148 || *r == BFD_RELOC_MIPS_GOT_LO16 3149 || *r == BFD_RELOC_MIPS_CALL_LO16 3150 || (ep->X_op == O_subtract 3151 && *r == BFD_RELOC_PCREL_LO16)); 3152 continue; 3153 3154 case 'u': 3155 *r = (bfd_reloc_code_real_type) va_arg (args, int); 3156 assert (ep != NULL 3157 && (ep->X_op == O_constant 3158 || (ep->X_op == O_symbol 3159 && (*r == BFD_RELOC_MIPS_HIGHEST 3160 || *r == BFD_RELOC_HI16_S 3161 || *r == BFD_RELOC_HI16 3162 || *r == BFD_RELOC_GPREL16 3163 || *r == BFD_RELOC_MIPS_GOT_HI16 3164 || *r == BFD_RELOC_MIPS_CALL_HI16)) 3165 || (ep->X_op == O_subtract 3166 && *r == BFD_RELOC_PCREL_HI16_S))); 3167 continue; 3168 3169 case 'p': 3170 assert (ep != NULL); 3171 /* 3172 * This allows macro() to pass an immediate expression for 3173 * creating short branches without creating a symbol. 3174 * Note that the expression still might come from the assembly 3175 * input, in which case the value is not checked for range nor 3176 * is a relocation entry generated (yuck). 3177 */ 3178 if (ep->X_op == O_constant) 3179 { 3180 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; 3181 ep = NULL; 3182 } 3183 else 3184 *r = BFD_RELOC_16_PCREL_S2; 3185 continue; 3186 3187 case 'a': 3188 assert (ep != NULL); 3189 *r = BFD_RELOC_MIPS_JMP; 3190 continue; 3191 3192 case 'C': 3193 insn.insn_opcode |= va_arg (args, unsigned long); 3194 continue; 3195 3196 default: 3197 internalError (); 3198 } 3199 break; 3200 } 3201 va_end (args); 3202 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 3203 3204 append_insn (&insn, ep, r); 3205} 3206 3207static void 3208mips16_macro_build (expressionS *ep, const char *name, const char *fmt, 3209 va_list args) 3210{ 3211 struct mips_cl_insn insn; 3212 bfd_reloc_code_real_type r[3] 3213 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 3214 3215 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); 3216 assert (insn.insn_mo); 3217 assert (strcmp (name, insn.insn_mo->name) == 0); 3218 3219 while (strcmp (fmt, insn.insn_mo->args) != 0 3220 || insn.insn_mo->pinfo == INSN_MACRO) 3221 { 3222 ++insn.insn_mo; 3223 assert (insn.insn_mo->name); 3224 assert (strcmp (name, insn.insn_mo->name) == 0); 3225 } 3226 3227 insn.insn_opcode = insn.insn_mo->match; 3228 insn.use_extend = FALSE; 3229 3230 for (;;) 3231 { 3232 int c; 3233 3234 c = *fmt++; 3235 switch (c) 3236 { 3237 case '\0': 3238 break; 3239 3240 case ',': 3241 case '(': 3242 case ')': 3243 continue; 3244 3245 case 'y': 3246 case 'w': 3247 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; 3248 continue; 3249 3250 case 'x': 3251 case 'v': 3252 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; 3253 continue; 3254 3255 case 'z': 3256 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; 3257 continue; 3258 3259 case 'Z': 3260 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; 3261 continue; 3262 3263 case '0': 3264 case 'S': 3265 case 'P': 3266 case 'R': 3267 continue; 3268 3269 case 'X': 3270 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; 3271 continue; 3272 3273 case 'Y': 3274 { 3275 int regno; 3276 3277 regno = va_arg (args, int); 3278 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); 3279 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; 3280 } 3281 continue; 3282 3283 case '<': 3284 case '>': 3285 case '4': 3286 case '5': 3287 case 'H': 3288 case 'W': 3289 case 'D': 3290 case 'j': 3291 case '8': 3292 case 'V': 3293 case 'C': 3294 case 'U': 3295 case 'k': 3296 case 'K': 3297 case 'p': 3298 case 'q': 3299 { 3300 assert (ep != NULL); 3301 3302 if (ep->X_op != O_constant) 3303 *r = (int) BFD_RELOC_UNUSED + c; 3304 else 3305 { 3306 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE, 3307 FALSE, &insn.insn_opcode, &insn.use_extend, 3308 &insn.extend); 3309 ep = NULL; 3310 *r = BFD_RELOC_UNUSED; 3311 } 3312 } 3313 continue; 3314 3315 case '6': 3316 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; 3317 continue; 3318 } 3319 3320 break; 3321 } 3322 3323 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 3324 3325 append_insn (&insn, ep, r); 3326} 3327 3328/* 3329 * Generate a "jalr" instruction with a relocation hint to the called 3330 * function. This occurs in NewABI PIC code. 3331 */ 3332static void 3333macro_build_jalr (expressionS *ep) 3334{ 3335 char *f = NULL; 3336 3337 if (HAVE_NEWABI) 3338 { 3339 frag_grow (8); 3340 f = frag_more (0); 3341 } 3342 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); 3343 if (HAVE_NEWABI) 3344 fix_new_exp (frag_now, f - frag_now->fr_literal, 3345 4, ep, FALSE, BFD_RELOC_MIPS_JALR); 3346} 3347 3348/* 3349 * Generate a "lui" instruction. 3350 */ 3351static void 3352macro_build_lui (expressionS *ep, int regnum) 3353{ 3354 expressionS high_expr; 3355 struct mips_cl_insn insn; 3356 bfd_reloc_code_real_type r[3] 3357 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; 3358 const char *name = "lui"; 3359 const char *fmt = "t,u"; 3360 3361 assert (! mips_opts.mips16); 3362 3363 high_expr = *ep; 3364 3365 if (high_expr.X_op == O_constant) 3366 { 3367 /* we can compute the instruction now without a relocation entry */ 3368 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) 3369 >> 16) & 0xffff; 3370 *r = BFD_RELOC_UNUSED; 3371 } 3372 else 3373 { 3374 assert (ep->X_op == O_symbol); 3375 /* _gp_disp is a special case, used from s_cpload. */ 3376 assert (mips_pic == NO_PIC 3377 || (! HAVE_NEWABI 3378 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)); 3379 *r = BFD_RELOC_HI16_S; 3380 } 3381 3382 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); 3383 assert (insn.insn_mo); 3384 assert (strcmp (name, insn.insn_mo->name) == 0); 3385 assert (strcmp (fmt, insn.insn_mo->args) == 0); 3386 3387 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); 3388 if (*r == BFD_RELOC_UNUSED) 3389 { 3390 insn.insn_opcode |= high_expr.X_add_number; 3391 append_insn (&insn, NULL, r); 3392 } 3393 else 3394 append_insn (&insn, &high_expr, r); 3395} 3396 3397/* Generate a sequence of instructions to do a load or store from a constant 3398 offset off of a base register (breg) into/from a target register (treg), 3399 using AT if necessary. */ 3400static void 3401macro_build_ldst_constoffset (expressionS *ep, const char *op, 3402 int treg, int breg, int dbl) 3403{ 3404 assert (ep->X_op == O_constant); 3405 3406 /* Sign-extending 32-bit constants makes their handling easier. */ 3407 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) 3408 == ~((bfd_vma) 0x7fffffff))) 3409 { 3410 if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) 3411 as_bad (_("constant too large")); 3412 3413 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) 3414 - 0x80000000); 3415 } 3416 3417 /* Right now, this routine can only handle signed 32-bit constants. */ 3418 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) 3419 as_warn (_("operand overflow")); 3420 3421 if (IS_SEXT_16BIT_NUM(ep->X_add_number)) 3422 { 3423 /* Signed 16-bit offset will fit in the op. Easy! */ 3424 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); 3425 } 3426 else 3427 { 3428 /* 32-bit offset, need multiple instructions and AT, like: 3429 lui $tempreg,const_hi (BFD_RELOC_HI16_S) 3430 addu $tempreg,$tempreg,$breg 3431 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) 3432 to handle the complete offset. */ 3433 macro_build_lui (ep, AT); 3434 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 3435 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); 3436 3437 if (mips_opts.noat) 3438 as_warn (_("Macro used $at after \".set noat\"")); 3439 } 3440} 3441 3442/* set_at() 3443 * Generates code to set the $at register to true (one) 3444 * if reg is less than the immediate expression. 3445 */ 3446static void 3447set_at (int reg, int unsignedp) 3448{ 3449 if (imm_expr.X_op == O_constant 3450 && imm_expr.X_add_number >= -0x8000 3451 && imm_expr.X_add_number < 0x8000) 3452 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", 3453 AT, reg, BFD_RELOC_LO16); 3454 else 3455 { 3456 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 3457 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); 3458 } 3459} 3460 3461static void 3462normalize_constant_expr (expressionS *ex) 3463{ 3464 if (ex->X_op == O_constant && HAVE_32BIT_GPRS) 3465 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 3466 - 0x80000000); 3467} 3468 3469/* Warn if an expression is not a constant. */ 3470 3471static void 3472check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex) 3473{ 3474 if (ex->X_op == O_big) 3475 as_bad (_("unsupported large constant")); 3476 else if (ex->X_op != O_constant) 3477 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); 3478 3479 normalize_constant_expr (ex); 3480} 3481 3482/* Count the leading zeroes by performing a binary chop. This is a 3483 bulky bit of source, but performance is a LOT better for the 3484 majority of values than a simple loop to count the bits: 3485 for (lcnt = 0; (lcnt < 32); lcnt++) 3486 if ((v) & (1 << (31 - lcnt))) 3487 break; 3488 However it is not code size friendly, and the gain will drop a bit 3489 on certain cached systems. 3490*/ 3491#define COUNT_TOP_ZEROES(v) \ 3492 (((v) & ~0xffff) == 0 \ 3493 ? ((v) & ~0xff) == 0 \ 3494 ? ((v) & ~0xf) == 0 \ 3495 ? ((v) & ~0x3) == 0 \ 3496 ? ((v) & ~0x1) == 0 \ 3497 ? !(v) \ 3498 ? 32 \ 3499 : 31 \ 3500 : 30 \ 3501 : ((v) & ~0x7) == 0 \ 3502 ? 29 \ 3503 : 28 \ 3504 : ((v) & ~0x3f) == 0 \ 3505 ? ((v) & ~0x1f) == 0 \ 3506 ? 27 \ 3507 : 26 \ 3508 : ((v) & ~0x7f) == 0 \ 3509 ? 25 \ 3510 : 24 \ 3511 : ((v) & ~0xfff) == 0 \ 3512 ? ((v) & ~0x3ff) == 0 \ 3513 ? ((v) & ~0x1ff) == 0 \ 3514 ? 23 \ 3515 : 22 \ 3516 : ((v) & ~0x7ff) == 0 \ 3517 ? 21 \ 3518 : 20 \ 3519 : ((v) & ~0x3fff) == 0 \ 3520 ? ((v) & ~0x1fff) == 0 \ 3521 ? 19 \ 3522 : 18 \ 3523 : ((v) & ~0x7fff) == 0 \ 3524 ? 17 \ 3525 : 16 \ 3526 : ((v) & ~0xffffff) == 0 \ 3527 ? ((v) & ~0xfffff) == 0 \ 3528 ? ((v) & ~0x3ffff) == 0 \ 3529 ? ((v) & ~0x1ffff) == 0 \ 3530 ? 15 \ 3531 : 14 \ 3532 : ((v) & ~0x7ffff) == 0 \ 3533 ? 13 \ 3534 : 12 \ 3535 : ((v) & ~0x3fffff) == 0 \ 3536 ? ((v) & ~0x1fffff) == 0 \ 3537 ? 11 \ 3538 : 10 \ 3539 : ((v) & ~0x7fffff) == 0 \ 3540 ? 9 \ 3541 : 8 \ 3542 : ((v) & ~0xfffffff) == 0 \ 3543 ? ((v) & ~0x3ffffff) == 0 \ 3544 ? ((v) & ~0x1ffffff) == 0 \ 3545 ? 7 \ 3546 : 6 \ 3547 : ((v) & ~0x7ffffff) == 0 \ 3548 ? 5 \ 3549 : 4 \ 3550 : ((v) & ~0x3fffffff) == 0 \ 3551 ? ((v) & ~0x1fffffff) == 0 \ 3552 ? 3 \ 3553 : 2 \ 3554 : ((v) & ~0x7fffffff) == 0 \ 3555 ? 1 \ 3556 : 0) 3557 3558/* load_register() 3559 * This routine generates the least number of instructions necessary to load 3560 * an absolute expression value into a register. 3561 */ 3562static void 3563load_register (int reg, expressionS *ep, int dbl) 3564{ 3565 int freg; 3566 expressionS hi32, lo32; 3567 3568 if (ep->X_op != O_big) 3569 { 3570 assert (ep->X_op == O_constant); 3571 3572 /* Sign-extending 32-bit constants makes their handling easier. */ 3573 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff)) 3574 == ~((bfd_vma) 0x7fffffff))) 3575 { 3576 if (ep->X_add_number & ~((bfd_vma) 0xffffffff)) 3577 as_bad (_("constant too large")); 3578 3579 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000) 3580 - 0x80000000); 3581 } 3582 3583 if (IS_SEXT_16BIT_NUM (ep->X_add_number)) 3584 { 3585 /* We can handle 16 bit signed values with an addiu to 3586 $zero. No need to ever use daddiu here, since $zero and 3587 the result are always correct in 32 bit mode. */ 3588 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 3589 return; 3590 } 3591 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) 3592 { 3593 /* We can handle 16 bit unsigned values with an ori to 3594 $zero. */ 3595 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 3596 return; 3597 } 3598 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) 3599 { 3600 /* 32 bit values require an lui. */ 3601 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16); 3602 if ((ep->X_add_number & 0xffff) != 0) 3603 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 3604 return; 3605 } 3606 } 3607 3608 /* The value is larger than 32 bits. */ 3609 3610 if (HAVE_32BIT_GPRS) 3611 { 3612 as_bad (_("Number (0x%lx) larger than 32 bits"), 3613 (unsigned long) ep->X_add_number); 3614 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 3615 return; 3616 } 3617 3618 if (ep->X_op != O_big) 3619 { 3620 hi32 = *ep; 3621 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 3622 hi32.X_add_number = (valueT) hi32.X_add_number >> 16; 3623 hi32.X_add_number &= 0xffffffff; 3624 lo32 = *ep; 3625 lo32.X_add_number &= 0xffffffff; 3626 } 3627 else 3628 { 3629 assert (ep->X_add_number > 2); 3630 if (ep->X_add_number == 3) 3631 generic_bignum[3] = 0; 3632 else if (ep->X_add_number > 4) 3633 as_bad (_("Number larger than 64 bits")); 3634 lo32.X_op = O_constant; 3635 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); 3636 hi32.X_op = O_constant; 3637 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); 3638 } 3639 3640 if (hi32.X_add_number == 0) 3641 freg = 0; 3642 else 3643 { 3644 int shift, bit; 3645 unsigned long hi, lo; 3646 3647 if (hi32.X_add_number == (offsetT) 0xffffffff) 3648 { 3649 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) 3650 { 3651 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 3652 return; 3653 } 3654 if (lo32.X_add_number & 0x80000000) 3655 { 3656 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); 3657 if (lo32.X_add_number & 0xffff) 3658 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); 3659 return; 3660 } 3661 } 3662 3663 /* Check for 16bit shifted constant. We know that hi32 is 3664 non-zero, so start the mask on the first bit of the hi32 3665 value. */ 3666 shift = 17; 3667 do 3668 { 3669 unsigned long himask, lomask; 3670 3671 if (shift < 32) 3672 { 3673 himask = 0xffff >> (32 - shift); 3674 lomask = (0xffff << shift) & 0xffffffff; 3675 } 3676 else 3677 { 3678 himask = 0xffff << (shift - 32); 3679 lomask = 0; 3680 } 3681 if ((hi32.X_add_number & ~(offsetT) himask) == 0 3682 && (lo32.X_add_number & ~(offsetT) lomask) == 0) 3683 { 3684 expressionS tmp; 3685 3686 tmp.X_op = O_constant; 3687 if (shift < 32) 3688 tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) 3689 | (lo32.X_add_number >> shift)); 3690 else 3691 tmp.X_add_number = hi32.X_add_number >> (shift - 32); 3692 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); 3693 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<", 3694 reg, reg, (shift >= 32) ? shift - 32 : shift); 3695 return; 3696 } 3697 ++shift; 3698 } 3699 while (shift <= (64 - 16)); 3700 3701 /* Find the bit number of the lowest one bit, and store the 3702 shifted value in hi/lo. */ 3703 hi = (unsigned long) (hi32.X_add_number & 0xffffffff); 3704 lo = (unsigned long) (lo32.X_add_number & 0xffffffff); 3705 if (lo != 0) 3706 { 3707 bit = 0; 3708 while ((lo & 1) == 0) 3709 { 3710 lo >>= 1; 3711 ++bit; 3712 } 3713 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); 3714 hi >>= bit; 3715 } 3716 else 3717 { 3718 bit = 32; 3719 while ((hi & 1) == 0) 3720 { 3721 hi >>= 1; 3722 ++bit; 3723 } 3724 lo = hi; 3725 hi = 0; 3726 } 3727 3728 /* Optimize if the shifted value is a (power of 2) - 1. */ 3729 if ((hi == 0 && ((lo + 1) & lo) == 0) 3730 || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) 3731 { 3732 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); 3733 if (shift != 0) 3734 { 3735 expressionS tmp; 3736 3737 /* This instruction will set the register to be all 3738 ones. */ 3739 tmp.X_op = O_constant; 3740 tmp.X_add_number = (offsetT) -1; 3741 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); 3742 if (bit != 0) 3743 { 3744 bit += shift; 3745 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<", 3746 reg, reg, (bit >= 32) ? bit - 32 : bit); 3747 } 3748 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<", 3749 reg, reg, (shift >= 32) ? shift - 32 : shift); 3750 return; 3751 } 3752 } 3753 3754 /* Sign extend hi32 before calling load_register, because we can 3755 generally get better code when we load a sign extended value. */ 3756 if ((hi32.X_add_number & 0x80000000) != 0) 3757 hi32.X_add_number |= ~(offsetT) 0xffffffff; 3758 load_register (reg, &hi32, 0); 3759 freg = reg; 3760 } 3761 if ((lo32.X_add_number & 0xffff0000) == 0) 3762 { 3763 if (freg != 0) 3764 { 3765 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0); 3766 freg = reg; 3767 } 3768 } 3769 else 3770 { 3771 expressionS mid16; 3772 3773 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) 3774 { 3775 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16); 3776 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0); 3777 return; 3778 } 3779 3780 if (freg != 0) 3781 { 3782 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16); 3783 freg = reg; 3784 } 3785 mid16 = lo32; 3786 mid16.X_add_number >>= 16; 3787 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 3788 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); 3789 freg = reg; 3790 } 3791 if ((lo32.X_add_number & 0xffff) != 0) 3792 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); 3793} 3794 3795/* Load an address into a register. */ 3796 3797static void 3798load_address (int reg, expressionS *ep, int *used_at) 3799{ 3800 if (ep->X_op != O_constant 3801 && ep->X_op != O_symbol) 3802 { 3803 as_bad (_("expression too complex")); 3804 ep->X_op = O_constant; 3805 } 3806 3807 if (ep->X_op == O_constant) 3808 { 3809 load_register (reg, ep, HAVE_64BIT_ADDRESSES); 3810 return; 3811 } 3812 3813 if (mips_pic == NO_PIC) 3814 { 3815 /* If this is a reference to a GP relative symbol, we want 3816 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) 3817 Otherwise we want 3818 lui $reg,<sym> (BFD_RELOC_HI16_S) 3819 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 3820 If we have an addend, we always use the latter form. 3821 3822 With 64bit address space and a usable $at we want 3823 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 3824 lui $at,<sym> (BFD_RELOC_HI16_S) 3825 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 3826 daddiu $at,<sym> (BFD_RELOC_LO16) 3827 dsll32 $reg,0 3828 daddu $reg,$reg,$at 3829 3830 If $at is already in use, we use a path which is suboptimal 3831 on superscalar processors. 3832 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) 3833 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) 3834 dsll $reg,16 3835 daddiu $reg,<sym> (BFD_RELOC_HI16_S) 3836 dsll $reg,16 3837 daddiu $reg,<sym> (BFD_RELOC_LO16) 3838 */ 3839 if (HAVE_64BIT_ADDRESSES) 3840 { 3841 /* ??? We don't provide a GP-relative alternative for these macros. 3842 It used not to be possible with the original relaxation code, 3843 but it could be done now. */ 3844 3845 if (*used_at == 0 && ! mips_opts.noat) 3846 { 3847 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); 3848 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S); 3849 macro_build (ep, "daddiu", "t,r,j", reg, reg, 3850 BFD_RELOC_MIPS_HIGHER); 3851 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); 3852 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0); 3853 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); 3854 *used_at = 1; 3855 } 3856 else 3857 { 3858 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST); 3859 macro_build (ep, "daddiu", "t,r,j", reg, reg, 3860 BFD_RELOC_MIPS_HIGHER); 3861 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); 3862 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); 3863 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16); 3864 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); 3865 } 3866 } 3867 else 3868 { 3869 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET 3870 && ! nopic_need_relax (ep->X_add_symbol, 1)) 3871 { 3872 relax_start (ep->X_add_symbol); 3873 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, 3874 mips_gp_register, BFD_RELOC_GPREL16); 3875 relax_switch (); 3876 } 3877 macro_build_lui (ep, reg); 3878 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", 3879 reg, reg, BFD_RELOC_LO16); 3880 if (mips_relax.sequence) 3881 relax_end (); 3882 } 3883 } 3884 else if (mips_pic == SVR4_PIC && ! mips_big_got) 3885 { 3886 expressionS ex; 3887 3888 /* If this is a reference to an external symbol, we want 3889 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 3890 Otherwise we want 3891 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 3892 nop 3893 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 3894 If there is a constant, it must be added in after. 3895 3896 If we have NewABI, we want 3897 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) 3898 unless we're referencing a global symbol with a non-zero 3899 offset, in which case cst must be added separately. */ 3900 if (HAVE_NEWABI) 3901 { 3902 if (ep->X_add_number) 3903 { 3904 ex.X_add_number = ep->X_add_number; 3905 ep->X_add_number = 0; 3906 relax_start (ep->X_add_symbol); 3907 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 3908 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 3909 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 3910 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 3911 ex.X_op = O_constant; 3912 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 3913 reg, reg, BFD_RELOC_LO16); 3914 ep->X_add_number = ex.X_add_number; 3915 relax_switch (); 3916 } 3917 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 3918 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 3919 if (mips_relax.sequence) 3920 relax_end (); 3921 } 3922 else 3923 { 3924 ex.X_add_number = ep->X_add_number; 3925 ep->X_add_number = 0; 3926 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 3927 BFD_RELOC_MIPS_GOT16, mips_gp_register); 3928 macro_build (NULL, "nop", ""); 3929 relax_start (ep->X_add_symbol); 3930 relax_switch (); 3931 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 3932 BFD_RELOC_LO16); 3933 relax_end (); 3934 3935 if (ex.X_add_number != 0) 3936 { 3937 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 3938 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 3939 ex.X_op = O_constant; 3940 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", 3941 reg, reg, BFD_RELOC_LO16); 3942 } 3943 } 3944 } 3945 else if (mips_pic == SVR4_PIC) 3946 { 3947 expressionS ex; 3948 3949 /* This is the large GOT case. If this is a reference to an 3950 external symbol, we want 3951 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 3952 addu $reg,$reg,$gp 3953 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) 3954 3955 Otherwise, for a reference to a local symbol in old ABI, we want 3956 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 3957 nop 3958 addiu $reg,$reg,<sym> (BFD_RELOC_LO16) 3959 If there is a constant, it must be added in after. 3960 3961 In the NewABI, for local symbols, with or without offsets, we want: 3962 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 3963 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 3964 */ 3965 if (HAVE_NEWABI) 3966 { 3967 ex.X_add_number = ep->X_add_number; 3968 ep->X_add_number = 0; 3969 relax_start (ep->X_add_symbol); 3970 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); 3971 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 3972 reg, reg, mips_gp_register); 3973 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 3974 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 3975 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 3976 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 3977 else if (ex.X_add_number) 3978 { 3979 ex.X_op = O_constant; 3980 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 3981 BFD_RELOC_LO16); 3982 } 3983 3984 ep->X_add_number = ex.X_add_number; 3985 relax_switch (); 3986 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 3987 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 3988 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 3989 BFD_RELOC_MIPS_GOT_OFST); 3990 relax_end (); 3991 } 3992 else 3993 { 3994 ex.X_add_number = ep->X_add_number; 3995 ep->X_add_number = 0; 3996 relax_start (ep->X_add_symbol); 3997 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16); 3998 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 3999 reg, reg, mips_gp_register); 4000 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", 4001 reg, BFD_RELOC_MIPS_GOT_LO16, reg); 4002 relax_switch (); 4003 if (reg_needs_delay (mips_gp_register)) 4004 { 4005 /* We need a nop before loading from $gp. This special 4006 check is required because the lui which starts the main 4007 instruction stream does not refer to $gp, and so will not 4008 insert the nop which may be required. */ 4009 macro_build (NULL, "nop", ""); 4010 } 4011 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, 4012 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4013 macro_build (NULL, "nop", ""); 4014 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4015 BFD_RELOC_LO16); 4016 relax_end (); 4017 4018 if (ex.X_add_number != 0) 4019 { 4020 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) 4021 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 4022 ex.X_op = O_constant; 4023 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, 4024 BFD_RELOC_LO16); 4025 } 4026 } 4027 } 4028 else if (mips_pic == EMBEDDED_PIC) 4029 { 4030 /* We always do 4031 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) 4032 */ 4033 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", 4034 reg, mips_gp_register, BFD_RELOC_GPREL16); 4035 } 4036 else 4037 abort (); 4038} 4039 4040/* Move the contents of register SOURCE into register DEST. */ 4041 4042static void 4043move_register (int dest, int source) 4044{ 4045 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", 4046 dest, source, 0); 4047} 4048 4049/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where 4050 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. 4051 The two alternatives are: 4052 4053 Global symbol Local sybmol 4054 ------------- ------------ 4055 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) 4056 ... ... 4057 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) 4058 4059 load_got_offset emits the first instruction and add_got_offset 4060 emits the second for a 16-bit offset or add_got_offset_hilo emits 4061 a sequence to add a 32-bit offset using a scratch register. */ 4062 4063static void 4064load_got_offset (int dest, expressionS *local) 4065{ 4066 expressionS global; 4067 4068 global = *local; 4069 global.X_add_number = 0; 4070 4071 relax_start (local->X_add_symbol); 4072 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, 4073 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4074 relax_switch (); 4075 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, 4076 BFD_RELOC_MIPS_GOT16, mips_gp_register); 4077 relax_end (); 4078} 4079 4080static void 4081add_got_offset (int dest, expressionS *local) 4082{ 4083 expressionS global; 4084 4085 global.X_op = O_constant; 4086 global.X_op_symbol = NULL; 4087 global.X_add_symbol = NULL; 4088 global.X_add_number = local->X_add_number; 4089 4090 relax_start (local->X_add_symbol); 4091 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", 4092 dest, dest, BFD_RELOC_LO16); 4093 relax_switch (); 4094 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); 4095 relax_end (); 4096} 4097 4098static void 4099add_got_offset_hilo (int dest, expressionS *local, int tmp) 4100{ 4101 expressionS global; 4102 int hold_mips_optimize; 4103 4104 global.X_op = O_constant; 4105 global.X_op_symbol = NULL; 4106 global.X_add_symbol = NULL; 4107 global.X_add_number = local->X_add_number; 4108 4109 relax_start (local->X_add_symbol); 4110 load_register (tmp, &global, HAVE_64BIT_ADDRESSES); 4111 relax_switch (); 4112 /* Set mips_optimize around the lui instruction to avoid 4113 inserting an unnecessary nop after the lw. */ 4114 hold_mips_optimize = mips_optimize; 4115 mips_optimize = 2; 4116 macro_build_lui (&global, tmp); 4117 mips_optimize = hold_mips_optimize; 4118 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); 4119 relax_end (); 4120 4121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); 4122} 4123 4124/* 4125 * Build macros 4126 * This routine implements the seemingly endless macro or synthesized 4127 * instructions and addressing modes in the mips assembly language. Many 4128 * of these macros are simple and are similar to each other. These could 4129 * probably be handled by some kind of table or grammar approach instead of 4130 * this verbose method. Others are not simple macros but are more like 4131 * optimizing code generation. 4132 * One interesting optimization is when several store macros appear 4133 * consecutively that would load AT with the upper half of the same address. 4134 * The ensuing load upper instructions are ommited. This implies some kind 4135 * of global optimization. We currently only optimize within a single macro. 4136 * For many of the load and store macros if the address is specified as a 4137 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we 4138 * first load register 'at' with zero and use it as the base register. The 4139 * mips assembler simply uses register $zero. Just one tiny optimization 4140 * we're missing. 4141 */ 4142static void 4143macro (struct mips_cl_insn *ip) 4144{ 4145 register int treg, sreg, dreg, breg; 4146 int tempreg; 4147 int mask; 4148 int used_at = 0; 4149 expressionS expr1; 4150 const char *s; 4151 const char *s2; 4152 const char *fmt; 4153 int likely = 0; 4154 int dbl = 0; 4155 int coproc = 0; 4156 int lr = 0; 4157 int imm = 0; 4158 int call = 0; 4159 int off; 4160 offsetT maxnum; 4161 bfd_reloc_code_real_type r; 4162 int hold_mips_optimize; 4163 4164 assert (! mips_opts.mips16); 4165 4166 treg = (ip->insn_opcode >> 16) & 0x1f; 4167 dreg = (ip->insn_opcode >> 11) & 0x1f; 4168 sreg = breg = (ip->insn_opcode >> 21) & 0x1f; 4169 mask = ip->insn_mo->mask; 4170 4171 expr1.X_op = O_constant; 4172 expr1.X_op_symbol = NULL; 4173 expr1.X_add_symbol = NULL; 4174 expr1.X_add_number = 1; 4175 4176 switch (mask) 4177 { 4178 case M_DABS: 4179 dbl = 1; 4180 case M_ABS: 4181 /* bgez $a0,.+12 4182 move v0,$a0 4183 sub v0,$zero,$a0 4184 */ 4185 4186 mips_emit_delays (TRUE); 4187 ++mips_opts.noreorder; 4188 mips_any_noreorder = 1; 4189 4190 expr1.X_add_number = 8; 4191 macro_build (&expr1, "bgez", "s,p", sreg); 4192 if (dreg == sreg) 4193 macro_build (NULL, "nop", "", 0); 4194 else 4195 move_register (dreg, sreg); 4196 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); 4197 4198 --mips_opts.noreorder; 4199 return; 4200 4201 case M_ADD_I: 4202 s = "addi"; 4203 s2 = "add"; 4204 goto do_addi; 4205 case M_ADDU_I: 4206 s = "addiu"; 4207 s2 = "addu"; 4208 goto do_addi; 4209 case M_DADD_I: 4210 dbl = 1; 4211 s = "daddi"; 4212 s2 = "dadd"; 4213 goto do_addi; 4214 case M_DADDU_I: 4215 dbl = 1; 4216 s = "daddiu"; 4217 s2 = "daddu"; 4218 do_addi: 4219 if (imm_expr.X_op == O_constant 4220 && imm_expr.X_add_number >= -0x8000 4221 && imm_expr.X_add_number < 0x8000) 4222 { 4223 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16); 4224 return; 4225 } 4226 load_register (AT, &imm_expr, dbl); 4227 macro_build (NULL, s2, "d,v,t", treg, sreg, AT); 4228 break; 4229 4230 case M_AND_I: 4231 s = "andi"; 4232 s2 = "and"; 4233 goto do_bit; 4234 case M_OR_I: 4235 s = "ori"; 4236 s2 = "or"; 4237 goto do_bit; 4238 case M_NOR_I: 4239 s = ""; 4240 s2 = "nor"; 4241 goto do_bit; 4242 case M_XOR_I: 4243 s = "xori"; 4244 s2 = "xor"; 4245 do_bit: 4246 if (imm_expr.X_op == O_constant 4247 && imm_expr.X_add_number >= 0 4248 && imm_expr.X_add_number < 0x10000) 4249 { 4250 if (mask != M_NOR_I) 4251 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16); 4252 else 4253 { 4254 macro_build (&imm_expr, "ori", "t,r,i", 4255 treg, sreg, BFD_RELOC_LO16); 4256 macro_build (NULL, "nor", "d,v,t", treg, treg, 0); 4257 } 4258 return; 4259 } 4260 4261 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 4262 macro_build (NULL, s2, "d,v,t", treg, sreg, AT); 4263 break; 4264 4265 case M_BEQ_I: 4266 s = "beq"; 4267 goto beq_i; 4268 case M_BEQL_I: 4269 s = "beql"; 4270 likely = 1; 4271 goto beq_i; 4272 case M_BNE_I: 4273 s = "bne"; 4274 goto beq_i; 4275 case M_BNEL_I: 4276 s = "bnel"; 4277 likely = 1; 4278 beq_i: 4279 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4280 { 4281 macro_build (&offset_expr, s, "s,t,p", sreg, 0); 4282 return; 4283 } 4284 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 4285 macro_build (&offset_expr, s, "s,t,p", sreg, AT); 4286 break; 4287 4288 case M_BGEL: 4289 likely = 1; 4290 case M_BGE: 4291 if (treg == 0) 4292 { 4293 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); 4294 return; 4295 } 4296 if (sreg == 0) 4297 { 4298 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg); 4299 return; 4300 } 4301 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); 4302 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4303 break; 4304 4305 case M_BGTL_I: 4306 likely = 1; 4307 case M_BGT_I: 4308 /* check for > max integer */ 4309 maxnum = 0x7fffffff; 4310 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) 4311 { 4312 maxnum <<= 16; 4313 maxnum |= 0xffff; 4314 maxnum <<= 16; 4315 maxnum |= 0xffff; 4316 } 4317 if (imm_expr.X_op == O_constant 4318 && imm_expr.X_add_number >= maxnum 4319 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) 4320 { 4321 do_false: 4322 /* result is always false */ 4323 if (! likely) 4324 macro_build (NULL, "nop", "", 0); 4325 else 4326 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0); 4327 return; 4328 } 4329 if (imm_expr.X_op != O_constant) 4330 as_bad (_("Unsupported large constant")); 4331 ++imm_expr.X_add_number; 4332 /* FALLTHROUGH */ 4333 case M_BGE_I: 4334 case M_BGEL_I: 4335 if (mask == M_BGEL_I) 4336 likely = 1; 4337 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4338 { 4339 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg); 4340 return; 4341 } 4342 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4343 { 4344 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); 4345 return; 4346 } 4347 maxnum = 0x7fffffff; 4348 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) 4349 { 4350 maxnum <<= 16; 4351 maxnum |= 0xffff; 4352 maxnum <<= 16; 4353 maxnum |= 0xffff; 4354 } 4355 maxnum = - maxnum - 1; 4356 if (imm_expr.X_op == O_constant 4357 && imm_expr.X_add_number <= maxnum 4358 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) 4359 { 4360 do_true: 4361 /* result is always true */ 4362 as_warn (_("Branch %s is always true"), ip->insn_mo->name); 4363 macro_build (&offset_expr, "b", "p"); 4364 return; 4365 } 4366 set_at (sreg, 0); 4367 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4368 break; 4369 4370 case M_BGEUL: 4371 likely = 1; 4372 case M_BGEU: 4373 if (treg == 0) 4374 goto do_true; 4375 if (sreg == 0) 4376 { 4377 macro_build (&offset_expr, likely ? "beql" : "beq", 4378 "s,t,p", 0, treg); 4379 return; 4380 } 4381 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); 4382 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4383 break; 4384 4385 case M_BGTUL_I: 4386 likely = 1; 4387 case M_BGTU_I: 4388 if (sreg == 0 4389 || (HAVE_32BIT_GPRS 4390 && imm_expr.X_op == O_constant 4391 && imm_expr.X_add_number == (offsetT) 0xffffffff)) 4392 goto do_false; 4393 if (imm_expr.X_op != O_constant) 4394 as_bad (_("Unsupported large constant")); 4395 ++imm_expr.X_add_number; 4396 /* FALLTHROUGH */ 4397 case M_BGEU_I: 4398 case M_BGEUL_I: 4399 if (mask == M_BGEUL_I) 4400 likely = 1; 4401 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4402 goto do_true; 4403 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4404 { 4405 macro_build (&offset_expr, likely ? "bnel" : "bne", 4406 "s,t,p", sreg, 0); 4407 return; 4408 } 4409 set_at (sreg, 1); 4410 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4411 break; 4412 4413 case M_BGTL: 4414 likely = 1; 4415 case M_BGT: 4416 if (treg == 0) 4417 { 4418 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg); 4419 return; 4420 } 4421 if (sreg == 0) 4422 { 4423 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg); 4424 return; 4425 } 4426 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); 4427 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4428 break; 4429 4430 case M_BGTUL: 4431 likely = 1; 4432 case M_BGTU: 4433 if (treg == 0) 4434 { 4435 macro_build (&offset_expr, likely ? "bnel" : "bne", 4436 "s,t,p", sreg, 0); 4437 return; 4438 } 4439 if (sreg == 0) 4440 goto do_false; 4441 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); 4442 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4443 break; 4444 4445 case M_BLEL: 4446 likely = 1; 4447 case M_BLE: 4448 if (treg == 0) 4449 { 4450 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); 4451 return; 4452 } 4453 if (sreg == 0) 4454 { 4455 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg); 4456 return; 4457 } 4458 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg); 4459 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4460 break; 4461 4462 case M_BLEL_I: 4463 likely = 1; 4464 case M_BLE_I: 4465 maxnum = 0x7fffffff; 4466 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) 4467 { 4468 maxnum <<= 16; 4469 maxnum |= 0xffff; 4470 maxnum <<= 16; 4471 maxnum |= 0xffff; 4472 } 4473 if (imm_expr.X_op == O_constant 4474 && imm_expr.X_add_number >= maxnum 4475 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) 4476 goto do_true; 4477 if (imm_expr.X_op != O_constant) 4478 as_bad (_("Unsupported large constant")); 4479 ++imm_expr.X_add_number; 4480 /* FALLTHROUGH */ 4481 case M_BLT_I: 4482 case M_BLTL_I: 4483 if (mask == M_BLTL_I) 4484 likely = 1; 4485 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4486 { 4487 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); 4488 return; 4489 } 4490 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4491 { 4492 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg); 4493 return; 4494 } 4495 set_at (sreg, 0); 4496 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4497 break; 4498 4499 case M_BLEUL: 4500 likely = 1; 4501 case M_BLEU: 4502 if (treg == 0) 4503 { 4504 macro_build (&offset_expr, likely ? "beql" : "beq", 4505 "s,t,p", sreg, 0); 4506 return; 4507 } 4508 if (sreg == 0) 4509 goto do_true; 4510 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg); 4511 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0); 4512 break; 4513 4514 case M_BLEUL_I: 4515 likely = 1; 4516 case M_BLEU_I: 4517 if (sreg == 0 4518 || (HAVE_32BIT_GPRS 4519 && imm_expr.X_op == O_constant 4520 && imm_expr.X_add_number == (offsetT) 0xffffffff)) 4521 goto do_true; 4522 if (imm_expr.X_op != O_constant) 4523 as_bad (_("Unsupported large constant")); 4524 ++imm_expr.X_add_number; 4525 /* FALLTHROUGH */ 4526 case M_BLTU_I: 4527 case M_BLTUL_I: 4528 if (mask == M_BLTUL_I) 4529 likely = 1; 4530 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4531 goto do_false; 4532 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4533 { 4534 macro_build (&offset_expr, likely ? "beql" : "beq", 4535 "s,t,p", sreg, 0); 4536 return; 4537 } 4538 set_at (sreg, 1); 4539 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4540 break; 4541 4542 case M_BLTL: 4543 likely = 1; 4544 case M_BLT: 4545 if (treg == 0) 4546 { 4547 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg); 4548 return; 4549 } 4550 if (sreg == 0) 4551 { 4552 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg); 4553 return; 4554 } 4555 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg); 4556 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4557 break; 4558 4559 case M_BLTUL: 4560 likely = 1; 4561 case M_BLTU: 4562 if (treg == 0) 4563 goto do_false; 4564 if (sreg == 0) 4565 { 4566 macro_build (&offset_expr, likely ? "bnel" : "bne", 4567 "s,t,p", 0, treg); 4568 return; 4569 } 4570 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg); 4571 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0); 4572 break; 4573 4574 case M_DEXT: 4575 { 4576 unsigned long pos; 4577 unsigned long size; 4578 4579 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) 4580 { 4581 as_bad (_("Unsupported large constant")); 4582 pos = size = 1; 4583 } 4584 else 4585 { 4586 pos = (unsigned long) imm_expr.X_add_number; 4587 size = (unsigned long) imm2_expr.X_add_number; 4588 } 4589 4590 if (pos > 63) 4591 { 4592 as_bad (_("Improper position (%lu)"), pos); 4593 pos = 1; 4594 } 4595 if (size == 0 || size > 64 4596 || (pos + size - 1) > 63) 4597 { 4598 as_bad (_("Improper extract size (%lu, position %lu)"), 4599 size, pos); 4600 size = 1; 4601 } 4602 4603 if (size <= 32 && pos < 32) 4604 { 4605 s = "dext"; 4606 fmt = "t,r,+A,+C"; 4607 } 4608 else if (size <= 32) 4609 { 4610 s = "dextu"; 4611 fmt = "t,r,+E,+H"; 4612 } 4613 else 4614 { 4615 s = "dextm"; 4616 fmt = "t,r,+A,+G"; 4617 } 4618 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1); 4619 } 4620 return; 4621 4622 case M_DINS: 4623 { 4624 unsigned long pos; 4625 unsigned long size; 4626 4627 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) 4628 { 4629 as_bad (_("Unsupported large constant")); 4630 pos = size = 1; 4631 } 4632 else 4633 { 4634 pos = (unsigned long) imm_expr.X_add_number; 4635 size = (unsigned long) imm2_expr.X_add_number; 4636 } 4637 4638 if (pos > 63) 4639 { 4640 as_bad (_("Improper position (%lu)"), pos); 4641 pos = 1; 4642 } 4643 if (size == 0 || size > 64 4644 || (pos + size - 1) > 63) 4645 { 4646 as_bad (_("Improper insert size (%lu, position %lu)"), 4647 size, pos); 4648 size = 1; 4649 } 4650 4651 if (pos < 32 && (pos + size - 1) < 32) 4652 { 4653 s = "dins"; 4654 fmt = "t,r,+A,+B"; 4655 } 4656 else if (pos >= 32) 4657 { 4658 s = "dinsu"; 4659 fmt = "t,r,+E,+F"; 4660 } 4661 else 4662 { 4663 s = "dinsm"; 4664 fmt = "t,r,+A,+F"; 4665 } 4666 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, 4667 pos + size - 1); 4668 } 4669 return; 4670 4671 case M_DDIV_3: 4672 dbl = 1; 4673 case M_DIV_3: 4674 s = "mflo"; 4675 goto do_div3; 4676 case M_DREM_3: 4677 dbl = 1; 4678 case M_REM_3: 4679 s = "mfhi"; 4680 do_div3: 4681 if (treg == 0) 4682 { 4683 as_warn (_("Divide by zero.")); 4684 if (mips_trap) 4685 macro_build (NULL, "teq", "s,t,q", 0, 0, 7); 4686 else 4687 macro_build (NULL, "break", "c", 7); 4688 return; 4689 } 4690 4691 mips_emit_delays (TRUE); 4692 ++mips_opts.noreorder; 4693 mips_any_noreorder = 1; 4694 if (mips_trap) 4695 { 4696 macro_build (NULL, "teq", "s,t,q", treg, 0, 7); 4697 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); 4698 } 4699 else 4700 { 4701 expr1.X_add_number = 8; 4702 macro_build (&expr1, "bne", "s,t,p", treg, 0); 4703 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg); 4704 macro_build (NULL, "break", "c", 7); 4705 } 4706 expr1.X_add_number = -1; 4707 load_register (AT, &expr1, dbl); 4708 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); 4709 macro_build (&expr1, "bne", "s,t,p", treg, AT); 4710 if (dbl) 4711 { 4712 expr1.X_add_number = 1; 4713 load_register (AT, &expr1, dbl); 4714 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31); 4715 } 4716 else 4717 { 4718 expr1.X_add_number = 0x80000000; 4719 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16); 4720 } 4721 if (mips_trap) 4722 { 4723 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6); 4724 /* We want to close the noreorder block as soon as possible, so 4725 that later insns are available for delay slot filling. */ 4726 --mips_opts.noreorder; 4727 } 4728 else 4729 { 4730 expr1.X_add_number = 8; 4731 macro_build (&expr1, "bne", "s,t,p", sreg, AT); 4732 macro_build (NULL, "nop", "", 0); 4733 4734 /* We want to close the noreorder block as soon as possible, so 4735 that later insns are available for delay slot filling. */ 4736 --mips_opts.noreorder; 4737 4738 macro_build (NULL, "break", "c", 6); 4739 } 4740 macro_build (NULL, s, "d", dreg); 4741 break; 4742 4743 case M_DIV_3I: 4744 s = "div"; 4745 s2 = "mflo"; 4746 goto do_divi; 4747 case M_DIVU_3I: 4748 s = "divu"; 4749 s2 = "mflo"; 4750 goto do_divi; 4751 case M_REM_3I: 4752 s = "div"; 4753 s2 = "mfhi"; 4754 goto do_divi; 4755 case M_REMU_3I: 4756 s = "divu"; 4757 s2 = "mfhi"; 4758 goto do_divi; 4759 case M_DDIV_3I: 4760 dbl = 1; 4761 s = "ddiv"; 4762 s2 = "mflo"; 4763 goto do_divi; 4764 case M_DDIVU_3I: 4765 dbl = 1; 4766 s = "ddivu"; 4767 s2 = "mflo"; 4768 goto do_divi; 4769 case M_DREM_3I: 4770 dbl = 1; 4771 s = "ddiv"; 4772 s2 = "mfhi"; 4773 goto do_divi; 4774 case M_DREMU_3I: 4775 dbl = 1; 4776 s = "ddivu"; 4777 s2 = "mfhi"; 4778 do_divi: 4779 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 4780 { 4781 as_warn (_("Divide by zero.")); 4782 if (mips_trap) 4783 macro_build (NULL, "teq", "s,t,q", 0, 0, 7); 4784 else 4785 macro_build (NULL, "break", "c", 7); 4786 return; 4787 } 4788 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) 4789 { 4790 if (strcmp (s2, "mflo") == 0) 4791 move_register (dreg, sreg); 4792 else 4793 move_register (dreg, 0); 4794 return; 4795 } 4796 if (imm_expr.X_op == O_constant 4797 && imm_expr.X_add_number == -1 4798 && s[strlen (s) - 1] != 'u') 4799 { 4800 if (strcmp (s2, "mflo") == 0) 4801 { 4802 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg); 4803 } 4804 else 4805 move_register (dreg, 0); 4806 return; 4807 } 4808 4809 load_register (AT, &imm_expr, dbl); 4810 macro_build (NULL, s, "z,s,t", sreg, AT); 4811 macro_build (NULL, s2, "d", dreg); 4812 break; 4813 4814 case M_DIVU_3: 4815 s = "divu"; 4816 s2 = "mflo"; 4817 goto do_divu3; 4818 case M_REMU_3: 4819 s = "divu"; 4820 s2 = "mfhi"; 4821 goto do_divu3; 4822 case M_DDIVU_3: 4823 s = "ddivu"; 4824 s2 = "mflo"; 4825 goto do_divu3; 4826 case M_DREMU_3: 4827 s = "ddivu"; 4828 s2 = "mfhi"; 4829 do_divu3: 4830 mips_emit_delays (TRUE); 4831 ++mips_opts.noreorder; 4832 mips_any_noreorder = 1; 4833 if (mips_trap) 4834 { 4835 macro_build (NULL, "teq", "s,t,q", treg, 0, 7); 4836 macro_build (NULL, s, "z,s,t", sreg, treg); 4837 /* We want to close the noreorder block as soon as possible, so 4838 that later insns are available for delay slot filling. */ 4839 --mips_opts.noreorder; 4840 } 4841 else 4842 { 4843 expr1.X_add_number = 8; 4844 macro_build (&expr1, "bne", "s,t,p", treg, 0); 4845 macro_build (NULL, s, "z,s,t", sreg, treg); 4846 4847 /* We want to close the noreorder block as soon as possible, so 4848 that later insns are available for delay slot filling. */ 4849 --mips_opts.noreorder; 4850 macro_build (NULL, "break", "c", 7); 4851 } 4852 macro_build (NULL, s2, "d", dreg); 4853 return; 4854 4855 case M_DLCA_AB: 4856 dbl = 1; 4857 case M_LCA_AB: 4858 call = 1; 4859 goto do_la; 4860 case M_DLA_AB: 4861 dbl = 1; 4862 case M_LA_AB: 4863 do_la: 4864 /* Load the address of a symbol into a register. If breg is not 4865 zero, we then add a base register to it. */ 4866 4867 if (dbl && HAVE_32BIT_GPRS) 4868 as_warn (_("dla used to load 32-bit register")); 4869 4870 if (! dbl && HAVE_64BIT_OBJECTS) 4871 as_warn (_("la used to load 64-bit address")); 4872 4873 if (offset_expr.X_op == O_constant 4874 && offset_expr.X_add_number >= -0x8000 4875 && offset_expr.X_add_number < 0x8000) 4876 { 4877 macro_build (&offset_expr, 4878 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", 4879 "t,r,j", treg, sreg, BFD_RELOC_LO16); 4880 return; 4881 } 4882 4883 if (treg == breg) 4884 { 4885 tempreg = AT; 4886 used_at = 1; 4887 } 4888 else 4889 { 4890 tempreg = treg; 4891 used_at = 0; 4892 } 4893 4894 /* When generating embedded PIC code, we permit expressions of 4895 the form 4896 la $treg,foo-bar 4897 la $treg,foo-bar($breg) 4898 where bar is an address in the current section. These are used 4899 when getting the addresses of functions. We don't permit 4900 X_add_number to be non-zero, because if the symbol is 4901 external the relaxing code needs to know that any addend is 4902 purely the offset to X_op_symbol. */ 4903 if (mips_pic == EMBEDDED_PIC 4904 && offset_expr.X_op == O_subtract 4905 && (symbol_constant_p (offset_expr.X_op_symbol) 4906 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg 4907 : (symbol_equated_p (offset_expr.X_op_symbol) 4908 && (S_GET_SEGMENT 4909 (symbol_get_value_expression (offset_expr.X_op_symbol) 4910 ->X_add_symbol) 4911 == now_seg))) 4912 && (offset_expr.X_add_number == 0 4913 || OUTPUT_FLAVOR == bfd_target_elf_flavour)) 4914 { 4915 if (breg == 0) 4916 { 4917 tempreg = treg; 4918 used_at = 0; 4919 macro_build (&offset_expr, "lui", "t,u", 4920 tempreg, BFD_RELOC_PCREL_HI16_S); 4921 } 4922 else 4923 { 4924 macro_build (&offset_expr, "lui", "t,u", 4925 tempreg, BFD_RELOC_PCREL_HI16_S); 4926 macro_build (NULL, 4927 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu", 4928 "d,v,t", tempreg, tempreg, breg); 4929 } 4930 macro_build (&offset_expr, 4931 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu", 4932 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16); 4933 if (! used_at) 4934 return; 4935 break; 4936 } 4937 4938 if (offset_expr.X_op != O_symbol 4939 && offset_expr.X_op != O_constant) 4940 { 4941 as_bad (_("expression too complex")); 4942 offset_expr.X_op = O_constant; 4943 } 4944 4945 if (offset_expr.X_op == O_constant) 4946 load_register (tempreg, &offset_expr, 4947 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) 4948 ? (dbl || HAVE_64BIT_ADDRESSES) 4949 : HAVE_64BIT_ADDRESSES)); 4950 else if (mips_pic == NO_PIC) 4951 { 4952 /* If this is a reference to a GP relative symbol, we want 4953 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) 4954 Otherwise we want 4955 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 4956 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 4957 If we have a constant, we need two instructions anyhow, 4958 so we may as well always use the latter form. 4959 4960 With 64bit address space and a usable $at we want 4961 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 4962 lui $at,<sym> (BFD_RELOC_HI16_S) 4963 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 4964 daddiu $at,<sym> (BFD_RELOC_LO16) 4965 dsll32 $tempreg,0 4966 daddu $tempreg,$tempreg,$at 4967 4968 If $at is already in use, we use a path which is suboptimal 4969 on superscalar processors. 4970 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 4971 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 4972 dsll $tempreg,16 4973 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 4974 dsll $tempreg,16 4975 daddiu $tempreg,<sym> (BFD_RELOC_LO16) 4976 */ 4977 if (HAVE_64BIT_ADDRESSES) 4978 { 4979 /* ??? We don't provide a GP-relative alternative for 4980 these macros. It used not to be possible with the 4981 original relaxation code, but it could be done now. */ 4982 4983 if (used_at == 0 && ! mips_opts.noat) 4984 { 4985 macro_build (&offset_expr, "lui", "t,u", 4986 tempreg, BFD_RELOC_MIPS_HIGHEST); 4987 macro_build (&offset_expr, "lui", "t,u", 4988 AT, BFD_RELOC_HI16_S); 4989 macro_build (&offset_expr, "daddiu", "t,r,j", 4990 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 4991 macro_build (&offset_expr, "daddiu", "t,r,j", 4992 AT, AT, BFD_RELOC_LO16); 4993 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); 4994 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 4995 used_at = 1; 4996 } 4997 else 4998 { 4999 macro_build (&offset_expr, "lui", "t,u", 5000 tempreg, BFD_RELOC_MIPS_HIGHEST); 5001 macro_build (&offset_expr, "daddiu", "t,r,j", 5002 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); 5003 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 5004 macro_build (&offset_expr, "daddiu", "t,r,j", 5005 tempreg, tempreg, BFD_RELOC_HI16_S); 5006 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 5007 macro_build (&offset_expr, "daddiu", "t,r,j", 5008 tempreg, tempreg, BFD_RELOC_LO16); 5009 } 5010 } 5011 else 5012 { 5013 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 5014 && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) 5015 { 5016 relax_start (offset_expr.X_add_symbol); 5017 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5018 tempreg, mips_gp_register, BFD_RELOC_GPREL16); 5019 relax_switch (); 5020 } 5021 macro_build_lui (&offset_expr, tempreg); 5022 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5023 tempreg, tempreg, BFD_RELOC_LO16); 5024 if (mips_relax.sequence) 5025 relax_end (); 5026 } 5027 } 5028 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI) 5029 { 5030 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 5031 5032 /* If this is a reference to an external symbol, and there 5033 is no constant, we want 5034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5035 or for lca or if tempreg is PIC_CALL_REG 5036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 5037 For a local symbol, we want 5038 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5039 nop 5040 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 5041 5042 If we have a small constant, and this is a reference to 5043 an external symbol, we want 5044 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5045 nop 5046 addiu $tempreg,$tempreg,<constant> 5047 For a local symbol, we want the same instruction 5048 sequence, but we output a BFD_RELOC_LO16 reloc on the 5049 addiu instruction. 5050 5051 If we have a large constant, and this is a reference to 5052 an external symbol, we want 5053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5054 lui $at,<hiconstant> 5055 addiu $at,$at,<loconstant> 5056 addu $tempreg,$tempreg,$at 5057 For a local symbol, we want the same instruction 5058 sequence, but we output a BFD_RELOC_LO16 reloc on the 5059 addiu instruction. 5060 */ 5061 5062 if (offset_expr.X_add_number == 0) 5063 { 5064 if (breg == 0 && (call || tempreg == PIC_CALL_REG)) 5065 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; 5066 5067 relax_start (offset_expr.X_add_symbol); 5068 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5069 lw_reloc_type, mips_gp_register); 5070 if (breg != 0) 5071 { 5072 /* We're going to put in an addu instruction using 5073 tempreg, so we may as well insert the nop right 5074 now. */ 5075 macro_build (NULL, "nop", ""); 5076 } 5077 relax_switch (); 5078 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5079 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); 5080 macro_build (NULL, "nop", ""); 5081 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5082 tempreg, tempreg, BFD_RELOC_LO16); 5083 relax_end (); 5084 /* FIXME: If breg == 0, and the next instruction uses 5085 $tempreg, then if this variant case is used an extra 5086 nop will be generated. */ 5087 } 5088 else if (offset_expr.X_add_number >= -0x8000 5089 && offset_expr.X_add_number < 0x8000) 5090 { 5091 load_got_offset (tempreg, &offset_expr); 5092 macro_build (NULL, "nop", ""); 5093 add_got_offset (tempreg, &offset_expr); 5094 } 5095 else 5096 { 5097 expr1.X_add_number = offset_expr.X_add_number; 5098 offset_expr.X_add_number = 5099 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000; 5100 load_got_offset (tempreg, &offset_expr); 5101 offset_expr.X_add_number = expr1.X_add_number; 5102 /* If we are going to add in a base register, and the 5103 target register and the base register are the same, 5104 then we are using AT as a temporary register. Since 5105 we want to load the constant into AT, we add our 5106 current AT (from the global offset table) and the 5107 register into the register now, and pretend we were 5108 not using a base register. */ 5109 if (breg == treg) 5110 { 5111 macro_build (NULL, "nop", ""); 5112 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5113 treg, AT, breg); 5114 breg = 0; 5115 tempreg = treg; 5116 } 5117 add_got_offset_hilo (tempreg, &offset_expr, AT); 5118 used_at = 1; 5119 } 5120 } 5121 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI) 5122 { 5123 int add_breg_early = 0; 5124 5125 /* If this is a reference to an external, and there is no 5126 constant, or local symbol (*), with or without a 5127 constant, we want 5128 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 5129 or for lca or if tempreg is PIC_CALL_REG 5130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 5131 5132 If we have a small constant, and this is a reference to 5133 an external symbol, we want 5134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 5135 addiu $tempreg,$tempreg,<constant> 5136 5137 If we have a large constant, and this is a reference to 5138 an external symbol, we want 5139 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) 5140 lui $at,<hiconstant> 5141 addiu $at,$at,<loconstant> 5142 addu $tempreg,$tempreg,$at 5143 5144 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for 5145 local symbols, even though it introduces an additional 5146 instruction. */ 5147 5148 if (offset_expr.X_add_number) 5149 { 5150 expr1.X_add_number = offset_expr.X_add_number; 5151 offset_expr.X_add_number = 0; 5152 5153 relax_start (offset_expr.X_add_symbol); 5154 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5155 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5156 5157 if (expr1.X_add_number >= -0x8000 5158 && expr1.X_add_number < 0x8000) 5159 { 5160 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 5161 tempreg, tempreg, BFD_RELOC_LO16); 5162 } 5163 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 5164 { 5165 int dreg; 5166 5167 /* If we are going to add in a base register, and the 5168 target register and the base register are the same, 5169 then we are using AT as a temporary register. Since 5170 we want to load the constant into AT, we add our 5171 current AT (from the global offset table) and the 5172 register into the register now, and pretend we were 5173 not using a base register. */ 5174 if (breg != treg) 5175 dreg = tempreg; 5176 else 5177 { 5178 assert (tempreg == AT); 5179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5180 treg, AT, breg); 5181 dreg = treg; 5182 add_breg_early = 1; 5183 } 5184 5185 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 5186 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5187 dreg, dreg, AT); 5188 5189 used_at = 1; 5190 } 5191 else 5192 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 5193 5194 relax_switch (); 5195 offset_expr.X_add_number = expr1.X_add_number; 5196 5197 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5198 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5199 if (add_breg_early) 5200 { 5201 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5202 treg, tempreg, breg); 5203 breg = 0; 5204 tempreg = treg; 5205 } 5206 relax_end (); 5207 } 5208 else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) 5209 { 5210 relax_start (offset_expr.X_add_symbol); 5211 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5212 BFD_RELOC_MIPS_CALL16, mips_gp_register); 5213 relax_switch (); 5214 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5215 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5216 relax_end (); 5217 } 5218 else 5219 { 5220 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5221 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); 5222 } 5223 } 5224 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) 5225 { 5226 int gpdelay; 5227 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 5228 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 5229 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 5230 5231 /* This is the large GOT case. If this is a reference to an 5232 external symbol, and there is no constant, we want 5233 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5234 addu $tempreg,$tempreg,$gp 5235 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5236 or for lca or if tempreg is PIC_CALL_REG 5237 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 5238 addu $tempreg,$tempreg,$gp 5239 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 5240 For a local symbol, we want 5241 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5242 nop 5243 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 5244 5245 If we have a small constant, and this is a reference to 5246 an external symbol, we want 5247 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5248 addu $tempreg,$tempreg,$gp 5249 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5250 nop 5251 addiu $tempreg,$tempreg,<constant> 5252 For a local symbol, we want 5253 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5254 nop 5255 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) 5256 5257 If we have a large constant, and this is a reference to 5258 an external symbol, we want 5259 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5260 addu $tempreg,$tempreg,$gp 5261 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5262 lui $at,<hiconstant> 5263 addiu $at,$at,<loconstant> 5264 addu $tempreg,$tempreg,$at 5265 For a local symbol, we want 5266 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5267 lui $at,<hiconstant> 5268 addiu $at,$at,<loconstant> (BFD_RELOC_LO16) 5269 addu $tempreg,$tempreg,$at 5270 */ 5271 5272 expr1.X_add_number = offset_expr.X_add_number; 5273 offset_expr.X_add_number = 0; 5274 relax_start (offset_expr.X_add_symbol); 5275 gpdelay = reg_needs_delay (mips_gp_register); 5276 if (expr1.X_add_number == 0 && breg == 0 5277 && (call || tempreg == PIC_CALL_REG)) 5278 { 5279 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 5280 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 5281 } 5282 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); 5283 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5284 tempreg, tempreg, mips_gp_register); 5285 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5286 tempreg, lw_reloc_type, tempreg); 5287 if (expr1.X_add_number == 0) 5288 { 5289 if (breg != 0) 5290 { 5291 /* We're going to put in an addu instruction using 5292 tempreg, so we may as well insert the nop right 5293 now. */ 5294 macro_build (NULL, "nop", ""); 5295 } 5296 } 5297 else if (expr1.X_add_number >= -0x8000 5298 && expr1.X_add_number < 0x8000) 5299 { 5300 macro_build (NULL, "nop", ""); 5301 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 5302 tempreg, tempreg, BFD_RELOC_LO16); 5303 } 5304 else 5305 { 5306 int dreg; 5307 5308 /* If we are going to add in a base register, and the 5309 target register and the base register are the same, 5310 then we are using AT as a temporary register. Since 5311 we want to load the constant into AT, we add our 5312 current AT (from the global offset table) and the 5313 register into the register now, and pretend we were 5314 not using a base register. */ 5315 if (breg != treg) 5316 dreg = tempreg; 5317 else 5318 { 5319 assert (tempreg == AT); 5320 macro_build (NULL, "nop", ""); 5321 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5322 treg, AT, breg); 5323 dreg = treg; 5324 } 5325 5326 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 5327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 5328 5329 used_at = 1; 5330 } 5331 offset_expr.X_add_number = 5332 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000; 5333 relax_switch (); 5334 5335 if (gpdelay) 5336 { 5337 /* This is needed because this instruction uses $gp, but 5338 the first instruction on the main stream does not. */ 5339 macro_build (NULL, "nop", ""); 5340 } 5341 5342 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5343 local_reloc_type, mips_gp_register); 5344 if (expr1.X_add_number >= -0x8000 5345 && expr1.X_add_number < 0x8000) 5346 { 5347 macro_build (NULL, "nop", ""); 5348 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5349 tempreg, tempreg, BFD_RELOC_LO16); 5350 /* FIXME: If add_number is 0, and there was no base 5351 register, the external symbol case ended with a load, 5352 so if the symbol turns out to not be external, and 5353 the next instruction uses tempreg, an unnecessary nop 5354 will be inserted. */ 5355 } 5356 else 5357 { 5358 if (breg == treg) 5359 { 5360 /* We must add in the base register now, as in the 5361 external symbol case. */ 5362 assert (tempreg == AT); 5363 macro_build (NULL, "nop", ""); 5364 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5365 treg, AT, breg); 5366 tempreg = treg; 5367 /* We set breg to 0 because we have arranged to add 5368 it in in both cases. */ 5369 breg = 0; 5370 } 5371 5372 macro_build_lui (&expr1, AT); 5373 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5374 AT, AT, BFD_RELOC_LO16); 5375 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5376 tempreg, tempreg, AT); 5377 } 5378 relax_end (); 5379 } 5380 else if (mips_pic == SVR4_PIC && HAVE_NEWABI) 5381 { 5382 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; 5383 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; 5384 int add_breg_early = 0; 5385 5386 /* This is the large GOT case. If this is a reference to an 5387 external symbol, and there is no constant, we want 5388 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5389 add $tempreg,$tempreg,$gp 5390 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5391 or for lca or if tempreg is PIC_CALL_REG 5392 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) 5393 add $tempreg,$tempreg,$gp 5394 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) 5395 5396 If we have a small constant, and this is a reference to 5397 an external symbol, we want 5398 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5399 add $tempreg,$tempreg,$gp 5400 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5401 addi $tempreg,$tempreg,<constant> 5402 5403 If we have a large constant, and this is a reference to 5404 an external symbol, we want 5405 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 5406 addu $tempreg,$tempreg,$gp 5407 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 5408 lui $at,<hiconstant> 5409 addi $at,$at,<loconstant> 5410 add $tempreg,$tempreg,$at 5411 5412 If we have NewABI, and we know it's a local symbol, we want 5413 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 5414 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) 5415 otherwise we have to resort to GOT_HI16/GOT_LO16. */ 5416 5417 relax_start (offset_expr.X_add_symbol); 5418 5419 expr1.X_add_number = offset_expr.X_add_number; 5420 offset_expr.X_add_number = 0; 5421 5422 if (expr1.X_add_number == 0 && breg == 0 5423 && (call || tempreg == PIC_CALL_REG)) 5424 { 5425 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; 5426 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; 5427 } 5428 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type); 5429 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5430 tempreg, tempreg, mips_gp_register); 5431 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5432 tempreg, lw_reloc_type, tempreg); 5433 5434 if (expr1.X_add_number == 0) 5435 ; 5436 else if (expr1.X_add_number >= -0x8000 5437 && expr1.X_add_number < 0x8000) 5438 { 5439 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", 5440 tempreg, tempreg, BFD_RELOC_LO16); 5441 } 5442 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) 5443 { 5444 int dreg; 5445 5446 /* If we are going to add in a base register, and the 5447 target register and the base register are the same, 5448 then we are using AT as a temporary register. Since 5449 we want to load the constant into AT, we add our 5450 current AT (from the global offset table) and the 5451 register into the register now, and pretend we were 5452 not using a base register. */ 5453 if (breg != treg) 5454 dreg = tempreg; 5455 else 5456 { 5457 assert (tempreg == AT); 5458 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5459 treg, AT, breg); 5460 dreg = treg; 5461 add_breg_early = 1; 5462 } 5463 5464 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); 5465 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); 5466 5467 used_at = 1; 5468 } 5469 else 5470 as_bad (_("PIC code offset overflow (max 32 signed bits)")); 5471 5472 relax_switch (); 5473 offset_expr.X_add_number = expr1.X_add_number; 5474 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 5475 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 5476 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 5477 tempreg, BFD_RELOC_MIPS_GOT_OFST); 5478 if (add_breg_early) 5479 { 5480 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 5481 treg, tempreg, breg); 5482 breg = 0; 5483 tempreg = treg; 5484 } 5485 relax_end (); 5486 } 5487 else if (mips_pic == EMBEDDED_PIC) 5488 { 5489 /* We use 5490 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) 5491 */ 5492 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 5493 mips_gp_register, BFD_RELOC_GPREL16); 5494 } 5495 else 5496 abort (); 5497 5498 if (breg != 0) 5499 { 5500 char *s; 5501 5502 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC) 5503 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu"; 5504 else 5505 s = ADDRESS_ADD_INSN; 5506 5507 macro_build (NULL, s, "d,v,t", treg, tempreg, breg); 5508 } 5509 5510 if (! used_at) 5511 return; 5512 5513 break; 5514 5515 case M_J_A: 5516 /* The j instruction may not be used in PIC code, since it 5517 requires an absolute address. We convert it to a b 5518 instruction. */ 5519 if (mips_pic == NO_PIC) 5520 macro_build (&offset_expr, "j", "a"); 5521 else 5522 macro_build (&offset_expr, "b", "p"); 5523 return; 5524 5525 /* The jal instructions must be handled as macros because when 5526 generating PIC code they expand to multi-instruction 5527 sequences. Normally they are simple instructions. */ 5528 case M_JAL_1: 5529 dreg = RA; 5530 /* Fall through. */ 5531 case M_JAL_2: 5532 if (mips_pic == NO_PIC 5533 || mips_pic == EMBEDDED_PIC) 5534 macro_build (NULL, "jalr", "d,s", dreg, sreg); 5535 else if (mips_pic == SVR4_PIC) 5536 { 5537 if (sreg != PIC_CALL_REG) 5538 as_warn (_("MIPS PIC call to register other than $25")); 5539 5540 macro_build (NULL, "jalr", "d,s", dreg, sreg); 5541 if (! HAVE_NEWABI) 5542 { 5543 if (mips_cprestore_offset < 0) 5544 as_warn (_("No .cprestore pseudo-op used in PIC code")); 5545 else 5546 { 5547 if (! mips_frame_reg_valid) 5548 { 5549 as_warn (_("No .frame pseudo-op used in PIC code")); 5550 /* Quiet this warning. */ 5551 mips_frame_reg_valid = 1; 5552 } 5553 if (! mips_cprestore_valid) 5554 { 5555 as_warn (_("No .cprestore pseudo-op used in PIC code")); 5556 /* Quiet this warning. */ 5557 mips_cprestore_valid = 1; 5558 } 5559 expr1.X_add_number = mips_cprestore_offset; 5560 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 5561 mips_gp_register, 5562 mips_frame_reg, 5563 HAVE_64BIT_ADDRESSES); 5564 } 5565 } 5566 } 5567 else 5568 abort (); 5569 5570 return; 5571 5572 case M_JAL_A: 5573 if (mips_pic == NO_PIC) 5574 macro_build (&offset_expr, "jal", "a"); 5575 else if (mips_pic == SVR4_PIC) 5576 { 5577 /* If this is a reference to an external symbol, and we are 5578 using a small GOT, we want 5579 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) 5580 nop 5581 jalr $ra,$25 5582 nop 5583 lw $gp,cprestore($sp) 5584 The cprestore value is set using the .cprestore 5585 pseudo-op. If we are using a big GOT, we want 5586 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) 5587 addu $25,$25,$gp 5588 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) 5589 nop 5590 jalr $ra,$25 5591 nop 5592 lw $gp,cprestore($sp) 5593 If the symbol is not external, we want 5594 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 5595 nop 5596 addiu $25,$25,<sym> (BFD_RELOC_LO16) 5597 jalr $ra,$25 5598 nop 5599 lw $gp,cprestore($sp) 5600 5601 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 5602 sequences above, minus nops, unless the symbol is local, 5603 which enables us to use GOT_PAGE/GOT_OFST (big got) or 5604 GOT_DISP. */ 5605 if (HAVE_NEWABI) 5606 { 5607 if (! mips_big_got) 5608 { 5609 relax_start (offset_expr.X_add_symbol); 5610 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5611 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 5612 mips_gp_register); 5613 relax_switch (); 5614 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5615 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, 5616 mips_gp_register); 5617 relax_end (); 5618 } 5619 else 5620 { 5621 relax_start (offset_expr.X_add_symbol); 5622 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, 5623 BFD_RELOC_MIPS_CALL_HI16); 5624 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 5625 PIC_CALL_REG, mips_gp_register); 5626 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5627 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 5628 PIC_CALL_REG); 5629 relax_switch (); 5630 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5631 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, 5632 mips_gp_register); 5633 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5634 PIC_CALL_REG, PIC_CALL_REG, 5635 BFD_RELOC_MIPS_GOT_OFST); 5636 relax_end (); 5637 } 5638 5639 macro_build_jalr (&offset_expr); 5640 } 5641 else 5642 { 5643 relax_start (offset_expr.X_add_symbol); 5644 if (! mips_big_got) 5645 { 5646 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5647 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, 5648 mips_gp_register); 5649 macro_build (NULL, "nop", ""); 5650 relax_switch (); 5651 } 5652 else 5653 { 5654 int gpdelay; 5655 5656 gpdelay = reg_needs_delay (mips_gp_register); 5657 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG, 5658 BFD_RELOC_MIPS_CALL_HI16); 5659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, 5660 PIC_CALL_REG, mips_gp_register); 5661 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5662 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, 5663 PIC_CALL_REG); 5664 macro_build (NULL, "nop", ""); 5665 relax_switch (); 5666 if (gpdelay) 5667 macro_build (NULL, "nop", ""); 5668 } 5669 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 5670 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, 5671 mips_gp_register); 5672 macro_build (NULL, "nop", ""); 5673 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", 5674 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); 5675 relax_end (); 5676 macro_build_jalr (&offset_expr); 5677 5678 if (mips_cprestore_offset < 0) 5679 as_warn (_("No .cprestore pseudo-op used in PIC code")); 5680 else 5681 { 5682 if (! mips_frame_reg_valid) 5683 { 5684 as_warn (_("No .frame pseudo-op used in PIC code")); 5685 /* Quiet this warning. */ 5686 mips_frame_reg_valid = 1; 5687 } 5688 if (! mips_cprestore_valid) 5689 { 5690 as_warn (_("No .cprestore pseudo-op used in PIC code")); 5691 /* Quiet this warning. */ 5692 mips_cprestore_valid = 1; 5693 } 5694 if (mips_opts.noreorder) 5695 macro_build (NULL, "nop", ""); 5696 expr1.X_add_number = mips_cprestore_offset; 5697 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, 5698 mips_gp_register, 5699 mips_frame_reg, 5700 HAVE_64BIT_ADDRESSES); 5701 } 5702 } 5703 } 5704 else if (mips_pic == EMBEDDED_PIC) 5705 { 5706 macro_build (&offset_expr, "bal", "p"); 5707 /* The linker may expand the call to a longer sequence which 5708 uses $at, so we must break rather than return. */ 5709 break; 5710 } 5711 else 5712 abort (); 5713 5714 return; 5715 5716 case M_LB_AB: 5717 s = "lb"; 5718 goto ld; 5719 case M_LBU_AB: 5720 s = "lbu"; 5721 goto ld; 5722 case M_LH_AB: 5723 s = "lh"; 5724 goto ld; 5725 case M_LHU_AB: 5726 s = "lhu"; 5727 goto ld; 5728 case M_LW_AB: 5729 s = "lw"; 5730 goto ld; 5731 case M_LWC0_AB: 5732 s = "lwc0"; 5733 /* Itbl support may require additional care here. */ 5734 coproc = 1; 5735 goto ld; 5736 case M_LWC1_AB: 5737 s = "lwc1"; 5738 /* Itbl support may require additional care here. */ 5739 coproc = 1; 5740 goto ld; 5741 case M_LWC2_AB: 5742 s = "lwc2"; 5743 /* Itbl support may require additional care here. */ 5744 coproc = 1; 5745 goto ld; 5746 case M_LWC3_AB: 5747 s = "lwc3"; 5748 /* Itbl support may require additional care here. */ 5749 coproc = 1; 5750 goto ld; 5751 case M_LWL_AB: 5752 s = "lwl"; 5753 lr = 1; 5754 goto ld; 5755 case M_LWR_AB: 5756 s = "lwr"; 5757 lr = 1; 5758 goto ld; 5759 case M_LDC1_AB: 5760 if (mips_opts.arch == CPU_R4650) 5761 { 5762 as_bad (_("opcode not supported on this processor")); 5763 return; 5764 } 5765 s = "ldc1"; 5766 /* Itbl support may require additional care here. */ 5767 coproc = 1; 5768 goto ld; 5769 case M_LDC2_AB: 5770 s = "ldc2"; 5771 /* Itbl support may require additional care here. */ 5772 coproc = 1; 5773 goto ld; 5774 case M_LDC3_AB: 5775 s = "ldc3"; 5776 /* Itbl support may require additional care here. */ 5777 coproc = 1; 5778 goto ld; 5779 case M_LDL_AB: 5780 s = "ldl"; 5781 lr = 1; 5782 goto ld; 5783 case M_LDR_AB: 5784 s = "ldr"; 5785 lr = 1; 5786 goto ld; 5787 case M_LL_AB: 5788 s = "ll"; 5789 goto ld; 5790 case M_LLD_AB: 5791 s = "lld"; 5792 goto ld; 5793 case M_LWU_AB: 5794 s = "lwu"; 5795 ld: 5796 if (breg == treg || coproc || lr) 5797 { 5798 tempreg = AT; 5799 used_at = 1; 5800 } 5801 else 5802 { 5803 tempreg = treg; 5804 used_at = 0; 5805 } 5806 goto ld_st; 5807 case M_SB_AB: 5808 s = "sb"; 5809 goto st; 5810 case M_SH_AB: 5811 s = "sh"; 5812 goto st; 5813 case M_SW_AB: 5814 s = "sw"; 5815 goto st; 5816 case M_SWC0_AB: 5817 s = "swc0"; 5818 /* Itbl support may require additional care here. */ 5819 coproc = 1; 5820 goto st; 5821 case M_SWC1_AB: 5822 s = "swc1"; 5823 /* Itbl support may require additional care here. */ 5824 coproc = 1; 5825 goto st; 5826 case M_SWC2_AB: 5827 s = "swc2"; 5828 /* Itbl support may require additional care here. */ 5829 coproc = 1; 5830 goto st; 5831 case M_SWC3_AB: 5832 s = "swc3"; 5833 /* Itbl support may require additional care here. */ 5834 coproc = 1; 5835 goto st; 5836 case M_SWL_AB: 5837 s = "swl"; 5838 goto st; 5839 case M_SWR_AB: 5840 s = "swr"; 5841 goto st; 5842 case M_SC_AB: 5843 s = "sc"; 5844 goto st; 5845 case M_SCD_AB: 5846 s = "scd"; 5847 goto st; 5848 case M_SDC1_AB: 5849 if (mips_opts.arch == CPU_R4650) 5850 { 5851 as_bad (_("opcode not supported on this processor")); 5852 return; 5853 } 5854 s = "sdc1"; 5855 coproc = 1; 5856 /* Itbl support may require additional care here. */ 5857 goto st; 5858 case M_SDC2_AB: 5859 s = "sdc2"; 5860 /* Itbl support may require additional care here. */ 5861 coproc = 1; 5862 goto st; 5863 case M_SDC3_AB: 5864 s = "sdc3"; 5865 /* Itbl support may require additional care here. */ 5866 coproc = 1; 5867 goto st; 5868 case M_SDL_AB: 5869 s = "sdl"; 5870 goto st; 5871 case M_SDR_AB: 5872 s = "sdr"; 5873 st: 5874 tempreg = AT; 5875 used_at = 1; 5876 ld_st: 5877 /* Itbl support may require additional care here. */ 5878 if (mask == M_LWC1_AB 5879 || mask == M_SWC1_AB 5880 || mask == M_LDC1_AB 5881 || mask == M_SDC1_AB 5882 || mask == M_L_DAB 5883 || mask == M_S_DAB) 5884 fmt = "T,o(b)"; 5885 else if (coproc) 5886 fmt = "E,o(b)"; 5887 else 5888 fmt = "t,o(b)"; 5889 5890 /* Sign-extending 32-bit constants makes their handling easier. 5891 The HAVE_64BIT_GPRS... part is due to the linux kernel hack 5892 described below. */ 5893 if ((! HAVE_64BIT_ADDRESSES 5894 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant)) 5895 && (offset_expr.X_op == O_constant) 5896 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff)) 5897 == ~((bfd_vma) 0x7fffffff))) 5898 { 5899 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff)) 5900 as_bad (_("constant too large")); 5901 5902 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff) 5903 ^ 0x80000000) - 0x80000000); 5904 } 5905 5906 /* For embedded PIC, we allow loads where the offset is calculated 5907 by subtracting a symbol in the current segment from an unknown 5908 symbol, relative to a base register, e.g.: 5909 <op> $treg, <sym>-<localsym>($breg) 5910 This is used by the compiler for switch statements. */ 5911 if (mips_pic == EMBEDDED_PIC 5912 && offset_expr.X_op == O_subtract 5913 && (symbol_constant_p (offset_expr.X_op_symbol) 5914 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg 5915 : (symbol_equated_p (offset_expr.X_op_symbol) 5916 && (S_GET_SEGMENT 5917 (symbol_get_value_expression (offset_expr.X_op_symbol) 5918 ->X_add_symbol) 5919 == now_seg))) 5920 && breg != 0 5921 && (offset_expr.X_add_number == 0 5922 || OUTPUT_FLAVOR == bfd_target_elf_flavour)) 5923 { 5924 /* For this case, we output the instructions: 5925 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S) 5926 addiu $tempreg,$tempreg,$breg 5927 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16) 5928 If the relocation would fit entirely in 16 bits, it would be 5929 nice to emit: 5930 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16) 5931 instead, but that seems quite difficult. */ 5932 macro_build (&offset_expr, "lui", "t,u", tempreg, 5933 BFD_RELOC_PCREL_HI16_S); 5934 macro_build (NULL, 5935 ((bfd_arch_bits_per_address (stdoutput) == 32 5936 || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) 5937 ? "addu" : "daddu"), 5938 "d,v,t", tempreg, tempreg, breg); 5939 macro_build (&offset_expr, s, fmt, treg, 5940 BFD_RELOC_PCREL_LO16, tempreg); 5941 if (! used_at) 5942 return; 5943 break; 5944 } 5945 5946 if (offset_expr.X_op != O_constant 5947 && offset_expr.X_op != O_symbol) 5948 { 5949 as_bad (_("expression too complex")); 5950 offset_expr.X_op = O_constant; 5951 } 5952 5953 /* A constant expression in PIC code can be handled just as it 5954 is in non PIC code. */ 5955 if (mips_pic == NO_PIC 5956 || offset_expr.X_op == O_constant) 5957 { 5958 /* If this is a reference to a GP relative symbol, and there 5959 is no base register, we want 5960 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 5961 Otherwise, if there is no base register, we want 5962 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 5963 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 5964 If we have a constant, we need two instructions anyhow, 5965 so we always use the latter form. 5966 5967 If we have a base register, and this is a reference to a 5968 GP relative symbol, we want 5969 addu $tempreg,$breg,$gp 5970 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) 5971 Otherwise we want 5972 lui $tempreg,<sym> (BFD_RELOC_HI16_S) 5973 addu $tempreg,$tempreg,$breg 5974 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 5975 With a constant we always use the latter case. 5976 5977 With 64bit address space and no base register and $at usable, 5978 we want 5979 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 5980 lui $at,<sym> (BFD_RELOC_HI16_S) 5981 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 5982 dsll32 $tempreg,0 5983 daddu $tempreg,$at 5984 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 5985 If we have a base register, we want 5986 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 5987 lui $at,<sym> (BFD_RELOC_HI16_S) 5988 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 5989 daddu $at,$breg 5990 dsll32 $tempreg,0 5991 daddu $tempreg,$at 5992 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 5993 5994 Without $at we can't generate the optimal path for superscalar 5995 processors here since this would require two temporary registers. 5996 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 5997 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 5998 dsll $tempreg,16 5999 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 6000 dsll $tempreg,16 6001 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6002 If we have a base register, we want 6003 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) 6004 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) 6005 dsll $tempreg,16 6006 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) 6007 dsll $tempreg,16 6008 daddu $tempreg,$tempreg,$breg 6009 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) 6010 6011 If we have 64-bit addresses, as an optimization, for 6012 addresses which are 32-bit constants (e.g. kseg0/kseg1 6013 addresses) we fall back to the 32-bit address generation 6014 mechanism since it is more efficient. Note that due to 6015 the signed offset used by memory operations, the 32-bit 6016 range is shifted down by 32768 here. This code should 6017 probably attempt to generate 64-bit constants more 6018 efficiently in general. 6019 6020 As an extension for architectures with 64-bit registers, 6021 we don't truncate 64-bit addresses given as literal 6022 constants down to 32 bits, to support existing practice 6023 in the mips64 Linux (the kernel), that compiles source 6024 files with -mabi=64, assembling them as o32 or n32 (with 6025 -Wa,-32 or -Wa,-n32). This is not beautiful, but since 6026 the whole kernel is loaded into a memory region that is 6027 addressable with sign-extended 32-bit addresses, it is 6028 wasteful to compute the upper 32 bits of every 6029 non-literal address, that takes more space and time. 6030 Some day this should probably be implemented as an 6031 assembler option, such that the kernel doesn't have to 6032 use such ugly hacks, even though it will still have to 6033 end up converting the binary to ELF32 for a number of 6034 platforms whose boot loaders don't support ELF64 6035 binaries. */ 6036 if ((HAVE_64BIT_ADDRESSES 6037 && ! (offset_expr.X_op == O_constant 6038 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) 6039 || (HAVE_64BIT_GPRS 6040 && offset_expr.X_op == O_constant 6041 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))) 6042 { 6043 /* ??? We don't provide a GP-relative alternative for 6044 these macros. It used not to be possible with the 6045 original relaxation code, but it could be done now. */ 6046 6047 if (used_at == 0 && ! mips_opts.noat) 6048 { 6049 macro_build (&offset_expr, "lui", "t,u", tempreg, 6050 BFD_RELOC_MIPS_HIGHEST); 6051 macro_build (&offset_expr, "lui", "t,u", AT, 6052 BFD_RELOC_HI16_S); 6053 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 6054 tempreg, BFD_RELOC_MIPS_HIGHER); 6055 if (breg != 0) 6056 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); 6057 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0); 6058 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); 6059 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, 6060 tempreg); 6061 used_at = 1; 6062 } 6063 else 6064 { 6065 macro_build (&offset_expr, "lui", "t,u", tempreg, 6066 BFD_RELOC_MIPS_HIGHEST); 6067 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 6068 tempreg, BFD_RELOC_MIPS_HIGHER); 6069 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 6070 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, 6071 tempreg, BFD_RELOC_HI16_S); 6072 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16); 6073 if (breg != 0) 6074 macro_build (NULL, "daddu", "d,v,t", 6075 tempreg, tempreg, breg); 6076 macro_build (&offset_expr, s, fmt, treg, 6077 BFD_RELOC_LO16, tempreg); 6078 } 6079 6080 return; 6081 } 6082 6083 if (offset_expr.X_op == O_constant 6084 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)) 6085 as_bad (_("load/store address overflow (max 32 bits)")); 6086 6087 if (breg == 0) 6088 { 6089 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 6090 && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) 6091 { 6092 relax_start (offset_expr.X_add_symbol); 6093 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, 6094 mips_gp_register); 6095 relax_switch (); 6096 used_at = 0; 6097 } 6098 macro_build_lui (&offset_expr, tempreg); 6099 macro_build (&offset_expr, s, fmt, treg, 6100 BFD_RELOC_LO16, tempreg); 6101 if (mips_relax.sequence) 6102 relax_end (); 6103 } 6104 else 6105 { 6106 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET 6107 && ! nopic_need_relax (offset_expr.X_add_symbol, 1)) 6108 { 6109 relax_start (offset_expr.X_add_symbol); 6110 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6111 tempreg, breg, mips_gp_register); 6112 macro_build (&offset_expr, s, fmt, treg, 6113 BFD_RELOC_GPREL16, tempreg); 6114 relax_switch (); 6115 } 6116 macro_build_lui (&offset_expr, tempreg); 6117 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6118 tempreg, tempreg, breg); 6119 macro_build (&offset_expr, s, fmt, treg, 6120 BFD_RELOC_LO16, tempreg); 6121 if (mips_relax.sequence) 6122 relax_end (); 6123 } 6124 } 6125 else if (mips_pic == SVR4_PIC && ! mips_big_got) 6126 { 6127 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; 6128 6129 /* If this is a reference to an external symbol, we want 6130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6131 nop 6132 <op> $treg,0($tempreg) 6133 Otherwise we want 6134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6135 nop 6136 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 6137 <op> $treg,0($tempreg) 6138 6139 For NewABI, we want 6140 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 6141 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) 6142 6143 If there is a base register, we add it to $tempreg before 6144 the <op>. If there is a constant, we stick it in the 6145 <op> instruction. We don't handle constants larger than 6146 16 bits, because we have no way to load the upper 16 bits 6147 (actually, we could handle them for the subset of cases 6148 in which we are not using $at). */ 6149 assert (offset_expr.X_op == O_symbol); 6150 if (HAVE_NEWABI) 6151 { 6152 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6153 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 6154 if (breg != 0) 6155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6156 tempreg, tempreg, breg); 6157 macro_build (&offset_expr, s, fmt, treg, 6158 BFD_RELOC_MIPS_GOT_OFST, tempreg); 6159 6160 if (! used_at) 6161 return; 6162 6163 break; 6164 } 6165 expr1.X_add_number = offset_expr.X_add_number; 6166 offset_expr.X_add_number = 0; 6167 if (expr1.X_add_number < -0x8000 6168 || expr1.X_add_number >= 0x8000) 6169 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6170 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6171 lw_reloc_type, mips_gp_register); 6172 macro_build (NULL, "nop", ""); 6173 relax_start (offset_expr.X_add_symbol); 6174 relax_switch (); 6175 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 6176 tempreg, BFD_RELOC_LO16); 6177 relax_end (); 6178 if (breg != 0) 6179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6180 tempreg, tempreg, breg); 6181 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6182 } 6183 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI) 6184 { 6185 int gpdelay; 6186 6187 /* If this is a reference to an external symbol, we want 6188 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 6189 addu $tempreg,$tempreg,$gp 6190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 6191 <op> $treg,0($tempreg) 6192 Otherwise we want 6193 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6194 nop 6195 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) 6196 <op> $treg,0($tempreg) 6197 If there is a base register, we add it to $tempreg before 6198 the <op>. If there is a constant, we stick it in the 6199 <op> instruction. We don't handle constants larger than 6200 16 bits, because we have no way to load the upper 16 bits 6201 (actually, we could handle them for the subset of cases 6202 in which we are not using $at). */ 6203 assert (offset_expr.X_op == O_symbol); 6204 expr1.X_add_number = offset_expr.X_add_number; 6205 offset_expr.X_add_number = 0; 6206 if (expr1.X_add_number < -0x8000 6207 || expr1.X_add_number >= 0x8000) 6208 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6209 gpdelay = reg_needs_delay (mips_gp_register); 6210 relax_start (offset_expr.X_add_symbol); 6211 macro_build (&offset_expr, "lui", "t,u", tempreg, 6212 BFD_RELOC_MIPS_GOT_HI16); 6213 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 6214 mips_gp_register); 6215 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6216 BFD_RELOC_MIPS_GOT_LO16, tempreg); 6217 relax_switch (); 6218 if (gpdelay) 6219 macro_build (NULL, "nop", ""); 6220 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6221 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6222 macro_build (NULL, "nop", ""); 6223 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, 6224 tempreg, BFD_RELOC_LO16); 6225 relax_end (); 6226 6227 if (breg != 0) 6228 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6229 tempreg, tempreg, breg); 6230 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6231 } 6232 else if (mips_pic == SVR4_PIC && HAVE_NEWABI) 6233 { 6234 /* If this is a reference to an external symbol, we want 6235 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) 6236 add $tempreg,$tempreg,$gp 6237 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) 6238 <op> $treg,<ofst>($tempreg) 6239 Otherwise, for local symbols, we want: 6240 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) 6241 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ 6242 assert (offset_expr.X_op == O_symbol); 6243 expr1.X_add_number = offset_expr.X_add_number; 6244 offset_expr.X_add_number = 0; 6245 if (expr1.X_add_number < -0x8000 6246 || expr1.X_add_number >= 0x8000) 6247 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6248 relax_start (offset_expr.X_add_symbol); 6249 macro_build (&offset_expr, "lui", "t,u", tempreg, 6250 BFD_RELOC_MIPS_GOT_HI16); 6251 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, 6252 mips_gp_register); 6253 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6254 BFD_RELOC_MIPS_GOT_LO16, tempreg); 6255 if (breg != 0) 6256 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6257 tempreg, tempreg, breg); 6258 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg); 6259 6260 relax_switch (); 6261 offset_expr.X_add_number = expr1.X_add_number; 6262 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, 6263 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); 6264 if (breg != 0) 6265 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6266 tempreg, tempreg, breg); 6267 macro_build (&offset_expr, s, fmt, treg, 6268 BFD_RELOC_MIPS_GOT_OFST, tempreg); 6269 relax_end (); 6270 } 6271 else if (mips_pic == EMBEDDED_PIC) 6272 { 6273 /* If there is no base register, we want 6274 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 6275 If there is a base register, we want 6276 addu $tempreg,$breg,$gp 6277 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16) 6278 */ 6279 assert (offset_expr.X_op == O_symbol); 6280 if (breg == 0) 6281 { 6282 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16, 6283 mips_gp_register); 6284 used_at = 0; 6285 } 6286 else 6287 { 6288 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6289 tempreg, breg, mips_gp_register); 6290 macro_build (&offset_expr, s, fmt, treg, 6291 BFD_RELOC_GPREL16, tempreg); 6292 } 6293 } 6294 else 6295 abort (); 6296 6297 if (! used_at) 6298 return; 6299 6300 break; 6301 6302 case M_LI: 6303 case M_LI_S: 6304 load_register (treg, &imm_expr, 0); 6305 return; 6306 6307 case M_DLI: 6308 load_register (treg, &imm_expr, 1); 6309 return; 6310 6311 case M_LI_SS: 6312 if (imm_expr.X_op == O_constant) 6313 { 6314 load_register (AT, &imm_expr, 0); 6315 macro_build (NULL, "mtc1", "t,G", AT, treg); 6316 break; 6317 } 6318 else 6319 { 6320 assert (offset_expr.X_op == O_symbol 6321 && strcmp (segment_name (S_GET_SEGMENT 6322 (offset_expr.X_add_symbol)), 6323 ".lit4") == 0 6324 && offset_expr.X_add_number == 0); 6325 macro_build (&offset_expr, "lwc1", "T,o(b)", treg, 6326 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 6327 return; 6328 } 6329 6330 case M_LI_D: 6331 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits 6332 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high 6333 order 32 bits of the value and the low order 32 bits are either 6334 zero or in OFFSET_EXPR. */ 6335 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) 6336 { 6337 if (HAVE_64BIT_GPRS) 6338 load_register (treg, &imm_expr, 1); 6339 else 6340 { 6341 int hreg, lreg; 6342 6343 if (target_big_endian) 6344 { 6345 hreg = treg; 6346 lreg = treg + 1; 6347 } 6348 else 6349 { 6350 hreg = treg + 1; 6351 lreg = treg; 6352 } 6353 6354 if (hreg <= 31) 6355 load_register (hreg, &imm_expr, 0); 6356 if (lreg <= 31) 6357 { 6358 if (offset_expr.X_op == O_absent) 6359 move_register (lreg, 0); 6360 else 6361 { 6362 assert (offset_expr.X_op == O_constant); 6363 load_register (lreg, &offset_expr, 0); 6364 } 6365 } 6366 } 6367 return; 6368 } 6369 6370 /* We know that sym is in the .rdata section. First we get the 6371 upper 16 bits of the address. */ 6372 if (mips_pic == NO_PIC) 6373 { 6374 macro_build_lui (&offset_expr, AT); 6375 } 6376 else if (mips_pic == SVR4_PIC) 6377 { 6378 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 6379 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6380 } 6381 else if (mips_pic == EMBEDDED_PIC) 6382 { 6383 /* For embedded PIC we pick up the entire address off $gp in 6384 a single instruction. */ 6385 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, 6386 mips_gp_register, BFD_RELOC_GPREL16); 6387 offset_expr.X_op = O_constant; 6388 offset_expr.X_add_number = 0; 6389 } 6390 else 6391 abort (); 6392 6393 /* Now we load the register(s). */ 6394 if (HAVE_64BIT_GPRS) 6395 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT); 6396 else 6397 { 6398 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT); 6399 if (treg != RA) 6400 { 6401 /* FIXME: How in the world do we deal with the possible 6402 overflow here? */ 6403 offset_expr.X_add_number += 4; 6404 macro_build (&offset_expr, "lw", "t,o(b)", 6405 treg + 1, BFD_RELOC_LO16, AT); 6406 } 6407 } 6408 break; 6409 6410 case M_LI_DD: 6411 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits 6412 wide, IMM_EXPR is the entire value and the GPRs are known to be 64 6413 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of 6414 the value and the low order 32 bits are either zero or in 6415 OFFSET_EXPR. */ 6416 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) 6417 { 6418 load_register (AT, &imm_expr, HAVE_64BIT_FPRS); 6419 if (HAVE_64BIT_FPRS) 6420 { 6421 assert (HAVE_64BIT_GPRS); 6422 macro_build (NULL, "dmtc1", "t,S", AT, treg); 6423 } 6424 else 6425 { 6426 macro_build (NULL, "mtc1", "t,G", AT, treg + 1); 6427 if (offset_expr.X_op == O_absent) 6428 macro_build (NULL, "mtc1", "t,G", 0, treg); 6429 else 6430 { 6431 assert (offset_expr.X_op == O_constant); 6432 load_register (AT, &offset_expr, 0); 6433 macro_build (NULL, "mtc1", "t,G", AT, treg); 6434 } 6435 } 6436 break; 6437 } 6438 6439 assert (offset_expr.X_op == O_symbol 6440 && offset_expr.X_add_number == 0); 6441 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); 6442 if (strcmp (s, ".lit8") == 0) 6443 { 6444 if (mips_opts.isa != ISA_MIPS1) 6445 { 6446 macro_build (&offset_expr, "ldc1", "T,o(b)", treg, 6447 BFD_RELOC_MIPS_LITERAL, mips_gp_register); 6448 return; 6449 } 6450 breg = mips_gp_register; 6451 r = BFD_RELOC_MIPS_LITERAL; 6452 goto dob; 6453 } 6454 else 6455 { 6456 assert (strcmp (s, RDATA_SECTION_NAME) == 0); 6457 if (mips_pic == SVR4_PIC) 6458 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 6459 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6460 else 6461 { 6462 /* FIXME: This won't work for a 64 bit address. */ 6463 macro_build_lui (&offset_expr, AT); 6464 } 6465 6466 if (mips_opts.isa != ISA_MIPS1) 6467 { 6468 macro_build (&offset_expr, "ldc1", "T,o(b)", 6469 treg, BFD_RELOC_LO16, AT); 6470 break; 6471 } 6472 breg = AT; 6473 r = BFD_RELOC_LO16; 6474 goto dob; 6475 } 6476 6477 case M_L_DOB: 6478 if (mips_opts.arch == CPU_R4650) 6479 { 6480 as_bad (_("opcode not supported on this processor")); 6481 return; 6482 } 6483 /* Even on a big endian machine $fn comes before $fn+1. We have 6484 to adjust when loading from memory. */ 6485 r = BFD_RELOC_LO16; 6486 dob: 6487 assert (mips_opts.isa == ISA_MIPS1); 6488 macro_build (&offset_expr, "lwc1", "T,o(b)", 6489 target_big_endian ? treg + 1 : treg, r, breg); 6490 /* FIXME: A possible overflow which I don't know how to deal 6491 with. */ 6492 offset_expr.X_add_number += 4; 6493 macro_build (&offset_expr, "lwc1", "T,o(b)", 6494 target_big_endian ? treg : treg + 1, r, breg); 6495 6496 if (breg != AT) 6497 return; 6498 break; 6499 6500 case M_L_DAB: 6501 /* 6502 * The MIPS assembler seems to check for X_add_number not 6503 * being double aligned and generating: 6504 * lui at,%hi(foo+1) 6505 * addu at,at,v1 6506 * addiu at,at,%lo(foo+1) 6507 * lwc1 f2,0(at) 6508 * lwc1 f3,4(at) 6509 * But, the resulting address is the same after relocation so why 6510 * generate the extra instruction? 6511 */ 6512 if (mips_opts.arch == CPU_R4650) 6513 { 6514 as_bad (_("opcode not supported on this processor")); 6515 return; 6516 } 6517 /* Itbl support may require additional care here. */ 6518 coproc = 1; 6519 if (mips_opts.isa != ISA_MIPS1) 6520 { 6521 s = "ldc1"; 6522 goto ld; 6523 } 6524 6525 s = "lwc1"; 6526 fmt = "T,o(b)"; 6527 goto ldd_std; 6528 6529 case M_S_DAB: 6530 if (mips_opts.arch == CPU_R4650) 6531 { 6532 as_bad (_("opcode not supported on this processor")); 6533 return; 6534 } 6535 6536 if (mips_opts.isa != ISA_MIPS1) 6537 { 6538 s = "sdc1"; 6539 goto st; 6540 } 6541 6542 s = "swc1"; 6543 fmt = "T,o(b)"; 6544 /* Itbl support may require additional care here. */ 6545 coproc = 1; 6546 goto ldd_std; 6547 6548 case M_LD_AB: 6549 if (HAVE_64BIT_GPRS) 6550 { 6551 s = "ld"; 6552 goto ld; 6553 } 6554 6555 s = "lw"; 6556 fmt = "t,o(b)"; 6557 goto ldd_std; 6558 6559 case M_SD_AB: 6560 if (HAVE_64BIT_GPRS) 6561 { 6562 s = "sd"; 6563 goto st; 6564 } 6565 6566 s = "sw"; 6567 fmt = "t,o(b)"; 6568 6569 ldd_std: 6570 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol) 6571 loads for the case of doing a pair of loads to simulate an 'ld'. 6572 This is not currently done by the compiler, and assembly coders 6573 writing embedded-pic code can cope. */ 6574 6575 if (offset_expr.X_op != O_symbol 6576 && offset_expr.X_op != O_constant) 6577 { 6578 as_bad (_("expression too complex")); 6579 offset_expr.X_op = O_constant; 6580 } 6581 6582 /* Even on a big endian machine $fn comes before $fn+1. We have 6583 to adjust when loading from memory. We set coproc if we must 6584 load $fn+1 first. */ 6585 /* Itbl support may require additional care here. */ 6586 if (! target_big_endian) 6587 coproc = 0; 6588 6589 if (mips_pic == NO_PIC 6590 || offset_expr.X_op == O_constant) 6591 { 6592 /* If this is a reference to a GP relative symbol, we want 6593 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 6594 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) 6595 If we have a base register, we use this 6596 addu $at,$breg,$gp 6597 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) 6598 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) 6599 If this is not a GP relative symbol, we want 6600 lui $at,<sym> (BFD_RELOC_HI16_S) 6601 <op> $treg,<sym>($at) (BFD_RELOC_LO16) 6602 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) 6603 If there is a base register, we add it to $at after the 6604 lui instruction. If there is a constant, we always use 6605 the last case. */ 6606 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET 6607 || nopic_need_relax (offset_expr.X_add_symbol, 1)) 6608 used_at = 1; 6609 else 6610 { 6611 relax_start (offset_expr.X_add_symbol); 6612 if (breg == 0) 6613 { 6614 tempreg = mips_gp_register; 6615 used_at = 0; 6616 } 6617 else 6618 { 6619 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6620 AT, breg, mips_gp_register); 6621 tempreg = AT; 6622 used_at = 1; 6623 } 6624 6625 /* Itbl support may require additional care here. */ 6626 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 6627 BFD_RELOC_GPREL16, tempreg); 6628 offset_expr.X_add_number += 4; 6629 6630 /* Set mips_optimize to 2 to avoid inserting an 6631 undesired nop. */ 6632 hold_mips_optimize = mips_optimize; 6633 mips_optimize = 2; 6634 /* Itbl support may require additional care here. */ 6635 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 6636 BFD_RELOC_GPREL16, tempreg); 6637 mips_optimize = hold_mips_optimize; 6638 6639 relax_switch (); 6640 6641 /* We just generated two relocs. When tc_gen_reloc 6642 handles this case, it will skip the first reloc and 6643 handle the second. The second reloc already has an 6644 extra addend of 4, which we added above. We must 6645 subtract it out, and then subtract another 4 to make 6646 the first reloc come out right. The second reloc 6647 will come out right because we are going to add 4 to 6648 offset_expr when we build its instruction below. 6649 6650 If we have a symbol, then we don't want to include 6651 the offset, because it will wind up being included 6652 when we generate the reloc. */ 6653 6654 if (offset_expr.X_op == O_constant) 6655 offset_expr.X_add_number -= 8; 6656 else 6657 { 6658 offset_expr.X_add_number = -4; 6659 offset_expr.X_op = O_constant; 6660 } 6661 } 6662 macro_build_lui (&offset_expr, AT); 6663 if (breg != 0) 6664 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 6665 /* Itbl support may require additional care here. */ 6666 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 6667 BFD_RELOC_LO16, AT); 6668 /* FIXME: How do we handle overflow here? */ 6669 offset_expr.X_add_number += 4; 6670 /* Itbl support may require additional care here. */ 6671 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 6672 BFD_RELOC_LO16, AT); 6673 if (mips_relax.sequence) 6674 relax_end (); 6675 } 6676 else if (mips_pic == SVR4_PIC && ! mips_big_got) 6677 { 6678 /* If this is a reference to an external symbol, we want 6679 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6680 nop 6681 <op> $treg,0($at) 6682 <op> $treg+1,4($at) 6683 Otherwise we want 6684 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6685 nop 6686 <op> $treg,<sym>($at) (BFD_RELOC_LO16) 6687 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) 6688 If there is a base register we add it to $at before the 6689 lwc1 instructions. If there is a constant we include it 6690 in the lwc1 instructions. */ 6691 used_at = 1; 6692 expr1.X_add_number = offset_expr.X_add_number; 6693 if (expr1.X_add_number < -0x8000 6694 || expr1.X_add_number >= 0x8000 - 4) 6695 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6696 load_got_offset (AT, &offset_expr); 6697 macro_build (NULL, "nop", ""); 6698 if (breg != 0) 6699 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 6700 6701 /* Set mips_optimize to 2 to avoid inserting an undesired 6702 nop. */ 6703 hold_mips_optimize = mips_optimize; 6704 mips_optimize = 2; 6705 6706 /* Itbl support may require additional care here. */ 6707 relax_start (offset_expr.X_add_symbol); 6708 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, 6709 BFD_RELOC_LO16, AT); 6710 expr1.X_add_number += 4; 6711 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, 6712 BFD_RELOC_LO16, AT); 6713 relax_switch (); 6714 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 6715 BFD_RELOC_LO16, AT); 6716 offset_expr.X_add_number += 4; 6717 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 6718 BFD_RELOC_LO16, AT); 6719 relax_end (); 6720 6721 mips_optimize = hold_mips_optimize; 6722 } 6723 else if (mips_pic == SVR4_PIC) 6724 { 6725 int gpdelay; 6726 6727 /* If this is a reference to an external symbol, we want 6728 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) 6729 addu $at,$at,$gp 6730 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) 6731 nop 6732 <op> $treg,0($at) 6733 <op> $treg+1,4($at) 6734 Otherwise we want 6735 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) 6736 nop 6737 <op> $treg,<sym>($at) (BFD_RELOC_LO16) 6738 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) 6739 If there is a base register we add it to $at before the 6740 lwc1 instructions. If there is a constant we include it 6741 in the lwc1 instructions. */ 6742 used_at = 1; 6743 expr1.X_add_number = offset_expr.X_add_number; 6744 offset_expr.X_add_number = 0; 6745 if (expr1.X_add_number < -0x8000 6746 || expr1.X_add_number >= 0x8000 - 4) 6747 as_bad (_("PIC code offset overflow (max 16 signed bits)")); 6748 gpdelay = reg_needs_delay (mips_gp_register); 6749 relax_start (offset_expr.X_add_symbol); 6750 macro_build (&offset_expr, "lui", "t,u", 6751 AT, BFD_RELOC_MIPS_GOT_HI16); 6752 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6753 AT, AT, mips_gp_register); 6754 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", 6755 AT, BFD_RELOC_MIPS_GOT_LO16, AT); 6756 macro_build (NULL, "nop", ""); 6757 if (breg != 0) 6758 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 6759 /* Itbl support may require additional care here. */ 6760 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg, 6761 BFD_RELOC_LO16, AT); 6762 expr1.X_add_number += 4; 6763 6764 /* Set mips_optimize to 2 to avoid inserting an undesired 6765 nop. */ 6766 hold_mips_optimize = mips_optimize; 6767 mips_optimize = 2; 6768 /* Itbl support may require additional care here. */ 6769 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1, 6770 BFD_RELOC_LO16, AT); 6771 mips_optimize = hold_mips_optimize; 6772 expr1.X_add_number -= 4; 6773 6774 relax_switch (); 6775 offset_expr.X_add_number = expr1.X_add_number; 6776 if (gpdelay) 6777 macro_build (NULL, "nop", ""); 6778 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, 6779 BFD_RELOC_MIPS_GOT16, mips_gp_register); 6780 macro_build (NULL, "nop", ""); 6781 if (breg != 0) 6782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); 6783 /* Itbl support may require additional care here. */ 6784 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 6785 BFD_RELOC_LO16, AT); 6786 offset_expr.X_add_number += 4; 6787 6788 /* Set mips_optimize to 2 to avoid inserting an undesired 6789 nop. */ 6790 hold_mips_optimize = mips_optimize; 6791 mips_optimize = 2; 6792 /* Itbl support may require additional care here. */ 6793 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 6794 BFD_RELOC_LO16, AT); 6795 mips_optimize = hold_mips_optimize; 6796 relax_end (); 6797 } 6798 else if (mips_pic == EMBEDDED_PIC) 6799 { 6800 /* If there is no base register, we use 6801 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16) 6802 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16) 6803 If we have a base register, we use 6804 addu $at,$breg,$gp 6805 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16) 6806 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16) 6807 */ 6808 if (breg == 0) 6809 { 6810 tempreg = mips_gp_register; 6811 used_at = 0; 6812 } 6813 else 6814 { 6815 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", 6816 AT, breg, mips_gp_register); 6817 tempreg = AT; 6818 used_at = 1; 6819 } 6820 6821 /* Itbl support may require additional care here. */ 6822 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg, 6823 BFD_RELOC_GPREL16, tempreg); 6824 offset_expr.X_add_number += 4; 6825 /* Itbl support may require additional care here. */ 6826 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1, 6827 BFD_RELOC_GPREL16, tempreg); 6828 } 6829 else 6830 abort (); 6831 6832 if (! used_at) 6833 return; 6834 6835 break; 6836 6837 case M_LD_OB: 6838 s = "lw"; 6839 goto sd_ob; 6840 case M_SD_OB: 6841 s = "sw"; 6842 sd_ob: 6843 assert (HAVE_32BIT_ADDRESSES); 6844 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); 6845 offset_expr.X_add_number += 4; 6846 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg); 6847 return; 6848 6849 /* New code added to support COPZ instructions. 6850 This code builds table entries out of the macros in mip_opcodes. 6851 R4000 uses interlocks to handle coproc delays. 6852 Other chips (like the R3000) require nops to be inserted for delays. 6853 6854 FIXME: Currently, we require that the user handle delays. 6855 In order to fill delay slots for non-interlocked chips, 6856 we must have a way to specify delays based on the coprocessor. 6857 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. 6858 What are the side-effects of the cop instruction? 6859 What cache support might we have and what are its effects? 6860 Both coprocessor & memory require delays. how long??? 6861 What registers are read/set/modified? 6862 6863 If an itbl is provided to interpret cop instructions, 6864 this knowledge can be encoded in the itbl spec. */ 6865 6866 case M_COP0: 6867 s = "c0"; 6868 goto copz; 6869 case M_COP1: 6870 s = "c1"; 6871 goto copz; 6872 case M_COP2: 6873 s = "c2"; 6874 goto copz; 6875 case M_COP3: 6876 s = "c3"; 6877 copz: 6878 /* For now we just do C (same as Cz). The parameter will be 6879 stored in insn_opcode by mips_ip. */ 6880 macro_build (NULL, s, "C", ip->insn_opcode); 6881 return; 6882 6883 case M_MOVE: 6884 move_register (dreg, sreg); 6885 return; 6886 6887#ifdef LOSING_COMPILER 6888 default: 6889 /* Try and see if this is a new itbl instruction. 6890 This code builds table entries out of the macros in mip_opcodes. 6891 FIXME: For now we just assemble the expression and pass it's 6892 value along as a 32-bit immediate. 6893 We may want to have the assembler assemble this value, 6894 so that we gain the assembler's knowledge of delay slots, 6895 symbols, etc. 6896 Would it be more efficient to use mask (id) here? */ 6897 if (itbl_have_entries 6898 && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) 6899 { 6900 s = ip->insn_mo->name; 6901 s2 = "cop3"; 6902 coproc = ITBL_DECODE_PNUM (immed_expr);; 6903 macro_build (&immed_expr, s, "C"); 6904 return; 6905 } 6906 macro2 (ip); 6907 return; 6908 } 6909 if (mips_opts.noat) 6910 as_warn (_("Macro used $at after \".set noat\"")); 6911} 6912 6913static void 6914macro2 (struct mips_cl_insn *ip) 6915{ 6916 register int treg, sreg, dreg, breg; 6917 int tempreg; 6918 int mask; 6919 int used_at; 6920 expressionS expr1; 6921 const char *s; 6922 const char *s2; 6923 const char *fmt; 6924 int likely = 0; 6925 int dbl = 0; 6926 int coproc = 0; 6927 int lr = 0; 6928 int imm = 0; 6929 int off; 6930 offsetT maxnum; 6931 bfd_reloc_code_real_type r; 6932 6933 treg = (ip->insn_opcode >> 16) & 0x1f; 6934 dreg = (ip->insn_opcode >> 11) & 0x1f; 6935 sreg = breg = (ip->insn_opcode >> 21) & 0x1f; 6936 mask = ip->insn_mo->mask; 6937 6938 expr1.X_op = O_constant; 6939 expr1.X_op_symbol = NULL; 6940 expr1.X_add_symbol = NULL; 6941 expr1.X_add_number = 1; 6942 6943 switch (mask) 6944 { 6945#endif /* LOSING_COMPILER */ 6946 6947 case M_DMUL: 6948 dbl = 1; 6949 case M_MUL: 6950 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg); 6951 macro_build (NULL, "mflo", "d", dreg); 6952 return; 6953 6954 case M_DMUL_I: 6955 dbl = 1; 6956 case M_MUL_I: 6957 /* The MIPS assembler some times generates shifts and adds. I'm 6958 not trying to be that fancy. GCC should do this for us 6959 anyway. */ 6960 load_register (AT, &imm_expr, dbl); 6961 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT); 6962 macro_build (NULL, "mflo", "d", dreg); 6963 break; 6964 6965 case M_DMULO_I: 6966 dbl = 1; 6967 case M_MULO_I: 6968 imm = 1; 6969 goto do_mulo; 6970 6971 case M_DMULO: 6972 dbl = 1; 6973 case M_MULO: 6974 do_mulo: 6975 mips_emit_delays (TRUE); 6976 ++mips_opts.noreorder; 6977 mips_any_noreorder = 1; 6978 if (imm) 6979 load_register (AT, &imm_expr, dbl); 6980 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); 6981 macro_build (NULL, "mflo", "d", dreg); 6982 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA); 6983 macro_build (NULL, "mfhi", "d", AT); 6984 if (mips_trap) 6985 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6); 6986 else 6987 { 6988 expr1.X_add_number = 8; 6989 macro_build (&expr1, "beq", "s,t,p", dreg, AT); 6990 macro_build (NULL, "nop", "", 0); 6991 macro_build (NULL, "break", "c", 6); 6992 } 6993 --mips_opts.noreorder; 6994 macro_build (NULL, "mflo", "d", dreg); 6995 break; 6996 6997 case M_DMULOU_I: 6998 dbl = 1; 6999 case M_MULOU_I: 7000 imm = 1; 7001 goto do_mulou; 7002 7003 case M_DMULOU: 7004 dbl = 1; 7005 case M_MULOU: 7006 do_mulou: 7007 mips_emit_delays (TRUE); 7008 ++mips_opts.noreorder; 7009 mips_any_noreorder = 1; 7010 if (imm) 7011 load_register (AT, &imm_expr, dbl); 7012 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", 7013 sreg, imm ? AT : treg); 7014 macro_build (NULL, "mfhi", "d", AT); 7015 macro_build (NULL, "mflo", "d", dreg); 7016 if (mips_trap) 7017 macro_build (NULL, "tne", "s,t,q", AT, 0, 6); 7018 else 7019 { 7020 expr1.X_add_number = 8; 7021 macro_build (&expr1, "beq", "s,t,p", AT, 0); 7022 macro_build (NULL, "nop", "", 0); 7023 macro_build (NULL, "break", "c", 6); 7024 } 7025 --mips_opts.noreorder; 7026 break; 7027 7028 case M_DROL: 7029 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7030 { 7031 if (dreg == sreg) 7032 { 7033 tempreg = AT; 7034 used_at = 1; 7035 } 7036 else 7037 { 7038 tempreg = dreg; 7039 used_at = 0; 7040 } 7041 macro_build (NULL, "dnegu", "d,w", tempreg, treg); 7042 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg); 7043 if (used_at) 7044 break; 7045 return; 7046 } 7047 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); 7048 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT); 7049 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg); 7050 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7051 break; 7052 7053 case M_ROL: 7054 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7055 { 7056 if (dreg == sreg) 7057 { 7058 tempreg = AT; 7059 used_at = 1; 7060 } 7061 else 7062 { 7063 tempreg = dreg; 7064 used_at = 0; 7065 } 7066 macro_build (NULL, "negu", "d,w", tempreg, treg); 7067 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg); 7068 if (used_at) 7069 break; 7070 return; 7071 } 7072 macro_build (NULL, "subu", "d,v,t", AT, 0, treg); 7073 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT); 7074 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg); 7075 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7076 break; 7077 7078 case M_DROL_I: 7079 { 7080 unsigned int rot; 7081 char *l, *r; 7082 7083 if (imm_expr.X_op != O_constant) 7084 as_bad (_("Improper rotate count")); 7085 rot = imm_expr.X_add_number & 0x3f; 7086 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7087 { 7088 rot = (64 - rot) & 0x3f; 7089 if (rot >= 32) 7090 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); 7091 else 7092 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); 7093 return; 7094 } 7095 if (rot == 0) 7096 { 7097 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); 7098 return; 7099 } 7100 l = (rot < 0x20) ? "dsll" : "dsll32"; 7101 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; 7102 rot &= 0x1f; 7103 macro_build (NULL, l, "d,w,<", AT, sreg, rot); 7104 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7105 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7106 } 7107 break; 7108 7109 case M_ROL_I: 7110 { 7111 unsigned int rot; 7112 7113 if (imm_expr.X_op != O_constant) 7114 as_bad (_("Improper rotate count")); 7115 rot = imm_expr.X_add_number & 0x1f; 7116 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7117 { 7118 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f); 7119 return; 7120 } 7121 if (rot == 0) 7122 { 7123 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); 7124 return; 7125 } 7126 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot); 7127 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7128 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7129 } 7130 break; 7131 7132 case M_DROR: 7133 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7134 { 7135 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg); 7136 return; 7137 } 7138 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg); 7139 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT); 7140 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg); 7141 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7142 break; 7143 7144 case M_ROR: 7145 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7146 { 7147 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg); 7148 return; 7149 } 7150 macro_build (NULL, "subu", "d,v,t", AT, 0, treg); 7151 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT); 7152 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg); 7153 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7154 break; 7155 7156 case M_DROR_I: 7157 { 7158 unsigned int rot; 7159 char *l, *r; 7160 7161 if (imm_expr.X_op != O_constant) 7162 as_bad (_("Improper rotate count")); 7163 rot = imm_expr.X_add_number & 0x3f; 7164 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) 7165 { 7166 if (rot >= 32) 7167 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32); 7168 else 7169 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot); 7170 return; 7171 } 7172 if (rot == 0) 7173 { 7174 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0); 7175 return; 7176 } 7177 r = (rot < 0x20) ? "dsrl" : "dsrl32"; 7178 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; 7179 rot &= 0x1f; 7180 macro_build (NULL, r, "d,w,<", AT, sreg, rot); 7181 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7182 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7183 } 7184 break; 7185 7186 case M_ROR_I: 7187 { 7188 unsigned int rot; 7189 7190 if (imm_expr.X_op != O_constant) 7191 as_bad (_("Improper rotate count")); 7192 rot = imm_expr.X_add_number & 0x1f; 7193 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) 7194 { 7195 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot); 7196 return; 7197 } 7198 if (rot == 0) 7199 { 7200 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0); 7201 return; 7202 } 7203 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot); 7204 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); 7205 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT); 7206 } 7207 break; 7208 7209 case M_S_DOB: 7210 if (mips_opts.arch == CPU_R4650) 7211 { 7212 as_bad (_("opcode not supported on this processor")); 7213 return; 7214 } 7215 assert (mips_opts.isa == ISA_MIPS1); 7216 /* Even on a big endian machine $fn comes before $fn+1. We have 7217 to adjust when storing to memory. */ 7218 macro_build (&offset_expr, "swc1", "T,o(b)", 7219 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg); 7220 offset_expr.X_add_number += 4; 7221 macro_build (&offset_expr, "swc1", "T,o(b)", 7222 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg); 7223 return; 7224 7225 case M_SEQ: 7226 if (sreg == 0) 7227 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16); 7228 else if (treg == 0) 7229 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7230 else 7231 { 7232 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); 7233 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); 7234 } 7235 return; 7236 7237 case M_SEQ_I: 7238 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 7239 { 7240 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7241 return; 7242 } 7243 if (sreg == 0) 7244 { 7245 as_warn (_("Instruction %s: result is always false"), 7246 ip->insn_mo->name); 7247 move_register (dreg, 0); 7248 return; 7249 } 7250 if (imm_expr.X_op == O_constant 7251 && imm_expr.X_add_number >= 0 7252 && imm_expr.X_add_number < 0x10000) 7253 { 7254 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); 7255 used_at = 0; 7256 } 7257 else if (imm_expr.X_op == O_constant 7258 && imm_expr.X_add_number > -0x8000 7259 && imm_expr.X_add_number < 0) 7260 { 7261 imm_expr.X_add_number = -imm_expr.X_add_number; 7262 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", 7263 "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7264 used_at = 0; 7265 } 7266 else 7267 { 7268 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7269 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); 7270 used_at = 1; 7271 } 7272 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16); 7273 if (used_at) 7274 break; 7275 return; 7276 7277 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ 7278 s = "slt"; 7279 goto sge; 7280 case M_SGEU: 7281 s = "sltu"; 7282 sge: 7283 macro_build (NULL, s, "d,v,t", dreg, sreg, treg); 7284 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7285 return; 7286 7287 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ 7288 case M_SGEU_I: 7289 if (imm_expr.X_op == O_constant 7290 && imm_expr.X_add_number >= -0x8000 7291 && imm_expr.X_add_number < 0x8000) 7292 { 7293 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", 7294 dreg, sreg, BFD_RELOC_LO16); 7295 used_at = 0; 7296 } 7297 else 7298 { 7299 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7300 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", 7301 dreg, sreg, AT); 7302 used_at = 1; 7303 } 7304 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7305 if (used_at) 7306 break; 7307 return; 7308 7309 case M_SGT: /* sreg > treg <==> treg < sreg */ 7310 s = "slt"; 7311 goto sgt; 7312 case M_SGTU: 7313 s = "sltu"; 7314 sgt: 7315 macro_build (NULL, s, "d,v,t", dreg, treg, sreg); 7316 return; 7317 7318 case M_SGT_I: /* sreg > I <==> I < sreg */ 7319 s = "slt"; 7320 goto sgti; 7321 case M_SGTU_I: 7322 s = "sltu"; 7323 sgti: 7324 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7325 macro_build (NULL, s, "d,v,t", dreg, AT, sreg); 7326 break; 7327 7328 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ 7329 s = "slt"; 7330 goto sle; 7331 case M_SLEU: 7332 s = "sltu"; 7333 sle: 7334 macro_build (NULL, s, "d,v,t", dreg, treg, sreg); 7335 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7336 return; 7337 7338 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ 7339 s = "slt"; 7340 goto slei; 7341 case M_SLEU_I: 7342 s = "sltu"; 7343 slei: 7344 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7345 macro_build (NULL, s, "d,v,t", dreg, AT, sreg); 7346 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16); 7347 break; 7348 7349 case M_SLT_I: 7350 if (imm_expr.X_op == O_constant 7351 && imm_expr.X_add_number >= -0x8000 7352 && imm_expr.X_add_number < 0x8000) 7353 { 7354 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7355 return; 7356 } 7357 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7358 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT); 7359 break; 7360 7361 case M_SLTU_I: 7362 if (imm_expr.X_op == O_constant 7363 && imm_expr.X_add_number >= -0x8000 7364 && imm_expr.X_add_number < 0x8000) 7365 { 7366 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg, 7367 BFD_RELOC_LO16); 7368 return; 7369 } 7370 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7371 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT); 7372 break; 7373 7374 case M_SNE: 7375 if (sreg == 0) 7376 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg); 7377 else if (treg == 0) 7378 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); 7379 else 7380 { 7381 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg); 7382 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); 7383 } 7384 return; 7385 7386 case M_SNE_I: 7387 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) 7388 { 7389 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg); 7390 return; 7391 } 7392 if (sreg == 0) 7393 { 7394 as_warn (_("Instruction %s: result is always true"), 7395 ip->insn_mo->name); 7396 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", 7397 dreg, 0, BFD_RELOC_LO16); 7398 return; 7399 } 7400 if (imm_expr.X_op == O_constant 7401 && imm_expr.X_add_number >= 0 7402 && imm_expr.X_add_number < 0x10000) 7403 { 7404 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16); 7405 used_at = 0; 7406 } 7407 else if (imm_expr.X_op == O_constant 7408 && imm_expr.X_add_number > -0x8000 7409 && imm_expr.X_add_number < 0) 7410 { 7411 imm_expr.X_add_number = -imm_expr.X_add_number; 7412 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", 7413 "t,r,j", dreg, sreg, BFD_RELOC_LO16); 7414 used_at = 0; 7415 } 7416 else 7417 { 7418 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7419 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT); 7420 used_at = 1; 7421 } 7422 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg); 7423 if (used_at) 7424 break; 7425 return; 7426 7427 case M_DSUB_I: 7428 dbl = 1; 7429 case M_SUB_I: 7430 if (imm_expr.X_op == O_constant 7431 && imm_expr.X_add_number > -0x8000 7432 && imm_expr.X_add_number <= 0x8000) 7433 { 7434 imm_expr.X_add_number = -imm_expr.X_add_number; 7435 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j", 7436 dreg, sreg, BFD_RELOC_LO16); 7437 return; 7438 } 7439 load_register (AT, &imm_expr, dbl); 7440 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); 7441 break; 7442 7443 case M_DSUBU_I: 7444 dbl = 1; 7445 case M_SUBU_I: 7446 if (imm_expr.X_op == O_constant 7447 && imm_expr.X_add_number > -0x8000 7448 && imm_expr.X_add_number <= 0x8000) 7449 { 7450 imm_expr.X_add_number = -imm_expr.X_add_number; 7451 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j", 7452 dreg, sreg, BFD_RELOC_LO16); 7453 return; 7454 } 7455 load_register (AT, &imm_expr, dbl); 7456 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); 7457 break; 7458 7459 case M_TEQ_I: 7460 s = "teq"; 7461 goto trap; 7462 case M_TGE_I: 7463 s = "tge"; 7464 goto trap; 7465 case M_TGEU_I: 7466 s = "tgeu"; 7467 goto trap; 7468 case M_TLT_I: 7469 s = "tlt"; 7470 goto trap; 7471 case M_TLTU_I: 7472 s = "tltu"; 7473 goto trap; 7474 case M_TNE_I: 7475 s = "tne"; 7476 trap: 7477 load_register (AT, &imm_expr, HAVE_64BIT_GPRS); 7478 macro_build (NULL, s, "s,t", sreg, AT); 7479 break; 7480 7481 case M_TRUNCWS: 7482 case M_TRUNCWD: 7483 assert (mips_opts.isa == ISA_MIPS1); 7484 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ 7485 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ 7486 7487 /* 7488 * Is the double cfc1 instruction a bug in the mips assembler; 7489 * or is there a reason for it? 7490 */ 7491 mips_emit_delays (TRUE); 7492 ++mips_opts.noreorder; 7493 mips_any_noreorder = 1; 7494 macro_build (NULL, "cfc1", "t,G", treg, RA); 7495 macro_build (NULL, "cfc1", "t,G", treg, RA); 7496 macro_build (NULL, "nop", ""); 7497 expr1.X_add_number = 3; 7498 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16); 7499 expr1.X_add_number = 2; 7500 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); 7501 macro_build (NULL, "ctc1", "t,G", AT, RA); 7502 macro_build (NULL, "nop", ""); 7503 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", 7504 dreg, sreg); 7505 macro_build (NULL, "ctc1", "t,G", treg, RA); 7506 macro_build (NULL, "nop", ""); 7507 --mips_opts.noreorder; 7508 break; 7509 7510 case M_ULH: 7511 s = "lb"; 7512 goto ulh; 7513 case M_ULHU: 7514 s = "lbu"; 7515 ulh: 7516 if (offset_expr.X_add_number >= 0x7fff) 7517 as_bad (_("operand overflow")); 7518 if (! target_big_endian) 7519 ++offset_expr.X_add_number; 7520 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg); 7521 if (! target_big_endian) 7522 --offset_expr.X_add_number; 7523 else 7524 ++offset_expr.X_add_number; 7525 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg); 7526 macro_build (NULL, "sll", "d,w,<", AT, AT, 8); 7527 macro_build (NULL, "or", "d,v,t", treg, treg, AT); 7528 break; 7529 7530 case M_ULD: 7531 s = "ldl"; 7532 s2 = "ldr"; 7533 off = 7; 7534 goto ulw; 7535 case M_ULW: 7536 s = "lwl"; 7537 s2 = "lwr"; 7538 off = 3; 7539 ulw: 7540 if (offset_expr.X_add_number >= 0x8000 - off) 7541 as_bad (_("operand overflow")); 7542 if (treg != breg) 7543 tempreg = treg; 7544 else 7545 tempreg = AT; 7546 if (! target_big_endian) 7547 offset_expr.X_add_number += off; 7548 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); 7549 if (! target_big_endian) 7550 offset_expr.X_add_number -= off; 7551 else 7552 offset_expr.X_add_number += off; 7553 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg); 7554 7555 /* If necessary, move the result in tempreg the final destination. */ 7556 if (treg == tempreg) 7557 return; 7558 /* Protect second load's delay slot. */ 7559 if (!gpr_interlocks) 7560 macro_build (NULL, "nop", ""); 7561 move_register (treg, tempreg); 7562 break; 7563 7564 case M_ULD_A: 7565 s = "ldl"; 7566 s2 = "ldr"; 7567 off = 7; 7568 goto ulwa; 7569 case M_ULW_A: 7570 s = "lwl"; 7571 s2 = "lwr"; 7572 off = 3; 7573 ulwa: 7574 used_at = 1; 7575 load_address (AT, &offset_expr, &used_at); 7576 if (breg != 0) 7577 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 7578 if (! target_big_endian) 7579 expr1.X_add_number = off; 7580 else 7581 expr1.X_add_number = 0; 7582 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); 7583 if (! target_big_endian) 7584 expr1.X_add_number = 0; 7585 else 7586 expr1.X_add_number = off; 7587 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); 7588 break; 7589 7590 case M_ULH_A: 7591 case M_ULHU_A: 7592 used_at = 1; 7593 load_address (AT, &offset_expr, &used_at); 7594 if (breg != 0) 7595 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 7596 if (target_big_endian) 7597 expr1.X_add_number = 0; 7598 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", 7599 treg, BFD_RELOC_LO16, AT); 7600 if (target_big_endian) 7601 expr1.X_add_number = 1; 7602 else 7603 expr1.X_add_number = 0; 7604 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); 7605 macro_build (NULL, "sll", "d,w,<", treg, treg, 8); 7606 macro_build (NULL, "or", "d,v,t", treg, treg, AT); 7607 break; 7608 7609 case M_USH: 7610 if (offset_expr.X_add_number >= 0x7fff) 7611 as_bad (_("operand overflow")); 7612 if (target_big_endian) 7613 ++offset_expr.X_add_number; 7614 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg); 7615 macro_build (NULL, "srl", "d,w,<", AT, treg, 8); 7616 if (target_big_endian) 7617 --offset_expr.X_add_number; 7618 else 7619 ++offset_expr.X_add_number; 7620 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg); 7621 break; 7622 7623 case M_USD: 7624 s = "sdl"; 7625 s2 = "sdr"; 7626 off = 7; 7627 goto usw; 7628 case M_USW: 7629 s = "swl"; 7630 s2 = "swr"; 7631 off = 3; 7632 usw: 7633 if (offset_expr.X_add_number >= 0x8000 - off) 7634 as_bad (_("operand overflow")); 7635 if (! target_big_endian) 7636 offset_expr.X_add_number += off; 7637 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg); 7638 if (! target_big_endian) 7639 offset_expr.X_add_number -= off; 7640 else 7641 offset_expr.X_add_number += off; 7642 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg); 7643 return; 7644 7645 case M_USD_A: 7646 s = "sdl"; 7647 s2 = "sdr"; 7648 off = 7; 7649 goto uswa; 7650 case M_USW_A: 7651 s = "swl"; 7652 s2 = "swr"; 7653 off = 3; 7654 uswa: 7655 used_at = 1; 7656 load_address (AT, &offset_expr, &used_at); 7657 if (breg != 0) 7658 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 7659 if (! target_big_endian) 7660 expr1.X_add_number = off; 7661 else 7662 expr1.X_add_number = 0; 7663 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT); 7664 if (! target_big_endian) 7665 expr1.X_add_number = 0; 7666 else 7667 expr1.X_add_number = off; 7668 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT); 7669 break; 7670 7671 case M_USH_A: 7672 used_at = 1; 7673 load_address (AT, &offset_expr, &used_at); 7674 if (breg != 0) 7675 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); 7676 if (! target_big_endian) 7677 expr1.X_add_number = 0; 7678 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); 7679 macro_build (NULL, "srl", "d,w,<", treg, treg, 8); 7680 if (! target_big_endian) 7681 expr1.X_add_number = 1; 7682 else 7683 expr1.X_add_number = 0; 7684 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT); 7685 if (! target_big_endian) 7686 expr1.X_add_number = 0; 7687 else 7688 expr1.X_add_number = 1; 7689 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT); 7690 macro_build (NULL, "sll", "d,w,<", treg, treg, 8); 7691 macro_build (NULL, "or", "d,v,t", treg, treg, AT); 7692 break; 7693 7694 default: 7695 /* FIXME: Check if this is one of the itbl macros, since they 7696 are added dynamically. */ 7697 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); 7698 break; 7699 } 7700 if (mips_opts.noat) 7701 as_warn (_("Macro used $at after \".set noat\"")); 7702} 7703 7704/* Implement macros in mips16 mode. */ 7705 7706static void 7707mips16_macro (struct mips_cl_insn *ip) 7708{ 7709 int mask; 7710 int xreg, yreg, zreg, tmp; 7711 expressionS expr1; 7712 int dbl; 7713 const char *s, *s2, *s3; 7714 7715 mask = ip->insn_mo->mask; 7716 7717 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; 7718 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; 7719 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; 7720 7721 expr1.X_op = O_constant; 7722 expr1.X_op_symbol = NULL; 7723 expr1.X_add_symbol = NULL; 7724 expr1.X_add_number = 1; 7725 7726 dbl = 0; 7727 7728 switch (mask) 7729 { 7730 default: 7731 internalError (); 7732 7733 case M_DDIV_3: 7734 dbl = 1; 7735 case M_DIV_3: 7736 s = "mflo"; 7737 goto do_div3; 7738 case M_DREM_3: 7739 dbl = 1; 7740 case M_REM_3: 7741 s = "mfhi"; 7742 do_div3: 7743 mips_emit_delays (TRUE); 7744 ++mips_opts.noreorder; 7745 mips_any_noreorder = 1; 7746 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg); 7747 expr1.X_add_number = 2; 7748 macro_build (&expr1, "bnez", "x,p", yreg); 7749 macro_build (NULL, "break", "6", 7); 7750 7751 /* FIXME: The normal code checks for of -1 / -0x80000000 here, 7752 since that causes an overflow. We should do that as well, 7753 but I don't see how to do the comparisons without a temporary 7754 register. */ 7755 --mips_opts.noreorder; 7756 macro_build (NULL, s, "x", zreg); 7757 break; 7758 7759 case M_DIVU_3: 7760 s = "divu"; 7761 s2 = "mflo"; 7762 goto do_divu3; 7763 case M_REMU_3: 7764 s = "divu"; 7765 s2 = "mfhi"; 7766 goto do_divu3; 7767 case M_DDIVU_3: 7768 s = "ddivu"; 7769 s2 = "mflo"; 7770 goto do_divu3; 7771 case M_DREMU_3: 7772 s = "ddivu"; 7773 s2 = "mfhi"; 7774 do_divu3: 7775 mips_emit_delays (TRUE); 7776 ++mips_opts.noreorder; 7777 mips_any_noreorder = 1; 7778 macro_build (NULL, s, "0,x,y", xreg, yreg); 7779 expr1.X_add_number = 2; 7780 macro_build (&expr1, "bnez", "x,p", yreg); 7781 macro_build (NULL, "break", "6", 7); 7782 --mips_opts.noreorder; 7783 macro_build (NULL, s2, "x", zreg); 7784 break; 7785 7786 case M_DMUL: 7787 dbl = 1; 7788 case M_MUL: 7789 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg); 7790 macro_build (NULL, "mflo", "x", zreg); 7791 return; 7792 7793 case M_DSUBU_I: 7794 dbl = 1; 7795 goto do_subu; 7796 case M_SUBU_I: 7797 do_subu: 7798 if (imm_expr.X_op != O_constant) 7799 as_bad (_("Unsupported large constant")); 7800 imm_expr.X_add_number = -imm_expr.X_add_number; 7801 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); 7802 break; 7803 7804 case M_SUBU_I_2: 7805 if (imm_expr.X_op != O_constant) 7806 as_bad (_("Unsupported large constant")); 7807 imm_expr.X_add_number = -imm_expr.X_add_number; 7808 macro_build (&imm_expr, "addiu", "x,k", xreg); 7809 break; 7810 7811 case M_DSUBU_I_2: 7812 if (imm_expr.X_op != O_constant) 7813 as_bad (_("Unsupported large constant")); 7814 imm_expr.X_add_number = -imm_expr.X_add_number; 7815 macro_build (&imm_expr, "daddiu", "y,j", yreg); 7816 break; 7817 7818 case M_BEQ: 7819 s = "cmp"; 7820 s2 = "bteqz"; 7821 goto do_branch; 7822 case M_BNE: 7823 s = "cmp"; 7824 s2 = "btnez"; 7825 goto do_branch; 7826 case M_BLT: 7827 s = "slt"; 7828 s2 = "btnez"; 7829 goto do_branch; 7830 case M_BLTU: 7831 s = "sltu"; 7832 s2 = "btnez"; 7833 goto do_branch; 7834 case M_BLE: 7835 s = "slt"; 7836 s2 = "bteqz"; 7837 goto do_reverse_branch; 7838 case M_BLEU: 7839 s = "sltu"; 7840 s2 = "bteqz"; 7841 goto do_reverse_branch; 7842 case M_BGE: 7843 s = "slt"; 7844 s2 = "bteqz"; 7845 goto do_branch; 7846 case M_BGEU: 7847 s = "sltu"; 7848 s2 = "bteqz"; 7849 goto do_branch; 7850 case M_BGT: 7851 s = "slt"; 7852 s2 = "btnez"; 7853 goto do_reverse_branch; 7854 case M_BGTU: 7855 s = "sltu"; 7856 s2 = "btnez"; 7857 7858 do_reverse_branch: 7859 tmp = xreg; 7860 xreg = yreg; 7861 yreg = tmp; 7862 7863 do_branch: 7864 macro_build (NULL, s, "x,y", xreg, yreg); 7865 macro_build (&offset_expr, s2, "p"); 7866 break; 7867 7868 case M_BEQ_I: 7869 s = "cmpi"; 7870 s2 = "bteqz"; 7871 s3 = "x,U"; 7872 goto do_branch_i; 7873 case M_BNE_I: 7874 s = "cmpi"; 7875 s2 = "btnez"; 7876 s3 = "x,U"; 7877 goto do_branch_i; 7878 case M_BLT_I: 7879 s = "slti"; 7880 s2 = "btnez"; 7881 s3 = "x,8"; 7882 goto do_branch_i; 7883 case M_BLTU_I: 7884 s = "sltiu"; 7885 s2 = "btnez"; 7886 s3 = "x,8"; 7887 goto do_branch_i; 7888 case M_BLE_I: 7889 s = "slti"; 7890 s2 = "btnez"; 7891 s3 = "x,8"; 7892 goto do_addone_branch_i; 7893 case M_BLEU_I: 7894 s = "sltiu"; 7895 s2 = "btnez"; 7896 s3 = "x,8"; 7897 goto do_addone_branch_i; 7898 case M_BGE_I: 7899 s = "slti"; 7900 s2 = "bteqz"; 7901 s3 = "x,8"; 7902 goto do_branch_i; 7903 case M_BGEU_I: 7904 s = "sltiu"; 7905 s2 = "bteqz"; 7906 s3 = "x,8"; 7907 goto do_branch_i; 7908 case M_BGT_I: 7909 s = "slti"; 7910 s2 = "bteqz"; 7911 s3 = "x,8"; 7912 goto do_addone_branch_i; 7913 case M_BGTU_I: 7914 s = "sltiu"; 7915 s2 = "bteqz"; 7916 s3 = "x,8"; 7917 7918 do_addone_branch_i: 7919 if (imm_expr.X_op != O_constant) 7920 as_bad (_("Unsupported large constant")); 7921 ++imm_expr.X_add_number; 7922 7923 do_branch_i: 7924 macro_build (&imm_expr, s, s3, xreg); 7925 macro_build (&offset_expr, s2, "p"); 7926 break; 7927 7928 case M_ABS: 7929 expr1.X_add_number = 0; 7930 macro_build (&expr1, "slti", "x,8", yreg); 7931 if (xreg != yreg) 7932 move_register (xreg, yreg); 7933 expr1.X_add_number = 2; 7934 macro_build (&expr1, "bteqz", "p"); 7935 macro_build (NULL, "neg", "x,w", xreg, xreg); 7936 } 7937} 7938 7939/* For consistency checking, verify that all bits are specified either 7940 by the match/mask part of the instruction definition, or by the 7941 operand list. */ 7942static int 7943validate_mips_insn (const struct mips_opcode *opc) 7944{ 7945 const char *p = opc->args; 7946 char c; 7947 unsigned long used_bits = opc->mask; 7948 7949 if ((used_bits & opc->match) != opc->match) 7950 { 7951 as_bad (_("internal: bad mips opcode (mask error): %s %s"), 7952 opc->name, opc->args); 7953 return 0; 7954 } 7955#define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) 7956 while (*p) 7957 switch (c = *p++) 7958 { 7959 case ',': break; 7960 case '(': break; 7961 case ')': break; 7962 case '+': 7963 switch (c = *p++) 7964 { 7965 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 7966 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; 7967 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; 7968 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); 7969 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; 7970 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 7971 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break; 7972 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; 7973 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break; 7974 case 'I': break; 7975 default: 7976 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), 7977 c, opc->name, opc->args); 7978 return 0; 7979 } 7980 break; 7981 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 7982 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 7983 case 'A': break; 7984 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; 7985 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; 7986 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; 7987 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 7988 case 'F': break; 7989 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 7990 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; 7991 case 'I': break; 7992 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; 7993 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 7994 case 'L': break; 7995 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; 7996 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; 7997 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break; 7998 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL); 7999 USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8000 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; 8001 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; 8002 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8003 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; 8004 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8005 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break; 8006 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break; 8007 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break; 8008 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; 8009 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8010 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; 8011 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 8012 case 'f': break; 8013 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; 8014 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; 8015 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; 8016 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; 8017 case 'l': break; 8018 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; 8019 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; 8020 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; 8021 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8022 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8023 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8024 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; 8025 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; 8026 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8027 case 'x': break; 8028 case 'z': break; 8029 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; 8030 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); 8031 USE_BITS (OP_MASK_RT, OP_SH_RT); break; 8032 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break; 8033 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break; 8034 case '[': break; 8035 case ']': break; 8036 default: 8037 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), 8038 c, opc->name, opc->args); 8039 return 0; 8040 } 8041#undef USE_BITS 8042 if (used_bits != 0xffffffff) 8043 { 8044 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), 8045 ~used_bits & 0xffffffff, opc->name, opc->args); 8046 return 0; 8047 } 8048 return 1; 8049} 8050 8051/* This routine assembles an instruction into its binary format. As a 8052 side effect, it sets one of the global variables imm_reloc or 8053 offset_reloc to the type of relocation to do if one of the operands 8054 is an address expression. */ 8055 8056static void 8057mips_ip (char *str, struct mips_cl_insn *ip) 8058{ 8059 char *s; 8060 const char *args; 8061 char c = 0; 8062 struct mips_opcode *insn; 8063 char *argsStart; 8064 unsigned int regno; 8065 unsigned int lastregno = 0; 8066 unsigned int lastpos = 0; 8067 unsigned int limlo, limhi; 8068 char *s_reset; 8069 char save_c = 0; 8070 8071 insn_error = NULL; 8072 8073 /* If the instruction contains a '.', we first try to match an instruction 8074 including the '.'. Then we try again without the '.'. */ 8075 insn = NULL; 8076 for (s = str; *s != '\0' && !ISSPACE (*s); ++s) 8077 continue; 8078 8079 /* If we stopped on whitespace, then replace the whitespace with null for 8080 the call to hash_find. Save the character we replaced just in case we 8081 have to re-parse the instruction. */ 8082 if (ISSPACE (*s)) 8083 { 8084 save_c = *s; 8085 *s++ = '\0'; 8086 } 8087 8088 insn = (struct mips_opcode *) hash_find (op_hash, str); 8089 8090 /* If we didn't find the instruction in the opcode table, try again, but 8091 this time with just the instruction up to, but not including the 8092 first '.'. */ 8093 if (insn == NULL) 8094 { 8095 /* Restore the character we overwrite above (if any). */ 8096 if (save_c) 8097 *(--s) = save_c; 8098 8099 /* Scan up to the first '.' or whitespace. */ 8100 for (s = str; 8101 *s != '\0' && *s != '.' && !ISSPACE (*s); 8102 ++s) 8103 continue; 8104 8105 /* If we did not find a '.', then we can quit now. */ 8106 if (*s != '.') 8107 { 8108 insn_error = "unrecognized opcode"; 8109 return; 8110 } 8111 8112 /* Lookup the instruction in the hash table. */ 8113 *s++ = '\0'; 8114 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) 8115 { 8116 insn_error = "unrecognized opcode"; 8117 return; 8118 } 8119 } 8120 8121 argsStart = s; 8122 for (;;) 8123 { 8124 bfd_boolean ok; 8125 8126 assert (strcmp (insn->name, str) == 0); 8127 8128 if (OPCODE_IS_MEMBER (insn, 8129 (mips_opts.isa 8130 | (file_ase_mips16 ? INSN_MIPS16 : 0) 8131 | (mips_opts.ase_mdmx ? INSN_MDMX : 0) 8132 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), 8133 mips_opts.arch)) 8134 ok = TRUE; 8135 else 8136 ok = FALSE; 8137 8138 if (insn->pinfo != INSN_MACRO) 8139 { 8140 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) 8141 ok = FALSE; 8142 } 8143 8144 if (! ok) 8145 { 8146 if (insn + 1 < &mips_opcodes[NUMOPCODES] 8147 && strcmp (insn->name, insn[1].name) == 0) 8148 { 8149 ++insn; 8150 continue; 8151 } 8152 else 8153 { 8154 if (!insn_error) 8155 { 8156 static char buf[100]; 8157 sprintf (buf, 8158 _("opcode not supported on this processor: %s (%s)"), 8159 mips_cpu_info_from_arch (mips_opts.arch)->name, 8160 mips_cpu_info_from_isa (mips_opts.isa)->name); 8161 insn_error = buf; 8162 } 8163 if (save_c) 8164 *(--s) = save_c; 8165 return; 8166 } 8167 } 8168 8169 ip->insn_mo = insn; 8170 ip->insn_opcode = insn->match; 8171 insn_error = NULL; 8172 for (args = insn->args;; ++args) 8173 { 8174 int is_mdmx; 8175 8176 s += strspn (s, " \t"); 8177 is_mdmx = 0; 8178 switch (*args) 8179 { 8180 case '\0': /* end of args */ 8181 if (*s == '\0') 8182 return; 8183 break; 8184 8185 case ',': 8186 if (*s++ == *args) 8187 continue; 8188 s--; 8189 switch (*++args) 8190 { 8191 case 'r': 8192 case 'v': 8193 ip->insn_opcode |= lastregno << OP_SH_RS; 8194 continue; 8195 8196 case 'w': 8197 ip->insn_opcode |= lastregno << OP_SH_RT; 8198 continue; 8199 8200 case 'W': 8201 ip->insn_opcode |= lastregno << OP_SH_FT; 8202 continue; 8203 8204 case 'V': 8205 ip->insn_opcode |= lastregno << OP_SH_FS; 8206 continue; 8207 } 8208 break; 8209 8210 case '(': 8211 /* Handle optional base register. 8212 Either the base register is omitted or 8213 we must have a left paren. */ 8214 /* This is dependent on the next operand specifier 8215 is a base register specification. */ 8216 assert (args[1] == 'b' || args[1] == '5' 8217 || args[1] == '-' || args[1] == '4'); 8218 if (*s == '\0') 8219 return; 8220 8221 case ')': /* these must match exactly */ 8222 case '[': 8223 case ']': 8224 if (*s++ == *args) 8225 continue; 8226 break; 8227 8228 case '+': /* Opcode extension character. */ 8229 switch (*++args) 8230 { 8231 case 'A': /* ins/ext position, becomes LSB. */ 8232 limlo = 0; 8233 limhi = 31; 8234 goto do_lsb; 8235 case 'E': 8236 limlo = 32; 8237 limhi = 63; 8238 goto do_lsb; 8239do_lsb: 8240 my_getExpression (&imm_expr, s); 8241 check_absolute_expr (ip, &imm_expr); 8242 if ((unsigned long) imm_expr.X_add_number < limlo 8243 || (unsigned long) imm_expr.X_add_number > limhi) 8244 { 8245 as_bad (_("Improper position (%lu)"), 8246 (unsigned long) imm_expr.X_add_number); 8247 imm_expr.X_add_number = limlo; 8248 } 8249 lastpos = imm_expr.X_add_number; 8250 ip->insn_opcode |= (imm_expr.X_add_number 8251 & OP_MASK_SHAMT) << OP_SH_SHAMT; 8252 imm_expr.X_op = O_absent; 8253 s = expr_end; 8254 continue; 8255 8256 case 'B': /* ins size, becomes MSB. */ 8257 limlo = 1; 8258 limhi = 32; 8259 goto do_msb; 8260 case 'F': 8261 limlo = 33; 8262 limhi = 64; 8263 goto do_msb; 8264do_msb: 8265 my_getExpression (&imm_expr, s); 8266 check_absolute_expr (ip, &imm_expr); 8267 /* Check for negative input so that small negative numbers 8268 will not succeed incorrectly. The checks against 8269 (pos+size) transitively check "size" itself, 8270 assuming that "pos" is reasonable. */ 8271 if ((long) imm_expr.X_add_number < 0 8272 || ((unsigned long) imm_expr.X_add_number 8273 + lastpos) < limlo 8274 || ((unsigned long) imm_expr.X_add_number 8275 + lastpos) > limhi) 8276 { 8277 as_bad (_("Improper insert size (%lu, position %lu)"), 8278 (unsigned long) imm_expr.X_add_number, 8279 (unsigned long) lastpos); 8280 imm_expr.X_add_number = limlo - lastpos; 8281 } 8282 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1) 8283 & OP_MASK_INSMSB) << OP_SH_INSMSB; 8284 imm_expr.X_op = O_absent; 8285 s = expr_end; 8286 continue; 8287 8288 case 'C': /* ext size, becomes MSBD. */ 8289 limlo = 1; 8290 limhi = 32; 8291 goto do_msbd; 8292 case 'G': 8293 limlo = 33; 8294 limhi = 64; 8295 goto do_msbd; 8296 case 'H': 8297 limlo = 33; 8298 limhi = 64; 8299 goto do_msbd; 8300do_msbd: 8301 my_getExpression (&imm_expr, s); 8302 check_absolute_expr (ip, &imm_expr); 8303 /* Check for negative input so that small negative numbers 8304 will not succeed incorrectly. The checks against 8305 (pos+size) transitively check "size" itself, 8306 assuming that "pos" is reasonable. */ 8307 if ((long) imm_expr.X_add_number < 0 8308 || ((unsigned long) imm_expr.X_add_number 8309 + lastpos) < limlo 8310 || ((unsigned long) imm_expr.X_add_number 8311 + lastpos) > limhi) 8312 { 8313 as_bad (_("Improper extract size (%lu, position %lu)"), 8314 (unsigned long) imm_expr.X_add_number, 8315 (unsigned long) lastpos); 8316 imm_expr.X_add_number = limlo - lastpos; 8317 } 8318 ip->insn_opcode |= ((imm_expr.X_add_number - 1) 8319 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD; 8320 imm_expr.X_op = O_absent; 8321 s = expr_end; 8322 continue; 8323 8324 case 'D': 8325 /* +D is for disassembly only; never match. */ 8326 break; 8327 8328 case 'I': 8329 /* "+I" is like "I", except that imm2_expr is used. */ 8330 my_getExpression (&imm2_expr, s); 8331 if (imm2_expr.X_op != O_big 8332 && imm2_expr.X_op != O_constant) 8333 insn_error = _("absolute expression required"); 8334 normalize_constant_expr (&imm2_expr); 8335 s = expr_end; 8336 continue; 8337 8338 default: 8339 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"), 8340 *args, insn->name, insn->args); 8341 /* Further processing is fruitless. */ 8342 return; 8343 } 8344 break; 8345 8346 case '<': /* must be at least one digit */ 8347 /* 8348 * According to the manual, if the shift amount is greater 8349 * than 31 or less than 0, then the shift amount should be 8350 * mod 32. In reality the mips assembler issues an error. 8351 * We issue a warning and mask out all but the low 5 bits. 8352 */ 8353 my_getExpression (&imm_expr, s); 8354 check_absolute_expr (ip, &imm_expr); 8355 if ((unsigned long) imm_expr.X_add_number > 31) 8356 { 8357 as_warn (_("Improper shift amount (%lu)"), 8358 (unsigned long) imm_expr.X_add_number); 8359 imm_expr.X_add_number &= OP_MASK_SHAMT; 8360 } 8361 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; 8362 imm_expr.X_op = O_absent; 8363 s = expr_end; 8364 continue; 8365 8366 case '>': /* shift amount minus 32 */ 8367 my_getExpression (&imm_expr, s); 8368 check_absolute_expr (ip, &imm_expr); 8369 if ((unsigned long) imm_expr.X_add_number < 32 8370 || (unsigned long) imm_expr.X_add_number > 63) 8371 break; 8372 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; 8373 imm_expr.X_op = O_absent; 8374 s = expr_end; 8375 continue; 8376 8377 case 'k': /* cache code */ 8378 case 'h': /* prefx code */ 8379 my_getExpression (&imm_expr, s); 8380 check_absolute_expr (ip, &imm_expr); 8381 if ((unsigned long) imm_expr.X_add_number > 31) 8382 { 8383 as_warn (_("Invalid value for `%s' (%lu)"), 8384 ip->insn_mo->name, 8385 (unsigned long) imm_expr.X_add_number); 8386 imm_expr.X_add_number &= 0x1f; 8387 } 8388 if (*args == 'k') 8389 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; 8390 else 8391 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; 8392 imm_expr.X_op = O_absent; 8393 s = expr_end; 8394 continue; 8395 8396 case 'c': /* break code */ 8397 my_getExpression (&imm_expr, s); 8398 check_absolute_expr (ip, &imm_expr); 8399 if ((unsigned long) imm_expr.X_add_number > 1023) 8400 { 8401 as_warn (_("Illegal break code (%lu)"), 8402 (unsigned long) imm_expr.X_add_number); 8403 imm_expr.X_add_number &= OP_MASK_CODE; 8404 } 8405 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; 8406 imm_expr.X_op = O_absent; 8407 s = expr_end; 8408 continue; 8409 8410 case 'q': /* lower break code */ 8411 my_getExpression (&imm_expr, s); 8412 check_absolute_expr (ip, &imm_expr); 8413 if ((unsigned long) imm_expr.X_add_number > 1023) 8414 { 8415 as_warn (_("Illegal lower break code (%lu)"), 8416 (unsigned long) imm_expr.X_add_number); 8417 imm_expr.X_add_number &= OP_MASK_CODE2; 8418 } 8419 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; 8420 imm_expr.X_op = O_absent; 8421 s = expr_end; 8422 continue; 8423 8424 case 'B': /* 20-bit syscall/break code. */ 8425 my_getExpression (&imm_expr, s); 8426 check_absolute_expr (ip, &imm_expr); 8427 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20) 8428 as_warn (_("Illegal 20-bit code (%lu)"), 8429 (unsigned long) imm_expr.X_add_number); 8430 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; 8431 imm_expr.X_op = O_absent; 8432 s = expr_end; 8433 continue; 8434 8435 case 'C': /* Coprocessor code */ 8436 my_getExpression (&imm_expr, s); 8437 check_absolute_expr (ip, &imm_expr); 8438 if ((unsigned long) imm_expr.X_add_number >= (1 << 25)) 8439 { 8440 as_warn (_("Coproccesor code > 25 bits (%lu)"), 8441 (unsigned long) imm_expr.X_add_number); 8442 imm_expr.X_add_number &= ((1 << 25) - 1); 8443 } 8444 ip->insn_opcode |= imm_expr.X_add_number; 8445 imm_expr.X_op = O_absent; 8446 s = expr_end; 8447 continue; 8448 8449 case 'J': /* 19-bit wait code. */ 8450 my_getExpression (&imm_expr, s); 8451 check_absolute_expr (ip, &imm_expr); 8452 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19) 8453 as_warn (_("Illegal 19-bit code (%lu)"), 8454 (unsigned long) imm_expr.X_add_number); 8455 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; 8456 imm_expr.X_op = O_absent; 8457 s = expr_end; 8458 continue; 8459 8460 case 'P': /* Performance register */ 8461 my_getExpression (&imm_expr, s); 8462 check_absolute_expr (ip, &imm_expr); 8463 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) 8464 { 8465 as_warn (_("Invalid performance register (%lu)"), 8466 (unsigned long) imm_expr.X_add_number); 8467 imm_expr.X_add_number &= OP_MASK_PERFREG; 8468 } 8469 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); 8470 imm_expr.X_op = O_absent; 8471 s = expr_end; 8472 continue; 8473 8474 case 'b': /* base register */ 8475 case 'd': /* destination register */ 8476 case 's': /* source register */ 8477 case 't': /* target register */ 8478 case 'r': /* both target and source */ 8479 case 'v': /* both dest and source */ 8480 case 'w': /* both dest and target */ 8481 case 'E': /* coprocessor target register */ 8482 case 'G': /* coprocessor destination register */ 8483 case 'K': /* 'rdhwr' destination register */ 8484 case 'x': /* ignore register name */ 8485 case 'z': /* must be zero register */ 8486 case 'U': /* destination register (clo/clz). */ 8487 s_reset = s; 8488 if (s[0] == '$') 8489 { 8490 8491 if (ISDIGIT (s[1])) 8492 { 8493 ++s; 8494 regno = 0; 8495 do 8496 { 8497 regno *= 10; 8498 regno += *s - '0'; 8499 ++s; 8500 } 8501 while (ISDIGIT (*s)); 8502 if (regno > 31) 8503 as_bad (_("Invalid register number (%d)"), regno); 8504 } 8505 else if (*args == 'E' || *args == 'G' || *args == 'K') 8506 goto notreg; 8507 else 8508 { 8509 if (s[1] == 'r' && s[2] == 'a') 8510 { 8511 s += 3; 8512 regno = RA; 8513 } 8514 else if (s[1] == 'f' && s[2] == 'p') 8515 { 8516 s += 3; 8517 regno = FP; 8518 } 8519 else if (s[1] == 's' && s[2] == 'p') 8520 { 8521 s += 3; 8522 regno = SP; 8523 } 8524 else if (s[1] == 'g' && s[2] == 'p') 8525 { 8526 s += 3; 8527 regno = GP; 8528 } 8529 else if (s[1] == 'a' && s[2] == 't') 8530 { 8531 s += 3; 8532 regno = AT; 8533 } 8534 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') 8535 { 8536 s += 4; 8537 regno = KT0; 8538 } 8539 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') 8540 { 8541 s += 4; 8542 regno = KT1; 8543 } 8544 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') 8545 { 8546 s += 5; 8547 regno = ZERO; 8548 } 8549 else if (itbl_have_entries) 8550 { 8551 char *p, *n; 8552 unsigned long r; 8553 8554 p = s + 1; /* advance past '$' */ 8555 n = itbl_get_field (&p); /* n is name */ 8556 8557 /* See if this is a register defined in an 8558 itbl entry. */ 8559 if (itbl_get_reg_val (n, &r)) 8560 { 8561 /* Get_field advances to the start of 8562 the next field, so we need to back 8563 rack to the end of the last field. */ 8564 if (p) 8565 s = p - 1; 8566 else 8567 s = strchr (s, '\0'); 8568 regno = r; 8569 } 8570 else 8571 goto notreg; 8572 } 8573 else 8574 goto notreg; 8575 } 8576 if (regno == AT 8577 && ! mips_opts.noat 8578 && *args != 'E' 8579 && *args != 'G' 8580 && *args != 'K') 8581 as_warn (_("Used $at without \".set noat\"")); 8582 c = *args; 8583 if (*s == ' ') 8584 ++s; 8585 if (args[1] != *s) 8586 { 8587 if (c == 'r' || c == 'v' || c == 'w') 8588 { 8589 regno = lastregno; 8590 s = s_reset; 8591 ++args; 8592 } 8593 } 8594 /* 'z' only matches $0. */ 8595 if (c == 'z' && regno != 0) 8596 break; 8597 8598 /* Now that we have assembled one operand, we use the args string 8599 * to figure out where it goes in the instruction. */ 8600 switch (c) 8601 { 8602 case 'r': 8603 case 's': 8604 case 'v': 8605 case 'b': 8606 ip->insn_opcode |= regno << OP_SH_RS; 8607 break; 8608 case 'd': 8609 case 'G': 8610 case 'K': 8611 ip->insn_opcode |= regno << OP_SH_RD; 8612 break; 8613 case 'U': 8614 ip->insn_opcode |= regno << OP_SH_RD; 8615 ip->insn_opcode |= regno << OP_SH_RT; 8616 break; 8617 case 'w': 8618 case 't': 8619 case 'E': 8620 ip->insn_opcode |= regno << OP_SH_RT; 8621 break; 8622 case 'x': 8623 /* This case exists because on the r3000 trunc 8624 expands into a macro which requires a gp 8625 register. On the r6000 or r4000 it is 8626 assembled into a single instruction which 8627 ignores the register. Thus the insn version 8628 is MIPS_ISA2 and uses 'x', and the macro 8629 version is MIPS_ISA1 and uses 't'. */ 8630 break; 8631 case 'z': 8632 /* This case is for the div instruction, which 8633 acts differently if the destination argument 8634 is $0. This only matches $0, and is checked 8635 outside the switch. */ 8636 break; 8637 case 'D': 8638 /* Itbl operand; not yet implemented. FIXME ?? */ 8639 break; 8640 /* What about all other operands like 'i', which 8641 can be specified in the opcode table? */ 8642 } 8643 lastregno = regno; 8644 continue; 8645 } 8646 notreg: 8647 switch (*args++) 8648 { 8649 case 'r': 8650 case 'v': 8651 ip->insn_opcode |= lastregno << OP_SH_RS; 8652 continue; 8653 case 'w': 8654 ip->insn_opcode |= lastregno << OP_SH_RT; 8655 continue; 8656 } 8657 break; 8658 8659 case 'O': /* MDMX alignment immediate constant. */ 8660 my_getExpression (&imm_expr, s); 8661 check_absolute_expr (ip, &imm_expr); 8662 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN) 8663 { 8664 as_warn ("Improper align amount (%ld), using low bits", 8665 (long) imm_expr.X_add_number); 8666 imm_expr.X_add_number &= OP_MASK_ALN; 8667 } 8668 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN; 8669 imm_expr.X_op = O_absent; 8670 s = expr_end; 8671 continue; 8672 8673 case 'Q': /* MDMX vector, element sel, or const. */ 8674 if (s[0] != '$') 8675 { 8676 /* MDMX Immediate. */ 8677 my_getExpression (&imm_expr, s); 8678 check_absolute_expr (ip, &imm_expr); 8679 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT) 8680 { 8681 as_warn (_("Invalid MDMX Immediate (%ld)"), 8682 (long) imm_expr.X_add_number); 8683 imm_expr.X_add_number &= OP_MASK_FT; 8684 } 8685 imm_expr.X_add_number &= OP_MASK_FT; 8686 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) 8687 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL; 8688 else 8689 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL; 8690 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT; 8691 imm_expr.X_op = O_absent; 8692 s = expr_end; 8693 continue; 8694 } 8695 /* Not MDMX Immediate. Fall through. */ 8696 case 'X': /* MDMX destination register. */ 8697 case 'Y': /* MDMX source register. */ 8698 case 'Z': /* MDMX target register. */ 8699 is_mdmx = 1; 8700 case 'D': /* floating point destination register */ 8701 case 'S': /* floating point source register */ 8702 case 'T': /* floating point target register */ 8703 case 'R': /* floating point source register */ 8704 case 'V': 8705 case 'W': 8706 s_reset = s; 8707 /* Accept $fN for FP and MDMX register numbers, and in 8708 addition accept $vN for MDMX register numbers. */ 8709 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2])) 8710 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v' 8711 && ISDIGIT (s[2]))) 8712 { 8713 s += 2; 8714 regno = 0; 8715 do 8716 { 8717 regno *= 10; 8718 regno += *s - '0'; 8719 ++s; 8720 } 8721 while (ISDIGIT (*s)); 8722 8723 if (regno > 31) 8724 as_bad (_("Invalid float register number (%d)"), regno); 8725 8726 if ((regno & 1) != 0 8727 && HAVE_32BIT_FPRS 8728 && ! (strcmp (str, "mtc1") == 0 8729 || strcmp (str, "mfc1") == 0 8730 || strcmp (str, "lwc1") == 0 8731 || strcmp (str, "swc1") == 0 8732 || strcmp (str, "l.s") == 0 8733 || strcmp (str, "s.s") == 0)) 8734 as_warn (_("Float register should be even, was %d"), 8735 regno); 8736 8737 c = *args; 8738 if (*s == ' ') 8739 ++s; 8740 if (args[1] != *s) 8741 { 8742 if (c == 'V' || c == 'W') 8743 { 8744 regno = lastregno; 8745 s = s_reset; 8746 ++args; 8747 } 8748 } 8749 switch (c) 8750 { 8751 case 'D': 8752 case 'X': 8753 ip->insn_opcode |= regno << OP_SH_FD; 8754 break; 8755 case 'V': 8756 case 'S': 8757 case 'Y': 8758 ip->insn_opcode |= regno << OP_SH_FS; 8759 break; 8760 case 'Q': 8761 /* This is like 'Z', but also needs to fix the MDMX 8762 vector/scalar select bits. Note that the 8763 scalar immediate case is handled above. */ 8764 if (*s == '[') 8765 { 8766 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL)); 8767 int max_el = (is_qh ? 3 : 7); 8768 s++; 8769 my_getExpression(&imm_expr, s); 8770 check_absolute_expr (ip, &imm_expr); 8771 s = expr_end; 8772 if (imm_expr.X_add_number > max_el) 8773 as_bad(_("Bad element selector %ld"), 8774 (long) imm_expr.X_add_number); 8775 imm_expr.X_add_number &= max_el; 8776 ip->insn_opcode |= (imm_expr.X_add_number 8777 << (OP_SH_VSEL + 8778 (is_qh ? 2 : 1))); 8779 if (*s != ']') 8780 as_warn(_("Expecting ']' found '%s'"), s); 8781 else 8782 s++; 8783 } 8784 else 8785 { 8786 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL)) 8787 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH 8788 << OP_SH_VSEL); 8789 else 8790 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB << 8791 OP_SH_VSEL); 8792 } 8793 /* Fall through */ 8794 case 'W': 8795 case 'T': 8796 case 'Z': 8797 ip->insn_opcode |= regno << OP_SH_FT; 8798 break; 8799 case 'R': 8800 ip->insn_opcode |= regno << OP_SH_FR; 8801 break; 8802 } 8803 lastregno = regno; 8804 continue; 8805 } 8806 8807 switch (*args++) 8808 { 8809 case 'V': 8810 ip->insn_opcode |= lastregno << OP_SH_FS; 8811 continue; 8812 case 'W': 8813 ip->insn_opcode |= lastregno << OP_SH_FT; 8814 continue; 8815 } 8816 break; 8817 8818 case 'I': 8819 my_getExpression (&imm_expr, s); 8820 if (imm_expr.X_op != O_big 8821 && imm_expr.X_op != O_constant) 8822 insn_error = _("absolute expression required"); 8823 normalize_constant_expr (&imm_expr); 8824 s = expr_end; 8825 continue; 8826 8827 case 'A': 8828 my_getExpression (&offset_expr, s); 8829 *imm_reloc = BFD_RELOC_32; 8830 s = expr_end; 8831 continue; 8832 8833 case 'F': 8834 case 'L': 8835 case 'f': 8836 case 'l': 8837 { 8838 int f64; 8839 int using_gprs; 8840 char *save_in; 8841 char *err; 8842 unsigned char temp[8]; 8843 int len; 8844 unsigned int length; 8845 segT seg; 8846 subsegT subseg; 8847 char *p; 8848 8849 /* These only appear as the last operand in an 8850 instruction, and every instruction that accepts 8851 them in any variant accepts them in all variants. 8852 This means we don't have to worry about backing out 8853 any changes if the instruction does not match. 8854 8855 The difference between them is the size of the 8856 floating point constant and where it goes. For 'F' 8857 and 'L' the constant is 64 bits; for 'f' and 'l' it 8858 is 32 bits. Where the constant is placed is based 8859 on how the MIPS assembler does things: 8860 F -- .rdata 8861 L -- .lit8 8862 f -- immediate value 8863 l -- .lit4 8864 8865 The .lit4 and .lit8 sections are only used if 8866 permitted by the -G argument. 8867 8868 When generating embedded PIC code, we use the 8869 .lit8 section but not the .lit4 section (we can do 8870 .lit4 inline easily; we need to put .lit8 8871 somewhere in the data segment, and using .lit8 8872 permits the linker to eventually combine identical 8873 .lit8 entries). 8874 8875 The code below needs to know whether the target register 8876 is 32 or 64 bits wide. It relies on the fact 'f' and 8877 'F' are used with GPR-based instructions and 'l' and 8878 'L' are used with FPR-based instructions. */ 8879 8880 f64 = *args == 'F' || *args == 'L'; 8881 using_gprs = *args == 'F' || *args == 'f'; 8882 8883 save_in = input_line_pointer; 8884 input_line_pointer = s; 8885 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); 8886 length = len; 8887 s = input_line_pointer; 8888 input_line_pointer = save_in; 8889 if (err != NULL && *err != '\0') 8890 { 8891 as_bad (_("Bad floating point constant: %s"), err); 8892 memset (temp, '\0', sizeof temp); 8893 length = f64 ? 8 : 4; 8894 } 8895 8896 assert (length == (unsigned) (f64 ? 8 : 4)); 8897 8898 if (*args == 'f' 8899 || (*args == 'l' 8900 && (! USE_GLOBAL_POINTER_OPT 8901 || mips_pic == EMBEDDED_PIC 8902 || g_switch_value < 4 8903 || (temp[0] == 0 && temp[1] == 0) 8904 || (temp[2] == 0 && temp[3] == 0)))) 8905 { 8906 imm_expr.X_op = O_constant; 8907 if (! target_big_endian) 8908 imm_expr.X_add_number = bfd_getl32 (temp); 8909 else 8910 imm_expr.X_add_number = bfd_getb32 (temp); 8911 } 8912 else if (length > 4 8913 && ! mips_disable_float_construction 8914 /* Constants can only be constructed in GPRs and 8915 copied to FPRs if the GPRs are at least as wide 8916 as the FPRs. Force the constant into memory if 8917 we are using 64-bit FPRs but the GPRs are only 8918 32 bits wide. */ 8919 && (using_gprs 8920 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) 8921 && ((temp[0] == 0 && temp[1] == 0) 8922 || (temp[2] == 0 && temp[3] == 0)) 8923 && ((temp[4] == 0 && temp[5] == 0) 8924 || (temp[6] == 0 && temp[7] == 0))) 8925 { 8926 /* The value is simple enough to load with a couple of 8927 instructions. If using 32-bit registers, set 8928 imm_expr to the high order 32 bits and offset_expr to 8929 the low order 32 bits. Otherwise, set imm_expr to 8930 the entire 64 bit constant. */ 8931 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) 8932 { 8933 imm_expr.X_op = O_constant; 8934 offset_expr.X_op = O_constant; 8935 if (! target_big_endian) 8936 { 8937 imm_expr.X_add_number = bfd_getl32 (temp + 4); 8938 offset_expr.X_add_number = bfd_getl32 (temp); 8939 } 8940 else 8941 { 8942 imm_expr.X_add_number = bfd_getb32 (temp); 8943 offset_expr.X_add_number = bfd_getb32 (temp + 4); 8944 } 8945 if (offset_expr.X_add_number == 0) 8946 offset_expr.X_op = O_absent; 8947 } 8948 else if (sizeof (imm_expr.X_add_number) > 4) 8949 { 8950 imm_expr.X_op = O_constant; 8951 if (! target_big_endian) 8952 imm_expr.X_add_number = bfd_getl64 (temp); 8953 else 8954 imm_expr.X_add_number = bfd_getb64 (temp); 8955 } 8956 else 8957 { 8958 imm_expr.X_op = O_big; 8959 imm_expr.X_add_number = 4; 8960 if (! target_big_endian) 8961 { 8962 generic_bignum[0] = bfd_getl16 (temp); 8963 generic_bignum[1] = bfd_getl16 (temp + 2); 8964 generic_bignum[2] = bfd_getl16 (temp + 4); 8965 generic_bignum[3] = bfd_getl16 (temp + 6); 8966 } 8967 else 8968 { 8969 generic_bignum[0] = bfd_getb16 (temp + 6); 8970 generic_bignum[1] = bfd_getb16 (temp + 4); 8971 generic_bignum[2] = bfd_getb16 (temp + 2); 8972 generic_bignum[3] = bfd_getb16 (temp); 8973 } 8974 } 8975 } 8976 else 8977 { 8978 const char *newname; 8979 segT new_seg; 8980 8981 /* Switch to the right section. */ 8982 seg = now_seg; 8983 subseg = now_subseg; 8984 switch (*args) 8985 { 8986 default: /* unused default case avoids warnings. */ 8987 case 'L': 8988 newname = RDATA_SECTION_NAME; 8989 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) 8990 || mips_pic == EMBEDDED_PIC) 8991 newname = ".lit8"; 8992 break; 8993 case 'F': 8994 if (mips_pic == EMBEDDED_PIC) 8995 newname = ".lit8"; 8996 else 8997 newname = RDATA_SECTION_NAME; 8998 break; 8999 case 'l': 9000 assert (!USE_GLOBAL_POINTER_OPT 9001 || g_switch_value >= 4); 9002 newname = ".lit4"; 9003 break; 9004 } 9005 new_seg = subseg_new (newname, (subsegT) 0); 9006 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 9007 bfd_set_section_flags (stdoutput, new_seg, 9008 (SEC_ALLOC 9009 | SEC_LOAD 9010 | SEC_READONLY 9011 | SEC_DATA)); 9012 frag_align (*args == 'l' ? 2 : 3, 0, 0); 9013 if (OUTPUT_FLAVOR == bfd_target_elf_flavour 9014 && strcmp (TARGET_OS, "elf") != 0) 9015 record_alignment (new_seg, 4); 9016 else 9017 record_alignment (new_seg, *args == 'l' ? 2 : 3); 9018 if (seg == now_seg) 9019 as_bad (_("Can't use floating point insn in this section")); 9020 9021 /* Set the argument to the current address in the 9022 section. */ 9023 offset_expr.X_op = O_symbol; 9024 offset_expr.X_add_symbol = 9025 symbol_new ("L0\001", now_seg, 9026 (valueT) frag_now_fix (), frag_now); 9027 offset_expr.X_add_number = 0; 9028 9029 /* Put the floating point number into the section. */ 9030 p = frag_more ((int) length); 9031 memcpy (p, temp, length); 9032 9033 /* Switch back to the original section. */ 9034 subseg_set (seg, subseg); 9035 } 9036 } 9037 continue; 9038 9039 case 'i': /* 16 bit unsigned immediate */ 9040 case 'j': /* 16 bit signed immediate */ 9041 *imm_reloc = BFD_RELOC_LO16; 9042 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0) 9043 { 9044 int more; 9045 offsetT minval, maxval; 9046 9047 more = (insn + 1 < &mips_opcodes[NUMOPCODES] 9048 && strcmp (insn->name, insn[1].name) == 0); 9049 9050 /* If the expression was written as an unsigned number, 9051 only treat it as signed if there are no more 9052 alternatives. */ 9053 if (more 9054 && *args == 'j' 9055 && sizeof (imm_expr.X_add_number) <= 4 9056 && imm_expr.X_op == O_constant 9057 && imm_expr.X_add_number < 0 9058 && imm_expr.X_unsigned 9059 && HAVE_64BIT_GPRS) 9060 break; 9061 9062 /* For compatibility with older assemblers, we accept 9063 0x8000-0xffff as signed 16-bit numbers when only 9064 signed numbers are allowed. */ 9065 if (*args == 'i') 9066 minval = 0, maxval = 0xffff; 9067 else if (more) 9068 minval = -0x8000, maxval = 0x7fff; 9069 else 9070 minval = -0x8000, maxval = 0xffff; 9071 9072 if (imm_expr.X_op != O_constant 9073 || imm_expr.X_add_number < minval 9074 || imm_expr.X_add_number > maxval) 9075 { 9076 if (more) 9077 break; 9078 if (imm_expr.X_op == O_constant 9079 || imm_expr.X_op == O_big) 9080 as_bad (_("expression out of range")); 9081 } 9082 } 9083 s = expr_end; 9084 continue; 9085 9086 case 'o': /* 16 bit offset */ 9087 /* Check whether there is only a single bracketed expression 9088 left. If so, it must be the base register and the 9089 constant must be zero. */ 9090 if (*s == '(' && strchr (s + 1, '(') == 0) 9091 { 9092 offset_expr.X_op = O_constant; 9093 offset_expr.X_add_number = 0; 9094 continue; 9095 } 9096 9097 /* If this value won't fit into a 16 bit offset, then go 9098 find a macro that will generate the 32 bit offset 9099 code pattern. */ 9100 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0 9101 && (offset_expr.X_op != O_constant 9102 || offset_expr.X_add_number >= 0x8000 9103 || offset_expr.X_add_number < -0x8000)) 9104 break; 9105 9106 s = expr_end; 9107 continue; 9108 9109 case 'p': /* pc relative offset */ 9110 *offset_reloc = BFD_RELOC_16_PCREL_S2; 9111 my_getExpression (&offset_expr, s); 9112 s = expr_end; 9113 continue; 9114 9115 case 'u': /* upper 16 bits */ 9116 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0 9117 && imm_expr.X_op == O_constant 9118 && (imm_expr.X_add_number < 0 9119 || imm_expr.X_add_number >= 0x10000)) 9120 as_bad (_("lui expression not in range 0..65535")); 9121 s = expr_end; 9122 continue; 9123 9124 case 'a': /* 26 bit address */ 9125 my_getExpression (&offset_expr, s); 9126 s = expr_end; 9127 *offset_reloc = BFD_RELOC_MIPS_JMP; 9128 continue; 9129 9130 case 'N': /* 3 bit branch condition code */ 9131 case 'M': /* 3 bit compare condition code */ 9132 if (strncmp (s, "$fcc", 4) != 0) 9133 break; 9134 s += 4; 9135 regno = 0; 9136 do 9137 { 9138 regno *= 10; 9139 regno += *s - '0'; 9140 ++s; 9141 } 9142 while (ISDIGIT (*s)); 9143 if (regno > 7) 9144 as_bad (_("Invalid condition code register $fcc%d"), regno); 9145 if ((strcmp(str + strlen(str) - 3, ".ps") == 0 9146 || strcmp(str + strlen(str) - 5, "any2f") == 0 9147 || strcmp(str + strlen(str) - 5, "any2t") == 0) 9148 && (regno & 1) != 0) 9149 as_warn(_("Condition code register should be even for %s, was %d"), 9150 str, regno); 9151 if ((strcmp(str + strlen(str) - 5, "any4f") == 0 9152 || strcmp(str + strlen(str) - 5, "any4t") == 0) 9153 && (regno & 3) != 0) 9154 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"), 9155 str, regno); 9156 if (*args == 'N') 9157 ip->insn_opcode |= regno << OP_SH_BCC; 9158 else 9159 ip->insn_opcode |= regno << OP_SH_CCC; 9160 continue; 9161 9162 case 'H': 9163 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) 9164 s += 2; 9165 if (ISDIGIT (*s)) 9166 { 9167 c = 0; 9168 do 9169 { 9170 c *= 10; 9171 c += *s - '0'; 9172 ++s; 9173 } 9174 while (ISDIGIT (*s)); 9175 } 9176 else 9177 c = 8; /* Invalid sel value. */ 9178 9179 if (c > 7) 9180 as_bad (_("invalid coprocessor sub-selection value (0-7)")); 9181 ip->insn_opcode |= c; 9182 continue; 9183 9184 case 'e': 9185 /* Must be at least one digit. */ 9186 my_getExpression (&imm_expr, s); 9187 check_absolute_expr (ip, &imm_expr); 9188 9189 if ((unsigned long) imm_expr.X_add_number 9190 > (unsigned long) OP_MASK_VECBYTE) 9191 { 9192 as_bad (_("bad byte vector index (%ld)"), 9193 (long) imm_expr.X_add_number); 9194 imm_expr.X_add_number = 0; 9195 } 9196 9197 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE; 9198 imm_expr.X_op = O_absent; 9199 s = expr_end; 9200 continue; 9201 9202 case '%': 9203 my_getExpression (&imm_expr, s); 9204 check_absolute_expr (ip, &imm_expr); 9205 9206 if ((unsigned long) imm_expr.X_add_number 9207 > (unsigned long) OP_MASK_VECALIGN) 9208 { 9209 as_bad (_("bad byte vector index (%ld)"), 9210 (long) imm_expr.X_add_number); 9211 imm_expr.X_add_number = 0; 9212 } 9213 9214 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN; 9215 imm_expr.X_op = O_absent; 9216 s = expr_end; 9217 continue; 9218 9219 default: 9220 as_bad (_("bad char = '%c'\n"), *args); 9221 internalError (); 9222 } 9223 break; 9224 } 9225 /* Args don't match. */ 9226 if (insn + 1 < &mips_opcodes[NUMOPCODES] && 9227 !strcmp (insn->name, insn[1].name)) 9228 { 9229 ++insn; 9230 s = argsStart; 9231 insn_error = _("illegal operands"); 9232 continue; 9233 } 9234 if (save_c) 9235 *(--s) = save_c; 9236 insn_error = _("illegal operands"); 9237 return; 9238 } 9239} 9240 9241/* This routine assembles an instruction into its binary format when 9242 assembling for the mips16. As a side effect, it sets one of the 9243 global variables imm_reloc or offset_reloc to the type of 9244 relocation to do if one of the operands is an address expression. 9245 It also sets mips16_small and mips16_ext if the user explicitly 9246 requested a small or extended instruction. */ 9247 9248static void 9249mips16_ip (char *str, struct mips_cl_insn *ip) 9250{ 9251 char *s; 9252 const char *args; 9253 struct mips_opcode *insn; 9254 char *argsstart; 9255 unsigned int regno; 9256 unsigned int lastregno = 0; 9257 char *s_reset; 9258 9259 insn_error = NULL; 9260 9261 mips16_small = FALSE; 9262 mips16_ext = FALSE; 9263 9264 for (s = str; ISLOWER (*s); ++s) 9265 ; 9266 switch (*s) 9267 { 9268 case '\0': 9269 break; 9270 9271 case ' ': 9272 *s++ = '\0'; 9273 break; 9274 9275 case '.': 9276 if (s[1] == 't' && s[2] == ' ') 9277 { 9278 *s = '\0'; 9279 mips16_small = TRUE; 9280 s += 3; 9281 break; 9282 } 9283 else if (s[1] == 'e' && s[2] == ' ') 9284 { 9285 *s = '\0'; 9286 mips16_ext = TRUE; 9287 s += 3; 9288 break; 9289 } 9290 /* Fall through. */ 9291 default: 9292 insn_error = _("unknown opcode"); 9293 return; 9294 } 9295 9296 if (mips_opts.noautoextend && ! mips16_ext) 9297 mips16_small = TRUE; 9298 9299 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) 9300 { 9301 insn_error = _("unrecognized opcode"); 9302 return; 9303 } 9304 9305 argsstart = s; 9306 for (;;) 9307 { 9308 assert (strcmp (insn->name, str) == 0); 9309 9310 ip->insn_mo = insn; 9311 ip->insn_opcode = insn->match; 9312 ip->use_extend = FALSE; 9313 imm_expr.X_op = O_absent; 9314 imm_reloc[0] = BFD_RELOC_UNUSED; 9315 imm_reloc[1] = BFD_RELOC_UNUSED; 9316 imm_reloc[2] = BFD_RELOC_UNUSED; 9317 imm2_expr.X_op = O_absent; 9318 offset_expr.X_op = O_absent; 9319 offset_reloc[0] = BFD_RELOC_UNUSED; 9320 offset_reloc[1] = BFD_RELOC_UNUSED; 9321 offset_reloc[2] = BFD_RELOC_UNUSED; 9322 for (args = insn->args; 1; ++args) 9323 { 9324 int c; 9325 9326 if (*s == ' ') 9327 ++s; 9328 9329 /* In this switch statement we call break if we did not find 9330 a match, continue if we did find a match, or return if we 9331 are done. */ 9332 9333 c = *args; 9334 switch (c) 9335 { 9336 case '\0': 9337 if (*s == '\0') 9338 { 9339 /* Stuff the immediate value in now, if we can. */ 9340 if (imm_expr.X_op == O_constant 9341 && *imm_reloc > BFD_RELOC_UNUSED 9342 && insn->pinfo != INSN_MACRO) 9343 { 9344 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED, 9345 imm_expr.X_add_number, TRUE, mips16_small, 9346 mips16_ext, &ip->insn_opcode, 9347 &ip->use_extend, &ip->extend); 9348 imm_expr.X_op = O_absent; 9349 *imm_reloc = BFD_RELOC_UNUSED; 9350 } 9351 9352 return; 9353 } 9354 break; 9355 9356 case ',': 9357 if (*s++ == c) 9358 continue; 9359 s--; 9360 switch (*++args) 9361 { 9362 case 'v': 9363 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; 9364 continue; 9365 case 'w': 9366 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; 9367 continue; 9368 } 9369 break; 9370 9371 case '(': 9372 case ')': 9373 if (*s++ == c) 9374 continue; 9375 break; 9376 9377 case 'v': 9378 case 'w': 9379 if (s[0] != '$') 9380 { 9381 if (c == 'v') 9382 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; 9383 else 9384 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; 9385 ++args; 9386 continue; 9387 } 9388 /* Fall through. */ 9389 case 'x': 9390 case 'y': 9391 case 'z': 9392 case 'Z': 9393 case '0': 9394 case 'S': 9395 case 'R': 9396 case 'X': 9397 case 'Y': 9398 if (s[0] != '$') 9399 break; 9400 s_reset = s; 9401 if (ISDIGIT (s[1])) 9402 { 9403 ++s; 9404 regno = 0; 9405 do 9406 { 9407 regno *= 10; 9408 regno += *s - '0'; 9409 ++s; 9410 } 9411 while (ISDIGIT (*s)); 9412 if (regno > 31) 9413 { 9414 as_bad (_("invalid register number (%d)"), regno); 9415 regno = 2; 9416 } 9417 } 9418 else 9419 { 9420 if (s[1] == 'r' && s[2] == 'a') 9421 { 9422 s += 3; 9423 regno = RA; 9424 } 9425 else if (s[1] == 'f' && s[2] == 'p') 9426 { 9427 s += 3; 9428 regno = FP; 9429 } 9430 else if (s[1] == 's' && s[2] == 'p') 9431 { 9432 s += 3; 9433 regno = SP; 9434 } 9435 else if (s[1] == 'g' && s[2] == 'p') 9436 { 9437 s += 3; 9438 regno = GP; 9439 } 9440 else if (s[1] == 'a' && s[2] == 't') 9441 { 9442 s += 3; 9443 regno = AT; 9444 } 9445 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') 9446 { 9447 s += 4; 9448 regno = KT0; 9449 } 9450 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') 9451 { 9452 s += 4; 9453 regno = KT1; 9454 } 9455 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o') 9456 { 9457 s += 5; 9458 regno = ZERO; 9459 } 9460 else 9461 break; 9462 } 9463 9464 if (*s == ' ') 9465 ++s; 9466 if (args[1] != *s) 9467 { 9468 if (c == 'v' || c == 'w') 9469 { 9470 regno = mips16_to_32_reg_map[lastregno]; 9471 s = s_reset; 9472 ++args; 9473 } 9474 } 9475 9476 switch (c) 9477 { 9478 case 'x': 9479 case 'y': 9480 case 'z': 9481 case 'v': 9482 case 'w': 9483 case 'Z': 9484 regno = mips32_to_16_reg_map[regno]; 9485 break; 9486 9487 case '0': 9488 if (regno != 0) 9489 regno = ILLEGAL_REG; 9490 break; 9491 9492 case 'S': 9493 if (regno != SP) 9494 regno = ILLEGAL_REG; 9495 break; 9496 9497 case 'R': 9498 if (regno != RA) 9499 regno = ILLEGAL_REG; 9500 break; 9501 9502 case 'X': 9503 case 'Y': 9504 if (regno == AT && ! mips_opts.noat) 9505 as_warn (_("used $at without \".set noat\"")); 9506 break; 9507 9508 default: 9509 internalError (); 9510 } 9511 9512 if (regno == ILLEGAL_REG) 9513 break; 9514 9515 switch (c) 9516 { 9517 case 'x': 9518 case 'v': 9519 ip->insn_opcode |= regno << MIPS16OP_SH_RX; 9520 break; 9521 case 'y': 9522 case 'w': 9523 ip->insn_opcode |= regno << MIPS16OP_SH_RY; 9524 break; 9525 case 'z': 9526 ip->insn_opcode |= regno << MIPS16OP_SH_RZ; 9527 break; 9528 case 'Z': 9529 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; 9530 case '0': 9531 case 'S': 9532 case 'R': 9533 break; 9534 case 'X': 9535 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; 9536 break; 9537 case 'Y': 9538 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); 9539 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; 9540 break; 9541 default: 9542 internalError (); 9543 } 9544 9545 lastregno = regno; 9546 continue; 9547 9548 case 'P': 9549 if (strncmp (s, "$pc", 3) == 0) 9550 { 9551 s += 3; 9552 continue; 9553 } 9554 break; 9555 9556 case '<': 9557 case '>': 9558 case '[': 9559 case ']': 9560 case '4': 9561 case '5': 9562 case 'H': 9563 case 'W': 9564 case 'D': 9565 case 'j': 9566 case '8': 9567 case 'V': 9568 case 'C': 9569 case 'U': 9570 case 'k': 9571 case 'K': 9572 if (s[0] == '%' 9573 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) 9574 { 9575 /* This is %gprel(SYMBOL). We need to read SYMBOL, 9576 and generate the appropriate reloc. If the text 9577 inside %gprel is not a symbol name with an 9578 optional offset, then we generate a normal reloc 9579 and will probably fail later. */ 9580 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); 9581 if (imm_expr.X_op == O_symbol) 9582 { 9583 mips16_ext = TRUE; 9584 *imm_reloc = BFD_RELOC_MIPS16_GPREL; 9585 s = expr_end; 9586 ip->use_extend = TRUE; 9587 ip->extend = 0; 9588 continue; 9589 } 9590 } 9591 else 9592 { 9593 /* Just pick up a normal expression. */ 9594 my_getExpression (&imm_expr, s); 9595 } 9596 9597 if (imm_expr.X_op == O_register) 9598 { 9599 /* What we thought was an expression turned out to 9600 be a register. */ 9601 9602 if (s[0] == '(' && args[1] == '(') 9603 { 9604 /* It looks like the expression was omitted 9605 before a register indirection, which means 9606 that the expression is implicitly zero. We 9607 still set up imm_expr, so that we handle 9608 explicit extensions correctly. */ 9609 imm_expr.X_op = O_constant; 9610 imm_expr.X_add_number = 0; 9611 *imm_reloc = (int) BFD_RELOC_UNUSED + c; 9612 continue; 9613 } 9614 9615 break; 9616 } 9617 9618 /* We need to relax this instruction. */ 9619 *imm_reloc = (int) BFD_RELOC_UNUSED + c; 9620 s = expr_end; 9621 continue; 9622 9623 case 'p': 9624 case 'q': 9625 case 'A': 9626 case 'B': 9627 case 'E': 9628 /* We use offset_reloc rather than imm_reloc for the PC 9629 relative operands. This lets macros with both 9630 immediate and address operands work correctly. */ 9631 my_getExpression (&offset_expr, s); 9632 9633 if (offset_expr.X_op == O_register) 9634 break; 9635 9636 /* We need to relax this instruction. */ 9637 *offset_reloc = (int) BFD_RELOC_UNUSED + c; 9638 s = expr_end; 9639 continue; 9640 9641 case '6': /* break code */ 9642 my_getExpression (&imm_expr, s); 9643 check_absolute_expr (ip, &imm_expr); 9644 if ((unsigned long) imm_expr.X_add_number > 63) 9645 { 9646 as_warn (_("Invalid value for `%s' (%lu)"), 9647 ip->insn_mo->name, 9648 (unsigned long) imm_expr.X_add_number); 9649 imm_expr.X_add_number &= 0x3f; 9650 } 9651 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; 9652 imm_expr.X_op = O_absent; 9653 s = expr_end; 9654 continue; 9655 9656 case 'a': /* 26 bit address */ 9657 my_getExpression (&offset_expr, s); 9658 s = expr_end; 9659 *offset_reloc = BFD_RELOC_MIPS16_JMP; 9660 ip->insn_opcode <<= 16; 9661 continue; 9662 9663 case 'l': /* register list for entry macro */ 9664 case 'L': /* register list for exit macro */ 9665 { 9666 int mask; 9667 9668 if (c == 'l') 9669 mask = 0; 9670 else 9671 mask = 7 << 3; 9672 while (*s != '\0') 9673 { 9674 int freg, reg1, reg2; 9675 9676 while (*s == ' ' || *s == ',') 9677 ++s; 9678 if (*s != '$') 9679 { 9680 as_bad (_("can't parse register list")); 9681 break; 9682 } 9683 ++s; 9684 if (*s != 'f') 9685 freg = 0; 9686 else 9687 { 9688 freg = 1; 9689 ++s; 9690 } 9691 reg1 = 0; 9692 while (ISDIGIT (*s)) 9693 { 9694 reg1 *= 10; 9695 reg1 += *s - '0'; 9696 ++s; 9697 } 9698 if (*s == ' ') 9699 ++s; 9700 if (*s != '-') 9701 reg2 = reg1; 9702 else 9703 { 9704 ++s; 9705 if (*s != '$') 9706 break; 9707 ++s; 9708 if (freg) 9709 { 9710 if (*s == 'f') 9711 ++s; 9712 else 9713 { 9714 as_bad (_("invalid register list")); 9715 break; 9716 } 9717 } 9718 reg2 = 0; 9719 while (ISDIGIT (*s)) 9720 { 9721 reg2 *= 10; 9722 reg2 += *s - '0'; 9723 ++s; 9724 } 9725 } 9726 if (freg && reg1 == 0 && reg2 == 0 && c == 'L') 9727 { 9728 mask &= ~ (7 << 3); 9729 mask |= 5 << 3; 9730 } 9731 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') 9732 { 9733 mask &= ~ (7 << 3); 9734 mask |= 6 << 3; 9735 } 9736 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') 9737 mask |= (reg2 - 3) << 3; 9738 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) 9739 mask |= (reg2 - 15) << 1; 9740 else if (reg1 == RA && reg2 == RA) 9741 mask |= 1; 9742 else 9743 { 9744 as_bad (_("invalid register list")); 9745 break; 9746 } 9747 } 9748 /* The mask is filled in in the opcode table for the 9749 benefit of the disassembler. We remove it before 9750 applying the actual mask. */ 9751 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); 9752 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; 9753 } 9754 continue; 9755 9756 case 'e': /* extend code */ 9757 my_getExpression (&imm_expr, s); 9758 check_absolute_expr (ip, &imm_expr); 9759 if ((unsigned long) imm_expr.X_add_number > 0x7ff) 9760 { 9761 as_warn (_("Invalid value for `%s' (%lu)"), 9762 ip->insn_mo->name, 9763 (unsigned long) imm_expr.X_add_number); 9764 imm_expr.X_add_number &= 0x7ff; 9765 } 9766 ip->insn_opcode |= imm_expr.X_add_number; 9767 imm_expr.X_op = O_absent; 9768 s = expr_end; 9769 continue; 9770 9771 default: 9772 internalError (); 9773 } 9774 break; 9775 } 9776 9777 /* Args don't match. */ 9778 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && 9779 strcmp (insn->name, insn[1].name) == 0) 9780 { 9781 ++insn; 9782 s = argsstart; 9783 continue; 9784 } 9785 9786 insn_error = _("illegal operands"); 9787 9788 return; 9789 } 9790} 9791 9792/* This structure holds information we know about a mips16 immediate 9793 argument type. */ 9794 9795struct mips16_immed_operand 9796{ 9797 /* The type code used in the argument string in the opcode table. */ 9798 int type; 9799 /* The number of bits in the short form of the opcode. */ 9800 int nbits; 9801 /* The number of bits in the extended form of the opcode. */ 9802 int extbits; 9803 /* The amount by which the short form is shifted when it is used; 9804 for example, the sw instruction has a shift count of 2. */ 9805 int shift; 9806 /* The amount by which the short form is shifted when it is stored 9807 into the instruction code. */ 9808 int op_shift; 9809 /* Non-zero if the short form is unsigned. */ 9810 int unsp; 9811 /* Non-zero if the extended form is unsigned. */ 9812 int extu; 9813 /* Non-zero if the value is PC relative. */ 9814 int pcrel; 9815}; 9816 9817/* The mips16 immediate operand types. */ 9818 9819static const struct mips16_immed_operand mips16_immed_operands[] = 9820{ 9821 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, 9822 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, 9823 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, 9824 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, 9825 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, 9826 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, 9827 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, 9828 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, 9829 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, 9830 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, 9831 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, 9832 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, 9833 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, 9834 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, 9835 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, 9836 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, 9837 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, 9838 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, 9839 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, 9840 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, 9841 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } 9842}; 9843 9844#define MIPS16_NUM_IMMED \ 9845 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) 9846 9847/* Handle a mips16 instruction with an immediate value. This or's the 9848 small immediate value into *INSN. It sets *USE_EXTEND to indicate 9849 whether an extended value is needed; if one is needed, it sets 9850 *EXTEND to the value. The argument type is TYPE. The value is VAL. 9851 If SMALL is true, an unextended opcode was explicitly requested. 9852 If EXT is true, an extended opcode was explicitly requested. If 9853 WARN is true, warn if EXT does not match reality. */ 9854 9855static void 9856mips16_immed (char *file, unsigned int line, int type, offsetT val, 9857 bfd_boolean warn, bfd_boolean small, bfd_boolean ext, 9858 unsigned long *insn, bfd_boolean *use_extend, 9859 unsigned short *extend) 9860{ 9861 register const struct mips16_immed_operand *op; 9862 int mintiny, maxtiny; 9863 bfd_boolean needext; 9864 9865 op = mips16_immed_operands; 9866 while (op->type != type) 9867 { 9868 ++op; 9869 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); 9870 } 9871 9872 if (op->unsp) 9873 { 9874 if (type == '<' || type == '>' || type == '[' || type == ']') 9875 { 9876 mintiny = 1; 9877 maxtiny = 1 << op->nbits; 9878 } 9879 else 9880 { 9881 mintiny = 0; 9882 maxtiny = (1 << op->nbits) - 1; 9883 } 9884 } 9885 else 9886 { 9887 mintiny = - (1 << (op->nbits - 1)); 9888 maxtiny = (1 << (op->nbits - 1)) - 1; 9889 } 9890 9891 /* Branch offsets have an implicit 0 in the lowest bit. */ 9892 if (type == 'p' || type == 'q') 9893 val /= 2; 9894 9895 if ((val & ((1 << op->shift) - 1)) != 0 9896 || val < (mintiny << op->shift) 9897 || val > (maxtiny << op->shift)) 9898 needext = TRUE; 9899 else 9900 needext = FALSE; 9901 9902 if (warn && ext && ! needext) 9903 as_warn_where (file, line, 9904 _("extended operand requested but not required")); 9905 if (small && needext) 9906 as_bad_where (file, line, _("invalid unextended operand value")); 9907 9908 if (small || (! ext && ! needext)) 9909 { 9910 int insnval; 9911 9912 *use_extend = FALSE; 9913 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); 9914 insnval <<= op->op_shift; 9915 *insn |= insnval; 9916 } 9917 else 9918 { 9919 long minext, maxext; 9920 int extval; 9921 9922 if (op->extu) 9923 { 9924 minext = 0; 9925 maxext = (1 << op->extbits) - 1; 9926 } 9927 else 9928 { 9929 minext = - (1 << (op->extbits - 1)); 9930 maxext = (1 << (op->extbits - 1)) - 1; 9931 } 9932 if (val < minext || val > maxext) 9933 as_bad_where (file, line, 9934 _("operand value out of range for instruction")); 9935 9936 *use_extend = TRUE; 9937 if (op->extbits == 16) 9938 { 9939 extval = ((val >> 11) & 0x1f) | (val & 0x7e0); 9940 val &= 0x1f; 9941 } 9942 else if (op->extbits == 15) 9943 { 9944 extval = ((val >> 11) & 0xf) | (val & 0x7f0); 9945 val &= 0xf; 9946 } 9947 else 9948 { 9949 extval = ((val & 0x1f) << 6) | (val & 0x20); 9950 val = 0; 9951 } 9952 9953 *extend = (unsigned short) extval; 9954 *insn |= val; 9955 } 9956} 9957 9958static const struct percent_op_match 9959{ 9960 const char *str; 9961 bfd_reloc_code_real_type reloc; 9962} percent_op[] = 9963{ 9964 {"%lo", BFD_RELOC_LO16}, 9965#ifdef OBJ_ELF 9966 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, 9967 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, 9968 {"%call16", BFD_RELOC_MIPS_CALL16}, 9969 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, 9970 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, 9971 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, 9972 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, 9973 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, 9974 {"%got", BFD_RELOC_MIPS_GOT16}, 9975 {"%gp_rel", BFD_RELOC_GPREL16}, 9976 {"%half", BFD_RELOC_16}, 9977 {"%highest", BFD_RELOC_MIPS_HIGHEST}, 9978 {"%higher", BFD_RELOC_MIPS_HIGHER}, 9979 {"%neg", BFD_RELOC_MIPS_SUB}, 9980#endif 9981 {"%hi", BFD_RELOC_HI16_S} 9982}; 9983 9984 9985/* Return true if *STR points to a relocation operator. When returning true, 9986 move *STR over the operator and store its relocation code in *RELOC. 9987 Leave both *STR and *RELOC alone when returning false. */ 9988 9989static bfd_boolean 9990parse_relocation (char **str, bfd_reloc_code_real_type *reloc) 9991{ 9992 size_t i; 9993 9994 for (i = 0; i < ARRAY_SIZE (percent_op); i++) 9995 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) 9996 { 9997 *str += strlen (percent_op[i].str); 9998 *reloc = percent_op[i].reloc; 9999 10000 /* Check whether the output BFD supports this relocation. 10001 If not, issue an error and fall back on something safe. */ 10002 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) 10003 { 10004 as_bad ("relocation %s isn't supported by the current ABI", 10005 percent_op[i].str); 10006 *reloc = BFD_RELOC_LO16; 10007 } 10008 return TRUE; 10009 } 10010 return FALSE; 10011} 10012 10013 10014/* Parse string STR as a 16-bit relocatable operand. Store the 10015 expression in *EP and the relocations in the array starting 10016 at RELOC. Return the number of relocation operators used. 10017 10018 On exit, EXPR_END points to the first character after the expression. 10019 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */ 10020 10021static size_t 10022my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 10023 char *str) 10024{ 10025 bfd_reloc_code_real_type reversed_reloc[3]; 10026 size_t reloc_index, i; 10027 int crux_depth, str_depth; 10028 char *crux; 10029 10030 /* Search for the start of the main expression, recoding relocations 10031 in REVERSED_RELOC. End the loop with CRUX pointing to the start 10032 of the main expression and with CRUX_DEPTH containing the number 10033 of open brackets at that point. */ 10034 reloc_index = -1; 10035 str_depth = 0; 10036 do 10037 { 10038 reloc_index++; 10039 crux = str; 10040 crux_depth = str_depth; 10041 10042 /* Skip over whitespace and brackets, keeping count of the number 10043 of brackets. */ 10044 while (*str == ' ' || *str == '\t' || *str == '(') 10045 if (*str++ == '(') 10046 str_depth++; 10047 } 10048 while (*str == '%' 10049 && reloc_index < (HAVE_NEWABI ? 3 : 1) 10050 && parse_relocation (&str, &reversed_reloc[reloc_index])); 10051 10052 my_getExpression (ep, crux); 10053 str = expr_end; 10054 10055 /* Match every open bracket. */ 10056 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 10057 if (*str++ == ')') 10058 crux_depth--; 10059 10060 if (crux_depth > 0) 10061 as_bad ("unclosed '('"); 10062 10063 expr_end = str; 10064 10065 if (reloc_index == 0) 10066 reloc[0] = BFD_RELOC_LO16; 10067 else 10068 { 10069 prev_reloc_op_frag = frag_now; 10070 for (i = 0; i < reloc_index; i++) 10071 reloc[i] = reversed_reloc[reloc_index - 1 - i]; 10072 } 10073 10074 return reloc_index; 10075} 10076 10077static void 10078my_getExpression (expressionS *ep, char *str) 10079{ 10080 char *save_in; 10081 valueT val; 10082 10083 save_in = input_line_pointer; 10084 input_line_pointer = str; 10085 expression (ep); 10086 expr_end = input_line_pointer; 10087 input_line_pointer = save_in; 10088 10089 /* If we are in mips16 mode, and this is an expression based on `.', 10090 then we bump the value of the symbol by 1 since that is how other 10091 text symbols are handled. We don't bother to handle complex 10092 expressions, just `.' plus or minus a constant. */ 10093 if (mips_opts.mips16 10094 && ep->X_op == O_symbol 10095 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 10096 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg 10097 && symbol_get_frag (ep->X_add_symbol) == frag_now 10098 && symbol_constant_p (ep->X_add_symbol) 10099 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) 10100 S_SET_VALUE (ep->X_add_symbol, val + 1); 10101} 10102 10103/* Turn a string in input_line_pointer into a floating point constant 10104 of type TYPE, and store the appropriate bytes in *LITP. The number 10105 of LITTLENUMS emitted is stored in *SIZEP. An error message is 10106 returned, or NULL on OK. */ 10107 10108char * 10109md_atof (int type, char *litP, int *sizeP) 10110{ 10111 int prec; 10112 LITTLENUM_TYPE words[4]; 10113 char *t; 10114 int i; 10115 10116 switch (type) 10117 { 10118 case 'f': 10119 prec = 2; 10120 break; 10121 10122 case 'd': 10123 prec = 4; 10124 break; 10125 10126 default: 10127 *sizeP = 0; 10128 return _("bad call to md_atof"); 10129 } 10130 10131 t = atof_ieee (input_line_pointer, type, words); 10132 if (t) 10133 input_line_pointer = t; 10134 10135 *sizeP = prec * 2; 10136 10137 if (! target_big_endian) 10138 { 10139 for (i = prec - 1; i >= 0; i--) 10140 { 10141 md_number_to_chars (litP, words[i], 2); 10142 litP += 2; 10143 } 10144 } 10145 else 10146 { 10147 for (i = 0; i < prec; i++) 10148 { 10149 md_number_to_chars (litP, words[i], 2); 10150 litP += 2; 10151 } 10152 } 10153 10154 return NULL; 10155} 10156 10157void 10158md_number_to_chars (char *buf, valueT val, int n) 10159{ 10160 if (target_big_endian) 10161 number_to_chars_bigendian (buf, val, n); 10162 else 10163 number_to_chars_littleendian (buf, val, n); 10164} 10165 10166#ifdef OBJ_ELF 10167static int support_64bit_objects(void) 10168{ 10169 const char **list, **l; 10170 int yes; 10171 10172 list = bfd_target_list (); 10173 for (l = list; *l != NULL; l++) 10174#ifdef TE_TMIPS 10175 /* This is traditional mips */ 10176 if (strcmp (*l, "elf64-tradbigmips") == 0 10177 || strcmp (*l, "elf64-tradlittlemips") == 0) 10178#else 10179 if (strcmp (*l, "elf64-bigmips") == 0 10180 || strcmp (*l, "elf64-littlemips") == 0) 10181#endif 10182 break; 10183 yes = (*l != NULL); 10184 free (list); 10185 return yes; 10186} 10187#endif /* OBJ_ELF */ 10188 10189const char *md_shortopts = "O::g::G:"; 10190 10191struct option md_longopts[] = 10192{ 10193 /* Options which specify architecture. */ 10194#define OPTION_ARCH_BASE (OPTION_MD_BASE) 10195#define OPTION_MARCH (OPTION_ARCH_BASE + 0) 10196 {"march", required_argument, NULL, OPTION_MARCH}, 10197#define OPTION_MTUNE (OPTION_ARCH_BASE + 1) 10198 {"mtune", required_argument, NULL, OPTION_MTUNE}, 10199#define OPTION_MIPS1 (OPTION_ARCH_BASE + 2) 10200 {"mips0", no_argument, NULL, OPTION_MIPS1}, 10201 {"mips1", no_argument, NULL, OPTION_MIPS1}, 10202#define OPTION_MIPS2 (OPTION_ARCH_BASE + 3) 10203 {"mips2", no_argument, NULL, OPTION_MIPS2}, 10204#define OPTION_MIPS3 (OPTION_ARCH_BASE + 4) 10205 {"mips3", no_argument, NULL, OPTION_MIPS3}, 10206#define OPTION_MIPS4 (OPTION_ARCH_BASE + 5) 10207 {"mips4", no_argument, NULL, OPTION_MIPS4}, 10208#define OPTION_MIPS5 (OPTION_ARCH_BASE + 6) 10209 {"mips5", no_argument, NULL, OPTION_MIPS5}, 10210#define OPTION_MIPS32 (OPTION_ARCH_BASE + 7) 10211 {"mips32", no_argument, NULL, OPTION_MIPS32}, 10212#define OPTION_MIPS64 (OPTION_ARCH_BASE + 8) 10213 {"mips64", no_argument, NULL, OPTION_MIPS64}, 10214#define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9) 10215 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, 10216#define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10) 10217 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, 10218 10219 /* Options which specify Application Specific Extensions (ASEs). */ 10220#define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11) 10221#define OPTION_MIPS16 (OPTION_ASE_BASE + 0) 10222 {"mips16", no_argument, NULL, OPTION_MIPS16}, 10223#define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1) 10224 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, 10225#define OPTION_MIPS3D (OPTION_ASE_BASE + 2) 10226 {"mips3d", no_argument, NULL, OPTION_MIPS3D}, 10227#define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3) 10228 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, 10229#define OPTION_MDMX (OPTION_ASE_BASE + 4) 10230 {"mdmx", no_argument, NULL, OPTION_MDMX}, 10231#define OPTION_NO_MDMX (OPTION_ASE_BASE + 5) 10232 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, 10233 10234 /* Old-style architecture options. Don't add more of these. */ 10235#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6) 10236#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0) 10237 {"m4650", no_argument, NULL, OPTION_M4650}, 10238#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1) 10239 {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, 10240#define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2) 10241 {"m4010", no_argument, NULL, OPTION_M4010}, 10242#define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3) 10243 {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, 10244#define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4) 10245 {"m4100", no_argument, NULL, OPTION_M4100}, 10246#define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5) 10247 {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, 10248#define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6) 10249 {"m3900", no_argument, NULL, OPTION_M3900}, 10250#define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7) 10251 {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, 10252 10253 /* Options which enable bug fixes. */ 10254#define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8) 10255#define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0) 10256 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, 10257#define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1) 10258 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 10259 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, 10260#define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2) 10261#define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3) 10262 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, 10263 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, 10264 10265 /* Miscellaneous options. */ 10266#define OPTION_MISC_BASE (OPTION_FIX_BASE + 4) 10267#define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0) 10268 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, 10269#define OPTION_TRAP (OPTION_MISC_BASE + 1) 10270 {"trap", no_argument, NULL, OPTION_TRAP}, 10271 {"no-break", no_argument, NULL, OPTION_TRAP}, 10272#define OPTION_BREAK (OPTION_MISC_BASE + 2) 10273 {"break", no_argument, NULL, OPTION_BREAK}, 10274 {"no-trap", no_argument, NULL, OPTION_BREAK}, 10275#define OPTION_EB (OPTION_MISC_BASE + 3) 10276 {"EB", no_argument, NULL, OPTION_EB}, 10277#define OPTION_EL (OPTION_MISC_BASE + 4) 10278 {"EL", no_argument, NULL, OPTION_EL}, 10279#define OPTION_FP32 (OPTION_MISC_BASE + 5) 10280 {"mfp32", no_argument, NULL, OPTION_FP32}, 10281#define OPTION_GP32 (OPTION_MISC_BASE + 6) 10282 {"mgp32", no_argument, NULL, OPTION_GP32}, 10283#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7) 10284 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, 10285#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8) 10286 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, 10287#define OPTION_FP64 (OPTION_MISC_BASE + 9) 10288 {"mfp64", no_argument, NULL, OPTION_FP64}, 10289#define OPTION_GP64 (OPTION_MISC_BASE + 10) 10290 {"mgp64", no_argument, NULL, OPTION_GP64}, 10291#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11) 10292#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12) 10293 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, 10294 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, 10295 10296 /* ELF-specific options. */ 10297#ifdef OBJ_ELF 10298#define OPTION_ELF_BASE (OPTION_MISC_BASE + 13) 10299#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) 10300 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, 10301 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, 10302#define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) 10303 {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, 10304#define OPTION_XGOT (OPTION_ELF_BASE + 2) 10305 {"xgot", no_argument, NULL, OPTION_XGOT}, 10306#define OPTION_MABI (OPTION_ELF_BASE + 3) 10307 {"mabi", required_argument, NULL, OPTION_MABI}, 10308#define OPTION_32 (OPTION_ELF_BASE + 4) 10309 {"32", no_argument, NULL, OPTION_32}, 10310#define OPTION_N32 (OPTION_ELF_BASE + 5) 10311 {"n32", no_argument, NULL, OPTION_N32}, 10312#define OPTION_64 (OPTION_ELF_BASE + 6) 10313 {"64", no_argument, NULL, OPTION_64}, 10314#define OPTION_MDEBUG (OPTION_ELF_BASE + 7) 10315 {"mdebug", no_argument, NULL, OPTION_MDEBUG}, 10316#define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8) 10317 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, 10318#define OPTION_PDR (OPTION_ELF_BASE + 9) 10319 {"mpdr", no_argument, NULL, OPTION_PDR}, 10320#define OPTION_NO_PDR (OPTION_ELF_BASE + 10) 10321 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, 10322#endif /* OBJ_ELF */ 10323 10324 {NULL, no_argument, NULL, 0} 10325}; 10326size_t md_longopts_size = sizeof (md_longopts); 10327 10328/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to 10329 NEW_VALUE. Warn if another value was already specified. Note: 10330 we have to defer parsing the -march and -mtune arguments in order 10331 to handle 'from-abi' correctly, since the ABI might be specified 10332 in a later argument. */ 10333 10334static void 10335mips_set_option_string (const char **string_ptr, const char *new_value) 10336{ 10337 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) 10338 as_warn (_("A different %s was already specified, is now %s"), 10339 string_ptr == &mips_arch_string ? "-march" : "-mtune", 10340 new_value); 10341 10342 *string_ptr = new_value; 10343} 10344 10345int 10346md_parse_option (int c, char *arg) 10347{ 10348 switch (c) 10349 { 10350 case OPTION_CONSTRUCT_FLOATS: 10351 mips_disable_float_construction = 0; 10352 break; 10353 10354 case OPTION_NO_CONSTRUCT_FLOATS: 10355 mips_disable_float_construction = 1; 10356 break; 10357 10358 case OPTION_TRAP: 10359 mips_trap = 1; 10360 break; 10361 10362 case OPTION_BREAK: 10363 mips_trap = 0; 10364 break; 10365 10366 case OPTION_EB: 10367 target_big_endian = 1; 10368 break; 10369 10370 case OPTION_EL: 10371 target_big_endian = 0; 10372 break; 10373 10374 case 'O': 10375 if (arg && arg[1] == '0') 10376 mips_optimize = 1; 10377 else 10378 mips_optimize = 2; 10379 break; 10380 10381 case 'g': 10382 if (arg == NULL) 10383 mips_debug = 2; 10384 else 10385 mips_debug = atoi (arg); 10386 /* When the MIPS assembler sees -g or -g2, it does not do 10387 optimizations which limit full symbolic debugging. We take 10388 that to be equivalent to -O0. */ 10389 if (mips_debug == 2) 10390 mips_optimize = 1; 10391 break; 10392 10393 case OPTION_MIPS1: 10394 file_mips_isa = ISA_MIPS1; 10395 break; 10396 10397 case OPTION_MIPS2: 10398 file_mips_isa = ISA_MIPS2; 10399 break; 10400 10401 case OPTION_MIPS3: 10402 file_mips_isa = ISA_MIPS3; 10403 break; 10404 10405 case OPTION_MIPS4: 10406 file_mips_isa = ISA_MIPS4; 10407 break; 10408 10409 case OPTION_MIPS5: 10410 file_mips_isa = ISA_MIPS5; 10411 break; 10412 10413 case OPTION_MIPS32: 10414 file_mips_isa = ISA_MIPS32; 10415 break; 10416 10417 case OPTION_MIPS32R2: 10418 file_mips_isa = ISA_MIPS32R2; 10419 break; 10420 10421 case OPTION_MIPS64R2: 10422 file_mips_isa = ISA_MIPS64R2; 10423 break; 10424 10425 case OPTION_MIPS64: 10426 file_mips_isa = ISA_MIPS64; 10427 break; 10428 10429 case OPTION_MTUNE: 10430 mips_set_option_string (&mips_tune_string, arg); 10431 break; 10432 10433 case OPTION_MARCH: 10434 mips_set_option_string (&mips_arch_string, arg); 10435 break; 10436 10437 case OPTION_M4650: 10438 mips_set_option_string (&mips_arch_string, "4650"); 10439 mips_set_option_string (&mips_tune_string, "4650"); 10440 break; 10441 10442 case OPTION_NO_M4650: 10443 break; 10444 10445 case OPTION_M4010: 10446 mips_set_option_string (&mips_arch_string, "4010"); 10447 mips_set_option_string (&mips_tune_string, "4010"); 10448 break; 10449 10450 case OPTION_NO_M4010: 10451 break; 10452 10453 case OPTION_M4100: 10454 mips_set_option_string (&mips_arch_string, "4100"); 10455 mips_set_option_string (&mips_tune_string, "4100"); 10456 break; 10457 10458 case OPTION_NO_M4100: 10459 break; 10460 10461 case OPTION_M3900: 10462 mips_set_option_string (&mips_arch_string, "3900"); 10463 mips_set_option_string (&mips_tune_string, "3900"); 10464 break; 10465 10466 case OPTION_NO_M3900: 10467 break; 10468 10469 case OPTION_MDMX: 10470 mips_opts.ase_mdmx = 1; 10471 break; 10472 10473 case OPTION_NO_MDMX: 10474 mips_opts.ase_mdmx = 0; 10475 break; 10476 10477 case OPTION_MIPS16: 10478 mips_opts.mips16 = 1; 10479 mips_no_prev_insn (FALSE); 10480 break; 10481 10482 case OPTION_NO_MIPS16: 10483 mips_opts.mips16 = 0; 10484 mips_no_prev_insn (FALSE); 10485 break; 10486 10487 case OPTION_MIPS3D: 10488 mips_opts.ase_mips3d = 1; 10489 break; 10490 10491 case OPTION_NO_MIPS3D: 10492 mips_opts.ase_mips3d = 0; 10493 break; 10494 10495 case OPTION_MEMBEDDED_PIC: 10496 mips_pic = EMBEDDED_PIC; 10497 if (USE_GLOBAL_POINTER_OPT && g_switch_seen) 10498 { 10499 as_bad (_("-G may not be used with embedded PIC code")); 10500 return 0; 10501 } 10502 g_switch_value = 0x7fffffff; 10503 break; 10504 10505 case OPTION_FIX_VR4120: 10506 mips_fix_vr4120 = 1; 10507 break; 10508 10509 case OPTION_NO_FIX_VR4120: 10510 mips_fix_vr4120 = 0; 10511 break; 10512 10513 case OPTION_RELAX_BRANCH: 10514 mips_relax_branch = 1; 10515 break; 10516 10517 case OPTION_NO_RELAX_BRANCH: 10518 mips_relax_branch = 0; 10519 break; 10520 10521#ifdef OBJ_ELF 10522 /* When generating ELF code, we permit -KPIC and -call_shared to 10523 select SVR4_PIC, and -non_shared to select no PIC. This is 10524 intended to be compatible with Irix 5. */ 10525 case OPTION_CALL_SHARED: 10526 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10527 { 10528 as_bad (_("-call_shared is supported only for ELF format")); 10529 return 0; 10530 } 10531 mips_pic = SVR4_PIC; 10532 mips_abicalls = TRUE; 10533 if (g_switch_seen && g_switch_value != 0) 10534 { 10535 as_bad (_("-G may not be used with SVR4 PIC code")); 10536 return 0; 10537 } 10538 g_switch_value = 0; 10539 break; 10540 10541 case OPTION_NON_SHARED: 10542 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10543 { 10544 as_bad (_("-non_shared is supported only for ELF format")); 10545 return 0; 10546 } 10547 mips_pic = NO_PIC; 10548 mips_abicalls = FALSE; 10549 break; 10550 10551 /* The -xgot option tells the assembler to use 32 offsets when 10552 accessing the got in SVR4_PIC mode. It is for Irix 10553 compatibility. */ 10554 case OPTION_XGOT: 10555 mips_big_got = 1; 10556 break; 10557#endif /* OBJ_ELF */ 10558 10559 case 'G': 10560 if (! USE_GLOBAL_POINTER_OPT) 10561 { 10562 as_bad (_("-G is not supported for this configuration")); 10563 return 0; 10564 } 10565 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) 10566 { 10567 as_bad (_("-G may not be used with SVR4 or embedded PIC code")); 10568 return 0; 10569 } 10570 else 10571 g_switch_value = atoi (arg); 10572 g_switch_seen = 1; 10573 break; 10574 10575#ifdef OBJ_ELF 10576 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 10577 and -mabi=64. */ 10578 case OPTION_32: 10579 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10580 { 10581 as_bad (_("-32 is supported for ELF format only")); 10582 return 0; 10583 } 10584 mips_abi = O32_ABI; 10585 break; 10586 10587 case OPTION_N32: 10588 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10589 { 10590 as_bad (_("-n32 is supported for ELF format only")); 10591 return 0; 10592 } 10593 mips_abi = N32_ABI; 10594 break; 10595 10596 case OPTION_64: 10597 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10598 { 10599 as_bad (_("-64 is supported for ELF format only")); 10600 return 0; 10601 } 10602 mips_abi = N64_ABI; 10603 if (! support_64bit_objects()) 10604 as_fatal (_("No compiled in support for 64 bit object file format")); 10605 break; 10606#endif /* OBJ_ELF */ 10607 10608 case OPTION_GP32: 10609 file_mips_gp32 = 1; 10610 break; 10611 10612 case OPTION_GP64: 10613 file_mips_gp32 = 0; 10614 break; 10615 10616 case OPTION_FP32: 10617 file_mips_fp32 = 1; 10618 break; 10619 10620 case OPTION_FP64: 10621 file_mips_fp32 = 0; 10622 break; 10623 10624#ifdef OBJ_ELF 10625 case OPTION_MABI: 10626 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 10627 { 10628 as_bad (_("-mabi is supported for ELF format only")); 10629 return 0; 10630 } 10631 if (strcmp (arg, "32") == 0) 10632 mips_abi = O32_ABI; 10633 else if (strcmp (arg, "o64") == 0) 10634 mips_abi = O64_ABI; 10635 else if (strcmp (arg, "n32") == 0) 10636 mips_abi = N32_ABI; 10637 else if (strcmp (arg, "64") == 0) 10638 { 10639 mips_abi = N64_ABI; 10640 if (! support_64bit_objects()) 10641 as_fatal (_("No compiled in support for 64 bit object file " 10642 "format")); 10643 } 10644 else if (strcmp (arg, "eabi") == 0) 10645 mips_abi = EABI_ABI; 10646 else 10647 { 10648 as_fatal (_("invalid abi -mabi=%s"), arg); 10649 return 0; 10650 } 10651 break; 10652#endif /* OBJ_ELF */ 10653 10654 case OPTION_M7000_HILO_FIX: 10655 mips_7000_hilo_fix = TRUE; 10656 break; 10657 10658 case OPTION_MNO_7000_HILO_FIX: 10659 mips_7000_hilo_fix = FALSE; 10660 break; 10661 10662#ifdef OBJ_ELF 10663 case OPTION_MDEBUG: 10664 mips_flag_mdebug = TRUE; 10665 break; 10666 10667 case OPTION_NO_MDEBUG: 10668 mips_flag_mdebug = FALSE; 10669 break; 10670 10671 case OPTION_PDR: 10672 mips_flag_pdr = TRUE; 10673 break; 10674 10675 case OPTION_NO_PDR: 10676 mips_flag_pdr = FALSE; 10677 break; 10678#endif /* OBJ_ELF */ 10679 10680 default: 10681 return 0; 10682 } 10683 10684 return 1; 10685} 10686 10687/* Set up globals to generate code for the ISA or processor 10688 described by INFO. */ 10689 10690static void 10691mips_set_architecture (const struct mips_cpu_info *info) 10692{ 10693 if (info != 0) 10694 { 10695 file_mips_arch = info->cpu; 10696 mips_opts.arch = info->cpu; 10697 mips_opts.isa = info->isa; 10698 } 10699} 10700 10701 10702/* Likewise for tuning. */ 10703 10704static void 10705mips_set_tune (const struct mips_cpu_info *info) 10706{ 10707 if (info != 0) 10708 mips_tune = info->cpu; 10709} 10710 10711 10712void 10713mips_after_parse_args (void) 10714{ 10715 const struct mips_cpu_info *arch_info = 0; 10716 const struct mips_cpu_info *tune_info = 0; 10717 10718 /* GP relative stuff not working for PE */ 10719 if (strncmp (TARGET_OS, "pe", 2) == 0 10720 && g_switch_value != 0) 10721 { 10722 if (g_switch_seen) 10723 as_bad (_("-G not supported in this configuration.")); 10724 g_switch_value = 0; 10725 } 10726 10727 if (mips_abi == NO_ABI) 10728 mips_abi = MIPS_DEFAULT_ABI; 10729 10730 /* The following code determines the architecture and register size. 10731 Similar code was added to GCC 3.3 (see override_options() in 10732 config/mips/mips.c). The GAS and GCC code should be kept in sync 10733 as much as possible. */ 10734 10735 if (mips_arch_string != 0) 10736 arch_info = mips_parse_cpu ("-march", mips_arch_string); 10737 10738 if (file_mips_isa != ISA_UNKNOWN) 10739 { 10740 /* Handle -mipsN. At this point, file_mips_isa contains the 10741 ISA level specified by -mipsN, while arch_info->isa contains 10742 the -march selection (if any). */ 10743 if (arch_info != 0) 10744 { 10745 /* -march takes precedence over -mipsN, since it is more descriptive. 10746 There's no harm in specifying both as long as the ISA levels 10747 are the same. */ 10748 if (file_mips_isa != arch_info->isa) 10749 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"), 10750 mips_cpu_info_from_isa (file_mips_isa)->name, 10751 mips_cpu_info_from_isa (arch_info->isa)->name); 10752 } 10753 else 10754 arch_info = mips_cpu_info_from_isa (file_mips_isa); 10755 } 10756 10757 if (arch_info == 0) 10758 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); 10759 10760 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) 10761 as_bad ("-march=%s is not compatible with the selected ABI", 10762 arch_info->name); 10763 10764 mips_set_architecture (arch_info); 10765 10766 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ 10767 if (mips_tune_string != 0) 10768 tune_info = mips_parse_cpu ("-mtune", mips_tune_string); 10769 10770 if (tune_info == 0) 10771 mips_set_tune (arch_info); 10772 else 10773 mips_set_tune (tune_info); 10774 10775 if (file_mips_gp32 >= 0) 10776 { 10777 /* The user specified the size of the integer registers. Make sure 10778 it agrees with the ABI and ISA. */ 10779 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) 10780 as_bad (_("-mgp64 used with a 32-bit processor")); 10781 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) 10782 as_bad (_("-mgp32 used with a 64-bit ABI")); 10783 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) 10784 as_bad (_("-mgp64 used with a 32-bit ABI")); 10785 } 10786 else 10787 { 10788 /* Infer the integer register size from the ABI and processor. 10789 Restrict ourselves to 32-bit registers if that's all the 10790 processor has, or if the ABI cannot handle 64-bit registers. */ 10791 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) 10792 || !ISA_HAS_64BIT_REGS (mips_opts.isa)); 10793 } 10794 10795 /* ??? GAS treats single-float processors as though they had 64-bit 10796 float registers (although it complains when double-precision 10797 instructions are used). As things stand, saying they have 32-bit 10798 registers would lead to spurious "register must be even" messages. 10799 So here we assume float registers are always the same size as 10800 integer ones, unless the user says otherwise. */ 10801 if (file_mips_fp32 < 0) 10802 file_mips_fp32 = file_mips_gp32; 10803 10804 /* End of GCC-shared inference code. */ 10805 10806 /* This flag is set when we have a 64-bit capable CPU but use only 10807 32-bit wide registers. Note that EABI does not use it. */ 10808 if (ISA_HAS_64BIT_REGS (mips_opts.isa) 10809 && ((mips_abi == NO_ABI && file_mips_gp32 == 1) 10810 || mips_abi == O32_ABI)) 10811 mips_32bitmode = 1; 10812 10813 if (mips_opts.isa == ISA_MIPS1 && mips_trap) 10814 as_bad (_("trap exception not supported at ISA 1")); 10815 10816 /* If the selected architecture includes support for ASEs, enable 10817 generation of code for them. */ 10818 if (mips_opts.mips16 == -1) 10819 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; 10820 if (mips_opts.ase_mips3d == -1) 10821 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0; 10822 if (mips_opts.ase_mdmx == -1) 10823 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0; 10824 10825 file_mips_isa = mips_opts.isa; 10826 file_ase_mips16 = mips_opts.mips16; 10827 file_ase_mips3d = mips_opts.ase_mips3d; 10828 file_ase_mdmx = mips_opts.ase_mdmx; 10829 mips_opts.gp32 = file_mips_gp32; 10830 mips_opts.fp32 = file_mips_fp32; 10831 10832 if (mips_flag_mdebug < 0) 10833 { 10834#ifdef OBJ_MAYBE_ECOFF 10835 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour) 10836 mips_flag_mdebug = 1; 10837 else 10838#endif /* OBJ_MAYBE_ECOFF */ 10839 mips_flag_mdebug = 0; 10840 } 10841} 10842 10843void 10844mips_init_after_args (void) 10845{ 10846 /* initialize opcodes */ 10847 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; 10848 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; 10849} 10850 10851long 10852md_pcrel_from (fixS *fixP) 10853{ 10854 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 10855 switch (fixP->fx_r_type) 10856 { 10857 case BFD_RELOC_16_PCREL_S2: 10858 case BFD_RELOC_MIPS_JMP: 10859 /* Return the address of the delay slot. */ 10860 return addr + 4; 10861 default: 10862 return addr; 10863 } 10864} 10865 10866/* This is called before the symbol table is processed. In order to 10867 work with gcc when using mips-tfile, we must keep all local labels. 10868 However, in other cases, we want to discard them. If we were 10869 called with -g, but we didn't see any debugging information, it may 10870 mean that gcc is smuggling debugging information through to 10871 mips-tfile, in which case we must generate all local labels. */ 10872 10873void 10874mips_frob_file_before_adjust (void) 10875{ 10876#ifndef NO_ECOFF_DEBUGGING 10877 if (ECOFF_DEBUGGING 10878 && mips_debug != 0 10879 && ! ecoff_debugging_seen) 10880 flag_keep_locals = 1; 10881#endif 10882} 10883 10884/* Sort any unmatched HI16_S relocs so that they immediately precede 10885 the corresponding LO reloc. This is called before md_apply_fix3 and 10886 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by 10887 explicit use of the %hi modifier. */ 10888 10889void 10890mips_frob_file (void) 10891{ 10892 struct mips_hi_fixup *l; 10893 10894 for (l = mips_hi_fixup_list; l != NULL; l = l->next) 10895 { 10896 segment_info_type *seginfo; 10897 int pass; 10898 10899 assert (reloc_needs_lo_p (l->fixp->fx_r_type)); 10900 10901 /* If a GOT16 relocation turns out to be against a global symbol, 10902 there isn't supposed to be a matching LO. */ 10903 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 10904 && !pic_need_relax (l->fixp->fx_addsy, l->seg)) 10905 continue; 10906 10907 /* Check quickly whether the next fixup happens to be a matching %lo. */ 10908 if (fixup_has_matching_lo_p (l->fixp)) 10909 continue; 10910 10911 /* Look through the fixups for this segment for a matching %lo. 10912 When we find one, move the %hi just in front of it. We do 10913 this in two passes. In the first pass, we try to find a 10914 unique %lo. In the second pass, we permit multiple %hi 10915 relocs for a single %lo (this is a GNU extension). */ 10916 seginfo = seg_info (l->seg); 10917 for (pass = 0; pass < 2; pass++) 10918 { 10919 fixS *f, *prev; 10920 10921 prev = NULL; 10922 for (f = seginfo->fix_root; f != NULL; f = f->fx_next) 10923 { 10924 /* Check whether this is a %lo fixup which matches l->fixp. */ 10925 if (f->fx_r_type == BFD_RELOC_LO16 10926 && f->fx_addsy == l->fixp->fx_addsy 10927 && f->fx_offset == l->fixp->fx_offset 10928 && (pass == 1 10929 || prev == NULL 10930 || !reloc_needs_lo_p (prev->fx_r_type) 10931 || !fixup_has_matching_lo_p (prev))) 10932 { 10933 fixS **pf; 10934 10935 /* Move l->fixp before f. */ 10936 for (pf = &seginfo->fix_root; 10937 *pf != l->fixp; 10938 pf = &(*pf)->fx_next) 10939 assert (*pf != NULL); 10940 10941 *pf = l->fixp->fx_next; 10942 10943 l->fixp->fx_next = f; 10944 if (prev == NULL) 10945 seginfo->fix_root = l->fixp; 10946 else 10947 prev->fx_next = l->fixp; 10948 10949 break; 10950 } 10951 10952 prev = f; 10953 } 10954 10955 if (f != NULL) 10956 break; 10957 10958#if 0 /* GCC code motion plus incomplete dead code elimination 10959 can leave a %hi without a %lo. */ 10960 if (pass == 1) 10961 as_warn_where (l->fixp->fx_file, l->fixp->fx_line, 10962 _("Unmatched %%hi reloc")); 10963#endif 10964 } 10965 } 10966} 10967 10968/* When generating embedded PIC code we need to use a special 10969 relocation to represent the difference of two symbols in the .text 10970 section (switch tables use a difference of this sort). See 10971 include/coff/mips.h for details. This macro checks whether this 10972 fixup requires the special reloc. */ 10973#define SWITCH_TABLE(fixp) \ 10974 ((fixp)->fx_r_type == BFD_RELOC_32 \ 10975 && OUTPUT_FLAVOR != bfd_target_elf_flavour \ 10976 && (fixp)->fx_addsy != NULL \ 10977 && (fixp)->fx_subsy != NULL \ 10978 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ 10979 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) 10980 10981/* When generating embedded PIC code we must keep all PC relative 10982 relocations, in case the linker has to relax a call. We also need 10983 to keep relocations for switch table entries. 10984 10985 We may have combined relocations without symbols in the N32/N64 ABI. 10986 We have to prevent gas from dropping them. */ 10987 10988int 10989mips_force_relocation (fixS *fixp) 10990{ 10991 if (generic_force_reloc (fixp)) 10992 return 1; 10993 10994 if (HAVE_NEWABI 10995 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr 10996 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB 10997 || fixp->fx_r_type == BFD_RELOC_HI16_S 10998 || fixp->fx_r_type == BFD_RELOC_LO16)) 10999 return 1; 11000 11001 return (mips_pic == EMBEDDED_PIC 11002 && (fixp->fx_pcrel 11003 || SWITCH_TABLE (fixp) 11004 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S 11005 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); 11006} 11007 11008/* This hook is called before a fix is simplified. We don't really 11009 decide whether to skip a fix here. Rather, we turn global symbols 11010 used as branch targets into local symbols, such that they undergo 11011 simplification. We can only do this if the symbol is defined and 11012 it is in the same section as the branch. If this doesn't hold, we 11013 emit a better error message than just saying the relocation is not 11014 valid for the selected object format. 11015 11016 FIXP is the fix-up we're going to try to simplify, SEG is the 11017 segment in which the fix up occurs. The return value should be 11018 non-zero to indicate the fix-up is valid for further 11019 simplifications. */ 11020 11021int 11022mips_validate_fix (struct fix *fixP, asection *seg) 11023{ 11024 /* There's a lot of discussion on whether it should be possible to 11025 use R_MIPS_PC16 to represent branch relocations. The outcome 11026 seems to be that it can, but gas/bfd are very broken in creating 11027 RELA relocations for this, so for now we only accept branches to 11028 symbols in the same section. Anything else is of dubious value, 11029 since there's no guarantee that at link time the symbol would be 11030 in range. Even for branches to local symbols this is arguably 11031 wrong, since it we assume the symbol is not going to be 11032 overridden, which should be possible per ELF library semantics, 11033 but then, there isn't a dynamic relocation that could be used to 11034 this effect, and the target would likely be out of range as well. 11035 11036 Unfortunately, it seems that there is too much code out there 11037 that relies on branches to symbols that are global to be resolved 11038 as if they were local, like the IRIX tools do, so we do it as 11039 well, but with a warning so that people are reminded to fix their 11040 code. If we ever get back to using R_MIPS_PC16 for branch 11041 targets, this entire block should go away (and probably the 11042 whole function). */ 11043 11044 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 11045 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour 11046 || OUTPUT_FLAVOR == bfd_target_elf_flavour) 11047 && mips_pic != EMBEDDED_PIC) 11048 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL) 11049 && fixP->fx_addsy) 11050 { 11051 if (! S_IS_DEFINED (fixP->fx_addsy)) 11052 { 11053 as_bad_where (fixP->fx_file, fixP->fx_line, 11054 _("Cannot branch to undefined symbol.")); 11055 /* Avoid any further errors about this fixup. */ 11056 fixP->fx_done = 1; 11057 } 11058 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg) 11059 { 11060 as_bad_where (fixP->fx_file, fixP->fx_line, 11061 _("Cannot branch to symbol in another section.")); 11062 fixP->fx_done = 1; 11063 } 11064 else if (S_IS_EXTERNAL (fixP->fx_addsy)) 11065 { 11066 symbolS *sym = fixP->fx_addsy; 11067 11068 if (mips_pic == SVR4_PIC) 11069 as_warn_where (fixP->fx_file, fixP->fx_line, 11070 _("Pretending global symbol used as branch target is local.")); 11071 11072 fixP->fx_addsy = symbol_create (S_GET_NAME (sym), 11073 S_GET_SEGMENT (sym), 11074 S_GET_VALUE (sym), 11075 symbol_get_frag (sym)); 11076 copy_symbol_attributes (fixP->fx_addsy, sym); 11077 S_CLEAR_EXTERNAL (fixP->fx_addsy); 11078 assert (symbol_resolved_p (sym)); 11079 symbol_mark_resolved (fixP->fx_addsy); 11080 } 11081 } 11082 11083 return 1; 11084} 11085 11086/* Apply a fixup to the object file. */ 11087 11088void 11089md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 11090{ 11091 bfd_byte *buf; 11092 long insn; 11093 static int previous_fx_r_type = 0; 11094 reloc_howto_type *howto; 11095 11096 /* We ignore generic BFD relocations we don't know about. */ 11097 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 11098 if (! howto) 11099 return; 11100 11101 assert (fixP->fx_size == 4 11102 || fixP->fx_r_type == BFD_RELOC_16 11103 || fixP->fx_r_type == BFD_RELOC_64 11104 || fixP->fx_r_type == BFD_RELOC_CTOR 11105 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB 11106 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 11107 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); 11108 11109 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); 11110 11111 /* We are not done if this is a composite relocation to set up gp. */ 11112 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel 11113 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB 11114 || (fixP->fx_r_type == BFD_RELOC_64 11115 && (previous_fx_r_type == BFD_RELOC_GPREL32 11116 || previous_fx_r_type == BFD_RELOC_GPREL16)) 11117 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB 11118 && (fixP->fx_r_type == BFD_RELOC_HI16_S 11119 || fixP->fx_r_type == BFD_RELOC_LO16)))) 11120 fixP->fx_done = 1; 11121 previous_fx_r_type = fixP->fx_r_type; 11122 11123 switch (fixP->fx_r_type) 11124 { 11125 case BFD_RELOC_MIPS_JMP: 11126 case BFD_RELOC_MIPS_SHIFT5: 11127 case BFD_RELOC_MIPS_SHIFT6: 11128 case BFD_RELOC_MIPS_GOT_DISP: 11129 case BFD_RELOC_MIPS_GOT_PAGE: 11130 case BFD_RELOC_MIPS_GOT_OFST: 11131 case BFD_RELOC_MIPS_SUB: 11132 case BFD_RELOC_MIPS_INSERT_A: 11133 case BFD_RELOC_MIPS_INSERT_B: 11134 case BFD_RELOC_MIPS_DELETE: 11135 case BFD_RELOC_MIPS_HIGHEST: 11136 case BFD_RELOC_MIPS_HIGHER: 11137 case BFD_RELOC_MIPS_SCN_DISP: 11138 case BFD_RELOC_MIPS_REL16: 11139 case BFD_RELOC_MIPS_RELGOT: 11140 case BFD_RELOC_MIPS_JALR: 11141 case BFD_RELOC_HI16: 11142 case BFD_RELOC_HI16_S: 11143 case BFD_RELOC_GPREL16: 11144 case BFD_RELOC_MIPS_LITERAL: 11145 case BFD_RELOC_MIPS_CALL16: 11146 case BFD_RELOC_MIPS_GOT16: 11147 case BFD_RELOC_GPREL32: 11148 case BFD_RELOC_MIPS_GOT_HI16: 11149 case BFD_RELOC_MIPS_GOT_LO16: 11150 case BFD_RELOC_MIPS_CALL_HI16: 11151 case BFD_RELOC_MIPS_CALL_LO16: 11152 case BFD_RELOC_MIPS16_GPREL: 11153 if (fixP->fx_pcrel) 11154 as_bad_where (fixP->fx_file, fixP->fx_line, 11155 _("Invalid PC relative reloc")); 11156 /* Nothing needed to do. The value comes from the reloc entry */ 11157 break; 11158 11159 case BFD_RELOC_MIPS16_JMP: 11160 /* We currently always generate a reloc against a symbol, which 11161 means that we don't want an addend even if the symbol is 11162 defined. */ 11163 *valP = 0; 11164 break; 11165 11166 case BFD_RELOC_PCREL_HI16_S: 11167 /* The addend for this is tricky if it is internal, so we just 11168 do everything here rather than in bfd_install_relocation. */ 11169 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) 11170 break; 11171 if (fixP->fx_addsy 11172 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) 11173 { 11174 /* For an external symbol adjust by the address to make it 11175 pcrel_offset. We use the address of the RELLO reloc 11176 which follows this one. */ 11177 *valP += (fixP->fx_next->fx_frag->fr_address 11178 + fixP->fx_next->fx_where); 11179 } 11180 *valP = ((*valP + 0x8000) >> 16) & 0xffff; 11181 if (target_big_endian) 11182 buf += 2; 11183 md_number_to_chars (buf, *valP, 2); 11184 break; 11185 11186 case BFD_RELOC_PCREL_LO16: 11187 /* The addend for this is tricky if it is internal, so we just 11188 do everything here rather than in bfd_install_relocation. */ 11189 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done) 11190 break; 11191 if (fixP->fx_addsy 11192 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) 11193 *valP += fixP->fx_frag->fr_address + fixP->fx_where; 11194 if (target_big_endian) 11195 buf += 2; 11196 md_number_to_chars (buf, *valP, 2); 11197 break; 11198 11199 case BFD_RELOC_64: 11200 /* This is handled like BFD_RELOC_32, but we output a sign 11201 extended value if we are only 32 bits. */ 11202 if (fixP->fx_done 11203 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) 11204 { 11205 if (8 <= sizeof (valueT)) 11206 md_number_to_chars (buf, *valP, 8); 11207 else 11208 { 11209 valueT hiv; 11210 11211 if ((*valP & 0x80000000) != 0) 11212 hiv = 0xffffffff; 11213 else 11214 hiv = 0; 11215 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0), 11216 *valP, 4); 11217 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4), 11218 hiv, 4); 11219 } 11220 } 11221 break; 11222 11223 case BFD_RELOC_RVA: 11224 case BFD_RELOC_32: 11225 /* If we are deleting this reloc entry, we must fill in the 11226 value now. This can happen if we have a .word which is not 11227 resolved when it appears but is later defined. We also need 11228 to fill in the value if this is an embedded PIC switch table 11229 entry. */ 11230 if (fixP->fx_done 11231 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) 11232 md_number_to_chars (buf, *valP, 4); 11233 break; 11234 11235 case BFD_RELOC_16: 11236 /* If we are deleting this reloc entry, we must fill in the 11237 value now. */ 11238 assert (fixP->fx_size == 2); 11239 if (fixP->fx_done) 11240 md_number_to_chars (buf, *valP, 2); 11241 break; 11242 11243 case BFD_RELOC_LO16: 11244 /* When handling an embedded PIC switch statement, we can wind 11245 up deleting a LO16 reloc. See the 'o' case in mips_ip. */ 11246 if (fixP->fx_done) 11247 { 11248 if (*valP + 0x8000 > 0xffff) 11249 as_bad_where (fixP->fx_file, fixP->fx_line, 11250 _("relocation overflow")); 11251 if (target_big_endian) 11252 buf += 2; 11253 md_number_to_chars (buf, *valP, 2); 11254 } 11255 break; 11256 11257 case BFD_RELOC_16_PCREL_S2: 11258 if ((*valP & 0x3) != 0) 11259 as_bad_where (fixP->fx_file, fixP->fx_line, 11260 _("Branch to odd address (%lx)"), (long) *valP); 11261 11262 /* 11263 * We need to save the bits in the instruction since fixup_segment() 11264 * might be deleting the relocation entry (i.e., a branch within 11265 * the current segment). 11266 */ 11267 if (! fixP->fx_done) 11268 break; 11269 11270 /* update old instruction data */ 11271 if (target_big_endian) 11272 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; 11273 else 11274 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; 11275 11276 if (*valP + 0x20000 <= 0x3ffff) 11277 { 11278 insn |= (*valP >> 2) & 0xffff; 11279 md_number_to_chars (buf, insn, 4); 11280 } 11281 else if (mips_pic == NO_PIC 11282 && fixP->fx_done 11283 && fixP->fx_frag->fr_address >= text_section->vma 11284 && (fixP->fx_frag->fr_address 11285 < text_section->vma + text_section->_raw_size) 11286 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ 11287 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ 11288 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ 11289 { 11290 /* The branch offset is too large. If this is an 11291 unconditional branch, and we are not generating PIC code, 11292 we can convert it to an absolute jump instruction. */ 11293 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ 11294 insn = 0x0c000000; /* jal */ 11295 else 11296 insn = 0x08000000; /* j */ 11297 fixP->fx_r_type = BFD_RELOC_MIPS_JMP; 11298 fixP->fx_done = 0; 11299 fixP->fx_addsy = section_symbol (text_section); 11300 *valP += md_pcrel_from (fixP); 11301 md_number_to_chars (buf, insn, 4); 11302 } 11303 else 11304 { 11305 /* If we got here, we have branch-relaxation disabled, 11306 and there's nothing we can do to fix this instruction 11307 without turning it into a longer sequence. */ 11308 as_bad_where (fixP->fx_file, fixP->fx_line, 11309 _("Branch out of range")); 11310 } 11311 break; 11312 11313 case BFD_RELOC_VTABLE_INHERIT: 11314 fixP->fx_done = 0; 11315 if (fixP->fx_addsy 11316 && !S_IS_DEFINED (fixP->fx_addsy) 11317 && !S_IS_WEAK (fixP->fx_addsy)) 11318 S_SET_WEAK (fixP->fx_addsy); 11319 break; 11320 11321 case BFD_RELOC_VTABLE_ENTRY: 11322 fixP->fx_done = 0; 11323 break; 11324 11325 default: 11326 internalError (); 11327 } 11328 11329 /* Remember value for tc_gen_reloc. */ 11330 fixP->fx_addnumber = *valP; 11331} 11332 11333#if 0 11334void 11335printInsn (unsigned long oc) 11336{ 11337 const struct mips_opcode *p; 11338 int treg, sreg, dreg, shamt; 11339 short imm; 11340 const char *args; 11341 int i; 11342 11343 for (i = 0; i < NUMOPCODES; ++i) 11344 { 11345 p = &mips_opcodes[i]; 11346 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) 11347 { 11348 printf ("%08lx %s\t", oc, p->name); 11349 treg = (oc >> 16) & 0x1f; 11350 sreg = (oc >> 21) & 0x1f; 11351 dreg = (oc >> 11) & 0x1f; 11352 shamt = (oc >> 6) & 0x1f; 11353 imm = oc; 11354 for (args = p->args;; ++args) 11355 { 11356 switch (*args) 11357 { 11358 case '\0': 11359 printf ("\n"); 11360 break; 11361 11362 case ',': 11363 case '(': 11364 case ')': 11365 printf ("%c", *args); 11366 continue; 11367 11368 case 'r': 11369 assert (treg == sreg); 11370 printf ("$%d,$%d", treg, sreg); 11371 continue; 11372 11373 case 'd': 11374 case 'G': 11375 printf ("$%d", dreg); 11376 continue; 11377 11378 case 't': 11379 case 'E': 11380 printf ("$%d", treg); 11381 continue; 11382 11383 case 'k': 11384 printf ("0x%x", treg); 11385 continue; 11386 11387 case 'b': 11388 case 's': 11389 printf ("$%d", sreg); 11390 continue; 11391 11392 case 'a': 11393 printf ("0x%08lx", oc & 0x1ffffff); 11394 continue; 11395 11396 case 'i': 11397 case 'j': 11398 case 'o': 11399 case 'u': 11400 printf ("%d", imm); 11401 continue; 11402 11403 case '<': 11404 case '>': 11405 printf ("$%d", shamt); 11406 continue; 11407 11408 default: 11409 internalError (); 11410 } 11411 break; 11412 } 11413 return; 11414 } 11415 } 11416 printf (_("%08lx UNDEFINED\n"), oc); 11417} 11418#endif 11419 11420static symbolS * 11421get_symbol (void) 11422{ 11423 int c; 11424 char *name; 11425 symbolS *p; 11426 11427 name = input_line_pointer; 11428 c = get_symbol_end (); 11429 p = (symbolS *) symbol_find_or_make (name); 11430 *input_line_pointer = c; 11431 return p; 11432} 11433 11434/* Align the current frag to a given power of two. The MIPS assembler 11435 also automatically adjusts any preceding label. */ 11436 11437static void 11438mips_align (int to, int fill, symbolS *label) 11439{ 11440 mips_emit_delays (FALSE); 11441 frag_align (to, fill, 0); 11442 record_alignment (now_seg, to); 11443 if (label != NULL) 11444 { 11445 assert (S_GET_SEGMENT (label) == now_seg); 11446 symbol_set_frag (label, frag_now); 11447 S_SET_VALUE (label, (valueT) frag_now_fix ()); 11448 } 11449} 11450 11451/* Align to a given power of two. .align 0 turns off the automatic 11452 alignment used by the data creating pseudo-ops. */ 11453 11454static void 11455s_align (int x ATTRIBUTE_UNUSED) 11456{ 11457 register int temp; 11458 register long temp_fill; 11459 long max_alignment = 15; 11460 11461 /* 11462 11463 o Note that the assembler pulls down any immediately preceding label 11464 to the aligned address. 11465 o It's not documented but auto alignment is reinstated by 11466 a .align pseudo instruction. 11467 o Note also that after auto alignment is turned off the mips assembler 11468 issues an error on attempt to assemble an improperly aligned data item. 11469 We don't. 11470 11471 */ 11472 11473 temp = get_absolute_expression (); 11474 if (temp > max_alignment) 11475 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); 11476 else if (temp < 0) 11477 { 11478 as_warn (_("Alignment negative: 0 assumed.")); 11479 temp = 0; 11480 } 11481 if (*input_line_pointer == ',') 11482 { 11483 ++input_line_pointer; 11484 temp_fill = get_absolute_expression (); 11485 } 11486 else 11487 temp_fill = 0; 11488 if (temp) 11489 { 11490 auto_align = 1; 11491 mips_align (temp, (int) temp_fill, 11492 insn_labels != NULL ? insn_labels->label : NULL); 11493 } 11494 else 11495 { 11496 auto_align = 0; 11497 } 11498 11499 demand_empty_rest_of_line (); 11500} 11501 11502void 11503mips_flush_pending_output (void) 11504{ 11505 mips_emit_delays (FALSE); 11506 mips_clear_insn_labels (); 11507} 11508 11509static void 11510s_change_sec (int sec) 11511{ 11512 segT seg; 11513 11514 /* When generating embedded PIC code, we only use the .text, .lit8, 11515 .sdata and .sbss sections. We change the .data and .rdata 11516 pseudo-ops to use .sdata. */ 11517 if (mips_pic == EMBEDDED_PIC 11518 && (sec == 'd' || sec == 'r')) 11519 sec = 's'; 11520 11521#ifdef OBJ_ELF 11522 /* The ELF backend needs to know that we are changing sections, so 11523 that .previous works correctly. We could do something like check 11524 for an obj_section_change_hook macro, but that might be confusing 11525 as it would not be appropriate to use it in the section changing 11526 functions in read.c, since obj-elf.c intercepts those. FIXME: 11527 This should be cleaner, somehow. */ 11528 obj_elf_section_change_hook (); 11529#endif 11530 11531 mips_emit_delays (FALSE); 11532 switch (sec) 11533 { 11534 case 't': 11535 s_text (0); 11536 break; 11537 case 'd': 11538 s_data (0); 11539 break; 11540 case 'b': 11541 subseg_set (bss_section, (subsegT) get_absolute_expression ()); 11542 demand_empty_rest_of_line (); 11543 break; 11544 11545 case 'r': 11546 if (USE_GLOBAL_POINTER_OPT) 11547 { 11548 seg = subseg_new (RDATA_SECTION_NAME, 11549 (subsegT) get_absolute_expression ()); 11550 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 11551 { 11552 bfd_set_section_flags (stdoutput, seg, 11553 (SEC_ALLOC 11554 | SEC_LOAD 11555 | SEC_READONLY 11556 | SEC_RELOC 11557 | SEC_DATA)); 11558 if (strcmp (TARGET_OS, "elf") != 0) 11559 record_alignment (seg, 4); 11560 } 11561 demand_empty_rest_of_line (); 11562 } 11563 else 11564 { 11565 as_bad (_("No read only data section in this object file format")); 11566 demand_empty_rest_of_line (); 11567 return; 11568 } 11569 break; 11570 11571 case 's': 11572 if (USE_GLOBAL_POINTER_OPT) 11573 { 11574 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); 11575 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 11576 { 11577 bfd_set_section_flags (stdoutput, seg, 11578 SEC_ALLOC | SEC_LOAD | SEC_RELOC 11579 | SEC_DATA); 11580 if (strcmp (TARGET_OS, "elf") != 0) 11581 record_alignment (seg, 4); 11582 } 11583 demand_empty_rest_of_line (); 11584 break; 11585 } 11586 else 11587 { 11588 as_bad (_("Global pointers not supported; recompile -G 0")); 11589 demand_empty_rest_of_line (); 11590 return; 11591 } 11592 } 11593 11594 auto_align = 1; 11595} 11596 11597void 11598s_change_section (int ignore ATTRIBUTE_UNUSED) 11599{ 11600#ifdef OBJ_ELF 11601 char *section_name; 11602 char c; 11603 char next_c = 0; 11604 int section_type; 11605 int section_flag; 11606 int section_entry_size; 11607 int section_alignment; 11608 11609 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 11610 return; 11611 11612 section_name = input_line_pointer; 11613 c = get_symbol_end (); 11614 if (c) 11615 next_c = *(input_line_pointer + 1); 11616 11617 /* Do we have .section Name<,"flags">? */ 11618 if (c != ',' || (c == ',' && next_c == '"')) 11619 { 11620 /* just after name is now '\0'. */ 11621 *input_line_pointer = c; 11622 input_line_pointer = section_name; 11623 obj_elf_section (ignore); 11624 return; 11625 } 11626 input_line_pointer++; 11627 11628 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ 11629 if (c == ',') 11630 section_type = get_absolute_expression (); 11631 else 11632 section_type = 0; 11633 if (*input_line_pointer++ == ',') 11634 section_flag = get_absolute_expression (); 11635 else 11636 section_flag = 0; 11637 if (*input_line_pointer++ == ',') 11638 section_entry_size = get_absolute_expression (); 11639 else 11640 section_entry_size = 0; 11641 if (*input_line_pointer++ == ',') 11642 section_alignment = get_absolute_expression (); 11643 else 11644 section_alignment = 0; 11645 11646 section_name = xstrdup (section_name); 11647 11648 /* When using the generic form of .section (as implemented by obj-elf.c), 11649 there's no way to set the section type to SHT_MIPS_DWARF. Users have 11650 traditionally had to fall back on the more common @progbits instead. 11651 11652 There's nothing really harmful in this, since bfd will correct 11653 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it 11654 means that, for backwards compatibiltiy, the special_section entries 11655 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. 11656 11657 Even so, we shouldn't force users of the MIPS .section syntax to 11658 incorrectly label the sections as SHT_PROGBITS. The best compromise 11659 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the 11660 generic type-checking code. */ 11661 if (section_type == SHT_MIPS_DWARF) 11662 section_type = SHT_PROGBITS; 11663 11664 obj_elf_change_section (section_name, section_type, section_flag, 11665 section_entry_size, 0, 0, 0); 11666 11667 if (now_seg->name != section_name) 11668 free (section_name); 11669#endif /* OBJ_ELF */ 11670} 11671 11672void 11673mips_enable_auto_align (void) 11674{ 11675 auto_align = 1; 11676} 11677 11678static void 11679s_cons (int log_size) 11680{ 11681 symbolS *label; 11682 11683 label = insn_labels != NULL ? insn_labels->label : NULL; 11684 mips_emit_delays (FALSE); 11685 if (log_size > 0 && auto_align) 11686 mips_align (log_size, 0, label); 11687 mips_clear_insn_labels (); 11688 cons (1 << log_size); 11689} 11690 11691static void 11692s_float_cons (int type) 11693{ 11694 symbolS *label; 11695 11696 label = insn_labels != NULL ? insn_labels->label : NULL; 11697 11698 mips_emit_delays (FALSE); 11699 11700 if (auto_align) 11701 { 11702 if (type == 'd') 11703 mips_align (3, 0, label); 11704 else 11705 mips_align (2, 0, label); 11706 } 11707 11708 mips_clear_insn_labels (); 11709 11710 float_cons (type); 11711} 11712 11713/* Handle .globl. We need to override it because on Irix 5 you are 11714 permitted to say 11715 .globl foo .text 11716 where foo is an undefined symbol, to mean that foo should be 11717 considered to be the address of a function. */ 11718 11719static void 11720s_mips_globl (int x ATTRIBUTE_UNUSED) 11721{ 11722 char *name; 11723 int c; 11724 symbolS *symbolP; 11725 flagword flag; 11726 11727 name = input_line_pointer; 11728 c = get_symbol_end (); 11729 symbolP = symbol_find_or_make (name); 11730 *input_line_pointer = c; 11731 SKIP_WHITESPACE (); 11732 11733 /* On Irix 5, every global symbol that is not explicitly labelled as 11734 being a function is apparently labelled as being an object. */ 11735 flag = BSF_OBJECT; 11736 11737 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 11738 { 11739 char *secname; 11740 asection *sec; 11741 11742 secname = input_line_pointer; 11743 c = get_symbol_end (); 11744 sec = bfd_get_section_by_name (stdoutput, secname); 11745 if (sec == NULL) 11746 as_bad (_("%s: no such section"), secname); 11747 *input_line_pointer = c; 11748 11749 if (sec != NULL && (sec->flags & SEC_CODE) != 0) 11750 flag = BSF_FUNCTION; 11751 } 11752 11753 symbol_get_bfdsym (symbolP)->flags |= flag; 11754 11755 S_SET_EXTERNAL (symbolP); 11756 demand_empty_rest_of_line (); 11757} 11758 11759static void 11760s_option (int x ATTRIBUTE_UNUSED) 11761{ 11762 char *opt; 11763 char c; 11764 11765 opt = input_line_pointer; 11766 c = get_symbol_end (); 11767 11768 if (*opt == 'O') 11769 { 11770 /* FIXME: What does this mean? */ 11771 } 11772 else if (strncmp (opt, "pic", 3) == 0) 11773 { 11774 int i; 11775 11776 i = atoi (opt + 3); 11777 if (i == 0) 11778 mips_pic = NO_PIC; 11779 else if (i == 2) 11780 { 11781 mips_pic = SVR4_PIC; 11782 mips_abicalls = TRUE; 11783 } 11784 else 11785 as_bad (_(".option pic%d not supported"), i); 11786 11787 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) 11788 { 11789 if (g_switch_seen && g_switch_value != 0) 11790 as_warn (_("-G may not be used with SVR4 PIC code")); 11791 g_switch_value = 0; 11792 bfd_set_gp_size (stdoutput, 0); 11793 } 11794 } 11795 else 11796 as_warn (_("Unrecognized option \"%s\""), opt); 11797 11798 *input_line_pointer = c; 11799 demand_empty_rest_of_line (); 11800} 11801 11802/* This structure is used to hold a stack of .set values. */ 11803 11804struct mips_option_stack 11805{ 11806 struct mips_option_stack *next; 11807 struct mips_set_options options; 11808}; 11809 11810static struct mips_option_stack *mips_opts_stack; 11811 11812/* Handle the .set pseudo-op. */ 11813 11814static void 11815s_mipsset (int x ATTRIBUTE_UNUSED) 11816{ 11817 char *name = input_line_pointer, ch; 11818 11819 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 11820 ++input_line_pointer; 11821 ch = *input_line_pointer; 11822 *input_line_pointer = '\0'; 11823 11824 if (strcmp (name, "reorder") == 0) 11825 { 11826 if (mips_opts.noreorder && prev_nop_frag != NULL) 11827 { 11828 /* If we still have pending nops, we can discard them. The 11829 usual nop handling will insert any that are still 11830 needed. */ 11831 prev_nop_frag->fr_fix -= (prev_nop_frag_holds 11832 * (mips_opts.mips16 ? 2 : 4)); 11833 prev_nop_frag = NULL; 11834 } 11835 mips_opts.noreorder = 0; 11836 } 11837 else if (strcmp (name, "noreorder") == 0) 11838 { 11839 mips_emit_delays (TRUE); 11840 mips_opts.noreorder = 1; 11841 mips_any_noreorder = 1; 11842 } 11843 else if (strcmp (name, "at") == 0) 11844 { 11845 mips_opts.noat = 0; 11846 } 11847 else if (strcmp (name, "noat") == 0) 11848 { 11849 mips_opts.noat = 1; 11850 } 11851 else if (strcmp (name, "macro") == 0) 11852 { 11853 mips_opts.warn_about_macros = 0; 11854 } 11855 else if (strcmp (name, "nomacro") == 0) 11856 { 11857 if (mips_opts.noreorder == 0) 11858 as_bad (_("`noreorder' must be set before `nomacro'")); 11859 mips_opts.warn_about_macros = 1; 11860 } 11861 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) 11862 { 11863 mips_opts.nomove = 0; 11864 } 11865 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) 11866 { 11867 mips_opts.nomove = 1; 11868 } 11869 else if (strcmp (name, "bopt") == 0) 11870 { 11871 mips_opts.nobopt = 0; 11872 } 11873 else if (strcmp (name, "nobopt") == 0) 11874 { 11875 mips_opts.nobopt = 1; 11876 } 11877 else if (strcmp (name, "mips16") == 0 11878 || strcmp (name, "MIPS-16") == 0) 11879 mips_opts.mips16 = 1; 11880 else if (strcmp (name, "nomips16") == 0 11881 || strcmp (name, "noMIPS-16") == 0) 11882 mips_opts.mips16 = 0; 11883 else if (strcmp (name, "mips3d") == 0) 11884 mips_opts.ase_mips3d = 1; 11885 else if (strcmp (name, "nomips3d") == 0) 11886 mips_opts.ase_mips3d = 0; 11887 else if (strcmp (name, "mdmx") == 0) 11888 mips_opts.ase_mdmx = 1; 11889 else if (strcmp (name, "nomdmx") == 0) 11890 mips_opts.ase_mdmx = 0; 11891 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) 11892 { 11893 int reset = 0; 11894 11895 /* Permit the user to change the ISA and architecture on the fly. 11896 Needless to say, misuse can cause serious problems. */ 11897 if (strcmp (name, "mips0") == 0) 11898 { 11899 reset = 1; 11900 mips_opts.isa = file_mips_isa; 11901 } 11902 else if (strcmp (name, "mips1") == 0) 11903 mips_opts.isa = ISA_MIPS1; 11904 else if (strcmp (name, "mips2") == 0) 11905 mips_opts.isa = ISA_MIPS2; 11906 else if (strcmp (name, "mips3") == 0) 11907 mips_opts.isa = ISA_MIPS3; 11908 else if (strcmp (name, "mips4") == 0) 11909 mips_opts.isa = ISA_MIPS4; 11910 else if (strcmp (name, "mips5") == 0) 11911 mips_opts.isa = ISA_MIPS5; 11912 else if (strcmp (name, "mips32") == 0) 11913 mips_opts.isa = ISA_MIPS32; 11914 else if (strcmp (name, "mips32r2") == 0) 11915 mips_opts.isa = ISA_MIPS32R2; 11916 else if (strcmp (name, "mips64") == 0) 11917 mips_opts.isa = ISA_MIPS64; 11918 else if (strcmp (name, "mips64r2") == 0) 11919 mips_opts.isa = ISA_MIPS64R2; 11920 else if (strcmp (name, "arch=default") == 0) 11921 { 11922 reset = 1; 11923 mips_opts.arch = file_mips_arch; 11924 mips_opts.isa = file_mips_isa; 11925 } 11926 else if (strncmp (name, "arch=", 5) == 0) 11927 { 11928 const struct mips_cpu_info *p; 11929 11930 p = mips_parse_cpu("internal use", name + 5); 11931 if (!p) 11932 as_bad (_("unknown architecture %s"), name + 5); 11933 else 11934 { 11935 mips_opts.arch = p->cpu; 11936 mips_opts.isa = p->isa; 11937 } 11938 } 11939 else 11940 as_bad (_("unknown ISA level %s"), name + 4); 11941 11942 switch (mips_opts.isa) 11943 { 11944 case 0: 11945 break; 11946 case ISA_MIPS1: 11947 case ISA_MIPS2: 11948 case ISA_MIPS32: 11949 case ISA_MIPS32R2: 11950 mips_opts.gp32 = 1; 11951 mips_opts.fp32 = 1; 11952 break; 11953 case ISA_MIPS3: 11954 case ISA_MIPS4: 11955 case ISA_MIPS5: 11956 case ISA_MIPS64: 11957 case ISA_MIPS64R2: 11958 mips_opts.gp32 = 0; 11959 mips_opts.fp32 = 0; 11960 break; 11961 default: 11962 as_bad (_("unknown ISA level %s"), name + 4); 11963 break; 11964 } 11965 if (reset) 11966 { 11967 mips_opts.gp32 = file_mips_gp32; 11968 mips_opts.fp32 = file_mips_fp32; 11969 } 11970 } 11971 else if (strcmp (name, "autoextend") == 0) 11972 mips_opts.noautoextend = 0; 11973 else if (strcmp (name, "noautoextend") == 0) 11974 mips_opts.noautoextend = 1; 11975 else if (strcmp (name, "push") == 0) 11976 { 11977 struct mips_option_stack *s; 11978 11979 s = (struct mips_option_stack *) xmalloc (sizeof *s); 11980 s->next = mips_opts_stack; 11981 s->options = mips_opts; 11982 mips_opts_stack = s; 11983 } 11984 else if (strcmp (name, "pop") == 0) 11985 { 11986 struct mips_option_stack *s; 11987 11988 s = mips_opts_stack; 11989 if (s == NULL) 11990 as_bad (_(".set pop with no .set push")); 11991 else 11992 { 11993 /* If we're changing the reorder mode we need to handle 11994 delay slots correctly. */ 11995 if (s->options.noreorder && ! mips_opts.noreorder) 11996 mips_emit_delays (TRUE); 11997 else if (! s->options.noreorder && mips_opts.noreorder) 11998 { 11999 if (prev_nop_frag != NULL) 12000 { 12001 prev_nop_frag->fr_fix -= (prev_nop_frag_holds 12002 * (mips_opts.mips16 ? 2 : 4)); 12003 prev_nop_frag = NULL; 12004 } 12005 } 12006 12007 mips_opts = s->options; 12008 mips_opts_stack = s->next; 12009 free (s); 12010 } 12011 } 12012 else 12013 { 12014 as_warn (_("Tried to set unrecognized symbol: %s\n"), name); 12015 } 12016 *input_line_pointer = ch; 12017 demand_empty_rest_of_line (); 12018} 12019 12020/* Handle the .abicalls pseudo-op. I believe this is equivalent to 12021 .option pic2. It means to generate SVR4 PIC calls. */ 12022 12023static void 12024s_abicalls (int ignore ATTRIBUTE_UNUSED) 12025{ 12026 mips_pic = SVR4_PIC; 12027 mips_abicalls = TRUE; 12028 if (USE_GLOBAL_POINTER_OPT) 12029 { 12030 if (g_switch_seen && g_switch_value != 0) 12031 as_warn (_("-G may not be used with SVR4 PIC code")); 12032 g_switch_value = 0; 12033 } 12034 bfd_set_gp_size (stdoutput, 0); 12035 demand_empty_rest_of_line (); 12036} 12037 12038/* Handle the .cpload pseudo-op. This is used when generating SVR4 12039 PIC code. It sets the $gp register for the function based on the 12040 function address, which is in the register named in the argument. 12041 This uses a relocation against _gp_disp, which is handled specially 12042 by the linker. The result is: 12043 lui $gp,%hi(_gp_disp) 12044 addiu $gp,$gp,%lo(_gp_disp) 12045 addu $gp,$gp,.cpload argument 12046 The .cpload argument is normally $25 == $t9. */ 12047 12048static void 12049s_cpload (int ignore ATTRIBUTE_UNUSED) 12050{ 12051 expressionS ex; 12052 12053 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 12054 .cpload is ignored. */ 12055 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 12056 { 12057 s_ignore (0); 12058 return; 12059 } 12060 12061 /* .cpload should be in a .set noreorder section. */ 12062 if (mips_opts.noreorder == 0) 12063 as_warn (_(".cpload not in noreorder section")); 12064 12065 ex.X_op = O_symbol; 12066 ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); 12067 ex.X_op_symbol = NULL; 12068 ex.X_add_number = 0; 12069 12070 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ 12071 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; 12072 12073 macro_start (); 12074 macro_build_lui (&ex, mips_gp_register); 12075 macro_build (&ex, "addiu", "t,r,j", mips_gp_register, 12076 mips_gp_register, BFD_RELOC_LO16); 12077 macro_build (NULL, "addu", "d,v,t", mips_gp_register, 12078 mips_gp_register, tc_get_register (0)); 12079 macro_end (); 12080 12081 demand_empty_rest_of_line (); 12082} 12083 12084/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: 12085 .cpsetup $reg1, offset|$reg2, label 12086 12087 If offset is given, this results in: 12088 sd $gp, offset($sp) 12089 lui $gp, %hi(%neg(%gp_rel(label))) 12090 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 12091 daddu $gp, $gp, $reg1 12092 12093 If $reg2 is given, this results in: 12094 daddu $reg2, $gp, $0 12095 lui $gp, %hi(%neg(%gp_rel(label))) 12096 addiu $gp, $gp, %lo(%neg(%gp_rel(label))) 12097 daddu $gp, $gp, $reg1 12098 $reg1 is normally $25 == $t9. */ 12099static void 12100s_cpsetup (int ignore ATTRIBUTE_UNUSED) 12101{ 12102 expressionS ex_off; 12103 expressionS ex_sym; 12104 int reg1; 12105 char *f; 12106 12107 /* If we are not generating SVR4 PIC code, .cpsetup is ignored. 12108 We also need NewABI support. */ 12109 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 12110 { 12111 s_ignore (0); 12112 return; 12113 } 12114 12115 reg1 = tc_get_register (0); 12116 SKIP_WHITESPACE (); 12117 if (*input_line_pointer != ',') 12118 { 12119 as_bad (_("missing argument separator ',' for .cpsetup")); 12120 return; 12121 } 12122 else 12123 ++input_line_pointer; 12124 SKIP_WHITESPACE (); 12125 if (*input_line_pointer == '$') 12126 { 12127 mips_cpreturn_register = tc_get_register (0); 12128 mips_cpreturn_offset = -1; 12129 } 12130 else 12131 { 12132 mips_cpreturn_offset = get_absolute_expression (); 12133 mips_cpreturn_register = -1; 12134 } 12135 SKIP_WHITESPACE (); 12136 if (*input_line_pointer != ',') 12137 { 12138 as_bad (_("missing argument separator ',' for .cpsetup")); 12139 return; 12140 } 12141 else 12142 ++input_line_pointer; 12143 SKIP_WHITESPACE (); 12144 expression (&ex_sym); 12145 12146 macro_start (); 12147 if (mips_cpreturn_register == -1) 12148 { 12149 ex_off.X_op = O_constant; 12150 ex_off.X_add_symbol = NULL; 12151 ex_off.X_op_symbol = NULL; 12152 ex_off.X_add_number = mips_cpreturn_offset; 12153 12154 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, 12155 BFD_RELOC_LO16, SP); 12156 } 12157 else 12158 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register, 12159 mips_gp_register, 0); 12160 12161 /* Ensure there's room for the next two instructions, so that `f' 12162 doesn't end up with an address in the wrong frag. */ 12163 frag_grow (8); 12164 f = frag_more (0); 12165 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16); 12166 fix_new (frag_now, f - frag_now->fr_literal, 12167 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); 12168 fix_new (frag_now, f - frag_now->fr_literal, 12169 4, NULL, 0, 0, BFD_RELOC_HI16_S); 12170 12171 f = frag_more (0); 12172 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, 12173 mips_gp_register, BFD_RELOC_GPREL16); 12174 fix_new (frag_now, f - frag_now->fr_literal, 12175 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB); 12176 fix_new (frag_now, f - frag_now->fr_literal, 12177 4, NULL, 0, 0, BFD_RELOC_LO16); 12178 12179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, 12180 mips_gp_register, reg1); 12181 macro_end (); 12182 12183 demand_empty_rest_of_line (); 12184} 12185 12186static void 12187s_cplocal (int ignore ATTRIBUTE_UNUSED) 12188{ 12189 /* If we are not generating SVR4 PIC code, or if this is not NewABI code, 12190 .cplocal is ignored. */ 12191 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 12192 { 12193 s_ignore (0); 12194 return; 12195 } 12196 12197 mips_gp_register = tc_get_register (0); 12198 demand_empty_rest_of_line (); 12199} 12200 12201/* Handle the .cprestore pseudo-op. This stores $gp into a given 12202 offset from $sp. The offset is remembered, and after making a PIC 12203 call $gp is restored from that location. */ 12204 12205static void 12206s_cprestore (int ignore ATTRIBUTE_UNUSED) 12207{ 12208 expressionS ex; 12209 12210 /* If we are not generating SVR4 PIC code, or if this is NewABI code, 12211 .cprestore is ignored. */ 12212 if (mips_pic != SVR4_PIC || HAVE_NEWABI) 12213 { 12214 s_ignore (0); 12215 return; 12216 } 12217 12218 mips_cprestore_offset = get_absolute_expression (); 12219 mips_cprestore_valid = 1; 12220 12221 ex.X_op = O_constant; 12222 ex.X_add_symbol = NULL; 12223 ex.X_op_symbol = NULL; 12224 ex.X_add_number = mips_cprestore_offset; 12225 12226 macro_start (); 12227 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, 12228 SP, HAVE_64BIT_ADDRESSES); 12229 macro_end (); 12230 12231 demand_empty_rest_of_line (); 12232} 12233 12234/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset 12235 was given in the preceding .cpsetup, it results in: 12236 ld $gp, offset($sp) 12237 12238 If a register $reg2 was given there, it results in: 12239 daddu $gp, $reg2, $0 12240 */ 12241static void 12242s_cpreturn (int ignore ATTRIBUTE_UNUSED) 12243{ 12244 expressionS ex; 12245 12246 /* If we are not generating SVR4 PIC code, .cpreturn is ignored. 12247 We also need NewABI support. */ 12248 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 12249 { 12250 s_ignore (0); 12251 return; 12252 } 12253 12254 macro_start (); 12255 if (mips_cpreturn_register == -1) 12256 { 12257 ex.X_op = O_constant; 12258 ex.X_add_symbol = NULL; 12259 ex.X_op_symbol = NULL; 12260 ex.X_add_number = mips_cpreturn_offset; 12261 12262 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); 12263 } 12264 else 12265 macro_build (NULL, "daddu", "d,v,t", mips_gp_register, 12266 mips_cpreturn_register, 0); 12267 macro_end (); 12268 12269 demand_empty_rest_of_line (); 12270} 12271 12272/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC 12273 code. It sets the offset to use in gp_rel relocations. */ 12274 12275static void 12276s_gpvalue (int ignore ATTRIBUTE_UNUSED) 12277{ 12278 /* If we are not generating SVR4 PIC code, .gpvalue is ignored. 12279 We also need NewABI support. */ 12280 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) 12281 { 12282 s_ignore (0); 12283 return; 12284 } 12285 12286 mips_gprel_offset = get_absolute_expression (); 12287 12288 demand_empty_rest_of_line (); 12289} 12290 12291/* Handle the .gpword pseudo-op. This is used when generating PIC 12292 code. It generates a 32 bit GP relative reloc. */ 12293 12294static void 12295s_gpword (int ignore ATTRIBUTE_UNUSED) 12296{ 12297 symbolS *label; 12298 expressionS ex; 12299 char *p; 12300 12301 /* When not generating PIC code, this is treated as .word. */ 12302 if (mips_pic != SVR4_PIC) 12303 { 12304 s_cons (2); 12305 return; 12306 } 12307 12308 label = insn_labels != NULL ? insn_labels->label : NULL; 12309 mips_emit_delays (TRUE); 12310 if (auto_align) 12311 mips_align (2, 0, label); 12312 mips_clear_insn_labels (); 12313 12314 expression (&ex); 12315 12316 if (ex.X_op != O_symbol || ex.X_add_number != 0) 12317 { 12318 as_bad (_("Unsupported use of .gpword")); 12319 ignore_rest_of_line (); 12320 } 12321 12322 p = frag_more (4); 12323 md_number_to_chars (p, 0, 4); 12324 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 12325 BFD_RELOC_GPREL32); 12326 12327 demand_empty_rest_of_line (); 12328} 12329 12330static void 12331s_gpdword (int ignore ATTRIBUTE_UNUSED) 12332{ 12333 symbolS *label; 12334 expressionS ex; 12335 char *p; 12336 12337 /* When not generating PIC code, this is treated as .dword. */ 12338 if (mips_pic != SVR4_PIC) 12339 { 12340 s_cons (3); 12341 return; 12342 } 12343 12344 label = insn_labels != NULL ? insn_labels->label : NULL; 12345 mips_emit_delays (TRUE); 12346 if (auto_align) 12347 mips_align (3, 0, label); 12348 mips_clear_insn_labels (); 12349 12350 expression (&ex); 12351 12352 if (ex.X_op != O_symbol || ex.X_add_number != 0) 12353 { 12354 as_bad (_("Unsupported use of .gpdword")); 12355 ignore_rest_of_line (); 12356 } 12357 12358 p = frag_more (8); 12359 md_number_to_chars (p, 0, 8); 12360 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, 12361 BFD_RELOC_GPREL32); 12362 12363 /* GPREL32 composed with 64 gives a 64-bit GP offset. */ 12364 ex.X_op = O_absent; 12365 ex.X_add_symbol = 0; 12366 ex.X_add_number = 0; 12367 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE, 12368 BFD_RELOC_64); 12369 12370 demand_empty_rest_of_line (); 12371} 12372 12373/* Handle the .cpadd pseudo-op. This is used when dealing with switch 12374 tables in SVR4 PIC code. */ 12375 12376static void 12377s_cpadd (int ignore ATTRIBUTE_UNUSED) 12378{ 12379 int reg; 12380 12381 /* This is ignored when not generating SVR4 PIC code. */ 12382 if (mips_pic != SVR4_PIC) 12383 { 12384 s_ignore (0); 12385 return; 12386 } 12387 12388 /* Add $gp to the register named as an argument. */ 12389 macro_start (); 12390 reg = tc_get_register (0); 12391 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); 12392 macro_end (); 12393 12394 demand_empty_rest_of_line (); 12395} 12396 12397/* Handle the .insn pseudo-op. This marks instruction labels in 12398 mips16 mode. This permits the linker to handle them specially, 12399 such as generating jalx instructions when needed. We also make 12400 them odd for the duration of the assembly, in order to generate the 12401 right sort of code. We will make them even in the adjust_symtab 12402 routine, while leaving them marked. This is convenient for the 12403 debugger and the disassembler. The linker knows to make them odd 12404 again. */ 12405 12406static void 12407s_insn (int ignore ATTRIBUTE_UNUSED) 12408{ 12409 mips16_mark_labels (); 12410 12411 demand_empty_rest_of_line (); 12412} 12413 12414/* Handle a .stabn directive. We need these in order to mark a label 12415 as being a mips16 text label correctly. Sometimes the compiler 12416 will emit a label, followed by a .stabn, and then switch sections. 12417 If the label and .stabn are in mips16 mode, then the label is 12418 really a mips16 text label. */ 12419 12420static void 12421s_mips_stab (int type) 12422{ 12423 if (type == 'n') 12424 mips16_mark_labels (); 12425 12426 s_stab (type); 12427} 12428 12429/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. 12430 */ 12431 12432static void 12433s_mips_weakext (int ignore ATTRIBUTE_UNUSED) 12434{ 12435 char *name; 12436 int c; 12437 symbolS *symbolP; 12438 expressionS exp; 12439 12440 name = input_line_pointer; 12441 c = get_symbol_end (); 12442 symbolP = symbol_find_or_make (name); 12443 S_SET_WEAK (symbolP); 12444 *input_line_pointer = c; 12445 12446 SKIP_WHITESPACE (); 12447 12448 if (! is_end_of_line[(unsigned char) *input_line_pointer]) 12449 { 12450 if (S_IS_DEFINED (symbolP)) 12451 { 12452 as_bad ("ignoring attempt to redefine symbol %s", 12453 S_GET_NAME (symbolP)); 12454 ignore_rest_of_line (); 12455 return; 12456 } 12457 12458 if (*input_line_pointer == ',') 12459 { 12460 ++input_line_pointer; 12461 SKIP_WHITESPACE (); 12462 } 12463 12464 expression (&exp); 12465 if (exp.X_op != O_symbol) 12466 { 12467 as_bad ("bad .weakext directive"); 12468 ignore_rest_of_line (); 12469 return; 12470 } 12471 symbol_set_value_expression (symbolP, &exp); 12472 } 12473 12474 demand_empty_rest_of_line (); 12475} 12476 12477/* Parse a register string into a number. Called from the ECOFF code 12478 to parse .frame. The argument is non-zero if this is the frame 12479 register, so that we can record it in mips_frame_reg. */ 12480 12481int 12482tc_get_register (int frame) 12483{ 12484 int reg; 12485 12486 SKIP_WHITESPACE (); 12487 if (*input_line_pointer++ != '$') 12488 { 12489 as_warn (_("expected `$'")); 12490 reg = ZERO; 12491 } 12492 else if (ISDIGIT (*input_line_pointer)) 12493 { 12494 reg = get_absolute_expression (); 12495 if (reg < 0 || reg >= 32) 12496 { 12497 as_warn (_("Bad register number")); 12498 reg = ZERO; 12499 } 12500 } 12501 else 12502 { 12503 if (strncmp (input_line_pointer, "ra", 2) == 0) 12504 { 12505 reg = RA; 12506 input_line_pointer += 2; 12507 } 12508 else if (strncmp (input_line_pointer, "fp", 2) == 0) 12509 { 12510 reg = FP; 12511 input_line_pointer += 2; 12512 } 12513 else if (strncmp (input_line_pointer, "sp", 2) == 0) 12514 { 12515 reg = SP; 12516 input_line_pointer += 2; 12517 } 12518 else if (strncmp (input_line_pointer, "gp", 2) == 0) 12519 { 12520 reg = GP; 12521 input_line_pointer += 2; 12522 } 12523 else if (strncmp (input_line_pointer, "at", 2) == 0) 12524 { 12525 reg = AT; 12526 input_line_pointer += 2; 12527 } 12528 else if (strncmp (input_line_pointer, "kt0", 3) == 0) 12529 { 12530 reg = KT0; 12531 input_line_pointer += 3; 12532 } 12533 else if (strncmp (input_line_pointer, "kt1", 3) == 0) 12534 { 12535 reg = KT1; 12536 input_line_pointer += 3; 12537 } 12538 else if (strncmp (input_line_pointer, "zero", 4) == 0) 12539 { 12540 reg = ZERO; 12541 input_line_pointer += 4; 12542 } 12543 else 12544 { 12545 as_warn (_("Unrecognized register name")); 12546 reg = ZERO; 12547 while (ISALNUM(*input_line_pointer)) 12548 input_line_pointer++; 12549 } 12550 } 12551 if (frame) 12552 { 12553 mips_frame_reg = reg != 0 ? reg : SP; 12554 mips_frame_reg_valid = 1; 12555 mips_cprestore_valid = 0; 12556 } 12557 return reg; 12558} 12559 12560valueT 12561md_section_align (asection *seg, valueT addr) 12562{ 12563 int align = bfd_get_section_alignment (stdoutput, seg); 12564 12565#ifdef OBJ_ELF 12566 /* We don't need to align ELF sections to the full alignment. 12567 However, Irix 5 may prefer that we align them at least to a 16 12568 byte boundary. We don't bother to align the sections if we are 12569 targeted for an embedded system. */ 12570 if (strcmp (TARGET_OS, "elf") == 0) 12571 return addr; 12572 if (align > 4) 12573 align = 4; 12574#endif 12575 12576 return ((addr + (1 << align) - 1) & (-1 << align)); 12577} 12578 12579/* Utility routine, called from above as well. If called while the 12580 input file is still being read, it's only an approximation. (For 12581 example, a symbol may later become defined which appeared to be 12582 undefined earlier.) */ 12583 12584static int 12585nopic_need_relax (symbolS *sym, int before_relaxing) 12586{ 12587 if (sym == 0) 12588 return 0; 12589 12590 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0) 12591 { 12592 const char *symname; 12593 int change; 12594 12595 /* Find out whether this symbol can be referenced off the $gp 12596 register. It can be if it is smaller than the -G size or if 12597 it is in the .sdata or .sbss section. Certain symbols can 12598 not be referenced off the $gp, although it appears as though 12599 they can. */ 12600 symname = S_GET_NAME (sym); 12601 if (symname != (const char *) NULL 12602 && (strcmp (symname, "eprol") == 0 12603 || strcmp (symname, "etext") == 0 12604 || strcmp (symname, "_gp") == 0 12605 || strcmp (symname, "edata") == 0 12606 || strcmp (symname, "_fbss") == 0 12607 || strcmp (symname, "_fdata") == 0 12608 || strcmp (symname, "_ftext") == 0 12609 || strcmp (symname, "end") == 0 12610 || strcmp (symname, "_gp_disp") == 0)) 12611 change = 1; 12612 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) 12613 && (0 12614#ifndef NO_ECOFF_DEBUGGING 12615 || (symbol_get_obj (sym)->ecoff_extern_size != 0 12616 && (symbol_get_obj (sym)->ecoff_extern_size 12617 <= g_switch_value)) 12618#endif 12619 /* We must defer this decision until after the whole 12620 file has been read, since there might be a .extern 12621 after the first use of this symbol. */ 12622 || (before_relaxing 12623#ifndef NO_ECOFF_DEBUGGING 12624 && symbol_get_obj (sym)->ecoff_extern_size == 0 12625#endif 12626 && S_GET_VALUE (sym) == 0) 12627 || (S_GET_VALUE (sym) != 0 12628 && S_GET_VALUE (sym) <= g_switch_value))) 12629 change = 0; 12630 else 12631 { 12632 const char *segname; 12633 12634 segname = segment_name (S_GET_SEGMENT (sym)); 12635 assert (strcmp (segname, ".lit8") != 0 12636 && strcmp (segname, ".lit4") != 0); 12637 change = (strcmp (segname, ".sdata") != 0 12638 && strcmp (segname, ".sbss") != 0 12639 && strncmp (segname, ".sdata.", 7) != 0 12640 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); 12641 } 12642 return change; 12643 } 12644 else 12645 /* We are not optimizing for the $gp register. */ 12646 return 1; 12647} 12648 12649 12650/* Return true if the given symbol should be considered local for SVR4 PIC. */ 12651 12652static bfd_boolean 12653pic_need_relax (symbolS *sym, asection *segtype) 12654{ 12655 asection *symsec; 12656 bfd_boolean linkonce; 12657 12658 /* Handle the case of a symbol equated to another symbol. */ 12659 while (symbol_equated_reloc_p (sym)) 12660 { 12661 symbolS *n; 12662 12663 /* It's possible to get a loop here in a badly written 12664 program. */ 12665 n = symbol_get_value_expression (sym)->X_add_symbol; 12666 if (n == sym) 12667 break; 12668 sym = n; 12669 } 12670 12671 symsec = S_GET_SEGMENT (sym); 12672 12673 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ 12674 linkonce = FALSE; 12675 if (symsec != segtype && ! S_IS_LOCAL (sym)) 12676 { 12677 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) 12678 != 0) 12679 linkonce = TRUE; 12680 12681 /* The GNU toolchain uses an extension for ELF: a section 12682 beginning with the magic string .gnu.linkonce is a linkonce 12683 section. */ 12684 if (strncmp (segment_name (symsec), ".gnu.linkonce", 12685 sizeof ".gnu.linkonce" - 1) == 0) 12686 linkonce = TRUE; 12687 } 12688 12689 /* This must duplicate the test in adjust_reloc_syms. */ 12690 return (symsec != &bfd_und_section 12691 && symsec != &bfd_abs_section 12692 && ! bfd_is_com_section (symsec) 12693 && !linkonce 12694#ifdef OBJ_ELF 12695 /* A global or weak symbol is treated as external. */ 12696 && (OUTPUT_FLAVOR != bfd_target_elf_flavour 12697 || (! S_IS_WEAK (sym) 12698 && (! S_IS_EXTERNAL (sym) 12699 || mips_pic == EMBEDDED_PIC))) 12700#endif 12701 ); 12702} 12703 12704 12705/* Given a mips16 variant frag FRAGP, return non-zero if it needs an 12706 extended opcode. SEC is the section the frag is in. */ 12707 12708static int 12709mips16_extended_frag (fragS *fragp, asection *sec, long stretch) 12710{ 12711 int type; 12712 register const struct mips16_immed_operand *op; 12713 offsetT val; 12714 int mintiny, maxtiny; 12715 segT symsec; 12716 fragS *sym_frag; 12717 12718 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) 12719 return 0; 12720 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) 12721 return 1; 12722 12723 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 12724 op = mips16_immed_operands; 12725 while (op->type != type) 12726 { 12727 ++op; 12728 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); 12729 } 12730 12731 if (op->unsp) 12732 { 12733 if (type == '<' || type == '>' || type == '[' || type == ']') 12734 { 12735 mintiny = 1; 12736 maxtiny = 1 << op->nbits; 12737 } 12738 else 12739 { 12740 mintiny = 0; 12741 maxtiny = (1 << op->nbits) - 1; 12742 } 12743 } 12744 else 12745 { 12746 mintiny = - (1 << (op->nbits - 1)); 12747 maxtiny = (1 << (op->nbits - 1)) - 1; 12748 } 12749 12750 sym_frag = symbol_get_frag (fragp->fr_symbol); 12751 val = S_GET_VALUE (fragp->fr_symbol); 12752 symsec = S_GET_SEGMENT (fragp->fr_symbol); 12753 12754 if (op->pcrel) 12755 { 12756 addressT addr; 12757 12758 /* We won't have the section when we are called from 12759 mips_relax_frag. However, we will always have been called 12760 from md_estimate_size_before_relax first. If this is a 12761 branch to a different section, we mark it as such. If SEC is 12762 NULL, and the frag is not marked, then it must be a branch to 12763 the same section. */ 12764 if (sec == NULL) 12765 { 12766 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) 12767 return 1; 12768 } 12769 else 12770 { 12771 /* Must have been called from md_estimate_size_before_relax. */ 12772 if (symsec != sec) 12773 { 12774 fragp->fr_subtype = 12775 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 12776 12777 /* FIXME: We should support this, and let the linker 12778 catch branches and loads that are out of range. */ 12779 as_bad_where (fragp->fr_file, fragp->fr_line, 12780 _("unsupported PC relative reference to different section")); 12781 12782 return 1; 12783 } 12784 if (fragp != sym_frag && sym_frag->fr_address == 0) 12785 /* Assume non-extended on the first relaxation pass. 12786 The address we have calculated will be bogus if this is 12787 a forward branch to another frag, as the forward frag 12788 will have fr_address == 0. */ 12789 return 0; 12790 } 12791 12792 /* In this case, we know for sure that the symbol fragment is in 12793 the same section. If the relax_marker of the symbol fragment 12794 differs from the relax_marker of this fragment, we have not 12795 yet adjusted the symbol fragment fr_address. We want to add 12796 in STRETCH in order to get a better estimate of the address. 12797 This particularly matters because of the shift bits. */ 12798 if (stretch != 0 12799 && sym_frag->relax_marker != fragp->relax_marker) 12800 { 12801 fragS *f; 12802 12803 /* Adjust stretch for any alignment frag. Note that if have 12804 been expanding the earlier code, the symbol may be 12805 defined in what appears to be an earlier frag. FIXME: 12806 This doesn't handle the fr_subtype field, which specifies 12807 a maximum number of bytes to skip when doing an 12808 alignment. */ 12809 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) 12810 { 12811 if (f->fr_type == rs_align || f->fr_type == rs_align_code) 12812 { 12813 if (stretch < 0) 12814 stretch = - ((- stretch) 12815 & ~ ((1 << (int) f->fr_offset) - 1)); 12816 else 12817 stretch &= ~ ((1 << (int) f->fr_offset) - 1); 12818 if (stretch == 0) 12819 break; 12820 } 12821 } 12822 if (f != NULL) 12823 val += stretch; 12824 } 12825 12826 addr = fragp->fr_address + fragp->fr_fix; 12827 12828 /* The base address rules are complicated. The base address of 12829 a branch is the following instruction. The base address of a 12830 PC relative load or add is the instruction itself, but if it 12831 is in a delay slot (in which case it can not be extended) use 12832 the address of the instruction whose delay slot it is in. */ 12833 if (type == 'p' || type == 'q') 12834 { 12835 addr += 2; 12836 12837 /* If we are currently assuming that this frag should be 12838 extended, then, the current address is two bytes 12839 higher. */ 12840 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 12841 addr += 2; 12842 12843 /* Ignore the low bit in the target, since it will be set 12844 for a text label. */ 12845 if ((val & 1) != 0) 12846 --val; 12847 } 12848 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 12849 addr -= 4; 12850 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 12851 addr -= 2; 12852 12853 val -= addr & ~ ((1 << op->shift) - 1); 12854 12855 /* Branch offsets have an implicit 0 in the lowest bit. */ 12856 if (type == 'p' || type == 'q') 12857 val /= 2; 12858 12859 /* If any of the shifted bits are set, we must use an extended 12860 opcode. If the address depends on the size of this 12861 instruction, this can lead to a loop, so we arrange to always 12862 use an extended opcode. We only check this when we are in 12863 the main relaxation loop, when SEC is NULL. */ 12864 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) 12865 { 12866 fragp->fr_subtype = 12867 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 12868 return 1; 12869 } 12870 12871 /* If we are about to mark a frag as extended because the value 12872 is precisely maxtiny + 1, then there is a chance of an 12873 infinite loop as in the following code: 12874 la $4,foo 12875 .skip 1020 12876 .align 2 12877 foo: 12878 In this case when the la is extended, foo is 0x3fc bytes 12879 away, so the la can be shrunk, but then foo is 0x400 away, so 12880 the la must be extended. To avoid this loop, we mark the 12881 frag as extended if it was small, and is about to become 12882 extended with a value of maxtiny + 1. */ 12883 if (val == ((maxtiny + 1) << op->shift) 12884 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) 12885 && sec == NULL) 12886 { 12887 fragp->fr_subtype = 12888 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); 12889 return 1; 12890 } 12891 } 12892 else if (symsec != absolute_section && sec != NULL) 12893 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); 12894 12895 if ((val & ((1 << op->shift) - 1)) != 0 12896 || val < (mintiny << op->shift) 12897 || val > (maxtiny << op->shift)) 12898 return 1; 12899 else 12900 return 0; 12901} 12902 12903/* Compute the length of a branch sequence, and adjust the 12904 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the 12905 worst-case length is computed, with UPDATE being used to indicate 12906 whether an unconditional (-1), branch-likely (+1) or regular (0) 12907 branch is to be computed. */ 12908static int 12909relaxed_branch_length (fragS *fragp, asection *sec, int update) 12910{ 12911 bfd_boolean toofar; 12912 int length; 12913 12914 if (fragp 12915 && S_IS_DEFINED (fragp->fr_symbol) 12916 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 12917 { 12918 addressT addr; 12919 offsetT val; 12920 12921 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 12922 12923 addr = fragp->fr_address + fragp->fr_fix + 4; 12924 12925 val -= addr; 12926 12927 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); 12928 } 12929 else if (fragp) 12930 /* If the symbol is not defined or it's in a different segment, 12931 assume the user knows what's going on and emit a short 12932 branch. */ 12933 toofar = FALSE; 12934 else 12935 toofar = TRUE; 12936 12937 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 12938 fragp->fr_subtype 12939 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype), 12940 RELAX_BRANCH_LIKELY (fragp->fr_subtype), 12941 RELAX_BRANCH_LINK (fragp->fr_subtype), 12942 toofar); 12943 12944 length = 4; 12945 if (toofar) 12946 { 12947 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) 12948 length += 8; 12949 12950 if (mips_pic != NO_PIC) 12951 { 12952 /* Additional space for PIC loading of target address. */ 12953 length += 8; 12954 if (mips_opts.isa == ISA_MIPS1) 12955 /* Additional space for $at-stabilizing nop. */ 12956 length += 4; 12957 } 12958 12959 /* If branch is conditional. */ 12960 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) 12961 length += 8; 12962 } 12963 12964 return length; 12965} 12966 12967/* Estimate the size of a frag before relaxing. Unless this is the 12968 mips16, we are not really relaxing here, and the final size is 12969 encoded in the subtype information. For the mips16, we have to 12970 decide whether we are using an extended opcode or not. */ 12971 12972int 12973md_estimate_size_before_relax (fragS *fragp, asection *segtype) 12974{ 12975 int change; 12976 12977 if (RELAX_BRANCH_P (fragp->fr_subtype)) 12978 { 12979 12980 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); 12981 12982 return fragp->fr_var; 12983 } 12984 12985 if (RELAX_MIPS16_P (fragp->fr_subtype)) 12986 /* We don't want to modify the EXTENDED bit here; it might get us 12987 into infinite loops. We change it only in mips_relax_frag(). */ 12988 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2); 12989 12990 if (mips_pic == NO_PIC) 12991 change = nopic_need_relax (fragp->fr_symbol, 0); 12992 else if (mips_pic == SVR4_PIC) 12993 change = pic_need_relax (fragp->fr_symbol, segtype); 12994 else 12995 abort (); 12996 12997 if (change) 12998 { 12999 fragp->fr_subtype |= RELAX_USE_SECOND; 13000 return -RELAX_FIRST (fragp->fr_subtype); 13001 } 13002 else 13003 return -RELAX_SECOND (fragp->fr_subtype); 13004} 13005 13006/* This is called to see whether a reloc against a defined symbol 13007 should be converted into a reloc against a section. Don't adjust 13008 MIPS16 jump relocations, so we don't have to worry about the format 13009 of the offset in the .o file. Don't adjust relocations against 13010 mips16 symbols, so that the linker can find them if it needs to set 13011 up a stub. */ 13012 13013int 13014mips_fix_adjustable (fixS *fixp) 13015{ 13016 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) 13017 return 0; 13018 13019 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT 13020 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 13021 return 0; 13022 13023 if (fixp->fx_addsy == NULL) 13024 return 1; 13025 13026 /* If symbol SYM is in a mergeable section, relocations of the form 13027 SYM + 0 can usually be made section-relative. The mergeable data 13028 is then identified by the section offset rather than by the symbol. 13029 13030 However, if we're generating REL LO16 relocations, the offset is split 13031 between the LO16 and parterning high part relocation. The linker will 13032 need to recalculate the complete offset in order to correctly identify 13033 the merge data. 13034 13035 The linker has traditionally not looked for the parterning high part 13036 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be 13037 placed anywhere. Rather than break backwards compatibility by changing 13038 this, it seems better not to force the issue, and instead keep the 13039 original symbol. This will work with either linker behavior. */ 13040 if ((fixp->fx_r_type == BFD_RELOC_LO16 13041 || reloc_needs_lo_p (fixp->fx_r_type)) 13042 && HAVE_IN_PLACE_ADDENDS 13043 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) 13044 return 0; 13045 13046#ifdef OBJ_ELF 13047 if (OUTPUT_FLAVOR == bfd_target_elf_flavour 13048 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 13049 && fixp->fx_subsy == NULL) 13050 return 0; 13051#endif 13052 13053 return 1; 13054} 13055 13056/* Translate internal representation of relocation info to BFD target 13057 format. */ 13058 13059arelent ** 13060tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 13061{ 13062 static arelent *retval[4]; 13063 arelent *reloc; 13064 bfd_reloc_code_real_type code; 13065 13066 memset (retval, 0, sizeof(retval)); 13067 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); 13068 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 13069 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 13070 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 13071 13072 if (mips_pic == EMBEDDED_PIC 13073 && SWITCH_TABLE (fixp)) 13074 { 13075 /* For a switch table entry we use a special reloc. The addend 13076 is actually the difference between the reloc address and the 13077 subtrahend. */ 13078 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); 13079 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) 13080 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); 13081 fixp->fx_r_type = BFD_RELOC_GPREL32; 13082 } 13083 else if (fixp->fx_pcrel) 13084 { 13085 bfd_vma pcrel_address; 13086 13087 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high 13088 high-part relocs is the address of the low-part reloc. */ 13089 if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) 13090 { 13091 assert (fixp->fx_next != NULL 13092 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); 13093 pcrel_address = (fixp->fx_next->fx_where 13094 + fixp->fx_next->fx_frag->fr_address); 13095 } 13096 else 13097 pcrel_address = reloc->address; 13098 13099 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 13100 { 13101 /* At this point, fx_addnumber is "symbol offset - pcrel_address". 13102 Relocations want only the symbol offset. */ 13103 reloc->addend = fixp->fx_addnumber + pcrel_address; 13104 } 13105 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16 13106 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) 13107 { 13108 /* We use a special addend for an internal RELLO or RELHI reloc. */ 13109 if (symbol_section_p (fixp->fx_addsy)) 13110 reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy); 13111 else 13112 reloc->addend = fixp->fx_addnumber + pcrel_address; 13113 } 13114 else 13115 { 13116 if (OUTPUT_FLAVOR != bfd_target_aout_flavour) 13117 /* A gruesome hack which is a result of the gruesome gas reloc 13118 handling. */ 13119 reloc->addend = pcrel_address; 13120 else 13121 reloc->addend = -pcrel_address; 13122 } 13123 } 13124 else 13125 reloc->addend = fixp->fx_addnumber; 13126 13127 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable 13128 entry to be used in the relocation's section offset. */ 13129 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 13130 { 13131 reloc->address = reloc->addend; 13132 reloc->addend = 0; 13133 } 13134 13135 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that 13136 fixup_segment converted a non-PC relative reloc into a PC 13137 relative reloc. In such a case, we need to convert the reloc 13138 code. */ 13139 code = fixp->fx_r_type; 13140 if (fixp->fx_pcrel) 13141 { 13142 switch (code) 13143 { 13144 case BFD_RELOC_8: 13145 code = BFD_RELOC_8_PCREL; 13146 break; 13147 case BFD_RELOC_16: 13148 code = BFD_RELOC_16_PCREL; 13149 break; 13150 case BFD_RELOC_32: 13151 code = BFD_RELOC_32_PCREL; 13152 break; 13153 case BFD_RELOC_64: 13154 code = BFD_RELOC_64_PCREL; 13155 break; 13156 case BFD_RELOC_8_PCREL: 13157 case BFD_RELOC_16_PCREL: 13158 case BFD_RELOC_32_PCREL: 13159 case BFD_RELOC_64_PCREL: 13160 case BFD_RELOC_16_PCREL_S2: 13161 case BFD_RELOC_PCREL_HI16_S: 13162 case BFD_RELOC_PCREL_LO16: 13163 break; 13164 default: 13165 as_bad_where (fixp->fx_file, fixp->fx_line, 13166 _("Cannot make %s relocation PC relative"), 13167 bfd_get_reloc_code_name (code)); 13168 } 13169 } 13170 13171 /* To support a PC relative reloc when generating embedded PIC code 13172 for ECOFF, we use a Cygnus extension. We check for that here to 13173 make sure that we don't let such a reloc escape normally. */ 13174 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour 13175 || OUTPUT_FLAVOR == bfd_target_elf_flavour) 13176 && code == BFD_RELOC_16_PCREL_S2 13177 && mips_pic != EMBEDDED_PIC) 13178 reloc->howto = NULL; 13179 else 13180 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 13181 13182 if (reloc->howto == NULL) 13183 { 13184 as_bad_where (fixp->fx_file, fixp->fx_line, 13185 _("Can not represent %s relocation in this object file format"), 13186 bfd_get_reloc_code_name (code)); 13187 retval[0] = NULL; 13188 } 13189 13190 return retval; 13191} 13192 13193/* Relax a machine dependent frag. This returns the amount by which 13194 the current size of the frag should change. */ 13195 13196int 13197mips_relax_frag (asection *sec, fragS *fragp, long stretch) 13198{ 13199 if (RELAX_BRANCH_P (fragp->fr_subtype)) 13200 { 13201 offsetT old_var = fragp->fr_var; 13202 13203 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 13204 13205 return fragp->fr_var - old_var; 13206 } 13207 13208 if (! RELAX_MIPS16_P (fragp->fr_subtype)) 13209 return 0; 13210 13211 if (mips16_extended_frag (fragp, NULL, stretch)) 13212 { 13213 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 13214 return 0; 13215 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); 13216 return 2; 13217 } 13218 else 13219 { 13220 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 13221 return 0; 13222 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); 13223 return -2; 13224 } 13225 13226 return 0; 13227} 13228 13229/* Convert a machine dependent frag. */ 13230 13231void 13232md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) 13233{ 13234 if (RELAX_BRANCH_P (fragp->fr_subtype)) 13235 { 13236 bfd_byte *buf; 13237 unsigned long insn; 13238 expressionS exp; 13239 fixS *fixp; 13240 13241 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; 13242 13243 if (target_big_endian) 13244 insn = bfd_getb32 (buf); 13245 else 13246 insn = bfd_getl32 (buf); 13247 13248 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) 13249 { 13250 /* We generate a fixup instead of applying it right now 13251 because, if there are linker relaxations, we're going to 13252 need the relocations. */ 13253 exp.X_op = O_symbol; 13254 exp.X_add_symbol = fragp->fr_symbol; 13255 exp.X_add_number = fragp->fr_offset; 13256 13257 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 13258 4, &exp, 1, 13259 BFD_RELOC_16_PCREL_S2); 13260 fixp->fx_file = fragp->fr_file; 13261 fixp->fx_line = fragp->fr_line; 13262 13263 md_number_to_chars (buf, insn, 4); 13264 buf += 4; 13265 } 13266 else 13267 { 13268 int i; 13269 13270 as_warn_where (fragp->fr_file, fragp->fr_line, 13271 _("relaxed out-of-range branch into a jump")); 13272 13273 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) 13274 goto uncond; 13275 13276 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 13277 { 13278 /* Reverse the branch. */ 13279 switch ((insn >> 28) & 0xf) 13280 { 13281 case 4: 13282 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can 13283 have the condition reversed by tweaking a single 13284 bit, and their opcodes all have 0x4???????. */ 13285 assert ((insn & 0xf1000000) == 0x41000000); 13286 insn ^= 0x00010000; 13287 break; 13288 13289 case 0: 13290 /* bltz 0x04000000 bgez 0x04010000 13291 bltzal 0x04100000 bgezal 0x04110000 */ 13292 assert ((insn & 0xfc0e0000) == 0x04000000); 13293 insn ^= 0x00010000; 13294 break; 13295 13296 case 1: 13297 /* beq 0x10000000 bne 0x14000000 13298 blez 0x18000000 bgtz 0x1c000000 */ 13299 insn ^= 0x04000000; 13300 break; 13301 13302 default: 13303 abort (); 13304 } 13305 } 13306 13307 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 13308 { 13309 /* Clear the and-link bit. */ 13310 assert ((insn & 0xfc1c0000) == 0x04100000); 13311 13312 /* bltzal 0x04100000 bgezal 0x04110000 13313 bltzall 0x04120000 bgezall 0x04130000 */ 13314 insn &= ~0x00100000; 13315 } 13316 13317 /* Branch over the branch (if the branch was likely) or the 13318 full jump (not likely case). Compute the offset from the 13319 current instruction to branch to. */ 13320 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 13321 i = 16; 13322 else 13323 { 13324 /* How many bytes in instructions we've already emitted? */ 13325 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; 13326 /* How many bytes in instructions from here to the end? */ 13327 i = fragp->fr_var - i; 13328 } 13329 /* Convert to instruction count. */ 13330 i >>= 2; 13331 /* Branch counts from the next instruction. */ 13332 i--; 13333 insn |= i; 13334 /* Branch over the jump. */ 13335 md_number_to_chars (buf, insn, 4); 13336 buf += 4; 13337 13338 /* Nop */ 13339 md_number_to_chars (buf, 0, 4); 13340 buf += 4; 13341 13342 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) 13343 { 13344 /* beql $0, $0, 2f */ 13345 insn = 0x50000000; 13346 /* Compute the PC offset from the current instruction to 13347 the end of the variable frag. */ 13348 /* How many bytes in instructions we've already emitted? */ 13349 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix; 13350 /* How many bytes in instructions from here to the end? */ 13351 i = fragp->fr_var - i; 13352 /* Convert to instruction count. */ 13353 i >>= 2; 13354 /* Don't decrement i, because we want to branch over the 13355 delay slot. */ 13356 13357 insn |= i; 13358 md_number_to_chars (buf, insn, 4); 13359 buf += 4; 13360 13361 md_number_to_chars (buf, 0, 4); 13362 buf += 4; 13363 } 13364 13365 uncond: 13366 if (mips_pic == NO_PIC) 13367 { 13368 /* j or jal. */ 13369 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) 13370 ? 0x0c000000 : 0x08000000); 13371 exp.X_op = O_symbol; 13372 exp.X_add_symbol = fragp->fr_symbol; 13373 exp.X_add_number = fragp->fr_offset; 13374 13375 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 13376 4, &exp, 0, BFD_RELOC_MIPS_JMP); 13377 fixp->fx_file = fragp->fr_file; 13378 fixp->fx_line = fragp->fr_line; 13379 13380 md_number_to_chars (buf, insn, 4); 13381 buf += 4; 13382 } 13383 else 13384 { 13385 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ 13386 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000; 13387 exp.X_op = O_symbol; 13388 exp.X_add_symbol = fragp->fr_symbol; 13389 exp.X_add_number = fragp->fr_offset; 13390 13391 if (fragp->fr_offset) 13392 { 13393 exp.X_add_symbol = make_expr_symbol (&exp); 13394 exp.X_add_number = 0; 13395 } 13396 13397 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 13398 4, &exp, 0, BFD_RELOC_MIPS_GOT16); 13399 fixp->fx_file = fragp->fr_file; 13400 fixp->fx_line = fragp->fr_line; 13401 13402 md_number_to_chars (buf, insn, 4); 13403 buf += 4; 13404 13405 if (mips_opts.isa == ISA_MIPS1) 13406 { 13407 /* nop */ 13408 md_number_to_chars (buf, 0, 4); 13409 buf += 4; 13410 } 13411 13412 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ 13413 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000; 13414 13415 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 13416 4, &exp, 0, BFD_RELOC_LO16); 13417 fixp->fx_file = fragp->fr_file; 13418 fixp->fx_line = fragp->fr_line; 13419 13420 md_number_to_chars (buf, insn, 4); 13421 buf += 4; 13422 13423 /* j(al)r $at. */ 13424 if (RELAX_BRANCH_LINK (fragp->fr_subtype)) 13425 insn = 0x0020f809; 13426 else 13427 insn = 0x00200008; 13428 13429 md_number_to_chars (buf, insn, 4); 13430 buf += 4; 13431 } 13432 } 13433 13434 assert (buf == (bfd_byte *)fragp->fr_literal 13435 + fragp->fr_fix + fragp->fr_var); 13436 13437 fragp->fr_fix += fragp->fr_var; 13438 13439 return; 13440 } 13441 13442 if (RELAX_MIPS16_P (fragp->fr_subtype)) 13443 { 13444 int type; 13445 register const struct mips16_immed_operand *op; 13446 bfd_boolean small, ext; 13447 offsetT val; 13448 bfd_byte *buf; 13449 unsigned long insn; 13450 bfd_boolean use_extend; 13451 unsigned short extend; 13452 13453 type = RELAX_MIPS16_TYPE (fragp->fr_subtype); 13454 op = mips16_immed_operands; 13455 while (op->type != type) 13456 ++op; 13457 13458 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) 13459 { 13460 small = FALSE; 13461 ext = TRUE; 13462 } 13463 else 13464 { 13465 small = TRUE; 13466 ext = FALSE; 13467 } 13468 13469 resolve_symbol_value (fragp->fr_symbol); 13470 val = S_GET_VALUE (fragp->fr_symbol); 13471 if (op->pcrel) 13472 { 13473 addressT addr; 13474 13475 addr = fragp->fr_address + fragp->fr_fix; 13476 13477 /* The rules for the base address of a PC relative reloc are 13478 complicated; see mips16_extended_frag. */ 13479 if (type == 'p' || type == 'q') 13480 { 13481 addr += 2; 13482 if (ext) 13483 addr += 2; 13484 /* Ignore the low bit in the target, since it will be 13485 set for a text label. */ 13486 if ((val & 1) != 0) 13487 --val; 13488 } 13489 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) 13490 addr -= 4; 13491 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) 13492 addr -= 2; 13493 13494 addr &= ~ (addressT) ((1 << op->shift) - 1); 13495 val -= addr; 13496 13497 /* Make sure the section winds up with the alignment we have 13498 assumed. */ 13499 if (op->shift > 0) 13500 record_alignment (asec, op->shift); 13501 } 13502 13503 if (ext 13504 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) 13505 || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) 13506 as_warn_where (fragp->fr_file, fragp->fr_line, 13507 _("extended instruction in delay slot")); 13508 13509 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); 13510 13511 if (target_big_endian) 13512 insn = bfd_getb16 (buf); 13513 else 13514 insn = bfd_getl16 (buf); 13515 13516 mips16_immed (fragp->fr_file, fragp->fr_line, type, val, 13517 RELAX_MIPS16_USER_EXT (fragp->fr_subtype), 13518 small, ext, &insn, &use_extend, &extend); 13519 13520 if (use_extend) 13521 { 13522 md_number_to_chars (buf, 0xf000 | extend, 2); 13523 fragp->fr_fix += 2; 13524 buf += 2; 13525 } 13526 13527 md_number_to_chars (buf, insn, 2); 13528 fragp->fr_fix += 2; 13529 buf += 2; 13530 } 13531 else 13532 { 13533 int first, second; 13534 fixS *fixp; 13535 13536 first = RELAX_FIRST (fragp->fr_subtype); 13537 second = RELAX_SECOND (fragp->fr_subtype); 13538 fixp = (fixS *) fragp->fr_opcode; 13539 13540 /* Possibly emit a warning if we've chosen the longer option. */ 13541 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0) 13542 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0)) 13543 { 13544 const char *msg = macro_warning (fragp->fr_subtype); 13545 if (msg != 0) 13546 as_warn_where (fragp->fr_file, fragp->fr_line, msg); 13547 } 13548 13549 /* Go through all the fixups for the first sequence. Disable them 13550 (by marking them as done) if we're going to use the second 13551 sequence instead. */ 13552 while (fixp 13553 && fixp->fx_frag == fragp 13554 && fixp->fx_where < fragp->fr_fix - second) 13555 { 13556 if (fragp->fr_subtype & RELAX_USE_SECOND) 13557 fixp->fx_done = 1; 13558 fixp = fixp->fx_next; 13559 } 13560 13561 /* Go through the fixups for the second sequence. Disable them if 13562 we're going to use the first sequence, otherwise adjust their 13563 addresses to account for the relaxation. */ 13564 while (fixp && fixp->fx_frag == fragp) 13565 { 13566 if (fragp->fr_subtype & RELAX_USE_SECOND) 13567 fixp->fx_where -= first; 13568 else 13569 fixp->fx_done = 1; 13570 fixp = fixp->fx_next; 13571 } 13572 13573 /* Now modify the frag contents. */ 13574 if (fragp->fr_subtype & RELAX_USE_SECOND) 13575 { 13576 char *start; 13577 13578 start = fragp->fr_literal + fragp->fr_fix - first - second; 13579 memmove (start, start + first, second); 13580 fragp->fr_fix -= first; 13581 } 13582 else 13583 fragp->fr_fix -= second; 13584 } 13585} 13586 13587#ifdef OBJ_ELF 13588 13589/* This function is called after the relocs have been generated. 13590 We've been storing mips16 text labels as odd. Here we convert them 13591 back to even for the convenience of the debugger. */ 13592 13593void 13594mips_frob_file_after_relocs (void) 13595{ 13596 asymbol **syms; 13597 unsigned int count, i; 13598 13599 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 13600 return; 13601 13602 syms = bfd_get_outsymbols (stdoutput); 13603 count = bfd_get_symcount (stdoutput); 13604 for (i = 0; i < count; i++, syms++) 13605 { 13606 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 13607 && ((*syms)->value & 1) != 0) 13608 { 13609 (*syms)->value &= ~1; 13610 /* If the symbol has an odd size, it was probably computed 13611 incorrectly, so adjust that as well. */ 13612 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) 13613 ++elf_symbol (*syms)->internal_elf_sym.st_size; 13614 } 13615 } 13616} 13617 13618#endif 13619 13620/* This function is called whenever a label is defined. It is used 13621 when handling branch delays; if a branch has a label, we assume we 13622 can not move it. */ 13623 13624void 13625mips_define_label (symbolS *sym) 13626{ 13627 struct insn_label_list *l; 13628 13629 if (free_insn_labels == NULL) 13630 l = (struct insn_label_list *) xmalloc (sizeof *l); 13631 else 13632 { 13633 l = free_insn_labels; 13634 free_insn_labels = l->next; 13635 } 13636 13637 l->label = sym; 13638 l->next = insn_labels; 13639 insn_labels = l; 13640} 13641 13642#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 13643 13644/* Some special processing for a MIPS ELF file. */ 13645 13646void 13647mips_elf_final_processing (void) 13648{ 13649 /* Write out the register information. */ 13650 if (mips_abi != N64_ABI) 13651 { 13652 Elf32_RegInfo s; 13653 13654 s.ri_gprmask = mips_gprmask; 13655 s.ri_cprmask[0] = mips_cprmask[0]; 13656 s.ri_cprmask[1] = mips_cprmask[1]; 13657 s.ri_cprmask[2] = mips_cprmask[2]; 13658 s.ri_cprmask[3] = mips_cprmask[3]; 13659 /* The gp_value field is set by the MIPS ELF backend. */ 13660 13661 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, 13662 ((Elf32_External_RegInfo *) 13663 mips_regmask_frag)); 13664 } 13665 else 13666 { 13667 Elf64_Internal_RegInfo s; 13668 13669 s.ri_gprmask = mips_gprmask; 13670 s.ri_pad = 0; 13671 s.ri_cprmask[0] = mips_cprmask[0]; 13672 s.ri_cprmask[1] = mips_cprmask[1]; 13673 s.ri_cprmask[2] = mips_cprmask[2]; 13674 s.ri_cprmask[3] = mips_cprmask[3]; 13675 /* The gp_value field is set by the MIPS ELF backend. */ 13676 13677 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, 13678 ((Elf64_External_RegInfo *) 13679 mips_regmask_frag)); 13680 } 13681 13682 /* Set the MIPS ELF flag bits. FIXME: There should probably be some 13683 sort of BFD interface for this. */ 13684 if (mips_any_noreorder) 13685 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; 13686 if (mips_pic != NO_PIC) 13687 { 13688 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; 13689 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 13690 } 13691 if (mips_abicalls) 13692 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; 13693 13694 /* Set MIPS ELF flags for ASEs. */ 13695 if (file_ase_mips16) 13696 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; 13697#if 0 /* XXX FIXME */ 13698 if (file_ase_mips3d) 13699 elf_elfheader (stdoutput)->e_flags |= ???; 13700#endif 13701 if (file_ase_mdmx) 13702 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; 13703 13704 /* Set the MIPS ELF ABI flags. */ 13705 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) 13706 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; 13707 else if (mips_abi == O64_ABI) 13708 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; 13709 else if (mips_abi == EABI_ABI) 13710 { 13711 if (!file_mips_gp32) 13712 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; 13713 else 13714 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; 13715 } 13716 else if (mips_abi == N32_ABI) 13717 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; 13718 13719 /* Nothing to do for N64_ABI. */ 13720 13721 if (mips_32bitmode) 13722 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; 13723} 13724 13725#endif /* OBJ_ELF || OBJ_MAYBE_ELF */ 13726 13727typedef struct proc { 13728 symbolS *isym; 13729 unsigned long reg_mask; 13730 unsigned long reg_offset; 13731 unsigned long fpreg_mask; 13732 unsigned long fpreg_offset; 13733 unsigned long frame_offset; 13734 unsigned long frame_reg; 13735 unsigned long pc_reg; 13736} procS; 13737 13738static procS cur_proc; 13739static procS *cur_proc_ptr; 13740static int numprocs; 13741 13742/* Fill in an rs_align_code fragment. */ 13743 13744void 13745mips_handle_align (fragS *fragp) 13746{ 13747 if (fragp->fr_type != rs_align_code) 13748 return; 13749 13750 if (mips_opts.mips16) 13751 { 13752 static const unsigned char be_nop[] = { 0x65, 0x00 }; 13753 static const unsigned char le_nop[] = { 0x00, 0x65 }; 13754 13755 int bytes; 13756 char *p; 13757 13758 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 13759 p = fragp->fr_literal + fragp->fr_fix; 13760 13761 if (bytes & 1) 13762 { 13763 *p++ = 0; 13764 fragp->fr_fix++; 13765 } 13766 13767 memcpy (p, (target_big_endian ? be_nop : le_nop), 2); 13768 fragp->fr_var = 2; 13769 } 13770 13771 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ 13772} 13773 13774static void 13775md_obj_begin (void) 13776{ 13777} 13778 13779static void 13780md_obj_end (void) 13781{ 13782 /* check for premature end, nesting errors, etc */ 13783 if (cur_proc_ptr) 13784 as_warn (_("missing .end at end of assembly")); 13785} 13786 13787static long 13788get_number (void) 13789{ 13790 int negative = 0; 13791 long val = 0; 13792 13793 if (*input_line_pointer == '-') 13794 { 13795 ++input_line_pointer; 13796 negative = 1; 13797 } 13798 if (!ISDIGIT (*input_line_pointer)) 13799 as_bad (_("expected simple number")); 13800 if (input_line_pointer[0] == '0') 13801 { 13802 if (input_line_pointer[1] == 'x') 13803 { 13804 input_line_pointer += 2; 13805 while (ISXDIGIT (*input_line_pointer)) 13806 { 13807 val <<= 4; 13808 val |= hex_value (*input_line_pointer++); 13809 } 13810 return negative ? -val : val; 13811 } 13812 else 13813 { 13814 ++input_line_pointer; 13815 while (ISDIGIT (*input_line_pointer)) 13816 { 13817 val <<= 3; 13818 val |= *input_line_pointer++ - '0'; 13819 } 13820 return negative ? -val : val; 13821 } 13822 } 13823 if (!ISDIGIT (*input_line_pointer)) 13824 { 13825 printf (_(" *input_line_pointer == '%c' 0x%02x\n"), 13826 *input_line_pointer, *input_line_pointer); 13827 as_warn (_("invalid number")); 13828 return -1; 13829 } 13830 while (ISDIGIT (*input_line_pointer)) 13831 { 13832 val *= 10; 13833 val += *input_line_pointer++ - '0'; 13834 } 13835 return negative ? -val : val; 13836} 13837 13838/* The .file directive; just like the usual .file directive, but there 13839 is an initial number which is the ECOFF file index. In the non-ECOFF 13840 case .file implies DWARF-2. */ 13841 13842static void 13843s_mips_file (int x ATTRIBUTE_UNUSED) 13844{ 13845 static int first_file_directive = 0; 13846 13847 if (ECOFF_DEBUGGING) 13848 { 13849 get_number (); 13850 s_app_file (0); 13851 } 13852 else 13853 { 13854 char *filename; 13855 13856 filename = dwarf2_directive_file (0); 13857 13858 /* Versions of GCC up to 3.1 start files with a ".file" 13859 directive even for stabs output. Make sure that this 13860 ".file" is handled. Note that you need a version of GCC 13861 after 3.1 in order to support DWARF-2 on MIPS. */ 13862 if (filename != NULL && ! first_file_directive) 13863 { 13864 (void) new_logical_line (filename, -1); 13865 s_app_file_string (filename); 13866 } 13867 first_file_directive = 1; 13868 } 13869} 13870 13871/* The .loc directive, implying DWARF-2. */ 13872 13873static void 13874s_mips_loc (int x ATTRIBUTE_UNUSED) 13875{ 13876 if (!ECOFF_DEBUGGING) 13877 dwarf2_directive_loc (0); 13878} 13879 13880/* The .end directive. */ 13881 13882static void 13883s_mips_end (int x ATTRIBUTE_UNUSED) 13884{ 13885 symbolS *p; 13886 13887 /* Following functions need their own .frame and .cprestore directives. */ 13888 mips_frame_reg_valid = 0; 13889 mips_cprestore_valid = 0; 13890 13891 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 13892 { 13893 p = get_symbol (); 13894 demand_empty_rest_of_line (); 13895 } 13896 else 13897 p = NULL; 13898 13899 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 13900 as_warn (_(".end not in text section")); 13901 13902 if (!cur_proc_ptr) 13903 { 13904 as_warn (_(".end directive without a preceding .ent directive.")); 13905 demand_empty_rest_of_line (); 13906 return; 13907 } 13908 13909 if (p != NULL) 13910 { 13911 assert (S_GET_NAME (p)); 13912 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) 13913 as_warn (_(".end symbol does not match .ent symbol.")); 13914 13915 if (debug_type == DEBUG_STABS) 13916 stabs_generate_asm_endfunc (S_GET_NAME (p), 13917 S_GET_NAME (p)); 13918 } 13919 else 13920 as_warn (_(".end directive missing or unknown symbol")); 13921 13922#ifdef OBJ_ELF 13923 /* Generate a .pdr section. */ 13924 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING 13925 && mips_flag_pdr) 13926 { 13927 segT saved_seg = now_seg; 13928 subsegT saved_subseg = now_subseg; 13929 valueT dot; 13930 expressionS exp; 13931 char *fragp; 13932 13933 dot = frag_now_fix (); 13934 13935#ifdef md_flush_pending_output 13936 md_flush_pending_output (); 13937#endif 13938 13939 assert (pdr_seg); 13940 subseg_set (pdr_seg, 0); 13941 13942 /* Write the symbol. */ 13943 exp.X_op = O_symbol; 13944 exp.X_add_symbol = p; 13945 exp.X_add_number = 0; 13946 emit_expr (&exp, 4); 13947 13948 fragp = frag_more (7 * 4); 13949 13950 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); 13951 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); 13952 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); 13953 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); 13954 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); 13955 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); 13956 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); 13957 13958 subseg_set (saved_seg, saved_subseg); 13959 } 13960#endif /* OBJ_ELF */ 13961 13962 cur_proc_ptr = NULL; 13963} 13964 13965/* The .aent and .ent directives. */ 13966 13967static void 13968s_mips_ent (int aent) 13969{ 13970 symbolS *symbolP; 13971 13972 symbolP = get_symbol (); 13973 if (*input_line_pointer == ',') 13974 ++input_line_pointer; 13975 SKIP_WHITESPACE (); 13976 if (ISDIGIT (*input_line_pointer) 13977 || *input_line_pointer == '-') 13978 get_number (); 13979 13980 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) 13981 as_warn (_(".ent or .aent not in text section.")); 13982 13983 if (!aent && cur_proc_ptr) 13984 as_warn (_("missing .end")); 13985 13986 if (!aent) 13987 { 13988 /* This function needs its own .frame and .cprestore directives. */ 13989 mips_frame_reg_valid = 0; 13990 mips_cprestore_valid = 0; 13991 13992 cur_proc_ptr = &cur_proc; 13993 memset (cur_proc_ptr, '\0', sizeof (procS)); 13994 13995 cur_proc_ptr->isym = symbolP; 13996 13997 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; 13998 13999 ++numprocs; 14000 14001 if (debug_type == DEBUG_STABS) 14002 stabs_generate_asm_func (S_GET_NAME (symbolP), 14003 S_GET_NAME (symbolP)); 14004 } 14005 14006 demand_empty_rest_of_line (); 14007} 14008 14009/* The .frame directive. If the mdebug section is present (IRIX 5 native) 14010 then ecoff.c (ecoff_directive_frame) is used. For embedded targets, 14011 s_mips_frame is used so that we can set the PDR information correctly. 14012 We can't use the ecoff routines because they make reference to the ecoff 14013 symbol table (in the mdebug section). */ 14014 14015static void 14016s_mips_frame (int ignore ATTRIBUTE_UNUSED) 14017{ 14018#ifdef OBJ_ELF 14019 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) 14020 { 14021 long val; 14022 14023 if (cur_proc_ptr == (procS *) NULL) 14024 { 14025 as_warn (_(".frame outside of .ent")); 14026 demand_empty_rest_of_line (); 14027 return; 14028 } 14029 14030 cur_proc_ptr->frame_reg = tc_get_register (1); 14031 14032 SKIP_WHITESPACE (); 14033 if (*input_line_pointer++ != ',' 14034 || get_absolute_expression_and_terminator (&val) != ',') 14035 { 14036 as_warn (_("Bad .frame directive")); 14037 --input_line_pointer; 14038 demand_empty_rest_of_line (); 14039 return; 14040 } 14041 14042 cur_proc_ptr->frame_offset = val; 14043 cur_proc_ptr->pc_reg = tc_get_register (0); 14044 14045 demand_empty_rest_of_line (); 14046 } 14047 else 14048#endif /* OBJ_ELF */ 14049 s_ignore (ignore); 14050} 14051 14052/* The .fmask and .mask directives. If the mdebug section is present 14053 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For 14054 embedded targets, s_mips_mask is used so that we can set the PDR 14055 information correctly. We can't use the ecoff routines because they 14056 make reference to the ecoff symbol table (in the mdebug section). */ 14057 14058static void 14059s_mips_mask (int reg_type) 14060{ 14061#ifdef OBJ_ELF 14062 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING) 14063 { 14064 long mask, off; 14065 14066 if (cur_proc_ptr == (procS *) NULL) 14067 { 14068 as_warn (_(".mask/.fmask outside of .ent")); 14069 demand_empty_rest_of_line (); 14070 return; 14071 } 14072 14073 if (get_absolute_expression_and_terminator (&mask) != ',') 14074 { 14075 as_warn (_("Bad .mask/.fmask directive")); 14076 --input_line_pointer; 14077 demand_empty_rest_of_line (); 14078 return; 14079 } 14080 14081 off = get_absolute_expression (); 14082 14083 if (reg_type == 'F') 14084 { 14085 cur_proc_ptr->fpreg_mask = mask; 14086 cur_proc_ptr->fpreg_offset = off; 14087 } 14088 else 14089 { 14090 cur_proc_ptr->reg_mask = mask; 14091 cur_proc_ptr->reg_offset = off; 14092 } 14093 14094 demand_empty_rest_of_line (); 14095 } 14096 else 14097#endif /* OBJ_ELF */ 14098 s_ignore (reg_type); 14099} 14100 14101/* The .loc directive. */ 14102 14103#if 0 14104static void 14105s_loc (int x) 14106{ 14107 symbolS *symbolP; 14108 int lineno; 14109 int addroff; 14110 14111 assert (now_seg == text_section); 14112 14113 lineno = get_number (); 14114 addroff = frag_now_fix (); 14115 14116 symbolP = symbol_new ("", N_SLINE, addroff, frag_now); 14117 S_SET_TYPE (symbolP, N_SLINE); 14118 S_SET_OTHER (symbolP, 0); 14119 S_SET_DESC (symbolP, lineno); 14120 symbolP->sy_segment = now_seg; 14121} 14122#endif 14123 14124/* A table describing all the processors gas knows about. Names are 14125 matched in the order listed. 14126 14127 To ease comparison, please keep this table in the same order as 14128 gcc's mips_cpu_info_table[]. */ 14129static const struct mips_cpu_info mips_cpu_info_table[] = 14130{ 14131 /* Entries for generic ISAs */ 14132 { "mips1", 1, ISA_MIPS1, CPU_R3000 }, 14133 { "mips2", 1, ISA_MIPS2, CPU_R6000 }, 14134 { "mips3", 1, ISA_MIPS3, CPU_R4000 }, 14135 { "mips4", 1, ISA_MIPS4, CPU_R8000 }, 14136 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 }, 14137 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 }, 14138 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 }, 14139 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 }, 14140 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 }, 14141 14142 /* MIPS I */ 14143 { "r3000", 0, ISA_MIPS1, CPU_R3000 }, 14144 { "r2000", 0, ISA_MIPS1, CPU_R3000 }, 14145 { "r3900", 0, ISA_MIPS1, CPU_R3900 }, 14146 14147 /* MIPS II */ 14148 { "r6000", 0, ISA_MIPS2, CPU_R6000 }, 14149 14150 /* MIPS III */ 14151 { "r4000", 0, ISA_MIPS3, CPU_R4000 }, 14152 { "r4010", 0, ISA_MIPS2, CPU_R4010 }, 14153 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 }, 14154 { "vr4111", 0, ISA_MIPS3, CPU_R4111 }, 14155 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 }, 14156 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 }, 14157 { "vr4181", 0, ISA_MIPS3, CPU_R4111 }, 14158 { "vr4300", 0, ISA_MIPS3, CPU_R4300 }, 14159 { "r4400", 0, ISA_MIPS3, CPU_R4400 }, 14160 { "r4600", 0, ISA_MIPS3, CPU_R4600 }, 14161 { "orion", 0, ISA_MIPS3, CPU_R4600 }, 14162 { "r4650", 0, ISA_MIPS3, CPU_R4650 }, 14163 14164 /* MIPS IV */ 14165 { "r8000", 0, ISA_MIPS4, CPU_R8000 }, 14166 { "r10000", 0, ISA_MIPS4, CPU_R10000 }, 14167 { "r12000", 0, ISA_MIPS4, CPU_R12000 }, 14168 { "vr5000", 0, ISA_MIPS4, CPU_R5000 }, 14169 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 }, 14170 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 }, 14171 { "rm5200", 0, ISA_MIPS4, CPU_R5000 }, 14172 { "rm5230", 0, ISA_MIPS4, CPU_R5000 }, 14173 { "rm5231", 0, ISA_MIPS4, CPU_R5000 }, 14174 { "rm5261", 0, ISA_MIPS4, CPU_R5000 }, 14175 { "rm5721", 0, ISA_MIPS4, CPU_R5000 }, 14176 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 }, 14177 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 }, 14178 14179 /* MIPS 32 */ 14180 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 }, 14181 { "4km", 0, ISA_MIPS32, CPU_MIPS32 }, 14182 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 }, 14183 14184 /* MIPS 64 */ 14185 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, 14186 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 }, 14187 14188 /* Broadcom SB-1 CPU core */ 14189 { "sb1", 0, ISA_MIPS64, CPU_SB1 }, 14190 14191 /* End marker */ 14192 { NULL, 0, 0, 0 } 14193}; 14194 14195 14196/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL 14197 with a final "000" replaced by "k". Ignore case. 14198 14199 Note: this function is shared between GCC and GAS. */ 14200 14201static bfd_boolean 14202mips_strict_matching_cpu_name_p (const char *canonical, const char *given) 14203{ 14204 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) 14205 given++, canonical++; 14206 14207 return ((*given == 0 && *canonical == 0) 14208 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); 14209} 14210 14211 14212/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied 14213 CPU name. We've traditionally allowed a lot of variation here. 14214 14215 Note: this function is shared between GCC and GAS. */ 14216 14217static bfd_boolean 14218mips_matching_cpu_name_p (const char *canonical, const char *given) 14219{ 14220 /* First see if the name matches exactly, or with a final "000" 14221 turned into "k". */ 14222 if (mips_strict_matching_cpu_name_p (canonical, given)) 14223 return TRUE; 14224 14225 /* If not, try comparing based on numerical designation alone. 14226 See if GIVEN is an unadorned number, or 'r' followed by a number. */ 14227 if (TOLOWER (*given) == 'r') 14228 given++; 14229 if (!ISDIGIT (*given)) 14230 return FALSE; 14231 14232 /* Skip over some well-known prefixes in the canonical name, 14233 hoping to find a number there too. */ 14234 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') 14235 canonical += 2; 14236 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') 14237 canonical += 2; 14238 else if (TOLOWER (canonical[0]) == 'r') 14239 canonical += 1; 14240 14241 return mips_strict_matching_cpu_name_p (canonical, given); 14242} 14243 14244 14245/* Parse an option that takes the name of a processor as its argument. 14246 OPTION is the name of the option and CPU_STRING is the argument. 14247 Return the corresponding processor enumeration if the CPU_STRING is 14248 recognized, otherwise report an error and return null. 14249 14250 A similar function exists in GCC. */ 14251 14252static const struct mips_cpu_info * 14253mips_parse_cpu (const char *option, const char *cpu_string) 14254{ 14255 const struct mips_cpu_info *p; 14256 14257 /* 'from-abi' selects the most compatible architecture for the given 14258 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the 14259 EABIs, we have to decide whether we're using the 32-bit or 64-bit 14260 version. Look first at the -mgp options, if given, otherwise base 14261 the choice on MIPS_DEFAULT_64BIT. 14262 14263 Treat NO_ABI like the EABIs. One reason to do this is that the 14264 plain 'mips' and 'mips64' configs have 'from-abi' as their default 14265 architecture. This code picks MIPS I for 'mips' and MIPS III for 14266 'mips64', just as we did in the days before 'from-abi'. */ 14267 if (strcasecmp (cpu_string, "from-abi") == 0) 14268 { 14269 if (ABI_NEEDS_32BIT_REGS (mips_abi)) 14270 return mips_cpu_info_from_isa (ISA_MIPS1); 14271 14272 if (ABI_NEEDS_64BIT_REGS (mips_abi)) 14273 return mips_cpu_info_from_isa (ISA_MIPS3); 14274 14275 if (file_mips_gp32 >= 0) 14276 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); 14277 14278 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT 14279 ? ISA_MIPS3 14280 : ISA_MIPS1); 14281 } 14282 14283 /* 'default' has traditionally been a no-op. Probably not very useful. */ 14284 if (strcasecmp (cpu_string, "default") == 0) 14285 return 0; 14286 14287 for (p = mips_cpu_info_table; p->name != 0; p++) 14288 if (mips_matching_cpu_name_p (p->name, cpu_string)) 14289 return p; 14290 14291 as_bad ("Bad value (%s) for %s", cpu_string, option); 14292 return 0; 14293} 14294 14295/* Return the canonical processor information for ISA (a member of the 14296 ISA_MIPS* enumeration). */ 14297 14298static const struct mips_cpu_info * 14299mips_cpu_info_from_isa (int isa) 14300{ 14301 int i; 14302 14303 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 14304 if (mips_cpu_info_table[i].is_isa 14305 && isa == mips_cpu_info_table[i].isa) 14306 return (&mips_cpu_info_table[i]); 14307 14308 return NULL; 14309} 14310 14311static const struct mips_cpu_info * 14312mips_cpu_info_from_arch (int arch) 14313{ 14314 int i; 14315 14316 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 14317 if (arch == mips_cpu_info_table[i].cpu) 14318 return (&mips_cpu_info_table[i]); 14319 14320 return NULL; 14321} 14322 14323static void 14324show (FILE *stream, const char *string, int *col_p, int *first_p) 14325{ 14326 if (*first_p) 14327 { 14328 fprintf (stream, "%24s", ""); 14329 *col_p = 24; 14330 } 14331 else 14332 { 14333 fprintf (stream, ", "); 14334 *col_p += 2; 14335 } 14336 14337 if (*col_p + strlen (string) > 72) 14338 { 14339 fprintf (stream, "\n%24s", ""); 14340 *col_p = 24; 14341 } 14342 14343 fprintf (stream, "%s", string); 14344 *col_p += strlen (string); 14345 14346 *first_p = 0; 14347} 14348 14349void 14350md_show_usage (FILE *stream) 14351{ 14352 int column, first; 14353 size_t i; 14354 14355 fprintf (stream, _("\ 14356MIPS options:\n\ 14357-membedded-pic generate embedded position independent code\n\ 14358-EB generate big endian output\n\ 14359-EL generate little endian output\n\ 14360-g, -g2 do not remove unneeded NOPs or swap branches\n\ 14361-G NUM allow referencing objects up to NUM bytes\n\ 14362 implicitly with the gp register [default 8]\n")); 14363 fprintf (stream, _("\ 14364-mips1 generate MIPS ISA I instructions\n\ 14365-mips2 generate MIPS ISA II instructions\n\ 14366-mips3 generate MIPS ISA III instructions\n\ 14367-mips4 generate MIPS ISA IV instructions\n\ 14368-mips5 generate MIPS ISA V instructions\n\ 14369-mips32 generate MIPS32 ISA instructions\n\ 14370-mips32r2 generate MIPS32 release 2 ISA instructions\n\ 14371-mips64 generate MIPS64 ISA instructions\n\ 14372-mips64r2 generate MIPS64 release 2 ISA instructions\n\ 14373-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); 14374 14375 first = 1; 14376 14377 for (i = 0; mips_cpu_info_table[i].name != NULL; i++) 14378 show (stream, mips_cpu_info_table[i].name, &column, &first); 14379 show (stream, "from-abi", &column, &first); 14380 fputc ('\n', stream); 14381 14382 fprintf (stream, _("\ 14383-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ 14384-no-mCPU don't generate code specific to CPU.\n\ 14385 For -mCPU and -no-mCPU, CPU must be one of:\n")); 14386 14387 first = 1; 14388 14389 show (stream, "3900", &column, &first); 14390 show (stream, "4010", &column, &first); 14391 show (stream, "4100", &column, &first); 14392 show (stream, "4650", &column, &first); 14393 fputc ('\n', stream); 14394 14395 fprintf (stream, _("\ 14396-mips16 generate mips16 instructions\n\ 14397-no-mips16 do not generate mips16 instructions\n")); 14398 fprintf (stream, _("\ 14399-mfix-vr4120 work around certain VR4120 errata\n\ 14400-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ 14401-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ 14402-O0 remove unneeded NOPs, do not swap branches\n\ 14403-O remove unneeded NOPs and swap branches\n\ 14404--[no-]construct-floats [dis]allow floating point values to be constructed\n\ 14405--trap, --no-break trap exception on div by 0 and mult overflow\n\ 14406--break, --no-trap break exception on div by 0 and mult overflow\n")); 14407#ifdef OBJ_ELF 14408 fprintf (stream, _("\ 14409-KPIC, -call_shared generate SVR4 position independent code\n\ 14410-non_shared do not generate position independent code\n\ 14411-xgot assume a 32 bit GOT\n\ 14412-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ 14413-mabi=ABI create ABI conformant object file for:\n")); 14414 14415 first = 1; 14416 14417 show (stream, "32", &column, &first); 14418 show (stream, "o64", &column, &first); 14419 show (stream, "n32", &column, &first); 14420 show (stream, "64", &column, &first); 14421 show (stream, "eabi", &column, &first); 14422 14423 fputc ('\n', stream); 14424 14425 fprintf (stream, _("\ 14426-32 create o32 ABI object file (default)\n\ 14427-n32 create n32 ABI object file\n\ 14428-64 create 64 ABI object file\n")); 14429#endif 14430} 14431 14432enum dwarf2_format 14433mips_dwarf2_format (void) 14434{ 14435 if (mips_abi == N64_ABI) 14436 { 14437#ifdef TE_IRIX 14438 return dwarf2_format_64bit_irix; 14439#else 14440 return dwarf2_format_64bit; 14441#endif 14442 } 14443 else 14444 return dwarf2_format_32bit; 14445} 14446 14447int 14448mips_dwarf2_addr_size (void) 14449{ 14450 if (mips_abi == N64_ABI) 14451 return 8; 14452 else 14453 return 4; 14454} 14455