tc-i386.h revision 77312
1/* tc-i386.h -- Header file for tc-i386.c 2 Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001 3 Free Software Foundation. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to the Free 19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 20 02111-1307, USA. */ 21 22 23/* $FreeBSD: head/contrib/binutils/gas/config/tc-i386.h 77312 2001-05-28 06:11:56Z obrien $ */ 24 25 26#ifndef TC_I386 27#define TC_I386 1 28 29#ifdef ANSI_PROTOTYPES 30struct fix; 31#endif 32 33#define TARGET_BYTES_BIG_ENDIAN 0 34 35#ifdef TE_LYNX 36#define TARGET_FORMAT "coff-i386-lynx" 37#endif 38 39#ifdef BFD_ASSEMBLER 40/* This is used to determine relocation types in tc-i386.c. The first 41 parameter is the current relocation type, the second one is the desired 42 type. The idea is that if the original type is already some kind of PIC 43 relocation, we leave it alone, otherwise we give it the desired type */ 44 45#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X) 46extern int tc_i386_fix_adjustable PARAMS ((struct fix *)); 47 48#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE) 49/* This arranges for gas/write.c to not apply a relocation if 50 tc_fix_adjustable() says it is not adjustable. 51 The "! symbol_used_in_reloc_p" test is there specifically to cover 52 the case of non-global symbols in linkonce sections. It's the 53 generally correct thing to do though; If a reloc is going to be 54 emitted against a symbol then we don't want to adjust the fixup by 55 applying the reloc during assembly. The reloc will be applied by 56 the linker during final link. */ 57#define TC_FIX_ADJUSTABLE(fixP) \ 58 (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP)) 59#endif 60 61/* This expression evaluates to false if the relocation is for a local object 62 for which we still want to do the relocation at runtime. True if we 63 are willing to perform this relocation while building the .o file. 64 This is only used for pcrel relocations, so GOTOFF does not need to be 65 checked here. I am not sure if some of the others are ever used with 66 pcrel, but it is easier to be safe than sorry. */ 67 68#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \ 69 ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \ 70 && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \ 71 && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \ 72 && ((FIX)->fx_addsy == NULL \ 73 || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \ 74 && ! S_IS_WEAK ((FIX)->fx_addsy) \ 75 && S_IS_DEFINED ((FIX)->fx_addsy) \ 76 && ! S_IS_COMMON ((FIX)->fx_addsy)))) 77 78#define TARGET_ARCH bfd_arch_i386 79#define TARGET_MACH (i386_mach ()) 80extern unsigned long i386_mach PARAMS ((void)); 81 82#ifdef TE_FreeBSD 83#define AOUT_TARGET_FORMAT "a.out-i386-freebsd" 84#endif 85#ifdef TE_NetBSD 86#define AOUT_TARGET_FORMAT "a.out-i386-netbsd" 87#endif 88#ifdef TE_386BSD 89#define AOUT_TARGET_FORMAT "a.out-i386-bsd" 90#endif 91#ifdef TE_LINUX 92#define AOUT_TARGET_FORMAT "a.out-i386-linux" 93#endif 94#ifdef TE_Mach 95#define AOUT_TARGET_FORMAT "a.out-mach3" 96#endif 97#ifdef TE_DYNIX 98#define AOUT_TARGET_FORMAT "a.out-i386-dynix" 99#endif 100#ifndef AOUT_TARGET_FORMAT 101#define AOUT_TARGET_FORMAT "a.out-i386" 102#endif 103 104#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 105 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 106extern const char *i386_target_format PARAMS ((void)); 107#define TARGET_FORMAT i386_target_format () 108#else 109#ifdef OBJ_ELF 110#define TARGET_FORMAT "elf32-i386" 111#endif 112#ifdef OBJ_AOUT 113#define TARGET_FORMAT AOUT_TARGET_FORMAT 114#endif 115#endif 116 117#else /* ! BFD_ASSEMBLER */ 118 119/* COFF STUFF */ 120 121#define COFF_MAGIC I386MAGIC 122#define BFD_ARCH bfd_arch_i386 123#define COFF_FLAGS F_AR32WR 124#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7) 125#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP) 126extern short tc_coff_fix2rtype PARAMS ((struct fix *)); 127#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag) 128extern int tc_coff_sizemachdep PARAMS ((fragS *frag)); 129 130#ifdef TE_GO32 131/* DJGPP now expects some sections to be 2**4 aligned. */ 132#define SUB_SEGMENT_ALIGN(SEG) \ 133 ((strcmp (obj_segment_name (SEG), ".text") == 0 \ 134 || strcmp (obj_segment_name (SEG), ".data") == 0 \ 135 || strcmp (obj_segment_name (SEG), ".bss") == 0 \ 136 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \ 137 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \ 138 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \ 139 ? 4 \ 140 : 2) 141#else 142#define SUB_SEGMENT_ALIGN(SEG) 2 143#endif 144 145#define TC_RVA_RELOC 7 146/* Need this for PIC relocations */ 147#define NEED_FX_R_TYPE 148 149#ifdef TE_386BSD 150/* The BSDI linker apparently rejects objects with a machine type of 151 M_386 (100). */ 152#define AOUT_MACHTYPE 0 153#else 154#define AOUT_MACHTYPE 100 155#endif 156 157#undef REVERSE_SORT_RELOCS 158 159#endif /* ! BFD_ASSEMBLER */ 160 161#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp) 162extern int tc_i386_force_relocation PARAMS ((struct fix *)); 163 164#ifdef BFD_ASSEMBLER 165#define NO_RELOC BFD_RELOC_NONE 166#else 167#define NO_RELOC 0 168#endif 169#define tc_coff_symbol_emit_hook(a) ; /* not used */ 170 171#ifndef BFD_ASSEMBLER 172#ifndef OBJ_AOUT 173#ifndef TE_PE 174#ifndef TE_GO32 175/* Local labels starts with .L */ 176#define LOCAL_LABEL(name) (name[0] == '.' \ 177 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.')) 178#endif 179#endif 180#endif 181#endif 182 183#define LOCAL_LABELS_FB 1 184 185#define tc_aout_pre_write_hook(x) {;} /* not used */ 186#define tc_crawl_symbol_chain(a) {;} /* not used */ 187#define tc_headers_hook(a) {;} /* not used */ 188 189extern const char extra_symbol_chars[]; 190#define tc_symbol_chars extra_symbol_chars 191 192#define MAX_OPERANDS 3 /* max operands per insn */ 193#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */ 194#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */ 195 196/* Prefixes will be emitted in the order defined below. 197 WAIT_PREFIX must be the first prefix since FWAIT is really is an 198 instruction, and so must come before any prefixes. */ 199#define WAIT_PREFIX 0 200#define LOCKREP_PREFIX 1 201#define ADDR_PREFIX 2 202#define DATA_PREFIX 3 203#define SEG_PREFIX 4 204#define REX_PREFIX 5 /* must come last. */ 205#define MAX_PREFIXES 6 /* max prefixes per opcode */ 206 207/* we define the syntax here (modulo base,index,scale syntax) */ 208#define REGISTER_PREFIX '%' 209#define IMMEDIATE_PREFIX '$' 210#define ABSOLUTE_PREFIX '*' 211 212#define TWO_BYTE_OPCODE_ESCAPE 0x0f 213#define NOP_OPCODE (char) 0x90 214 215/* register numbers */ 216#define EBP_REG_NUM 5 217#define ESP_REG_NUM 4 218 219/* modrm_byte.regmem for twobyte escape */ 220#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 221/* index_base_byte.index for no index register addressing */ 222#define NO_INDEX_REGISTER ESP_REG_NUM 223/* index_base_byte.base for no base register addressing */ 224#define NO_BASE_REGISTER EBP_REG_NUM 225#define NO_BASE_REGISTER_16 6 226 227/* these are the instruction mnemonic suffixes. */ 228#define WORD_MNEM_SUFFIX 'w' 229#define BYTE_MNEM_SUFFIX 'b' 230#define SHORT_MNEM_SUFFIX 's' 231#define LONG_MNEM_SUFFIX 'l' 232#define QWORD_MNEM_SUFFIX 'q' 233/* Intel Syntax */ 234#define LONG_DOUBLE_MNEM_SUFFIX 'x' 235 236/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 237#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 238#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 239 240#define END_OF_INSN '\0' 241 242/* Intel Syntax */ 243/* Values 0-4 map onto scale factor */ 244#define BYTE_PTR 0 245#define WORD_PTR 1 246#define DWORD_PTR 2 247#define QWORD_PTR 3 248#define XWORD_PTR 4 249#define SHORT 5 250#define OFFSET_FLAT 6 251#define FLAT 7 252#define NONE_FOUND 8 253 254typedef struct 255{ 256 /* instruction name sans width suffix ("mov" for movl insns) */ 257 char *name; 258 259 /* how many operands */ 260 unsigned int operands; 261 262 /* base_opcode is the fundamental opcode byte without optional 263 prefix(es). */ 264 unsigned int base_opcode; 265 266 /* extension_opcode is the 3 bit extension for group <n> insns. 267 This field is also used to store the 8-bit opcode suffix for the 268 AMD 3DNow! instructions. 269 If this template has no extension opcode (the usual case) use None */ 270 unsigned int extension_opcode; 271#define None 0xffff /* If no extension_opcode is possible. */ 272 273 /* cpu feature flags */ 274 unsigned int cpu_flags; 275#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */ 276#define Cpu186 0x2 /* i186 or better required */ 277#define Cpu286 0x4 /* i286 or better required */ 278#define Cpu386 0x8 /* i386 or better required */ 279#define Cpu486 0x10 /* i486 or better required */ 280#define Cpu586 0x20 /* i585 or better required */ 281#define Cpu686 0x40 /* i686 or better required */ 282#define CpuP4 0x80 /* Pentium4 or better required */ 283#define CpuK6 0x100 /* AMD K6 or better required*/ 284#define CpuAthlon 0x200 /* AMD Athlon or better required*/ 285#define CpuSledgehammer 0x400 /* Sledgehammer or better required */ 286#define CpuMMX 0x800 /* MMX support required */ 287#define CpuSSE 0x1000 /* Streaming SIMD extensions required */ 288#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */ 289#define Cpu3dnow 0x4000 /* 3dnow! support required */ 290#define CpuUnknown 0x8000 /* The CPU is unknown, be on the safe side. */ 291 292 /* These flags are set by gas depending on the flag_code. */ 293#define Cpu64 0x4000000 /* 64bit support required */ 294#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ 295 296 /* The default value for unknown CPUs - enable all features to avoid problems. */ 297#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon) 298 299 /* the bits in opcode_modifier are used to generate the final opcode from 300 the base_opcode. These bits also are used to detect alternate forms of 301 the same instruction */ 302 unsigned int opcode_modifier; 303 304 /* opcode_modifier bits: */ 305#define W 0x1 /* set if operands can be words or dwords 306 encoded the canonical way */ 307#define D 0x2 /* D = 0 if Reg --> Regmem; 308 D = 1 if Regmem --> Reg: MUST BE 0x2 */ 309#define Modrm 0x4 310#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */ 311#define ShortForm 0x10 /* register is in low 3 bits of opcode */ 312#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */ 313#define Jump 0x40 /* special case for jump insns. */ 314#define JumpDword 0x80 /* call and jump */ 315#define JumpByte 0x100 /* loop and jecxz */ 316#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */ 317#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */ 318#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */ 319#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */ 320#define Size16 0x2000 /* needs size prefix if in 32-bit mode */ 321#define Size32 0x4000 /* needs size prefix if in 16-bit mode */ 322#define Size64 0x8000 /* needs size prefix if in 16-bit mode */ 323#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */ 324#define DefaultSize 0x20000 /* default insn size depends on mode */ 325#define No_bSuf 0x40000 /* b suffix on instruction illegal */ 326#define No_wSuf 0x80000 /* w suffix on instruction illegal */ 327#define No_lSuf 0x100000 /* l suffix on instruction illegal */ 328#define No_sSuf 0x200000 /* s suffix on instruction illegal */ 329#define No_qSuf 0x400000 /* q suffix on instruction illegal */ 330#define No_xSuf 0x800000 /* x suffix on instruction illegal */ 331#define FWait 0x1000000 /* instruction needs FWAIT */ 332#define IsString 0x2000000 /* quick test for string instructions */ 333#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */ 334#define IsPrefix 0x8000000 /* opcode is a prefix */ 335#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */ 336#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */ 337#define Rex64 0x40000000 /* instruction require Rex64 prefix. */ 338#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */ 339 340 /* operand_types[i] describes the type of operand i. This is made 341 by OR'ing together all of the possible type masks. (e.g. 342 'operand_types[i] = Reg|Imm' specifies that operand i can be 343 either a register or an immediate operand. */ 344 unsigned int operand_types[3]; 345 346 /* operand_types[i] bits */ 347 /* register */ 348#define Reg8 0x1 /* 8 bit reg */ 349#define Reg16 0x2 /* 16 bit reg */ 350#define Reg32 0x4 /* 32 bit reg */ 351#define Reg64 0x8 /* 64 bit reg */ 352 /* immediate */ 353#define Imm8 0x10 /* 8 bit immediate */ 354#define Imm8S 0x20 /* 8 bit immediate sign extended */ 355#define Imm16 0x40 /* 16 bit immediate */ 356#define Imm32 0x80 /* 32 bit immediate */ 357#define Imm32S 0x100 /* 32 bit immediate sign extended */ 358#define Imm64 0x200 /* 64 bit immediate */ 359#define Imm1 0x400 /* 1 bit immediate */ 360 /* memory */ 361#define BaseIndex 0x800 362 /* Disp8,16,32 are used in different ways, depending on the 363 instruction. For jumps, they specify the size of the PC relative 364 displacement, for baseindex type instructions, they specify the 365 size of the offset relative to the base register, and for memory 366 offset instructions such as `mov 1234,%al' they specify the size of 367 the offset relative to the segment base. */ 368#define Disp8 0x1000 /* 8 bit displacement */ 369#define Disp16 0x2000 /* 16 bit displacement */ 370#define Disp32 0x4000 /* 32 bit displacement */ 371#define Disp32S 0x8000 /* 32 bit signed displacement */ 372#define Disp64 0x10000 /* 64 bit displacement */ 373 /* specials */ 374#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */ 375#define ShiftCount 0x40000 /* register to hold shift cound = cl */ 376#define Control 0x80000 /* Control register */ 377#define Debug 0x100000 /* Debug register */ 378#define Test 0x200000 /* Test register */ 379#define FloatReg 0x400000 /* Float register */ 380#define FloatAcc 0x800000 /* Float stack top %st(0) */ 381#define SReg2 0x1000000 /* 2 bit segment register */ 382#define SReg3 0x2000000 /* 3 bit segment register */ 383#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */ 384#define JumpAbsolute 0x8000000 385#define RegMMX 0x10000000 /* MMX register */ 386#define RegXMM 0x20000000 /* XMM registers in PIII */ 387#define EsSeg 0x40000000 /* String insn operand with fixed es segment */ 388 389 /* InvMem is for instructions with a modrm byte that only allow a 390 general register encoding in the i.tm.mode and i.tm.regmem fields, 391 eg. control reg moves. They really ought to support a memory form, 392 but don't, so we add an InvMem flag to the register operand to 393 indicate that it should be encoded in the i.tm.regmem field. */ 394#define InvMem 0x80000000 395 396#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ 397#define WordReg (Reg16|Reg32|Reg64) 398#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc) 399#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */ 400#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */ 401#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */ 402#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */ 403 /* The following aliases are defined because the opcode table 404 carefully specifies the allowed memory types for each instruction. 405 At the moment we can only tell a memory reference size by the 406 instruction suffix, so there's not much point in defining Mem8, 407 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use 408 the suffix directly to check memory operands. */ 409#define LLongMem AnyMem /* 64 bits (or more) */ 410#define LongMem AnyMem /* 32 bit memory ref */ 411#define ShortMem AnyMem /* 16 bit memory ref */ 412#define WordMem AnyMem /* 16 or 32 bit memory ref */ 413#define ByteMem AnyMem /* 8 bit memory ref */ 414} 415template; 416 417/* 418 'templates' is for grouping together 'template' structures for opcodes 419 of the same name. This is only used for storing the insns in the grand 420 ole hash table of insns. 421 The templates themselves start at START and range up to (but not including) 422 END. 423 */ 424typedef struct 425{ 426 const template *start; 427 const template *end; 428} 429templates; 430 431/* these are for register name --> number & type hash lookup */ 432typedef struct 433{ 434 char *reg_name; 435 unsigned int reg_type; 436 unsigned int reg_flags; 437#define RegRex 0x1 /* Extended register. */ 438#define RegRex64 0x2 /* Extended 8 bit register. */ 439 unsigned int reg_num; 440} 441reg_entry; 442 443typedef struct 444{ 445 char *seg_name; 446 unsigned int seg_prefix; 447} 448seg_entry; 449 450/* 386 operand encoding bytes: see 386 book for details of this. */ 451typedef struct 452{ 453 unsigned int regmem; /* codes register or memory operand */ 454 unsigned int reg; /* codes register operand (or extended opcode) */ 455 unsigned int mode; /* how to interpret regmem & reg */ 456} 457modrm_byte; 458 459/* x86-64 extension prefix. */ 460typedef struct 461 { 462 unsigned int mode64; 463 unsigned int extX; /* Used to extend modrm reg field. */ 464 unsigned int extY; /* Used to extend SIB index field. */ 465 unsigned int extZ; /* Used to extend modrm reg/mem, SIB base, modrm base fields. */ 466 unsigned int empty; /* Used to old-style byte registers to new style. */ 467 } 468rex_byte; 469 470/* 386 opcode byte to code indirect addressing. */ 471typedef struct 472{ 473 unsigned base; 474 unsigned index; 475 unsigned scale; 476} 477sib_byte; 478 479/* x86 arch names and features */ 480typedef struct 481{ 482 const char *name; /* arch name */ 483 unsigned int flags; /* cpu feature flags */ 484} 485arch_entry; 486 487/* The name of the global offset table generated by the compiler. Allow 488 this to be overridden if need be. */ 489#ifndef GLOBAL_OFFSET_TABLE_NAME 490#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" 491#endif 492 493#ifdef BFD_ASSEMBLER 494void i386_validate_fix PARAMS ((struct fix *)); 495#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP) 496#endif 497 498#endif /* TC_I386 */ 499 500#define md_operand(x) 501 502extern const struct relax_type md_relax_table[]; 503#define TC_GENERIC_RELAX_TABLE md_relax_table 504 505#define md_do_align(n, fill, len, max, around) \ 506if ((n) && !need_pass_2 \ 507 && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \ 508 && subseg_text_p (now_seg)) \ 509 { \ 510 frag_align_code ((n), (max)); \ 511 goto around; \ 512 } 513 514#define MAX_MEM_FOR_RS_ALIGN_CODE 15 515 516extern void i386_align_code PARAMS ((fragS *, int)); 517 518#define HANDLE_ALIGN(fragP) \ 519if (fragP->fr_type == rs_align_code) \ 520 i386_align_code (fragP, (fragP->fr_next->fr_address \ 521 - fragP->fr_address \ 522 - fragP->fr_fix)); 523 524/* call md_apply_fix3 with segment instead of md_apply_fix */ 525#define MD_APPLY_FIX3 526 527void i386_print_statistics PARAMS ((FILE *)); 528#define tc_print_statistics i386_print_statistics 529 530#define md_number_to_chars number_to_chars_littleendian 531 532#ifdef SCO_ELF 533#define tc_init_after_args() sco_id () 534extern void sco_id PARAMS ((void)); 535#endif 536 537#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ 538