1185743Ssam/*- 2185743Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185743Ssam * All rights reserved. 4185743Ssam * 5185743Ssam * Redistribution and use in source and binary forms, with or without 6185743Ssam * modification, are permitted provided that the following conditions 7185743Ssam * are met: 8185743Ssam * 1. Redistributions of source code must retain the above copyright 9185743Ssam * notice, this list of conditions and the following disclaimer, 10185743Ssam * without modification. 11185743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12185743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13185743Ssam * redistribution must be conditioned upon including a substantially 14185743Ssam * similar Disclaimer requirement for further binary redistribution. 15185743Ssam * 16185743Ssam * NO WARRANTY 17185743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18185743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19185743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20185743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21185743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22185743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23185743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24185743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25185743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26185743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27185743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28185743Ssam * 29185743Ssam * $FreeBSD: releng/10.3/tools/tools/ath/common/dumpregs_5211.c 196696 2009-08-31 13:23:55Z jhb $ 30185743Ssam */ 31185743Ssam#include "diag.h" 32185743Ssam 33185743Ssam#include "ah.h" 34185743Ssam#include "ah_internal.h" 35185743Ssam#include "ar5211/ar5211reg.h" 36189701Ssam#include "ar5211/ar5211phy.h" 37185743Ssam 38185743Ssam#include "dumpregs.h" 39185743Ssam 40185743Ssam#define N(a) (sizeof(a) / sizeof(a[0])) 41185743Ssam 42185743Ssamstatic struct dumpreg ar5211regs[] = { 43189701Ssam DEFBASICfmt(AR_CR, "CR", AR_CR_BITS), 44189701Ssam DEFBASIC(AR_RXDP, "RXDP"), 45189701Ssam DEFBASICfmt(AR_CFG, "CFG", AR_CFG_BITS), 46189701Ssam DEFBASICfmt(AR_IER, "IER", AR_IER_BITS), 47189701Ssam DEFBASIC(AR_RTSD0, "RTSD0"), 48189701Ssam DEFBASIC(AR_RTSD1, "RTSD1"), 49189701Ssam DEFBASICfmt(AR_TXCFG, "TXCFG", AR_TXCFG_BITS), 50189701Ssam DEFBASIC(AR_RXCFG, "RXCFG"), 51189701Ssam DEFBASIC(AR5211_JUMBO_LAST, "JLAST"), 52189701Ssam DEFBASIC(AR_MIBC, "MIBC"), 53189701Ssam DEFBASIC(AR_TOPS, "TOPS"), 54189701Ssam DEFBASIC(AR_RXNPTO, "RXNPTO"), 55189701Ssam DEFBASIC(AR_TXNPTO, "TXNPTO"), 56189701Ssam DEFBASIC(AR_RFGTO, "RFGTO"), 57189701Ssam DEFBASIC(AR_RFCNT, "RFCNT"), 58189701Ssam DEFBASIC(AR_MACMISC, "MISC"), 59189701Ssam DEFVOID(AR5311_QDCLKGATE, "AR5311_QDCLKGATE"), 60185743Ssam 61189701Ssam DEFINT(AR_ISR, "ISR"), 62189701Ssam DEFINT(AR_ISR_S0, "ISR_S0"), 63189701Ssam DEFINT(AR_ISR_S1, "ISR_S1"), 64189701Ssam DEFINT(AR_ISR_S2, "ISR_S2"), 65189701Ssam DEFINT(AR_ISR_S3, "ISR_S3"), 66189701Ssam DEFINT(AR_ISR_S4, "ISR_S4"), 67189701Ssam DEFINT(AR_IMR, "IMR"), 68189701Ssam DEFINT(AR_IMR_S0, "IMR_S0"), 69189701Ssam DEFINT(AR_IMR_S1, "IMR_S1"), 70189701Ssam DEFINT(AR_IMR_S2, "IMR_S2"), 71189701Ssam DEFINT(AR_IMR_S3, "IMR_S3"), 72189701Ssam DEFINT(AR_IMR_S4, "IMR_S4"), 73185743Ssam /* NB: don't read the RAC so we don't affect operation */ 74189701Ssam DEFVOID(AR_ISR_RAC, "ISR_RAC"), 75189701Ssam DEFINT(AR_ISR_S0_S, "ISR_S0_S"), 76189701Ssam DEFINT(AR_ISR_S1_S, "ISR_S1_S"), 77189701Ssam DEFINT(AR_ISR_S2_S, "ISR_S2_S"), 78189701Ssam DEFINT(AR_ISR_S3_S, "ISR_S3_S"), 79189701Ssam DEFINT(AR_ISR_S4_S, "ISR_S4_S"), 80185743Ssam 81189701Ssam DEFQCU(AR_Q0_TXDP, "Q0_TXDP"), 82189701Ssam DEFQCU(AR_Q1_TXDP, "Q1_TXDP"), 83189701Ssam DEFQCU(AR_Q2_TXDP, "Q2_TXDP"), 84189701Ssam DEFQCU(AR_Q3_TXDP, "Q3_TXDP"), 85189701Ssam DEFQCU(AR_Q4_TXDP, "Q4_TXDP"), 86189701Ssam DEFQCU(AR_Q5_TXDP, "Q5_TXDP"), 87189701Ssam DEFQCU(AR_Q6_TXDP, "Q6_TXDP"), 88189701Ssam DEFQCU(AR_Q7_TXDP, "Q7_TXDP"), 89189701Ssam DEFQCU(AR_Q8_TXDP, "Q8_TXDP"), 90189701Ssam DEFQCU(AR_Q9_TXDP, "Q9_TXDP"), 91185743Ssam 92189701Ssam DEFQCU(AR_Q_TXE, "Q_TXE"), 93189701Ssam DEFQCU(AR_Q_TXD, "Q_TXD"), 94185743Ssam 95189701Ssam DEFQCU(AR_Q0_CBRCFG, "Q0_CBR"), 96189701Ssam DEFQCU(AR_Q1_CBRCFG, "Q1_CBR"), 97189701Ssam DEFQCU(AR_Q2_CBRCFG, "Q2_CBR"), 98189701Ssam DEFQCU(AR_Q3_CBRCFG, "Q3_CBR"), 99189701Ssam DEFQCU(AR_Q4_CBRCFG, "Q4_CBR"), 100189701Ssam DEFQCU(AR_Q5_CBRCFG, "Q5_CBR"), 101189701Ssam DEFQCU(AR_Q6_CBRCFG, "Q6_CBR"), 102189701Ssam DEFQCU(AR_Q7_CBRCFG, "Q7_CBR"), 103189701Ssam DEFQCU(AR_Q8_CBRCFG, "Q8_CBR"), 104189701Ssam DEFQCU(AR_Q9_CBRCFG, "Q9_CBR"), 105185743Ssam 106189701Ssam DEFQCU(AR_Q0_RDYTIMECFG, "Q0_RDYT"), 107189701Ssam DEFQCU(AR_Q1_RDYTIMECFG, "Q1_RDYT"), 108189701Ssam DEFQCU(AR_Q2_RDYTIMECFG, "Q2_RDYT"), 109189701Ssam DEFQCU(AR_Q3_RDYTIMECFG, "Q3_RDYT"), 110189701Ssam DEFQCU(AR_Q4_RDYTIMECFG, "Q4_RDYT"), 111189701Ssam DEFQCU(AR_Q5_RDYTIMECFG, "Q5_RDYT"), 112189701Ssam DEFQCU(AR_Q6_RDYTIMECFG, "Q6_RDYT"), 113189701Ssam DEFQCU(AR_Q7_RDYTIMECFG, "Q7_RDYT"), 114189701Ssam DEFQCU(AR_Q8_RDYTIMECFG, "Q8_RDYT"), 115189701Ssam DEFQCU(AR_Q9_RDYTIMECFG, "Q9_RDYT"), 116185743Ssam 117189701Ssam DEFQCU(AR_Q_ONESHOTARM_SC, "Q_ONESHOTARM_SC"), 118189701Ssam DEFQCU(AR_Q_ONESHOTARM_CC, "Q_ONESHOTARM_CC"), 119185743Ssam 120189701Ssam DEFQCU(AR_Q0_MISC, "Q0_MISC"), 121189701Ssam DEFQCU(AR_Q1_MISC, "Q1_MISC"), 122189701Ssam DEFQCU(AR_Q2_MISC, "Q2_MISC"), 123189701Ssam DEFQCU(AR_Q3_MISC, "Q3_MISC"), 124189701Ssam DEFQCU(AR_Q4_MISC, "Q4_MISC"), 125189701Ssam DEFQCU(AR_Q5_MISC, "Q5_MISC"), 126189701Ssam DEFQCU(AR_Q6_MISC, "Q6_MISC"), 127189701Ssam DEFQCU(AR_Q7_MISC, "Q7_MISC"), 128189701Ssam DEFQCU(AR_Q8_MISC, "Q8_MISC"), 129189701Ssam DEFQCU(AR_Q9_MISC, "Q9_MISC"), 130185743Ssam 131189701Ssam DEFQCU(AR_Q0_STS, "Q0_STS"), 132189701Ssam DEFQCU(AR_Q1_STS, "Q1_STS"), 133189701Ssam DEFQCU(AR_Q2_STS, "Q2_STS"), 134189701Ssam DEFQCU(AR_Q3_STS, "Q3_STS"), 135189701Ssam DEFQCU(AR_Q4_STS, "Q4_STS"), 136189701Ssam DEFQCU(AR_Q5_STS, "Q5_STS"), 137189701Ssam DEFQCU(AR_Q6_STS, "Q6_STS"), 138189701Ssam DEFQCU(AR_Q7_STS, "Q7_STS"), 139189701Ssam DEFQCU(AR_Q8_STS, "Q8_STS"), 140189701Ssam DEFQCU(AR_Q9_STS, "Q9_STS"), 141185743Ssam 142189701Ssam DEFQCU(AR_Q_RDYTIMESHDN, "Q_RDYTIMSHD"), 143185743Ssam 144189701Ssam DEFQCU(AR_D0_QCUMASK, "D0_MASK"), 145189701Ssam DEFQCU(AR_D1_QCUMASK, "D1_MASK"), 146189701Ssam DEFQCU(AR_D2_QCUMASK, "D2_MASK"), 147189701Ssam DEFQCU(AR_D3_QCUMASK, "D3_MASK"), 148189701Ssam DEFQCU(AR_D4_QCUMASK, "D4_MASK"), 149189701Ssam DEFQCU(AR_D5_QCUMASK, "D5_MASK"), 150189701Ssam DEFQCU(AR_D6_QCUMASK, "D6_MASK"), 151189701Ssam DEFQCU(AR_D7_QCUMASK, "D7_MASK"), 152189701Ssam DEFQCU(AR_D8_QCUMASK, "D8_MASK"), 153189701Ssam DEFQCU(AR_D9_QCUMASK, "D9_MASK"), 154185743Ssam 155189701Ssam DEFDCU(AR_D0_LCL_IFS, "D0_IFS"), 156189701Ssam DEFDCU(AR_D1_LCL_IFS, "D1_IFS"), 157189701Ssam DEFDCU(AR_D2_LCL_IFS, "D2_IFS"), 158189701Ssam DEFDCU(AR_D3_LCL_IFS, "D3_IFS"), 159189701Ssam DEFDCU(AR_D4_LCL_IFS, "D4_IFS"), 160189701Ssam DEFDCU(AR_D5_LCL_IFS, "D5_IFS"), 161189701Ssam DEFDCU(AR_D6_LCL_IFS, "D6_IFS"), 162189701Ssam DEFDCU(AR_D7_LCL_IFS, "D7_IFS"), 163189701Ssam DEFDCU(AR_D8_LCL_IFS, "D8_IFS"), 164189701Ssam DEFDCU(AR_D9_LCL_IFS, "D9_IFS"), 165185743Ssam 166189701Ssam DEFDCU(AR_D0_RETRY_LIMIT, "D0_RTRY"), 167189701Ssam DEFDCU(AR_D1_RETRY_LIMIT, "D1_RTRY"), 168189701Ssam DEFDCU(AR_D2_RETRY_LIMIT, "D2_RTRY"), 169189701Ssam DEFDCU(AR_D3_RETRY_LIMIT, "D3_RTRY"), 170189701Ssam DEFDCU(AR_D4_RETRY_LIMIT, "D4_RTRY"), 171189701Ssam DEFDCU(AR_D5_RETRY_LIMIT, "D5_RTRY"), 172189701Ssam DEFDCU(AR_D6_RETRY_LIMIT, "D6_RTRY"), 173189701Ssam DEFDCU(AR_D7_RETRY_LIMIT, "D7_RTRY"), 174189701Ssam DEFDCU(AR_D8_RETRY_LIMIT, "D8_RTRY"), 175189701Ssam DEFDCU(AR_D9_RETRY_LIMIT, "D9_RTRY"), 176185743Ssam 177189701Ssam DEFDCU(AR_D0_CHNTIME, "D0_CHNT"), 178189701Ssam DEFDCU(AR_D1_CHNTIME, "D1_CHNT"), 179189701Ssam DEFDCU(AR_D2_CHNTIME, "D2_CHNT"), 180189701Ssam DEFDCU(AR_D3_CHNTIME, "D3_CHNT"), 181189701Ssam DEFDCU(AR_D4_CHNTIME, "D4_CHNT"), 182189701Ssam DEFDCU(AR_D5_CHNTIME, "D5_CHNT"), 183189701Ssam DEFDCU(AR_D6_CHNTIME, "D6_CHNT"), 184189701Ssam DEFDCU(AR_D7_CHNTIME, "D7_CHNT"), 185189701Ssam DEFDCU(AR_D8_CHNTIME, "D8_CHNT"), 186189701Ssam DEFDCU(AR_D9_CHNTIME, "D9_CHNT"), 187185743Ssam 188189701Ssam DEFDCU(AR_D0_MISC, "D0_MISC"), 189189701Ssam DEFDCU(AR_D1_MISC, "D1_MISC"), 190189701Ssam DEFDCU(AR_D2_MISC, "D2_MISC"), 191189701Ssam DEFDCU(AR_D3_MISC, "D3_MISC"), 192189701Ssam DEFDCU(AR_D4_MISC, "D4_MISC"), 193189701Ssam DEFDCU(AR_D5_MISC, "D5_MISC"), 194189701Ssam DEFDCU(AR_D6_MISC, "D6_MISC"), 195189701Ssam DEFDCU(AR_D7_MISC, "D7_MISC"), 196189701Ssam DEFDCU(AR_D8_MISC, "D8_MISC"), 197189701Ssam DEFDCU(AR_D9_MISC, "D9_MISC"), 198185743Ssam 199189701Ssam DEFDCU(AR_D0_SEQNUM, "D0_SEQ"), 200189701Ssam DEFDCU(AR_D1_SEQNUM, "D1_SEQ"), 201189701Ssam DEFDCU(AR_D2_SEQNUM, "D2_SEQ"), 202189701Ssam DEFDCU(AR_D3_SEQNUM, "D3_SEQ"), 203189701Ssam DEFDCU(AR_D4_SEQNUM, "D4_SEQ"), 204189701Ssam DEFDCU(AR_D5_SEQNUM, "D5_SEQ"), 205189701Ssam DEFDCU(AR_D6_SEQNUM, "D6_SEQ"), 206189701Ssam DEFDCU(AR_D7_SEQNUM, "D7_SEQ"), 207189701Ssam DEFDCU(AR_D8_SEQNUM, "D8_SEQ"), 208189701Ssam DEFDCU(AR_D9_SEQNUM, "D9_SEQ"), 209185743Ssam 210189701Ssam DEFBASIC(AR_D_GBL_IFS_SIFS, "D_SIFS"), 211189701Ssam DEFBASIC(AR_D_GBL_IFS_SLOT, "D_SLOT"), 212189701Ssam DEFBASIC(AR_D_GBL_IFS_EIFS, "D_EIFS"), 213189701Ssam DEFBASIC(AR_D_GBL_IFS_MISC, "D_MISC"), 214189701Ssam DEFBASIC(AR_D_FPCTL, "D_FPCTL"), 215189701Ssam DEFBASIC(AR_D_TXPSE, "D_TXPSE"), 216189701Ssam DEFVOID(AR_D_TXBLK_CMD, "D_CMD"), 217185743Ssam#if 0 218189701Ssam DEFVOID(AR_D_TXBLK_DATA, "D_DATA"), 219185743Ssam#endif 220189701Ssam DEFVOID(AR_D_TXBLK_CLR, "D_CLR"), 221189701Ssam DEFVOID(AR_D_TXBLK_SET, "D_SET"), 222189701Ssam DEFBASICfmt(AR_RC, "RC", AR_RC_BITS), 223189701Ssam DEFBASICfmt(AR_SCR, "SCR", AR_SCR_BITS), 224189701Ssam DEFBASICfmt(AR_INTPEND, "INTPEND", AR_INTPEND_BITS), 225189701Ssam DEFBASIC(AR_SFR, "SFR"), 226189701Ssam DEFBASICfmt(AR_PCICFG, "PCICFG", AR_PCICFG_BITS), 227189701Ssam DEFBASIC(AR_GPIOCR, "GPIOCR"), 228189701Ssam DEFBASIC(AR_GPIODO, "GPIODO"), 229189701Ssam DEFBASIC(AR_GPIODI, "GPIODI"), 230189701Ssam DEFBASIC(AR_SREV, "SREV"), 231189701Ssam DEFVOID(AR_EEPROM_ADDR, "EEADDR"), 232189701Ssam DEFVOID(AR_EEPROM_DATA, "EEDATA"), 233189701Ssam DEFVOID(AR_EEPROM_CMD, "EECMD"), 234189701Ssam DEFVOID(AR_EEPROM_STS, "EESTS"), 235189701Ssam DEFVOID(AR_EEPROM_CFG, "EECFG"), 236189701Ssam DEFBASIC(AR_STA_ID0, "STA_ID0"), 237189701Ssam DEFBASICfmt(AR_STA_ID1, "STA_ID1", AR_STA_ID1_BITS), 238189701Ssam DEFBASIC(AR_BSS_ID0, "BSS_ID0"), 239189701Ssam DEFBASIC(AR_BSS_ID1, "BSS_ID1"), 240189701Ssam DEFBASIC(AR_SLOT_TIME, "SLOTTIME"), 241189701Ssam DEFBASIC(AR_TIME_OUT, "TIME_OUT"), 242189701Ssam DEFBASIC(AR_RSSI_THR, "RSSI_THR"), 243189701Ssam DEFBASIC(AR_USEC, "USEC"), 244189701Ssam DEFBASICfmt(AR_BEACON, "BEACON", AR_BEACON_BITS), 245189701Ssam DEFBASIC(AR_CFP_PERIOD, "CFP_PER"), 246189701Ssam DEFBASIC(AR_TIMER0, "TIMER0"), 247189701Ssam DEFBASIC(AR_TIMER1, "TIMER1"), 248189701Ssam DEFBASIC(AR_TIMER2, "TIMER2"), 249189701Ssam DEFBASIC(AR_TIMER3, "TIMER3"), 250189701Ssam DEFBASIC(AR_CFP_DUR, "CFP_DUR"), 251189701Ssam DEFBASICfmt(AR_RX_FILTER, "RXFILTER", AR_RX_FILTER_BITS), 252189701Ssam DEFBASIC(AR_MCAST_FIL0, "MCAST_0"), 253189701Ssam DEFBASIC(AR_MCAST_FIL1, "MCAST_1"), 254189701Ssam DEFBASICfmt(AR_DIAG_SW, "DIAG_SW", AR_DIAG_SW_BITS), 255189701Ssam DEFBASIC(AR_TSF_L32, "TSF_L32"), 256189701Ssam DEFBASIC(AR_TSF_U32, "TSF_U32"), 257189701Ssam DEFBASIC(AR_TST_ADDAC, "TST_ADAC"), 258189701Ssam DEFBASIC(AR_DEF_ANTENNA, "DEF_ANT"), 259185743Ssam 260189701Ssam DEFBASIC(AR_LAST_TSTP, "LAST_TST"), 261189701Ssam DEFBASIC(AR_NAV, "NAV"), 262189701Ssam DEFBASIC(AR_RTS_OK, "RTS_OK"), 263189701Ssam DEFBASIC(AR_RTS_FAIL, "RTS_FAIL"), 264189701Ssam DEFBASIC(AR_ACK_FAIL, "ACK_FAIL"), 265189701Ssam DEFBASIC(AR_FCS_FAIL, "FCS_FAIL"), 266189701Ssam DEFBASIC(AR_BEACON_CNT, "BEAC_CNT"), 267189701Ssam 268189701Ssam DEFVOID(AR_PHY_TURBO, "PHY_TURBO"), 269189701Ssam DEFVOID(AR_PHY_CHIP_ID, "PHY_CHIP_ID"), 270189701Ssam DEFVOID(AR_PHY_ACTIVE, "PHY_ACTIVE"), 271189701Ssam DEFVOID(AR_PHY_AGC_CONTROL, "PHY_AGC_CONTROL"), 272189701Ssam DEFVOID(AR_PHY_PLL_CTL, "PHY_PLL_CTL"), 273189701Ssam DEFVOID(AR_PHY_RX_DELAY, "PHY_RX_DELAY"), 274189701Ssam DEFVOID(AR_PHY_TIMING_CTRL4,"PHY_TIMING_CTRL4"), 275189701Ssam DEFVOID(AR_PHY_RADAR_0, "PHY_RADAR_0"), 276189701Ssam DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_I,"PHY_IQCAL_RES_PWR_MEAS_I"), 277189701Ssam DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_Q,"PHY_IQCAL_RES_PWR_MEAS_Q"), 278189701Ssam DEFVOID(AR_PHY_IQCAL_RES_IQ_CORR_MEAS,"PHY_IQCAL_RES_IQ_CORR_MEAS"), 279189701Ssam DEFVOID(AR_PHY_CURRENT_RSSI,"PHY_CURRENT_RSSI"), 280189701Ssam DEFVOID(AR5211_PHY_MODE, "PHY_MODE"), 281185743Ssam}; 282185743Ssam 283185743Ssamstatic __constructor void 284185743Ssamar5211_ctor(void) 285185743Ssam{ 286185743Ssam#define MAC5211 SREV(2,0), SREV(4,5) 287185743Ssam register_regs(ar5211regs, N(ar5211regs), MAC5211, PHYANY); 288185743Ssam register_keycache(128, MAC5211, PHYANY); 289185743Ssam 290185743Ssam register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5211, PHYANY); 291185743Ssam register_range(0x9900, 0x995c, DUMP_BASEBAND, MAC5211, PHYANY); 292185743Ssam register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5211, PHYANY); 293185743Ssam} 294