xen.h revision 181624
1181624Skmacy/******************************************************************************
2181624Skmacy * arch-x86/xen.h
3181624Skmacy *
4181624Skmacy * Guest OS interface to x86 Xen.
5181624Skmacy *
6181624Skmacy * Permission is hereby granted, free of charge, to any person obtaining a copy
7181624Skmacy * of this software and associated documentation files (the "Software"), to
8181624Skmacy * deal in the Software without restriction, including without limitation the
9181624Skmacy * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10181624Skmacy * sell copies of the Software, and to permit persons to whom the Software is
11181624Skmacy * furnished to do so, subject to the following conditions:
12181624Skmacy *
13181624Skmacy * The above copyright notice and this permission notice shall be included in
14181624Skmacy * all copies or substantial portions of the Software.
15181624Skmacy *
16181624Skmacy * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17181624Skmacy * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18181624Skmacy * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19181624Skmacy * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20181624Skmacy * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21181624Skmacy * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22181624Skmacy * DEALINGS IN THE SOFTWARE.
23181624Skmacy *
24181624Skmacy * Copyright (c) 2004-2006, K A Fraser
25181624Skmacy */
26181624Skmacy
27181624Skmacy#ifndef __XEN_PUBLIC_ARCH_X86_XEN_H__
28181624Skmacy#define __XEN_PUBLIC_ARCH_X86_XEN_H__
29181624Skmacy
30181624Skmacy#if defined(__i386__)
31181624Skmacy#include <xen/interface/arch-x86/xen-x86_32.h>
32181624Skmacy#elif defined(__x86_64__)
33181624Skmacy#include "xen-x86_64.h"
34181624Skmacy#endif
35181624Skmacy
36181624Skmacy#ifndef __ASSEMBLY__
37181624Skmacy/* Guest handles for primitive C types. */
38181624Skmacy__DEFINE_XEN_GUEST_HANDLE(uchar, unsigned char);
39181624Skmacy__DEFINE_XEN_GUEST_HANDLE(uint,  unsigned int);
40181624Skmacy__DEFINE_XEN_GUEST_HANDLE(ulong, unsigned long);
41181624Skmacy#if 0
42181624SkmacyDEFINE_XEN_GUEST_HANDLE(char);
43181624SkmacyDEFINE_XEN_GUEST_HANDLE(int);
44181624SkmacyDEFINE_XEN_GUEST_HANDLE(long);
45181624SkmacyDEFINE_XEN_GUEST_HANDLE(void);
46181624Skmacy#endif
47181624Skmacytypedef unsigned long xen_pfn_t;
48181624SkmacyDEFINE_XEN_GUEST_HANDLE(xen_pfn_t);
49181624Skmacy#define PRI_xen_pfn "lx"
50181624Skmacy#endif
51181624Skmacy
52181624Skmacy/*
53181624Skmacy * SEGMENT DESCRIPTOR TABLES
54181624Skmacy */
55181624Skmacy/*
56181624Skmacy * A number of GDT entries are reserved by Xen. These are not situated at the
57181624Skmacy * start of the GDT because some stupid OSes export hard-coded selector values
58181624Skmacy * in their ABI. These hard-coded values are always near the start of the GDT,
59181624Skmacy * so Xen places itself out of the way, at the far end of the GDT.
60181624Skmacy */
61181624Skmacy#define FIRST_RESERVED_GDT_PAGE  14
62181624Skmacy#define FIRST_RESERVED_GDT_BYTE  (FIRST_RESERVED_GDT_PAGE * 4096)
63181624Skmacy#define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8)
64181624Skmacy
65181624Skmacy/* Maximum number of virtual CPUs in multi-processor guests. */
66181624Skmacy#define MAX_VIRT_CPUS 32
67181624Skmacy
68181624Skmacy#ifndef __ASSEMBLY__
69181624Skmacy
70181624Skmacytypedef unsigned long xen_ulong_t;
71181624Skmacy
72181624Skmacy/*
73181624Skmacy * Send an array of these to HYPERVISOR_set_trap_table().
74181624Skmacy * The privilege level specifies which modes may enter a trap via a software
75181624Skmacy * interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate
76181624Skmacy * privilege levels as follows:
77181624Skmacy *  Level == 0: Noone may enter
78181624Skmacy *  Level == 1: Kernel may enter
79181624Skmacy *  Level == 2: Kernel may enter
80181624Skmacy *  Level == 3: Everyone may enter
81181624Skmacy */
82181624Skmacy#define TI_GET_DPL(_ti)      ((_ti)->flags & 3)
83181624Skmacy#define TI_GET_IF(_ti)       ((_ti)->flags & 4)
84181624Skmacy#define TI_SET_DPL(_ti,_dpl) ((_ti)->flags |= (_dpl))
85181624Skmacy#define TI_SET_IF(_ti,_if)   ((_ti)->flags |= ((!!(_if))<<2))
86181624Skmacystruct trap_info {
87181624Skmacy    uint8_t       vector;  /* exception vector                              */
88181624Skmacy    uint8_t       flags;   /* 0-3: privilege level; 4: clear event enable?  */
89181624Skmacy    uint16_t      cs;      /* code selector                                 */
90181624Skmacy    unsigned long address; /* code offset                                   */
91181624Skmacy};
92181624Skmacytypedef struct trap_info trap_info_t;
93181624SkmacyDEFINE_XEN_GUEST_HANDLE(trap_info_t);
94181624Skmacy
95181624Skmacytypedef uint64_t tsc_timestamp_t; /* RDTSC timestamp */
96181624Skmacy
97181624Skmacy/*
98181624Skmacy * The following is all CPU context. Note that the fpu_ctxt block is filled
99181624Skmacy * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
100181624Skmacy */
101181624Skmacystruct vcpu_guest_context {
102181624Skmacy    /* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */
103181624Skmacy    struct { char x[512]; } fpu_ctxt;       /* User-level FPU registers     */
104181624Skmacy#define VGCF_I387_VALID                (1<<0)
105181624Skmacy#define VGCF_IN_KERNEL                 (1<<2)
106181624Skmacy#define _VGCF_i387_valid               0
107181624Skmacy#define VGCF_i387_valid                (1<<_VGCF_i387_valid)
108181624Skmacy#define _VGCF_in_kernel                2
109181624Skmacy#define VGCF_in_kernel                 (1<<_VGCF_in_kernel)
110181624Skmacy#define _VGCF_failsafe_disables_events 3
111181624Skmacy#define VGCF_failsafe_disables_events  (1<<_VGCF_failsafe_disables_events)
112181624Skmacy#define _VGCF_syscall_disables_events  4
113181624Skmacy#define VGCF_syscall_disables_events   (1<<_VGCF_syscall_disables_events)
114181624Skmacy#define _VGCF_online                   5
115181624Skmacy#define VGCF_online                    (1<<_VGCF_online)
116181624Skmacy    unsigned long flags;                    /* VGCF_* flags                 */
117181624Skmacy    struct cpu_user_regs user_regs;         /* User-level CPU registers     */
118181624Skmacy    struct trap_info trap_ctxt[256];        /* Virtual IDT                  */
119181624Skmacy    unsigned long ldt_base, ldt_ents;       /* LDT (linear address, # ents) */
120181624Skmacy    unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
121181624Skmacy    unsigned long kernel_ss, kernel_sp;     /* Virtual TSS (only SS1/SP1)   */
122181624Skmacy    /* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */
123181624Skmacy    unsigned long ctrlreg[8];               /* CR0-CR7 (control registers)  */
124181624Skmacy    unsigned long debugreg[8];              /* DB0-DB7 (debug registers)    */
125181624Skmacy#ifdef __i386__
126181624Skmacy    unsigned long event_callback_cs;        /* CS:EIP of event callback     */
127181624Skmacy    unsigned long event_callback_eip;
128181624Skmacy    unsigned long failsafe_callback_cs;     /* CS:EIP of failsafe callback  */
129181624Skmacy    unsigned long failsafe_callback_eip;
130181624Skmacy#else
131181624Skmacy    unsigned long event_callback_eip;
132181624Skmacy    unsigned long failsafe_callback_eip;
133181624Skmacy#ifdef __XEN__
134181624Skmacy    union {
135181624Skmacy        unsigned long syscall_callback_eip;
136181624Skmacy        struct {
137181624Skmacy            unsigned int event_callback_cs;    /* compat CS of event cb     */
138181624Skmacy            unsigned int failsafe_callback_cs; /* compat CS of failsafe cb  */
139181624Skmacy        };
140181624Skmacy    } u;
141181624Skmacy#else
142181624Skmacy    unsigned long syscall_callback_eip;
143181624Skmacy#endif
144181624Skmacy#endif
145181624Skmacy    unsigned long vm_assist;                /* VMASST_TYPE_* bitmap */
146181624Skmacy#ifdef __x86_64__
147181624Skmacy    /* Segment base addresses. */
148181624Skmacy    uint64_t      fs_base;
149181624Skmacy    uint64_t      gs_base_kernel;
150181624Skmacy    uint64_t      gs_base_user;
151181624Skmacy#endif
152181624Skmacy};
153181624Skmacytypedef struct vcpu_guest_context vcpu_guest_context_t;
154181624SkmacyDEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
155181624Skmacy
156181624Skmacystruct arch_shared_info {
157181624Skmacy    unsigned long max_pfn;                  /* max pfn that appears in table */
158181624Skmacy    /* Frame containing list of mfns containing list of mfns containing p2m. */
159181624Skmacy    xen_pfn_t     pfn_to_mfn_frame_list_list;
160181624Skmacy    unsigned long nmi_reason;
161181624Skmacy    uint64_t pad[32];
162181624Skmacy};
163181624Skmacytypedef struct arch_shared_info arch_shared_info_t;
164181624Skmacy
165181624Skmacy#endif /* !__ASSEMBLY__ */
166181624Skmacy
167181624Skmacy/*
168181624Skmacy * Prefix forces emulation of some non-trapping instructions.
169181624Skmacy * Currently only CPUID.
170181624Skmacy */
171181624Skmacy#ifdef __ASSEMBLY__
172181624Skmacy#define XEN_EMULATE_PREFIX .byte 0x0f,0x0b,0x78,0x65,0x6e ;
173181624Skmacy#define XEN_CPUID          XEN_EMULATE_PREFIX cpuid
174181624Skmacy#else
175181624Skmacy#define XEN_EMULATE_PREFIX ".byte 0x0f,0x0b,0x78,0x65,0x6e ; "
176181624Skmacy#define XEN_CPUID          XEN_EMULATE_PREFIX "cpuid"
177181624Skmacy#endif
178181624Skmacy
179181624Skmacy#endif /* __XEN_PUBLIC_ARCH_X86_XEN_H__ */
180181624Skmacy
181181624Skmacy/*
182181624Skmacy * Local variables:
183181624Skmacy * mode: C
184181624Skmacy * c-set-style: "BSD"
185181624Skmacy * c-basic-offset: 4
186181624Skmacy * tab-width: 4
187181624Skmacy * indent-tabs-mode: nil
188181624Skmacy * End:
189181624Skmacy */
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