1128928Sjhb/*- 2128928Sjhb * Copyright (c) 2004 John Baldwin <jhb@FreeBSD.org> 3128928Sjhb * All rights reserved. 4128928Sjhb * 5128928Sjhb * Redistribution and use in source and binary forms, with or without 6128928Sjhb * modification, are permitted provided that the following conditions 7128928Sjhb * are met: 8128928Sjhb * 1. Redistributions of source code must retain the above copyright 9128928Sjhb * notice, this list of conditions and the following disclaimer. 10128928Sjhb * 2. Redistributions in binary form must reproduce the above copyright 11128928Sjhb * notice, this list of conditions and the following disclaimer in the 12128928Sjhb * documentation and/or other materials provided with the distribution. 13128928Sjhb * 14128928Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15128928Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16128928Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17128928Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18128928Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19128928Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20128928Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21128928Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22128928Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23128928Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24128928Sjhb * SUCH DAMAGE. 25128928Sjhb */ 26128928Sjhb 27128928Sjhb#include <sys/cdefs.h> 28128928Sjhb__FBSDID("$FreeBSD: releng/10.3/sys/x86/isa/elcr.c 262192 2014-02-18 20:27:17Z jhb $"); 29128928Sjhb 30128928Sjhb/* 31128928Sjhb * The ELCR is a register that controls the trigger mode and polarity of 32128928Sjhb * EISA and ISA interrupts. In FreeBSD 3.x and 4.x, the ELCR was only 33128928Sjhb * consulted for determining the appropriate trigger mode of EISA 34128928Sjhb * interrupts when using an APIC. However, it seems that almost all 35128928Sjhb * systems that include PCI also include an ELCR that manages the ISA 36128928Sjhb * IRQs 0 through 15. Thus, we check for the presence of an ELCR on 37128928Sjhb * every machine by checking to see if the values found at bootup are 38128928Sjhb * sane. Note that the polarity of ISA and EISA IRQs are linked to the 39128928Sjhb * trigger mode. All edge triggered IRQs use active-hi polarity, and 40128928Sjhb * all level triggered interrupts use active-lo polarity. 41128928Sjhb * 42128928Sjhb * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0 43128928Sjhb * controls IRQ 0, bit 1 controls IRQ 1, etc. If the bit is zero, the 44128928Sjhb * associated IRQ is edge triggered. If the bit is one, the IRQ is 45128928Sjhb * level triggered. 46128928Sjhb */ 47128928Sjhb 48128928Sjhb#include <sys/param.h> 49128928Sjhb#include <sys/bus.h> 50128928Sjhb#include <sys/systm.h> 51128928Sjhb#include <machine/intr_machdep.h> 52128928Sjhb 53128928Sjhb#define ELCR_PORT 0x4d0 54128928Sjhb#define ELCR_MASK(irq) (1 << (irq)) 55128928Sjhb 56128928Sjhbstatic int elcr_status; 57140451Sjhbint elcr_found; 58128928Sjhb 59128928Sjhb/* 60128928Sjhb * Check to see if we have what looks like a valid ELCR. We do this by 61128928Sjhb * verifying that IRQs 0, 1, 2, and 13 are all edge triggered. 62128928Sjhb */ 63128928Sjhbint 64128928Sjhbelcr_probe(void) 65128928Sjhb{ 66128928Sjhb int i; 67128928Sjhb 68128928Sjhb elcr_status = inb(ELCR_PORT) | inb(ELCR_PORT + 1) << 8; 69128928Sjhb if ((elcr_status & (ELCR_MASK(0) | ELCR_MASK(1) | ELCR_MASK(2) | 70128928Sjhb ELCR_MASK(8) | ELCR_MASK(13))) != 0) 71128928Sjhb return (ENXIO); 72128928Sjhb if (bootverbose) { 73128928Sjhb printf("ELCR Found. ISA IRQs programmed as:\n"); 74128928Sjhb for (i = 0; i < 16; i++) 75128928Sjhb printf(" %2d", i); 76128928Sjhb printf("\n"); 77128928Sjhb for (i = 0; i < 16; i++) 78128928Sjhb if (elcr_status & ELCR_MASK(i)) 79128928Sjhb printf(" L"); 80128928Sjhb else 81128928Sjhb printf(" E"); 82128928Sjhb printf("\n"); 83128928Sjhb } 84241885Seadler if (resource_disabled("elcr", 0)) 85241885Seadler return (ENXIO); 86128928Sjhb elcr_found = 1; 87128928Sjhb return (0); 88128928Sjhb} 89128928Sjhb 90128928Sjhb/* 91128928Sjhb * Returns 1 for level trigger, 0 for edge. 92128928Sjhb */ 93128928Sjhbenum intr_trigger 94128928Sjhbelcr_read_trigger(u_int irq) 95128928Sjhb{ 96128928Sjhb 97128928Sjhb KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); 98128928Sjhb KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); 99128928Sjhb if (elcr_status & ELCR_MASK(irq)) 100128928Sjhb return (INTR_TRIGGER_LEVEL); 101128928Sjhb else 102128928Sjhb return (INTR_TRIGGER_EDGE); 103128928Sjhb} 104128928Sjhb 105128928Sjhb/* 106128928Sjhb * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered, 107128928Sjhb * and a mode of 1 means level triggered. 108128928Sjhb */ 109128928Sjhbvoid 110128928Sjhbelcr_write_trigger(u_int irq, enum intr_trigger trigger) 111128928Sjhb{ 112128928Sjhb int new_status; 113128928Sjhb 114128928Sjhb KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); 115128928Sjhb KASSERT(irq <= 15, ("%s: invalid IRQ %u", __func__, irq)); 116128928Sjhb if (trigger == INTR_TRIGGER_LEVEL) 117128928Sjhb new_status = elcr_status | ELCR_MASK(irq); 118128928Sjhb else 119128928Sjhb new_status = elcr_status & ~ELCR_MASK(irq); 120128928Sjhb if (new_status == elcr_status) 121128928Sjhb return; 122128928Sjhb elcr_status = new_status; 123128928Sjhb if (irq >= 8) 124128928Sjhb outb(ELCR_PORT + 1, elcr_status >> 8); 125128928Sjhb else 126128928Sjhb outb(ELCR_PORT, elcr_status & 0xff); 127128928Sjhb} 128128928Sjhb 129128928Sjhbvoid 130128928Sjhbelcr_resume(void) 131128928Sjhb{ 132128928Sjhb 133128928Sjhb KASSERT(elcr_found, ("%s: no ELCR was found!", __func__)); 134128928Sjhb outb(ELCR_PORT, elcr_status & 0xff); 135128928Sjhb outb(ELCR_PORT + 1, elcr_status >> 8); 136128928Sjhb} 137