1257251Skib/*- 2278947Skib * Copyright (c) 2013-2015 The FreeBSD Foundation 3257251Skib * All rights reserved. 4257251Skib * 5257251Skib * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 6257251Skib * under sponsorship from the FreeBSD Foundation. 7257251Skib * 8257251Skib * Redistribution and use in source and binary forms, with or without 9257251Skib * modification, are permitted provided that the following conditions 10257251Skib * are met: 11257251Skib * 1. Redistributions of source code must retain the above copyright 12257251Skib * notice, this list of conditions and the following disclaimer. 13257251Skib * 2. Redistributions in binary form must reproduce the above copyright 14257251Skib * notice, this list of conditions and the following disclaimer in the 15257251Skib * documentation and/or other materials provided with the distribution. 16257251Skib * 17257251Skib * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18257251Skib * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19257251Skib * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20257251Skib * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21257251Skib * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22257251Skib * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23257251Skib * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24257251Skib * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25257251Skib * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26257251Skib * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27257251Skib * SUCH DAMAGE. 28257251Skib * 29257251Skib * $FreeBSD: releng/10.3/sys/x86/iommu/intel_reg.h 280684 2015-03-26 10:44:16Z kib $ 30257251Skib */ 31257251Skib 32257251Skib#ifndef __X86_IOMMU_INTEL_REG_H 33257251Skib#define __X86_IOMMU_INTEL_REG_H 34257251Skib 35257251Skib#define DMAR_PAGE_SIZE PAGE_SIZE 36257251Skib#define DMAR_PAGE_MASK (DMAR_PAGE_SIZE - 1) 37257251Skib#define DMAR_PAGE_SHIFT PAGE_SHIFT 38257251Skib#define DMAR_NPTEPG (DMAR_PAGE_SIZE / sizeof(dmar_pte_t)) 39257251Skib#define DMAR_NPTEPGSHIFT 9 40257251Skib#define DMAR_PTEMASK (DMAR_NPTEPG - 1) 41257251Skib 42257251Skibtypedef struct dmar_root_entry { 43257251Skib uint64_t r1; 44257251Skib uint64_t r2; 45257251Skib} dmar_root_entry_t; 46257251Skib#define DMAR_ROOT_R1_P 1 /* Present */ 47257251Skib#define DMAR_ROOT_R1_CTP_MASK 0xfffffffffffff000 /* Mask for Context-Entry 48257251Skib Table Pointer */ 49257251Skib 50257251Skib#define DMAR_CTX_CNT (DMAR_PAGE_SIZE / sizeof(dmar_root_entry_t)) 51257251Skib 52257251Skibtypedef struct dmar_ctx_entry { 53257251Skib uint64_t ctx1; 54257251Skib uint64_t ctx2; 55257251Skib} dmar_ctx_entry_t; 56257251Skib#define DMAR_CTX1_P 1 /* Present */ 57257251Skib#define DMAR_CTX1_FPD 2 /* Fault Processing Disable */ 58257251Skib /* Translation Type: */ 59257251Skib#define DMAR_CTX1_T_UNTR 0 /* only Untranslated */ 60257251Skib#define DMAR_CTX1_T_TR 4 /* both Untranslated 61257251Skib and Translated */ 62257251Skib#define DMAR_CTX1_T_PASS 8 /* Pass-Through */ 63257251Skib#define DMAR_CTX1_ASR_MASK 0xfffffffffffff000 /* Mask for the Address 64257251Skib Space Root */ 65257251Skib#define DMAR_CTX2_AW_2LVL 0 /* 2-level page tables */ 66257251Skib#define DMAR_CTX2_AW_3LVL 1 /* 3-level page tables */ 67257251Skib#define DMAR_CTX2_AW_4LVL 2 /* 4-level page tables */ 68257251Skib#define DMAR_CTX2_AW_5LVL 3 /* 5-level page tables */ 69257251Skib#define DMAR_CTX2_AW_6LVL 4 /* 6-level page tables */ 70257251Skib#define DMAR_CTX2_DID(x) ((x) << 8) /* Domain Identifier */ 71257251Skib 72257251Skibtypedef struct dmar_pte { 73257251Skib uint64_t pte; 74257251Skib} dmar_pte_t; 75257251Skib#define DMAR_PTE_R 1 /* Read */ 76257251Skib#define DMAR_PTE_W (1 << 1) /* Write */ 77257251Skib#define DMAR_PTE_SP (1 << 7) /* Super Page */ 78257251Skib#define DMAR_PTE_SNP (1 << 11) /* Snoop Behaviour */ 79257251Skib#define DMAR_PTE_ADDR_MASK 0xffffffffff000 /* Address Mask */ 80257251Skib#define DMAR_PTE_TM (1ULL << 62) /* Transient Mapping */ 81257251Skib 82278947Skibtypedef struct dmar_irte { 83278947Skib uint64_t irte1; 84278947Skib uint64_t irte2; 85278947Skib} dmar_irte_t; 86278947Skib/* Source Validation Type */ 87278947Skib#define DMAR_IRTE2_SVT_NONE (0ULL << (82 - 64)) 88278947Skib#define DMAR_IRTE2_SVT_RID (1ULL << (82 - 64)) 89278947Skib#define DMAR_IRTE2_SVT_BUS (2ULL << (82 - 64)) 90278947Skib/* Source-id Qualifier */ 91278947Skib#define DMAR_IRTE2_SQ_RID (0ULL << (80 - 64)) 92278947Skib#define DMAR_IRTE2_SQ_RID_N2 (1ULL << (80 - 64)) 93278947Skib#define DMAR_IRTE2_SQ_RID_N21 (2ULL << (80 - 64)) 94278947Skib#define DMAR_IRTE2_SQ_RID_N210 (3ULL << (80 - 64)) 95278947Skib/* Source Identifier */ 96278947Skib#define DMAR_IRTE2_SID_RID(x) ((uint64_t)(x)) 97278947Skib#define DMAR_IRTE2_SID_BUS(start, end) ((((uint64_t)(start)) << 8) | (end)) 98278947Skib/* Destination Id */ 99278947Skib#define DMAR_IRTE1_DST_xAPIC(x) (((uint64_t)(x)) << 40) 100278947Skib#define DMAR_IRTE1_DST_x2APIC(x) (((uint64_t)(x)) << 32) 101278947Skib/* Vector */ 102278947Skib#define DMAR_IRTE1_V(x) (((uint64_t)x) << 16) 103278947Skib#define DMAR_IRTE1_IM_POSTED (1ULL << 15) /* Posted */ 104278947Skib/* Delivery Mode */ 105278947Skib#define DMAR_IRTE1_DLM_FM (0ULL << 5) 106280343Skib#define DMAR_IRTE1_DLM_LP (1ULL << 5) 107278947Skib#define DMAR_IRTE1_DLM_SMI (2ULL << 5) 108278947Skib#define DMAR_IRTE1_DLM_NMI (4ULL << 5) 109278947Skib#define DMAR_IRTE1_DLM_INIT (5ULL << 5) 110278947Skib#define DMAR_IRTE1_DLM_ExtINT (7ULL << 5) 111278947Skib/* Trigger Mode */ 112278947Skib#define DMAR_IRTE1_TM_EDGE (0ULL << 4) 113278947Skib#define DMAR_IRTE1_TM_LEVEL (1ULL << 4) 114278947Skib/* Redirection Hint */ 115278947Skib#define DMAR_IRTE1_RH_DIRECT (0ULL << 3) 116278947Skib#define DMAR_IRTE1_RH_SELECT (1ULL << 3) 117278947Skib/* Destination Mode */ 118278947Skib#define DMAR_IRTE1_DM_PHYSICAL (0ULL << 2) 119278947Skib#define DMAR_IRTE1_DM_LOGICAL (1ULL << 2) 120278947Skib#define DMAR_IRTE1_FPD (1ULL << 1) /* Fault Processing Disable */ 121278947Skib#define DMAR_IRTE1_P (1ULL) /* Present */ 122278947Skib 123257251Skib/* Version register */ 124257251Skib#define DMAR_VER_REG 0 125257251Skib#define DMAR_MAJOR_VER(x) (((x) >> 4) & 0xf) 126257251Skib#define DMAR_MINOR_VER(x) ((x) & 0xf) 127257251Skib 128257251Skib/* Capabilities register */ 129257251Skib#define DMAR_CAP_REG 0x8 130278947Skib#define DMAR_CAP_PI (1ULL << 59) /* Posted Interrupts */ 131278947Skib#define DMAR_CAP_FL1GP (1ULL << 56) /* First Level 1GByte Page */ 132257251Skib#define DMAR_CAP_DRD (1ULL << 55) /* DMA Read Draining */ 133257251Skib#define DMAR_CAP_DWD (1ULL << 54) /* DMA Write Draining */ 134257251Skib#define DMAR_CAP_MAMV(x) ((u_int)(((x) >> 48) & 0x3f)) 135257251Skib /* Maximum Address Mask */ 136257251Skib#define DMAR_CAP_NFR(x) ((u_int)(((x) >> 40) & 0xff) + 1) 137257251Skib /* Num of Fault-recording regs */ 138257251Skib#define DMAR_CAP_PSI (1ULL << 39) /* Page Selective Invalidation */ 139257251Skib#define DMAR_CAP_SPS(x) ((u_int)(((x) >> 34) & 0xf)) /* Super-Page Support */ 140257251Skib#define DMAR_CAP_SPS_2M 0x1 141257251Skib#define DMAR_CAP_SPS_1G 0x2 142257251Skib#define DMAR_CAP_SPS_512G 0x4 143257251Skib#define DMAR_CAP_SPS_1T 0x8 144257251Skib#define DMAR_CAP_FRO(x) ((u_int)(((x) >> 24) & 0x1ff)) 145257251Skib /* Fault-recording reg offset */ 146257251Skib#define DMAR_CAP_ISOCH (1 << 23) /* Isochrony */ 147257251Skib#define DMAR_CAP_ZLR (1 << 22) /* Zero-length reads */ 148257251Skib#define DMAR_CAP_MGAW(x) ((u_int)(((x) >> 16) & 0x3f)) 149257251Skib /* Max Guest Address Width */ 150257251Skib#define DMAR_CAP_SAGAW(x) ((u_int)(((x) >> 8) & 0x1f)) 151257251Skib /* Adjusted Guest Address Width */ 152257251Skib#define DMAR_CAP_SAGAW_2LVL 0x01 153257251Skib#define DMAR_CAP_SAGAW_3LVL 0x02 154257251Skib#define DMAR_CAP_SAGAW_4LVL 0x04 155257251Skib#define DMAR_CAP_SAGAW_5LVL 0x08 156257251Skib#define DMAR_CAP_SAGAW_6LVL 0x10 157257251Skib#define DMAR_CAP_CM (1 << 7) /* Caching mode */ 158257251Skib#define DMAR_CAP_PHMR (1 << 6) /* Protected High-mem Region */ 159257251Skib#define DMAR_CAP_PLMR (1 << 5) /* Protected Low-mem Region */ 160257251Skib#define DMAR_CAP_RWBF (1 << 4) /* Required Write-Buffer Flushing */ 161257251Skib#define DMAR_CAP_AFL (1 << 3) /* Advanced Fault Logging */ 162257251Skib#define DMAR_CAP_ND(x) ((u_int)((x) & 0x3)) /* Number of domains */ 163257251Skib 164257251Skib/* Extended Capabilities register */ 165257251Skib#define DMAR_ECAP_REG 0x10 166278947Skib#define DMAR_ECAP_PSS(x) (((x) >> 35) & 0xf) /* PASID Size Supported */ 167278947Skib#define DMAR_ECAP_EAFS (1ULL << 34) /* Extended Accessed Flag */ 168278947Skib#define DMAR_ECAP_NWFS (1ULL << 33) /* No Write Flag */ 169278947Skib#define DMAR_ECAP_SRS (1ULL << 31) /* Supervisor Request */ 170278947Skib#define DMAR_ECAP_ERS (1ULL << 30) /* Execute Request */ 171278947Skib#define DMAR_ECAP_PRS (1ULL << 29) /* Page Request */ 172278947Skib#define DMAR_ECAP_PASID (1ULL << 28) /* Process Address Space Id */ 173278947Skib#define DMAR_ECAP_DIS (1ULL << 27) /* Deferred Invalidate */ 174278947Skib#define DMAR_ECAP_NEST (1ULL << 26) /* Nested Translation */ 175278947Skib#define DMAR_ECAP_MTS (1ULL << 25) /* Memory Type */ 176278947Skib#define DMAR_ECAP_ECS (1ULL << 24) /* Extended Context */ 177257251Skib#define DMAR_ECAP_MHMV(x) ((u_int)(((x) >> 20) & 0xf)) 178257251Skib /* Maximum Handle Mask Value */ 179257251Skib#define DMAR_ECAP_IRO(x) ((u_int)(((x) >> 8) & 0x3ff)) 180257251Skib /* IOTLB Register Offset */ 181257251Skib#define DMAR_ECAP_SC (1 << 7) /* Snoop Control */ 182257251Skib#define DMAR_ECAP_PT (1 << 6) /* Pass Through */ 183280684Skib#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode (x2APIC) */ 184257251Skib#define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */ 185257251Skib#define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */ 186257251Skib#define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */ 187257251Skib#define DMAR_ECAP_C (1 << 0) /* Coherency */ 188257251Skib 189257251Skib/* Global Command register */ 190257251Skib#define DMAR_GCMD_REG 0x18 191261455Seadler#define DMAR_GCMD_TE (1U << 31) /* Translation Enable */ 192257251Skib#define DMAR_GCMD_SRTP (1 << 30) /* Set Root Table Pointer */ 193257251Skib#define DMAR_GCMD_SFL (1 << 29) /* Set Fault Log */ 194257251Skib#define DMAR_GCMD_EAFL (1 << 28) /* Enable Advanced Fault Logging */ 195257251Skib#define DMAR_GCMD_WBF (1 << 27) /* Write Buffer Flush */ 196257251Skib#define DMAR_GCMD_QIE (1 << 26) /* Queued Invalidation Enable */ 197257251Skib#define DMAR_GCMD_IRE (1 << 25) /* Interrupt Remapping Enable */ 198257251Skib#define DMAR_GCMD_SIRTP (1 << 24) /* Set Interrupt Remap Table Pointer */ 199257251Skib#define DMAR_GCMD_CFI (1 << 23) /* Compatibility Format Interrupt */ 200257251Skib 201257251Skib/* Global Status register */ 202257251Skib#define DMAR_GSTS_REG 0x1c 203261455Seadler#define DMAR_GSTS_TES (1U << 31) /* Translation Enable Status */ 204257251Skib#define DMAR_GSTS_RTPS (1 << 30) /* Root Table Pointer Status */ 205257251Skib#define DMAR_GSTS_FLS (1 << 29) /* Fault Log Status */ 206257251Skib#define DMAR_GSTS_AFLS (1 << 28) /* Advanced Fault Logging Status */ 207257251Skib#define DMAR_GSTS_WBFS (1 << 27) /* Write Buffer Flush Status */ 208257251Skib#define DMAR_GSTS_QIES (1 << 26) /* Queued Invalidation Enable Status */ 209257251Skib#define DMAR_GSTS_IRES (1 << 25) /* Interrupt Remapping Enable Status */ 210257251Skib#define DMAR_GSTS_IRTPS (1 << 24) /* Interrupt Remapping Table 211257251Skib Pointer Status */ 212257251Skib#define DMAR_GSTS_CFIS (1 << 23) /* Compatibility Format 213257251Skib Interrupt Status */ 214257251Skib 215257251Skib/* Root-Entry Table Address register */ 216257251Skib#define DMAR_RTADDR_REG 0x20 217257251Skib 218257251Skib/* Context Command register */ 219257251Skib#define DMAR_CCMD_REG 0x28 220257251Skib#define DMAR_CCMD_ICC (1ULL << 63) /* Invalidate Context-Cache */ 221261455Seadler#define DMAR_CCMD_ICC32 (1U << 31) 222257251Skib#define DMAR_CCMD_CIRG_MASK (0x3ULL << 61) /* Context Invalidation 223257251Skib Request Granularity */ 224257251Skib#define DMAR_CCMD_CIRG_GLOB (0x1ULL << 61) /* Global */ 225257251Skib#define DMAR_CCMD_CIRG_DOM (0x2ULL << 61) /* Domain */ 226257251Skib#define DMAR_CCMD_CIRG_DEV (0x3ULL << 61) /* Device */ 227257251Skib#define DMAR_CCMD_CAIG(x) (((x) >> 59) & 0x3) /* Context Actual 228257251Skib Invalidation Granularity */ 229257251Skib#define DMAR_CCMD_CAIG_GLOB 0x1 /* Global */ 230257251Skib#define DMAR_CCMD_CAIG_DOM 0x2 /* Domain */ 231257251Skib#define DMAR_CCMD_CAIG_DEV 0x3 /* Device */ 232257251Skib#define DMAR_CCMD_FM (0x3UUL << 32) /* Function Mask */ 233257251Skib#define DMAR_CCMD_SID(x) (((x) & 0xffff) << 16) /* Source-ID */ 234257251Skib#define DMAR_CCMD_DID(x) ((x) & 0xffff) /* Domain-ID */ 235257251Skib 236257251Skib/* Invalidate Address register */ 237257251Skib#define DMAR_IVA_REG_OFF 0 238257251Skib#define DMAR_IVA_IH (1 << 6) /* Invalidation Hint */ 239257251Skib#define DMAR_IVA_AM(x) ((x) & 0x1f) /* Address Mask */ 240257251Skib#define DMAR_IVA_ADDR(x) ((x) & ~0xfffULL) /* Address */ 241257251Skib 242257251Skib/* IOTLB Invalidate register */ 243257251Skib#define DMAR_IOTLB_REG_OFF 0x8 244257251Skib#define DMAR_IOTLB_IVT (1ULL << 63) /* Invalidate IOTLB */ 245261455Seadler#define DMAR_IOTLB_IVT32 (1U << 31) 246257251Skib#define DMAR_IOTLB_IIRG_MASK (0x3ULL << 60) /* Invalidation Request 247257251Skib Granularity */ 248257251Skib#define DMAR_IOTLB_IIRG_GLB (0x1ULL << 60) /* Global */ 249257251Skib#define DMAR_IOTLB_IIRG_DOM (0x2ULL << 60) /* Domain-selective */ 250257251Skib#define DMAR_IOTLB_IIRG_PAGE (0x3ULL << 60) /* Page-selective */ 251257251Skib#define DMAR_IOTLB_IAIG_MASK (0x3ULL << 57) /* Actual Invalidation 252257251Skib Granularity */ 253257251Skib#define DMAR_IOTLB_IAIG_INVLD 0 /* Hw detected error */ 254257251Skib#define DMAR_IOTLB_IAIG_GLB (0x1ULL << 57) /* Global */ 255257251Skib#define DMAR_IOTLB_IAIG_DOM (0x2ULL << 57) /* Domain-selective */ 256257251Skib#define DMAR_IOTLB_IAIG_PAGE (0x3ULL << 57) /* Page-selective */ 257257251Skib#define DMAR_IOTLB_DR (0x1ULL << 49) /* Drain Reads */ 258257251Skib#define DMAR_IOTLB_DW (0x1ULL << 48) /* Drain Writes */ 259257251Skib#define DMAR_IOTLB_DID(x) (((uint64_t)(x) & 0xffff) << 32) /* Domain Id */ 260257251Skib 261257251Skib/* Fault Status register */ 262257251Skib#define DMAR_FSTS_REG 0x34 263257251Skib#define DMAR_FSTS_FRI(x) (((x) >> 8) & 0xff) /* Fault Record Index */ 264257251Skib#define DMAR_FSTS_ITE (1 << 6) /* Invalidation Time-out */ 265257251Skib#define DMAR_FSTS_ICE (1 << 5) /* Invalidation Completion */ 266257251Skib#define DMAR_FSTS_IQE (1 << 4) /* Invalidation Queue */ 267257251Skib#define DMAR_FSTS_APF (1 << 3) /* Advanced Pending Fault */ 268257251Skib#define DMAR_FSTS_AFO (1 << 2) /* Advanced Fault Overflow */ 269257251Skib#define DMAR_FSTS_PPF (1 << 1) /* Primary Pending Fault */ 270257251Skib#define DMAR_FSTS_PFO 1 /* Fault Overflow */ 271257251Skib 272257251Skib/* Fault Event Control register */ 273257251Skib#define DMAR_FECTL_REG 0x38 274261455Seadler#define DMAR_FECTL_IM (1U << 31) /* Interrupt Mask */ 275257251Skib#define DMAR_FECTL_IP (1 << 30) /* Interrupt Pending */ 276257251Skib 277257251Skib/* Fault Event Data register */ 278257251Skib#define DMAR_FEDATA_REG 0x3c 279257251Skib 280257251Skib/* Fault Event Address register */ 281257251Skib#define DMAR_FEADDR_REG 0x40 282257251Skib 283257251Skib/* Fault Event Upper Address register */ 284257251Skib#define DMAR_FEUADDR_REG 0x44 285257251Skib 286257251Skib/* Advanced Fault Log register */ 287257251Skib#define DMAR_AFLOG_REG 0x58 288257251Skib 289257251Skib/* Fault Recording Register, also usable for Advanced Fault Log records */ 290257251Skib#define DMAR_FRCD2_F (1ULL << 63) /* Fault */ 291261455Seadler#define DMAR_FRCD2_F32 (1U << 31) 292257251Skib#define DMAR_FRCD2_T(x) ((int)((x >> 62) & 1)) /* Type */ 293257251Skib#define DMAR_FRCD2_T_W 0 /* Write request */ 294257251Skib#define DMAR_FRCD2_T_R 1 /* Read or AtomicOp */ 295257251Skib#define DMAR_FRCD2_AT(x) ((int)((x >> 60) & 0x3)) /* Address Type */ 296257251Skib#define DMAR_FRCD2_FR(x) ((int)((x >> 32) & 0xff)) /* Fault Reason */ 297257251Skib#define DMAR_FRCD2_SID(x) ((int)(x & 0xffff)) /* Source Identifier */ 298257251Skib#define DMAR_FRCS1_FI_MASK 0xffffffffff000 /* Fault Info, Address Mask */ 299257251Skib 300257251Skib/* Protected Memory Enable register */ 301257251Skib#define DMAR_PMEN_REG 0x64 302261455Seadler#define DMAR_PMEN_EPM (1U << 31) /* Enable Protected Memory */ 303257251Skib#define DMAR_PMEN_PRS 1 /* Protected Region Status */ 304257251Skib 305257251Skib/* Protected Low-Memory Base register */ 306257251Skib#define DMAR_PLMBASE_REG 0x68 307257251Skib 308257251Skib/* Protected Low-Memory Limit register */ 309257251Skib#define DMAR_PLMLIMIT_REG 0x6c 310257251Skib 311257251Skib/* Protected High-Memory Base register */ 312257251Skib#define DMAR_PHMBASE_REG 0x70 313257251Skib 314257251Skib/* Protected High-Memory Limit register */ 315257251Skib#define DMAR_PHMLIMIT_REG 0x78 316257251Skib 317259512Skib/* Queued Invalidation Descriptors */ 318259512Skib#define DMAR_IQ_DESCR_SZ_SHIFT 4 /* Shift for descriptor count 319259512Skib to ring offset */ 320259512Skib#define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT) 321259512Skib /* Descriptor size */ 322259512Skib 323280684Skib/* Context-cache Invalidate Descriptor */ 324280684Skib#define DMAR_IQ_DESCR_CTX_INV 0x1 325259512Skib#define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */ 326259512Skib#define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */ 327259512Skib#define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */ 328259512Skib#define DMAR_IQ_DESCR_CTX_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ 329259512Skib#define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */ 330259512Skib#define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */ 331259512Skib 332280684Skib/* IOTLB Invalidate Descriptor */ 333280684Skib#define DMAR_IQ_DESCR_IOTLB_INV 0x2 334259512Skib#define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */ 335259512Skib#define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */ 336259512Skib#define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */ 337259512Skib#define DMAR_IQ_DESCR_IOTLB_DW (1 << 6) /* Drain Writes */ 338259512Skib#define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */ 339259512Skib#define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ 340259512Skib 341280684Skib/* Device-TLB Invalidate Descriptor */ 342280684Skib#define DMAR_IQ_DESCR_DTLB_INV 0x3 343280684Skib 344280684Skib/* Invalidate Interrupt Entry Cache */ 345280684Skib#define DMAR_IQ_DESCR_IEC_INV 0x4 346278947Skib#define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */ 347278947Skib#define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */ 348278947Skib#define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */ 349278947Skib 350280684Skib/* Invalidation Wait Descriptor */ 351280684Skib#define DMAR_IQ_DESCR_WAIT_ID 0x5 352259512Skib#define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */ 353259512Skib#define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */ 354259512Skib#define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */ 355259512Skib#define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */ 356259512Skib 357280684Skib/* Extended IOTLB Invalidate Descriptor */ 358280684Skib#define DMAR_IQ_DESCR_EIOTLB_INV 0x6 359280684Skib 360280684Skib/* PASID-Cache Invalidate Descriptor */ 361280684Skib#define DMAR_IQ_DESCR_PASIDC_INV 0x7 362280684Skib 363280684Skib/* Extended Device-TLB Invalidate Descriptor */ 364280684Skib#define DMAR_IQ_DESCR_EDTLB_INV 0x8 365280684Skib 366257251Skib/* Invalidation Queue Head register */ 367257251Skib#define DMAR_IQH_REG 0x80 368259512Skib#define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */ 369257251Skib 370257251Skib/* Invalidation Queue Tail register */ 371257251Skib#define DMAR_IQT_REG 0x88 372259512Skib#define DMAR_IQT_MASK 0x7fff0 373257251Skib 374257251Skib/* Invalidation Queue Address register */ 375257251Skib#define DMAR_IQA_REG 0x90 376259512Skib#define DMAR_IQA_IQA_MASK 0xfffffffffffff000 /* Invalidation Queue 377259512Skib Base Address mask */ 378259512Skib#define DMAR_IQA_QS_MASK 0x7 /* Queue Size in pages */ 379259512Skib#define DMAR_IQA_QS_MAX 0x7 /* Max Queue size */ 380259512Skib#define DMAR_IQA_QS_DEF 3 381257251Skib 382257251Skib /* Invalidation Completion Status register */ 383257251Skib#define DMAR_ICS_REG 0x9c 384257251Skib#define DMAR_ICS_IWC 1 /* Invalidation Wait 385257251Skib Descriptor Complete */ 386257251Skib 387257251Skib/* Invalidation Event Control register */ 388257251Skib#define DMAR_IECTL_REG 0xa0 389261455Seadler#define DMAR_IECTL_IM (1U << 31) /* Interrupt Mask */ 390257251Skib#define DMAR_IECTL_IP (1 << 30) /* Interrupt Pending */ 391257251Skib 392257251Skib/* Invalidation Event Data register */ 393257251Skib#define DMAR_IEDATA_REG 0xa4 394257251Skib 395257251Skib/* Invalidation Event Address register */ 396257251Skib#define DMAR_IEADDR_REG 0xa8 397257251Skib 398257251Skib/* Invalidation Event Upper Address register */ 399257251Skib#define DMAR_IEUADDR_REG 0xac 400257251Skib 401257251Skib/* Interrupt Remapping Table Address register */ 402257251Skib#define DMAR_IRTA_REG 0xb8 403278947Skib#define DMAR_IRTA_EIME (1 << 11) /* Extended Interrupt Mode 404278947Skib Enable */ 405278947Skib#define DMAR_IRTA_S_MASK 0xf /* Size Mask */ 406257251Skib 407257251Skib#endif 408