p4tcc.c revision 241885
1139724Simp/*- 2142308Snjl * Copyright (c) 2005 Nate Lawson 3124684Ssobomax * All rights reserved. 4124684Ssobomax * 5124684Ssobomax * Redistribution and use in source and binary forms, with or without 6124684Ssobomax * modification, are permitted provided that the following conditions 7124684Ssobomax * are met: 8124684Ssobomax * 1. Redistributions of source code must retain the above copyright 9124684Ssobomax * notice, this list of conditions and the following disclaimer. 10124684Ssobomax * 2. Redistributions in binary form must reproduce the above copyright 11124684Ssobomax * notice, this list of conditions and the following disclaimer in the 12124684Ssobomax * documentation and/or other materials provided with the distribution. 13124684Ssobomax * 14124684Ssobomax * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15124684Ssobomax * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16124684Ssobomax * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17124684Ssobomax * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18124684Ssobomax * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19124684Ssobomax * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20124684Ssobomax * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21124684Ssobomax * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22124684Ssobomax * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23124684Ssobomax * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24124684Ssobomax * SUCH DAMAGE. 25124684Ssobomax */ 26142308Snjl 27124684Ssobomax/* 28142308Snjl * Throttle clock frequency by using the thermal control circuit. This 29142308Snjl * operates independently of SpeedStep and ACPI throttling and is supported 30142308Snjl * on Pentium 4 and later models (feature TM). 31124684Ssobomax * 32142308Snjl * Reference: Intel Developer's manual v.3 #245472-012 33124684Ssobomax * 34142308Snjl * The original version of this driver was written by Ted Unangst for 35142308Snjl * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson 36142308Snjl * for use with the cpufreq framework. 37124684Ssobomax */ 38124684Ssobomax 39124684Ssobomax#include <sys/cdefs.h> 40124684Ssobomax__FBSDID("$FreeBSD: head/sys/x86/cpufreq/p4tcc.c 241885 2012-10-22 13:06:09Z eadler $"); 41124684Ssobomax 42124684Ssobomax#include <sys/param.h> 43124684Ssobomax#include <sys/systm.h> 44142308Snjl#include <sys/bus.h> 45142308Snjl#include <sys/cpu.h> 46124684Ssobomax#include <sys/kernel.h> 47142308Snjl#include <sys/module.h> 48124684Ssobomax 49124684Ssobomax#include <machine/md_var.h> 50124684Ssobomax#include <machine/specialreg.h> 51124684Ssobomax 52142308Snjl#include "cpufreq_if.h" 53124684Ssobomax 54193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 55193530Sjkim 56144877Snjl#include <dev/acpica/acpivar.h> 57144877Snjl#include "acpi_if.h" 58144877Snjl 59142308Snjlstruct p4tcc_softc { 60142308Snjl device_t dev; 61142308Snjl int set_count; 62142308Snjl int lowest_val; 63142308Snjl int auto_mode; 64124684Ssobomax}; 65124684Ssobomax 66142308Snjl#define TCC_NUM_SETTINGS 8 67124684Ssobomax 68142308Snjl#define TCC_ENABLE_ONDEMAND (1<<4) 69142308Snjl#define TCC_REG_OFFSET 1 70142308Snjl#define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS) 71124684Ssobomax 72144877Snjlstatic int p4tcc_features(driver_t *driver, u_int *features); 73142308Snjlstatic void p4tcc_identify(driver_t *driver, device_t parent); 74142308Snjlstatic int p4tcc_probe(device_t dev); 75142308Snjlstatic int p4tcc_attach(device_t dev); 76142308Snjlstatic int p4tcc_settings(device_t dev, struct cf_setting *sets, 77142308Snjl int *count); 78142308Snjlstatic int p4tcc_set(device_t dev, const struct cf_setting *set); 79142308Snjlstatic int p4tcc_get(device_t dev, struct cf_setting *set); 80142308Snjlstatic int p4tcc_type(device_t dev, int *type); 81124684Ssobomax 82142308Snjlstatic device_method_t p4tcc_methods[] = { 83142308Snjl /* Device interface */ 84142308Snjl DEVMETHOD(device_identify, p4tcc_identify), 85142308Snjl DEVMETHOD(device_probe, p4tcc_probe), 86142308Snjl DEVMETHOD(device_attach, p4tcc_attach), 87124684Ssobomax 88142308Snjl /* cpufreq interface */ 89142308Snjl DEVMETHOD(cpufreq_drv_set, p4tcc_set), 90142308Snjl DEVMETHOD(cpufreq_drv_get, p4tcc_get), 91142308Snjl DEVMETHOD(cpufreq_drv_type, p4tcc_type), 92142308Snjl DEVMETHOD(cpufreq_drv_settings, p4tcc_settings), 93144877Snjl 94144877Snjl /* ACPI interface */ 95144877Snjl DEVMETHOD(acpi_get_features, p4tcc_features), 96144877Snjl 97142308Snjl {0, 0} 98142308Snjl}; 99124684Ssobomax 100142308Snjlstatic driver_t p4tcc_driver = { 101142308Snjl "p4tcc", 102142308Snjl p4tcc_methods, 103142308Snjl sizeof(struct p4tcc_softc), 104142308Snjl}; 105124684Ssobomax 106142308Snjlstatic devclass_t p4tcc_devclass; 107142308SnjlDRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0); 108124684Ssobomax 109144877Snjlstatic int 110144877Snjlp4tcc_features(driver_t *driver, u_int *features) 111144877Snjl{ 112144877Snjl 113144877Snjl /* Notify the ACPI CPU that we support direct access to MSRs */ 114144877Snjl *features = ACPI_CAP_THR_MSRS; 115144877Snjl return (0); 116144877Snjl} 117144877Snjl 118124684Ssobomaxstatic void 119142308Snjlp4tcc_identify(driver_t *driver, device_t parent) 120124684Ssobomax{ 121124684Ssobomax 122142308Snjl if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM)) 123134200Ssobomax return; 124142625Snjl 125142625Snjl /* Make sure we're not being doubly invoked. */ 126142625Snjl if (device_find_child(parent, "p4tcc", -1) != NULL) 127142625Snjl return; 128142625Snjl 129142625Snjl /* 130142625Snjl * We attach a p4tcc child for every CPU since settings need to 131142625Snjl * be performed on every CPU in the SMP case. See section 13.15.3 132142625Snjl * of the IA32 Intel Architecture Software Developer's Manual, 133142625Snjl * Volume 3, for more info. 134142625Snjl */ 135181691Sjhb if (BUS_ADD_CHILD(parent, 10, "p4tcc", -1) == NULL) 136142308Snjl device_printf(parent, "add p4tcc child failed\n"); 137124684Ssobomax} 138124684Ssobomax 139124684Ssobomaxstatic int 140142308Snjlp4tcc_probe(device_t dev) 141124684Ssobomax{ 142241885Seadler 143241885Seadler if (resource_disabled("p4tcc", 0)) 144241885Seadler return (ENXIO); 145241885Seadler 146142308Snjl device_set_desc(dev, "CPU Frequency Thermal Control"); 147124684Ssobomax return (0); 148124684Ssobomax} 149124684Ssobomax 150142308Snjlstatic int 151142308Snjlp4tcc_attach(device_t dev) 152124684Ssobomax{ 153142308Snjl struct p4tcc_softc *sc; 154151593Snjl struct cf_setting set; 155124684Ssobomax 156142308Snjl sc = device_get_softc(dev); 157142308Snjl sc->dev = dev; 158142308Snjl sc->set_count = TCC_NUM_SETTINGS; 159124684Ssobomax 160142308Snjl /* 161142308Snjl * On boot, the TCC is usually in Automatic mode where reading the 162142308Snjl * current performance level is likely to produce bogus results. 163142308Snjl * We record that state here and don't trust the contents of the 164142308Snjl * status MSR until we've set it ourselves. 165142308Snjl */ 166142308Snjl sc->auto_mode = TRUE; 167142308Snjl 168177297Sphk /* 169177297Sphk * XXX: After a cursory glance at various Intel specification 170177297Sphk * XXX: updates it seems like these tests for errata is bogus. 171177297Sphk * XXX: As far as I can tell, the failure mode is benign, in 172177297Sphk * XXX: that cpus with no errata will have their bottom two 173177297Sphk * XXX: STPCLK# rates disabled, so rather than waste more time 174177297Sphk * XXX: hunting down intel docs, just document it and punt. /phk 175177297Sphk */ 176177295Sphk switch (cpu_id & 0xff) { 177142308Snjl case 0x22: 178177295Sphk case 0x24: 179177295Sphk case 0x25: 180177295Sphk case 0x27: 181177295Sphk case 0x29: 182142308Snjl /* 183142308Snjl * These CPU models hang when set to 12.5%. 184142308Snjl * See Errata O50, P44, and Z21. 185142308Snjl */ 186142308Snjl sc->set_count -= 1; 187124684Ssobomax break; 188124684Ssobomax case 0x07: /* errata N44 and P18 */ 189124684Ssobomax case 0x0a: 190124684Ssobomax case 0x12: 191124684Ssobomax case 0x13: 192185331Ssobomax case 0x62: /* Pentium D B1: errata AA21 */ 193185331Ssobomax case 0x64: /* Pentium D C1: errata AA21 */ 194185331Ssobomax case 0x65: /* Pentium D D0: errata AA21 */ 195142308Snjl /* 196142308Snjl * These CPU models hang when set to 12.5% or 25%. 197185331Ssobomax * See Errata N44, P18l and AA21. 198142308Snjl */ 199142308Snjl sc->set_count -= 2; 200124684Ssobomax break; 201124684Ssobomax } 202142308Snjl sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1; 203124684Ssobomax 204151593Snjl /* 205151593Snjl * Before we finish attach, switch to 100%. It's possible the BIOS 206151593Snjl * set us to a lower rate. The user can override this after boot. 207151593Snjl */ 208151593Snjl set.freq = 10000; 209151593Snjl p4tcc_set(dev, &set); 210151593Snjl 211142308Snjl cpufreq_register(dev); 212142308Snjl return (0); 213142308Snjl} 214142308Snjl 215142308Snjlstatic int 216142308Snjlp4tcc_settings(device_t dev, struct cf_setting *sets, int *count) 217142308Snjl{ 218142308Snjl struct p4tcc_softc *sc; 219142308Snjl int i, val; 220142308Snjl 221142308Snjl sc = device_get_softc(dev); 222142308Snjl if (sets == NULL || count == NULL) 223142308Snjl return (EINVAL); 224142308Snjl if (*count < sc->set_count) 225142308Snjl return (E2BIG); 226142308Snjl 227142308Snjl /* Return a list of valid settings for this driver. */ 228142308Snjl memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); 229142308Snjl val = TCC_NUM_SETTINGS; 230142308Snjl for (i = 0; i < sc->set_count; i++, val--) { 231142308Snjl sets[i].freq = TCC_SPEED_PERCENT(val); 232142308Snjl sets[i].dev = dev; 233134199Ssobomax } 234142308Snjl *count = sc->set_count; 235134199Ssobomax 236142308Snjl return (0); 237142308Snjl} 238124930Ssobomax 239142308Snjlstatic int 240142308Snjlp4tcc_set(device_t dev, const struct cf_setting *set) 241142308Snjl{ 242142308Snjl struct p4tcc_softc *sc; 243142308Snjl uint64_t mask, msr; 244142308Snjl int val; 245142308Snjl 246142308Snjl if (set == NULL) 247142308Snjl return (EINVAL); 248142308Snjl sc = device_get_softc(dev); 249142308Snjl 250141455Ssobomax /* 251142308Snjl * Validate requested state converts to a setting that is an integer 252142308Snjl * from [sc->lowest_val .. TCC_NUM_SETTINGS]. 253141455Ssobomax */ 254142308Snjl val = set->freq * TCC_NUM_SETTINGS / 10000; 255142308Snjl if (val * 10000 != set->freq * TCC_NUM_SETTINGS || 256142308Snjl val < sc->lowest_val || val > TCC_NUM_SETTINGS) 257142308Snjl return (EINVAL); 258141455Ssobomax 259142308Snjl /* 260142308Snjl * Read the current register and mask off the old setting and 261142308Snjl * On-Demand bit. If the new val is < 100%, set it and the On-Demand 262142308Snjl * bit, otherwise just return to Automatic mode. 263142308Snjl */ 264142308Snjl msr = rdmsr(MSR_THERM_CONTROL); 265142308Snjl mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET; 266142308Snjl msr &= ~(mask | TCC_ENABLE_ONDEMAND); 267142308Snjl if (val < TCC_NUM_SETTINGS) 268142308Snjl msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; 269142308Snjl wrmsr(MSR_THERM_CONTROL, msr); 270124684Ssobomax 271142308Snjl /* 272142308Snjl * Record whether we're now in Automatic or On-Demand mode. We have 273142308Snjl * to cache this since there is no reliable way to check if TCC is in 274142308Snjl * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of 275142308Snjl * the ACPI Thermal Monitor Control Register produces 0 no matter 276142308Snjl * what the current mode. 277142308Snjl */ 278142308Snjl if (msr & TCC_ENABLE_ONDEMAND) 279232199Skan sc->auto_mode = FALSE; 280232199Skan else 281142308Snjl sc->auto_mode = TRUE; 282124684Ssobomax 283142308Snjl return (0); 284124684Ssobomax} 285142308Snjl 286142308Snjlstatic int 287142308Snjlp4tcc_get(device_t dev, struct cf_setting *set) 288142308Snjl{ 289142308Snjl struct p4tcc_softc *sc; 290142308Snjl uint64_t msr; 291142308Snjl int val; 292142308Snjl 293142308Snjl if (set == NULL) 294142308Snjl return (EINVAL); 295142308Snjl sc = device_get_softc(dev); 296142308Snjl 297142308Snjl /* 298142308Snjl * Read the current register and extract the current setting. If 299142308Snjl * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%). 300142308Snjl * 301142308Snjl * XXX This is not completely reliable since at high temperatures 302142308Snjl * the CPU may be automatically throttling to 50% but it's the best 303142308Snjl * we can do. 304142308Snjl */ 305142308Snjl if (!sc->auto_mode) { 306142308Snjl msr = rdmsr(MSR_THERM_CONTROL); 307142308Snjl val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); 308142308Snjl } else 309142308Snjl val = TCC_NUM_SETTINGS; 310142308Snjl 311142308Snjl memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 312142308Snjl set->freq = TCC_SPEED_PERCENT(val); 313142308Snjl set->dev = dev; 314142308Snjl 315142308Snjl return (0); 316142308Snjl} 317142308Snjl 318142308Snjlstatic int 319142308Snjlp4tcc_type(device_t dev, int *type) 320142308Snjl{ 321142308Snjl 322142308Snjl if (type == NULL) 323142308Snjl return (EINVAL); 324142308Snjl 325142308Snjl *type = CPUFREQ_TYPE_RELATIVE; 326142308Snjl return (0); 327142308Snjl} 328