p4tcc.c revision 181691
1139724Simp/*- 2142308Snjl * Copyright (c) 2005 Nate Lawson 3124684Ssobomax * All rights reserved. 4124684Ssobomax * 5124684Ssobomax * Redistribution and use in source and binary forms, with or without 6124684Ssobomax * modification, are permitted provided that the following conditions 7124684Ssobomax * are met: 8124684Ssobomax * 1. Redistributions of source code must retain the above copyright 9124684Ssobomax * notice, this list of conditions and the following disclaimer. 10124684Ssobomax * 2. Redistributions in binary form must reproduce the above copyright 11124684Ssobomax * notice, this list of conditions and the following disclaimer in the 12124684Ssobomax * documentation and/or other materials provided with the distribution. 13124684Ssobomax * 14124684Ssobomax * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15124684Ssobomax * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16124684Ssobomax * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17124684Ssobomax * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18124684Ssobomax * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19124684Ssobomax * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20124684Ssobomax * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21124684Ssobomax * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22124684Ssobomax * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23124684Ssobomax * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24124684Ssobomax * SUCH DAMAGE. 25124684Ssobomax */ 26142308Snjl 27124684Ssobomax/* 28142308Snjl * Throttle clock frequency by using the thermal control circuit. This 29142308Snjl * operates independently of SpeedStep and ACPI throttling and is supported 30142308Snjl * on Pentium 4 and later models (feature TM). 31124684Ssobomax * 32142308Snjl * Reference: Intel Developer's manual v.3 #245472-012 33124684Ssobomax * 34142308Snjl * The original version of this driver was written by Ted Unangst for 35142308Snjl * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson 36142308Snjl * for use with the cpufreq framework. 37124684Ssobomax */ 38124684Ssobomax 39124684Ssobomax#include <sys/cdefs.h> 40124684Ssobomax__FBSDID("$FreeBSD: head/sys/i386/cpufreq/p4tcc.c 181691 2008-08-13 16:09:40Z jhb $"); 41124684Ssobomax 42124684Ssobomax#include <sys/param.h> 43124684Ssobomax#include <sys/systm.h> 44142308Snjl#include <sys/bus.h> 45142308Snjl#include <sys/cpu.h> 46124684Ssobomax#include <sys/kernel.h> 47142308Snjl#include <sys/module.h> 48124684Ssobomax 49124684Ssobomax#include <machine/md_var.h> 50124684Ssobomax#include <machine/specialreg.h> 51124684Ssobomax 52142308Snjl#include "cpufreq_if.h" 53124684Ssobomax 54144877Snjl#include <contrib/dev/acpica/acpi.h> 55144877Snjl#include <dev/acpica/acpivar.h> 56144877Snjl#include "acpi_if.h" 57144877Snjl 58142308Snjlstruct p4tcc_softc { 59142308Snjl device_t dev; 60142308Snjl int set_count; 61142308Snjl int lowest_val; 62142308Snjl int auto_mode; 63124684Ssobomax}; 64124684Ssobomax 65142308Snjl#define TCC_NUM_SETTINGS 8 66124684Ssobomax 67142308Snjl#define TCC_ENABLE_ONDEMAND (1<<4) 68142308Snjl#define TCC_REG_OFFSET 1 69142308Snjl#define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS) 70124684Ssobomax 71144877Snjlstatic int p4tcc_features(driver_t *driver, u_int *features); 72142308Snjlstatic void p4tcc_identify(driver_t *driver, device_t parent); 73142308Snjlstatic int p4tcc_probe(device_t dev); 74142308Snjlstatic int p4tcc_attach(device_t dev); 75142308Snjlstatic int p4tcc_settings(device_t dev, struct cf_setting *sets, 76142308Snjl int *count); 77142308Snjlstatic int p4tcc_set(device_t dev, const struct cf_setting *set); 78142308Snjlstatic int p4tcc_get(device_t dev, struct cf_setting *set); 79142308Snjlstatic int p4tcc_type(device_t dev, int *type); 80124684Ssobomax 81142308Snjlstatic device_method_t p4tcc_methods[] = { 82142308Snjl /* Device interface */ 83142308Snjl DEVMETHOD(device_identify, p4tcc_identify), 84142308Snjl DEVMETHOD(device_probe, p4tcc_probe), 85142308Snjl DEVMETHOD(device_attach, p4tcc_attach), 86124684Ssobomax 87142308Snjl /* cpufreq interface */ 88142308Snjl DEVMETHOD(cpufreq_drv_set, p4tcc_set), 89142308Snjl DEVMETHOD(cpufreq_drv_get, p4tcc_get), 90142308Snjl DEVMETHOD(cpufreq_drv_type, p4tcc_type), 91142308Snjl DEVMETHOD(cpufreq_drv_settings, p4tcc_settings), 92144877Snjl 93144877Snjl /* ACPI interface */ 94144877Snjl DEVMETHOD(acpi_get_features, p4tcc_features), 95144877Snjl 96142308Snjl {0, 0} 97142308Snjl}; 98124684Ssobomax 99142308Snjlstatic driver_t p4tcc_driver = { 100142308Snjl "p4tcc", 101142308Snjl p4tcc_methods, 102142308Snjl sizeof(struct p4tcc_softc), 103142308Snjl}; 104124684Ssobomax 105142308Snjlstatic devclass_t p4tcc_devclass; 106142308SnjlDRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0); 107124684Ssobomax 108144877Snjlstatic int 109144877Snjlp4tcc_features(driver_t *driver, u_int *features) 110144877Snjl{ 111144877Snjl 112144877Snjl /* Notify the ACPI CPU that we support direct access to MSRs */ 113144877Snjl *features = ACPI_CAP_THR_MSRS; 114144877Snjl return (0); 115144877Snjl} 116144877Snjl 117124684Ssobomaxstatic void 118142308Snjlp4tcc_identify(driver_t *driver, device_t parent) 119124684Ssobomax{ 120124684Ssobomax 121142308Snjl if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM)) 122134200Ssobomax return; 123142625Snjl 124142625Snjl /* Make sure we're not being doubly invoked. */ 125142625Snjl if (device_find_child(parent, "p4tcc", -1) != NULL) 126142625Snjl return; 127142625Snjl 128142625Snjl /* 129142625Snjl * We attach a p4tcc child for every CPU since settings need to 130142625Snjl * be performed on every CPU in the SMP case. See section 13.15.3 131142625Snjl * of the IA32 Intel Architecture Software Developer's Manual, 132142625Snjl * Volume 3, for more info. 133142625Snjl */ 134181691Sjhb if (BUS_ADD_CHILD(parent, 10, "p4tcc", -1) == NULL) 135142308Snjl device_printf(parent, "add p4tcc child failed\n"); 136124684Ssobomax} 137124684Ssobomax 138124684Ssobomaxstatic int 139142308Snjlp4tcc_probe(device_t dev) 140124684Ssobomax{ 141124684Ssobomax 142142308Snjl if (resource_disabled("p4tcc", 0)) 143142308Snjl return (ENXIO); 144124684Ssobomax 145142308Snjl device_set_desc(dev, "CPU Frequency Thermal Control"); 146124684Ssobomax return (0); 147124684Ssobomax} 148124684Ssobomax 149142308Snjlstatic int 150142308Snjlp4tcc_attach(device_t dev) 151124684Ssobomax{ 152142308Snjl struct p4tcc_softc *sc; 153151593Snjl struct cf_setting set; 154124684Ssobomax 155142308Snjl sc = device_get_softc(dev); 156142308Snjl sc->dev = dev; 157142308Snjl sc->set_count = TCC_NUM_SETTINGS; 158124684Ssobomax 159142308Snjl /* 160142308Snjl * On boot, the TCC is usually in Automatic mode where reading the 161142308Snjl * current performance level is likely to produce bogus results. 162142308Snjl * We record that state here and don't trust the contents of the 163142308Snjl * status MSR until we've set it ourselves. 164142308Snjl */ 165142308Snjl sc->auto_mode = TRUE; 166142308Snjl 167177297Sphk /* 168177297Sphk * XXX: After a cursory glance at various Intel specification 169177297Sphk * XXX: updates it seems like these tests for errata is bogus. 170177297Sphk * XXX: As far as I can tell, the failure mode is benign, in 171177297Sphk * XXX: that cpus with no errata will have their bottom two 172177297Sphk * XXX: STPCLK# rates disabled, so rather than waste more time 173177297Sphk * XXX: hunting down intel docs, just document it and punt. /phk 174177297Sphk */ 175177295Sphk switch (cpu_id & 0xff) { 176142308Snjl case 0x22: 177177295Sphk case 0x24: 178177295Sphk case 0x25: 179177295Sphk case 0x27: 180177295Sphk case 0x29: 181142308Snjl /* 182142308Snjl * These CPU models hang when set to 12.5%. 183142308Snjl * See Errata O50, P44, and Z21. 184142308Snjl */ 185142308Snjl sc->set_count -= 1; 186124684Ssobomax break; 187124684Ssobomax case 0x07: /* errata N44 and P18 */ 188124684Ssobomax case 0x0a: 189124684Ssobomax case 0x12: 190124684Ssobomax case 0x13: 191142308Snjl /* 192142308Snjl * These CPU models hang when set to 12.5% or 25%. 193142308Snjl * See Errata N44 and P18l. 194142308Snjl */ 195142308Snjl sc->set_count -= 2; 196124684Ssobomax break; 197124684Ssobomax } 198142308Snjl sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1; 199124684Ssobomax 200151593Snjl /* 201151593Snjl * Before we finish attach, switch to 100%. It's possible the BIOS 202151593Snjl * set us to a lower rate. The user can override this after boot. 203151593Snjl */ 204151593Snjl set.freq = 10000; 205151593Snjl p4tcc_set(dev, &set); 206151593Snjl 207142308Snjl cpufreq_register(dev); 208142308Snjl return (0); 209142308Snjl} 210142308Snjl 211142308Snjlstatic int 212142308Snjlp4tcc_settings(device_t dev, struct cf_setting *sets, int *count) 213142308Snjl{ 214142308Snjl struct p4tcc_softc *sc; 215142308Snjl int i, val; 216142308Snjl 217142308Snjl sc = device_get_softc(dev); 218142308Snjl if (sets == NULL || count == NULL) 219142308Snjl return (EINVAL); 220142308Snjl if (*count < sc->set_count) 221142308Snjl return (E2BIG); 222142308Snjl 223142308Snjl /* Return a list of valid settings for this driver. */ 224142308Snjl memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); 225142308Snjl val = TCC_NUM_SETTINGS; 226142308Snjl for (i = 0; i < sc->set_count; i++, val--) { 227142308Snjl sets[i].freq = TCC_SPEED_PERCENT(val); 228142308Snjl sets[i].dev = dev; 229134199Ssobomax } 230142308Snjl *count = sc->set_count; 231134199Ssobomax 232142308Snjl return (0); 233142308Snjl} 234124930Ssobomax 235142308Snjlstatic int 236142308Snjlp4tcc_set(device_t dev, const struct cf_setting *set) 237142308Snjl{ 238142308Snjl struct p4tcc_softc *sc; 239142308Snjl uint64_t mask, msr; 240142308Snjl int val; 241142308Snjl 242142308Snjl if (set == NULL) 243142308Snjl return (EINVAL); 244142308Snjl sc = device_get_softc(dev); 245142308Snjl 246141455Ssobomax /* 247142308Snjl * Validate requested state converts to a setting that is an integer 248142308Snjl * from [sc->lowest_val .. TCC_NUM_SETTINGS]. 249141455Ssobomax */ 250142308Snjl val = set->freq * TCC_NUM_SETTINGS / 10000; 251142308Snjl if (val * 10000 != set->freq * TCC_NUM_SETTINGS || 252142308Snjl val < sc->lowest_val || val > TCC_NUM_SETTINGS) 253142308Snjl return (EINVAL); 254141455Ssobomax 255142308Snjl /* 256142308Snjl * Read the current register and mask off the old setting and 257142308Snjl * On-Demand bit. If the new val is < 100%, set it and the On-Demand 258142308Snjl * bit, otherwise just return to Automatic mode. 259142308Snjl */ 260142308Snjl msr = rdmsr(MSR_THERM_CONTROL); 261142308Snjl mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET; 262142308Snjl msr &= ~(mask | TCC_ENABLE_ONDEMAND); 263142308Snjl if (val < TCC_NUM_SETTINGS) 264142308Snjl msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; 265142308Snjl wrmsr(MSR_THERM_CONTROL, msr); 266124684Ssobomax 267142308Snjl /* 268142308Snjl * Record whether we're now in Automatic or On-Demand mode. We have 269142308Snjl * to cache this since there is no reliable way to check if TCC is in 270142308Snjl * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of 271142308Snjl * the ACPI Thermal Monitor Control Register produces 0 no matter 272142308Snjl * what the current mode. 273142308Snjl */ 274142308Snjl if (msr & TCC_ENABLE_ONDEMAND) 275142308Snjl sc->auto_mode = TRUE; 276142308Snjl else 277142308Snjl sc->auto_mode = FALSE; 278124684Ssobomax 279142308Snjl return (0); 280124684Ssobomax} 281142308Snjl 282142308Snjlstatic int 283142308Snjlp4tcc_get(device_t dev, struct cf_setting *set) 284142308Snjl{ 285142308Snjl struct p4tcc_softc *sc; 286142308Snjl uint64_t msr; 287142308Snjl int val; 288142308Snjl 289142308Snjl if (set == NULL) 290142308Snjl return (EINVAL); 291142308Snjl sc = device_get_softc(dev); 292142308Snjl 293142308Snjl /* 294142308Snjl * Read the current register and extract the current setting. If 295142308Snjl * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%). 296142308Snjl * 297142308Snjl * XXX This is not completely reliable since at high temperatures 298142308Snjl * the CPU may be automatically throttling to 50% but it's the best 299142308Snjl * we can do. 300142308Snjl */ 301142308Snjl if (!sc->auto_mode) { 302142308Snjl msr = rdmsr(MSR_THERM_CONTROL); 303142308Snjl val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); 304142308Snjl } else 305142308Snjl val = TCC_NUM_SETTINGS; 306142308Snjl 307142308Snjl memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 308142308Snjl set->freq = TCC_SPEED_PERCENT(val); 309142308Snjl set->dev = dev; 310142308Snjl 311142308Snjl return (0); 312142308Snjl} 313142308Snjl 314142308Snjlstatic int 315142308Snjlp4tcc_type(device_t dev, int *type) 316142308Snjl{ 317142308Snjl 318142308Snjl if (type == NULL) 319142308Snjl return (EINVAL); 320142308Snjl 321142308Snjl *type = CPUFREQ_TYPE_RELATIVE; 322142308Snjl return (0); 323142308Snjl} 324