p4tcc.c revision 142625
1139724Simp/*- 2142308Snjl * Copyright (c) 2005 Nate Lawson 3124684Ssobomax * All rights reserved. 4124684Ssobomax * 5124684Ssobomax * Redistribution and use in source and binary forms, with or without 6124684Ssobomax * modification, are permitted provided that the following conditions 7124684Ssobomax * are met: 8124684Ssobomax * 1. Redistributions of source code must retain the above copyright 9124684Ssobomax * notice, this list of conditions and the following disclaimer. 10124684Ssobomax * 2. Redistributions in binary form must reproduce the above copyright 11124684Ssobomax * notice, this list of conditions and the following disclaimer in the 12124684Ssobomax * documentation and/or other materials provided with the distribution. 13124684Ssobomax * 14124684Ssobomax * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15124684Ssobomax * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16124684Ssobomax * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17124684Ssobomax * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18124684Ssobomax * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19124684Ssobomax * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20124684Ssobomax * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21124684Ssobomax * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22124684Ssobomax * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23124684Ssobomax * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24124684Ssobomax * SUCH DAMAGE. 25124684Ssobomax */ 26142308Snjl 27124684Ssobomax/* 28142308Snjl * Throttle clock frequency by using the thermal control circuit. This 29142308Snjl * operates independently of SpeedStep and ACPI throttling and is supported 30142308Snjl * on Pentium 4 and later models (feature TM). 31124684Ssobomax * 32142308Snjl * Reference: Intel Developer's manual v.3 #245472-012 33124684Ssobomax * 34142308Snjl * The original version of this driver was written by Ted Unangst for 35142308Snjl * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson 36142308Snjl * for use with the cpufreq framework. 37124684Ssobomax */ 38124684Ssobomax 39124684Ssobomax#include <sys/cdefs.h> 40124684Ssobomax__FBSDID("$FreeBSD: head/sys/i386/cpufreq/p4tcc.c 142625 2005-02-27 02:43:02Z njl $"); 41124684Ssobomax 42124684Ssobomax#include <sys/param.h> 43124684Ssobomax#include <sys/systm.h> 44142308Snjl#include <sys/bus.h> 45142308Snjl#include <sys/cpu.h> 46124684Ssobomax#include <sys/kernel.h> 47142308Snjl#include <sys/module.h> 48124684Ssobomax 49124684Ssobomax#include <machine/md_var.h> 50124684Ssobomax#include <machine/specialreg.h> 51124684Ssobomax 52142308Snjl#include "cpufreq_if.h" 53124684Ssobomax 54142308Snjlstruct p4tcc_softc { 55142308Snjl device_t dev; 56142308Snjl int set_count; 57142308Snjl int lowest_val; 58142308Snjl int auto_mode; 59124684Ssobomax}; 60124684Ssobomax 61142308Snjl#define TCC_NUM_SETTINGS 8 62124684Ssobomax 63142308Snjl#define TCC_ENABLE_ONDEMAND (1<<4) 64142308Snjl#define TCC_REG_OFFSET 1 65142308Snjl#define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS) 66124684Ssobomax 67142308Snjlstatic void p4tcc_identify(driver_t *driver, device_t parent); 68142308Snjlstatic int p4tcc_probe(device_t dev); 69142308Snjlstatic int p4tcc_attach(device_t dev); 70142308Snjlstatic int p4tcc_settings(device_t dev, struct cf_setting *sets, 71142308Snjl int *count); 72142308Snjlstatic int p4tcc_set(device_t dev, const struct cf_setting *set); 73142308Snjlstatic int p4tcc_get(device_t dev, struct cf_setting *set); 74142308Snjlstatic int p4tcc_type(device_t dev, int *type); 75124684Ssobomax 76142308Snjlstatic device_method_t p4tcc_methods[] = { 77142308Snjl /* Device interface */ 78142308Snjl DEVMETHOD(device_identify, p4tcc_identify), 79142308Snjl DEVMETHOD(device_probe, p4tcc_probe), 80142308Snjl DEVMETHOD(device_attach, p4tcc_attach), 81124684Ssobomax 82142308Snjl /* cpufreq interface */ 83142308Snjl DEVMETHOD(cpufreq_drv_set, p4tcc_set), 84142308Snjl DEVMETHOD(cpufreq_drv_get, p4tcc_get), 85142308Snjl DEVMETHOD(cpufreq_drv_type, p4tcc_type), 86142308Snjl DEVMETHOD(cpufreq_drv_settings, p4tcc_settings), 87142308Snjl {0, 0} 88142308Snjl}; 89124684Ssobomax 90142308Snjlstatic driver_t p4tcc_driver = { 91142308Snjl "p4tcc", 92142308Snjl p4tcc_methods, 93142308Snjl sizeof(struct p4tcc_softc), 94142308Snjl}; 95124684Ssobomax 96142308Snjlstatic devclass_t p4tcc_devclass; 97142308SnjlDRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0); 98124684Ssobomax 99124684Ssobomaxstatic void 100142308Snjlp4tcc_identify(driver_t *driver, device_t parent) 101124684Ssobomax{ 102124684Ssobomax 103142308Snjl if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM)) 104134200Ssobomax return; 105142625Snjl 106142625Snjl /* Make sure we're not being doubly invoked. */ 107142625Snjl if (device_find_child(parent, "p4tcc", -1) != NULL) 108142625Snjl return; 109142625Snjl 110142625Snjl /* 111142625Snjl * We attach a p4tcc child for every CPU since settings need to 112142625Snjl * be performed on every CPU in the SMP case. See section 13.15.3 113142625Snjl * of the IA32 Intel Architecture Software Developer's Manual, 114142625Snjl * Volume 3, for more info. 115142625Snjl */ 116142308Snjl if (BUS_ADD_CHILD(parent, 0, "p4tcc", -1) == NULL) 117142308Snjl device_printf(parent, "add p4tcc child failed\n"); 118124684Ssobomax} 119124684Ssobomax 120124684Ssobomaxstatic int 121142308Snjlp4tcc_probe(device_t dev) 122124684Ssobomax{ 123124684Ssobomax 124142308Snjl if (resource_disabled("p4tcc", 0)) 125142308Snjl return (ENXIO); 126124684Ssobomax 127142308Snjl device_set_desc(dev, "CPU Frequency Thermal Control"); 128124684Ssobomax return (0); 129124684Ssobomax} 130124684Ssobomax 131142308Snjlstatic int 132142308Snjlp4tcc_attach(device_t dev) 133124684Ssobomax{ 134142308Snjl struct p4tcc_softc *sc; 135124684Ssobomax 136142308Snjl sc = device_get_softc(dev); 137142308Snjl sc->dev = dev; 138142308Snjl sc->set_count = TCC_NUM_SETTINGS; 139124684Ssobomax 140142308Snjl /* 141142308Snjl * On boot, the TCC is usually in Automatic mode where reading the 142142308Snjl * current performance level is likely to produce bogus results. 143142308Snjl * We record that state here and don't trust the contents of the 144142308Snjl * status MSR until we've set it ourselves. 145142308Snjl */ 146142308Snjl sc->auto_mode = TRUE; 147142308Snjl 148124684Ssobomax switch (cpu_id & 0xf) { 149142308Snjl case 0x22: 150124684Ssobomax case 0x24: 151124684Ssobomax case 0x25: 152124684Ssobomax case 0x27: 153124684Ssobomax case 0x29: 154142308Snjl /* 155142308Snjl * These CPU models hang when set to 12.5%. 156142308Snjl * See Errata O50, P44, and Z21. 157142308Snjl */ 158142308Snjl sc->set_count -= 1; 159124684Ssobomax break; 160124684Ssobomax case 0x07: /* errata N44 and P18 */ 161124684Ssobomax case 0x0a: 162124684Ssobomax case 0x12: 163124684Ssobomax case 0x13: 164142308Snjl /* 165142308Snjl * These CPU models hang when set to 12.5% or 25%. 166142308Snjl * See Errata N44 and P18l. 167142308Snjl */ 168142308Snjl sc->set_count -= 2; 169124684Ssobomax break; 170124684Ssobomax } 171142308Snjl sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1; 172124684Ssobomax 173142308Snjl cpufreq_register(dev); 174142308Snjl return (0); 175142308Snjl} 176142308Snjl 177142308Snjlstatic int 178142308Snjlp4tcc_settings(device_t dev, struct cf_setting *sets, int *count) 179142308Snjl{ 180142308Snjl struct p4tcc_softc *sc; 181142308Snjl int i, val; 182142308Snjl 183142308Snjl sc = device_get_softc(dev); 184142308Snjl if (sets == NULL || count == NULL) 185142308Snjl return (EINVAL); 186142308Snjl if (*count < sc->set_count) 187142308Snjl return (E2BIG); 188142308Snjl 189142308Snjl /* Return a list of valid settings for this driver. */ 190142308Snjl memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); 191142308Snjl val = TCC_NUM_SETTINGS; 192142308Snjl for (i = 0; i < sc->set_count; i++, val--) { 193142308Snjl sets[i].freq = TCC_SPEED_PERCENT(val); 194142308Snjl sets[i].dev = dev; 195134199Ssobomax } 196142308Snjl *count = sc->set_count; 197134199Ssobomax 198142308Snjl return (0); 199142308Snjl} 200124930Ssobomax 201142308Snjlstatic int 202142308Snjlp4tcc_set(device_t dev, const struct cf_setting *set) 203142308Snjl{ 204142308Snjl struct p4tcc_softc *sc; 205142308Snjl uint64_t mask, msr; 206142308Snjl int val; 207142308Snjl 208142308Snjl if (set == NULL) 209142308Snjl return (EINVAL); 210142308Snjl sc = device_get_softc(dev); 211142308Snjl 212141455Ssobomax /* 213142308Snjl * Validate requested state converts to a setting that is an integer 214142308Snjl * from [sc->lowest_val .. TCC_NUM_SETTINGS]. 215141455Ssobomax */ 216142308Snjl val = set->freq * TCC_NUM_SETTINGS / 10000; 217142308Snjl if (val * 10000 != set->freq * TCC_NUM_SETTINGS || 218142308Snjl val < sc->lowest_val || val > TCC_NUM_SETTINGS) 219142308Snjl return (EINVAL); 220141455Ssobomax 221142308Snjl /* 222142308Snjl * Read the current register and mask off the old setting and 223142308Snjl * On-Demand bit. If the new val is < 100%, set it and the On-Demand 224142308Snjl * bit, otherwise just return to Automatic mode. 225142308Snjl */ 226142308Snjl msr = rdmsr(MSR_THERM_CONTROL); 227142308Snjl mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET; 228142308Snjl msr &= ~(mask | TCC_ENABLE_ONDEMAND); 229142308Snjl if (val < TCC_NUM_SETTINGS) 230142308Snjl msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; 231142308Snjl wrmsr(MSR_THERM_CONTROL, msr); 232124684Ssobomax 233142308Snjl /* 234142308Snjl * Record whether we're now in Automatic or On-Demand mode. We have 235142308Snjl * to cache this since there is no reliable way to check if TCC is in 236142308Snjl * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of 237142308Snjl * the ACPI Thermal Monitor Control Register produces 0 no matter 238142308Snjl * what the current mode. 239142308Snjl */ 240142308Snjl if (msr & TCC_ENABLE_ONDEMAND) 241142308Snjl sc->auto_mode = TRUE; 242142308Snjl else 243142308Snjl sc->auto_mode = FALSE; 244124684Ssobomax 245142308Snjl return (0); 246124684Ssobomax} 247142308Snjl 248142308Snjlstatic int 249142308Snjlp4tcc_get(device_t dev, struct cf_setting *set) 250142308Snjl{ 251142308Snjl struct p4tcc_softc *sc; 252142308Snjl uint64_t msr; 253142308Snjl int val; 254142308Snjl 255142308Snjl if (set == NULL) 256142308Snjl return (EINVAL); 257142308Snjl sc = device_get_softc(dev); 258142308Snjl 259142308Snjl /* 260142308Snjl * Read the current register and extract the current setting. If 261142308Snjl * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%). 262142308Snjl * 263142308Snjl * XXX This is not completely reliable since at high temperatures 264142308Snjl * the CPU may be automatically throttling to 50% but it's the best 265142308Snjl * we can do. 266142308Snjl */ 267142308Snjl if (!sc->auto_mode) { 268142308Snjl msr = rdmsr(MSR_THERM_CONTROL); 269142308Snjl val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); 270142308Snjl } else 271142308Snjl val = TCC_NUM_SETTINGS; 272142308Snjl 273142308Snjl memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 274142308Snjl set->freq = TCC_SPEED_PERCENT(val); 275142308Snjl set->dev = dev; 276142308Snjl 277142308Snjl return (0); 278142308Snjl} 279142308Snjl 280142308Snjlstatic int 281142308Snjlp4tcc_type(device_t dev, int *type) 282142308Snjl{ 283142308Snjl 284142308Snjl if (type == NULL) 285142308Snjl return (EINVAL); 286142308Snjl 287142308Snjl *type = CPUFREQ_TYPE_RELATIVE; 288142308Snjl return (0); 289142308Snjl} 290