1139724Simp/*- 2142308Snjl * Copyright (c) 2005 Nate Lawson 3124684Ssobomax * All rights reserved. 4124684Ssobomax * 5124684Ssobomax * Redistribution and use in source and binary forms, with or without 6124684Ssobomax * modification, are permitted provided that the following conditions 7124684Ssobomax * are met: 8124684Ssobomax * 1. Redistributions of source code must retain the above copyright 9124684Ssobomax * notice, this list of conditions and the following disclaimer. 10124684Ssobomax * 2. Redistributions in binary form must reproduce the above copyright 11124684Ssobomax * notice, this list of conditions and the following disclaimer in the 12124684Ssobomax * documentation and/or other materials provided with the distribution. 13124684Ssobomax * 14124684Ssobomax * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15124684Ssobomax * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16124684Ssobomax * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17124684Ssobomax * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18124684Ssobomax * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19124684Ssobomax * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20124684Ssobomax * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21124684Ssobomax * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22124684Ssobomax * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23124684Ssobomax * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24124684Ssobomax * SUCH DAMAGE. 25124684Ssobomax */ 26142308Snjl 27124684Ssobomax/* 28142308Snjl * Throttle clock frequency by using the thermal control circuit. This 29142308Snjl * operates independently of SpeedStep and ACPI throttling and is supported 30142308Snjl * on Pentium 4 and later models (feature TM). 31124684Ssobomax * 32142308Snjl * Reference: Intel Developer's manual v.3 #245472-012 33124684Ssobomax * 34142308Snjl * The original version of this driver was written by Ted Unangst for 35142308Snjl * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson 36142308Snjl * for use with the cpufreq framework. 37124684Ssobomax */ 38124684Ssobomax 39124684Ssobomax#include <sys/cdefs.h> 40124684Ssobomax__FBSDID("$FreeBSD: releng/10.3/sys/x86/cpufreq/p4tcc.c 250487 2013-05-10 22:43:27Z hiren $"); 41124684Ssobomax 42124684Ssobomax#include <sys/param.h> 43124684Ssobomax#include <sys/systm.h> 44142308Snjl#include <sys/bus.h> 45142308Snjl#include <sys/cpu.h> 46124684Ssobomax#include <sys/kernel.h> 47142308Snjl#include <sys/module.h> 48124684Ssobomax 49124684Ssobomax#include <machine/md_var.h> 50124684Ssobomax#include <machine/specialreg.h> 51124684Ssobomax 52142308Snjl#include "cpufreq_if.h" 53124684Ssobomax 54193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 55193530Sjkim 56144877Snjl#include <dev/acpica/acpivar.h> 57144877Snjl#include "acpi_if.h" 58144877Snjl 59142308Snjlstruct p4tcc_softc { 60142308Snjl device_t dev; 61142308Snjl int set_count; 62142308Snjl int lowest_val; 63142308Snjl int auto_mode; 64124684Ssobomax}; 65124684Ssobomax 66142308Snjl#define TCC_NUM_SETTINGS 8 67124684Ssobomax 68142308Snjl#define TCC_ENABLE_ONDEMAND (1<<4) 69142308Snjl#define TCC_REG_OFFSET 1 70142308Snjl#define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS) 71124684Ssobomax 72144877Snjlstatic int p4tcc_features(driver_t *driver, u_int *features); 73142308Snjlstatic void p4tcc_identify(driver_t *driver, device_t parent); 74142308Snjlstatic int p4tcc_probe(device_t dev); 75142308Snjlstatic int p4tcc_attach(device_t dev); 76250487Shirenstatic int p4tcc_detach(device_t dev); 77142308Snjlstatic int p4tcc_settings(device_t dev, struct cf_setting *sets, 78142308Snjl int *count); 79142308Snjlstatic int p4tcc_set(device_t dev, const struct cf_setting *set); 80142308Snjlstatic int p4tcc_get(device_t dev, struct cf_setting *set); 81142308Snjlstatic int p4tcc_type(device_t dev, int *type); 82124684Ssobomax 83142308Snjlstatic device_method_t p4tcc_methods[] = { 84142308Snjl /* Device interface */ 85142308Snjl DEVMETHOD(device_identify, p4tcc_identify), 86142308Snjl DEVMETHOD(device_probe, p4tcc_probe), 87142308Snjl DEVMETHOD(device_attach, p4tcc_attach), 88250487Shiren DEVMETHOD(device_detach, p4tcc_detach), 89124684Ssobomax 90142308Snjl /* cpufreq interface */ 91142308Snjl DEVMETHOD(cpufreq_drv_set, p4tcc_set), 92142308Snjl DEVMETHOD(cpufreq_drv_get, p4tcc_get), 93142308Snjl DEVMETHOD(cpufreq_drv_type, p4tcc_type), 94142308Snjl DEVMETHOD(cpufreq_drv_settings, p4tcc_settings), 95144877Snjl 96144877Snjl /* ACPI interface */ 97144877Snjl DEVMETHOD(acpi_get_features, p4tcc_features), 98144877Snjl 99142308Snjl {0, 0} 100142308Snjl}; 101124684Ssobomax 102142308Snjlstatic driver_t p4tcc_driver = { 103142308Snjl "p4tcc", 104142308Snjl p4tcc_methods, 105142308Snjl sizeof(struct p4tcc_softc), 106142308Snjl}; 107124684Ssobomax 108142308Snjlstatic devclass_t p4tcc_devclass; 109142308SnjlDRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0); 110124684Ssobomax 111144877Snjlstatic int 112144877Snjlp4tcc_features(driver_t *driver, u_int *features) 113144877Snjl{ 114144877Snjl 115144877Snjl /* Notify the ACPI CPU that we support direct access to MSRs */ 116144877Snjl *features = ACPI_CAP_THR_MSRS; 117144877Snjl return (0); 118144877Snjl} 119144877Snjl 120124684Ssobomaxstatic void 121142308Snjlp4tcc_identify(driver_t *driver, device_t parent) 122124684Ssobomax{ 123124684Ssobomax 124142308Snjl if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM)) 125134200Ssobomax return; 126142625Snjl 127142625Snjl /* Make sure we're not being doubly invoked. */ 128142625Snjl if (device_find_child(parent, "p4tcc", -1) != NULL) 129142625Snjl return; 130142625Snjl 131142625Snjl /* 132142625Snjl * We attach a p4tcc child for every CPU since settings need to 133142625Snjl * be performed on every CPU in the SMP case. See section 13.15.3 134142625Snjl * of the IA32 Intel Architecture Software Developer's Manual, 135142625Snjl * Volume 3, for more info. 136142625Snjl */ 137181691Sjhb if (BUS_ADD_CHILD(parent, 10, "p4tcc", -1) == NULL) 138142308Snjl device_printf(parent, "add p4tcc child failed\n"); 139124684Ssobomax} 140124684Ssobomax 141124684Ssobomaxstatic int 142142308Snjlp4tcc_probe(device_t dev) 143124684Ssobomax{ 144241885Seadler 145241885Seadler if (resource_disabled("p4tcc", 0)) 146241885Seadler return (ENXIO); 147241885Seadler 148142308Snjl device_set_desc(dev, "CPU Frequency Thermal Control"); 149124684Ssobomax return (0); 150124684Ssobomax} 151124684Ssobomax 152142308Snjlstatic int 153142308Snjlp4tcc_attach(device_t dev) 154124684Ssobomax{ 155142308Snjl struct p4tcc_softc *sc; 156151593Snjl struct cf_setting set; 157124684Ssobomax 158142308Snjl sc = device_get_softc(dev); 159142308Snjl sc->dev = dev; 160142308Snjl sc->set_count = TCC_NUM_SETTINGS; 161124684Ssobomax 162142308Snjl /* 163142308Snjl * On boot, the TCC is usually in Automatic mode where reading the 164142308Snjl * current performance level is likely to produce bogus results. 165142308Snjl * We record that state here and don't trust the contents of the 166142308Snjl * status MSR until we've set it ourselves. 167142308Snjl */ 168142308Snjl sc->auto_mode = TRUE; 169142308Snjl 170177297Sphk /* 171177297Sphk * XXX: After a cursory glance at various Intel specification 172177297Sphk * XXX: updates it seems like these tests for errata is bogus. 173177297Sphk * XXX: As far as I can tell, the failure mode is benign, in 174177297Sphk * XXX: that cpus with no errata will have their bottom two 175177297Sphk * XXX: STPCLK# rates disabled, so rather than waste more time 176177297Sphk * XXX: hunting down intel docs, just document it and punt. /phk 177177297Sphk */ 178177295Sphk switch (cpu_id & 0xff) { 179142308Snjl case 0x22: 180177295Sphk case 0x24: 181177295Sphk case 0x25: 182177295Sphk case 0x27: 183177295Sphk case 0x29: 184142308Snjl /* 185142308Snjl * These CPU models hang when set to 12.5%. 186142308Snjl * See Errata O50, P44, and Z21. 187142308Snjl */ 188142308Snjl sc->set_count -= 1; 189124684Ssobomax break; 190124684Ssobomax case 0x07: /* errata N44 and P18 */ 191124684Ssobomax case 0x0a: 192124684Ssobomax case 0x12: 193124684Ssobomax case 0x13: 194185331Ssobomax case 0x62: /* Pentium D B1: errata AA21 */ 195185331Ssobomax case 0x64: /* Pentium D C1: errata AA21 */ 196185331Ssobomax case 0x65: /* Pentium D D0: errata AA21 */ 197142308Snjl /* 198142308Snjl * These CPU models hang when set to 12.5% or 25%. 199185331Ssobomax * See Errata N44, P18l and AA21. 200142308Snjl */ 201142308Snjl sc->set_count -= 2; 202124684Ssobomax break; 203124684Ssobomax } 204142308Snjl sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1; 205124684Ssobomax 206151593Snjl /* 207151593Snjl * Before we finish attach, switch to 100%. It's possible the BIOS 208151593Snjl * set us to a lower rate. The user can override this after boot. 209151593Snjl */ 210151593Snjl set.freq = 10000; 211151593Snjl p4tcc_set(dev, &set); 212151593Snjl 213142308Snjl cpufreq_register(dev); 214142308Snjl return (0); 215142308Snjl} 216142308Snjl 217142308Snjlstatic int 218250487Shirenp4tcc_detach(device_t dev) 219250487Shiren{ 220250487Shiren struct cf_setting set; 221250487Shiren int error; 222250487Shiren 223250487Shiren error = cpufreq_unregister(dev); 224250487Shiren if (error) 225250487Shiren return (error); 226250487Shiren 227250487Shiren /* 228250487Shiren * Before we finish detach, switch to Automatic mode. 229250487Shiren */ 230250487Shiren set.freq = 10000; 231250487Shiren p4tcc_set(dev, &set); 232250487Shiren return(0); 233250487Shiren} 234250487Shiren 235250487Shirenstatic int 236142308Snjlp4tcc_settings(device_t dev, struct cf_setting *sets, int *count) 237142308Snjl{ 238142308Snjl struct p4tcc_softc *sc; 239142308Snjl int i, val; 240142308Snjl 241142308Snjl sc = device_get_softc(dev); 242142308Snjl if (sets == NULL || count == NULL) 243142308Snjl return (EINVAL); 244142308Snjl if (*count < sc->set_count) 245142308Snjl return (E2BIG); 246142308Snjl 247142308Snjl /* Return a list of valid settings for this driver. */ 248142308Snjl memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); 249142308Snjl val = TCC_NUM_SETTINGS; 250142308Snjl for (i = 0; i < sc->set_count; i++, val--) { 251142308Snjl sets[i].freq = TCC_SPEED_PERCENT(val); 252142308Snjl sets[i].dev = dev; 253134199Ssobomax } 254142308Snjl *count = sc->set_count; 255134199Ssobomax 256142308Snjl return (0); 257142308Snjl} 258124930Ssobomax 259142308Snjlstatic int 260142308Snjlp4tcc_set(device_t dev, const struct cf_setting *set) 261142308Snjl{ 262142308Snjl struct p4tcc_softc *sc; 263142308Snjl uint64_t mask, msr; 264142308Snjl int val; 265142308Snjl 266142308Snjl if (set == NULL) 267142308Snjl return (EINVAL); 268142308Snjl sc = device_get_softc(dev); 269142308Snjl 270141455Ssobomax /* 271142308Snjl * Validate requested state converts to a setting that is an integer 272142308Snjl * from [sc->lowest_val .. TCC_NUM_SETTINGS]. 273141455Ssobomax */ 274142308Snjl val = set->freq * TCC_NUM_SETTINGS / 10000; 275142308Snjl if (val * 10000 != set->freq * TCC_NUM_SETTINGS || 276142308Snjl val < sc->lowest_val || val > TCC_NUM_SETTINGS) 277142308Snjl return (EINVAL); 278141455Ssobomax 279142308Snjl /* 280142308Snjl * Read the current register and mask off the old setting and 281142308Snjl * On-Demand bit. If the new val is < 100%, set it and the On-Demand 282142308Snjl * bit, otherwise just return to Automatic mode. 283142308Snjl */ 284142308Snjl msr = rdmsr(MSR_THERM_CONTROL); 285142308Snjl mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET; 286142308Snjl msr &= ~(mask | TCC_ENABLE_ONDEMAND); 287142308Snjl if (val < TCC_NUM_SETTINGS) 288142308Snjl msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; 289142308Snjl wrmsr(MSR_THERM_CONTROL, msr); 290124684Ssobomax 291142308Snjl /* 292142308Snjl * Record whether we're now in Automatic or On-Demand mode. We have 293142308Snjl * to cache this since there is no reliable way to check if TCC is in 294142308Snjl * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of 295142308Snjl * the ACPI Thermal Monitor Control Register produces 0 no matter 296142308Snjl * what the current mode. 297142308Snjl */ 298142308Snjl if (msr & TCC_ENABLE_ONDEMAND) 299232199Skan sc->auto_mode = FALSE; 300232199Skan else 301142308Snjl sc->auto_mode = TRUE; 302124684Ssobomax 303142308Snjl return (0); 304124684Ssobomax} 305142308Snjl 306142308Snjlstatic int 307142308Snjlp4tcc_get(device_t dev, struct cf_setting *set) 308142308Snjl{ 309142308Snjl struct p4tcc_softc *sc; 310142308Snjl uint64_t msr; 311142308Snjl int val; 312142308Snjl 313142308Snjl if (set == NULL) 314142308Snjl return (EINVAL); 315142308Snjl sc = device_get_softc(dev); 316142308Snjl 317142308Snjl /* 318142308Snjl * Read the current register and extract the current setting. If 319142308Snjl * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%). 320142308Snjl * 321142308Snjl * XXX This is not completely reliable since at high temperatures 322142308Snjl * the CPU may be automatically throttling to 50% but it's the best 323142308Snjl * we can do. 324142308Snjl */ 325142308Snjl if (!sc->auto_mode) { 326142308Snjl msr = rdmsr(MSR_THERM_CONTROL); 327142308Snjl val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); 328142308Snjl } else 329142308Snjl val = TCC_NUM_SETTINGS; 330142308Snjl 331142308Snjl memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 332142308Snjl set->freq = TCC_SPEED_PERCENT(val); 333142308Snjl set->dev = dev; 334142308Snjl 335142308Snjl return (0); 336142308Snjl} 337142308Snjl 338142308Snjlstatic int 339142308Snjlp4tcc_type(device_t dev, int *type) 340142308Snjl{ 341142308Snjl 342142308Snjl if (type == NULL) 343142308Snjl return (EINVAL); 344142308Snjl 345142308Snjl *type = CPUFREQ_TYPE_RELATIVE; 346142308Snjl return (0); 347142308Snjl} 348