1219567Smarius/* $NetBSD: lsi64854reg.h,v 1.6 2008/04/28 20:23:50 martin Exp $ */ 2130293Sscottl 3130293Sscottl/*- 4130293Sscottl * Copyright (c) 1998 The NetBSD Foundation, Inc. 5130293Sscottl * All rights reserved. 6130293Sscottl * 7130293Sscottl * This code is derived from software contributed to The NetBSD Foundation 8130293Sscottl * by Paul Kranenburg. 9130293Sscottl * 10130293Sscottl * Redistribution and use in source and binary forms, with or without 11130293Sscottl * modification, are permitted provided that the following conditions 12130293Sscottl * are met: 13130293Sscottl * 1. Redistributions of source code must retain the above copyright 14130293Sscottl * notice, this list of conditions and the following disclaimer. 15130293Sscottl * 2. Redistributions in binary form must reproduce the above copyright 16130293Sscottl * notice, this list of conditions and the following disclaimer in the 17130293Sscottl * documentation and/or other materials provided with the distribution. 18130293Sscottl * 19130293Sscottl * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20130293Sscottl * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21130293Sscottl * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22130293Sscottl * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23130293Sscottl * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24130293Sscottl * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25130293Sscottl * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26130293Sscottl * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27130293Sscottl * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28130293Sscottl * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29130293Sscottl * POSSIBILITY OF SUCH DAMAGE. 30130293Sscottl */ 31130293Sscottl 32130293Sscottl/* $FreeBSD: releng/10.3/sys/sparc64/sbus/lsi64854reg.h 219567 2011-03-12 14:33:32Z marius $ */ 33130293Sscottl 34130293Sscottl/* 35130293Sscottl * LSI 64854 DMA engine. Contains three independent channels 36130293Sscottl * designed to interface with (a) a NCR539X SCSI controller, 37130293Sscottl * (b) a AM7990 Ethernet controller, (c) Parallel port hardware.. 38130293Sscottl */ 39130293Sscottl 40130293Sscottl/* 41130293Sscottl * Register offsets to bus handle. 42130293Sscottl */ 43130293Sscottl#define L64854_REG_CSR 0 /* Control bits */ 44130293Sscottl#define L64854_REG_ADDR 4 /* DMA Address */ 45130293Sscottl#define L64854_REG_CNT 8 /* DMA count */ 46130293Sscottl#define L64854_REG_CNT_MASK 0x00ffffff /* only 24 bits */ 47130293Sscottl#define L64854_REG_ENBAR 12 /* ENET Base register */ 48130293Sscottl#define L64854_REG_TEST 12 /* SCSI Test register */ 49130293Sscottl#define L64854_REG_HCR 16 /* PP Hardware Configuration */ 50130293Sscottl#define L64854_REG_OCR 18 /* PP Operation Configuration */ 51130293Sscottl#define L64854_REG_DR 20 /* PP Data register */ 52130293Sscottl#define L64854_REG_TCR 21 /* PP Transfer Control */ 53130293Sscottl#define L64854_REG_OR 22 /* PP Output register */ 54130293Sscottl#define L64854_REG_IR 23 /* PP Input register */ 55130293Sscottl#define L64854_REG_ICR 24 /* PP Interrupt Control */ 56130293Sscottl 57130293Sscottl 58130293Sscottl/* 59130293Sscottl * Control bits common to all three channels. 60130293Sscottl */ 61130293Sscottl#define L64854_INT_PEND 0x00000001 /* Interrupt pending */ 62130293Sscottl#define L64854_ERR_PEND 0x00000002 /* Error pending */ 63130293Sscottl#define L64854_DRAINING 0x0000000c /* FIFO draining */ 64130293Sscottl#define L64854_INT_EN 0x00000010 /* Interrupt enable */ 65130293Sscottl#define L64854_INVALIDATE 0x00000020 /* Invalidate FIFO */ 66130293Sscottl#define L64854_SLAVE_ERR 0x00000040 /* Slave access size error */ 67130293Sscottl#define L64854_RESET 0x00000080 /* Reset device */ 68130293Sscottl#define L64854_WRITE 0x00000100 /* 1: xfer to memory */ 69130293Sscottl#define L64854_EN_DMA 0x00000200 /* enable DMA transfers */ 70130293Sscottl 71130293Sscottl#define L64854_BURST_SIZE 0x000c0000 /* Read/write burst size */ 72130293Sscottl#define L64854_BURST_0 0x00080000 /* no bursts (SCSI-only) */ 73130293Sscottl#define L64854_BURST_16 0x00000000 /* 16-byte bursts */ 74130293Sscottl#define L64854_BURST_32 0x00040000 /* 32-byte bursts */ 75130293Sscottl#define L64854_BURST_64 0x000c0000 /* 64-byte bursts (fas) */ 76130293Sscottl 77130293Sscottl#define L64854_RST_FAS366 0x08000000 /* FAS366 hardware reset */ 78130293Sscottl 79130293Sscottl#define L64854_DEVID 0xf0000000 /* device ID bits */ 80130293Sscottl 81130293Sscottl/* 82130293Sscottl * SCSI DMA control bits. 83130293Sscottl */ 84130293Sscottl#define D_INT_PEND L64854_INT_PEND /* interrupt pending */ 85130293Sscottl#define D_ERR_PEND L64854_ERR_PEND /* error pending */ 86130293Sscottl#define D_DRAINING L64854_DRAINING /* fifo draining */ 87130293Sscottl#define D_INT_EN L64854_INT_EN /* interrupt enable */ 88130293Sscottl#define D_INVALIDATE L64854_INVALIDATE/* invalidate fifo */ 89130293Sscottl#define D_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */ 90130293Sscottl#define D_RESET L64854_RESET /* reset scsi */ 91130293Sscottl#define D_WRITE L64854_WRITE /* 1 = dev -> mem */ 92130293Sscottl#define D_EN_DMA L64854_EN_DMA /* enable DMA requests */ 93130293Sscottl#define D_EN_CNT 0x00002000 /* enable byte counter */ 94130293Sscottl#define D_TC 0x00004000 /* terminal count */ 95130293Sscottl#define D_WIDE_EN 0x00008000 /* enable wide mode SBUS DMA (fas) */ 96130293Sscottl#define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */ 97130293Sscottl#define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */ 98130293Sscottl 99130293Sscottl#define D_DIAG 0x00100000 /* disable fifo drain on addr */ 100130293Sscottl#define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */ 101130293Sscottl#define D_FASTER 0x00400000 /* 3 clocks per transfer */ 102130293Sscottl#define D_TCI_DIS 0x00800000 /* disable intr on D_TC */ 103130293Sscottl#define D_EN_NEXT 0x01000000 /* enable auto next address */ 104130293Sscottl#define D_DMA_ON 0x02000000 /* enable dma from scsi XXX */ 105130293Sscottl#define D_DSBL_PARITY_CHK \ 106130293Sscottl 0x02000000 /* disable checking for parity on bus (default 1:fas) */ 107130293Sscottl#define D_A_LOADED 0x04000000 /* address loaded */ 108130293Sscottl#define D_NA_LOADED 0x08000000 /* next address loaded */ 109130293Sscottl#define D_HW_RESET_FAS366 \ 110130293Sscottl 0x08000000 /* hardware reset FAS366 (fas) */ 111130293Sscottl#define D_DEV_ID L64854_DEVID /* device ID */ 112130293Sscottl#define DMAREV_0 0x00000000 /* Sunray DMA */ 113130293Sscottl#define DMAREV_ESC 0x40000000 /* DMA ESC array */ 114130293Sscottl#define DMAREV_1 0x80000000 /* 'DMA' */ 115130293Sscottl#define DMAREV_PLUS 0x90000000 /* 'DMA+' */ 116130293Sscottl#define DMAREV_2 0xa0000000 /* 'DMA2' */ 117130293Sscottl#define DMAREV_HME 0xb0000000 /* 'HME' */ 118130293Sscottl 119130293Sscottl/* 120130293Sscottl * revisions 0,1 and ESC have different bits. 121130293Sscottl */ 122130293Sscottl#define D_ESC_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */ 123130293Sscottl#define D_ESC_R_PEND 0x00000400 /* rev0,1: request pending */ 124130293Sscottl#define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */ 125130293Sscottl#define D_ESC_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */ 126130293Sscottl 127130293Sscottl#define DDMACSR_BITS "\177\020" \ 128130293Sscottl "b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \ 129130293Sscottl "b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \ 130130293Sscottl "b\15ENCNT\0b\16TC\0\b\20DSBL_CSR_DRN\0" \ 131130293Sscottl "b\21DSBL_SCSI_DRN\0f\22\2BURST\0b\25TWOCYCLE\0" \ 132130293Sscottl "b\26FASTER\0b\27TCIDIS\0b\30ENNXT\0b\031DMAON\0" \ 133130293Sscottl "b\32ALOADED\0b\33NALOADED\0" 134130293Sscottl 135130293Sscottl 136130293Sscottl/* 137130293Sscottl * ENET DMA control bits. 138130293Sscottl */ 139130293Sscottl#define E_INT_PEND L64854_INT_PEND /* interrupt pending */ 140130293Sscottl#define E_ERR_PEND L64854_ERR_PEND /* error pending */ 141130293Sscottl#define E_DRAINING L64854_DRAINING /* fifo draining */ 142130293Sscottl#define E_INT_EN L64854_INT_EN /* interrupt enable */ 143130293Sscottl#define E_INVALIDATE L64854_INVALIDATE/* invalidate fifo */ 144130293Sscottl#define E_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */ 145130293Sscottl#define E_RESET L64854_RESET /* reset ENET */ 146130293Sscottl#define E_reserved1 0x00000300 /* */ 147130293Sscottl#define E_DRAIN 0x00000400 /* force Ecache drain */ 148130293Sscottl#define E_DSBL_WR_DRN 0x00000800 /* disable Ecache drain on .. */ 149130293Sscottl#define E_DSBL_RD_DRN 0x00001000 /* disable Ecache drain on .. */ 150130293Sscottl#define E_reserved2 0x00006000 /* */ 151130293Sscottl#define E_ILACC 0x00008000 /* ... */ 152130293Sscottl#define E_DSBL_BUF_WR 0x00010000 /* no buffering of slave writes */ 153130293Sscottl#define E_DSBL_WR_INVAL 0x00020000 /* no Ecache invalidate on slave writes */ 154130293Sscottl 155130293Sscottl#define E_reserved3 0x00100000 /* */ 156130293Sscottl#define E_LOOP_TEST 0x00200000 /* loopback mode */ 157130293Sscottl#define E_TP_AUI 0x00400000 /* 1 for TP, 0 for AUI */ 158130293Sscottl#define E_reserved4 0x0c800000 /* */ 159130293Sscottl#define E_DEV_ID L64854_DEVID /* ID bits */ 160130293Sscottl 161130293Sscottl#define EDMACSR_BITS "\177\020" \ 162130293Sscottl "b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \ 163130293Sscottl "b\06SLVERR\0b\07RST\0b\10WRITE\0b\12DRAIN\0" \ 164130293Sscottl "b\13DSBL_WR_DRN\0b\14DSBL_RD_DRN\0b\17ILACC\0" \ 165130293Sscottl "b\20DSBL_BUF_WR\0b\21DSBL_WR_INVAL\0" \ 166130293Sscottl "b\25LOOPTEST\0b\26TP\0" 167130293Sscottl 168130293Sscottl/* 169130293Sscottl * PP DMA control bits. 170130293Sscottl */ 171130293Sscottl#define P_INT_PEND L64854_INT_PEND /* interrupt pending */ 172130293Sscottl#define P_ERR_PEND L64854_ERR_PEND /* error pending */ 173130293Sscottl#define P_DRAINING L64854_DRAINING /* fifo draining */ 174130293Sscottl#define P_INT_EN L64854_INT_EN /* interrupt enable */ 175130293Sscottl#define P_INVALIDATE L64854_INVALIDATE/* invalidate fifo */ 176130293Sscottl#define P_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */ 177130293Sscottl#define P_RESET L64854_RESET /* reset PP */ 178130293Sscottl#define P_WRITE L64854_WRITE /* 1: xfer to memory */ 179130293Sscottl#define P_EN_DMA L64854_EN_DMA /* enable DMA transfers */ 180130293Sscottl#define P_reserved1 0x00001c00 /* */ 181130293Sscottl#define P_EN_CNT 0x00002000 /* enable counter */ 182130293Sscottl#define P_TC 0x00004000 /* terminal count */ 183130293Sscottl#define P_reserved2 0x00038000 /* */ 184130293Sscottl 185130293Sscottl#define P_DIAG 0x00100000 /* ... */ 186130293Sscottl#define P_reserved3 0x00600000 /* */ 187130293Sscottl#define P_TCI_DIS 0x00800000 /* no interrupt on terminal count */ 188130293Sscottl#define P_EN_NEXT 0x01000000 /* enable DMA chaining */ 189130293Sscottl#define P_DMA_ON 0x02000000 /* DMA xfers enabled */ 190130293Sscottl#define P_A_LOADED 0x04000000 /* addr and byte count valid */ 191130293Sscottl#define P_NA_LOADED 0x08000000 /* next addr & count valid but not used */ 192130293Sscottl#define P_DEV_ID L64854_DEVID /* ID bits */ 193130293Sscottl 194130293Sscottl#define PDMACSR_BITS "\177\020" \ 195130293Sscottl "b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \ 196130293Sscottl "b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \ 197130293Sscottl "b\15ENCNT\0b\16TC\0\b\24DIAG\0b\27TCIDIS\0" \ 198130293Sscottl "b\30ENNXT\0b\031DMAON\0b\32ALOADED\0b\33NALOADED\0" 199