schizo.c revision 206020
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 206020 2010-03-31 22:32:56Z marius $"); 36 37/* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39 * PCI 2.2 bridges 40 */ 41 42#include "opt_ofw_pci.h" 43#include "opt_schizo.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/rman.h> 55#include <sys/time.h> 56#include <sys/timetc.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/fsr.h> 66#include <machine/iommureg.h> 67#include <machine/iommuvar.h> 68#include <machine/resource.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73#include <sparc64/pci/ofw_pci.h> 74#include <sparc64/pci/schizoreg.h> 75#include <sparc64/pci/schizovar.h> 76 77#include "pcib_if.h" 78 79static const struct schizo_desc *schizo_get_desc(device_t); 80static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 81 driver_filter_t); 82static driver_filter_t schizo_dma_sync_stub; 83static driver_filter_t ichip_dma_sync_stub; 84static void schizo_intr_enable(void *); 85static void schizo_intr_disable(void *); 86static void schizo_intr_assign(void *); 87static void schizo_intr_clear(void *); 88static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 89static int schizo_get_intrmap(struct schizo_softc *, u_int, 90 bus_addr_t *, bus_addr_t *); 91static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 92static timecounter_get_t schizo_get_timecount; 93 94/* Interrupt handlers */ 95static driver_filter_t schizo_pci_bus; 96static driver_filter_t schizo_ue; 97static driver_filter_t schizo_ce; 98static driver_filter_t schizo_host_bus; 99static driver_filter_t schizo_cdma; 100 101/* IOMMU support */ 102static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 103 104/* 105 * Methods 106 */ 107static device_probe_t schizo_probe; 108static device_attach_t schizo_attach; 109static bus_read_ivar_t schizo_read_ivar; 110static bus_setup_intr_t schizo_setup_intr; 111static bus_teardown_intr_t schizo_teardown_intr; 112static bus_alloc_resource_t schizo_alloc_resource; 113static bus_activate_resource_t schizo_activate_resource; 114static bus_deactivate_resource_t schizo_deactivate_resource; 115static bus_release_resource_t schizo_release_resource; 116static bus_describe_intr_t schizo_describe_intr; 117static bus_get_dma_tag_t schizo_get_dma_tag; 118static pcib_maxslots_t schizo_maxslots; 119static pcib_read_config_t schizo_read_config; 120static pcib_write_config_t schizo_write_config; 121static pcib_route_interrupt_t schizo_route_interrupt; 122static ofw_bus_get_node_t schizo_get_node; 123 124static device_method_t schizo_methods[] = { 125 /* Device interface */ 126 DEVMETHOD(device_probe, schizo_probe), 127 DEVMETHOD(device_attach, schizo_attach), 128 DEVMETHOD(device_shutdown, bus_generic_shutdown), 129 DEVMETHOD(device_suspend, bus_generic_suspend), 130 DEVMETHOD(device_resume, bus_generic_resume), 131 132 /* Bus interface */ 133 DEVMETHOD(bus_print_child, bus_generic_print_child), 134 DEVMETHOD(bus_read_ivar, schizo_read_ivar), 135 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 136 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 137 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 138 DEVMETHOD(bus_activate_resource, schizo_activate_resource), 139 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 140 DEVMETHOD(bus_release_resource, schizo_release_resource), 141 DEVMETHOD(bus_describe_intr, schizo_describe_intr), 142 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 143 144 /* pcib interface */ 145 DEVMETHOD(pcib_maxslots, schizo_maxslots), 146 DEVMETHOD(pcib_read_config, schizo_read_config), 147 DEVMETHOD(pcib_write_config, schizo_write_config), 148 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 149 150 /* ofw_bus interface */ 151 DEVMETHOD(ofw_bus_get_node, schizo_get_node), 152 153 KOBJMETHOD_END 154}; 155 156static devclass_t schizo_devclass; 157 158DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 159 sizeof(struct schizo_softc)); 160DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 161 162static SLIST_HEAD(, schizo_softc) schizo_softcs = 163 SLIST_HEAD_INITIALIZER(schizo_softcs); 164 165static const struct intr_controller schizo_ic = { 166 schizo_intr_enable, 167 schizo_intr_disable, 168 schizo_intr_assign, 169 schizo_intr_clear 170}; 171 172struct schizo_icarg { 173 struct schizo_softc *sica_sc; 174 bus_addr_t sica_map; 175 bus_addr_t sica_clr; 176}; 177 178struct schizo_dma_sync { 179 struct schizo_softc *sds_sc; 180 driver_filter_t *sds_handler; 181 void *sds_arg; 182 void *sds_cookie; 183 uint64_t sds_syncval; 184 device_t sds_ppb; /* farest PCI-PCI bridge */ 185 uint8_t sds_bus; /* bus of farest PCI dev. */ 186 uint8_t sds_slot; /* slot of farest PCI dev. */ 187 uint8_t sds_func; /* func. of farest PCI dev. */ 188}; 189 190#define SCHIZO_PERF_CNT_QLTY 100 191 192#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 193 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 194#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 195 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 196 197#define SCHIZO_PCI_READ_8(sc, offs) \ 198 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 199#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 200 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 201#define SCHIZO_CTRL_READ_8(sc, offs) \ 202 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 203#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 204 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 205#define SCHIZO_PCICFG_READ_8(sc, offs) \ 206 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 207#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 208 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 209#define SCHIZO_ICON_READ_8(sc, offs) \ 210 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 211#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 212 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 213 214struct schizo_desc { 215 const char *sd_string; 216 int sd_mode; 217 const char *sd_name; 218}; 219 220static const struct schizo_desc const schizo_compats[] = { 221 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 222 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 223 { NULL, 0, NULL } 224}; 225 226static const struct schizo_desc * 227schizo_get_desc(device_t dev) 228{ 229 const struct schizo_desc *desc; 230 const char *compat; 231 232 compat = ofw_bus_get_compat(dev); 233 if (compat == NULL) 234 return (NULL); 235 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 236 if (strcmp(desc->sd_string, compat) == 0) 237 return (desc); 238 return (NULL); 239} 240 241static int 242schizo_probe(device_t dev) 243{ 244 const char *dtype; 245 246 dtype = ofw_bus_get_type(dev); 247 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 248 schizo_get_desc(dev) != NULL) { 249 device_set_desc(dev, "Sun Host-PCI bridge"); 250 return (0); 251 } 252 return (ENXIO); 253} 254 255static int 256schizo_attach(device_t dev) 257{ 258 struct ofw_pci_ranges *range; 259 const struct schizo_desc *desc; 260 struct schizo_softc *asc, *sc, *osc; 261 struct timecounter *tc; 262 uint64_t ino_bitmap, reg; 263 phandle_t node; 264 uint32_t prop, prop_array[2]; 265 int i, j, mode, rid, tsbsize; 266 267 sc = device_get_softc(dev); 268 node = ofw_bus_get_node(dev); 269 desc = schizo_get_desc(dev); 270 mode = desc->sd_mode; 271 272 sc->sc_dev = dev; 273 sc->sc_node = node; 274 sc->sc_mode = mode; 275 sc->sc_flags = 0; 276 277 /* 278 * The Schizo has three register banks: 279 * (0) per-PBM PCI configuration and status registers, but for bus B 280 * shared with the UPA64s interrupt mapping register banks 281 * (1) shared Schizo controller configuration and status registers 282 * (2) per-PBM PCI configuration space 283 * 284 * The Tomatillo has four register banks: 285 * (0) per-PBM PCI configuration and status registers 286 * (1) per-PBM Tomatillo controller configuration registers, but on 287 * machines having the `jbusppm' device shared with its Estar 288 * register bank for bus A 289 * (2) per-PBM PCI configuration space 290 * (3) per-PBM interrupt concentrator registers 291 */ 292 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 293 20) & 1; 294 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 295 i++) { 296 rid = i; 297 sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 298 SYS_RES_MEMORY, &rid, 299 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 300 i == STX_PCI) || i == STX_CTRL)) || 301 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 302 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 303 if (sc->sc_mem_res[i] == NULL) 304 panic("%s: could not allocate register bank %d", 305 __func__, i); 306 } 307 308 /* 309 * Match other Schizos that are already configured against 310 * the controller base physical address. This will be the 311 * same for a pair of devices that share register space. 312 */ 313 osc = NULL; 314 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 315 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 316 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 317 /* Found partner. */ 318 osc = asc; 319 break; 320 } 321 } 322 if (osc == NULL) { 323 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 324 M_NOWAIT | M_ZERO); 325 if (sc->sc_mtx == NULL) 326 panic("%s: could not malloc mutex", __func__); 327 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 328 } else { 329 if (sc->sc_mode != SCHIZO_MODE_SCZ) 330 panic("%s: no partner expected", __func__); 331 if (mtx_initialized(osc->sc_mtx) == 0) 332 panic("%s: mutex not initialized", __func__); 333 sc->sc_mtx = osc->sc_mtx; 334 } 335 336 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 337 panic("%s: could not determine IGN", __func__); 338 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 339 -1) 340 panic("%s: could not determine version", __func__); 341 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 342 prop = 33000000; 343 344 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 345 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 346 prop / 1000 / 1000); 347 348 /* Set up the PCI interrupt retry timer. */ 349#ifdef SCHIZO_DEBUG 350 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 351 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 352#endif 353 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 354 355 /* Set up the PCI control register. */ 356 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 357 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 358 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 359 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 360 if (OF_getproplen(node, "no-bus-parking") < 0) 361 reg |= STX_PCI_CTRL_ARB_PARK; 362 if (mode == SCHIZO_MODE_TOM) { 363 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 364 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 365 reg |= TOM_PCI_CTRL_DTO_IEN; 366 else 367 reg |= STX_PCI_CTRL_PTO; 368 } 369#ifdef SCHIZO_DEBUG 370 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 371 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 372 (unsigned long long)reg); 373#endif 374 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 375 376 /* Set up the PCI diagnostic register. */ 377 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 378 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 379 STX_PCI_DIAG_INTRSYNC_DIS); 380#ifdef SCHIZO_DEBUG 381 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 382 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 383 (unsigned long long)reg); 384#endif 385 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 386 387 /* 388 * On Tomatillo clear the I/O prefetch lengths (workaround for a 389 * Jalapeno bug). 390 */ 391 if (mode == SCHIZO_MODE_TOM) 392 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 393 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 394 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 395 396 /* 397 * Hunt through all the interrupt mapping regs and register 398 * the interrupt controller for our interrupt vectors. We do 399 * this early in order to be able to catch stray interrupts. 400 * This is complicated by the fact that a pair of Schizo PBMs 401 * shares one IGN. 402 */ 403 i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 404 sizeof(prop_array)); 405 if (i != -1) 406 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 407 else { 408 /* 409 * If the ino-bitmap property is missing, just provide the 410 * default set of interrupts for this controller and let 411 * schizo_setup_intr() take care of child interrupts. 412 */ 413 if (sc->sc_half == 0) 414 ino_bitmap = (1ULL << STX_UE_INO) | 415 (1ULL << STX_CE_INO) | 416 (1ULL << STX_PCIERR_A_INO) | 417 (1ULL << STX_BUS_INO); 418 else 419 ino_bitmap = 1ULL << STX_PCIERR_B_INO; 420 } 421 for (i = 0; i <= STX_MAX_INO; i++) { 422 if ((ino_bitmap & (1ULL << i)) == 0) 423 continue; 424 if (i == STX_FB0_INO || i == STX_FB1_INO) 425 /* Leave for upa(4). */ 426 continue; 427 j = schizo_intr_register(sc, i); 428 if (j != 0) 429 device_printf(dev, "could not register interrupt " 430 "controller for INO %d (%d)\n", i, j); 431 } 432 433 /* 434 * Setup Safari/JBus performance counter 0 in bus cycle counting 435 * mode as timecounter. Unfortunately, this is broken with at 436 * least the version 4 Tomatillos found in Fire V120 and Blade 437 * 1500, which apparently actually count some different event at 438 * ~0.5 and 3MHz respectively instead (also when running in full 439 * power mode). Besides, one counter seems to be shared by a 440 * "pair" of Tomatillos, too. 441 */ 442 if (sc->sc_half == 0) { 443 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 444 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 445 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 446 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 447 if (tc == NULL) 448 panic("%s: could not malloc timecounter", __func__); 449 tc->tc_get_timecount = schizo_get_timecount; 450 tc->tc_poll_pps = NULL; 451 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 452 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 453 sizeof(prop)) == -1) 454 panic("%s: could not determine clock frequency", 455 __func__); 456 tc->tc_frequency = prop; 457 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 458 if (mode == SCHIZO_MODE_SCZ) 459 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 460 else 461 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 462 tc->tc_priv = sc; 463 tc_init(tc); 464 } 465 466 /* 467 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 468 * one per PBM. Schizo and XMITS additionally have a streaming 469 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 470 * affected by several errata and basically unusable though. 471 */ 472 sc->sc_is.is_flags = IOMMU_PRESERVE_PROM; 473 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 474 sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0; 475 if (OF_getproplen(node, "no-streaming-cache") < 0 && 476 !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 477 sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 478 479#define TSBCASE(x) \ 480 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 481 tsbsize = (x); \ 482 break; \ 483 484 i = OF_getprop(node, "virtual-dma", (void *)prop_array, 485 sizeof(prop_array)); 486 if (i == -1 || i != sizeof(prop_array)) 487 schizo_iommu_init(sc, 7, -1); 488 else { 489 switch (prop_array[1]) { 490 TSBCASE(1); 491 TSBCASE(2); 492 TSBCASE(3); 493 TSBCASE(4); 494 TSBCASE(5); 495 TSBCASE(6); 496 TSBCASE(7); 497 TSBCASE(8); 498 default: 499 panic("%s: unsupported DVMA size 0x%x", 500 __func__, prop_array[1]); 501 /* NOTREACHED */ 502 } 503 schizo_iommu_init(sc, tsbsize, prop_array[0]); 504 } 505 506#undef TSBCASE 507 508 /* Initialize memory and I/O rmans. */ 509 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 510 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 511 if (rman_init(&sc->sc_pci_io_rman) != 0 || 512 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 513 panic("%s: failed to set up I/O rman", __func__); 514 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 515 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 516 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 517 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 518 panic("%s: failed to set up memory rman", __func__); 519 520 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 521 /* 522 * Make sure that the expected ranges are present. The 523 * OFW_PCI_CS_MEM64 one is not currently used though. 524 */ 525 if (i != STX_NRANGE) 526 panic("%s: unsupported number of ranges", __func__); 527 /* 528 * Find the addresses of the various bus spaces. 529 * There should not be multiple ones of one kind. 530 * The physical start addresses of the ranges are the configuration, 531 * memory and I/O handles. 532 */ 533 for (i = 0; i < STX_NRANGE; i++) { 534 j = OFW_PCI_RANGE_CS(&range[i]); 535 if (sc->sc_pci_bh[j] != 0) 536 panic("%s: duplicate range for space %d", 537 __func__, j); 538 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 539 } 540 free(range, M_OFWPROP); 541 542 /* Register the softc, this is needed for paired Schizos. */ 543 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 544 545 /* Allocate our tags. */ 546 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 547 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 548 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 549 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 550 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 551 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 552 panic("%s: bus_dma_tag_create failed", __func__); 553 /* Customize the tag. */ 554 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 555 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 556 557 /* 558 * Get the bus range from the firmware. 559 * NB: Tomatillos don't support PCI bus reenumeration. 560 */ 561 i = OF_getprop(node, "bus-range", (void *)prop_array, 562 sizeof(prop_array)); 563 if (i == -1) 564 panic("%s: could not get bus-range", __func__); 565 if (i != sizeof(prop_array)) 566 panic("%s: broken bus-range (%d)", __func__, i); 567 sc->sc_pci_secbus = prop_array[0]; 568 sc->sc_pci_subbus = prop_array[1]; 569 if (bootverbose) 570 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 571 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 572 573 /* Clear any pending PCI error bits. */ 574 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 575 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 576 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 577 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 578 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 579 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 580 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 581 582 /* 583 * Establish handlers for interesting interrupts... 584 * Someone at Sun clearly was smoking crack; with Schizos PCI 585 * bus error interrupts for one PBM can be routed to the other 586 * PBM though we obviously need to use the softc of the former 587 * as the argument for the interrupt handler and the softc of 588 * the latter as the argument for the interrupt controller. 589 */ 590 if (sc->sc_half == 0) { 591 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 592 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 593 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 594 sica_sc == osc)) 595 /* 596 * We are the driver for PBM A and either also 597 * registered the interrupt controller for us or 598 * the driver for PBM B has probed first and 599 * registered it for us. 600 */ 601 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 602 schizo_pci_bus); 603 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 604 osc != NULL) 605 /* 606 * We are the driver for PBM A but registered 607 * the interrupt controller for PBM B, i.e. the 608 * driver for PBM B attached first but couldn't 609 * set up a handler for PBM B. 610 */ 611 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 612 schizo_pci_bus); 613 } else { 614 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 615 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 616 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 617 sica_sc == osc)) 618 /* 619 * We are the driver for PBM B and either also 620 * registered the interrupt controller for us or 621 * the driver for PBM A has probed first and 622 * registered it for us. 623 */ 624 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 625 schizo_pci_bus); 626 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 627 osc != NULL) 628 /* 629 * We are the driver for PBM B but registered 630 * the interrupt controller for PBM A, i.e. the 631 * driver for PBM A attached first but couldn't 632 * set up a handler for PBM A. 633 */ 634 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 635 schizo_pci_bus); 636 } 637 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 638 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 639 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 640 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 641 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 642 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 643 644 /* 645 * According to the Schizo Errata I-13, consistent DMA flushing/ 646 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 647 * so we can't use it and need to live with the consequences. With 648 * Schizo version >= 5, CDMA flushing/syncing is usable but requires 649 * the workaround described in Schizo Errata I-23. With Tomatillo 650 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 651 * version <= 4 (i.e. revision <= 2.3) bridges additionally require 652 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 653 */ 654 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 655 sc->sc_mode == SCHIZO_MODE_TOM || 656 sc->sc_mode == SCHIZO_MODE_XMS) { 657 sc->sc_flags |= SCHIZO_FLAGS_CDMA; 658 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 659 sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 660 /* 661 * Some firmware versions include the CDMA interrupt 662 * at RID 4 but most don't. With the latter we add 663 * it ourselves at the spare RID 5. 664 */ 665 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 666 4)); 667 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 668 (void)schizo_get_intrmap(sc, i, NULL, 669 &sc->sc_cdma_clr); 670 schizo_set_intr(sc, 4, i, schizo_cdma); 671 } else { 672 i = STX_CDMA_A_INO + sc->sc_half; 673 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 674 INTMAP_VEC(sc->sc_ign, i), 1) != 0) 675 panic("%s: failed to add CDMA " 676 "interrupt", __func__); 677 j = schizo_intr_register(sc, i); 678 if (j != 0) 679 panic("%s: could not register " 680 "interrupt controller for CDMA " 681 "(%d)", __func__, j); 682 (void)schizo_get_intrmap(sc, i, NULL, 683 &sc->sc_cdma_clr); 684 schizo_set_intr(sc, 5, i, schizo_cdma); 685 } 686 } 687 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 688 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 689 } 690 691 /* 692 * Set the latency timer register as this isn't always done by the 693 * firmware. 694 */ 695 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 696 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 697 698 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 699 700 /* 701 * At least when booting Fire V890 from disk a Schizo comes up with 702 * a PCI bus error residing which triggers as soon as we register 703 * schizo_pci_bus() even when clearing it from all involved registers 704 * beforehand (but is quiet once it has fired). Thus we make PCI bus 705 * errors non-fatal until we actually touch the bus. 706 */ 707 sc->sc_flags |= SCHIZO_FLAGS_ARMED; 708 device_add_child(dev, "pci", -1); 709 return (bus_generic_attach(dev)); 710} 711 712static void 713schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 714 driver_filter_t handler) 715{ 716 u_long vec; 717 int rid; 718 719 rid = index; 720 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 721 SYS_RES_IRQ, &rid, RF_ACTIVE); 722 if (sc->sc_irq_res[index] == NULL || 723 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 724 INTIGN(vec) != sc->sc_ign || 725 intr_vectors[vec].iv_ic != &schizo_ic || 726 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 727 INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 728 &sc->sc_ihand[index]) != 0) 729 panic("%s: failed to set up interrupt %d", __func__, index); 730} 731 732static int 733schizo_intr_register(struct schizo_softc *sc, u_int ino) 734{ 735 struct schizo_icarg *sica; 736 bus_addr_t intrclr, intrmap; 737 int error; 738 739 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 740 return (ENXIO); 741 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 742 if (sica == NULL) 743 return (ENOMEM); 744 sica->sica_sc = sc; 745 sica->sica_map = intrmap; 746 sica->sica_clr = intrclr; 747#ifdef SCHIZO_DEBUG 748 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 749 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 750 (u_long)intrclr); 751#endif 752 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 753 &schizo_ic, sica)); 754 if (error != 0) 755 free(sica, M_DEVBUF); 756 return (error); 757} 758 759static int 760schizo_get_intrmap(struct schizo_softc *sc, u_int ino, 761 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 762{ 763 bus_addr_t intrclr, intrmap; 764 uint64_t mr; 765 766 /* 767 * XXX we only look for INOs rather than INRs since the firmware 768 * may not provide the IGN and the IGN is constant for all devices 769 * on that PCI controller. 770 */ 771 772 if (ino > STX_MAX_INO) { 773 device_printf(sc->sc_dev, "out of range INO %d requested\n", 774 ino); 775 return (0); 776 } 777 778 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 779 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 780 mr = SCHIZO_PCI_READ_8(sc, intrmap); 781 if (INTINO(mr) != ino) { 782 device_printf(sc->sc_dev, 783 "interrupt map entry does not match INO (%d != %d)\n", 784 (int)INTINO(mr), ino); 785 return (0); 786 } 787 788 if (intrmapptr != NULL) 789 *intrmapptr = intrmap; 790 if (intrclrptr != NULL) 791 *intrclrptr = intrclr; 792 return (1); 793} 794 795/* 796 * Interrupt handlers 797 */ 798static int 799schizo_pci_bus(void *arg) 800{ 801 struct schizo_softc *sc = arg; 802 uint64_t afar, afsr, csr, iommu; 803 uint32_t status; 804 805 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 806 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 807 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 808 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 809 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 810 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 811 if ((sc->sc_flags & SCHIZO_FLAGS_ARMED) == 0) 812 goto clear_error; 813 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 814 if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 815 goto clear_error; 816 817 /* These are non-fatal if target abort was signaled. */ 818 if ((status & PCIM_STATUS_STABORT) != 0 && 819 ((iommu & TOM_PCI_IOMMU_ERRMASK) == 820 TOM_PCI_IOMMU_INVALID_ERR || 821 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 822 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 823 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 824 goto clear_error; 825 } 826 } 827 828 panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 829 "IOMMU %#llx STATUS %#llx", device_get_nameunit(sc->sc_dev), 830 'A' + sc->sc_half, (unsigned long long)afar, 831 (unsigned long long)afsr, (unsigned long long)csr, 832 (unsigned long long)iommu, (unsigned long long)status); 833 834 clear_error: 835 if (bootverbose) 836 device_printf(sc->sc_dev, 837 "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 838 "STATUS %#llx", 'A' + sc->sc_half, 839 (unsigned long long)afar, (unsigned long long)afsr, 840 (unsigned long long)csr, (unsigned long long)status); 841 /* Clear the error bits that we caught. */ 842 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 843 STX_CS_FUNC, PCIR_STATUS, status, 2); 844 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 845 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 846 return (FILTER_HANDLED); 847} 848 849static int 850schizo_ue(void *arg) 851{ 852 struct schizo_softc *sc = arg; 853 uint64_t afar, afsr; 854 int i; 855 856 mtx_lock_spin(sc->sc_mtx); 857 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 858 for (i = 0; i < 1000; i++) 859 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 860 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 861 break; 862 mtx_unlock_spin(sc->sc_mtx); 863 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 864 device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 865 (unsigned long long)afsr); 866 return (FILTER_HANDLED); 867} 868 869static int 870schizo_ce(void *arg) 871{ 872 struct schizo_softc *sc = arg; 873 uint64_t afar, afsr; 874 int i; 875 876 mtx_lock_spin(sc->sc_mtx); 877 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 878 for (i = 0; i < 1000; i++) 879 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 880 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 881 break; 882 device_printf(sc->sc_dev, 883 "correctable DMA error AFAR %#llx AFSR %#llx\n", 884 (unsigned long long)afar, (unsigned long long)afsr); 885 /* Clear the error bits that we caught. */ 886 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 887 mtx_unlock_spin(sc->sc_mtx); 888 return (FILTER_HANDLED); 889} 890 891static int 892schizo_host_bus(void *arg) 893{ 894 struct schizo_softc *sc = arg; 895 uint64_t errlog; 896 897 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 898 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 899 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 900 (unsigned long long)errlog); 901 return (FILTER_HANDLED); 902} 903 904static int 905schizo_cdma(void *arg) 906{ 907 struct schizo_softc *sc = arg; 908 909 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 910 return (FILTER_HANDLED); 911} 912 913static void 914schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 915{ 916 917 /* Punch in our copies. */ 918 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 919 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 920 sc->sc_is.is_iommu = STX_PCI_IOMMU; 921 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 922 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 923 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 924 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 925 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 926 927 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 928 dvmabase, 0); 929} 930 931static int 932schizo_maxslots(device_t dev) 933{ 934 struct schizo_softc *sc; 935 936 sc = device_get_softc(dev); 937 if (sc->sc_mode == SCHIZO_MODE_SCZ) 938 return (sc->sc_half == 0 ? 4 : 6); 939 940 /* XXX: is this correct? */ 941 return (PCI_SLOTMAX); 942} 943 944static uint32_t 945schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 946 int width) 947{ 948 struct schizo_softc *sc; 949 bus_space_handle_t bh; 950 u_long offset = 0; 951 uint32_t r, wrd; 952 int i; 953 uint16_t shrt; 954 uint8_t byte; 955 956 sc = device_get_softc(dev); 957 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 958 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 959 return (-1); 960 961 /* 962 * The Schizo bridges contain a dupe of their header at 0x80. 963 */ 964 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 965 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 966 reg + width > 0x80) 967 return (0); 968 969 offset = STX_CONF_OFF(bus, slot, func, reg); 970 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 971 switch (width) { 972 case 1: 973 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 974 r = byte; 975 break; 976 case 2: 977 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 978 r = shrt; 979 break; 980 case 4: 981 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 982 r = wrd; 983 break; 984 default: 985 panic("%s: bad width", __func__); 986 /* NOTREACHED */ 987 } 988 989 if (i) { 990#ifdef SCHIZO_DEBUG 991 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 992 __func__, bus, slot, func, reg); 993#endif 994 r = -1; 995 } 996 return (r); 997} 998 999static void 1000schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1001 u_int reg, uint32_t val, int width) 1002{ 1003 struct schizo_softc *sc; 1004 bus_space_handle_t bh; 1005 u_long offset = 0; 1006 1007 sc = device_get_softc(dev); 1008 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1009 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1010 return; 1011 1012 offset = STX_CONF_OFF(bus, slot, func, reg); 1013 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1014 switch (width) { 1015 case 1: 1016 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1017 break; 1018 case 2: 1019 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1020 break; 1021 case 4: 1022 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1023 break; 1024 default: 1025 panic("%s: bad width", __func__); 1026 /* NOTREACHED */ 1027 } 1028} 1029 1030static int 1031schizo_route_interrupt(device_t bridge, device_t dev, int pin) 1032{ 1033 struct schizo_softc *sc; 1034 struct ofw_pci_register reg; 1035 ofw_pci_intr_t pintr, mintr; 1036 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1037 1038 sc = device_get_softc(bridge); 1039 pintr = pin; 1040 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1041 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1042 maskbuf)) 1043 return (mintr); 1044 1045 device_printf(bridge, "could not route pin %d for device %d.%d\n", 1046 pin, pci_get_slot(dev), pci_get_function(dev)); 1047 return (PCI_INVALID_IRQ); 1048} 1049 1050static int 1051schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1052{ 1053 struct schizo_softc *sc; 1054 1055 sc = device_get_softc(dev); 1056 switch (which) { 1057 case PCIB_IVAR_DOMAIN: 1058 *result = device_get_unit(dev); 1059 return (0); 1060 case PCIB_IVAR_BUS: 1061 *result = sc->sc_pci_secbus; 1062 return (0); 1063 } 1064 return (ENOENT); 1065} 1066 1067static int 1068schizo_dma_sync_stub(void *arg) 1069{ 1070 struct timeval cur, end; 1071 struct schizo_dma_sync *sds = arg; 1072 struct schizo_softc *sc = sds->sds_sc; 1073 uint32_t state; 1074 1075 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1076 sds->sds_func, PCIR_VENDOR, 2); 1077 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1078 SCHIZO_CDMA_STATE_DONE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1079 ; 1080 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1081 microuptime(&cur); 1082 end.tv_sec = 1; 1083 end.tv_usec = 0; 1084 timevaladd(&end, &cur); 1085 for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1086 SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1087 microuptime(&cur); 1088 if (state != SCHIZO_CDMA_STATE_DONE) 1089 panic("%s: DMA does not sync", __func__); 1090 return (sds->sds_handler(sds->sds_arg)); 1091} 1092 1093#define VIS_BLOCKSIZE 64 1094 1095static int 1096ichip_dma_sync_stub(void *arg) 1097{ 1098 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1099 struct timeval cur, end; 1100 struct schizo_dma_sync *sds = arg; 1101 struct schizo_softc *sc = sds->sds_sc; 1102 register_t reg, s; 1103 1104 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1105 sds->sds_func, PCIR_VENDOR, 2); 1106 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1107 microuptime(&cur); 1108 end.tv_sec = 1; 1109 end.tv_usec = 0; 1110 timevaladd(&end, &cur); 1111 for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1112 sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1113 microuptime(&cur); 1114 if ((reg & sds->sds_syncval) != 0) 1115 panic("%s: DMA does not sync", __func__); 1116 1117 if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1118 s = intr_disable(); 1119 reg = rd(fprs); 1120 wr(fprs, reg | FPRS_FEF, 0); 1121 __asm __volatile("stda %%f0, [%0] %1" 1122 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1123 membar(Sync); 1124 wr(fprs, reg, 0); 1125 intr_restore(s); 1126 } 1127 return (sds->sds_handler(sds->sds_arg)); 1128} 1129 1130static void 1131schizo_intr_enable(void *arg) 1132{ 1133 struct intr_vector *iv = arg; 1134 struct schizo_icarg *sica = iv->iv_icarg; 1135 1136 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1137 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1138} 1139 1140static void 1141schizo_intr_disable(void *arg) 1142{ 1143 struct intr_vector *iv = arg; 1144 struct schizo_icarg *sica = iv->iv_icarg; 1145 1146 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1147} 1148 1149static void 1150schizo_intr_assign(void *arg) 1151{ 1152 struct intr_vector *iv = arg; 1153 struct schizo_icarg *sica = iv->iv_icarg; 1154 1155 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1156 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1157} 1158 1159static void 1160schizo_intr_clear(void *arg) 1161{ 1162 struct intr_vector *iv = arg; 1163 struct schizo_icarg *sica = iv->iv_icarg; 1164 1165 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1166} 1167 1168static int 1169schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1170 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1171 void **cookiep) 1172{ 1173 devclass_t pci_devclass; 1174 device_t cdev, pdev, pcidev; 1175 struct schizo_dma_sync *sds; 1176 struct schizo_softc *sc; 1177 u_long vec; 1178 int error, found; 1179 1180 sc = device_get_softc(dev); 1181 /* 1182 * Make sure the vector is fully specified. 1183 */ 1184 vec = rman_get_start(ires); 1185 if (INTIGN(vec) != sc->sc_ign) { 1186 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1187 return (EINVAL); 1188 } 1189 1190 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1191 /* 1192 * Ensure we use the right softc in case the interrupt 1193 * is routed to our companion PBM for some odd reason. 1194 */ 1195 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1196 sica_sc; 1197 } else if (intr_vectors[vec].iv_ic == NULL) { 1198 /* 1199 * Work around broken firmware which misses entries in 1200 * the ino-bitmap. 1201 */ 1202 error = schizo_intr_register(sc, INTINO(vec)); 1203 if (error != 0) { 1204 device_printf(dev, "could not register interrupt " 1205 "controller for vector 0x%lx (%d)\n", vec, error); 1206 return (error); 1207 } 1208 if (bootverbose) 1209 device_printf(dev, "belatedly registered as " 1210 "interrupt controller for vector 0x%lx\n", vec); 1211 } else { 1212 device_printf(dev, 1213 "invalid interrupt controller for vector 0x%lx\n", vec); 1214 return (EINVAL); 1215 } 1216 1217 /* 1218 * Install a a wrapper for CDMA flushing/syncing for devices 1219 * behind PCI-PCI bridges if possible. 1220 */ 1221 pcidev = NULL; 1222 found = 0; 1223 pci_devclass = devclass_find("pci"); 1224 for (cdev = child; cdev != dev; cdev = pdev) { 1225 pdev = device_get_parent(cdev); 1226 if (pcidev == NULL) { 1227 if (device_get_devclass(pdev) != pci_devclass) 1228 continue; 1229 pcidev = cdev; 1230 continue; 1231 } 1232 if (pci_get_class(cdev) == PCIC_BRIDGE && 1233 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1234 found = 1; 1235 } 1236 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1237 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1238 if (sds == NULL) 1239 return (ENOMEM); 1240 if (found != 0 && pcidev != NULL) { 1241 sds->sds_sc = sc; 1242 sds->sds_arg = arg; 1243 sds->sds_ppb = 1244 device_get_parent(device_get_parent(pcidev)); 1245 sds->sds_bus = pci_get_bus(pcidev); 1246 sds->sds_slot = pci_get_slot(pcidev); 1247 sds->sds_func = pci_get_function(pcidev); 1248 sds->sds_syncval = 1ULL << INTINO(vec); 1249 if (bootverbose) 1250 device_printf(dev, "installed DMA sync " 1251 "wrapper for device %d.%d on bus %d\n", 1252 sds->sds_slot, sds->sds_func, 1253 sds->sds_bus); 1254 1255#define DMA_SYNC_STUB \ 1256 (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1257 ichip_dma_sync_stub) 1258 1259 if (intr == NULL) { 1260 sds->sds_handler = filt; 1261 error = bus_generic_setup_intr(dev, child, 1262 ires, flags, DMA_SYNC_STUB, intr, sds, 1263 cookiep); 1264 } else { 1265 sds->sds_handler = (driver_filter_t *)intr; 1266 error = bus_generic_setup_intr(dev, child, 1267 ires, flags, filt, (driver_intr_t *) 1268 DMA_SYNC_STUB, sds, cookiep); 1269 } 1270 1271#undef DMA_SYNC_STUB 1272 1273 } else 1274 error = bus_generic_setup_intr(dev, child, ires, 1275 flags, filt, intr, arg, cookiep); 1276 if (error != 0) { 1277 free(sds, M_DEVBUF); 1278 return (error); 1279 } 1280 sds->sds_cookie = *cookiep; 1281 *cookiep = sds; 1282 return (error); 1283 } else if (found != 0) 1284 device_printf(dev, "WARNING: using devices behind PCI-PCI " 1285 "bridges may cause data corruption\n"); 1286 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1287 arg, cookiep)); 1288} 1289 1290static int 1291schizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1292 void *cookie) 1293{ 1294 struct schizo_dma_sync *sds; 1295 struct schizo_softc *sc; 1296 int error; 1297 1298 sc = device_get_softc(dev); 1299 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1300 sds = cookie; 1301 error = bus_generic_teardown_intr(dev, child, vec, 1302 sds->sds_cookie); 1303 if (error == 0) 1304 free(sds, M_DEVBUF); 1305 return (error); 1306 } 1307 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1308} 1309 1310static int 1311schizo_describe_intr(device_t dev, device_t child, struct resource *vec, 1312 void *cookie, const char *descr) 1313{ 1314 struct schizo_softc *sc; 1315 1316 sc = device_get_softc(dev); 1317 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) 1318 cookie = ((struct schizo_dma_sync *)cookie)->sds_cookie; 1319 return (bus_generic_describe_intr(dev, child, vec, cookie, descr)); 1320} 1321 1322static struct resource * 1323schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1324 u_long start, u_long end, u_long count, u_int flags) 1325{ 1326 struct schizo_softc *sc; 1327 struct resource *rv; 1328 struct rman *rm; 1329 bus_space_tag_t bt; 1330 bus_space_handle_t bh; 1331 int needactivate = flags & RF_ACTIVE; 1332 1333 flags &= ~RF_ACTIVE; 1334 1335 sc = device_get_softc(bus); 1336 if (type == SYS_RES_IRQ) { 1337 /* 1338 * XXX: Don't accept blank ranges for now, only single 1339 * interrupts. The other case should not happen with 1340 * the MI PCI code... 1341 * XXX: This may return a resource that is out of the 1342 * range that was specified. Is this correct...? 1343 */ 1344 if (start != end) 1345 panic("%s: XXX: interrupt range", __func__); 1346 start = end = INTMAP_VEC(sc->sc_ign, end); 1347 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 1348 type, rid, start, end, count, flags)); 1349 } 1350 switch (type) { 1351 case SYS_RES_MEMORY: 1352 rm = &sc->sc_pci_mem_rman; 1353 bt = sc->sc_pci_memt; 1354 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1355 break; 1356 case SYS_RES_IOPORT: 1357 rm = &sc->sc_pci_io_rman; 1358 bt = sc->sc_pci_iot; 1359 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1360 break; 1361 default: 1362 return (NULL); 1363 /* NOTREACHED */ 1364 } 1365 1366 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1367 if (rv == NULL) 1368 return (NULL); 1369 rman_set_rid(rv, *rid); 1370 bh += rman_get_start(rv); 1371 rman_set_bustag(rv, bt); 1372 rman_set_bushandle(rv, bh); 1373 1374 if (needactivate) { 1375 if (bus_activate_resource(child, type, *rid, rv)) { 1376 rman_release_resource(rv); 1377 return (NULL); 1378 } 1379 } 1380 return (rv); 1381} 1382 1383static int 1384schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1385 struct resource *r) 1386{ 1387 void *p; 1388 int error; 1389 1390 if (type == SYS_RES_IRQ) 1391 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1392 type, rid, r)); 1393 if (type == SYS_RES_MEMORY) { 1394 /* 1395 * Need to memory-map the device space, as some drivers 1396 * depend on the virtual address being set and usable. 1397 */ 1398 error = sparc64_bus_mem_map(rman_get_bustag(r), 1399 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1400 if (error != 0) 1401 return (error); 1402 rman_set_virtual(r, p); 1403 } 1404 return (rman_activate_resource(r)); 1405} 1406 1407static int 1408schizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1409 struct resource *r) 1410{ 1411 1412 if (type == SYS_RES_IRQ) 1413 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1414 type, rid, r)); 1415 if (type == SYS_RES_MEMORY) { 1416 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1417 rman_set_virtual(r, NULL); 1418 } 1419 return (rman_deactivate_resource(r)); 1420} 1421 1422static int 1423schizo_release_resource(device_t bus, device_t child, int type, int rid, 1424 struct resource *r) 1425{ 1426 int error; 1427 1428 if (type == SYS_RES_IRQ) 1429 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1430 type, rid, r)); 1431 if (rman_get_flags(r) & RF_ACTIVE) { 1432 error = bus_deactivate_resource(child, type, rid, r); 1433 if (error) 1434 return (error); 1435 } 1436 return (rman_release_resource(r)); 1437} 1438 1439static bus_dma_tag_t 1440schizo_get_dma_tag(device_t bus, device_t child) 1441{ 1442 struct schizo_softc *sc; 1443 1444 sc = device_get_softc(bus); 1445 return (sc->sc_pci_dmat); 1446} 1447 1448static phandle_t 1449schizo_get_node(device_t bus, device_t dev) 1450{ 1451 struct schizo_softc *sc; 1452 1453 sc = device_get_softc(bus); 1454 /* We only have one child, the PCI bus, which needs our own node. */ 1455 return (sc->sc_node); 1456} 1457 1458static bus_space_tag_t 1459schizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1460{ 1461 bus_space_tag_t bt; 1462 1463 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1464 M_NOWAIT | M_ZERO); 1465 if (bt == NULL) 1466 panic("%s: out of memory", __func__); 1467 1468 bt->bst_cookie = sc; 1469 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1470 bt->bst_type = type; 1471 return (bt); 1472} 1473 1474static u_int 1475schizo_get_timecount(struct timecounter *tc) 1476{ 1477 struct schizo_softc *sc; 1478 1479 sc = tc->tc_priv; 1480 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1481 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1482} 1483