schizo.c revision 201199
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 201199 2009-12-29 14:03:38Z marius $"); 36 37/* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39 * PCI 2.2 bridges 40 */ 41 42#include "opt_ofw_pci.h" 43#include "opt_schizo.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/rman.h> 55#include <sys/time.h> 56#include <sys/timetc.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/fsr.h> 66#include <machine/iommureg.h> 67#include <machine/iommuvar.h> 68#include <machine/resource.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73#include <sparc64/pci/ofw_pci.h> 74#include <sparc64/pci/schizoreg.h> 75#include <sparc64/pci/schizovar.h> 76 77#include "pcib_if.h" 78 79static const struct schizo_desc *schizo_get_desc(device_t); 80static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 81 driver_filter_t); 82static driver_filter_t schizo_dma_sync_stub; 83static driver_filter_t ichip_dma_sync_stub; 84static void schizo_intr_enable(void *); 85static void schizo_intr_disable(void *); 86static void schizo_intr_assign(void *); 87static void schizo_intr_clear(void *); 88static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 89static int schizo_get_intrmap(struct schizo_softc *, u_int, 90 bus_addr_t *, bus_addr_t *); 91static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 92static timecounter_get_t schizo_get_timecount; 93 94/* Interrupt handlers */ 95static driver_filter_t schizo_pci_bus; 96static driver_filter_t schizo_ue; 97static driver_filter_t schizo_ce; 98static driver_filter_t schizo_host_bus; 99static driver_filter_t schizo_cdma; 100 101/* IOMMU support */ 102static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 103 104/* 105 * Methods 106 */ 107static device_probe_t schizo_probe; 108static device_attach_t schizo_attach; 109static bus_read_ivar_t schizo_read_ivar; 110static bus_setup_intr_t schizo_setup_intr; 111static bus_teardown_intr_t schizo_teardown_intr; 112static bus_alloc_resource_t schizo_alloc_resource; 113static bus_activate_resource_t schizo_activate_resource; 114static bus_deactivate_resource_t schizo_deactivate_resource; 115static bus_release_resource_t schizo_release_resource; 116static bus_describe_intr_t schizo_describe_intr; 117static bus_get_dma_tag_t schizo_get_dma_tag; 118static pcib_maxslots_t schizo_maxslots; 119static pcib_read_config_t schizo_read_config; 120static pcib_write_config_t schizo_write_config; 121static pcib_route_interrupt_t schizo_route_interrupt; 122static ofw_bus_get_node_t schizo_get_node; 123 124static device_method_t schizo_methods[] = { 125 /* Device interface */ 126 DEVMETHOD(device_probe, schizo_probe), 127 DEVMETHOD(device_attach, schizo_attach), 128 DEVMETHOD(device_shutdown, bus_generic_shutdown), 129 DEVMETHOD(device_suspend, bus_generic_suspend), 130 DEVMETHOD(device_resume, bus_generic_resume), 131 132 /* Bus interface */ 133 DEVMETHOD(bus_print_child, bus_generic_print_child), 134 DEVMETHOD(bus_read_ivar, schizo_read_ivar), 135 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 136 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 137 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 138 DEVMETHOD(bus_activate_resource, schizo_activate_resource), 139 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 140 DEVMETHOD(bus_release_resource, schizo_release_resource), 141 DEVMETHOD(bus_describe_intr, schizo_describe_intr), 142 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 143 144 /* pcib interface */ 145 DEVMETHOD(pcib_maxslots, schizo_maxslots), 146 DEVMETHOD(pcib_read_config, schizo_read_config), 147 DEVMETHOD(pcib_write_config, schizo_write_config), 148 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 149 150 /* ofw_bus interface */ 151 DEVMETHOD(ofw_bus_get_node, schizo_get_node), 152 153 KOBJMETHOD_END 154}; 155 156static devclass_t schizo_devclass; 157 158DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 159 sizeof(struct schizo_softc)); 160DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 161 162static SLIST_HEAD(, schizo_softc) schizo_softcs = 163 SLIST_HEAD_INITIALIZER(schizo_softcs); 164 165static const struct intr_controller schizo_ic = { 166 schizo_intr_enable, 167 schizo_intr_disable, 168 schizo_intr_assign, 169 schizo_intr_clear 170}; 171 172struct schizo_icarg { 173 struct schizo_softc *sica_sc; 174 bus_addr_t sica_map; 175 bus_addr_t sica_clr; 176}; 177 178struct schizo_dma_sync { 179 struct schizo_softc *sds_sc; 180 driver_filter_t *sds_handler; 181 void *sds_arg; 182 void *sds_cookie; 183 uint64_t sds_syncval; 184 device_t sds_ppb; /* farest PCI-PCI bridge */ 185 uint8_t sds_bus; /* bus of farest PCI dev. */ 186 uint8_t sds_slot; /* slot of farest PCI dev. */ 187 uint8_t sds_func; /* func. of farest PCI dev. */ 188}; 189 190#define SCHIZO_PERF_CNT_QLTY 100 191 192#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 193 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 194#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 195 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 196 197#define SCHIZO_PCI_READ_8(sc, offs) \ 198 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 199#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 200 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 201#define SCHIZO_CTRL_READ_8(sc, offs) \ 202 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 203#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 204 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 205#define SCHIZO_PCICFG_READ_8(sc, offs) \ 206 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 207#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 208 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 209#define SCHIZO_ICON_READ_8(sc, offs) \ 210 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 211#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 212 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 213 214struct schizo_desc { 215 const char *sd_string; 216 int sd_mode; 217 const char *sd_name; 218}; 219 220static const struct schizo_desc const schizo_compats[] = { 221 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 222 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 223 { NULL, 0, NULL } 224}; 225 226static const struct schizo_desc * 227schizo_get_desc(device_t dev) 228{ 229 const struct schizo_desc *desc; 230 const char *compat; 231 232 compat = ofw_bus_get_compat(dev); 233 if (compat == NULL) 234 return (NULL); 235 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 236 if (strcmp(desc->sd_string, compat) == 0) 237 return (desc); 238 return (NULL); 239} 240 241static int 242schizo_probe(device_t dev) 243{ 244 const char *dtype; 245 246 dtype = ofw_bus_get_type(dev); 247 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 248 schizo_get_desc(dev) != NULL) { 249 device_set_desc(dev, "Sun Host-PCI bridge"); 250 return (0); 251 } 252 return (ENXIO); 253} 254 255static int 256schizo_attach(device_t dev) 257{ 258 struct ofw_pci_ranges *range; 259 const struct schizo_desc *desc; 260 struct schizo_softc *asc, *sc, *osc; 261 struct timecounter *tc; 262 uint64_t ino_bitmap, reg; 263 phandle_t node; 264 uint32_t prop, prop_array[2]; 265 int i, j, mode, rid, tsbsize; 266 267 sc = device_get_softc(dev); 268 node = ofw_bus_get_node(dev); 269 desc = schizo_get_desc(dev); 270 mode = desc->sd_mode; 271 272 sc->sc_dev = dev; 273 sc->sc_node = node; 274 sc->sc_mode = mode; 275 sc->sc_flags = 0; 276 277 /* 278 * The Schizo has three register banks: 279 * (0) per-PBM PCI configuration and status registers, but for bus B 280 * shared with the UPA64s interrupt mapping register banks 281 * (1) shared Schizo controller configuration and status registers 282 * (2) per-PBM PCI configuration space 283 * 284 * The Tomatillo has four register banks: 285 * (0) per-PBM PCI configuration and status registers 286 * (1) per-PBM Tomatillo controller configuration registers, but on 287 * machines having the `jbusppm' device shared with its Estar 288 * register bank for bus A 289 * (2) per-PBM PCI configuration space 290 * (3) per-PBM interrupt concentrator registers 291 */ 292 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 293 20) & 1; 294 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 295 i++) { 296 rid = i; 297 sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 298 SYS_RES_MEMORY, &rid, 299 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 300 i == STX_PCI) || i == STX_CTRL)) || 301 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 302 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 303 if (sc->sc_mem_res[i] == NULL) 304 panic("%s: could not allocate register bank %d", 305 __func__, i); 306 } 307 308 /* 309 * Match other Schizos that are already configured against 310 * the controller base physical address. This will be the 311 * same for a pair of devices that share register space. 312 */ 313 osc = NULL; 314 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 315 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 316 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 317 /* Found partner. */ 318 osc = asc; 319 break; 320 } 321 } 322 if (osc == NULL) { 323 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 324 M_NOWAIT | M_ZERO); 325 if (sc->sc_mtx == NULL) 326 panic("%s: could not malloc mutex", __func__); 327 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 328 } else { 329 if (sc->sc_mode != SCHIZO_MODE_SCZ) 330 panic("%s: no partner expected", __func__); 331 if (mtx_initialized(osc->sc_mtx) == 0) 332 panic("%s: mutex not initialized", __func__); 333 sc->sc_mtx = osc->sc_mtx; 334 } 335 336 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 337 panic("%s: could not determine IGN", __func__); 338 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 339 -1) 340 panic("%s: could not determine version", __func__); 341 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 342 prop = 33000000; 343 344 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 345 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 346 prop / 1000 / 1000); 347 348 /* Set up the PCI interrupt retry timer. */ 349#ifdef SCHIZO_DEBUG 350 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 351 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 352#endif 353 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 354 355 /* Set up the PCI control register. */ 356 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 357 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 358 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 359 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 360 if (OF_getproplen(node, "no-bus-parking") < 0) 361 reg |= STX_PCI_CTRL_ARB_PARK; 362 if (mode == SCHIZO_MODE_TOM) { 363 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 364 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 365 reg |= TOM_PCI_CTRL_DTO_IEN; 366 else 367 reg |= STX_PCI_CTRL_PTO; 368 } 369#ifdef SCHIZO_DEBUG 370 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 371 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 372 (unsigned long long)reg); 373#endif 374 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 375 376 /* Set up the PCI diagnostic register. */ 377 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 378 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 379 STX_PCI_DIAG_INTRSYNC_DIS); 380#ifdef SCHIZO_DEBUG 381 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 382 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 383 (unsigned long long)reg); 384#endif 385 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 386 387 /* 388 * On Tomatillo clear the I/O prefetch lengths (workaround for a 389 * Jalapeno bug). 390 */ 391 if (mode == SCHIZO_MODE_TOM) 392 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 393 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 394 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 395 396 /* 397 * Hunt through all the interrupt mapping regs and register 398 * the interrupt controller for our interrupt vectors. We do 399 * this early in order to be able to catch stray interrupts. 400 * This is complicated by the fact that a pair of Schizo PBMs 401 * shares one IGN. 402 */ 403 i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 404 sizeof(prop_array)); 405 if (i == -1) 406 panic("%s: could not get ino-bitmap", __func__); 407 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 408 for (i = 0; i <= STX_MAX_INO; i++) { 409 if ((ino_bitmap & (1ULL << i)) == 0) 410 continue; 411 if (i == STX_FB0_INO || i == STX_FB1_INO) 412 /* Leave for upa(4). */ 413 continue; 414 j = schizo_intr_register(sc, i); 415 if (j != 0) 416 device_printf(dev, "could not register interrupt " 417 "controller for INO %d (%d)\n", i, j); 418 } 419 420 /* 421 * Setup Safari/JBus performance counter 0 in bus cycle counting 422 * mode as timecounter. Unfortunately, this is broken with at 423 * least the version 4 Tomatillos found in Fire V120 and Blade 424 * 1500, which apparently actually count some different event at 425 * ~0.5 and 3MHz respectively instead (also when running in full 426 * power mode). Besides, one counter seems to be shared by a 427 * "pair" of Tomatillos, too. 428 */ 429 if (sc->sc_half == 0) { 430 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 431 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 432 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 433 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 434 if (tc == NULL) 435 panic("%s: could not malloc timecounter", __func__); 436 tc->tc_get_timecount = schizo_get_timecount; 437 tc->tc_poll_pps = NULL; 438 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 439 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 440 sizeof(prop)) == -1) 441 panic("%s: could not determine clock frequency", 442 __func__); 443 tc->tc_frequency = prop; 444 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 445 if (mode == SCHIZO_MODE_SCZ) 446 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 447 else 448 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 449 tc->tc_priv = sc; 450 tc_init(tc); 451 } 452 453 /* 454 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 455 * one per PBM. Schizo and XMITS additionally have a streaming 456 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 457 * affected by several errata and basically unusable though. 458 */ 459 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 460 sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0; 461 if (OF_getproplen(node, "no-streaming-cache") < 0 && 462 !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 463 sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 464 465#define TSBCASE(x) \ 466 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 467 tsbsize = (x); \ 468 break; \ 469 470 i = OF_getprop(node, "virtual-dma", (void *)prop_array, 471 sizeof(prop_array)); 472 if (i == -1 || i != sizeof(prop_array)) 473 schizo_iommu_init(sc, 7, -1); 474 else { 475 switch (prop_array[1]) { 476 TSBCASE(1); 477 TSBCASE(2); 478 TSBCASE(3); 479 TSBCASE(4); 480 TSBCASE(5); 481 TSBCASE(6); 482 TSBCASE(7); 483 TSBCASE(8); 484 default: 485 panic("%s: unsupported DVMA size 0x%x", 486 __func__, prop_array[1]); 487 /* NOTREACHED */ 488 } 489 schizo_iommu_init(sc, tsbsize, prop_array[0]); 490 } 491 492#undef TSBCASE 493 494 /* Initialize memory and I/O rmans. */ 495 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 496 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 497 if (rman_init(&sc->sc_pci_io_rman) != 0 || 498 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 499 panic("%s: failed to set up I/O rman", __func__); 500 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 501 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 502 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 503 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 504 panic("%s: failed to set up memory rman", __func__); 505 506 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 507 /* 508 * Make sure that the expected ranges are present. The 509 * OFW_PCI_CS_MEM64 one is not currently used though. 510 */ 511 if (i != STX_NRANGE) 512 panic("%s: unsupported number of ranges", __func__); 513 /* 514 * Find the addresses of the various bus spaces. 515 * There should not be multiple ones of one kind. 516 * The physical start addresses of the ranges are the configuration, 517 * memory and I/O handles. 518 */ 519 for (i = 0; i < STX_NRANGE; i++) { 520 j = OFW_PCI_RANGE_CS(&range[i]); 521 if (sc->sc_pci_bh[j] != 0) 522 panic("%s: duplicate range for space %d", 523 __func__, j); 524 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 525 } 526 free(range, M_OFWPROP); 527 528 /* Register the softc, this is needed for paired Schizos. */ 529 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 530 531 /* Allocate our tags. */ 532 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 533 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 534 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 535 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 536 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 537 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 538 panic("%s: bus_dma_tag_create failed", __func__); 539 /* Customize the tag. */ 540 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 541 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 542 543 /* 544 * Get the bus range from the firmware. 545 * NB: Tomatillos don't support PCI bus reenumeration. 546 */ 547 i = OF_getprop(node, "bus-range", (void *)prop_array, 548 sizeof(prop_array)); 549 if (i == -1) 550 panic("%s: could not get bus-range", __func__); 551 if (i != sizeof(prop_array)) 552 panic("%s: broken bus-range (%d)", __func__, i); 553 if (bootverbose) 554 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 555 prop_array[0], prop_array[1], prop_array[0]); 556 sc->sc_pci_secbus = prop_array[0]; 557 558 /* Clear any pending PCI error bits. */ 559 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 560 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 561 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 562 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 563 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 564 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 565 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 566 567 /* 568 * Establish handlers for interesting interrupts... 569 * Someone at Sun clearly was smoking crack; with Schizos PCI 570 * bus error interrupts for one PBM can be routed to the other 571 * PBM though we obviously need to use the softc of the former 572 * as the argument for the interrupt handler and the softc of 573 * the latter as the argument for the interrupt controller. 574 */ 575 if (sc->sc_half == 0) { 576 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 577 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 578 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 579 sica_sc == osc)) 580 /* 581 * We are the driver for PBM A and either also 582 * registered the interrupt controller for us or 583 * the driver for PBM B has probed first and 584 * registered it for us. 585 */ 586 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 587 schizo_pci_bus); 588 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 589 osc != NULL) 590 /* 591 * We are the driver for PBM A but registered 592 * the interrupt controller for PBM B, i.e. the 593 * driver for PBM B attached first but couldn't 594 * set up a handler for PBM B. 595 */ 596 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 597 schizo_pci_bus); 598 } else { 599 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 600 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 601 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 602 sica_sc == osc)) 603 /* 604 * We are the driver for PBM B and either also 605 * registered the interrupt controller for us or 606 * the driver for PBM A has probed first and 607 * registered it for us. 608 */ 609 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 610 schizo_pci_bus); 611 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 612 osc != NULL) 613 /* 614 * We are the driver for PBM B but registered 615 * the interrupt controller for PBM A, i.e. the 616 * driver for PBM A attached first but couldn't 617 * set up a handler for PBM A. 618 */ 619 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 620 schizo_pci_bus); 621 } 622 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 623 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 624 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 625 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 626 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 627 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 628 629 /* 630 * According to the Schizo Errata I-13, consistent DMA flushing/ 631 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 632 * so we can't use it and need to live with the consequences. With 633 * Schizo version >= 5, CDMA flushing/syncing is usable but requires 634 * the workaround described in Schizo Errata I-23. With Tomatillo 635 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 636 * version <= 4 (i.e. revision <= 2.3) bridges additionally require 637 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 638 */ 639 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 640 sc->sc_mode == SCHIZO_MODE_TOM || 641 sc->sc_mode == SCHIZO_MODE_XMS) { 642 sc->sc_flags |= SCHIZO_FLAGS_CDMA; 643 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 644 sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 645 /* 646 * Some firmware versions include the CDMA interrupt 647 * at RID 4 but most don't. With the latter we add 648 * it ourselves at the spare RID 5. 649 */ 650 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 651 4)); 652 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 653 (void)schizo_get_intrmap(sc, i, NULL, 654 &sc->sc_cdma_clr); 655 schizo_set_intr(sc, 4, i, schizo_cdma); 656 } else { 657 i = STX_CDMA_A_INO + sc->sc_half; 658 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 659 INTMAP_VEC(sc->sc_ign, i), 1) != 0) 660 panic("%s: failed to add CDMA " 661 "interrupt", __func__); 662 j = schizo_intr_register(sc, i); 663 if (j != 0) 664 panic("%s: could not register " 665 "interrupt controller for CDMA " 666 "(%d)", __func__, j); 667 (void)schizo_get_intrmap(sc, i, NULL, 668 &sc->sc_cdma_clr); 669 schizo_set_intr(sc, 5, i, schizo_cdma); 670 } 671 } 672 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 673 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 674 } 675 676 /* 677 * Set the latency timer register as this isn't always done by the 678 * firmware. 679 */ 680 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 681 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 682 683 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 684 685 device_add_child(dev, "pci", -1); 686 return (bus_generic_attach(dev)); 687} 688 689static void 690schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 691 driver_filter_t handler) 692{ 693 u_long vec; 694 int rid; 695 696 rid = index; 697 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 698 SYS_RES_IRQ, &rid, RF_ACTIVE); 699 if (sc->sc_irq_res[index] == NULL || 700 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 701 INTIGN(vec) != sc->sc_ign || 702 intr_vectors[vec].iv_ic != &schizo_ic || 703 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 704 INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 705 &sc->sc_ihand[index]) != 0) 706 panic("%s: failed to set up interrupt %d", __func__, index); 707} 708 709static int 710schizo_intr_register(struct schizo_softc *sc, u_int ino) 711{ 712 struct schizo_icarg *sica; 713 bus_addr_t intrclr, intrmap; 714 int error; 715 716 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 717 return (ENXIO); 718 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 719 if (sica == NULL) 720 return (ENOMEM); 721 sica->sica_sc = sc; 722 sica->sica_map = intrmap; 723 sica->sica_clr = intrclr; 724#ifdef SCHIZO_DEBUG 725 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 726 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 727 (u_long)intrclr); 728#endif 729 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 730 &schizo_ic, sica)); 731 if (error != 0) 732 free(sica, M_DEVBUF); 733 return (error); 734} 735 736static int 737schizo_get_intrmap(struct schizo_softc *sc, u_int ino, 738 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 739{ 740 bus_addr_t intrclr, intrmap; 741 uint64_t mr; 742 743 /* 744 * XXX we only look for INOs rather than INRs since the firmware 745 * may not provide the IGN and the IGN is constant for all devices 746 * on that PCI controller. 747 */ 748 749 if (ino > STX_MAX_INO) { 750 device_printf(sc->sc_dev, "out of range INO %d requested\n", 751 ino); 752 return (0); 753 } 754 755 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 756 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 757 mr = SCHIZO_PCI_READ_8(sc, intrmap); 758 if (INTINO(mr) != ino) { 759 device_printf(sc->sc_dev, 760 "interrupt map entry does not match INO (%d != %d)\n", 761 (int)INTINO(mr), ino); 762 return (0); 763 } 764 765 if (intrmapptr != NULL) 766 *intrmapptr = intrmap; 767 if (intrclrptr != NULL) 768 *intrclrptr = intrclr; 769 return (1); 770} 771 772/* 773 * Interrupt handlers 774 */ 775static int 776schizo_pci_bus(void *arg) 777{ 778 struct schizo_softc *sc = arg; 779 uint64_t afar, afsr, csr, iommu; 780 uint32_t status; 781 782 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 783 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 784 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 785 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 786 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 787 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 788 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 789 if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 790 goto clear_error; 791 792 /* These are non-fatal if target abort was signaled. */ 793 if ((status & PCIM_STATUS_STABORT) != 0 && 794 ((iommu & TOM_PCI_IOMMU_ERRMASK) == 795 TOM_PCI_IOMMU_INVALID_ERR || 796 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 797 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 798 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 799 goto clear_error; 800 } 801 } 802 803 panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 804 "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 805 'A' + sc->sc_half, (unsigned long long)afar, 806 (unsigned long long)afsr, (unsigned long long)csr, 807 (unsigned long long)iommu, (unsigned long long)status); 808 809 clear_error: 810 if (bootverbose) 811 device_printf(sc->sc_dev, 812 "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 813 "STATUS %#llx", 'A' + sc->sc_half, 814 (unsigned long long)afar, (unsigned long long)afsr, 815 (unsigned long long)csr, (unsigned long long)status); 816 /* Clear the error bits that we caught. */ 817 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 818 STX_CS_FUNC, PCIR_STATUS, status, 2); 819 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 820 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 821 return (FILTER_HANDLED); 822} 823 824static int 825schizo_ue(void *arg) 826{ 827 struct schizo_softc *sc = arg; 828 uint64_t afar, afsr; 829 int i; 830 831 mtx_lock_spin(sc->sc_mtx); 832 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 833 for (i = 0; i < 1000; i++) 834 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 835 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 836 break; 837 mtx_unlock_spin(sc->sc_mtx); 838 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 839 device_get_name(sc->sc_dev), (unsigned long long)afar, 840 (unsigned long long)afsr); 841 return (FILTER_HANDLED); 842} 843 844static int 845schizo_ce(void *arg) 846{ 847 struct schizo_softc *sc = arg; 848 uint64_t afar, afsr; 849 int i; 850 851 mtx_lock_spin(sc->sc_mtx); 852 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 853 for (i = 0; i < 1000; i++) 854 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 855 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 856 break; 857 device_printf(sc->sc_dev, 858 "correctable DMA error AFAR %#llx AFSR %#llx\n", 859 (unsigned long long)afar, (unsigned long long)afsr); 860 /* Clear the error bits that we caught. */ 861 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 862 mtx_unlock_spin(sc->sc_mtx); 863 return (FILTER_HANDLED); 864} 865 866static int 867schizo_host_bus(void *arg) 868{ 869 struct schizo_softc *sc = arg; 870 uint64_t errlog; 871 872 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 873 panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 874 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 875 (unsigned long long)errlog); 876 return (FILTER_HANDLED); 877} 878 879static int 880schizo_cdma(void *arg) 881{ 882 struct schizo_softc *sc = arg; 883 884 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 885 return (FILTER_HANDLED); 886} 887 888static void 889schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 890{ 891 892 /* Punch in our copies. */ 893 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 894 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 895 sc->sc_is.is_iommu = STX_PCI_IOMMU; 896 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 897 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 898 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 899 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 900 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 901 902 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 903 dvmabase, 0); 904} 905 906static int 907schizo_maxslots(device_t dev) 908{ 909 struct schizo_softc *sc; 910 911 sc = device_get_softc(dev); 912 if (sc->sc_mode == SCHIZO_MODE_SCZ) 913 return (sc->sc_half == 0 ? 4 : 6); 914 915 /* XXX: is this correct? */ 916 return (PCI_SLOTMAX); 917} 918 919static uint32_t 920schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 921 int width) 922{ 923 struct schizo_softc *sc; 924 bus_space_handle_t bh; 925 u_long offset = 0; 926 uint32_t r, wrd; 927 int i; 928 uint16_t shrt; 929 uint8_t byte; 930 931 sc = device_get_softc(dev); 932 933 /* 934 * The Schizo bridges contain a dupe of their header at 0x80. 935 */ 936 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 937 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 938 reg + width > 0x80) 939 return (0); 940 941 offset = STX_CONF_OFF(bus, slot, func, reg); 942 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 943 switch (width) { 944 case 1: 945 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 946 r = byte; 947 break; 948 case 2: 949 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 950 r = shrt; 951 break; 952 case 4: 953 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 954 r = wrd; 955 break; 956 default: 957 panic("%s: bad width", __func__); 958 /* NOTREACHED */ 959 } 960 961 if (i) { 962#ifdef SCHIZO_DEBUG 963 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 964 __func__, bus, slot, func, reg); 965#endif 966 r = -1; 967 } 968 return (r); 969} 970 971static void 972schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 973 u_int reg, uint32_t val, int width) 974{ 975 struct schizo_softc *sc; 976 bus_space_handle_t bh; 977 u_long offset = 0; 978 979 sc = device_get_softc(dev); 980 offset = STX_CONF_OFF(bus, slot, func, reg); 981 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 982 switch (width) { 983 case 1: 984 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 985 break; 986 case 2: 987 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 988 break; 989 case 4: 990 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 991 break; 992 default: 993 panic("%s: bad width", __func__); 994 /* NOTREACHED */ 995 } 996} 997 998static int 999schizo_route_interrupt(device_t bridge, device_t dev, int pin) 1000{ 1001 struct schizo_softc *sc; 1002 struct ofw_pci_register reg; 1003 ofw_pci_intr_t pintr, mintr; 1004 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1005 1006 sc = device_get_softc(bridge); 1007 pintr = pin; 1008 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1009 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1010 maskbuf)) 1011 return (mintr); 1012 1013 device_printf(bridge, "could not route pin %d for device %d.%d\n", 1014 pin, pci_get_slot(dev), pci_get_function(dev)); 1015 return (PCI_INVALID_IRQ); 1016} 1017 1018static int 1019schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1020{ 1021 struct schizo_softc *sc; 1022 1023 sc = device_get_softc(dev); 1024 switch (which) { 1025 case PCIB_IVAR_DOMAIN: 1026 *result = device_get_unit(dev); 1027 return (0); 1028 case PCIB_IVAR_BUS: 1029 *result = sc->sc_pci_secbus; 1030 return (0); 1031 } 1032 return (ENOENT); 1033} 1034 1035static int 1036schizo_dma_sync_stub(void *arg) 1037{ 1038 struct timeval cur, end; 1039 struct schizo_dma_sync *sds = arg; 1040 struct schizo_softc *sc = sds->sds_sc; 1041 uint32_t state; 1042 1043 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1044 sds->sds_func, PCIR_VENDOR, 2); 1045 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1046 SCHIZO_CDMA_STATE_DONE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1047 ; 1048 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1); 1049 microuptime(&cur); 1050 end.tv_sec = 1; 1051 end.tv_usec = 0; 1052 timevaladd(&end, &cur); 1053 for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1054 SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1055 microuptime(&cur); 1056 if (state != SCHIZO_CDMA_STATE_DONE) 1057 panic("%s: DMA does not sync", __func__); 1058 return (sds->sds_handler(sds->sds_arg)); 1059} 1060 1061#define VIS_BLOCKSIZE 64 1062 1063static int 1064ichip_dma_sync_stub(void *arg) 1065{ 1066 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1067 struct timeval cur, end; 1068 struct schizo_dma_sync *sds = arg; 1069 struct schizo_softc *sc = sds->sds_sc; 1070 register_t reg, s; 1071 1072 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1073 sds->sds_func, PCIR_VENDOR, 2); 1074 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1075 microuptime(&cur); 1076 end.tv_sec = 1; 1077 end.tv_usec = 0; 1078 timevaladd(&end, &cur); 1079 for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1080 sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1081 microuptime(&cur); 1082 if ((reg & sds->sds_syncval) != 0) 1083 panic("%s: DMA does not sync", __func__); 1084 1085 if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1086 s = intr_disable(); 1087 reg = rd(fprs); 1088 wr(fprs, reg | FPRS_FEF, 0); 1089 __asm __volatile("stda %%f0, [%0] %1" 1090 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1091 membar(Sync); 1092 wr(fprs, reg, 0); 1093 intr_restore(s); 1094 } 1095 return (sds->sds_handler(sds->sds_arg)); 1096} 1097 1098static void 1099schizo_intr_enable(void *arg) 1100{ 1101 struct intr_vector *iv = arg; 1102 struct schizo_icarg *sica = iv->iv_icarg; 1103 1104 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1105 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1106} 1107 1108static void 1109schizo_intr_disable(void *arg) 1110{ 1111 struct intr_vector *iv = arg; 1112 struct schizo_icarg *sica = iv->iv_icarg; 1113 1114 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1115} 1116 1117static void 1118schizo_intr_assign(void *arg) 1119{ 1120 struct intr_vector *iv = arg; 1121 struct schizo_icarg *sica = iv->iv_icarg; 1122 1123 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1124 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1125} 1126 1127static void 1128schizo_intr_clear(void *arg) 1129{ 1130 struct intr_vector *iv = arg; 1131 struct schizo_icarg *sica = iv->iv_icarg; 1132 1133 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0); 1134} 1135 1136static int 1137schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1138 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1139 void **cookiep) 1140{ 1141 devclass_t pci_devclass; 1142 device_t cdev, pdev, pcidev; 1143 struct schizo_dma_sync *sds; 1144 struct schizo_softc *sc; 1145 u_long vec; 1146 int error, found; 1147 1148 sc = device_get_softc(dev); 1149 /* 1150 * Make sure the vector is fully specified. 1151 */ 1152 vec = rman_get_start(ires); 1153 if (INTIGN(vec) != sc->sc_ign) { 1154 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1155 return (EINVAL); 1156 } 1157 1158 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1159 /* 1160 * Ensure we use the right softc in case the interrupt 1161 * is routed to our companion PBM for some odd reason. 1162 */ 1163 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1164 sica_sc; 1165 } else if (intr_vectors[vec].iv_ic == NULL) { 1166 /* 1167 * Work around broken firmware which misses entries in 1168 * the ino-bitmap. 1169 */ 1170 error = schizo_intr_register(sc, INTINO(vec)); 1171 if (error != 0) { 1172 device_printf(dev, "could not register interrupt " 1173 "controller for vector 0x%lx (%d)\n", vec, error); 1174 return (error); 1175 } 1176 if (bootverbose) 1177 device_printf(dev, "belatedly registered as " 1178 "interrupt controller for vector 0x%lx\n", vec); 1179 } else { 1180 device_printf(dev, 1181 "invalid interrupt controller for vector 0x%lx\n", vec); 1182 return (EINVAL); 1183 } 1184 1185 /* 1186 * Install a a wrapper for CDMA flushing/syncing for devices 1187 * behind PCI-PCI bridges if possible. 1188 */ 1189 pcidev = NULL; 1190 found = 0; 1191 pci_devclass = devclass_find("pci"); 1192 for (cdev = child; cdev != dev; cdev = pdev) { 1193 pdev = device_get_parent(cdev); 1194 if (pcidev == NULL) { 1195 if (device_get_devclass(pdev) != pci_devclass) 1196 continue; 1197 pcidev = cdev; 1198 continue; 1199 } 1200 if (pci_get_class(cdev) == PCIC_BRIDGE && 1201 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1202 found = 1; 1203 } 1204 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1205 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1206 if (sds == NULL) 1207 return (ENOMEM); 1208 if (found != 0 && pcidev != NULL) { 1209 sds->sds_sc = sc; 1210 sds->sds_arg = arg; 1211 sds->sds_ppb = 1212 device_get_parent(device_get_parent(pcidev)); 1213 sds->sds_bus = pci_get_bus(pcidev); 1214 sds->sds_slot = pci_get_slot(pcidev); 1215 sds->sds_func = pci_get_function(pcidev); 1216 sds->sds_syncval = 1ULL << INTINO(vec); 1217 if (bootverbose) 1218 device_printf(dev, "installed DMA sync " 1219 "wrapper for device %d.%d on bus %d\n", 1220 sds->sds_slot, sds->sds_func, 1221 sds->sds_bus); 1222 1223#define DMA_SYNC_STUB \ 1224 (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1225 ichip_dma_sync_stub) 1226 1227 if (intr == NULL) { 1228 sds->sds_handler = filt; 1229 error = bus_generic_setup_intr(dev, child, 1230 ires, flags, DMA_SYNC_STUB, intr, sds, 1231 cookiep); 1232 } else { 1233 sds->sds_handler = (driver_filter_t *)intr; 1234 error = bus_generic_setup_intr(dev, child, 1235 ires, flags, filt, (driver_intr_t *) 1236 DMA_SYNC_STUB, sds, cookiep); 1237 } 1238 1239#undef DMA_SYNC_STUB 1240 1241 } else 1242 error = bus_generic_setup_intr(dev, child, ires, 1243 flags, filt, intr, arg, cookiep); 1244 if (error != 0) { 1245 free(sds, M_DEVBUF); 1246 return (error); 1247 } 1248 sds->sds_cookie = *cookiep; 1249 *cookiep = sds; 1250 return (error); 1251 } else if (found != 0) 1252 device_printf(dev, "WARNING: using devices behind PCI-PCI " 1253 "bridges may cause data corruption\n"); 1254 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1255 arg, cookiep)); 1256} 1257 1258static int 1259schizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1260 void *cookie) 1261{ 1262 struct schizo_dma_sync *sds; 1263 struct schizo_softc *sc; 1264 int error; 1265 1266 sc = device_get_softc(dev); 1267 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1268 sds = cookie; 1269 error = bus_generic_teardown_intr(dev, child, vec, 1270 sds->sds_cookie); 1271 if (error == 0) 1272 free(sds, M_DEVBUF); 1273 return (error); 1274 } 1275 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1276} 1277 1278static int 1279schizo_describe_intr(device_t dev, device_t child, struct resource *vec, 1280 void *cookie, const char *descr) 1281{ 1282 struct schizo_softc *sc; 1283 1284 sc = device_get_softc(dev); 1285 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) 1286 cookie = ((struct schizo_dma_sync *)cookie)->sds_cookie; 1287 return (bus_generic_describe_intr(dev, child, vec, cookie, descr)); 1288} 1289 1290static struct resource * 1291schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1292 u_long start, u_long end, u_long count, u_int flags) 1293{ 1294 struct schizo_softc *sc; 1295 struct resource *rv; 1296 struct rman *rm; 1297 bus_space_tag_t bt; 1298 bus_space_handle_t bh; 1299 int needactivate = flags & RF_ACTIVE; 1300 1301 flags &= ~RF_ACTIVE; 1302 1303 sc = device_get_softc(bus); 1304 if (type == SYS_RES_IRQ) { 1305 /* 1306 * XXX: Don't accept blank ranges for now, only single 1307 * interrupts. The other case should not happen with 1308 * the MI PCI code... 1309 * XXX: This may return a resource that is out of the 1310 * range that was specified. Is this correct...? 1311 */ 1312 if (start != end) 1313 panic("%s: XXX: interrupt range", __func__); 1314 start = end = INTMAP_VEC(sc->sc_ign, end); 1315 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 1316 type, rid, start, end, count, flags)); 1317 } 1318 switch (type) { 1319 case SYS_RES_MEMORY: 1320 rm = &sc->sc_pci_mem_rman; 1321 bt = sc->sc_pci_memt; 1322 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1323 break; 1324 case SYS_RES_IOPORT: 1325 rm = &sc->sc_pci_io_rman; 1326 bt = sc->sc_pci_iot; 1327 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1328 break; 1329 default: 1330 return (NULL); 1331 /* NOTREACHED */ 1332 } 1333 1334 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1335 if (rv == NULL) 1336 return (NULL); 1337 rman_set_rid(rv, *rid); 1338 bh += rman_get_start(rv); 1339 rman_set_bustag(rv, bt); 1340 rman_set_bushandle(rv, bh); 1341 1342 if (needactivate) { 1343 if (bus_activate_resource(child, type, *rid, rv)) { 1344 rman_release_resource(rv); 1345 return (NULL); 1346 } 1347 } 1348 return (rv); 1349} 1350 1351static int 1352schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1353 struct resource *r) 1354{ 1355 void *p; 1356 int error; 1357 1358 if (type == SYS_RES_IRQ) 1359 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1360 type, rid, r)); 1361 if (type == SYS_RES_MEMORY) { 1362 /* 1363 * Need to memory-map the device space, as some drivers 1364 * depend on the virtual address being set and usable. 1365 */ 1366 error = sparc64_bus_mem_map(rman_get_bustag(r), 1367 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1368 if (error != 0) 1369 return (error); 1370 rman_set_virtual(r, p); 1371 } 1372 return (rman_activate_resource(r)); 1373} 1374 1375static int 1376schizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1377 struct resource *r) 1378{ 1379 1380 if (type == SYS_RES_IRQ) 1381 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1382 type, rid, r)); 1383 if (type == SYS_RES_MEMORY) { 1384 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1385 rman_set_virtual(r, NULL); 1386 } 1387 return (rman_deactivate_resource(r)); 1388} 1389 1390static int 1391schizo_release_resource(device_t bus, device_t child, int type, int rid, 1392 struct resource *r) 1393{ 1394 int error; 1395 1396 if (type == SYS_RES_IRQ) 1397 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1398 type, rid, r)); 1399 if (rman_get_flags(r) & RF_ACTIVE) { 1400 error = bus_deactivate_resource(child, type, rid, r); 1401 if (error) 1402 return (error); 1403 } 1404 return (rman_release_resource(r)); 1405} 1406 1407static bus_dma_tag_t 1408schizo_get_dma_tag(device_t bus, device_t child) 1409{ 1410 struct schizo_softc *sc; 1411 1412 sc = device_get_softc(bus); 1413 return (sc->sc_pci_dmat); 1414} 1415 1416static phandle_t 1417schizo_get_node(device_t bus, device_t dev) 1418{ 1419 struct schizo_softc *sc; 1420 1421 sc = device_get_softc(bus); 1422 /* We only have one child, the PCI bus, which needs our own node. */ 1423 return (sc->sc_node); 1424} 1425 1426static bus_space_tag_t 1427schizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1428{ 1429 bus_space_tag_t bt; 1430 1431 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1432 M_NOWAIT | M_ZERO); 1433 if (bt == NULL) 1434 panic("%s: out of memory", __func__); 1435 1436 bt->bst_cookie = sc; 1437 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1438 bt->bst_type = type; 1439 return (bt); 1440} 1441 1442static u_int 1443schizo_get_timecount(struct timecounter *tc) 1444{ 1445 struct schizo_softc *sc; 1446 1447 sc = tc->tc_priv; 1448 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1449 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1450} 1451