schizo.c revision 186290
178556Sobrien/*- 278556Sobrien * Copyright (c) 1999, 2000 Matthew R. Green 378556Sobrien * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 478556Sobrien * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 578556Sobrien * All rights reserved. 6167977Sdelphij * 7167977Sdelphij * Redistribution and use in source and binary forms, with or without 8167977Sdelphij * modification, are permitted provided that the following conditions 978556Sobrien * are met: 10215041Sobrien * 1. Redistributions of source code must retain the above copyright 11215041Sobrien * notice, this list of conditions and the following disclaimer. 1278556Sobrien * 2. Redistributions in binary form must reproduce the above copyright 13167977Sdelphij * notice, this list of conditions and the following disclaimer in the 14167977Sdelphij * documentation and/or other materials provided with the distribution. 1578556Sobrien * 3. The name of the author may not be used to endorse or promote products 16167977Sdelphij * derived from this software without specific prior written permission. 17167977Sdelphij * 18167977Sdelphij * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1978556Sobrien * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2078556Sobrien * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21167977Sdelphij * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22167977Sdelphij * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23167977Sdelphij * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24167977Sdelphij * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25167977Sdelphij * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2678556Sobrien * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2778556Sobrien * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2878556Sobrien * SUCH DAMAGE. 2978556Sobrien * 3078556Sobrien * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 3190067Ssobomax * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 3290067Ssobomax */ 3390067Ssobomax 3478556Sobrien#include <sys/cdefs.h> 3578556Sobrien__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 186290 2008-12-18 18:29:15Z marius $"); 3678556Sobrien 3778556Sobrien/* 3878556Sobrien * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 3978556Sobrien * PCI 2.2 bridges 4078556Sobrien */ 4178556Sobrien 4278556Sobrien#include "opt_ofw_pci.h" 4378556Sobrien#include "opt_schizo.h" 4478556Sobrien 4578556Sobrien#include <sys/param.h> 4678556Sobrien#include <sys/systm.h> 4778556Sobrien#include <sys/bus.h> 4878556Sobrien#include <sys/kernel.h> 4978556Sobrien#include <sys/lock.h> 5078556Sobrien#include <sys/malloc.h> 5178556Sobrien#include <sys/module.h> 5278556Sobrien#include <sys/mutex.h> 5378556Sobrien#include <sys/pcpu.h> 5478556Sobrien#include <sys/rman.h> 5578556Sobrien#include <sys/time.h> 5678556Sobrien#include <sys/timetc.h> 5778556Sobrien 5878556Sobrien#include <dev/ofw/ofw_bus.h> 5978556Sobrien#include <dev/ofw/ofw_pci.h> 6078556Sobrien#include <dev/ofw/openfirm.h> 6178556Sobrien 6278556Sobrien#include <machine/bus.h> 6378556Sobrien#include <machine/bus_common.h> 6478556Sobrien#include <machine/bus_private.h> 6578556Sobrien#include <machine/fsr.h> 6678556Sobrien#include <machine/iommureg.h> 6778556Sobrien#include <machine/iommuvar.h> 6878556Sobrien#include <machine/resource.h> 6978556Sobrien 7090067Ssobomax#include <dev/pci/pcireg.h> 7178556Sobrien#include <dev/pci/pcivar.h> 7278556Sobrien 7378556Sobrien#include <sparc64/pci/ofw_pci.h> 7478556Sobrien#include <sparc64/pci/schizoreg.h> 7578556Sobrien#include <sparc64/pci/schizovar.h> 7678556Sobrien 7778556Sobrien#include "pcib_if.h" 7878556Sobrien 7978556Sobrienstatic const struct schizo_desc *schizo_get_desc(device_t); 8090067Ssobomaxstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 8190067Ssobomax driver_filter_t); 8278556Sobrienstatic driver_filter_t schizo_dma_sync_stub; 8378556Sobrienstatic driver_filter_t ichip_dma_sync_stub; 8478556Sobrienstatic void schizo_intr_enable(void *); 8578556Sobrienstatic void schizo_intr_disable(void *); 8678556Sobrienstatic void schizo_intr_assign(void *); 8778556Sobrienstatic void schizo_intr_clear(void *); 8878556Sobrienstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 8978556Sobrienstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 9078556Sobrien bus_addr_t *, bus_addr_t *); 9178556Sobrienstatic bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 9278556Sobrienstatic timecounter_get_t schizo_get_timecount; 9378556Sobrien 9478556Sobrien/* Interrupt handlers */ 9578556Sobrienstatic driver_filter_t schizo_pci_bus; 9690067Ssobomaxstatic driver_filter_t schizo_ue; 9778556Sobrienstatic driver_filter_t schizo_ce; 9878556Sobrienstatic driver_filter_t schizo_host_bus; 9978556Sobrienstatic driver_filter_t schizo_cdma; 10078556Sobrien 10190067Ssobomax/* IOMMU support */ 10278556Sobrienstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 10390067Ssobomax 10478556Sobrien/* 10578556Sobrien * Methods 10678556Sobrien */ 10778556Sobrienstatic device_probe_t schizo_probe; 10890067Ssobomaxstatic device_attach_t schizo_attach; 10978556Sobrienstatic bus_read_ivar_t schizo_read_ivar; 11078556Sobrienstatic bus_setup_intr_t schizo_setup_intr; 11178556Sobrienstatic bus_teardown_intr_t schizo_teardown_intr; 11290067Ssobomaxstatic bus_alloc_resource_t schizo_alloc_resource; 11378556Sobrienstatic bus_activate_resource_t schizo_activate_resource; 11478556Sobrienstatic bus_deactivate_resource_t schizo_deactivate_resource; 11578556Sobrienstatic bus_release_resource_t schizo_release_resource; 11678556Sobrienstatic bus_get_dma_tag_t schizo_get_dma_tag; 11778556Sobrienstatic pcib_maxslots_t schizo_maxslots; 11878556Sobrienstatic pcib_read_config_t schizo_read_config; 11978556Sobrienstatic pcib_write_config_t schizo_write_config; 12090067Ssobomaxstatic pcib_route_interrupt_t schizo_route_interrupt; 12178556Sobrienstatic ofw_bus_get_node_t schizo_get_node; 12278556Sobrien 12378556Sobrienstatic device_method_t schizo_methods[] = { 12490067Ssobomax /* Device interface */ 12578556Sobrien DEVMETHOD(device_probe, schizo_probe), 12678556Sobrien DEVMETHOD(device_attach, schizo_attach), 12778556Sobrien DEVMETHOD(device_shutdown, bus_generic_shutdown), 12878556Sobrien DEVMETHOD(device_suspend, bus_generic_suspend), 12978556Sobrien DEVMETHOD(device_resume, bus_generic_resume), 13078556Sobrien 13178556Sobrien /* Bus interface */ 13278556Sobrien DEVMETHOD(bus_print_child, bus_generic_print_child), 13378556Sobrien DEVMETHOD(bus_read_ivar, schizo_read_ivar), 13478556Sobrien DEVMETHOD(bus_setup_intr, schizo_setup_intr), 13578556Sobrien DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 13678556Sobrien DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 13790067Ssobomax DEVMETHOD(bus_activate_resource, schizo_activate_resource), 13890067Ssobomax DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 13978556Sobrien DEVMETHOD(bus_release_resource, schizo_release_resource), 14078556Sobrien DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 14178556Sobrien 14278556Sobrien /* pcib interface */ 14378556Sobrien DEVMETHOD(pcib_maxslots, schizo_maxslots), 14478556Sobrien DEVMETHOD(pcib_read_config, schizo_read_config), 14578556Sobrien DEVMETHOD(pcib_write_config, schizo_write_config), 14678556Sobrien DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 14778556Sobrien 14878556Sobrien /* ofw_bus interface */ 14990067Ssobomax DEVMETHOD(ofw_bus_get_node, schizo_get_node), 15078556Sobrien 15178556Sobrien { 0, 0 } 15278556Sobrien}; 15390067Ssobomax 15478556Sobrienstatic devclass_t schizo_devclass; 15578556Sobrien 15678556SobrienDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 15778556Sobrien sizeof(struct schizo_softc)); 15878556SobrienDRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 15978556Sobrien 16078556Sobrienstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 16178556Sobrien SLIST_HEAD_INITIALIZER(schizo_softcs); 16278556Sobrien 16378556Sobrienstatic const struct intr_controller schizo_ic = { 16478556Sobrien schizo_intr_enable, 16578556Sobrien schizo_intr_disable, 16678556Sobrien schizo_intr_assign, 16778556Sobrien schizo_intr_clear 16878556Sobrien}; 16978556Sobrien 17078556Sobrienstruct schizo_icarg { 17178556Sobrien struct schizo_softc *sica_sc; 17278556Sobrien bus_addr_t sica_map; 17378556Sobrien bus_addr_t sica_clr; 17478556Sobrien}; 17578556Sobrien 17678556Sobrienstruct schizo_dma_sync { 17778556Sobrien struct schizo_softc *sds_sc; 17878556Sobrien driver_filter_t *sds_handler; 17978556Sobrien void *sds_arg; 18078556Sobrien void *sds_cookie; 18178556Sobrien uint64_t sds_syncval; 18278556Sobrien device_t sds_ppb; /* farest PCI-PCI bridge */ 18378556Sobrien uint8_t sds_bus; /* bus of farest PCI device */ 18478556Sobrien uint8_t sds_slot; /* slot of farest PCI device */ 18578556Sobrien uint8_t sds_func; /* func. of farest PCI device */ 18678556Sobrien}; 18778556Sobrien 18878556Sobrien#define SCHIZO_PERF_CNT_QLTY 100 18978556Sobrien 19078556Sobrien#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 19178556Sobrien bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 19278556Sobrien#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 19378556Sobrien bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 19478556Sobrien 19578556Sobrien#define SCHIZO_PCI_READ_8(sc, offs) \ 19678556Sobrien SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 19778556Sobrien#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 19878556Sobrien SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 19978556Sobrien#define SCHIZO_CTRL_READ_8(sc, offs) \ 20078556Sobrien SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 20178556Sobrien#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 20278556Sobrien SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 20378556Sobrien#define SCHIZO_PCICFG_READ_8(sc, offs) \ 20478556Sobrien SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 20578556Sobrien#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 20678556Sobrien SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 20778556Sobrien#define SCHIZO_ICON_READ_8(sc, offs) \ 20878556Sobrien SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 20978556Sobrien#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 21078556Sobrien SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 21178556Sobrien 21278556Sobrien#define OFW_PCI_TYPE "pci" 213167977Sdelphij 214167977Sdelphijstruct schizo_desc { 215167977Sdelphij const char *sd_string; 216167977Sdelphij int sd_mode; 217167977Sdelphij const char *sd_name; 218167977Sdelphij}; 219167977Sdelphij 22078556Sobrienstatic const struct schizo_desc const schizo_compats[] = { 22178556Sobrien { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 22278556Sobrien { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 223167977Sdelphij { NULL, 0, NULL } 22478556Sobrien}; 22578556Sobrien 22678556Sobrienstatic const struct schizo_desc * 22778556Sobrienschizo_get_desc(device_t dev) 22878556Sobrien{ 22978556Sobrien const struct schizo_desc *desc; 23078556Sobrien const char *compat; 23178556Sobrien 23278556Sobrien compat = ofw_bus_get_compat(dev); 23378556Sobrien if (compat == NULL) 23478556Sobrien return (NULL); 23578556Sobrien for (desc = schizo_compats; desc->sd_string != NULL; desc++) 23690067Ssobomax if (strcmp(desc->sd_string, compat) == 0) 23778556Sobrien return (desc); 23878556Sobrien return (NULL); 23978556Sobrien} 24078556Sobrien 24178556Sobrienstatic int 24278556Sobrienschizo_probe(device_t dev) 24378556Sobrien{ 24478556Sobrien const char *dtype; 24578556Sobrien 24678556Sobrien dtype = ofw_bus_get_type(dev); 24778556Sobrien if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 24878556Sobrien schizo_get_desc(dev) != NULL) { 24978556Sobrien device_set_desc(dev, "Sun Host-PCI bridge"); 25090067Ssobomax return (0); 25178556Sobrien } 25278556Sobrien return (ENXIO); 25378556Sobrien} 25478556Sobrien 25578556Sobrienstatic int 25678556Sobrienschizo_attach(device_t dev) 25778556Sobrien{ 25878556Sobrien struct ofw_pci_ranges *range; 25978556Sobrien const struct schizo_desc *desc; 26078556Sobrien struct schizo_softc *asc, *sc, *osc; 26178556Sobrien struct timecounter *tc; 26278556Sobrien uint64_t ino_bitmap, reg; 26378556Sobrien phandle_t node; 26478556Sobrien uint32_t prop, prop_array[2]; 26578556Sobrien int i, mode, n, nrange, rid, tsbsize; 26678556Sobrien 26778556Sobrien sc = device_get_softc(dev); 26878556Sobrien node = ofw_bus_get_node(dev); 26978556Sobrien desc = schizo_get_desc(dev); 27078556Sobrien mode = desc->sd_mode; 27178556Sobrien 27278556Sobrien sc->sc_dev = dev; 27378556Sobrien sc->sc_node = node; 27490067Ssobomax sc->sc_mode = mode; 27590067Ssobomax sc->sc_flags = 0; 27690067Ssobomax 27778556Sobrien /* 27878556Sobrien * The Schizo has three register banks: 27990067Ssobomax * (0) per-PBM PCI configuration and status registers, but for bus B 28078556Sobrien * shared with the UPA64s interrupt mapping register banks 28190067Ssobomax * (1) shared Schizo controller configuration and status registers 28290067Ssobomax * (2) per-PBM PCI configuration space 28390067Ssobomax * 28490067Ssobomax * The Tomatillo has four register banks: 28590067Ssobomax * (0) per-PBM PCI configuration and status registers 28690067Ssobomax * (1) per-PBM Tomatillo controller configuration registers, but on 28790067Ssobomax * machines having the `jbusppm' device shared with its Estar 28890067Ssobomax * register bank for bus A 28978556Sobrien * (2) per-PBM PCI configuration space 29078556Sobrien * (3) per-PBM interrupt concentrator registers 29178556Sobrien */ 29278556Sobrien sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 29378556Sobrien 20) & 1; 29478556Sobrien for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 29578556Sobrien n++) { 29678556Sobrien rid = n; 29778556Sobrien sc->sc_mem_res[n] = bus_alloc_resource_any(dev, 29878556Sobrien SYS_RES_MEMORY, &rid, 29978556Sobrien (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 30078556Sobrien n == STX_PCI) || n == STX_CTRL)) || 30178556Sobrien (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 30278556Sobrien n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 30378556Sobrien if (sc->sc_mem_res[n] == NULL) 30478556Sobrien panic("%s: could not allocate register bank %d", 30578556Sobrien __func__, n); 30678556Sobrien } 30790067Ssobomax 30890067Ssobomax /* 30978556Sobrien * Match other Schizos that are already configured against 31078556Sobrien * the controller base physical address. This will be the 31178556Sobrien * same for a pair of devices that share register space. 31278556Sobrien */ 31378556Sobrien osc = NULL; 31478556Sobrien SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 31578556Sobrien if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 31678556Sobrien rman_get_start(sc->sc_mem_res[STX_CTRL])) { 31778556Sobrien /* Found partner. */ 31878556Sobrien osc = asc; 31978556Sobrien break; 32078556Sobrien } 32178556Sobrien } 32278556Sobrien if (osc == NULL) { 32378556Sobrien sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 32478556Sobrien M_NOWAIT | M_ZERO); 32578556Sobrien if (sc->sc_mtx == NULL) 32678556Sobrien panic("%s: could not malloc mutex", __func__); 32778556Sobrien mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 32878556Sobrien } else { 32978556Sobrien if (sc->sc_mode != SCHIZO_MODE_SCZ) 33078556Sobrien panic("%s: no partner expected", __func__); 33178556Sobrien if (mtx_initialized(osc->sc_mtx) == 0) 33278556Sobrien panic("%s: mutex not initialized", __func__); 33378556Sobrien sc->sc_mtx = osc->sc_mtx; 33478556Sobrien } 33578556Sobrien 33678556Sobrien if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 33778556Sobrien panic("%s: could not determine IGN", __func__); 33878556Sobrien if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1) 33978556Sobrien panic("%s: could not determine version", __func__); 34078556Sobrien if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 34178556Sobrien prop = 33000000; 34278556Sobrien 34378556Sobrien device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 34478556Sobrien desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 34578556Sobrien prop / 1000 / 1000); 34678556Sobrien 34778556Sobrien /* Set up the PCI interrupt retry timer. */ 34878556Sobrien#ifdef SCHIZO_DEBUG 34978556Sobrien device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 35078556Sobrien SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 35178556Sobrien#endif 35278556Sobrien SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 35378556Sobrien 35478556Sobrien /* Set up the PCI control register. */ 35578556Sobrien reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 35678556Sobrien reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 35778556Sobrien STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 35878556Sobrien reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 35978556Sobrien if (OF_getproplen(node, "no-bus-parking") < 0) 36078556Sobrien reg |= STX_PCI_CTRL_ARB_PARK; 36178556Sobrien if (mode == SCHIZO_MODE_TOM) { 36278556Sobrien reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 36378556Sobrien if (sc->sc_ver <= 1) /* revision <= 2.0 */ 36478556Sobrien reg |= TOM_PCI_CTRL_DTO_IEN; 36578556Sobrien else 36678556Sobrien reg |= STX_PCI_CTRL_PTO; 36778556Sobrien } 36878556Sobrien#ifdef SCHIZO_DEBUG 369167977Sdelphij device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 370147666Ssimon (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 371167977Sdelphij (unsigned long long)reg); 37278556Sobrien#endif 37390067Ssobomax SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 37478556Sobrien 37578556Sobrien /* Set up the PCI diagnostic register. */ 37690067Ssobomax reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 37778556Sobrien reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 37878556Sobrien STX_PCI_DIAG_INTRSYNC_DIS); 37978556Sobrien#ifdef SCHIZO_DEBUG 38078556Sobrien device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 38178556Sobrien (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 38290067Ssobomax (unsigned long long)reg); 38390067Ssobomax#endif 38490067Ssobomax SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 38590067Ssobomax 38690067Ssobomax /* 38790067Ssobomax * On Tomatillo clear the I/O prefetch lengths (workaround for a 38890067Ssobomax * Jalapeno bug). 38990067Ssobomax */ 39090067Ssobomax if (mode == SCHIZO_MODE_TOM) 39190067Ssobomax SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 39290067Ssobomax (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 39390067Ssobomax TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 39490067Ssobomax 39590067Ssobomax /* 39690067Ssobomax * Hunt through all the interrupt mapping regs and register 39790067Ssobomax * the interrupt controller for our interrupt vectors. We do 39890067Ssobomax * this early in order to be able to catch stray interrupts. 39990067Ssobomax * This is complicated by the fact that a pair of Schizo PBMs 40090067Ssobomax * shares one IGN. 40190067Ssobomax */ 40290067Ssobomax n = OF_getprop(node, "ino-bitmap", (void *)prop_array, 40390067Ssobomax sizeof(prop_array)); 40490067Ssobomax if (n == -1) 40578556Sobrien panic("%s: could not get ino-bitmap", __func__); 40678556Sobrien ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 40778556Sobrien for (n = 0; n <= STX_MAX_INO; n++) { 40878556Sobrien if ((ino_bitmap & (1ULL << n)) == 0) 40978556Sobrien continue; 41078556Sobrien if (n == STX_FB0_INO || n == STX_FB1_INO) 41178556Sobrien /* Leave for upa(4). */ 41278556Sobrien continue; 41378556Sobrien i = schizo_intr_register(sc, n); 41478556Sobrien if (i != 0) 41578556Sobrien device_printf(dev, "could not register interrupt " 41678556Sobrien "controller for INO %d (%d)\n", n, i); 41778556Sobrien } 41878556Sobrien 41978556Sobrien /* 42078556Sobrien * Setup Safari/JBus performance counter 0 in bus cycle counting 42178556Sobrien * mode as timecounter. Unfortunately, this is broken with at 42278556Sobrien * least the version 4 Tomatillos found in Fire V120 and Blade 42378556Sobrien * 1500, which apparently actually count some different event at 42478556Sobrien * ~0.5 and 3MHz respectively instead (also when running in full 42578556Sobrien * power mode). Besides, one counter seems to be shared by a 42678556Sobrien * "pair" of Tomatillos, too. 42778556Sobrien */ 42878556Sobrien if (sc->sc_half == 0) { 42978556Sobrien SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 43078556Sobrien (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 43178556Sobrien (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 43278556Sobrien tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 43378556Sobrien if (tc == NULL) 43478556Sobrien panic("%s: could not malloc timecounter", __func__); 43578556Sobrien tc->tc_get_timecount = schizo_get_timecount; 43678556Sobrien tc->tc_poll_pps = NULL; 43778556Sobrien tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 43878556Sobrien if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 43978556Sobrien sizeof(prop)) == -1) 440146293Sobrien panic("%s: could not determine clock frequency", 44178556Sobrien __func__); 44278556Sobrien tc->tc_frequency = prop; 44378556Sobrien tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 44478556Sobrien if (mode == SCHIZO_MODE_SCZ) 44578556Sobrien tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 44678556Sobrien else 44778556Sobrien tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 44878556Sobrien tc->tc_priv = sc; 44978556Sobrien tc_init(tc); 45078556Sobrien } 45178556Sobrien 45278556Sobrien /* Set up the IOMMU. Both Schizo and Tomatillo have one per PBM. */ 45378556Sobrien sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 45478556Sobrien sc->sc_is.is_sb[0] = 0; 45578556Sobrien sc->sc_is.is_sb[1] = 0; 45678556Sobrien#ifdef notyet 45778556Sobrien if (OF_getproplen(node, "no-streaming-cache") < 0) 45878556Sobrien sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 45978556Sobrien#endif 46078556Sobrien 46178556Sobrien#define TSBCASE(x) \ 46278556Sobrien case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 46390067Ssobomax tsbsize = (x); \ 46478556Sobrien break; \ 46578556Sobrien 46678556Sobrien n = OF_getprop(node, "virtual-dma", (void *)prop_array, 46778556Sobrien sizeof(prop_array)); 46878556Sobrien if (n == -1 || n != sizeof(prop_array)) 46978556Sobrien schizo_iommu_init(sc, 7, -1); 470146293Sobrien else { 47178556Sobrien switch (prop_array[1]) { 47278556Sobrien TSBCASE(1); 473146293Sobrien TSBCASE(2); 47478556Sobrien TSBCASE(3); 47578556Sobrien TSBCASE(4); 47678556Sobrien TSBCASE(5); 47778556Sobrien TSBCASE(6); 47878556Sobrien TSBCASE(7); 47978556Sobrien TSBCASE(8); 48078556Sobrien default: 48178556Sobrien panic("%s: unsupported DVMA size 0x%x", 48290067Ssobomax __func__, prop_array[1]); 48378556Sobrien /* NOTREACHED */ 484167977Sdelphij } 485167977Sdelphij schizo_iommu_init(sc, tsbsize, prop_array[0]); 486147666Ssimon } 487167977Sdelphij 488147666Ssimon#undef TSBCASE 48978556Sobrien 49078556Sobrien /* Initialize memory and I/O rmans. */ 49178556Sobrien sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 49278556Sobrien sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 49378556Sobrien if (rman_init(&sc->sc_pci_io_rman) != 0 || 49478556Sobrien rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 49578556Sobrien panic("%s: failed to set up I/O rman", __func__); 49678556Sobrien sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 49790067Ssobomax sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 49878556Sobrien if (rman_init(&sc->sc_pci_mem_rman) != 0 || 49978556Sobrien rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 50090067Ssobomax panic("%s: failed to set up memory rman", __func__); 50178556Sobrien 50278556Sobrien nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 50378556Sobrien (void **)&range); 50490067Ssobomax /* 50590067Ssobomax * Make sure that the expected ranges are present. The 50690067Ssobomax * OFW_PCI_CS_MEM64 one is not currently used though. 50790067Ssobomax */ 50890067Ssobomax if (nrange != STX_NRANGE) 50990067Ssobomax panic("%s: unsupported number of ranges", __func__); 51090067Ssobomax /* 51190067Ssobomax * Find the addresses of the various bus spaces. 51290067Ssobomax * There should not be multiple ones of one kind. 51390067Ssobomax * The physical start addresses of the ranges are the configuration, 51490067Ssobomax * memory and I/O handles. 51590067Ssobomax */ 51690067Ssobomax for (n = 0; n < STX_NRANGE; n++) { 51778556Sobrien i = OFW_PCI_RANGE_CS(&range[n]); 51878556Sobrien if (sc->sc_pci_bh[i] != 0) 51978556Sobrien panic("%s: duplicate range for space %d", __func__, i); 52078556Sobrien sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 52178556Sobrien } 52278556Sobrien free(range, M_OFWPROP); 52378556Sobrien 52478556Sobrien /* Register the softc, this is needed for paired Schizos. */ 52578556Sobrien SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 52678556Sobrien 52778556Sobrien /* Allocate our tags. */ 52878556Sobrien sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 52978556Sobrien sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 53078556Sobrien sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 53178556Sobrien if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 53278556Sobrien sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 53378556Sobrien 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 53478556Sobrien panic("%s: bus_dma_tag_create failed", __func__); 53578556Sobrien /* Customize the tag. */ 53678556Sobrien sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 53778556Sobrien sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 53878556Sobrien 53978556Sobrien /* 54078556Sobrien * Get the bus range from the firmware. 54178556Sobrien * NB: Tomatillos don't support PCI bus reenumeration. 54278556Sobrien */ 54378556Sobrien n = OF_getprop(node, "bus-range", (void *)prop_array, 54478556Sobrien sizeof(prop_array)); 54578556Sobrien if (n == -1) 54678556Sobrien panic("%s: could not get bus-range", __func__); 54778556Sobrien if (n != sizeof(prop_array)) 54878556Sobrien panic("%s: broken bus-range (%d)", __func__, n); 54978556Sobrien if (bootverbose) 55078556Sobrien device_printf(dev, "bus range %u to %u; PCI bus %d\n", 55178556Sobrien prop_array[0], prop_array[1], prop_array[0]); 55278556Sobrien sc->sc_pci_secbus = prop_array[0]; 55378556Sobrien 55478556Sobrien /* Clear any pending PCI error bits. */ 55578556Sobrien PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 55678556Sobrien PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 55778556Sobrien STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 55878556Sobrien SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 55978556Sobrien SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 56078556Sobrien SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 561146293Sobrien SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 56278556Sobrien 56378556Sobrien /* 56478556Sobrien * Establish handlers for interesting interrupts... 56578556Sobrien * Someone at Sun clearly was smoking crack; with Schizos PCI 56678556Sobrien * bus error interrupts for one PBM can be routed to the other 56778556Sobrien * PBM though we obviously need to use the softc of the former 56878556Sobrien * as the argument for the interrupt handler and the softc of 56978556Sobrien * the latter as the argument for the interrupt controller. 57078556Sobrien */ 57178556Sobrien if (sc->sc_half == 0) { 57278556Sobrien if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 57378556Sobrien (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 57478556Sobrien INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 57578556Sobrien sica_sc == osc)) 57678556Sobrien /* 57778556Sobrien * We are the driver for PBM A and either also 57878556Sobrien * registered the interrupt controller for us or 57978556Sobrien * the driver for PBM B has probed first and 58078556Sobrien * registered it for us. 58178556Sobrien */ 58278556Sobrien schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 58378556Sobrien schizo_pci_bus); 58478556Sobrien if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 585146293Sobrien osc != NULL) 58678556Sobrien /* 58778556Sobrien * We are the driver for PBM A but registered 588146293Sobrien * the interrupt controller for PBM B, i.e. the 58978556Sobrien * driver for PBM B attached first but couldn't 59078556Sobrien * set up a handler for PBM B. 59178556Sobrien */ 59278556Sobrien schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 59378556Sobrien schizo_pci_bus); 59478556Sobrien } else { 59578556Sobrien if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 59678556Sobrien (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 59778556Sobrien INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 59878556Sobrien sica_sc == osc)) 59978556Sobrien /* 60078556Sobrien * We are the driver for PBM B and either also 60178556Sobrien * registered the interrupt controller for us or 60278556Sobrien * the driver for PBM A has probed first and 60378556Sobrien * registered it for us. 60478556Sobrien */ 60578556Sobrien schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 60678556Sobrien schizo_pci_bus); 60778556Sobrien if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 60878556Sobrien osc != NULL) 60978556Sobrien /* 61078556Sobrien * We are the driver for PBM B but registered 61178556Sobrien * the interrupt controller for PBM A, i.e. the 61278556Sobrien * driver for PBM A attached first but couldn't 61378556Sobrien * set up a handler for PBM A. 61478556Sobrien */ 61578556Sobrien schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 61678556Sobrien schizo_pci_bus); 61778556Sobrien } 61878556Sobrien if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 61978556Sobrien schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 62078556Sobrien if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 62178556Sobrien schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 62278556Sobrien if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 62378556Sobrien schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 62478556Sobrien 62578556Sobrien /* 62678556Sobrien * According to the Schizo Errata I-13, consistent DMA flushing/ 62778556Sobrien * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 62878556Sobrien * so we can't use it and need to live with the consequences. 62978556Sobrien * With Schizo version >= 5, CDMA flushing/syncing is usable 63078556Sobrien * but requires the the workaround described in Schizo Errata 63178556Sobrien * I-23. With Tomatillo and XMITS, CDMA flushing/syncing works 63278556Sobrien * as expected, Tomatillo version <= 4 (i.e. revision <= 2.3) 63378556Sobrien * bridges additionally require a block store after a write to 63478556Sobrien * TOMXMS_PCI_DMA_SYNC_PEND though. 63578556Sobrien */ 63678556Sobrien if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 63778556Sobrien sc->sc_mode == SCHIZO_MODE_TOM || sc->sc_mode == SCHIZO_MODE_XMS) { 63878556Sobrien sc->sc_flags |= SCHIZO_FLAGS_CDMA; 63978556Sobrien if (sc->sc_mode == SCHIZO_MODE_SCZ) { 64078556Sobrien n = STX_CDMA_A_INO + sc->sc_half; 64178556Sobrien if (bus_set_resource(dev, SYS_RES_IRQ, 5, 64278556Sobrien INTMAP_VEC(sc->sc_ign, n), 1) != 0) 64378556Sobrien panic("%s: failed to add CDMA interrupt", 64478556Sobrien __func__); 64578556Sobrien i = schizo_intr_register(sc, n); 64678556Sobrien if (i != 0) 64778556Sobrien panic("%s: could not register interrupt " 64878556Sobrien "controller for CDMA (%d)", __func__, i); 64978556Sobrien (void)schizo_get_intrmap(sc, n, NULL, 65078556Sobrien &sc->sc_cdma_clr); 65178556Sobrien sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 65278556Sobrien schizo_set_intr(sc, 5, n, schizo_cdma); 65378556Sobrien } 65478556Sobrien if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 65578556Sobrien sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 65678556Sobrien } 65778556Sobrien 65878556Sobrien /* 65978556Sobrien * Set the latency timer register as this isn't always done by the 66078556Sobrien * firmware. 66178556Sobrien */ 66278556Sobrien PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 66378556Sobrien PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 66478556Sobrien 66578556Sobrien ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 66690067Ssobomax 66778556Sobrien device_add_child(dev, "pci", -1); 66878556Sobrien return (bus_generic_attach(dev)); 66978556Sobrien} 67078556Sobrien 67178556Sobrienstatic void 67278556Sobrienschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 67378556Sobrien driver_filter_t handler) 67478556Sobrien{ 67578556Sobrien u_long vec; 67678556Sobrien int rid; 67778556Sobrien 67878556Sobrien rid = index; 67978556Sobrien sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 68078556Sobrien &rid, RF_ACTIVE); 68178556Sobrien if (sc->sc_irq_res[index] == NULL || 68278556Sobrien INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 68378556Sobrien INTINO(vec) != ino || 68478556Sobrien intr_vectors[vec].iv_ic != &schizo_ic || 68578556Sobrien bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 68678556Sobrien INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 68778556Sobrien &sc->sc_ihand[index]) != 0) 68878556Sobrien panic("%s: failed to set up interrupt %d", __func__, index); 68990067Ssobomax} 69090067Ssobomax 69178556Sobrienstatic int 69278556Sobrienschizo_intr_register(struct schizo_softc *sc, u_int ino) 69378556Sobrien{ 69478556Sobrien struct schizo_icarg *sica; 69590067Ssobomax bus_addr_t intrclr, intrmap; 69690067Ssobomax int error; 69790067Ssobomax 69890067Ssobomax if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 69990067Ssobomax return (ENXIO); 70090067Ssobomax sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 70190067Ssobomax if (sica == NULL) 70290067Ssobomax return (ENOMEM); 70390067Ssobomax sica->sica_sc = sc; 70490067Ssobomax sica->sica_map = intrmap; 70590067Ssobomax sica->sica_clr = intrclr; 70690067Ssobomax#ifdef SCHIZO_DEBUG 70790067Ssobomax device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 70890067Ssobomax ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 70990067Ssobomax (u_long)intrclr); 71090067Ssobomax#endif 71190067Ssobomax error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 71290067Ssobomax &schizo_ic, sica)); 71390067Ssobomax if (error != 0) 71490067Ssobomax free(sica, M_DEVBUF); 71590067Ssobomax return (error); 71678556Sobrien} 71790067Ssobomax 71890067Ssobomaxstatic int 71990067Ssobomaxschizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr, 72090067Ssobomax bus_addr_t *intrclrptr) 72178556Sobrien{ 72290067Ssobomax bus_addr_t intrclr, intrmap; 72390067Ssobomax uint64_t mr; 72490067Ssobomax 72590067Ssobomax /* 72690067Ssobomax * XXX we only look for INOs rather than INRs since the firmware 72790067Ssobomax * may not provide the IGN and the IGN is constant for all devices 72890067Ssobomax * on that PCI controller. 72990067Ssobomax */ 73078556Sobrien 73190067Ssobomax if (ino > STX_MAX_INO) { 73278556Sobrien device_printf(sc->sc_dev, "out of range INO %d requested\n", 73378556Sobrien ino); 73478556Sobrien return (0); 73590067Ssobomax } 73690067Ssobomax 73790067Ssobomax intrmap = STX_PCI_IMAP_BASE + (ino << 3); 73878556Sobrien intrclr = STX_PCI_ICLR_BASE + (ino << 3); 73978556Sobrien mr = SCHIZO_PCI_READ_8(sc, intrmap); 74078556Sobrien if (INTINO(mr) != ino) { 74178556Sobrien device_printf(sc->sc_dev, 74278556Sobrien "interrupt map entry does not match INO (%d != %d)\n", 74378556Sobrien (int)INTINO(mr), ino); 74478556Sobrien return (0); 74578556Sobrien } 746167977Sdelphij 74778556Sobrien if (intrmapptr != NULL) 74878556Sobrien *intrmapptr = intrmap; 74978556Sobrien if (intrclrptr != NULL) 75078556Sobrien *intrclrptr = intrclr; 75178556Sobrien return (1); 752146293Sobrien} 75378556Sobrien 75478556Sobrien/* 75578556Sobrien * Interrupt handlers 75678556Sobrien */ 75778556Sobrienstatic int 75878556Sobrienschizo_pci_bus(void *arg) 75978556Sobrien{ 76078556Sobrien struct schizo_softc *sc = arg; 76178556Sobrien uint64_t afar, afsr, csr, iommu; 76278556Sobrien uint32_t status; 76378556Sobrien 76478556Sobrien afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 76578556Sobrien afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 76678556Sobrien csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 76778556Sobrien iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 76878556Sobrien status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 76978556Sobrien STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 77078556Sobrien if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 77178556Sobrien if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 77278556Sobrien goto clear_error; 77378556Sobrien 77478556Sobrien /* These are non-fatal if target abort was signaled. */ 77578556Sobrien if ((status & PCIM_STATUS_STABORT) != 0 && 77690067Ssobomax ((iommu & TOM_PCI_IOMMU_ERRMASK) == 77790067Ssobomax TOM_PCI_IOMMU_INVALID_ERR || 77890067Ssobomax (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 77990067Ssobomax (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 78090067Ssobomax SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 78190067Ssobomax goto clear_error; 78290067Ssobomax } 78390067Ssobomax } 78490067Ssobomax 78590067Ssobomax panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 78678556Sobrien "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 78778556Sobrien 'A' + sc->sc_half, (unsigned long long)afar, 78878556Sobrien (unsigned long long)afsr, (unsigned long long)csr, 78978556Sobrien (unsigned long long)iommu, (unsigned long long)status); 79078556Sobrien 79178556Sobrien clear_error: 79278556Sobrien if (bootverbose) 79378556Sobrien device_printf(sc->sc_dev, 79478556Sobrien "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 79578556Sobrien "STATUS %#llx", 'A' + sc->sc_half, 79678556Sobrien (unsigned long long)afar, (unsigned long long)afsr, 79778556Sobrien (unsigned long long)csr, (unsigned long long)status); 79878556Sobrien /* Clear the error bits that we caught. */ 79978556Sobrien PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 80078556Sobrien STX_CS_FUNC, PCIR_STATUS, status, 2); 80178556Sobrien SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 80278556Sobrien SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 80378556Sobrien return (FILTER_HANDLED); 80478556Sobrien} 80578556Sobrien 80678556Sobrienstatic int 80778556Sobrienschizo_ue(void *arg) 80878556Sobrien{ 80978556Sobrien struct schizo_softc *sc = arg; 81078556Sobrien uint64_t afar, afsr; 81178556Sobrien int i; 81278556Sobrien 81378556Sobrien mtx_lock_spin(sc->sc_mtx); 81478556Sobrien afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 81578556Sobrien for (i = 0; i < 1000; i++) 81678556Sobrien if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 81778556Sobrien STX_CTRL_CE_AFSR_ERRPNDG) == 0) 81878556Sobrien break; 81978556Sobrien mtx_unlock_spin(sc->sc_mtx); 82078556Sobrien panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 82178556Sobrien device_get_name(sc->sc_dev), (unsigned long long)afar, 82278556Sobrien (unsigned long long)afsr); 82378556Sobrien return (FILTER_HANDLED); 82478556Sobrien} 82578556Sobrien 82678556Sobrienstatic int 82778556Sobrienschizo_ce(void *arg) 82878556Sobrien{ 82978556Sobrien struct schizo_softc *sc = arg; 83078556Sobrien uint64_t afar, afsr; 83178556Sobrien int i; 832146293Sobrien 83378556Sobrien mtx_lock_spin(sc->sc_mtx); 83478556Sobrien afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 83578556Sobrien for (i = 0; i < 1000; i++) 83678556Sobrien if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 83778556Sobrien STX_CTRL_CE_AFSR_ERRPNDG) == 0) 83878556Sobrien break; 83978556Sobrien device_printf(sc->sc_dev, 84078556Sobrien "correctable DMA error AFAR %#llx AFSR %#llx\n", 84178556Sobrien (unsigned long long)afar, (unsigned long long)afsr); 84278556Sobrien /* Clear the error bits that we caught. */ 84378556Sobrien SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 84478556Sobrien mtx_unlock_spin(sc->sc_mtx); 84578556Sobrien return (FILTER_HANDLED); 84678556Sobrien} 84778556Sobrien 84878556Sobrienstatic int 84978556Sobrienschizo_host_bus(void *arg) 85078556Sobrien{ 85178556Sobrien struct schizo_softc *sc = arg; 85278556Sobrien uint64_t errlog; 85378556Sobrien 85478556Sobrien errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 855146293Sobrien panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 85678556Sobrien sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 85778556Sobrien (unsigned long long)errlog); 85878556Sobrien return (FILTER_HANDLED); 85978556Sobrien} 86078556Sobrien 86178556Sobrienstatic int 86278556Sobrienschizo_cdma(void *arg) 86378556Sobrien{ 86478556Sobrien struct schizo_softc *sc = arg; 86578556Sobrien 86678556Sobrien atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 86778556Sobrien return (FILTER_HANDLED); 86878556Sobrien} 86978556Sobrien 87078556Sobrienstatic void 87178556Sobrienschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 87278556Sobrien{ 87378556Sobrien 87478556Sobrien /* Punch in our copies. */ 87578556Sobrien sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 87678556Sobrien sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 87778556Sobrien sc->sc_is.is_iommu = STX_PCI_IOMMU; 87878556Sobrien sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 87978556Sobrien sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 88078556Sobrien sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 88178556Sobrien sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 88278556Sobrien sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 88378556Sobrien 88478556Sobrien iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 88578556Sobrien dvmabase, 0); 88678556Sobrien} 88778556Sobrien 88878556Sobrienstatic int 88978556Sobrienschizo_maxslots(device_t dev) 89078556Sobrien{ 89178556Sobrien struct schizo_softc *sc; 89278556Sobrien 89378556Sobrien sc = device_get_softc(dev); 89478556Sobrien if (sc->sc_mode == SCHIZO_MODE_SCZ) 89578556Sobrien return (sc->sc_half == 0 ? 4 : 6); 89678556Sobrien 89778556Sobrien /* XXX: is this correct? */ 89878556Sobrien return (PCI_SLOTMAX); 89978556Sobrien} 90078556Sobrien 90190067Ssobomaxstatic uint32_t 90290067Ssobomaxschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 90390067Ssobomax int width) 90490067Ssobomax{ 90590067Ssobomax struct schizo_softc *sc; 90678556Sobrien bus_space_handle_t bh; 90778556Sobrien u_long offset = 0; 90878556Sobrien uint32_t r, wrd; 90978556Sobrien int i; 91078556Sobrien uint16_t shrt; 91178556Sobrien uint8_t byte; 91278556Sobrien 91378556Sobrien sc = device_get_softc(dev); 91478556Sobrien 91578556Sobrien /* 91678556Sobrien * The Schizo bridges contain a dupe of their header at 0x80. 91778556Sobrien */ 91878556Sobrien if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 91978556Sobrien slot == STX_CS_DEVICE && func == STX_CS_FUNC && 92078556Sobrien reg + width > 0x80) 92178556Sobrien return (0); 92278556Sobrien 92378556Sobrien offset = STX_CONF_OFF(bus, slot, func, reg); 92478556Sobrien bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 92578556Sobrien switch (width) { 92678556Sobrien case 1: 92778556Sobrien i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 92878556Sobrien r = byte; 92978556Sobrien break; 93078556Sobrien case 2: 93178556Sobrien i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 93278556Sobrien r = shrt; 93378556Sobrien break; 93478556Sobrien case 4: 93578556Sobrien i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 93678556Sobrien r = wrd; 93778556Sobrien break; 93878556Sobrien default: 93978556Sobrien panic("%s: bad width", __func__); 94078556Sobrien /* NOTREACHED */ 94178556Sobrien } 94278556Sobrien 94378556Sobrien if (i) { 94478556Sobrien#ifdef SCHIZO_DEBUG 94578556Sobrien printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 94678556Sobrien __func__, bus, slot, func, reg); 94778556Sobrien#endif 94878556Sobrien r = -1; 94978556Sobrien } 95090067Ssobomax return (r); 95190067Ssobomax} 95290067Ssobomax 95390067Ssobomaxstatic void 95490067Ssobomaxschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 95590067Ssobomax uint32_t val, int width) 95690067Ssobomax{ 95790067Ssobomax struct schizo_softc *sc; 95890067Ssobomax bus_space_handle_t bh; 959167977Sdelphij u_long offset = 0; 96090067Ssobomax 96190067Ssobomax sc = device_get_softc(dev); 96290067Ssobomax offset = STX_CONF_OFF(bus, slot, func, reg); 96390067Ssobomax bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 96490067Ssobomax switch (width) { 96590067Ssobomax case 1: 96690067Ssobomax bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 96790067Ssobomax break; 96890067Ssobomax case 2: 96990067Ssobomax bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 97090067Ssobomax break; 97190067Ssobomax case 4: 97290067Ssobomax bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 97390067Ssobomax break; 97490067Ssobomax default: 97590067Ssobomax panic("%s: bad width", __func__); 97690067Ssobomax /* NOTREACHED */ 97778556Sobrien } 97878556Sobrien} 97978556Sobrien 98078556Sobrienstatic int 98178556Sobrienschizo_route_interrupt(device_t bridge, device_t dev, int pin) 98278556Sobrien{ 98378556Sobrien struct schizo_softc *sc; 98478556Sobrien struct ofw_pci_register reg; 98578556Sobrien ofw_pci_intr_t pintr, mintr; 98678556Sobrien uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 98778556Sobrien 98890067Ssobomax sc = device_get_softc(bridge); 98978556Sobrien pintr = pin; 99078556Sobrien if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 99178556Sobrien sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 99278556Sobrien return (mintr); 99378556Sobrien 99478556Sobrien device_printf(bridge, "could not route pin %d for device %d.%d\n", 99578556Sobrien pin, pci_get_slot(dev), pci_get_function(dev)); 99678556Sobrien return (PCI_INVALID_IRQ); 99778556Sobrien} 99878556Sobrien 99978556Sobrienstatic int 100078556Sobrienschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 100178556Sobrien{ 100278556Sobrien struct schizo_softc *sc; 100378556Sobrien 100478556Sobrien sc = device_get_softc(dev); 100578556Sobrien switch (which) { 100678556Sobrien case PCIB_IVAR_DOMAIN: 100778556Sobrien *result = device_get_unit(dev); 100878556Sobrien return (0); 100978556Sobrien case PCIB_IVAR_BUS: 101090067Ssobomax *result = sc->sc_pci_secbus; 101190067Ssobomax return (0); 101290067Ssobomax } 101390067Ssobomax return (ENOENT); 101490067Ssobomax} 101590067Ssobomax 101690067Ssobomaxstatic int 101790067Ssobomaxschizo_dma_sync_stub(void *arg) 101890067Ssobomax{ 101990067Ssobomax struct timeval cur, end; 102090067Ssobomax struct schizo_dma_sync *sds = arg; 102190067Ssobomax struct schizo_softc *sc = sds->sds_sc; 102290067Ssobomax uint32_t state; 102390067Ssobomax 102490067Ssobomax (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 102590067Ssobomax sds->sds_func, PCIR_VENDOR, 2); 102690067Ssobomax for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE, 102790067Ssobomax SCHIZO_CDMA_STATE_PENDING) == 0;) 102890067Ssobomax ; 102990067Ssobomax SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1); 103090067Ssobomax microuptime(&cur); 103190067Ssobomax end.tv_sec = 1; 103290067Ssobomax end.tv_usec = 0; 103378556Sobrien timevaladd(&end, &cur); 103490067Ssobomax for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 103590067Ssobomax SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 103690067Ssobomax microuptime(&cur); 103790067Ssobomax if (state != SCHIZO_CDMA_STATE_DONE) 103890067Ssobomax panic("%s: DMA does not sync", __func__); 103978556Sobrien return (sds->sds_handler(sds->sds_arg)); 104090067Ssobomax} 104190067Ssobomax 104290067Ssobomax#define VIS_BLOCKSIZE 64 104390067Ssobomax 104490067Ssobomaxstatic int 104590067Ssobomaxichip_dma_sync_stub(void *arg) 104690067Ssobomax{ 104790067Ssobomax static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 104890067Ssobomax struct timeval cur, end; 104990067Ssobomax struct schizo_dma_sync *sds = arg; 1050147666Ssimon struct schizo_softc *sc = sds->sds_sc; 105190067Ssobomax register_t reg, s; 105290067Ssobomax 105378556Sobrien (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 105478556Sobrien sds->sds_func, PCIR_VENDOR, 2); 105578556Sobrien SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 105690067Ssobomax microuptime(&cur); 105790067Ssobomax end.tv_sec = 1; 105878556Sobrien end.tv_usec = 0; 105978556Sobrien timevaladd(&end, &cur); 106078556Sobrien for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1061147666Ssimon sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1062147666Ssimon microuptime(&cur); 106378556Sobrien if ((reg & sds->sds_syncval) != 0) 1064147666Ssimon panic("%s: DMA does not sync", __func__); 1065167977Sdelphij 1066147666Ssimon if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1067147666Ssimon s = intr_disable(); 1068167977Sdelphij reg = rd(fprs); 1069147666Ssimon wr(fprs, reg | FPRS_FEF, 0); 1070147666Ssimon __asm __volatile("stda %%f0, [%0] %1" 1071167977Sdelphij : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1072147666Ssimon membar(Sync); 1073147666Ssimon wr(fprs, reg, 0); 107478556Sobrien intr_restore(s); 107578556Sobrien } 107678556Sobrien return (sds->sds_handler(sds->sds_arg)); 107790067Ssobomax} 107878556Sobrien 107978556Sobrienstatic void 108078556Sobrienschizo_intr_enable(void *arg) 108178556Sobrien{ 108278556Sobrien struct intr_vector *iv = arg; 108378556Sobrien struct schizo_icarg *sica = iv->iv_icarg; 108478556Sobrien 108590067Ssobomax SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 108690067Ssobomax INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 108790067Ssobomax} 108890067Ssobomax 108990067Ssobomaxstatic void 109090067Ssobomaxschizo_intr_disable(void *arg) 109190067Ssobomax{ 109290067Ssobomax struct intr_vector *iv = arg; 109390067Ssobomax struct schizo_icarg *sica = iv->iv_icarg; 109478556Sobrien 109590067Ssobomax SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 109690067Ssobomax} 109790067Ssobomax 109878556Sobrienstatic void 109978556Sobrienschizo_intr_assign(void *arg) 110078556Sobrien{ 110178556Sobrien struct intr_vector *iv = arg; 110278556Sobrien struct schizo_icarg *sica = iv->iv_icarg; 110378556Sobrien 1104167977Sdelphij SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 110578556Sobrien SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1106167977Sdelphij} 110778556Sobrien 110878556Sobrienstatic void 110978556Sobrienschizo_intr_clear(void *arg) 1110167977Sdelphij{ 111178556Sobrien struct intr_vector *iv = arg; 111278556Sobrien struct schizo_icarg *sica = iv->iv_icarg; 111378556Sobrien 111478556Sobrien SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0); 111578556Sobrien} 111678556Sobrien 111778556Sobrienstatic int 111878556Sobrienschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 111978556Sobrien int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 112078556Sobrien void **cookiep) 1121167977Sdelphij{ 1122167977Sdelphij devclass_t pci_devclass; 112378556Sobrien device_t cdev, pdev, pcidev; 112478556Sobrien struct schizo_dma_sync *sds; 112578556Sobrien struct schizo_softc *sc; 112678556Sobrien u_long vec; 112778556Sobrien int error, found; 112878556Sobrien 112978556Sobrien sc = device_get_softc(dev); 113078556Sobrien /* 113178556Sobrien * Make sure the vector is fully specified. 113278556Sobrien */ 113378556Sobrien vec = rman_get_start(ires); 113478556Sobrien if (INTIGN(vec) != sc->sc_ign) { 113578556Sobrien device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 113678556Sobrien return (EINVAL); 113778556Sobrien } 113890067Ssobomax 113978556Sobrien if (intr_vectors[vec].iv_ic == &schizo_ic) { 114078556Sobrien /* 114178556Sobrien * Ensure we use the right softc in case the interrupt 114278556Sobrien * is routed to our companion PBM for some odd reason. 114378556Sobrien */ 114478556Sobrien sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 114578556Sobrien sica_sc; 114678556Sobrien } else if (intr_vectors[vec].iv_ic == NULL) { 1147167977Sdelphij /* 1148167977Sdelphij * Work around broken firmware which misses entries in 114978556Sobrien * the ino-bitmap. 115078556Sobrien */ 115178556Sobrien error = schizo_intr_register(sc, INTINO(vec)); 115278556Sobrien if (error != 0) { 115378556Sobrien device_printf(dev, "could not register interrupt " 115478556Sobrien "controller for vector 0x%lx (%d)\n", vec, error); 115578556Sobrien return (error); 115678556Sobrien } 1157167977Sdelphij device_printf(dev, "belatedly registered as interrupt " 115878556Sobrien "controller for vector 0x%lx\n", vec); 115978556Sobrien } else { 116078556Sobrien device_printf(dev, 116178556Sobrien "invalid interrupt controller for vector 0x%lx\n", vec); 116278556Sobrien return (EINVAL); 116378556Sobrien } 116478556Sobrien 116578556Sobrien /* 116678556Sobrien * Install a a wrapper for CDMA flushing/syncing for devices 116778556Sobrien * behind PCI-PCI bridges if possible. 116878556Sobrien */ 116978556Sobrien pcidev = NULL; 117078556Sobrien found = 0; 117178556Sobrien pci_devclass = devclass_find("pci"); 117278556Sobrien for (cdev = child; cdev != dev; cdev = pdev) { 117378556Sobrien pdev = device_get_parent(cdev); 117478556Sobrien if (pcidev == NULL) { 117578556Sobrien if (device_get_devclass(pdev) != pci_devclass) 117678556Sobrien continue; 117778556Sobrien pcidev = cdev; 117878556Sobrien continue; 117978556Sobrien } 118078556Sobrien if (pci_get_class(cdev) == PCIC_BRIDGE && 118178556Sobrien pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 118278556Sobrien found = 1; 118378556Sobrien } 118490067Ssobomax if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 118590067Ssobomax sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 118690067Ssobomax if (sds == NULL) 118790067Ssobomax return (ENOMEM); 118890067Ssobomax if (found != 0 && pcidev != NULL) { 118990067Ssobomax sds->sds_sc = sc; 119090067Ssobomax sds->sds_arg = arg; 119190067Ssobomax sds->sds_ppb = 119290067Ssobomax device_get_parent(device_get_parent(pcidev)); 119390067Ssobomax sds->sds_bus = pci_get_bus(pcidev); 119478556Sobrien sds->sds_slot = pci_get_slot(pcidev); 119578556Sobrien sds->sds_func = pci_get_function(pcidev); 119678556Sobrien sds->sds_syncval = 1ULL << INTINO(vec); 119778556Sobrien if (bootverbose) 119878556Sobrien device_printf(dev, "installed DMA sync " 119978556Sobrien "wrapper for device %d.%d on bus %d\n", 120078556Sobrien sds->sds_slot, sds->sds_func, 120190067Ssobomax sds->sds_bus); 120290067Ssobomax 120390067Ssobomax#define DMA_SYNC_STUB \ 120490067Ssobomax (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 120590067Ssobomax ichip_dma_sync_stub) 120690067Ssobomax 120790067Ssobomax if (intr == NULL) { 120890067Ssobomax sds->sds_handler = filt; 120990067Ssobomax error = bus_generic_setup_intr(dev, child, 121078556Sobrien ires, flags, DMA_SYNC_STUB, intr, sds, 121178556Sobrien cookiep); 121278556Sobrien } else { 121378556Sobrien sds->sds_handler = (driver_filter_t *)intr; 121478556Sobrien error = bus_generic_setup_intr(dev, child, 121578556Sobrien ires, flags, filt, (driver_intr_t *) 121678556Sobrien DMA_SYNC_STUB, sds, cookiep); 121778556Sobrien } 121878556Sobrien 121990067Ssobomax#undef DMA_SYNC_STUB 122090067Ssobomax 122190067Ssobomax } else 122290067Ssobomax error = bus_generic_setup_intr(dev, child, ires, 122390067Ssobomax flags, filt, intr, arg, cookiep); 122490067Ssobomax if (error != 0) { 122578556Sobrien free(sds, M_DEVBUF); 122678556Sobrien return (error); 122778556Sobrien } 122878556Sobrien sds->sds_cookie = *cookiep; 122978556Sobrien *cookiep = sds; 123078556Sobrien return (error); 123178556Sobrien } else if (found != 0) 123278556Sobrien device_printf(dev, "WARNING: using devices behind PCI-PCI " 123378556Sobrien "bridges may cause data corruption\n"); 123478556Sobrien return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 123578556Sobrien arg, cookiep)); 123678556Sobrien} 123778556Sobrien 123878556Sobrienstatic int 123978556Sobrienschizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 124078556Sobrien void *cookie) 124178556Sobrien{ 124278556Sobrien struct schizo_dma_sync *sds; 124378556Sobrien struct schizo_softc *sc; 124478556Sobrien int error; 124578556Sobrien 124678556Sobrien sc = device_get_softc(dev); 124778556Sobrien if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 124878556Sobrien sds = cookie; 124978556Sobrien error = bus_generic_teardown_intr(dev, child, vec, 125078556Sobrien sds->sds_cookie); 125178556Sobrien if (error == 0) 125278556Sobrien free(sds, M_DEVBUF); 125378556Sobrien return (error); 125478556Sobrien } 125578556Sobrien return (bus_generic_teardown_intr(dev, child, vec, cookie)); 125678556Sobrien} 125778556Sobrien 125878556Sobrienstatic struct resource * 125978556Sobrienschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 126078556Sobrien u_long start, u_long end, u_long count, u_int flags) 126178556Sobrien{ 126278556Sobrien struct schizo_softc *sc; 126378556Sobrien struct resource *rv; 126490067Ssobomax struct rman *rm; 126578556Sobrien bus_space_tag_t bt; 126678556Sobrien bus_space_handle_t bh; 126778556Sobrien int needactivate = flags & RF_ACTIVE; 126878556Sobrien 126978556Sobrien flags &= ~RF_ACTIVE; 127078556Sobrien 127178556Sobrien sc = device_get_softc(bus); 127278556Sobrien if (type == SYS_RES_IRQ) { 127378556Sobrien /* 127478556Sobrien * XXX: Don't accept blank ranges for now, only single 127578556Sobrien * interrupts. The other case should not happen with 127678556Sobrien * the MI PCI code... 127778556Sobrien * XXX: This may return a resource that is out of the 127878556Sobrien * range that was specified. Is this correct...? 127978556Sobrien */ 128078556Sobrien if (start != end) 128178556Sobrien panic("%s: XXX: interrupt range", __func__); 128278556Sobrien start = end = INTMAP_VEC(sc->sc_ign, end); 128378556Sobrien return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 128478556Sobrien rid, start, end, count, flags)); 128578556Sobrien } 128678556Sobrien switch (type) { 128778556Sobrien case SYS_RES_MEMORY: 128878556Sobrien rm = &sc->sc_pci_mem_rman; 128978556Sobrien bt = sc->sc_pci_memt; 129078556Sobrien bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 129178556Sobrien break; 129278556Sobrien case SYS_RES_IOPORT: 129378556Sobrien rm = &sc->sc_pci_io_rman; 129478556Sobrien bt = sc->sc_pci_iot; 129578556Sobrien bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 129678556Sobrien break; 129778556Sobrien default: 129878556Sobrien return (NULL); 129978556Sobrien /* NOTREACHED */ 1300147666Ssimon } 130178556Sobrien 130278556Sobrien rv = rman_reserve_resource(rm, start, end, count, flags, child); 130378556Sobrien if (rv == NULL) 130478556Sobrien return (NULL); 130578556Sobrien rman_set_rid(rv, *rid); 130678556Sobrien bh += rman_get_start(rv); 130778556Sobrien rman_set_bustag(rv, bt); 130878556Sobrien rman_set_bushandle(rv, bh); 130978556Sobrien 131078556Sobrien if (needactivate) { 131178556Sobrien if (bus_activate_resource(child, type, *rid, rv)) { 131278556Sobrien rman_release_resource(rv); 131378556Sobrien return (NULL); 131478556Sobrien } 131578556Sobrien } 131678556Sobrien return (rv); 131778556Sobrien} 131878556Sobrien 131978556Sobrienstatic int 132078556Sobrienschizo_activate_resource(device_t bus, device_t child, int type, int rid, 132190067Ssobomax struct resource *r) 132278556Sobrien{ 132378556Sobrien void *p; 132478556Sobrien int error; 132578556Sobrien 132678556Sobrien if (type == SYS_RES_IRQ) 132778556Sobrien return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 132878556Sobrien type, rid, r)); 132978556Sobrien if (type == SYS_RES_MEMORY) { 133078556Sobrien /* 1331167977Sdelphij * Need to memory-map the device space, as some drivers 1332167977Sdelphij * depend on the virtual address being set and usable. 133378556Sobrien */ 133478556Sobrien error = sparc64_bus_mem_map(rman_get_bustag(r), 133578556Sobrien rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 133678556Sobrien if (error != 0) 133778556Sobrien return (error); 133878556Sobrien rman_set_virtual(r, p); 133978556Sobrien } 134078556Sobrien return (rman_activate_resource(r)); 134178556Sobrien} 134278556Sobrien 134378556Sobrienstatic int 134478556Sobrienschizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1345167977Sdelphij struct resource *r) 134678556Sobrien{ 134778556Sobrien 134878556Sobrien if (type == SYS_RES_IRQ) 134978556Sobrien return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 135078556Sobrien type, rid, r)); 135178556Sobrien if (type == SYS_RES_MEMORY) { 135278556Sobrien sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 135378556Sobrien rman_set_virtual(r, NULL); 135478556Sobrien } 135578556Sobrien return (rman_deactivate_resource(r)); 135678556Sobrien} 135778556Sobrien 135878556Sobrienstatic int 135978556Sobrienschizo_release_resource(device_t bus, device_t child, int type, int rid, 136078556Sobrien struct resource *r) 136178556Sobrien{ 136278556Sobrien int error; 136390067Ssobomax 136490067Ssobomax if (type == SYS_RES_IRQ) 136590067Ssobomax return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 136690067Ssobomax type, rid, r)); 136790067Ssobomax if (rman_get_flags(r) & RF_ACTIVE) { 136890067Ssobomax error = bus_deactivate_resource(child, type, rid, r); 136990067Ssobomax if (error) 137090067Ssobomax return (error); 137190067Ssobomax } 137290067Ssobomax return (rman_release_resource(r)); 137378556Sobrien} 137478556Sobrien 137578556Sobrienstatic bus_dma_tag_t 137678556Sobrienschizo_get_dma_tag(device_t bus, device_t child) 137778556Sobrien{ 137878556Sobrien struct schizo_softc *sc; 137978556Sobrien 138078556Sobrien sc = device_get_softc(bus); 138178556Sobrien return (sc->sc_pci_dmat); 138278556Sobrien} 138378556Sobrien 138478556Sobrienstatic phandle_t 138578556Sobrienschizo_get_node(device_t bus, device_t dev) 138678556Sobrien{ 138790067Ssobomax struct schizo_softc *sc; 138890067Ssobomax 138990067Ssobomax sc = device_get_softc(bus); 139090067Ssobomax /* We only have one child, the PCI bus, which needs our own node. */ 139190067Ssobomax return (sc->sc_node); 139290067Ssobomax} 139390067Ssobomax 139490067Ssobomaxstatic bus_space_tag_t 139590067Ssobomaxschizo_alloc_bus_tag(struct schizo_softc *sc, int type) 139678556Sobrien{ 139778556Sobrien bus_space_tag_t bt; 139878556Sobrien 139978556Sobrien bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 140078556Sobrien M_NOWAIT | M_ZERO); 140178556Sobrien if (bt == NULL) 140278556Sobrien panic("%s: out of memory", __func__); 140378556Sobrien 140478556Sobrien bt->bst_cookie = sc; 140590067Ssobomax bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 140690067Ssobomax bt->bst_type = type; 140790067Ssobomax return (bt); 140890067Ssobomax} 140990067Ssobomax 141090067Ssobomaxstatic u_int 141178556Sobrienschizo_get_timecount(struct timecounter *tc) 141278556Sobrien{ 141378556Sobrien struct schizo_softc *sc; 141478556Sobrien 141578556Sobrien sc = tc->tc_priv; 141678556Sobrien return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 141778556Sobrien (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 141878556Sobrien} 141978556Sobrien