schizo.c revision 230664
1249259Sdim/*- 2249259Sdim * Copyright (c) 1999, 2000 Matthew R. Green 3249259Sdim * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4249259Sdim * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 5249259Sdim * All rights reserved. 6249259Sdim * 7249259Sdim * Redistribution and use in source and binary forms, with or without 8249259Sdim * modification, are permitted provided that the following conditions 9249259Sdim * are met: 10249259Sdim * 1. Redistributions of source code must retain the above copyright 11249259Sdim * notice, this list of conditions and the following disclaimer. 12249259Sdim * 2. Redistributions in binary form must reproduce the above copyright 13249259Sdim * notice, this list of conditions and the following disclaimer in the 14249259Sdim * documentation and/or other materials provided with the distribution. 15249259Sdim * 3. The name of the author may not be used to endorse or promote products 16249259Sdim * derived from this software without specific prior written permission. 17249259Sdim * 18249259Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19249259Sdim * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20249259Sdim * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21249259Sdim * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22249259Sdim * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23249259Sdim * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24249259Sdim * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25249259Sdim * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26249259Sdim * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27249259Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28249259Sdim * SUCH DAMAGE. 29249259Sdim * 30249259Sdim * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31249259Sdim * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32249259Sdim */ 33249259Sdim 34249259Sdim#include <sys/cdefs.h> 35249259Sdim__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 230664 2012-01-28 22:42:33Z marius $"); 36249259Sdim 37249259Sdim/* 38249259Sdim * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 39249259Sdim * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 40249259Sdim */ 41249259Sdim 42249259Sdim#include "opt_ofw_pci.h" 43249259Sdim#include "opt_schizo.h" 44249259Sdim 45249259Sdim#include <sys/param.h> 46249259Sdim#include <sys/systm.h> 47249259Sdim#include <sys/bus.h> 48249259Sdim#include <sys/kernel.h> 49249259Sdim#include <sys/lock.h> 50249259Sdim#include <sys/malloc.h> 51249259Sdim#include <sys/module.h> 52249259Sdim#include <sys/mutex.h> 53249259Sdim#include <sys/pcpu.h> 54249259Sdim#include <sys/rman.h> 55249259Sdim#include <sys/sysctl.h> 56249259Sdim#include <sys/time.h> 57249259Sdim#include <sys/timetc.h> 58249259Sdim 59249259Sdim#include <dev/ofw/ofw_bus.h> 60249259Sdim#include <dev/ofw/ofw_pci.h> 61249259Sdim#include <dev/ofw/openfirm.h> 62249259Sdim 63249259Sdim#include <machine/bus.h> 64249259Sdim#include <machine/bus_common.h> 65249259Sdim#include <machine/bus_private.h> 66249259Sdim#include <machine/fsr.h> 67249259Sdim#include <machine/iommureg.h> 68249259Sdim#include <machine/iommuvar.h> 69249259Sdim#include <machine/resource.h> 70249259Sdim 71249259Sdim#include <dev/pci/pcireg.h> 72249259Sdim#include <dev/pci/pcivar.h> 73249259Sdim 74249259Sdim#include <sparc64/pci/ofw_pci.h> 75249259Sdim#include <sparc64/pci/schizoreg.h> 76249259Sdim#include <sparc64/pci/schizovar.h> 77249259Sdim 78249259Sdim#include "pcib_if.h" 79249259Sdim 80249259Sdimstatic const struct schizo_desc *schizo_get_desc(device_t); 81249259Sdimstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82249259Sdim driver_filter_t); 83249259Sdimstatic void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 84249259Sdim bus_dmasync_op_t op); 85249259Sdimstatic void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 86249259Sdim bus_dmasync_op_t op); 87249259Sdimstatic void schizo_intr_enable(void *); 88249259Sdimstatic void schizo_intr_disable(void *); 89249259Sdimstatic void schizo_intr_assign(void *); 90249259Sdimstatic void schizo_intr_clear(void *); 91249259Sdimstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 92249259Sdimstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 93249259Sdim bus_addr_t *, bus_addr_t *); 94249259Sdimstatic timecounter_get_t schizo_get_timecount; 95249259Sdim 96249259Sdim/* Interrupt handlers */ 97249259Sdimstatic driver_filter_t schizo_pci_bus; 98249259Sdimstatic driver_filter_t schizo_ue; 99249259Sdimstatic driver_filter_t schizo_ce; 100249259Sdimstatic driver_filter_t schizo_host_bus; 101249259Sdimstatic driver_filter_t schizo_cdma; 102249259Sdim 103249259Sdim/* IOMMU support */ 104249259Sdimstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 105249259Sdim 106249259Sdim/* 107249259Sdim * Methods 108249259Sdim */ 109249259Sdimstatic device_probe_t schizo_probe; 110249259Sdimstatic device_attach_t schizo_attach; 111249259Sdimstatic bus_read_ivar_t schizo_read_ivar; 112249259Sdimstatic bus_setup_intr_t schizo_setup_intr; 113249259Sdimstatic bus_alloc_resource_t schizo_alloc_resource; 114249259Sdimstatic bus_activate_resource_t schizo_activate_resource; 115249259Sdimstatic bus_adjust_resource_t schizo_adjust_resource; 116249259Sdimstatic bus_get_dma_tag_t schizo_get_dma_tag; 117249259Sdimstatic pcib_maxslots_t schizo_maxslots; 118249259Sdimstatic pcib_read_config_t schizo_read_config; 119249259Sdimstatic pcib_write_config_t schizo_write_config; 120249259Sdimstatic pcib_route_interrupt_t schizo_route_interrupt; 121249259Sdimstatic ofw_bus_get_node_t schizo_get_node; 122249259Sdimstatic ofw_pci_setup_device_t schizo_setup_device; 123249259Sdim 124249259Sdimstatic device_method_t schizo_methods[] = { 125249259Sdim /* Device interface */ 126249259Sdim DEVMETHOD(device_probe, schizo_probe), 127249259Sdim DEVMETHOD(device_attach, schizo_attach), 128249259Sdim DEVMETHOD(device_shutdown, bus_generic_shutdown), 129249259Sdim DEVMETHOD(device_suspend, bus_generic_suspend), 130249259Sdim DEVMETHOD(device_resume, bus_generic_resume), 131249259Sdim 132249259Sdim /* Bus interface */ 133249259Sdim DEVMETHOD(bus_read_ivar, schizo_read_ivar), 134249259Sdim DEVMETHOD(bus_setup_intr, schizo_setup_intr), 135249259Sdim DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 136249259Sdim DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 137249259Sdim DEVMETHOD(bus_activate_resource, schizo_activate_resource), 138249259Sdim DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 139249259Sdim DEVMETHOD(bus_adjust_resource, schizo_adjust_resource), 140249259Sdim DEVMETHOD(bus_release_resource, bus_generic_release_resource), 141249259Sdim DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 142249259Sdim 143249259Sdim /* pcib interface */ 144249259Sdim DEVMETHOD(pcib_maxslots, schizo_maxslots), 145249259Sdim DEVMETHOD(pcib_read_config, schizo_read_config), 146249259Sdim DEVMETHOD(pcib_write_config, schizo_write_config), 147249259Sdim DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 148249259Sdim 149249259Sdim /* ofw_bus interface */ 150249259Sdim DEVMETHOD(ofw_bus_get_node, schizo_get_node), 151249259Sdim 152249259Sdim /* ofw_pci interface */ 153249259Sdim DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 154249259Sdim 155249259Sdim DEVMETHOD_END 156249259Sdim}; 157249259Sdim 158249259Sdimstatic devclass_t schizo_devclass; 159249259Sdim 160249259SdimDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 161249259Sdim sizeof(struct schizo_softc)); 162249259SdimEARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 163249259Sdim BUS_PASS_BUS); 164249259Sdim 165249259Sdimstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 166249259Sdim SLIST_HEAD_INITIALIZER(schizo_softcs); 167249259Sdim 168249259Sdimstatic const struct intr_controller schizo_ic = { 169249259Sdim schizo_intr_enable, 170249259Sdim schizo_intr_disable, 171249259Sdim schizo_intr_assign, 172249259Sdim schizo_intr_clear 173249259Sdim}; 174249259Sdim 175249259Sdimstruct schizo_icarg { 176249259Sdim struct schizo_softc *sica_sc; 177249259Sdim bus_addr_t sica_map; 178249259Sdim bus_addr_t sica_clr; 179249259Sdim}; 180249259Sdim 181249259Sdim#define SCHIZO_CDMA_TIMEOUT 1 /* 1 second per try */ 182249259Sdim#define SCHIZO_CDMA_TRIES 15 183249259Sdim#define SCHIZO_PERF_CNT_QLTY 100 184249259Sdim 185249259Sdim#define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 186249259Sdim bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 187249259Sdim#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 188249259Sdim bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 189249259Sdim#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 190249259Sdim bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 191249259Sdim 192249259Sdim#ifndef SCHIZO_DEBUG 193249259Sdim#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 194249259Sdim SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 195249259Sdim#else 196249259Sdim#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 197249259Sdim device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 198249259Sdim (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 199249259Sdim (unsigned long long)(v)); \ 200249259Sdim SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 201249259Sdim } while (0) 202249259Sdim#endif 203249259Sdim 204249259Sdim#define SCHIZO_PCI_READ_8(sc, offs) \ 205249259Sdim SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 206249259Sdim#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 207249259Sdim SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 208249259Sdim#define SCHIZO_CTRL_READ_8(sc, offs) \ 209249259Sdim SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 210249259Sdim#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 211249259Sdim SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 212249259Sdim#define SCHIZO_PCICFG_READ_8(sc, offs) \ 213249259Sdim SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 214249259Sdim#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 215249259Sdim SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 216249259Sdim#define SCHIZO_ICON_READ_8(sc, offs) \ 217249259Sdim SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 218249259Sdim#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 219249259Sdim SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 220249259Sdim 221249259Sdim#define SCHIZO_PCI_SET(sc, offs, v) \ 222249259Sdim SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 223249259Sdim#define SCHIZO_CTRL_SET(sc, offs, v) \ 224249259Sdim SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 225249259Sdim 226249259Sdimstruct schizo_desc { 227249259Sdim const char *sd_string; 228249259Sdim int sd_mode; 229249259Sdim const char *sd_name; 230249259Sdim}; 231249259Sdim 232249259Sdimstatic const struct schizo_desc const schizo_compats[] = { 233249259Sdim { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 234249259Sdim#if 0 235249259Sdim { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 236249259Sdim#endif 237249259Sdim { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 238249259Sdim { NULL, 0, NULL } 239249259Sdim}; 240249259Sdim 241249259Sdimstatic const struct schizo_desc * 242249259Sdimschizo_get_desc(device_t dev) 243249259Sdim{ 244249259Sdim const struct schizo_desc *desc; 245249259Sdim const char *compat; 246249259Sdim 247249259Sdim compat = ofw_bus_get_compat(dev); 248249259Sdim if (compat == NULL) 249249259Sdim return (NULL); 250249259Sdim for (desc = schizo_compats; desc->sd_string != NULL; desc++) 251249259Sdim if (strcmp(desc->sd_string, compat) == 0) 252249259Sdim return (desc); 253249259Sdim return (NULL); 254249259Sdim} 255249259Sdim 256249259Sdimstatic int 257249259Sdimschizo_probe(device_t dev) 258249259Sdim{ 259249259Sdim const char *dtype; 260249259Sdim 261249259Sdim dtype = ofw_bus_get_type(dev); 262249259Sdim if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 263249259Sdim schizo_get_desc(dev) != NULL) { 264249259Sdim device_set_desc(dev, "Sun Host-PCI bridge"); 265249259Sdim return (0); 266249259Sdim } 267249259Sdim return (ENXIO); 268249259Sdim} 269249259Sdim 270249259Sdimstatic int 271249259Sdimschizo_attach(device_t dev) 272249259Sdim{ 273249259Sdim struct ofw_pci_ranges *range; 274249259Sdim const struct schizo_desc *desc; 275249259Sdim struct schizo_softc *asc, *sc, *osc; 276249259Sdim struct timecounter *tc; 277249259Sdim uint64_t ino_bitmap, reg; 278249259Sdim phandle_t node; 279249259Sdim uint32_t prop, prop_array[2]; 280249259Sdim int i, j, mode, rid, tsbsize; 281249259Sdim 282249259Sdim sc = device_get_softc(dev); 283249259Sdim node = ofw_bus_get_node(dev); 284249259Sdim desc = schizo_get_desc(dev); 285249259Sdim mode = desc->sd_mode; 286249259Sdim 287249259Sdim sc->sc_dev = dev; 288249259Sdim sc->sc_node = node; 289249259Sdim sc->sc_mode = mode; 290249259Sdim sc->sc_flags = 0; 291249259Sdim 292249259Sdim /* 293249259Sdim * The Schizo has three register banks: 294249259Sdim * (0) per-PBM PCI configuration and status registers, but for bus B 295249259Sdim * shared with the UPA64s interrupt mapping register banks 296249259Sdim * (1) shared Schizo controller configuration and status registers 297249259Sdim * (2) per-PBM PCI configuration space 298249259Sdim * 299249259Sdim * The Tomatillo has four register banks: 300249259Sdim * (0) per-PBM PCI configuration and status registers 301249259Sdim * (1) per-PBM Tomatillo controller configuration registers, but on 302249259Sdim * machines having the `jbusppm' device shared with its Estar 303249259Sdim * register bank for bus A 304249259Sdim * (2) per-PBM PCI configuration space 305249259Sdim * (3) per-PBM interrupt concentrator registers 306249259Sdim */ 307249259Sdim sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 308249259Sdim 20) & 1; 309249259Sdim for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 310249259Sdim i++) { 311249259Sdim rid = i; 312249259Sdim sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 313249259Sdim SYS_RES_MEMORY, &rid, 314249259Sdim (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 315249259Sdim i == STX_PCI) || i == STX_CTRL)) || 316249259Sdim (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 317249259Sdim i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 318249259Sdim if (sc->sc_mem_res[i] == NULL) 319249259Sdim panic("%s: could not allocate register bank %d", 320249259Sdim __func__, i); 321249259Sdim } 322249259Sdim 323249259Sdim /* 324249259Sdim * Match other Schizos that are already configured against 325249259Sdim * the controller base physical address. This will be the 326249259Sdim * same for a pair of devices that share register space. 327249259Sdim */ 328249259Sdim osc = NULL; 329249259Sdim SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 330249259Sdim if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 331249259Sdim rman_get_start(sc->sc_mem_res[STX_CTRL])) { 332249259Sdim /* Found partner. */ 333249259Sdim osc = asc; 334249259Sdim break; 335249259Sdim } 336249259Sdim } 337249259Sdim if (osc == NULL) { 338249259Sdim sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 339249259Sdim M_NOWAIT | M_ZERO); 340249259Sdim if (sc->sc_mtx == NULL) 341249259Sdim panic("%s: could not malloc mutex", __func__); 342249259Sdim mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 343249259Sdim } else { 344249259Sdim if (sc->sc_mode != SCHIZO_MODE_SCZ) 345249259Sdim panic("%s: no partner expected", __func__); 346249259Sdim if (mtx_initialized(osc->sc_mtx) == 0) 347249259Sdim panic("%s: mutex not initialized", __func__); 348249259Sdim sc->sc_mtx = osc->sc_mtx; 349249259Sdim } 350249259Sdim 351249259Sdim if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 352249259Sdim panic("%s: could not determine IGN", __func__); 353249259Sdim if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 354249259Sdim -1) 355249259Sdim panic("%s: could not determine version", __func__); 356249259Sdim if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 357249259Sdim &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 358249259Sdim panic("%s: could not determine module-revision", __func__); 359249259Sdim if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 360249259Sdim prop = 33000000; 361249259Sdim 362249259Sdim if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 363249259Sdim XMS_PCI_CTRL_X_MODE) != 0) { 364249259Sdim if (sc->sc_mrev < 1) 365249259Sdim panic("PCI-X mode unsupported"); 366249259Sdim sc->sc_flags |= SCHIZO_FLAGS_XMODE; 367249259Sdim } 368249259Sdim 369249259Sdim device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 370249259Sdim if (mode == SCHIZO_MODE_XMS) 371249259Sdim printf("module-revision %d, ", sc->sc_mrev); 372249259Sdim printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 373249259Sdim 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 374249259Sdim "-X" : "", prop / 1000 / 1000); 375249259Sdim 376249259Sdim /* Set up the PCI interrupt retry timer. */ 377249259Sdim SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 378249259Sdim 379249259Sdim /* Set up the PCI control register. */ 380249259Sdim reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 381249259Sdim reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 382249259Sdim STX_PCI_CTRL_ARB_MASK); 383249259Sdim reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 384249259Sdim STX_PCI_CTRL_ERR_IEN; 385249259Sdim if (OF_getproplen(node, "no-bus-parking") < 0) 386249259Sdim reg |= STX_PCI_CTRL_ARB_PARK; 387249259Sdim if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 388249259Sdim reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 389249259Sdim else 390249259Sdim reg |= STX_PCI_CTRL_ARB_MASK; 391249259Sdim if (mode == SCHIZO_MODE_TOM) { 392249259Sdim reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 393249259Sdim if (sc->sc_ver <= 1) /* revision <= 2.0 */ 394249259Sdim reg |= TOM_PCI_CTRL_DTO_IEN; 395249259Sdim else 396249259Sdim reg |= STX_PCI_CTRL_PTO; 397249259Sdim } else if (mode == SCHIZO_MODE_XMS) { 398249259Sdim SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 399249259Sdim SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 400249259Sdim reg |= XMS_PCI_CTRL_X_ERRINT_EN; 401249259Sdim } 402249259Sdim SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 403249259Sdim 404249259Sdim /* Set up the PCI diagnostic register. */ 405249259Sdim reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 406249259Sdim reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 407249259Sdim STX_PCI_DIAG_INTRSYNC_DIS); 408249259Sdim SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 409249259Sdim 410249259Sdim /* 411249259Sdim * Enable DMA write parity error interrupts of version >= 7 (i.e. 412249259Sdim * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 413249259Sdim * no effect though). 414249259Sdim */ 415249259Sdim if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 416249259Sdim mode == SCHIZO_MODE_XMS) { 417249259Sdim reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 418249259Sdim reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 419249259Sdim SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 420249259Sdim } 421249259Sdim 422249259Sdim /* 423249259Sdim * On Tomatillo clear the I/O prefetch lengths (workaround for a 424249259Sdim * Jalapeno bug). 425249259Sdim */ 426249259Sdim if (mode == SCHIZO_MODE_TOM) 427249259Sdim SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 428249259Sdim (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 429249259Sdim TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 430249259Sdim 431249259Sdim /* 432249259Sdim * Hunt through all the interrupt mapping regs and register 433249259Sdim * the interrupt controller for our interrupt vectors. We do 434249259Sdim * this early in order to be able to catch stray interrupts. 435249259Sdim * This is complicated by the fact that a pair of Schizo PBMs 436249259Sdim * shares one IGN. 437249259Sdim */ 438249259Sdim i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 439249259Sdim sizeof(prop_array)); 440249259Sdim if (i != -1) 441249259Sdim ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 442249259Sdim else { 443249259Sdim /* 444249259Sdim * If the ino-bitmap property is missing, just provide the 445249259Sdim * default set of interrupts for this controller and let 446249259Sdim * schizo_setup_intr() take care of child interrupts. 447249259Sdim */ 448249259Sdim if (sc->sc_half == 0) 449249259Sdim ino_bitmap = (1ULL << STX_UE_INO) | 450249259Sdim (1ULL << STX_CE_INO) | 451249259Sdim (1ULL << STX_PCIERR_A_INO) | 452249259Sdim (1ULL << STX_BUS_INO); 453249259Sdim else 454249259Sdim ino_bitmap = 1ULL << STX_PCIERR_B_INO; 455249259Sdim } 456249259Sdim for (i = 0; i <= STX_MAX_INO; i++) { 457249259Sdim if ((ino_bitmap & (1ULL << i)) == 0) 458249259Sdim continue; 459249259Sdim if (i == STX_FB0_INO || i == STX_FB1_INO) 460249259Sdim /* Leave for upa(4). */ 461249259Sdim continue; 462249259Sdim j = schizo_intr_register(sc, i); 463249259Sdim if (j != 0) 464249259Sdim device_printf(dev, "could not register interrupt " 465249259Sdim "controller for INO %d (%d)\n", i, j); 466249259Sdim } 467249259Sdim 468249259Sdim /* 469249259Sdim * Setup Safari/JBus performance counter 0 in bus cycle counting 470249259Sdim * mode as timecounter. Unfortunately, this is broken with at 471249259Sdim * least the version 4 Tomatillos found in Fire V120 and Blade 472249259Sdim * 1500, which apparently actually count some different event at 473249259Sdim * ~0.5 and 3MHz respectively instead (also when running in full 474249259Sdim * power mode). Besides, one counter seems to be shared by a 475249259Sdim * "pair" of Tomatillos, too. 476249259Sdim */ 477249259Sdim if (sc->sc_half == 0) { 478249259Sdim SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 479249259Sdim (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 480249259Sdim (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 481249259Sdim tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 482249259Sdim if (tc == NULL) 483249259Sdim panic("%s: could not malloc timecounter", __func__); 484249259Sdim tc->tc_get_timecount = schizo_get_timecount; 485249259Sdim tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 486249259Sdim if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 487249259Sdim sizeof(prop)) == -1) 488249259Sdim panic("%s: could not determine clock frequency", 489249259Sdim __func__); 490249259Sdim tc->tc_frequency = prop; 491249259Sdim tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 492249259Sdim if (mode == SCHIZO_MODE_SCZ) 493249259Sdim tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 494249259Sdim else 495249259Sdim tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 496249259Sdim tc->tc_priv = sc; 497249259Sdim tc_init(tc); 498249259Sdim } 499249259Sdim 500249259Sdim /* 501249259Sdim * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 502249259Sdim * one per PBM. Schizo and XMITS additionally have a streaming 503249259Sdim * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 504249259Sdim * affected by several errata though. However, except for context 505249259Sdim * flushes, taking advantage of it should be okay even with those. 506249259Sdim */ 507249259Sdim memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 508249259Sdim sizeof(sc->sc_dma_methods)); 509249259Sdim sc->sc_is.sis_sc = sc; 510249259Sdim sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 511249259Sdim sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 512249259Sdim sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 513249259Sdim if (OF_getproplen(node, "no-streaming-cache") < 0) 514249259Sdim sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 515249259Sdim 516249259Sdim#define TSBCASE(x) \ 517249259Sdim case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 518249259Sdim tsbsize = (x); \ 519249259Sdim break; \ 520249259Sdim 521249259Sdim i = OF_getprop(node, "virtual-dma", (void *)prop_array, 522249259Sdim sizeof(prop_array)); 523249259Sdim if (i == -1 || i != sizeof(prop_array)) 524249259Sdim schizo_iommu_init(sc, 7, -1); 525249259Sdim else { 526249259Sdim switch (prop_array[1]) { 527249259Sdim TSBCASE(1); 528249259Sdim TSBCASE(2); 529249259Sdim TSBCASE(3); 530249259Sdim TSBCASE(4); 531249259Sdim TSBCASE(5); 532249259Sdim TSBCASE(6); 533249259Sdim TSBCASE(7); 534249259Sdim TSBCASE(8); 535249259Sdim default: 536249259Sdim panic("%s: unsupported DVMA size 0x%x", 537249259Sdim __func__, prop_array[1]); 538249259Sdim /* NOTREACHED */ 539249259Sdim } 540249259Sdim schizo_iommu_init(sc, tsbsize, prop_array[0]); 541249259Sdim } 542249259Sdim 543249259Sdim#undef TSBCASE 544249259Sdim 545249259Sdim /* Initialize memory and I/O rmans. */ 546249259Sdim sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 547249259Sdim sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 548249259Sdim if (rman_init(&sc->sc_pci_io_rman) != 0 || 549249259Sdim rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 550249259Sdim panic("%s: failed to set up I/O rman", __func__); 551249259Sdim sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 552249259Sdim sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 553249259Sdim if (rman_init(&sc->sc_pci_mem_rman) != 0 || 554249259Sdim rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 555249259Sdim panic("%s: failed to set up memory rman", __func__); 556249259Sdim 557249259Sdim i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 558249259Sdim /* 559249259Sdim * Make sure that the expected ranges are present. The 560249259Sdim * OFW_PCI_CS_MEM64 one is not currently used though. 561249259Sdim */ 562249259Sdim if (i != STX_NRANGE) 563249259Sdim panic("%s: unsupported number of ranges", __func__); 564249259Sdim /* 565249259Sdim * Find the addresses of the various bus spaces. 566249259Sdim * There should not be multiple ones of one kind. 567249259Sdim * The physical start addresses of the ranges are the configuration, 568249259Sdim * memory and I/O handles. 569249259Sdim */ 570249259Sdim for (i = 0; i < STX_NRANGE; i++) { 571249259Sdim j = OFW_PCI_RANGE_CS(&range[i]); 572249259Sdim if (sc->sc_pci_bh[j] != 0) 573249259Sdim panic("%s: duplicate range for space %d", 574249259Sdim __func__, j); 575249259Sdim sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 576249259Sdim } 577249259Sdim free(range, M_OFWPROP); 578249259Sdim 579249259Sdim /* Register the softc, this is needed for paired Schizos. */ 580249259Sdim SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 581249259Sdim 582249259Sdim /* Allocate our tags. */ 583249259Sdim sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 584249259Sdim sc->sc_mem_res[STX_PCI]), PCI_IO_BUS_SPACE, NULL); 585249259Sdim if (sc->sc_pci_iot == NULL) 586249259Sdim panic("%s: could not allocate PCI I/O tag", __func__); 587249259Sdim sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 588249259Sdim sc->sc_mem_res[STX_PCI]), PCI_CONFIG_BUS_SPACE, NULL); 589249259Sdim if (sc->sc_pci_cfgt == NULL) 590249259Sdim panic("%s: could not allocate PCI configuration space tag", 591249259Sdim __func__); 592249259Sdim if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 593249259Sdim sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 594249259Sdim sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 595249259Sdim &sc->sc_pci_dmat) != 0) 596249259Sdim panic("%s: could not create PCI DMA tag", __func__); 597249259Sdim /* Customize the tag. */ 598249259Sdim sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 599249259Sdim sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods; 600249259Sdim 601249259Sdim /* 602249259Sdim * Get the bus range from the firmware. 603249259Sdim * NB: Tomatillos don't support PCI bus reenumeration. 604249259Sdim */ 605249259Sdim i = OF_getprop(node, "bus-range", (void *)prop_array, 606249259Sdim sizeof(prop_array)); 607249259Sdim if (i == -1) 608249259Sdim panic("%s: could not get bus-range", __func__); 609249259Sdim if (i != sizeof(prop_array)) 610249259Sdim panic("%s: broken bus-range (%d)", __func__, i); 611249259Sdim sc->sc_pci_secbus = prop_array[0]; 612249259Sdim sc->sc_pci_subbus = prop_array[1]; 613249259Sdim if (bootverbose) 614249259Sdim device_printf(dev, "bus range %u to %u; PCI bus %d\n", 615249259Sdim sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 616249259Sdim 617249259Sdim /* Clear any pending PCI error bits. */ 618249259Sdim PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 619249259Sdim PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 620249259Sdim STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 621249259Sdim SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 622249259Sdim SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 623249259Sdim 624249259Sdim /* 625249259Sdim * Establish handlers for interesting interrupts... 626249259Sdim * Someone at Sun clearly was smoking crack; with Schizos PCI 627249259Sdim * bus error interrupts for one PBM can be routed to the other 628249259Sdim * PBM though we obviously need to use the softc of the former 629249259Sdim * as the argument for the interrupt handler and the softc of 630249259Sdim * the latter as the argument for the interrupt controller. 631249259Sdim */ 632249259Sdim if (sc->sc_half == 0) { 633249259Sdim if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 634249259Sdim (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 635249259Sdim INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 636249259Sdim sica_sc == osc)) 637249259Sdim /* 638249259Sdim * We are the driver for PBM A and either also 639249259Sdim * registered the interrupt controller for us or 640249259Sdim * the driver for PBM B has probed first and 641249259Sdim * registered it for us. 642249259Sdim */ 643249259Sdim schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 644249259Sdim schizo_pci_bus); 645249259Sdim if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 646249259Sdim osc != NULL) 647249259Sdim /* 648249259Sdim * We are the driver for PBM A but registered 649249259Sdim * the interrupt controller for PBM B, i.e. the 650249259Sdim * driver for PBM B attached first but couldn't 651249259Sdim * set up a handler for PBM B. 652249259Sdim */ 653249259Sdim schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 654249259Sdim schizo_pci_bus); 655249259Sdim } else { 656249259Sdim if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 657249259Sdim (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 658249259Sdim INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 659249259Sdim sica_sc == osc)) 660249259Sdim /* 661249259Sdim * We are the driver for PBM B and either also 662249259Sdim * registered the interrupt controller for us or 663249259Sdim * the driver for PBM A has probed first and 664249259Sdim * registered it for us. 665249259Sdim */ 666249259Sdim schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 667249259Sdim schizo_pci_bus); 668249259Sdim if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 669249259Sdim osc != NULL) 670249259Sdim /* 671249259Sdim * We are the driver for PBM B but registered 672249259Sdim * the interrupt controller for PBM A, i.e. the 673249259Sdim * driver for PBM A attached first but couldn't 674249259Sdim * set up a handler for PBM A. 675249259Sdim */ 676249259Sdim schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 677249259Sdim schizo_pci_bus); 678249259Sdim } 679249259Sdim if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 680249259Sdim schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 681249259Sdim if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 682249259Sdim schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 683249259Sdim if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 684249259Sdim schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 685249259Sdim 686249259Sdim /* 687249259Sdim * According to the Schizo Errata I-13, consistent DMA flushing/ 688249259Sdim * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 689249259Sdim * so we can't use it and need to live with the consequences. With 690249259Sdim * Schizo version >= 5, CDMA flushing/syncing is usable but requires 691249259Sdim * the workaround described in Schizo Errata I-23. With Tomatillo 692249259Sdim * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 693249259Sdim * version <= 4 (i.e. revision <= 2.3) bridges additionally require 694249259Sdim * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 695249259Sdim */ 696249259Sdim if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 697249259Sdim sc->sc_mode == SCHIZO_MODE_TOM || 698249259Sdim sc->sc_mode == SCHIZO_MODE_XMS) { 699249259Sdim if (sc->sc_mode == SCHIZO_MODE_SCZ) { 700249259Sdim sc->sc_dma_methods.dm_dmamap_sync = 701249259Sdim schizo_dmamap_sync; 702249259Sdim sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 703249259Sdim /* 704249259Sdim * Some firmware versions include the CDMA interrupt 705249259Sdim * at RID 4 but most don't. With the latter we add 706249259Sdim * it ourselves at the spare RID 5. 707249259Sdim */ 708249259Sdim i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 709249259Sdim 4)); 710249259Sdim if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 711249259Sdim sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 712249259Sdim (void)schizo_get_intrmap(sc, i, 713249259Sdim &sc->sc_cdma_map, &sc->sc_cdma_clr); 714249259Sdim schizo_set_intr(sc, 4, i, schizo_cdma); 715249259Sdim } else { 716249259Sdim i = STX_CDMA_A_INO + sc->sc_half; 717249259Sdim sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 718249259Sdim if (bus_set_resource(dev, SYS_RES_IRQ, 5, 719249259Sdim sc->sc_cdma_vec, 1) != 0) 720249259Sdim panic("%s: failed to add CDMA " 721249259Sdim "interrupt", __func__); 722249259Sdim j = schizo_intr_register(sc, i); 723249259Sdim if (j != 0) 724249259Sdim panic("%s: could not register " 725249259Sdim "interrupt controller for CDMA " 726249259Sdim "(%d)", __func__, j); 727249259Sdim (void)schizo_get_intrmap(sc, i, 728249259Sdim &sc->sc_cdma_map, &sc->sc_cdma_clr); 729249259Sdim schizo_set_intr(sc, 5, i, schizo_cdma); 730249259Sdim } 731249259Sdim } else { 732249259Sdim if (sc->sc_mode == SCHIZO_MODE_XMS) 733249259Sdim mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 734249259Sdim NULL, MTX_SPIN); 735249259Sdim sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 736249259Sdim sc->sc_half); 737249259Sdim sc->sc_dma_methods.dm_dmamap_sync = 738249259Sdim ichip_dmamap_sync; 739249259Sdim } 740249259Sdim if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 741249259Sdim sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 742249259Sdim } 743249259Sdim 744249259Sdim /* 745249259Sdim * Set the latency timer register as this isn't always done by the 746249259Sdim * firmware. 747249259Sdim */ 748249259Sdim PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 749249259Sdim PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 750249259Sdim 751249259Sdim ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 752249259Sdim 753249259Sdim#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 754249259Sdim SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 755249259Sdim SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 756249259Sdim (name), CTLFLAG_RD, (arg), 0, (desc)) 757249259Sdim 758249259Sdim SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 759249259Sdim "DMA correctable errors"); 760249259Sdim SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 761249259Sdim "PCI bus non-fatal errors"); 762249259Sdim 763249259Sdim#undef SCHIZO_SYSCTL_ADD_UINT 764249259Sdim 765249259Sdim device_add_child(dev, "pci", -1); 766249259Sdim return (bus_generic_attach(dev)); 767249259Sdim} 768249259Sdim 769249259Sdimstatic void 770249259Sdimschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 771249259Sdim driver_filter_t handler) 772249259Sdim{ 773249259Sdim u_long vec; 774249259Sdim int rid; 775249259Sdim 776249259Sdim rid = index; 777249259Sdim sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 778249259Sdim SYS_RES_IRQ, &rid, RF_ACTIVE); 779249259Sdim if (sc->sc_irq_res[index] == NULL || 780249259Sdim INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 781249259Sdim INTIGN(vec) != sc->sc_ign || 782249259Sdim intr_vectors[vec].iv_ic != &schizo_ic || 783249259Sdim bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 784249259Sdim INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 785249259Sdim &sc->sc_ihand[index]) != 0) 786249259Sdim panic("%s: failed to set up interrupt %d", __func__, index); 787249259Sdim} 788249259Sdim 789249259Sdimstatic int 790249259Sdimschizo_intr_register(struct schizo_softc *sc, u_int ino) 791249259Sdim{ 792249259Sdim struct schizo_icarg *sica; 793249259Sdim bus_addr_t intrclr, intrmap; 794249259Sdim int error; 795249259Sdim 796249259Sdim if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 797249259Sdim return (ENXIO); 798249259Sdim sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 799249259Sdim if (sica == NULL) 800249259Sdim return (ENOMEM); 801249259Sdim sica->sica_sc = sc; 802249259Sdim sica->sica_map = intrmap; 803249259Sdim sica->sica_clr = intrclr; 804249259Sdim#ifdef SCHIZO_DEBUG 805249259Sdim device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 806249259Sdim ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 807249259Sdim (u_long)intrclr); 808249259Sdim#endif 809249259Sdim error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 810249259Sdim &schizo_ic, sica)); 811249259Sdim if (error != 0) 812249259Sdim free(sica, M_DEVBUF); 813249259Sdim return (error); 814249259Sdim} 815249259Sdim 816249259Sdimstatic int 817249259Sdimschizo_get_intrmap(struct schizo_softc *sc, u_int ino, 818249259Sdim bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 819249259Sdim{ 820249259Sdim bus_addr_t intrclr, intrmap; 821249259Sdim uint64_t mr; 822249259Sdim 823249259Sdim /* 824249259Sdim * XXX we only look for INOs rather than INRs since the firmware 825249259Sdim * may not provide the IGN and the IGN is constant for all devices 826249259Sdim * on that PCI controller. 827249259Sdim */ 828249259Sdim 829249259Sdim if (ino > STX_MAX_INO) { 830249259Sdim device_printf(sc->sc_dev, "out of range INO %d requested\n", 831249259Sdim ino); 832249259Sdim return (0); 833249259Sdim } 834249259Sdim 835249259Sdim intrmap = STX_PCI_IMAP_BASE + (ino << 3); 836249259Sdim intrclr = STX_PCI_ICLR_BASE + (ino << 3); 837249259Sdim mr = SCHIZO_PCI_READ_8(sc, intrmap); 838249259Sdim if (INTINO(mr) != ino) { 839249259Sdim device_printf(sc->sc_dev, 840249259Sdim "interrupt map entry does not match INO (%d != %d)\n", 841249259Sdim (int)INTINO(mr), ino); 842249259Sdim return (0); 843249259Sdim } 844249259Sdim 845249259Sdim if (intrmapptr != NULL) 846249259Sdim *intrmapptr = intrmap; 847249259Sdim if (intrclrptr != NULL) 848249259Sdim *intrclrptr = intrclr; 849249259Sdim return (1); 850249259Sdim} 851249259Sdim 852249259Sdim/* 853249259Sdim * Interrupt handlers 854249259Sdim */ 855249259Sdimstatic int 856249259Sdimschizo_pci_bus(void *arg) 857249259Sdim{ 858249259Sdim struct schizo_softc *sc = arg; 859249259Sdim uint64_t afar, afsr, csr, iommu, xstat; 860249259Sdim uint32_t status; 861249259Sdim u_int fatal; 862249259Sdim 863249259Sdim fatal = 0; 864249259Sdim 865249259Sdim mtx_lock_spin(sc->sc_mtx); 866249259Sdim 867249259Sdim afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 868249259Sdim afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 869249259Sdim csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 870249259Sdim iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 871249259Sdim if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 872249259Sdim xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 873249259Sdim else 874249259Sdim xstat = 0; 875249259Sdim status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 876249259Sdim STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 877249259Sdim 878249259Sdim /* 879249259Sdim * IOMMU errors are only fatal on Tomatillo and there also only if 880249259Sdim * target abort was not signaled. 881249259Sdim */ 882249259Sdim if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 883249259Sdim (iommu & TOM_PCI_IOMMU_ERR) != 0 && 884249259Sdim ((status & PCIM_STATUS_STABORT) == 0 || 885249259Sdim ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 886249259Sdim (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 887249259Sdim (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 888249259Sdim fatal = 1; 889249259Sdim else if ((status & PCIM_STATUS_STABORT) != 0) 890249259Sdim fatal = 1; 891249259Sdim if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 892249259Sdim PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 893249259Sdim PCIM_STATUS_MDPERR)) != 0 || 894249259Sdim (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 895249259Sdim STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 896249259Sdim SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 897249259Sdim (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 898249259Sdim STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 899249259Sdim STX_PCI_AFSR_P_UNUS)) != 0) 900249259Sdim fatal = 1; 901249259Sdim if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 902249259Sdim XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 903249259Sdim XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 904249259Sdim XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 905249259Sdim fatal = 1; 906249259Sdim if (fatal == 0) 907249259Sdim sc->sc_stats_pci_non_fatal++; 908249259Sdim 909249259Sdim device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 910249259Sdim "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 911249259Sdim 'A' + sc->sc_half, (unsigned long long)afar, 912263508Sdim (unsigned long long)afsr, (unsigned long long)csr, 913263508Sdim (unsigned long long)iommu, (unsigned long long)xstat, status); 914263508Sdim 915263508Sdim /* Clear the error bits that we caught. */ 916263508Sdim PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 917263508Sdim STX_CS_FUNC, PCIR_STATUS, status, 2); 918263508Sdim SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 919263508Sdim SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 920263508Sdim SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 921263508Sdim if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 922263508Sdim SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 923263508Sdim 924249259Sdim mtx_unlock_spin(sc->sc_mtx); 925249259Sdim 926249259Sdim if (fatal != 0) 927249259Sdim panic("%s: fatal PCI bus error", 928249259Sdim device_get_nameunit(sc->sc_dev)); 929249259Sdim return (FILTER_HANDLED); 930249259Sdim} 931249259Sdim 932249259Sdimstatic int 933249259Sdimschizo_ue(void *arg) 934249259Sdim{ 935249259Sdim struct schizo_softc *sc = arg; 936249259Sdim uint64_t afar, afsr; 937249259Sdim int i; 938263508Sdim 939263508Sdim afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 940263508Sdim for (i = 0; i < 1000; i++) 941249259Sdim if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 942249259Sdim STX_CTRL_CE_AFSR_ERRPNDG) == 0) 943249259Sdim break; 944249259Sdim panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 945249259Sdim device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 946249259Sdim (unsigned long long)afsr); 947249259Sdim return (FILTER_HANDLED); 948249259Sdim} 949249259Sdim 950249259Sdimstatic int 951249259Sdimschizo_ce(void *arg) 952249259Sdim{ 953263508Sdim struct schizo_softc *sc = arg; 954263508Sdim uint64_t afar, afsr; 955263508Sdim int i; 956249259Sdim 957249259Sdim mtx_lock_spin(sc->sc_mtx); 958249259Sdim 959249259Sdim afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 960249259Sdim for (i = 0; i < 1000; i++) 961249259Sdim if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 962249259Sdim STX_CTRL_CE_AFSR_ERRPNDG) == 0) 963249259Sdim break; 964249259Sdim sc->sc_stats_dma_ce++; 965249259Sdim device_printf(sc->sc_dev, 966263508Sdim "correctable DMA error AFAR %#llx AFSR %#llx\n", 967263508Sdim (unsigned long long)afar, (unsigned long long)afsr); 968263508Sdim 969249259Sdim /* Clear the error bits that we caught. */ 970249259Sdim SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 971249259Sdim 972249259Sdim mtx_unlock_spin(sc->sc_mtx); 973249259Sdim 974249259Sdim return (FILTER_HANDLED); 975249259Sdim} 976249259Sdim 977249259Sdimstatic int 978249259Sdimschizo_host_bus(void *arg) 979249259Sdim{ 980249259Sdim struct schizo_softc *sc = arg; 981249259Sdim uint64_t errlog; 982249259Sdim 983249259Sdim errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 984249259Sdim panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 985249259Sdim sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 986249259Sdim (unsigned long long)errlog); 987249259Sdim return (FILTER_HANDLED); 988249259Sdim} 989249259Sdim 990249259Sdimstatic int 991249259Sdimschizo_cdma(void *arg) 992249259Sdim{ 993249259Sdim struct schizo_softc *sc = arg; 994249259Sdim 995249259Sdim atomic_cmpset_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_PENDING, 996249259Sdim SCHIZO_CDMA_STATE_RECEIVED); 997249259Sdim return (FILTER_HANDLED); 998249259Sdim} 999249259Sdim 1000249259Sdimstatic void 1001249259Sdimschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 1002249259Sdim{ 1003249259Sdim 1004249259Sdim /* Punch in our copies. */ 1005249259Sdim sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1006249259Sdim sc->sc_is.sis_is.is_bushandle = 1007249259Sdim rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 1008249259Sdim sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 1009249259Sdim sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 1010249259Sdim sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 1011249259Sdim sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 1012249259Sdim sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 1013249259Sdim sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 1014249259Sdim 1015249259Sdim iommu_init(device_get_nameunit(sc->sc_dev), 1016249259Sdim (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 1017249259Sdim} 1018249259Sdim 1019249259Sdimstatic int 1020249259Sdimschizo_maxslots(device_t dev) 1021249259Sdim{ 1022249259Sdim struct schizo_softc *sc; 1023249259Sdim 1024249259Sdim sc = device_get_softc(dev); 1025249259Sdim if (sc->sc_mode == SCHIZO_MODE_SCZ) 1026249259Sdim return (sc->sc_half == 0 ? 4 : 6); 1027249259Sdim 1028249259Sdim /* XXX: is this correct? */ 1029249259Sdim return (PCI_SLOTMAX); 1030249259Sdim} 1031249259Sdim 1032249259Sdimstatic uint32_t 1033249259Sdimschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 1034249259Sdim int width) 1035249259Sdim{ 1036249259Sdim struct schizo_softc *sc; 1037249259Sdim bus_space_handle_t bh; 1038249259Sdim u_long offset = 0; 1039249259Sdim uint32_t r, wrd; 1040249259Sdim int i; 1041249259Sdim uint16_t shrt; 1042249259Sdim uint8_t byte; 1043249259Sdim 1044249259Sdim sc = device_get_softc(dev); 1045249259Sdim if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1046249259Sdim slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1047249259Sdim return (-1); 1048249259Sdim 1049249259Sdim /* 1050249259Sdim * The Schizo bridges contain a dupe of their header at 0x80. 1051249259Sdim */ 1052249259Sdim if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1053249259Sdim slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1054249259Sdim reg + width > 0x80) 1055249259Sdim return (0); 1056249259Sdim 1057249259Sdim offset = STX_CONF_OFF(bus, slot, func, reg); 1058249259Sdim bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1059249259Sdim switch (width) { 1060249259Sdim case 1: 1061249259Sdim i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1062249259Sdim r = byte; 1063249259Sdim break; 1064249259Sdim case 2: 1065249259Sdim i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1066249259Sdim r = shrt; 1067249259Sdim break; 1068249259Sdim case 4: 1069249259Sdim i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1070249259Sdim r = wrd; 1071249259Sdim break; 1072249259Sdim default: 1073249259Sdim panic("%s: bad width", __func__); 1074249259Sdim /* NOTREACHED */ 1075249259Sdim } 1076249259Sdim 1077249259Sdim if (i) { 1078249259Sdim#ifdef SCHIZO_DEBUG 1079249259Sdim printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1080249259Sdim __func__, bus, slot, func, reg); 1081249259Sdim#endif 1082249259Sdim r = -1; 1083249259Sdim } 1084249259Sdim return (r); 1085249259Sdim} 1086249259Sdim 1087249259Sdimstatic void 1088249259Sdimschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1089249259Sdim u_int reg, uint32_t val, int width) 1090249259Sdim{ 1091249259Sdim struct schizo_softc *sc; 1092249259Sdim bus_space_handle_t bh; 1093249259Sdim u_long offset = 0; 1094249259Sdim 1095249259Sdim sc = device_get_softc(dev); 1096249259Sdim if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1097249259Sdim slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1098249259Sdim return; 1099249259Sdim 1100249259Sdim offset = STX_CONF_OFF(bus, slot, func, reg); 1101249259Sdim bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1102249259Sdim switch (width) { 1103249259Sdim case 1: 1104249259Sdim bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1105249259Sdim break; 1106249259Sdim case 2: 1107249259Sdim bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1108249259Sdim break; 1109249259Sdim case 4: 1110249259Sdim bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1111249259Sdim break; 1112249259Sdim default: 1113249259Sdim panic("%s: bad width", __func__); 1114249259Sdim /* NOTREACHED */ 1115249259Sdim } 1116249259Sdim} 1117249259Sdim 1118249259Sdimstatic int 1119249259Sdimschizo_route_interrupt(device_t bridge, device_t dev, int pin) 1120249259Sdim{ 1121249259Sdim struct schizo_softc *sc; 1122249259Sdim struct ofw_pci_register reg; 1123249259Sdim ofw_pci_intr_t pintr, mintr; 1124249259Sdim uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1125249259Sdim 1126249259Sdim sc = device_get_softc(bridge); 1127249259Sdim pintr = pin; 1128249259Sdim if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1129249259Sdim ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1130249259Sdim NULL, maskbuf)) 1131249259Sdim return (mintr); 1132249259Sdim 1133249259Sdim device_printf(bridge, "could not route pin %d for device %d.%d\n", 1134249259Sdim pin, pci_get_slot(dev), pci_get_function(dev)); 1135249259Sdim return (PCI_INVALID_IRQ); 1136249259Sdim} 1137249259Sdim 1138249259Sdimstatic int 1139249259Sdimschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1140249259Sdim{ 1141249259Sdim struct schizo_softc *sc; 1142249259Sdim 1143249259Sdim sc = device_get_softc(dev); 1144249259Sdim switch (which) { 1145249259Sdim case PCIB_IVAR_DOMAIN: 1146249259Sdim *result = device_get_unit(dev); 1147249259Sdim return (0); 1148249259Sdim case PCIB_IVAR_BUS: 1149249259Sdim *result = sc->sc_pci_secbus; 1150249259Sdim return (0); 1151249259Sdim } 1152249259Sdim return (ENOENT); 1153249259Sdim} 1154249259Sdim 1155249259Sdimstatic void 1156249259Sdimschizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1157249259Sdim{ 1158249259Sdim struct timeval cur, end; 1159249259Sdim struct schizo_iommu_state *sis = dt->dt_cookie; 1160249259Sdim struct schizo_softc *sc = sis->sis_sc; 1161249259Sdim int i, res; 1162249259Sdim#ifdef INVARIANTS 1163249259Sdim register_t pil; 1164249259Sdim#endif 1165249259Sdim 1166249259Sdim if ((map->dm_flags & DMF_STREAMED) != 0) { 1167249259Sdim iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1168249259Sdim return; 1169249259Sdim } 1170249259Sdim 1171249259Sdim if ((map->dm_flags & DMF_LOADED) == 0) 1172249259Sdim return; 1173249259Sdim 1174249259Sdim if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1175249259Sdim /* 1176249259Sdim * Note that in order to allow this function to be called from 1177249259Sdim * filters we would need to use a spin mutex for serialization 1178249259Sdim * but given that these disable interrupts we have to emulate 1179249259Sdim * one. 1180249259Sdim */ 1181249259Sdim critical_enter(); 1182249259Sdim KASSERT((rdpr(pstate) & PSTATE_IE) != 0, 1183249259Sdim ("%s: interrupts disabled", __func__)); 1184249259Sdim KASSERT((pil = rdpr(pil)) <= PIL_BRIDGE, 1185249259Sdim ("%s: PIL too low (%ld)", __func__, pil)); 1186249259Sdim for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1187249259Sdim SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1188249259Sdim ; 1189249259Sdim SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_map, 1190249259Sdim INTMAP_ENABLE(sc->sc_cdma_vec, PCPU_GET(mid))); 1191249259Sdim for (i = 0; i < SCHIZO_CDMA_TRIES; i++) { 1192249259Sdim if (i > 0) 1193249259Sdim printf("%s: try %d\n", __func__, i); 1194249259Sdim SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1195249259Sdim INTCLR_RECEIVED); 1196249259Sdim microuptime(&cur); 1197249259Sdim end.tv_sec = SCHIZO_CDMA_TIMEOUT; 1198249259Sdim end.tv_usec = 0; 1199249259Sdim timevaladd(&end, &cur); 1200249259Sdim for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1201249259Sdim SCHIZO_CDMA_STATE_RECEIVED, 1202249259Sdim SCHIZO_CDMA_STATE_IDLE)) == 0 && 1203249259Sdim timevalcmp(&cur, &end, <=);) 1204249259Sdim microuptime(&cur); 1205249259Sdim if (res != 0) 1206249259Sdim break; 1207249259Sdim } 1208249259Sdim if (res == 0) 1209249259Sdim panic("%s: DMA does not sync", __func__); 1210249259Sdim critical_exit(); 1211249259Sdim } 1212249259Sdim 1213249259Sdim if ((op & BUS_DMASYNC_PREWRITE) != 0) 1214249259Sdim membar(Sync); 1215249259Sdim} 1216249259Sdim 1217249259Sdim#define VIS_BLOCKSIZE 64 1218249259Sdim 1219249259Sdimstatic void 1220249259Sdimichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1221249259Sdim{ 1222249259Sdim static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1223249259Sdim struct timeval cur, end; 1224249259Sdim struct schizo_iommu_state *sis = dt->dt_cookie; 1225249259Sdim struct schizo_softc *sc = sis->sis_sc; 1226249259Sdim register_t reg, s; 1227249259Sdim 1228249259Sdim if ((map->dm_flags & DMF_STREAMED) != 0) { 1229249259Sdim iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1230249259Sdim return; 1231249259Sdim } 1232249259Sdim 1233249259Sdim if ((map->dm_flags & DMF_LOADED) == 0) 1234249259Sdim return; 1235249259Sdim 1236249259Sdim if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1237249259Sdim if (sc->sc_mode == SCHIZO_MODE_XMS) 1238249259Sdim mtx_lock_spin(&sc->sc_sync_mtx); 1239249259Sdim SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1240249259Sdim sc->sc_sync_val); 1241249259Sdim microuptime(&cur); 1242249259Sdim end.tv_sec = 1; 1243249259Sdim end.tv_usec = 0; 1244249259Sdim timevaladd(&end, &cur); 1245249259Sdim for (; ((reg = SCHIZO_PCI_READ_8(sc, 1246249259Sdim TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1247249259Sdim timevalcmp(&cur, &end, <=);) 1248249259Sdim microuptime(&cur); 1249249259Sdim if ((reg & sc->sc_sync_val) != 0) 1250249259Sdim panic("%s: DMA does not sync", __func__); 1251249259Sdim if (sc->sc_mode == SCHIZO_MODE_XMS) 1252249259Sdim mtx_unlock_spin(&sc->sc_sync_mtx); 1253249259Sdim else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1254249259Sdim s = intr_disable(); 1255249259Sdim reg = rd(fprs); 1256249259Sdim wr(fprs, reg | FPRS_FEF, 0); 1257249259Sdim __asm __volatile("stda %%f0, [%0] %1" 1258249259Sdim : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1259249259Sdim membar(Sync); 1260249259Sdim wr(fprs, reg, 0); 1261249259Sdim intr_restore(s); 1262249259Sdim return; 1263249259Sdim } 1264249259Sdim } 1265249259Sdim 1266249259Sdim if ((op & BUS_DMASYNC_PREWRITE) != 0) 1267249259Sdim membar(Sync); 1268249259Sdim} 1269249259Sdim 1270249259Sdimstatic void 1271249259Sdimschizo_intr_enable(void *arg) 1272249259Sdim{ 1273263508Sdim struct intr_vector *iv = arg; 1274263508Sdim struct schizo_icarg *sica = iv->iv_icarg; 1275263508Sdim 1276263508Sdim SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1277263508Sdim INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1278249259Sdim} 1279249259Sdim 1280249259Sdimstatic void 1281249259Sdimschizo_intr_disable(void *arg) 1282249259Sdim{ 1283249259Sdim struct intr_vector *iv = arg; 1284249259Sdim struct schizo_icarg *sica = iv->iv_icarg; 1285249259Sdim 1286249259Sdim SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1287263508Sdim} 1288263508Sdim 1289263508Sdimstatic void 1290263508Sdimschizo_intr_assign(void *arg) 1291263508Sdim{ 1292263508Sdim struct intr_vector *iv = arg; 1293263508Sdim struct schizo_icarg *sica = iv->iv_icarg; 1294249259Sdim 1295249259Sdim SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1296249259Sdim SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1297249259Sdim} 1298249259Sdim 1299249259Sdimstatic void 1300249259Sdimschizo_intr_clear(void *arg) 1301249259Sdim{ 1302249259Sdim struct intr_vector *iv = arg; 1303249259Sdim struct schizo_icarg *sica = iv->iv_icarg; 1304249259Sdim 1305249259Sdim SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1306249259Sdim} 1307249259Sdim 1308249259Sdimstatic int 1309249259Sdimschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1310249259Sdim int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1311249259Sdim void **cookiep) 1312249259Sdim{ 1313249259Sdim struct schizo_softc *sc; 1314249259Sdim u_long vec; 1315249259Sdim int error; 1316249259Sdim 1317249259Sdim sc = device_get_softc(dev); 1318249259Sdim /* 1319249259Sdim * Make sure the vector is fully specified. 1320249259Sdim */ 1321249259Sdim vec = rman_get_start(ires); 1322249259Sdim if (INTIGN(vec) != sc->sc_ign) { 1323249259Sdim device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1324249259Sdim return (EINVAL); 1325249259Sdim } 1326249259Sdim 1327249259Sdim if (intr_vectors[vec].iv_ic == &schizo_ic) { 1328249259Sdim /* 1329249259Sdim * Ensure we use the right softc in case the interrupt 1330249259Sdim * is routed to our companion PBM for some odd reason. 1331249259Sdim */ 1332249259Sdim sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1333249259Sdim sica_sc; 1334249259Sdim } else if (intr_vectors[vec].iv_ic == NULL) { 1335249259Sdim /* 1336249259Sdim * Work around broken firmware which misses entries in 1337249259Sdim * the ino-bitmap. 1338249259Sdim */ 1339249259Sdim error = schizo_intr_register(sc, INTINO(vec)); 1340249259Sdim if (error != 0) { 1341249259Sdim device_printf(dev, "could not register interrupt " 1342249259Sdim "controller for vector 0x%lx (%d)\n", vec, error); 1343249259Sdim return (error); 1344249259Sdim } 1345249259Sdim if (bootverbose) 1346249259Sdim device_printf(dev, "belatedly registered as " 1347249259Sdim "interrupt controller for vector 0x%lx\n", vec); 1348249259Sdim } else { 1349249259Sdim device_printf(dev, 1350249259Sdim "invalid interrupt controller for vector 0x%lx\n", vec); 1351249259Sdim return (EINVAL); 1352249259Sdim } 1353249259Sdim return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1354249259Sdim arg, cookiep)); 1355249259Sdim} 1356249259Sdim 1357249259Sdimstatic struct resource * 1358249259Sdimschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1359249259Sdim u_long start, u_long end, u_long count, u_int flags) 1360249259Sdim{ 1361249259Sdim struct schizo_softc *sc; 1362249259Sdim struct resource *rv; 1363249259Sdim struct rman *rm; 1364249259Sdim 1365249259Sdim sc = device_get_softc(bus); 1366249259Sdim switch (type) { 1367249259Sdim case SYS_RES_IRQ: 1368249259Sdim /* 1369249259Sdim * XXX: Don't accept blank ranges for now, only single 1370249259Sdim * interrupts. The other case should not happen with 1371249259Sdim * the MI PCI code... 1372249259Sdim * XXX: This may return a resource that is out of the 1373249259Sdim * range that was specified. Is this correct...? 1374249259Sdim */ 1375249259Sdim if (start != end) 1376249259Sdim panic("%s: XXX: interrupt range", __func__); 1377249259Sdim start = end = INTMAP_VEC(sc->sc_ign, end); 1378249259Sdim return (bus_generic_alloc_resource(bus, child, type, rid, 1379249259Sdim start, end, count, flags)); 1380249259Sdim case SYS_RES_MEMORY: 1381249259Sdim rm = &sc->sc_pci_mem_rman; 1382249259Sdim break; 1383249259Sdim case SYS_RES_IOPORT: 1384263508Sdim rm = &sc->sc_pci_io_rman; 1385263508Sdim break; 1386263508Sdim default: 1387249259Sdim return (NULL); 1388249259Sdim } 1389249259Sdim 1390249259Sdim rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 1391249259Sdim child); 1392249259Sdim if (rv == NULL) 1393249259Sdim return (NULL); 1394249259Sdim rman_set_rid(rv, *rid); 1395249259Sdim 1396249259Sdim if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type, 1397249259Sdim *rid, rv) != 0) { 1398249259Sdim rman_release_resource(rv); 1399249259Sdim return (NULL); 1400249259Sdim } 1401249259Sdim return (rv); 1402249259Sdim} 1403249259Sdim 1404249259Sdimstatic int 1405249259Sdimschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1406249259Sdim struct resource *r) 1407249259Sdim{ 1408249259Sdim struct schizo_softc *sc; 1409249259Sdim struct bus_space_tag *tag; 1410249259Sdim 1411249259Sdim sc = device_get_softc(bus); 1412249259Sdim switch (type) { 1413249259Sdim case SYS_RES_IRQ: 1414249259Sdim return (bus_generic_activate_resource(bus, child, type, rid, 1415249259Sdim r)); 1416249259Sdim case SYS_RES_MEMORY: 1417249259Sdim tag = sparc64_alloc_bus_tag(r, rman_get_bustag( 1418249259Sdim sc->sc_mem_res[STX_PCI]), PCI_MEMORY_BUS_SPACE, NULL); 1419249259Sdim if (tag == NULL) 1420249259Sdim return (ENOMEM); 1421249259Sdim rman_set_bustag(r, tag); 1422249259Sdim rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] + 1423249259Sdim rman_get_start(r)); 1424249259Sdim break; 1425249259Sdim case SYS_RES_IOPORT: 1426249259Sdim rman_set_bustag(r, sc->sc_pci_iot); 1427249259Sdim rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] + 1428249259Sdim rman_get_start(r)); 1429249259Sdim break; 1430249259Sdim } 1431249259Sdim return (rman_activate_resource(r)); 1432249259Sdim} 1433249259Sdim 1434249259Sdimstatic int 1435249259Sdimschizo_adjust_resource(device_t bus, device_t child, int type, 1436249259Sdim struct resource *r, u_long start, u_long end) 1437249259Sdim{ 1438249259Sdim struct schizo_softc *sc; 1439249259Sdim struct rman *rm; 1440249259Sdim 1441249259Sdim sc = device_get_softc(bus); 1442249259Sdim switch (type) { 1443249259Sdim case SYS_RES_IRQ: 1444249259Sdim return (bus_generic_adjust_resource(bus, child, type, r, 1445249259Sdim start, end)); 1446249259Sdim case SYS_RES_MEMORY: 1447249259Sdim rm = &sc->sc_pci_mem_rman; 1448249259Sdim break; 1449249259Sdim case SYS_RES_IOPORT: 1450249259Sdim rm = &sc->sc_pci_io_rman; 1451249259Sdim break; 1452249259Sdim default: 1453249259Sdim return (EINVAL); 1454249259Sdim } 1455249259Sdim if (rman_is_region_manager(r, rm) == 0) 1456249259Sdim return (EINVAL); 1457249259Sdim return (rman_adjust_resource(r, start, end)); 1458249259Sdim} 1459249259Sdim 1460249259Sdimstatic bus_dma_tag_t 1461249259Sdimschizo_get_dma_tag(device_t bus, device_t child __unused) 1462249259Sdim{ 1463249259Sdim struct schizo_softc *sc; 1464249259Sdim 1465249259Sdim sc = device_get_softc(bus); 1466249259Sdim return (sc->sc_pci_dmat); 1467249259Sdim} 1468249259Sdim 1469249259Sdimstatic phandle_t 1470249259Sdimschizo_get_node(device_t bus, device_t child __unused) 1471249259Sdim{ 1472249259Sdim struct schizo_softc *sc; 1473249259Sdim 1474249259Sdim sc = device_get_softc(bus); 1475249259Sdim /* We only have one child, the PCI bus, which needs our own node. */ 1476249259Sdim return (sc->sc_node); 1477249259Sdim} 1478249259Sdim 1479249259Sdimstatic void 1480249259Sdimschizo_setup_device(device_t bus, device_t child) 1481249259Sdim{ 1482249259Sdim struct schizo_softc *sc; 1483249259Sdim uint64_t reg; 1484249259Sdim int capreg; 1485249259Sdim 1486249259Sdim sc = device_get_softc(bus); 1487249259Sdim /* 1488249259Sdim * Disable bus parking in order to work around a bus hang caused by 1489249259Sdim * Casinni/Skyhawk combinations. 1490249259Sdim */ 1491249259Sdim if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1492249259Sdim SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1493249259Sdim STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1494249259Sdim 1495249259Sdim if (sc->sc_mode == SCHIZO_MODE_XMS) { 1496249259Sdim /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1497249259Sdim if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1498249259Sdim (pci_read_config(child, PCIR_HDRTYPE, 1) & 1499249259Sdim PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1500249259Sdim pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1501249259Sdim pci_write_config(child, capreg + PCIXR_COMMAND, 1502249259Sdim pci_read_config(child, capreg + PCIXR_COMMAND, 1503249259Sdim 2) & 0x7c, 2); 1504249259Sdim /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1505249259Sdim if (sc->sc_mrev >= 4) { 1506249259Sdim reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1507249259Sdim 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1508249259Sdim if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1509249259Sdim XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1510249259Sdim SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1511249259Sdim } 1512249259Sdim } 1513249259Sdim} 1514249259Sdim 1515249259Sdimstatic u_int 1516249259Sdimschizo_get_timecount(struct timecounter *tc) 1517249259Sdim{ 1518249259Sdim struct schizo_softc *sc; 1519249259Sdim 1520249259Sdim sc = tc->tc_priv; 1521249259Sdim return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1522249259Sdim (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >> 1523249259Sdim STX_CTRL_PERF_CNT_CNT0_SHIFT); 1524249259Sdim} 1525249259Sdim