schizo.c revision 225931
1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4220038Smarius * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 225931 2011-10-02 23:22:38Z marius $"); 36183423Smarius 37183423Smarius/* 38220038Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 39220038Smarius * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55208097Smarius#include <sys/sysctl.h> 56185133Smarius#include <sys/time.h> 57183423Smarius#include <sys/timetc.h> 58183423Smarius 59183423Smarius#include <dev/ofw/ofw_bus.h> 60183423Smarius#include <dev/ofw/ofw_pci.h> 61183423Smarius#include <dev/ofw/openfirm.h> 62183423Smarius 63183423Smarius#include <machine/bus.h> 64183423Smarius#include <machine/bus_common.h> 65183423Smarius#include <machine/bus_private.h> 66183423Smarius#include <machine/fsr.h> 67183423Smarius#include <machine/iommureg.h> 68183423Smarius#include <machine/iommuvar.h> 69183423Smarius#include <machine/resource.h> 70183423Smarius 71183423Smarius#include <dev/pci/pcireg.h> 72183423Smarius#include <dev/pci/pcivar.h> 73183423Smarius 74183423Smarius#include <sparc64/pci/ofw_pci.h> 75183423Smarius#include <sparc64/pci/schizoreg.h> 76183423Smarius#include <sparc64/pci/schizovar.h> 77183423Smarius 78183423Smarius#include "pcib_if.h" 79183423Smarius 80183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 81183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82183423Smarius driver_filter_t); 83220038Smariusstatic void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 84220038Smarius bus_dmasync_op_t op); 85220038Smariusstatic void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 86220038Smarius bus_dmasync_op_t op); 87183423Smariusstatic void schizo_intr_enable(void *); 88183423Smariusstatic void schizo_intr_disable(void *); 89183423Smariusstatic void schizo_intr_assign(void *); 90183423Smariusstatic void schizo_intr_clear(void *); 91185133Smariusstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 92183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 93183423Smarius bus_addr_t *, bus_addr_t *); 94183423Smariusstatic timecounter_get_t schizo_get_timecount; 95183423Smarius 96183423Smarius/* Interrupt handlers */ 97183423Smariusstatic driver_filter_t schizo_pci_bus; 98183423Smariusstatic driver_filter_t schizo_ue; 99183423Smariusstatic driver_filter_t schizo_ce; 100183423Smariusstatic driver_filter_t schizo_host_bus; 101185133Smariusstatic driver_filter_t schizo_cdma; 102183423Smarius 103183423Smarius/* IOMMU support */ 104183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 105183423Smarius 106183423Smarius/* 107183423Smarius * Methods 108183423Smarius */ 109183423Smariusstatic device_probe_t schizo_probe; 110183423Smariusstatic device_attach_t schizo_attach; 111183423Smariusstatic bus_read_ivar_t schizo_read_ivar; 112183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 113183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 114183423Smariusstatic bus_activate_resource_t schizo_activate_resource; 115225931Smariusstatic bus_adjust_resource_t schizo_adjust_resource; 116183423Smariusstatic bus_get_dma_tag_t schizo_get_dma_tag; 117183423Smariusstatic pcib_maxslots_t schizo_maxslots; 118183423Smariusstatic pcib_read_config_t schizo_read_config; 119183423Smariusstatic pcib_write_config_t schizo_write_config; 120183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 121183423Smariusstatic ofw_bus_get_node_t schizo_get_node; 122220038Smariusstatic ofw_pci_setup_device_t schizo_setup_device; 123183423Smarius 124183423Smariusstatic device_method_t schizo_methods[] = { 125183423Smarius /* Device interface */ 126183423Smarius DEVMETHOD(device_probe, schizo_probe), 127183423Smarius DEVMETHOD(device_attach, schizo_attach), 128183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 129183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 130183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 131183423Smarius 132183423Smarius /* Bus interface */ 133183423Smarius DEVMETHOD(bus_print_child, bus_generic_print_child), 134183423Smarius DEVMETHOD(bus_read_ivar, schizo_read_ivar), 135183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 136220038Smarius DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 137183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 138225931Smarius DEVMETHOD(bus_activate_resource, schizo_activate_resource), 139225931Smarius DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 140225931Smarius DEVMETHOD(bus_adjust_resource, schizo_adjust_resource), 141225931Smarius DEVMETHOD(bus_release_resource, bus_generic_release_resource), 142183423Smarius DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 143183423Smarius 144183423Smarius /* pcib interface */ 145183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 146183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 147183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 148183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 149183423Smarius 150183423Smarius /* ofw_bus interface */ 151183423Smarius DEVMETHOD(ofw_bus_get_node, schizo_get_node), 152183423Smarius 153225931Smarius /* ofw_pci interface */ 154220038Smarius DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 155220038Smarius 156190108Smarius KOBJMETHOD_END 157183423Smarius}; 158183423Smarius 159183423Smariusstatic devclass_t schizo_devclass; 160183423Smarius 161183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 162183423Smarius sizeof(struct schizo_softc)); 163215349SmariusEARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 164215349Smarius BUS_PASS_BUS); 165183423Smarius 166183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 167183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 168183423Smarius 169183423Smariusstatic const struct intr_controller schizo_ic = { 170183423Smarius schizo_intr_enable, 171183423Smarius schizo_intr_disable, 172183423Smarius schizo_intr_assign, 173183423Smarius schizo_intr_clear 174183423Smarius}; 175183423Smarius 176183423Smariusstruct schizo_icarg { 177183423Smarius struct schizo_softc *sica_sc; 178183423Smarius bus_addr_t sica_map; 179183423Smarius bus_addr_t sica_clr; 180183423Smarius}; 181183423Smarius 182183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 183183423Smarius 184220038Smarius#define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 185220038Smarius bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 186206018Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 187183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 188206018Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 189183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 190183423Smarius 191220038Smarius#ifndef SCHIZO_DEBUG 192220038Smarius#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 193220038Smarius SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 194220038Smarius#else 195220038Smarius#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 196220038Smarius device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 197220038Smarius (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 198220038Smarius (unsigned long long)(v)); \ 199220038Smarius SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 200220038Smarius } while (0) 201220038Smarius#endif 202220038Smarius 203206018Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 204183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 205206018Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 206183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 207206018Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 208183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 209206018Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 210183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 211206018Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 212183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 213206018Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 214183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 215206018Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 216183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 217206018Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 218183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 219183423Smarius 220220038Smarius#define SCHIZO_PCI_SET(sc, offs, v) \ 221220038Smarius SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 222220038Smarius#define SCHIZO_CTRL_SET(sc, offs, v) \ 223220038Smarius SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 224220038Smarius 225183423Smariusstruct schizo_desc { 226183423Smarius const char *sd_string; 227183423Smarius int sd_mode; 228183423Smarius const char *sd_name; 229183423Smarius}; 230183423Smarius 231185133Smariusstatic const struct schizo_desc const schizo_compats[] = { 232183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 233220038Smarius#if 0 234220038Smarius { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 235220038Smarius#endif 236183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 237183423Smarius { NULL, 0, NULL } 238183423Smarius}; 239183423Smarius 240183423Smariusstatic const struct schizo_desc * 241183423Smariusschizo_get_desc(device_t dev) 242183423Smarius{ 243183423Smarius const struct schizo_desc *desc; 244183423Smarius const char *compat; 245183423Smarius 246183423Smarius compat = ofw_bus_get_compat(dev); 247183423Smarius if (compat == NULL) 248183423Smarius return (NULL); 249183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 250183423Smarius if (strcmp(desc->sd_string, compat) == 0) 251183423Smarius return (desc); 252183423Smarius return (NULL); 253183423Smarius} 254183423Smarius 255183423Smariusstatic int 256183423Smariusschizo_probe(device_t dev) 257183423Smarius{ 258183423Smarius const char *dtype; 259183423Smarius 260183423Smarius dtype = ofw_bus_get_type(dev); 261197164Smarius if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 262183423Smarius schizo_get_desc(dev) != NULL) { 263183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 264183423Smarius return (0); 265183423Smarius } 266183423Smarius return (ENXIO); 267183423Smarius} 268183423Smarius 269183423Smariusstatic int 270183423Smariusschizo_attach(device_t dev) 271183423Smarius{ 272183423Smarius struct ofw_pci_ranges *range; 273183423Smarius const struct schizo_desc *desc; 274183423Smarius struct schizo_softc *asc, *sc, *osc; 275183423Smarius struct timecounter *tc; 276183423Smarius uint64_t ino_bitmap, reg; 277183423Smarius phandle_t node; 278183423Smarius uint32_t prop, prop_array[2]; 279201199Smarius int i, j, mode, rid, tsbsize; 280183423Smarius 281183423Smarius sc = device_get_softc(dev); 282183423Smarius node = ofw_bus_get_node(dev); 283183423Smarius desc = schizo_get_desc(dev); 284183423Smarius mode = desc->sd_mode; 285183423Smarius 286183423Smarius sc->sc_dev = dev; 287183423Smarius sc->sc_node = node; 288183423Smarius sc->sc_mode = mode; 289185133Smarius sc->sc_flags = 0; 290183423Smarius 291183423Smarius /* 292183423Smarius * The Schizo has three register banks: 293183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 294183423Smarius * shared with the UPA64s interrupt mapping register banks 295183423Smarius * (1) shared Schizo controller configuration and status registers 296183423Smarius * (2) per-PBM PCI configuration space 297183423Smarius * 298183423Smarius * The Tomatillo has four register banks: 299183423Smarius * (0) per-PBM PCI configuration and status registers 300183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 301183423Smarius * machines having the `jbusppm' device shared with its Estar 302183423Smarius * register bank for bus A 303183423Smarius * (2) per-PBM PCI configuration space 304183423Smarius * (3) per-PBM interrupt concentrator registers 305183423Smarius */ 306183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 307183423Smarius 20) & 1; 308201199Smarius for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 309201199Smarius i++) { 310201199Smarius rid = i; 311201199Smarius sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 312183423Smarius SYS_RES_MEMORY, &rid, 313183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 314201199Smarius i == STX_PCI) || i == STX_CTRL)) || 315183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 316201199Smarius i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 317201199Smarius if (sc->sc_mem_res[i] == NULL) 318183423Smarius panic("%s: could not allocate register bank %d", 319201199Smarius __func__, i); 320183423Smarius } 321183423Smarius 322183423Smarius /* 323183423Smarius * Match other Schizos that are already configured against 324183423Smarius * the controller base physical address. This will be the 325183423Smarius * same for a pair of devices that share register space. 326183423Smarius */ 327183423Smarius osc = NULL; 328183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 329183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 330183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 331183423Smarius /* Found partner. */ 332183423Smarius osc = asc; 333183423Smarius break; 334183423Smarius } 335183423Smarius } 336183423Smarius if (osc == NULL) { 337183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 338183423Smarius M_NOWAIT | M_ZERO); 339183423Smarius if (sc->sc_mtx == NULL) 340183423Smarius panic("%s: could not malloc mutex", __func__); 341183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 342183423Smarius } else { 343185133Smarius if (sc->sc_mode != SCHIZO_MODE_SCZ) 344185133Smarius panic("%s: no partner expected", __func__); 345183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 346183423Smarius panic("%s: mutex not initialized", __func__); 347183423Smarius sc->sc_mtx = osc->sc_mtx; 348183423Smarius } 349183423Smarius 350183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 351183423Smarius panic("%s: could not determine IGN", __func__); 352201199Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 353201199Smarius -1) 354183423Smarius panic("%s: could not determine version", __func__); 355220038Smarius if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 356220038Smarius &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 357220038Smarius panic("%s: could not determine module-revision", __func__); 358183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 359183423Smarius prop = 33000000; 360183423Smarius 361220038Smarius if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 362220038Smarius XMS_PCI_CTRL_X_MODE) != 0) { 363220038Smarius if (sc->sc_mrev < 1) 364220038Smarius panic("PCI-X mode unsupported"); 365220038Smarius sc->sc_flags |= SCHIZO_FLAGS_XMODE; 366220038Smarius } 367183423Smarius 368220038Smarius device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 369220038Smarius if (mode == SCHIZO_MODE_XMS) 370220038Smarius printf("module-revision %d, ", sc->sc_mrev); 371220038Smarius printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 372220038Smarius 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 373220038Smarius "-X" : "", prop / 1000 / 1000); 374220038Smarius 375183423Smarius /* Set up the PCI interrupt retry timer. */ 376220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 377183423Smarius 378183423Smarius /* Set up the PCI control register. */ 379183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 380220038Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 381220038Smarius STX_PCI_CTRL_ARB_MASK); 382183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 383220038Smarius STX_PCI_CTRL_ERR_IEN; 384183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 385183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 386220038Smarius if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 387220038Smarius reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 388220038Smarius else 389220038Smarius reg |= STX_PCI_CTRL_ARB_MASK; 390183423Smarius if (mode == SCHIZO_MODE_TOM) { 391183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 392183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 393183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 394183423Smarius else 395183423Smarius reg |= STX_PCI_CTRL_PTO; 396220038Smarius } else if (mode == SCHIZO_MODE_XMS) { 397220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 398220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 399220038Smarius reg |= XMS_PCI_CTRL_X_ERRINT_EN; 400183423Smarius } 401220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 402183423Smarius 403183423Smarius /* Set up the PCI diagnostic register. */ 404183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 405183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 406183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 407220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 408183423Smarius 409183423Smarius /* 410208097Smarius * Enable DMA write parity error interrupts of version >= 7 (i.e. 411220038Smarius * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 412220038Smarius * no effect though). 413208097Smarius */ 414220038Smarius if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 415220038Smarius mode == SCHIZO_MODE_XMS) { 416208097Smarius reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 417208097Smarius reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 418220038Smarius SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 419208097Smarius } 420208097Smarius 421208097Smarius /* 422183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 423183423Smarius * Jalapeno bug). 424183423Smarius */ 425183423Smarius if (mode == SCHIZO_MODE_TOM) 426220038Smarius SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 427183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 428183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 429183423Smarius 430183423Smarius /* 431183423Smarius * Hunt through all the interrupt mapping regs and register 432186290Smarius * the interrupt controller for our interrupt vectors. We do 433186290Smarius * this early in order to be able to catch stray interrupts. 434186290Smarius * This is complicated by the fact that a pair of Schizo PBMs 435186290Smarius * shares one IGN. 436183423Smarius */ 437201199Smarius i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 438183423Smarius sizeof(prop_array)); 439205254Smarius if (i != -1) 440205254Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 441205254Smarius else { 442205254Smarius /* 443205254Smarius * If the ino-bitmap property is missing, just provide the 444205254Smarius * default set of interrupts for this controller and let 445205254Smarius * schizo_setup_intr() take care of child interrupts. 446205254Smarius */ 447205254Smarius if (sc->sc_half == 0) 448205254Smarius ino_bitmap = (1ULL << STX_UE_INO) | 449205254Smarius (1ULL << STX_CE_INO) | 450205254Smarius (1ULL << STX_PCIERR_A_INO) | 451205254Smarius (1ULL << STX_BUS_INO); 452205254Smarius else 453205254Smarius ino_bitmap = 1ULL << STX_PCIERR_B_INO; 454205254Smarius } 455201199Smarius for (i = 0; i <= STX_MAX_INO; i++) { 456201199Smarius if ((ino_bitmap & (1ULL << i)) == 0) 457183423Smarius continue; 458201199Smarius if (i == STX_FB0_INO || i == STX_FB1_INO) 459183423Smarius /* Leave for upa(4). */ 460183423Smarius continue; 461201199Smarius j = schizo_intr_register(sc, i); 462201199Smarius if (j != 0) 463186290Smarius device_printf(dev, "could not register interrupt " 464201199Smarius "controller for INO %d (%d)\n", i, j); 465183423Smarius } 466183423Smarius 467183423Smarius /* 468183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 469183423Smarius * mode as timecounter. Unfortunately, this is broken with at 470183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 471183423Smarius * 1500, which apparently actually count some different event at 472183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 473183423Smarius * power mode). Besides, one counter seems to be shared by a 474183423Smarius * "pair" of Tomatillos, too. 475183423Smarius */ 476183423Smarius if (sc->sc_half == 0) { 477220038Smarius SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 478183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 479183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 480183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 481183423Smarius if (tc == NULL) 482183423Smarius panic("%s: could not malloc timecounter", __func__); 483183423Smarius tc->tc_get_timecount = schizo_get_timecount; 484183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 485183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 486183423Smarius sizeof(prop)) == -1) 487183423Smarius panic("%s: could not determine clock frequency", 488183423Smarius __func__); 489183423Smarius tc->tc_frequency = prop; 490183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 491183423Smarius if (mode == SCHIZO_MODE_SCZ) 492183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 493183423Smarius else 494183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 495183423Smarius tc->tc_priv = sc; 496183423Smarius tc_init(tc); 497183423Smarius } 498183423Smarius 499190108Smarius /* 500190108Smarius * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 501190108Smarius * one per PBM. Schizo and XMITS additionally have a streaming 502190108Smarius * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 503225891Smarius * affected by several errata though. However, except for context 504225891Smarius * flushes, taking advantage of it should be okay even with those. 505190108Smarius */ 506220038Smarius memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 507220038Smarius sizeof(sc->sc_dma_methods)); 508220038Smarius sc->sc_is.sis_sc = sc; 509220038Smarius sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 510220038Smarius sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 511220038Smarius sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 512225891Smarius if (OF_getproplen(node, "no-streaming-cache") < 0) 513220038Smarius sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 514183423Smarius 515183423Smarius#define TSBCASE(x) \ 516183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 517183423Smarius tsbsize = (x); \ 518183423Smarius break; \ 519183423Smarius 520201199Smarius i = OF_getprop(node, "virtual-dma", (void *)prop_array, 521183423Smarius sizeof(prop_array)); 522201199Smarius if (i == -1 || i != sizeof(prop_array)) 523183423Smarius schizo_iommu_init(sc, 7, -1); 524183423Smarius else { 525183423Smarius switch (prop_array[1]) { 526183423Smarius TSBCASE(1); 527183423Smarius TSBCASE(2); 528183423Smarius TSBCASE(3); 529183423Smarius TSBCASE(4); 530183423Smarius TSBCASE(5); 531183423Smarius TSBCASE(6); 532183423Smarius TSBCASE(7); 533183423Smarius TSBCASE(8); 534183423Smarius default: 535183423Smarius panic("%s: unsupported DVMA size 0x%x", 536183423Smarius __func__, prop_array[1]); 537183423Smarius /* NOTREACHED */ 538183423Smarius } 539183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 540183423Smarius } 541185133Smarius 542183423Smarius#undef TSBCASE 543183423Smarius 544183423Smarius /* Initialize memory and I/O rmans. */ 545183423Smarius sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 546183423Smarius sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 547183423Smarius if (rman_init(&sc->sc_pci_io_rman) != 0 || 548183423Smarius rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 549183423Smarius panic("%s: failed to set up I/O rman", __func__); 550183423Smarius sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 551183423Smarius sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 552183423Smarius if (rman_init(&sc->sc_pci_mem_rman) != 0 || 553183423Smarius rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 554183423Smarius panic("%s: failed to set up memory rman", __func__); 555183423Smarius 556201199Smarius i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 557183423Smarius /* 558183423Smarius * Make sure that the expected ranges are present. The 559183423Smarius * OFW_PCI_CS_MEM64 one is not currently used though. 560183423Smarius */ 561201199Smarius if (i != STX_NRANGE) 562183423Smarius panic("%s: unsupported number of ranges", __func__); 563183423Smarius /* 564183423Smarius * Find the addresses of the various bus spaces. 565183423Smarius * There should not be multiple ones of one kind. 566183423Smarius * The physical start addresses of the ranges are the configuration, 567183423Smarius * memory and I/O handles. 568183423Smarius */ 569201199Smarius for (i = 0; i < STX_NRANGE; i++) { 570201199Smarius j = OFW_PCI_RANGE_CS(&range[i]); 571201199Smarius if (sc->sc_pci_bh[j] != 0) 572201199Smarius panic("%s: duplicate range for space %d", 573201199Smarius __func__, j); 574201199Smarius sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 575183423Smarius } 576183423Smarius free(range, M_OFWPROP); 577183423Smarius 578183423Smarius /* Register the softc, this is needed for paired Schizos. */ 579183423Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 580183423Smarius 581183423Smarius /* Allocate our tags. */ 582225931Smarius sc->sc_pci_iot = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 583225931Smarius sc->sc_mem_res[STX_PCI]), PCI_IO_BUS_SPACE, NULL); 584225931Smarius if (sc->sc_pci_iot == NULL) 585225931Smarius panic("%s: could not allocate PCI I/O tag", __func__); 586225931Smarius sc->sc_pci_cfgt = sparc64_alloc_bus_tag(NULL, rman_get_bustag( 587225931Smarius sc->sc_mem_res[STX_PCI]), PCI_CONFIG_BUS_SPACE, NULL); 588225931Smarius if (sc->sc_pci_cfgt == NULL) 589225931Smarius panic("%s: could not allocate PCI configuration space tag", 590225931Smarius __func__); 591183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 592220038Smarius sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 593220038Smarius sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 594220038Smarius &sc->sc_pci_dmat) != 0) 595225931Smarius panic("%s: could not create PCI DMA tag", __func__); 596183423Smarius /* Customize the tag. */ 597183423Smarius sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 598220038Smarius sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods; 599183423Smarius 600183423Smarius /* 601183423Smarius * Get the bus range from the firmware. 602183423Smarius * NB: Tomatillos don't support PCI bus reenumeration. 603183423Smarius */ 604201199Smarius i = OF_getprop(node, "bus-range", (void *)prop_array, 605183423Smarius sizeof(prop_array)); 606201199Smarius if (i == -1) 607183423Smarius panic("%s: could not get bus-range", __func__); 608201199Smarius if (i != sizeof(prop_array)) 609201199Smarius panic("%s: broken bus-range (%d)", __func__, i); 610201395Smarius sc->sc_pci_secbus = prop_array[0]; 611201395Smarius sc->sc_pci_subbus = prop_array[1]; 612183423Smarius if (bootverbose) 613183423Smarius device_printf(dev, "bus range %u to %u; PCI bus %d\n", 614201395Smarius sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 615183423Smarius 616183423Smarius /* Clear any pending PCI error bits. */ 617183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 618183423Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 619183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 620220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 621220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 622183423Smarius 623183423Smarius /* 624183423Smarius * Establish handlers for interesting interrupts... 625183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 626183423Smarius * bus error interrupts for one PBM can be routed to the other 627183423Smarius * PBM though we obviously need to use the softc of the former 628183423Smarius * as the argument for the interrupt handler and the softc of 629183423Smarius * the latter as the argument for the interrupt controller. 630183423Smarius */ 631183423Smarius if (sc->sc_half == 0) { 632183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 633183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 634183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 635183423Smarius sica_sc == osc)) 636183423Smarius /* 637183423Smarius * We are the driver for PBM A and either also 638183423Smarius * registered the interrupt controller for us or 639183423Smarius * the driver for PBM B has probed first and 640183423Smarius * registered it for us. 641183423Smarius */ 642183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 643183423Smarius schizo_pci_bus); 644183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 645183423Smarius osc != NULL) 646183423Smarius /* 647183423Smarius * We are the driver for PBM A but registered 648183423Smarius * the interrupt controller for PBM B, i.e. the 649183423Smarius * driver for PBM B attached first but couldn't 650183423Smarius * set up a handler for PBM B. 651183423Smarius */ 652183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 653183423Smarius schizo_pci_bus); 654183423Smarius } else { 655183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 656183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 657183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 658183423Smarius sica_sc == osc)) 659183423Smarius /* 660183423Smarius * We are the driver for PBM B and either also 661183423Smarius * registered the interrupt controller for us or 662183423Smarius * the driver for PBM A has probed first and 663183423Smarius * registered it for us. 664183423Smarius */ 665183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 666183423Smarius schizo_pci_bus); 667183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 668183423Smarius osc != NULL) 669183423Smarius /* 670183423Smarius * We are the driver for PBM B but registered 671183423Smarius * the interrupt controller for PBM A, i.e. the 672183423Smarius * driver for PBM A attached first but couldn't 673183423Smarius * set up a handler for PBM A. 674183423Smarius */ 675183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 676183423Smarius schizo_pci_bus); 677183423Smarius } 678183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 679183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 680183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 681183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 682183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 683183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 684183423Smarius 685183423Smarius /* 686185133Smarius * According to the Schizo Errata I-13, consistent DMA flushing/ 687185133Smarius * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 688201126Smarius * so we can't use it and need to live with the consequences. With 689201126Smarius * Schizo version >= 5, CDMA flushing/syncing is usable but requires 690201126Smarius * the workaround described in Schizo Errata I-23. With Tomatillo 691201126Smarius * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 692201126Smarius * version <= 4 (i.e. revision <= 2.3) bridges additionally require 693201126Smarius * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 694185133Smarius */ 695185133Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 696201199Smarius sc->sc_mode == SCHIZO_MODE_TOM || 697201199Smarius sc->sc_mode == SCHIZO_MODE_XMS) { 698185133Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) { 699220038Smarius sc->sc_dma_methods.dm_dmamap_sync = 700220038Smarius schizo_dmamap_sync; 701220038Smarius sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 702201126Smarius /* 703201126Smarius * Some firmware versions include the CDMA interrupt 704201126Smarius * at RID 4 but most don't. With the latter we add 705201126Smarius * it ourselves at the spare RID 5. 706201126Smarius */ 707201199Smarius i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 708201126Smarius 4)); 709201199Smarius if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 710201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 711201126Smarius &sc->sc_cdma_clr); 712201199Smarius schizo_set_intr(sc, 4, i, schizo_cdma); 713201126Smarius } else { 714201199Smarius i = STX_CDMA_A_INO + sc->sc_half; 715201126Smarius if (bus_set_resource(dev, SYS_RES_IRQ, 5, 716201199Smarius INTMAP_VEC(sc->sc_ign, i), 1) != 0) 717201126Smarius panic("%s: failed to add CDMA " 718201126Smarius "interrupt", __func__); 719201199Smarius j = schizo_intr_register(sc, i); 720201199Smarius if (j != 0) 721201126Smarius panic("%s: could not register " 722201126Smarius "interrupt controller for CDMA " 723201199Smarius "(%d)", __func__, j); 724201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 725201126Smarius &sc->sc_cdma_clr); 726201199Smarius schizo_set_intr(sc, 5, i, schizo_cdma); 727201126Smarius } 728220038Smarius } else { 729220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 730220038Smarius mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 731220038Smarius NULL, MTX_SPIN); 732220038Smarius sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 733220038Smarius sc->sc_half); 734220038Smarius sc->sc_dma_methods.dm_dmamap_sync = 735220038Smarius ichip_dmamap_sync; 736185133Smarius } 737185133Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 738185133Smarius sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 739185133Smarius } 740185133Smarius 741185133Smarius /* 742183423Smarius * Set the latency timer register as this isn't always done by the 743183423Smarius * firmware. 744183423Smarius */ 745183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 746183423Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 747183423Smarius 748183423Smarius ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 749183423Smarius 750208097Smarius#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 751208097Smarius SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 752208097Smarius SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 753208097Smarius (name), CTLFLAG_RD, (arg), 0, (desc)) 754208097Smarius 755208097Smarius SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 756208097Smarius "DMA correctable errors"); 757208097Smarius SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 758208097Smarius "PCI bus non-fatal errors"); 759208097Smarius 760208097Smarius#undef SCHIZO_SYSCTL_ADD_UINT 761208097Smarius 762183423Smarius device_add_child(dev, "pci", -1); 763183423Smarius return (bus_generic_attach(dev)); 764183423Smarius} 765183423Smarius 766183423Smariusstatic void 767183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 768183423Smarius driver_filter_t handler) 769183423Smarius{ 770183423Smarius u_long vec; 771183423Smarius int rid; 772183423Smarius 773183423Smarius rid = index; 774201199Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 775201199Smarius SYS_RES_IRQ, &rid, RF_ACTIVE); 776183423Smarius if (sc->sc_irq_res[index] == NULL || 777201199Smarius INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 778201199Smarius INTIGN(vec) != sc->sc_ign || 779183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 780185133Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 781216961Smarius INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 782185133Smarius &sc->sc_ihand[index]) != 0) 783183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 784183423Smarius} 785183423Smarius 786183423Smariusstatic int 787185133Smariusschizo_intr_register(struct schizo_softc *sc, u_int ino) 788185133Smarius{ 789185133Smarius struct schizo_icarg *sica; 790185133Smarius bus_addr_t intrclr, intrmap; 791185133Smarius int error; 792185133Smarius 793185133Smarius if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 794185133Smarius return (ENXIO); 795185133Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 796185133Smarius if (sica == NULL) 797185133Smarius return (ENOMEM); 798185133Smarius sica->sica_sc = sc; 799185133Smarius sica->sica_map = intrmap; 800185133Smarius sica->sica_clr = intrclr; 801185133Smarius#ifdef SCHIZO_DEBUG 802185133Smarius device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 803185133Smarius ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 804185133Smarius (u_long)intrclr); 805185133Smarius#endif 806185133Smarius error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 807185133Smarius &schizo_ic, sica)); 808185133Smarius if (error != 0) 809185133Smarius free(sica, M_DEVBUF); 810185133Smarius return (error); 811185133Smarius} 812185133Smarius 813185133Smariusstatic int 814201199Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, 815201199Smarius bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 816183423Smarius{ 817183423Smarius bus_addr_t intrclr, intrmap; 818183423Smarius uint64_t mr; 819183423Smarius 820183423Smarius /* 821183423Smarius * XXX we only look for INOs rather than INRs since the firmware 822183423Smarius * may not provide the IGN and the IGN is constant for all devices 823183423Smarius * on that PCI controller. 824183423Smarius */ 825183423Smarius 826183423Smarius if (ino > STX_MAX_INO) { 827183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 828183423Smarius ino); 829183423Smarius return (0); 830183423Smarius } 831183423Smarius 832183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 833183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 834183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 835183423Smarius if (INTINO(mr) != ino) { 836183423Smarius device_printf(sc->sc_dev, 837183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 838183423Smarius (int)INTINO(mr), ino); 839183423Smarius return (0); 840183423Smarius } 841183423Smarius 842183423Smarius if (intrmapptr != NULL) 843183423Smarius *intrmapptr = intrmap; 844183423Smarius if (intrclrptr != NULL) 845183423Smarius *intrclrptr = intrclr; 846183423Smarius return (1); 847183423Smarius} 848183423Smarius 849183423Smarius/* 850183423Smarius * Interrupt handlers 851183423Smarius */ 852183423Smariusstatic int 853183423Smariusschizo_pci_bus(void *arg) 854183423Smarius{ 855183423Smarius struct schizo_softc *sc = arg; 856220038Smarius uint64_t afar, afsr, csr, iommu, xstat; 857183423Smarius uint32_t status; 858208097Smarius u_int fatal; 859183423Smarius 860208097Smarius fatal = 0; 861208097Smarius 862208097Smarius mtx_lock_spin(sc->sc_mtx); 863208097Smarius 864183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 865183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 866183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 867183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 868220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 869220038Smarius xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 870220038Smarius else 871220038Smarius xstat = 0; 872183423Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 873183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 874183423Smarius 875208097Smarius /* 876208097Smarius * IOMMU errors are only fatal on Tomatillo and there also only if 877208097Smarius * target abort was not signaled. 878208097Smarius */ 879208097Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 880208097Smarius (iommu & TOM_PCI_IOMMU_ERR) != 0 && 881208097Smarius ((status & PCIM_STATUS_STABORT) == 0 || 882208097Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 883208097Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 884208097Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 885208097Smarius fatal = 1; 886208097Smarius else if ((status & PCIM_STATUS_STABORT) != 0) 887208097Smarius fatal = 1; 888208097Smarius if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 889208097Smarius PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 890212378Sjhb PCIM_STATUS_MDPERR)) != 0 || 891208097Smarius (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 892208097Smarius STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 893208097Smarius SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 894208097Smarius (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 895208097Smarius STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 896208097Smarius STX_PCI_AFSR_P_UNUS)) != 0) 897208097Smarius fatal = 1; 898220038Smarius if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 899220038Smarius XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 900220038Smarius XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 901220038Smarius XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 902220038Smarius fatal = 1; 903208097Smarius if (fatal == 0) 904208097Smarius sc->sc_stats_pci_non_fatal++; 905183423Smarius 906208097Smarius device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 907220038Smarius "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 908220038Smarius 'A' + sc->sc_half, (unsigned long long)afar, 909220038Smarius (unsigned long long)afsr, (unsigned long long)csr, 910220038Smarius (unsigned long long)iommu, (unsigned long long)xstat, status); 911183423Smarius 912183423Smarius /* Clear the error bits that we caught. */ 913183423Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 914183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 915183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 916183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 917208097Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 918220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 919220038Smarius SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 920208097Smarius 921208097Smarius mtx_unlock_spin(sc->sc_mtx); 922208097Smarius 923208097Smarius if (fatal != 0) 924208097Smarius panic("%s: fatal PCI bus error", 925208097Smarius device_get_nameunit(sc->sc_dev)); 926183423Smarius return (FILTER_HANDLED); 927183423Smarius} 928183423Smarius 929183423Smariusstatic int 930183423Smariusschizo_ue(void *arg) 931183423Smarius{ 932183423Smarius struct schizo_softc *sc = arg; 933183423Smarius uint64_t afar, afsr; 934183423Smarius int i; 935183423Smarius 936183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 937183423Smarius for (i = 0; i < 1000; i++) 938183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 939183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 940183423Smarius break; 941183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 942206020Smarius device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 943183423Smarius (unsigned long long)afsr); 944183423Smarius return (FILTER_HANDLED); 945183423Smarius} 946183423Smarius 947183423Smariusstatic int 948183423Smariusschizo_ce(void *arg) 949183423Smarius{ 950183423Smarius struct schizo_softc *sc = arg; 951183423Smarius uint64_t afar, afsr; 952183423Smarius int i; 953183423Smarius 954183423Smarius mtx_lock_spin(sc->sc_mtx); 955208097Smarius 956183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 957183423Smarius for (i = 0; i < 1000; i++) 958183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 959183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 960183423Smarius break; 961208097Smarius sc->sc_stats_dma_ce++; 962183423Smarius device_printf(sc->sc_dev, 963183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 964183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 965208097Smarius 966183423Smarius /* Clear the error bits that we caught. */ 967183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 968208097Smarius 969183423Smarius mtx_unlock_spin(sc->sc_mtx); 970208097Smarius 971183423Smarius return (FILTER_HANDLED); 972183423Smarius} 973183423Smarius 974183423Smariusstatic int 975183423Smariusschizo_host_bus(void *arg) 976183423Smarius{ 977183423Smarius struct schizo_softc *sc = arg; 978183423Smarius uint64_t errlog; 979183423Smarius 980183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 981206020Smarius panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 982183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 983183423Smarius (unsigned long long)errlog); 984183423Smarius return (FILTER_HANDLED); 985183423Smarius} 986183423Smarius 987185133Smariusstatic int 988185133Smariusschizo_cdma(void *arg) 989185133Smarius{ 990185133Smarius struct schizo_softc *sc = arg; 991185133Smarius 992220038Smarius atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_RECEIVED); 993185133Smarius return (FILTER_HANDLED); 994185133Smarius} 995185133Smarius 996183423Smariusstatic void 997183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 998183423Smarius{ 999183423Smarius 1000183423Smarius /* Punch in our copies. */ 1001220038Smarius sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1002220038Smarius sc->sc_is.sis_is.is_bushandle = 1003220038Smarius rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 1004220038Smarius sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 1005220038Smarius sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 1006220038Smarius sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 1007220038Smarius sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 1008220038Smarius sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 1009220038Smarius sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 1010183423Smarius 1011220038Smarius iommu_init(device_get_nameunit(sc->sc_dev), 1012220038Smarius (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 1013183423Smarius} 1014183423Smarius 1015183423Smariusstatic int 1016183423Smariusschizo_maxslots(device_t dev) 1017183423Smarius{ 1018183423Smarius struct schizo_softc *sc; 1019183423Smarius 1020183423Smarius sc = device_get_softc(dev); 1021183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 1022183423Smarius return (sc->sc_half == 0 ? 4 : 6); 1023183423Smarius 1024183423Smarius /* XXX: is this correct? */ 1025183423Smarius return (PCI_SLOTMAX); 1026183423Smarius} 1027183423Smarius 1028183423Smariusstatic uint32_t 1029183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 1030183423Smarius int width) 1031183423Smarius{ 1032183423Smarius struct schizo_softc *sc; 1033183423Smarius bus_space_handle_t bh; 1034183423Smarius u_long offset = 0; 1035183423Smarius uint32_t r, wrd; 1036183423Smarius int i; 1037183423Smarius uint16_t shrt; 1038183423Smarius uint8_t byte; 1039183423Smarius 1040183423Smarius sc = device_get_softc(dev); 1041201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1042201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1043201395Smarius return (-1); 1044183423Smarius 1045183423Smarius /* 1046183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 1047183423Smarius */ 1048183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1049183423Smarius slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1050183423Smarius reg + width > 0x80) 1051183423Smarius return (0); 1052183423Smarius 1053183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1054183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1055183423Smarius switch (width) { 1056183423Smarius case 1: 1057183423Smarius i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1058183423Smarius r = byte; 1059183423Smarius break; 1060183423Smarius case 2: 1061183423Smarius i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1062183423Smarius r = shrt; 1063183423Smarius break; 1064183423Smarius case 4: 1065183423Smarius i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1066183423Smarius r = wrd; 1067183423Smarius break; 1068183423Smarius default: 1069183423Smarius panic("%s: bad width", __func__); 1070183423Smarius /* NOTREACHED */ 1071183423Smarius } 1072183423Smarius 1073183423Smarius if (i) { 1074183423Smarius#ifdef SCHIZO_DEBUG 1075183423Smarius printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1076183423Smarius __func__, bus, slot, func, reg); 1077183423Smarius#endif 1078183423Smarius r = -1; 1079183423Smarius } 1080183423Smarius return (r); 1081183423Smarius} 1082183423Smarius 1083183423Smariusstatic void 1084201199Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1085201199Smarius u_int reg, uint32_t val, int width) 1086183423Smarius{ 1087183423Smarius struct schizo_softc *sc; 1088183423Smarius bus_space_handle_t bh; 1089183423Smarius u_long offset = 0; 1090183423Smarius 1091183423Smarius sc = device_get_softc(dev); 1092201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1093201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1094201395Smarius return; 1095201395Smarius 1096183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1097183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1098183423Smarius switch (width) { 1099183423Smarius case 1: 1100183423Smarius bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1101183423Smarius break; 1102183423Smarius case 2: 1103183423Smarius bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1104183423Smarius break; 1105183423Smarius case 4: 1106183423Smarius bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1107183423Smarius break; 1108183423Smarius default: 1109183423Smarius panic("%s: bad width", __func__); 1110183423Smarius /* NOTREACHED */ 1111183423Smarius } 1112183423Smarius} 1113183423Smarius 1114183423Smariusstatic int 1115183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 1116183423Smarius{ 1117183423Smarius struct schizo_softc *sc; 1118183423Smarius struct ofw_pci_register reg; 1119183423Smarius ofw_pci_intr_t pintr, mintr; 1120183423Smarius uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1121183423Smarius 1122183423Smarius sc = device_get_softc(bridge); 1123183423Smarius pintr = pin; 1124201199Smarius if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1125201199Smarius ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1126209298Snwhitehorn NULL, maskbuf)) 1127183423Smarius return (mintr); 1128183423Smarius 1129183423Smarius device_printf(bridge, "could not route pin %d for device %d.%d\n", 1130183423Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 1131183423Smarius return (PCI_INVALID_IRQ); 1132183423Smarius} 1133183423Smarius 1134183423Smariusstatic int 1135183423Smariusschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1136183423Smarius{ 1137183423Smarius struct schizo_softc *sc; 1138183423Smarius 1139183423Smarius sc = device_get_softc(dev); 1140183423Smarius switch (which) { 1141183423Smarius case PCIB_IVAR_DOMAIN: 1142183423Smarius *result = device_get_unit(dev); 1143183423Smarius return (0); 1144183423Smarius case PCIB_IVAR_BUS: 1145183423Smarius *result = sc->sc_pci_secbus; 1146183423Smarius return (0); 1147183423Smarius } 1148183423Smarius return (ENOENT); 1149183423Smarius} 1150183423Smarius 1151220038Smariusstatic void 1152220038Smariusschizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1153185133Smarius{ 1154185133Smarius struct timeval cur, end; 1155220038Smarius struct schizo_iommu_state *sis = dt->dt_cookie; 1156220038Smarius struct schizo_softc *sc = sis->sis_sc; 1157220038Smarius int res; 1158185133Smarius 1159220038Smarius if ((map->dm_flags & DMF_STREAMED) != 0) { 1160220038Smarius iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1161220038Smarius return; 1162220038Smarius } 1163220038Smarius 1164220038Smarius if ((map->dm_flags & DMF_LOADED) == 0) 1165220038Smarius return; 1166220038Smarius 1167220038Smarius if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1168220038Smarius /* 1169225931Smarius * Note that in order to allow this function to be called from 1170220038Smarius * filters we would need to use a spin mutex for serialization 1171220038Smarius * but given that these disable interrupts we have to emulate 1172220038Smarius * one. 1173220038Smarius */ 1174220038Smarius for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1175220038Smarius SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1176220038Smarius ; 1177220038Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1178185133Smarius microuptime(&cur); 1179220038Smarius end.tv_sec = 1; 1180220038Smarius end.tv_usec = 0; 1181220038Smarius timevaladd(&end, &cur); 1182220038Smarius for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1183220038Smarius SCHIZO_CDMA_STATE_RECEIVED, SCHIZO_CDMA_STATE_IDLE)) == 1184220038Smarius 0 && timevalcmp(&cur, &end, <=);) 1185220038Smarius microuptime(&cur); 1186220038Smarius if (res == 0) 1187220038Smarius panic("%s: DMA does not sync", __func__); 1188220038Smarius } 1189220038Smarius 1190220038Smarius if ((op & BUS_DMASYNC_PREWRITE) != 0) 1191220038Smarius membar(Sync); 1192185133Smarius} 1193185133Smarius 1194183423Smarius#define VIS_BLOCKSIZE 64 1195183423Smarius 1196220038Smariusstatic void 1197220038Smariusichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1198183423Smarius{ 1199183423Smarius static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1200185133Smarius struct timeval cur, end; 1201220038Smarius struct schizo_iommu_state *sis = dt->dt_cookie; 1202220038Smarius struct schizo_softc *sc = sis->sis_sc; 1203184428Smarius register_t reg, s; 1204183423Smarius 1205220038Smarius if ((map->dm_flags & DMF_STREAMED) != 0) { 1206220038Smarius iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1207220038Smarius return; 1208220038Smarius } 1209220038Smarius 1210220038Smarius if ((map->dm_flags & DMF_LOADED) == 0) 1211220038Smarius return; 1212220038Smarius 1213220038Smarius if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1214220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 1215220038Smarius mtx_lock_spin(&sc->sc_sync_mtx); 1216220038Smarius SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1217220038Smarius sc->sc_sync_val); 1218185133Smarius microuptime(&cur); 1219220038Smarius end.tv_sec = 1; 1220220038Smarius end.tv_usec = 0; 1221220038Smarius timevaladd(&end, &cur); 1222220038Smarius for (; ((reg = SCHIZO_PCI_READ_8(sc, 1223220038Smarius TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1224220038Smarius timevalcmp(&cur, &end, <=);) 1225220038Smarius microuptime(&cur); 1226220038Smarius if ((reg & sc->sc_sync_val) != 0) 1227220038Smarius panic("%s: DMA does not sync", __func__); 1228220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 1229220038Smarius mtx_unlock_spin(&sc->sc_sync_mtx); 1230220038Smarius else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1231220038Smarius s = intr_disable(); 1232220038Smarius reg = rd(fprs); 1233220038Smarius wr(fprs, reg | FPRS_FEF, 0); 1234220038Smarius __asm __volatile("stda %%f0, [%0] %1" 1235220038Smarius : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1236220038Smarius membar(Sync); 1237220038Smarius wr(fprs, reg, 0); 1238220038Smarius intr_restore(s); 1239220038Smarius return; 1240220038Smarius } 1241220038Smarius } 1242183423Smarius 1243220038Smarius if ((op & BUS_DMASYNC_PREWRITE) != 0) 1244184428Smarius membar(Sync); 1245183423Smarius} 1246183423Smarius 1247183423Smariusstatic void 1248183423Smariusschizo_intr_enable(void *arg) 1249183423Smarius{ 1250183423Smarius struct intr_vector *iv = arg; 1251183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1252183423Smarius 1253183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1254183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1255183423Smarius} 1256183423Smarius 1257183423Smariusstatic void 1258183423Smariusschizo_intr_disable(void *arg) 1259183423Smarius{ 1260183423Smarius struct intr_vector *iv = arg; 1261183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1262183423Smarius 1263183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1264183423Smarius} 1265183423Smarius 1266183423Smariusstatic void 1267183423Smariusschizo_intr_assign(void *arg) 1268183423Smarius{ 1269183423Smarius struct intr_vector *iv = arg; 1270183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1271183423Smarius 1272183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1273183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1274183423Smarius} 1275183423Smarius 1276183423Smariusstatic void 1277183423Smariusschizo_intr_clear(void *arg) 1278183423Smarius{ 1279183423Smarius struct intr_vector *iv = arg; 1280183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1281183423Smarius 1282206018Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1283183423Smarius} 1284183423Smarius 1285183423Smariusstatic int 1286183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1287183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1288183423Smarius void **cookiep) 1289183423Smarius{ 1290183423Smarius struct schizo_softc *sc; 1291183423Smarius u_long vec; 1292220038Smarius int error; 1293183423Smarius 1294183423Smarius sc = device_get_softc(dev); 1295183423Smarius /* 1296186290Smarius * Make sure the vector is fully specified. 1297183423Smarius */ 1298183423Smarius vec = rman_get_start(ires); 1299186290Smarius if (INTIGN(vec) != sc->sc_ign) { 1300183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1301183423Smarius return (EINVAL); 1302183423Smarius } 1303183423Smarius 1304186290Smarius if (intr_vectors[vec].iv_ic == &schizo_ic) { 1305186290Smarius /* 1306186290Smarius * Ensure we use the right softc in case the interrupt 1307186290Smarius * is routed to our companion PBM for some odd reason. 1308186290Smarius */ 1309186290Smarius sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1310186290Smarius sica_sc; 1311186290Smarius } else if (intr_vectors[vec].iv_ic == NULL) { 1312186290Smarius /* 1313186290Smarius * Work around broken firmware which misses entries in 1314186290Smarius * the ino-bitmap. 1315186290Smarius */ 1316186290Smarius error = schizo_intr_register(sc, INTINO(vec)); 1317186290Smarius if (error != 0) { 1318186290Smarius device_printf(dev, "could not register interrupt " 1319186290Smarius "controller for vector 0x%lx (%d)\n", vec, error); 1320186290Smarius return (error); 1321186290Smarius } 1322190108Smarius if (bootverbose) 1323190108Smarius device_printf(dev, "belatedly registered as " 1324190108Smarius "interrupt controller for vector 0x%lx\n", vec); 1325186290Smarius } else { 1326186290Smarius device_printf(dev, 1327186290Smarius "invalid interrupt controller for vector 0x%lx\n", vec); 1328186290Smarius return (EINVAL); 1329186290Smarius } 1330183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1331183423Smarius arg, cookiep)); 1332183423Smarius} 1333183423Smarius 1334183423Smariusstatic struct resource * 1335183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1336183423Smarius u_long start, u_long end, u_long count, u_int flags) 1337183423Smarius{ 1338183423Smarius struct schizo_softc *sc; 1339183423Smarius struct resource *rv; 1340183423Smarius struct rman *rm; 1341183423Smarius 1342183423Smarius sc = device_get_softc(bus); 1343225931Smarius switch (type) { 1344225931Smarius case SYS_RES_IRQ: 1345183423Smarius /* 1346183423Smarius * XXX: Don't accept blank ranges for now, only single 1347183423Smarius * interrupts. The other case should not happen with 1348183423Smarius * the MI PCI code... 1349183423Smarius * XXX: This may return a resource that is out of the 1350183423Smarius * range that was specified. Is this correct...? 1351183423Smarius */ 1352183423Smarius if (start != end) 1353183423Smarius panic("%s: XXX: interrupt range", __func__); 1354183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1355225931Smarius return (bus_generic_alloc_resource(bus, child, type, rid, 1356225931Smarius start, end, count, flags)); 1357183423Smarius case SYS_RES_MEMORY: 1358183423Smarius rm = &sc->sc_pci_mem_rman; 1359183423Smarius break; 1360183423Smarius case SYS_RES_IOPORT: 1361183423Smarius rm = &sc->sc_pci_io_rman; 1362183423Smarius break; 1363183423Smarius default: 1364183423Smarius return (NULL); 1365183423Smarius } 1366183423Smarius 1367225931Smarius rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 1368225931Smarius child); 1369183423Smarius if (rv == NULL) 1370183423Smarius return (NULL); 1371183423Smarius rman_set_rid(rv, *rid); 1372183423Smarius 1373225931Smarius if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child, type, 1374225931Smarius *rid, rv) != 0) { 1375225931Smarius rman_release_resource(rv); 1376225931Smarius return (NULL); 1377183423Smarius } 1378183423Smarius return (rv); 1379183423Smarius} 1380183423Smarius 1381183423Smariusstatic int 1382183423Smariusschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1383183423Smarius struct resource *r) 1384183423Smarius{ 1385225931Smarius struct schizo_softc *sc; 1386225931Smarius struct bus_space_tag *tag; 1387183423Smarius 1388225931Smarius sc = device_get_softc(bus); 1389225931Smarius switch (type) { 1390225931Smarius case SYS_RES_IRQ: 1391225931Smarius return (bus_generic_activate_resource(bus, child, type, rid, 1392225931Smarius r)); 1393225931Smarius case SYS_RES_MEMORY: 1394225931Smarius tag = sparc64_alloc_bus_tag(r, rman_get_bustag( 1395225931Smarius sc->sc_mem_res[STX_PCI]), PCI_MEMORY_BUS_SPACE, NULL); 1396225931Smarius if (tag == NULL) 1397225931Smarius return (ENOMEM); 1398225931Smarius rman_set_bustag(r, tag); 1399225931Smarius rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_MEM32] + 1400225931Smarius rman_get_start(r)); 1401225931Smarius break; 1402225931Smarius case SYS_RES_IOPORT: 1403225931Smarius rman_set_bustag(r, sc->sc_pci_iot); 1404225931Smarius rman_set_bushandle(r, sc->sc_pci_bh[OFW_PCI_CS_IO] + 1405225931Smarius rman_get_start(r)); 1406225931Smarius break; 1407183423Smarius } 1408183423Smarius return (rman_activate_resource(r)); 1409183423Smarius} 1410183423Smarius 1411183423Smariusstatic int 1412225931Smariusschizo_adjust_resource(device_t bus, device_t child, int type, 1413225931Smarius struct resource *r, u_long start, u_long end) 1414183423Smarius{ 1415225931Smarius struct schizo_softc *sc; 1416225931Smarius struct rman *rm; 1417183423Smarius 1418225931Smarius sc = device_get_softc(bus); 1419225931Smarius switch (type) { 1420225931Smarius case SYS_RES_IRQ: 1421225931Smarius return (bus_generic_adjust_resource(bus, child, type, r, 1422225931Smarius start, end)); 1423225931Smarius case SYS_RES_MEMORY: 1424225931Smarius rm = &sc->sc_pci_mem_rman; 1425225931Smarius break; 1426225931Smarius case SYS_RES_IOPORT: 1427225931Smarius rm = &sc->sc_pci_io_rman; 1428225931Smarius break; 1429225931Smarius default: 1430225931Smarius return (EINVAL); 1431183423Smarius } 1432225931Smarius if (rman_is_region_manager(r, rm) == 0) 1433225931Smarius return (EINVAL); 1434225931Smarius return (rman_adjust_resource(r, start, end)); 1435183423Smarius} 1436183423Smarius 1437183423Smariusstatic bus_dma_tag_t 1438220038Smariusschizo_get_dma_tag(device_t bus, device_t child __unused) 1439183423Smarius{ 1440183423Smarius struct schizo_softc *sc; 1441183423Smarius 1442183423Smarius sc = device_get_softc(bus); 1443183423Smarius return (sc->sc_pci_dmat); 1444183423Smarius} 1445183423Smarius 1446183423Smariusstatic phandle_t 1447220038Smariusschizo_get_node(device_t bus, device_t child __unused) 1448183423Smarius{ 1449183423Smarius struct schizo_softc *sc; 1450183423Smarius 1451183423Smarius sc = device_get_softc(bus); 1452183423Smarius /* We only have one child, the PCI bus, which needs our own node. */ 1453183423Smarius return (sc->sc_node); 1454183423Smarius} 1455183423Smarius 1456220038Smariusstatic void 1457220038Smariusschizo_setup_device(device_t bus, device_t child) 1458220038Smarius{ 1459220038Smarius struct schizo_softc *sc; 1460220038Smarius uint64_t reg; 1461220038Smarius int capreg; 1462220038Smarius 1463220038Smarius sc = device_get_softc(bus); 1464220038Smarius /* 1465220038Smarius * Disable bus parking in order to work around a bus hang caused by 1466220038Smarius * Casinni/Skyhawk combinations. 1467225931Smarius */ 1468220038Smarius if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1469220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1470220038Smarius STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1471220038Smarius 1472220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) { 1473220038Smarius /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1474220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1475220038Smarius (pci_read_config(child, PCIR_HDRTYPE, 1) & 1476220038Smarius PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1477220038Smarius pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1478220038Smarius pci_write_config(child, capreg + PCIXR_COMMAND, 1479220038Smarius pci_read_config(child, capreg + PCIXR_COMMAND, 1480220038Smarius 2) & 0x7c, 2); 1481220038Smarius /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1482220038Smarius if (sc->sc_mrev >= 4) { 1483220038Smarius reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1484220038Smarius 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1485220038Smarius if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1486220038Smarius XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1487220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1488220038Smarius } 1489220038Smarius } 1490220038Smarius} 1491220038Smarius 1492183423Smariusstatic u_int 1493183423Smariusschizo_get_timecount(struct timecounter *tc) 1494183423Smarius{ 1495183423Smarius struct schizo_softc *sc; 1496183423Smarius 1497183423Smarius sc = tc->tc_priv; 1498223959Smarius return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1499223959Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >> 1500223959Smarius STX_CTRL_PERF_CNT_CNT0_SHIFT); 1501183423Smarius} 1502