schizo.c revision 223959
1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4220038Smarius * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 223959 2011-07-12 17:55:34Z marius $"); 36183423Smarius 37183423Smarius/* 38220038Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 39220038Smarius * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55208097Smarius#include <sys/sysctl.h> 56185133Smarius#include <sys/time.h> 57183423Smarius#include <sys/timetc.h> 58183423Smarius 59183423Smarius#include <dev/ofw/ofw_bus.h> 60183423Smarius#include <dev/ofw/ofw_pci.h> 61183423Smarius#include <dev/ofw/openfirm.h> 62183423Smarius 63183423Smarius#include <machine/bus.h> 64183423Smarius#include <machine/bus_common.h> 65183423Smarius#include <machine/bus_private.h> 66183423Smarius#include <machine/fsr.h> 67183423Smarius#include <machine/iommureg.h> 68183423Smarius#include <machine/iommuvar.h> 69183423Smarius#include <machine/resource.h> 70183423Smarius 71183423Smarius#include <dev/pci/pcireg.h> 72183423Smarius#include <dev/pci/pcivar.h> 73183423Smarius 74183423Smarius#include <sparc64/pci/ofw_pci.h> 75183423Smarius#include <sparc64/pci/schizoreg.h> 76183423Smarius#include <sparc64/pci/schizovar.h> 77183423Smarius 78183423Smarius#include "pcib_if.h" 79183423Smarius 80183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 81183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82183423Smarius driver_filter_t); 83220038Smariusstatic void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 84220038Smarius bus_dmasync_op_t op); 85220038Smariusstatic void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 86220038Smarius bus_dmasync_op_t op); 87183423Smariusstatic void schizo_intr_enable(void *); 88183423Smariusstatic void schizo_intr_disable(void *); 89183423Smariusstatic void schizo_intr_assign(void *); 90183423Smariusstatic void schizo_intr_clear(void *); 91185133Smariusstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 92183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 93183423Smarius bus_addr_t *, bus_addr_t *); 94183423Smariusstatic bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 95183423Smariusstatic timecounter_get_t schizo_get_timecount; 96183423Smarius 97183423Smarius/* Interrupt handlers */ 98183423Smariusstatic driver_filter_t schizo_pci_bus; 99183423Smariusstatic driver_filter_t schizo_ue; 100183423Smariusstatic driver_filter_t schizo_ce; 101183423Smariusstatic driver_filter_t schizo_host_bus; 102185133Smariusstatic driver_filter_t schizo_cdma; 103183423Smarius 104183423Smarius/* IOMMU support */ 105183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 106183423Smarius 107183423Smarius/* 108183423Smarius * Methods 109183423Smarius */ 110183423Smariusstatic device_probe_t schizo_probe; 111183423Smariusstatic device_attach_t schizo_attach; 112183423Smariusstatic bus_read_ivar_t schizo_read_ivar; 113183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 114183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 115183423Smariusstatic bus_activate_resource_t schizo_activate_resource; 116183423Smariusstatic bus_deactivate_resource_t schizo_deactivate_resource; 117183423Smariusstatic bus_release_resource_t schizo_release_resource; 118183423Smariusstatic bus_get_dma_tag_t schizo_get_dma_tag; 119183423Smariusstatic pcib_maxslots_t schizo_maxslots; 120183423Smariusstatic pcib_read_config_t schizo_read_config; 121183423Smariusstatic pcib_write_config_t schizo_write_config; 122183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 123183423Smariusstatic ofw_bus_get_node_t schizo_get_node; 124220038Smariusstatic ofw_pci_setup_device_t schizo_setup_device; 125183423Smarius 126183423Smariusstatic device_method_t schizo_methods[] = { 127183423Smarius /* Device interface */ 128183423Smarius DEVMETHOD(device_probe, schizo_probe), 129183423Smarius DEVMETHOD(device_attach, schizo_attach), 130183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 131183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 132183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 133183423Smarius 134183423Smarius /* Bus interface */ 135183423Smarius DEVMETHOD(bus_print_child, bus_generic_print_child), 136183423Smarius DEVMETHOD(bus_read_ivar, schizo_read_ivar), 137183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 138220038Smarius DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 139183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 140183423Smarius DEVMETHOD(bus_activate_resource, schizo_activate_resource), 141183423Smarius DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 142183423Smarius DEVMETHOD(bus_release_resource, schizo_release_resource), 143183423Smarius DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 144183423Smarius 145183423Smarius /* pcib interface */ 146183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 147183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 148183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 149183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 150183423Smarius 151183423Smarius /* ofw_bus interface */ 152183423Smarius DEVMETHOD(ofw_bus_get_node, schizo_get_node), 153183423Smarius 154220038Smarius /* ofw_pci interface */ 155220038Smarius DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 156220038Smarius 157190108Smarius KOBJMETHOD_END 158183423Smarius}; 159183423Smarius 160183423Smariusstatic devclass_t schizo_devclass; 161183423Smarius 162183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 163183423Smarius sizeof(struct schizo_softc)); 164215349SmariusEARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 165215349Smarius BUS_PASS_BUS); 166183423Smarius 167183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 168183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 169183423Smarius 170183423Smariusstatic const struct intr_controller schizo_ic = { 171183423Smarius schizo_intr_enable, 172183423Smarius schizo_intr_disable, 173183423Smarius schizo_intr_assign, 174183423Smarius schizo_intr_clear 175183423Smarius}; 176183423Smarius 177183423Smariusstruct schizo_icarg { 178183423Smarius struct schizo_softc *sica_sc; 179183423Smarius bus_addr_t sica_map; 180183423Smarius bus_addr_t sica_clr; 181183423Smarius}; 182183423Smarius 183183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 184183423Smarius 185220038Smarius#define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 186220038Smarius bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 187206018Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 188183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 189206018Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 190183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 191183423Smarius 192220038Smarius#ifndef SCHIZO_DEBUG 193220038Smarius#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 194220038Smarius SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 195220038Smarius#else 196220038Smarius#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 197220038Smarius device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 198220038Smarius (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 199220038Smarius (unsigned long long)(v)); \ 200220038Smarius SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 201220038Smarius } while (0) 202220038Smarius#endif 203220038Smarius 204206018Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 205183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 206206018Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 207183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 208206018Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 209183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 210206018Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 211183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 212206018Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 213183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 214206018Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 215183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 216206018Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 217183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 218206018Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 219183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 220183423Smarius 221220038Smarius#define SCHIZO_PCI_SET(sc, offs, v) \ 222220038Smarius SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 223220038Smarius#define SCHIZO_CTRL_SET(sc, offs, v) \ 224220038Smarius SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 225220038Smarius 226183423Smariusstruct schizo_desc { 227183423Smarius const char *sd_string; 228183423Smarius int sd_mode; 229183423Smarius const char *sd_name; 230183423Smarius}; 231183423Smarius 232185133Smariusstatic const struct schizo_desc const schizo_compats[] = { 233183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 234220038Smarius#if 0 235220038Smarius { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 236220038Smarius#endif 237183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 238183423Smarius { NULL, 0, NULL } 239183423Smarius}; 240183423Smarius 241183423Smariusstatic const struct schizo_desc * 242183423Smariusschizo_get_desc(device_t dev) 243183423Smarius{ 244183423Smarius const struct schizo_desc *desc; 245183423Smarius const char *compat; 246183423Smarius 247183423Smarius compat = ofw_bus_get_compat(dev); 248183423Smarius if (compat == NULL) 249183423Smarius return (NULL); 250183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 251183423Smarius if (strcmp(desc->sd_string, compat) == 0) 252183423Smarius return (desc); 253183423Smarius return (NULL); 254183423Smarius} 255183423Smarius 256183423Smariusstatic int 257183423Smariusschizo_probe(device_t dev) 258183423Smarius{ 259183423Smarius const char *dtype; 260183423Smarius 261183423Smarius dtype = ofw_bus_get_type(dev); 262197164Smarius if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 263183423Smarius schizo_get_desc(dev) != NULL) { 264183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 265183423Smarius return (0); 266183423Smarius } 267183423Smarius return (ENXIO); 268183423Smarius} 269183423Smarius 270183423Smariusstatic int 271183423Smariusschizo_attach(device_t dev) 272183423Smarius{ 273183423Smarius struct ofw_pci_ranges *range; 274183423Smarius const struct schizo_desc *desc; 275183423Smarius struct schizo_softc *asc, *sc, *osc; 276183423Smarius struct timecounter *tc; 277183423Smarius uint64_t ino_bitmap, reg; 278183423Smarius phandle_t node; 279183423Smarius uint32_t prop, prop_array[2]; 280201199Smarius int i, j, mode, rid, tsbsize; 281183423Smarius 282183423Smarius sc = device_get_softc(dev); 283183423Smarius node = ofw_bus_get_node(dev); 284183423Smarius desc = schizo_get_desc(dev); 285183423Smarius mode = desc->sd_mode; 286183423Smarius 287183423Smarius sc->sc_dev = dev; 288183423Smarius sc->sc_node = node; 289183423Smarius sc->sc_mode = mode; 290185133Smarius sc->sc_flags = 0; 291183423Smarius 292183423Smarius /* 293183423Smarius * The Schizo has three register banks: 294183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 295183423Smarius * shared with the UPA64s interrupt mapping register banks 296183423Smarius * (1) shared Schizo controller configuration and status registers 297183423Smarius * (2) per-PBM PCI configuration space 298183423Smarius * 299183423Smarius * The Tomatillo has four register banks: 300183423Smarius * (0) per-PBM PCI configuration and status registers 301183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 302183423Smarius * machines having the `jbusppm' device shared with its Estar 303183423Smarius * register bank for bus A 304183423Smarius * (2) per-PBM PCI configuration space 305183423Smarius * (3) per-PBM interrupt concentrator registers 306183423Smarius */ 307183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 308183423Smarius 20) & 1; 309201199Smarius for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 310201199Smarius i++) { 311201199Smarius rid = i; 312201199Smarius sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 313183423Smarius SYS_RES_MEMORY, &rid, 314183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 315201199Smarius i == STX_PCI) || i == STX_CTRL)) || 316183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 317201199Smarius i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 318201199Smarius if (sc->sc_mem_res[i] == NULL) 319183423Smarius panic("%s: could not allocate register bank %d", 320201199Smarius __func__, i); 321183423Smarius } 322183423Smarius 323183423Smarius /* 324183423Smarius * Match other Schizos that are already configured against 325183423Smarius * the controller base physical address. This will be the 326183423Smarius * same for a pair of devices that share register space. 327183423Smarius */ 328183423Smarius osc = NULL; 329183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 330183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 331183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 332183423Smarius /* Found partner. */ 333183423Smarius osc = asc; 334183423Smarius break; 335183423Smarius } 336183423Smarius } 337183423Smarius if (osc == NULL) { 338183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 339183423Smarius M_NOWAIT | M_ZERO); 340183423Smarius if (sc->sc_mtx == NULL) 341183423Smarius panic("%s: could not malloc mutex", __func__); 342183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 343183423Smarius } else { 344185133Smarius if (sc->sc_mode != SCHIZO_MODE_SCZ) 345185133Smarius panic("%s: no partner expected", __func__); 346183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 347183423Smarius panic("%s: mutex not initialized", __func__); 348183423Smarius sc->sc_mtx = osc->sc_mtx; 349183423Smarius } 350183423Smarius 351183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 352183423Smarius panic("%s: could not determine IGN", __func__); 353201199Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 354201199Smarius -1) 355183423Smarius panic("%s: could not determine version", __func__); 356220038Smarius if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 357220038Smarius &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 358220038Smarius panic("%s: could not determine module-revision", __func__); 359183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 360183423Smarius prop = 33000000; 361183423Smarius 362220038Smarius if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 363220038Smarius XMS_PCI_CTRL_X_MODE) != 0) { 364220038Smarius if (sc->sc_mrev < 1) 365220038Smarius panic("PCI-X mode unsupported"); 366220038Smarius sc->sc_flags |= SCHIZO_FLAGS_XMODE; 367220038Smarius } 368183423Smarius 369220038Smarius device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 370220038Smarius if (mode == SCHIZO_MODE_XMS) 371220038Smarius printf("module-revision %d, ", sc->sc_mrev); 372220038Smarius printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 373220038Smarius 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 374220038Smarius "-X" : "", prop / 1000 / 1000); 375220038Smarius 376183423Smarius /* Set up the PCI interrupt retry timer. */ 377220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 378183423Smarius 379183423Smarius /* Set up the PCI control register. */ 380183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 381220038Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 382220038Smarius STX_PCI_CTRL_ARB_MASK); 383183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 384220038Smarius STX_PCI_CTRL_ERR_IEN; 385183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 386183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 387220038Smarius if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 388220038Smarius reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 389220038Smarius else 390220038Smarius reg |= STX_PCI_CTRL_ARB_MASK; 391183423Smarius if (mode == SCHIZO_MODE_TOM) { 392183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 393183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 394183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 395183423Smarius else 396183423Smarius reg |= STX_PCI_CTRL_PTO; 397220038Smarius } else if (mode == SCHIZO_MODE_XMS) { 398220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 399220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 400220038Smarius reg |= XMS_PCI_CTRL_X_ERRINT_EN; 401183423Smarius } 402220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 403183423Smarius 404183423Smarius /* Set up the PCI diagnostic register. */ 405183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 406183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 407183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 408220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 409183423Smarius 410183423Smarius /* 411208097Smarius * Enable DMA write parity error interrupts of version >= 7 (i.e. 412220038Smarius * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 413220038Smarius * no effect though). 414208097Smarius */ 415220038Smarius if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 416220038Smarius mode == SCHIZO_MODE_XMS) { 417208097Smarius reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 418208097Smarius reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 419220038Smarius SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 420208097Smarius } 421208097Smarius 422208097Smarius /* 423183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 424183423Smarius * Jalapeno bug). 425183423Smarius */ 426183423Smarius if (mode == SCHIZO_MODE_TOM) 427220038Smarius SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 428183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 429183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 430183423Smarius 431183423Smarius /* 432183423Smarius * Hunt through all the interrupt mapping regs and register 433186290Smarius * the interrupt controller for our interrupt vectors. We do 434186290Smarius * this early in order to be able to catch stray interrupts. 435186290Smarius * This is complicated by the fact that a pair of Schizo PBMs 436186290Smarius * shares one IGN. 437183423Smarius */ 438201199Smarius i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 439183423Smarius sizeof(prop_array)); 440205254Smarius if (i != -1) 441205254Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 442205254Smarius else { 443205254Smarius /* 444205254Smarius * If the ino-bitmap property is missing, just provide the 445205254Smarius * default set of interrupts for this controller and let 446205254Smarius * schizo_setup_intr() take care of child interrupts. 447205254Smarius */ 448205254Smarius if (sc->sc_half == 0) 449205254Smarius ino_bitmap = (1ULL << STX_UE_INO) | 450205254Smarius (1ULL << STX_CE_INO) | 451205254Smarius (1ULL << STX_PCIERR_A_INO) | 452205254Smarius (1ULL << STX_BUS_INO); 453205254Smarius else 454205254Smarius ino_bitmap = 1ULL << STX_PCIERR_B_INO; 455205254Smarius } 456201199Smarius for (i = 0; i <= STX_MAX_INO; i++) { 457201199Smarius if ((ino_bitmap & (1ULL << i)) == 0) 458183423Smarius continue; 459201199Smarius if (i == STX_FB0_INO || i == STX_FB1_INO) 460183423Smarius /* Leave for upa(4). */ 461183423Smarius continue; 462201199Smarius j = schizo_intr_register(sc, i); 463201199Smarius if (j != 0) 464186290Smarius device_printf(dev, "could not register interrupt " 465201199Smarius "controller for INO %d (%d)\n", i, j); 466183423Smarius } 467183423Smarius 468183423Smarius /* 469183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 470183423Smarius * mode as timecounter. Unfortunately, this is broken with at 471183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 472183423Smarius * 1500, which apparently actually count some different event at 473183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 474183423Smarius * power mode). Besides, one counter seems to be shared by a 475183423Smarius * "pair" of Tomatillos, too. 476183423Smarius */ 477183423Smarius if (sc->sc_half == 0) { 478220038Smarius SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 479183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 480183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 481183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 482183423Smarius if (tc == NULL) 483183423Smarius panic("%s: could not malloc timecounter", __func__); 484183423Smarius tc->tc_get_timecount = schizo_get_timecount; 485183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 486183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 487183423Smarius sizeof(prop)) == -1) 488183423Smarius panic("%s: could not determine clock frequency", 489183423Smarius __func__); 490183423Smarius tc->tc_frequency = prop; 491183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 492183423Smarius if (mode == SCHIZO_MODE_SCZ) 493183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 494183423Smarius else 495183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 496183423Smarius tc->tc_priv = sc; 497183423Smarius tc_init(tc); 498183423Smarius } 499183423Smarius 500190108Smarius /* 501190108Smarius * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 502190108Smarius * one per PBM. Schizo and XMITS additionally have a streaming 503190108Smarius * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 504190108Smarius * affected by several errata and basically unusable though. 505190108Smarius */ 506220038Smarius memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 507220038Smarius sizeof(sc->sc_dma_methods)); 508220038Smarius sc->sc_is.sis_sc = sc; 509220038Smarius sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 510220038Smarius sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 511220038Smarius sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 512190108Smarius if (OF_getproplen(node, "no-streaming-cache") < 0 && 513190108Smarius !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 514220038Smarius sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 515183423Smarius 516183423Smarius#define TSBCASE(x) \ 517183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 518183423Smarius tsbsize = (x); \ 519183423Smarius break; \ 520183423Smarius 521201199Smarius i = OF_getprop(node, "virtual-dma", (void *)prop_array, 522183423Smarius sizeof(prop_array)); 523201199Smarius if (i == -1 || i != sizeof(prop_array)) 524183423Smarius schizo_iommu_init(sc, 7, -1); 525183423Smarius else { 526183423Smarius switch (prop_array[1]) { 527183423Smarius TSBCASE(1); 528183423Smarius TSBCASE(2); 529183423Smarius TSBCASE(3); 530183423Smarius TSBCASE(4); 531183423Smarius TSBCASE(5); 532183423Smarius TSBCASE(6); 533183423Smarius TSBCASE(7); 534183423Smarius TSBCASE(8); 535183423Smarius default: 536183423Smarius panic("%s: unsupported DVMA size 0x%x", 537183423Smarius __func__, prop_array[1]); 538183423Smarius /* NOTREACHED */ 539183423Smarius } 540183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 541183423Smarius } 542185133Smarius 543183423Smarius#undef TSBCASE 544183423Smarius 545183423Smarius /* Initialize memory and I/O rmans. */ 546183423Smarius sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 547183423Smarius sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 548183423Smarius if (rman_init(&sc->sc_pci_io_rman) != 0 || 549183423Smarius rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 550183423Smarius panic("%s: failed to set up I/O rman", __func__); 551183423Smarius sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 552183423Smarius sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 553183423Smarius if (rman_init(&sc->sc_pci_mem_rman) != 0 || 554183423Smarius rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 555183423Smarius panic("%s: failed to set up memory rman", __func__); 556183423Smarius 557201199Smarius i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 558183423Smarius /* 559183423Smarius * Make sure that the expected ranges are present. The 560183423Smarius * OFW_PCI_CS_MEM64 one is not currently used though. 561183423Smarius */ 562201199Smarius if (i != STX_NRANGE) 563183423Smarius panic("%s: unsupported number of ranges", __func__); 564183423Smarius /* 565183423Smarius * Find the addresses of the various bus spaces. 566183423Smarius * There should not be multiple ones of one kind. 567183423Smarius * The physical start addresses of the ranges are the configuration, 568183423Smarius * memory and I/O handles. 569183423Smarius */ 570201199Smarius for (i = 0; i < STX_NRANGE; i++) { 571201199Smarius j = OFW_PCI_RANGE_CS(&range[i]); 572201199Smarius if (sc->sc_pci_bh[j] != 0) 573201199Smarius panic("%s: duplicate range for space %d", 574201199Smarius __func__, j); 575201199Smarius sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 576183423Smarius } 577183423Smarius free(range, M_OFWPROP); 578183423Smarius 579183423Smarius /* Register the softc, this is needed for paired Schizos. */ 580183423Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 581183423Smarius 582183423Smarius /* Allocate our tags. */ 583183423Smarius sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 584183423Smarius sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 585183423Smarius sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 586183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 587220038Smarius sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 588220038Smarius sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 589220038Smarius &sc->sc_pci_dmat) != 0) 590183423Smarius panic("%s: bus_dma_tag_create failed", __func__); 591183423Smarius /* Customize the tag. */ 592183423Smarius sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 593220038Smarius sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods; 594183423Smarius 595183423Smarius /* 596183423Smarius * Get the bus range from the firmware. 597183423Smarius * NB: Tomatillos don't support PCI bus reenumeration. 598183423Smarius */ 599201199Smarius i = OF_getprop(node, "bus-range", (void *)prop_array, 600183423Smarius sizeof(prop_array)); 601201199Smarius if (i == -1) 602183423Smarius panic("%s: could not get bus-range", __func__); 603201199Smarius if (i != sizeof(prop_array)) 604201199Smarius panic("%s: broken bus-range (%d)", __func__, i); 605201395Smarius sc->sc_pci_secbus = prop_array[0]; 606201395Smarius sc->sc_pci_subbus = prop_array[1]; 607183423Smarius if (bootverbose) 608183423Smarius device_printf(dev, "bus range %u to %u; PCI bus %d\n", 609201395Smarius sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 610183423Smarius 611183423Smarius /* Clear any pending PCI error bits. */ 612183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 613183423Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 614183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 615220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 616220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 617183423Smarius 618183423Smarius /* 619183423Smarius * Establish handlers for interesting interrupts... 620183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 621183423Smarius * bus error interrupts for one PBM can be routed to the other 622183423Smarius * PBM though we obviously need to use the softc of the former 623183423Smarius * as the argument for the interrupt handler and the softc of 624183423Smarius * the latter as the argument for the interrupt controller. 625183423Smarius */ 626183423Smarius if (sc->sc_half == 0) { 627183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 628183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 629183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 630183423Smarius sica_sc == osc)) 631183423Smarius /* 632183423Smarius * We are the driver for PBM A and either also 633183423Smarius * registered the interrupt controller for us or 634183423Smarius * the driver for PBM B has probed first and 635183423Smarius * registered it for us. 636183423Smarius */ 637183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 638183423Smarius schizo_pci_bus); 639183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 640183423Smarius osc != NULL) 641183423Smarius /* 642183423Smarius * We are the driver for PBM A but registered 643183423Smarius * the interrupt controller for PBM B, i.e. the 644183423Smarius * driver for PBM B attached first but couldn't 645183423Smarius * set up a handler for PBM B. 646183423Smarius */ 647183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 648183423Smarius schizo_pci_bus); 649183423Smarius } else { 650183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 651183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 652183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 653183423Smarius sica_sc == osc)) 654183423Smarius /* 655183423Smarius * We are the driver for PBM B and either also 656183423Smarius * registered the interrupt controller for us or 657183423Smarius * the driver for PBM A has probed first and 658183423Smarius * registered it for us. 659183423Smarius */ 660183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 661183423Smarius schizo_pci_bus); 662183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 663183423Smarius osc != NULL) 664183423Smarius /* 665183423Smarius * We are the driver for PBM B but registered 666183423Smarius * the interrupt controller for PBM A, i.e. the 667183423Smarius * driver for PBM A attached first but couldn't 668183423Smarius * set up a handler for PBM A. 669183423Smarius */ 670183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 671183423Smarius schizo_pci_bus); 672183423Smarius } 673183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 674183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 675183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 676183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 677183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 678183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 679183423Smarius 680183423Smarius /* 681185133Smarius * According to the Schizo Errata I-13, consistent DMA flushing/ 682185133Smarius * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 683201126Smarius * so we can't use it and need to live with the consequences. With 684201126Smarius * Schizo version >= 5, CDMA flushing/syncing is usable but requires 685201126Smarius * the workaround described in Schizo Errata I-23. With Tomatillo 686201126Smarius * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 687201126Smarius * version <= 4 (i.e. revision <= 2.3) bridges additionally require 688201126Smarius * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 689185133Smarius */ 690185133Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 691201199Smarius sc->sc_mode == SCHIZO_MODE_TOM || 692201199Smarius sc->sc_mode == SCHIZO_MODE_XMS) { 693185133Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) { 694220038Smarius sc->sc_dma_methods.dm_dmamap_sync = 695220038Smarius schizo_dmamap_sync; 696220038Smarius sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 697201126Smarius /* 698201126Smarius * Some firmware versions include the CDMA interrupt 699201126Smarius * at RID 4 but most don't. With the latter we add 700201126Smarius * it ourselves at the spare RID 5. 701201126Smarius */ 702201199Smarius i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 703201126Smarius 4)); 704201199Smarius if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 705201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 706201126Smarius &sc->sc_cdma_clr); 707201199Smarius schizo_set_intr(sc, 4, i, schizo_cdma); 708201126Smarius } else { 709201199Smarius i = STX_CDMA_A_INO + sc->sc_half; 710201126Smarius if (bus_set_resource(dev, SYS_RES_IRQ, 5, 711201199Smarius INTMAP_VEC(sc->sc_ign, i), 1) != 0) 712201126Smarius panic("%s: failed to add CDMA " 713201126Smarius "interrupt", __func__); 714201199Smarius j = schizo_intr_register(sc, i); 715201199Smarius if (j != 0) 716201126Smarius panic("%s: could not register " 717201126Smarius "interrupt controller for CDMA " 718201199Smarius "(%d)", __func__, j); 719201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 720201126Smarius &sc->sc_cdma_clr); 721201199Smarius schizo_set_intr(sc, 5, i, schizo_cdma); 722201126Smarius } 723220038Smarius } else { 724220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 725220038Smarius mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 726220038Smarius NULL, MTX_SPIN); 727220038Smarius sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 728220038Smarius sc->sc_half); 729220038Smarius sc->sc_dma_methods.dm_dmamap_sync = 730220038Smarius ichip_dmamap_sync; 731185133Smarius } 732185133Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 733185133Smarius sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 734185133Smarius } 735185133Smarius 736185133Smarius /* 737183423Smarius * Set the latency timer register as this isn't always done by the 738183423Smarius * firmware. 739183423Smarius */ 740183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 741183423Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 742183423Smarius 743183423Smarius ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 744183423Smarius 745208097Smarius#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 746208097Smarius SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 747208097Smarius SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 748208097Smarius (name), CTLFLAG_RD, (arg), 0, (desc)) 749208097Smarius 750208097Smarius SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 751208097Smarius "DMA correctable errors"); 752208097Smarius SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 753208097Smarius "PCI bus non-fatal errors"); 754208097Smarius 755208097Smarius#undef SCHIZO_SYSCTL_ADD_UINT 756208097Smarius 757183423Smarius device_add_child(dev, "pci", -1); 758183423Smarius return (bus_generic_attach(dev)); 759183423Smarius} 760183423Smarius 761183423Smariusstatic void 762183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 763183423Smarius driver_filter_t handler) 764183423Smarius{ 765183423Smarius u_long vec; 766183423Smarius int rid; 767183423Smarius 768183423Smarius rid = index; 769201199Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 770201199Smarius SYS_RES_IRQ, &rid, RF_ACTIVE); 771183423Smarius if (sc->sc_irq_res[index] == NULL || 772201199Smarius INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 773201199Smarius INTIGN(vec) != sc->sc_ign || 774183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 775185133Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 776216961Smarius INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 777185133Smarius &sc->sc_ihand[index]) != 0) 778183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 779183423Smarius} 780183423Smarius 781183423Smariusstatic int 782185133Smariusschizo_intr_register(struct schizo_softc *sc, u_int ino) 783185133Smarius{ 784185133Smarius struct schizo_icarg *sica; 785185133Smarius bus_addr_t intrclr, intrmap; 786185133Smarius int error; 787185133Smarius 788185133Smarius if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 789185133Smarius return (ENXIO); 790185133Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 791185133Smarius if (sica == NULL) 792185133Smarius return (ENOMEM); 793185133Smarius sica->sica_sc = sc; 794185133Smarius sica->sica_map = intrmap; 795185133Smarius sica->sica_clr = intrclr; 796185133Smarius#ifdef SCHIZO_DEBUG 797185133Smarius device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 798185133Smarius ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 799185133Smarius (u_long)intrclr); 800185133Smarius#endif 801185133Smarius error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 802185133Smarius &schizo_ic, sica)); 803185133Smarius if (error != 0) 804185133Smarius free(sica, M_DEVBUF); 805185133Smarius return (error); 806185133Smarius} 807185133Smarius 808185133Smariusstatic int 809201199Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, 810201199Smarius bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 811183423Smarius{ 812183423Smarius bus_addr_t intrclr, intrmap; 813183423Smarius uint64_t mr; 814183423Smarius 815183423Smarius /* 816183423Smarius * XXX we only look for INOs rather than INRs since the firmware 817183423Smarius * may not provide the IGN and the IGN is constant for all devices 818183423Smarius * on that PCI controller. 819183423Smarius */ 820183423Smarius 821183423Smarius if (ino > STX_MAX_INO) { 822183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 823183423Smarius ino); 824183423Smarius return (0); 825183423Smarius } 826183423Smarius 827183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 828183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 829183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 830183423Smarius if (INTINO(mr) != ino) { 831183423Smarius device_printf(sc->sc_dev, 832183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 833183423Smarius (int)INTINO(mr), ino); 834183423Smarius return (0); 835183423Smarius } 836183423Smarius 837183423Smarius if (intrmapptr != NULL) 838183423Smarius *intrmapptr = intrmap; 839183423Smarius if (intrclrptr != NULL) 840183423Smarius *intrclrptr = intrclr; 841183423Smarius return (1); 842183423Smarius} 843183423Smarius 844183423Smarius/* 845183423Smarius * Interrupt handlers 846183423Smarius */ 847183423Smariusstatic int 848183423Smariusschizo_pci_bus(void *arg) 849183423Smarius{ 850183423Smarius struct schizo_softc *sc = arg; 851220038Smarius uint64_t afar, afsr, csr, iommu, xstat; 852183423Smarius uint32_t status; 853208097Smarius u_int fatal; 854183423Smarius 855208097Smarius fatal = 0; 856208097Smarius 857208097Smarius mtx_lock_spin(sc->sc_mtx); 858208097Smarius 859183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 860183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 861183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 862183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 863220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 864220038Smarius xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 865220038Smarius else 866220038Smarius xstat = 0; 867183423Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 868183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 869183423Smarius 870208097Smarius /* 871208097Smarius * IOMMU errors are only fatal on Tomatillo and there also only if 872208097Smarius * target abort was not signaled. 873208097Smarius */ 874208097Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 875208097Smarius (iommu & TOM_PCI_IOMMU_ERR) != 0 && 876208097Smarius ((status & PCIM_STATUS_STABORT) == 0 || 877208097Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 878208097Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 879208097Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 880208097Smarius fatal = 1; 881208097Smarius else if ((status & PCIM_STATUS_STABORT) != 0) 882208097Smarius fatal = 1; 883208097Smarius if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 884208097Smarius PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 885212378Sjhb PCIM_STATUS_MDPERR)) != 0 || 886208097Smarius (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 887208097Smarius STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 888208097Smarius SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 889208097Smarius (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 890208097Smarius STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 891208097Smarius STX_PCI_AFSR_P_UNUS)) != 0) 892208097Smarius fatal = 1; 893220038Smarius if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 894220038Smarius XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 895220038Smarius XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 896220038Smarius XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 897220038Smarius fatal = 1; 898208097Smarius if (fatal == 0) 899208097Smarius sc->sc_stats_pci_non_fatal++; 900183423Smarius 901208097Smarius device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 902220038Smarius "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 903220038Smarius 'A' + sc->sc_half, (unsigned long long)afar, 904220038Smarius (unsigned long long)afsr, (unsigned long long)csr, 905220038Smarius (unsigned long long)iommu, (unsigned long long)xstat, status); 906183423Smarius 907183423Smarius /* Clear the error bits that we caught. */ 908183423Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 909183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 910183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 911183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 912208097Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 913220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 914220038Smarius SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 915208097Smarius 916208097Smarius mtx_unlock_spin(sc->sc_mtx); 917208097Smarius 918208097Smarius if (fatal != 0) 919208097Smarius panic("%s: fatal PCI bus error", 920208097Smarius device_get_nameunit(sc->sc_dev)); 921183423Smarius return (FILTER_HANDLED); 922183423Smarius} 923183423Smarius 924183423Smariusstatic int 925183423Smariusschizo_ue(void *arg) 926183423Smarius{ 927183423Smarius struct schizo_softc *sc = arg; 928183423Smarius uint64_t afar, afsr; 929183423Smarius int i; 930183423Smarius 931183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 932183423Smarius for (i = 0; i < 1000; i++) 933183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 934183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 935183423Smarius break; 936183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 937206020Smarius device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 938183423Smarius (unsigned long long)afsr); 939183423Smarius return (FILTER_HANDLED); 940183423Smarius} 941183423Smarius 942183423Smariusstatic int 943183423Smariusschizo_ce(void *arg) 944183423Smarius{ 945183423Smarius struct schizo_softc *sc = arg; 946183423Smarius uint64_t afar, afsr; 947183423Smarius int i; 948183423Smarius 949183423Smarius mtx_lock_spin(sc->sc_mtx); 950208097Smarius 951183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 952183423Smarius for (i = 0; i < 1000; i++) 953183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 954183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 955183423Smarius break; 956208097Smarius sc->sc_stats_dma_ce++; 957183423Smarius device_printf(sc->sc_dev, 958183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 959183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 960208097Smarius 961183423Smarius /* Clear the error bits that we caught. */ 962183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 963208097Smarius 964183423Smarius mtx_unlock_spin(sc->sc_mtx); 965208097Smarius 966183423Smarius return (FILTER_HANDLED); 967183423Smarius} 968183423Smarius 969183423Smariusstatic int 970183423Smariusschizo_host_bus(void *arg) 971183423Smarius{ 972183423Smarius struct schizo_softc *sc = arg; 973183423Smarius uint64_t errlog; 974183423Smarius 975183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 976206020Smarius panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 977183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 978183423Smarius (unsigned long long)errlog); 979183423Smarius return (FILTER_HANDLED); 980183423Smarius} 981183423Smarius 982185133Smariusstatic int 983185133Smariusschizo_cdma(void *arg) 984185133Smarius{ 985185133Smarius struct schizo_softc *sc = arg; 986185133Smarius 987220038Smarius atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_RECEIVED); 988185133Smarius return (FILTER_HANDLED); 989185133Smarius} 990185133Smarius 991183423Smariusstatic void 992183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 993183423Smarius{ 994183423Smarius 995183423Smarius /* Punch in our copies. */ 996220038Smarius sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 997220038Smarius sc->sc_is.sis_is.is_bushandle = 998220038Smarius rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 999220038Smarius sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 1000220038Smarius sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 1001220038Smarius sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 1002220038Smarius sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 1003220038Smarius sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 1004220038Smarius sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 1005183423Smarius 1006220038Smarius iommu_init(device_get_nameunit(sc->sc_dev), 1007220038Smarius (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 1008183423Smarius} 1009183423Smarius 1010183423Smariusstatic int 1011183423Smariusschizo_maxslots(device_t dev) 1012183423Smarius{ 1013183423Smarius struct schizo_softc *sc; 1014183423Smarius 1015183423Smarius sc = device_get_softc(dev); 1016183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 1017183423Smarius return (sc->sc_half == 0 ? 4 : 6); 1018183423Smarius 1019183423Smarius /* XXX: is this correct? */ 1020183423Smarius return (PCI_SLOTMAX); 1021183423Smarius} 1022183423Smarius 1023183423Smariusstatic uint32_t 1024183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 1025183423Smarius int width) 1026183423Smarius{ 1027183423Smarius struct schizo_softc *sc; 1028183423Smarius bus_space_handle_t bh; 1029183423Smarius u_long offset = 0; 1030183423Smarius uint32_t r, wrd; 1031183423Smarius int i; 1032183423Smarius uint16_t shrt; 1033183423Smarius uint8_t byte; 1034183423Smarius 1035183423Smarius sc = device_get_softc(dev); 1036201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1037201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1038201395Smarius return (-1); 1039183423Smarius 1040183423Smarius /* 1041183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 1042183423Smarius */ 1043183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1044183423Smarius slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1045183423Smarius reg + width > 0x80) 1046183423Smarius return (0); 1047183423Smarius 1048183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1049183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1050183423Smarius switch (width) { 1051183423Smarius case 1: 1052183423Smarius i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1053183423Smarius r = byte; 1054183423Smarius break; 1055183423Smarius case 2: 1056183423Smarius i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1057183423Smarius r = shrt; 1058183423Smarius break; 1059183423Smarius case 4: 1060183423Smarius i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1061183423Smarius r = wrd; 1062183423Smarius break; 1063183423Smarius default: 1064183423Smarius panic("%s: bad width", __func__); 1065183423Smarius /* NOTREACHED */ 1066183423Smarius } 1067183423Smarius 1068183423Smarius if (i) { 1069183423Smarius#ifdef SCHIZO_DEBUG 1070183423Smarius printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1071183423Smarius __func__, bus, slot, func, reg); 1072183423Smarius#endif 1073183423Smarius r = -1; 1074183423Smarius } 1075183423Smarius return (r); 1076183423Smarius} 1077183423Smarius 1078183423Smariusstatic void 1079201199Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1080201199Smarius u_int reg, uint32_t val, int width) 1081183423Smarius{ 1082183423Smarius struct schizo_softc *sc; 1083183423Smarius bus_space_handle_t bh; 1084183423Smarius u_long offset = 0; 1085183423Smarius 1086183423Smarius sc = device_get_softc(dev); 1087201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1088201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1089201395Smarius return; 1090201395Smarius 1091183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1092183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1093183423Smarius switch (width) { 1094183423Smarius case 1: 1095183423Smarius bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1096183423Smarius break; 1097183423Smarius case 2: 1098183423Smarius bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1099183423Smarius break; 1100183423Smarius case 4: 1101183423Smarius bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1102183423Smarius break; 1103183423Smarius default: 1104183423Smarius panic("%s: bad width", __func__); 1105183423Smarius /* NOTREACHED */ 1106183423Smarius } 1107183423Smarius} 1108183423Smarius 1109183423Smariusstatic int 1110183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 1111183423Smarius{ 1112183423Smarius struct schizo_softc *sc; 1113183423Smarius struct ofw_pci_register reg; 1114183423Smarius ofw_pci_intr_t pintr, mintr; 1115183423Smarius uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1116183423Smarius 1117183423Smarius sc = device_get_softc(bridge); 1118183423Smarius pintr = pin; 1119201199Smarius if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1120201199Smarius ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1121209298Snwhitehorn NULL, maskbuf)) 1122183423Smarius return (mintr); 1123183423Smarius 1124183423Smarius device_printf(bridge, "could not route pin %d for device %d.%d\n", 1125183423Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 1126183423Smarius return (PCI_INVALID_IRQ); 1127183423Smarius} 1128183423Smarius 1129183423Smariusstatic int 1130183423Smariusschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1131183423Smarius{ 1132183423Smarius struct schizo_softc *sc; 1133183423Smarius 1134183423Smarius sc = device_get_softc(dev); 1135183423Smarius switch (which) { 1136183423Smarius case PCIB_IVAR_DOMAIN: 1137183423Smarius *result = device_get_unit(dev); 1138183423Smarius return (0); 1139183423Smarius case PCIB_IVAR_BUS: 1140183423Smarius *result = sc->sc_pci_secbus; 1141183423Smarius return (0); 1142183423Smarius } 1143183423Smarius return (ENOENT); 1144183423Smarius} 1145183423Smarius 1146220038Smariusstatic void 1147220038Smariusschizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1148185133Smarius{ 1149185133Smarius struct timeval cur, end; 1150220038Smarius struct schizo_iommu_state *sis = dt->dt_cookie; 1151220038Smarius struct schizo_softc *sc = sis->sis_sc; 1152220038Smarius int res; 1153185133Smarius 1154220038Smarius if ((map->dm_flags & DMF_STREAMED) != 0) { 1155220038Smarius iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1156220038Smarius return; 1157220038Smarius } 1158220038Smarius 1159220038Smarius if ((map->dm_flags & DMF_LOADED) == 0) 1160220038Smarius return; 1161220038Smarius 1162220038Smarius if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1163220038Smarius /* 1164220038Smarius * Note that in order to allow this function to be called from 1165220038Smarius * filters we would need to use a spin mutex for serialization 1166220038Smarius * but given that these disable interrupts we have to emulate 1167220038Smarius * one. 1168220038Smarius */ 1169220038Smarius for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1170220038Smarius SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1171220038Smarius ; 1172220038Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1173185133Smarius microuptime(&cur); 1174220038Smarius end.tv_sec = 1; 1175220038Smarius end.tv_usec = 0; 1176220038Smarius timevaladd(&end, &cur); 1177220038Smarius for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1178220038Smarius SCHIZO_CDMA_STATE_RECEIVED, SCHIZO_CDMA_STATE_IDLE)) == 1179220038Smarius 0 && timevalcmp(&cur, &end, <=);) 1180220038Smarius microuptime(&cur); 1181220038Smarius if (res == 0) 1182220038Smarius panic("%s: DMA does not sync", __func__); 1183220038Smarius } 1184220038Smarius 1185220038Smarius if ((op & BUS_DMASYNC_PREWRITE) != 0) 1186220038Smarius membar(Sync); 1187185133Smarius} 1188185133Smarius 1189183423Smarius#define VIS_BLOCKSIZE 64 1190183423Smarius 1191220038Smariusstatic void 1192220038Smariusichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1193183423Smarius{ 1194183423Smarius static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1195185133Smarius struct timeval cur, end; 1196220038Smarius struct schizo_iommu_state *sis = dt->dt_cookie; 1197220038Smarius struct schizo_softc *sc = sis->sis_sc; 1198184428Smarius register_t reg, s; 1199183423Smarius 1200220038Smarius if ((map->dm_flags & DMF_STREAMED) != 0) { 1201220038Smarius iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1202220038Smarius return; 1203220038Smarius } 1204220038Smarius 1205220038Smarius if ((map->dm_flags & DMF_LOADED) == 0) 1206220038Smarius return; 1207220038Smarius 1208220038Smarius if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1209220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 1210220038Smarius mtx_lock_spin(&sc->sc_sync_mtx); 1211220038Smarius SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1212220038Smarius sc->sc_sync_val); 1213185133Smarius microuptime(&cur); 1214220038Smarius end.tv_sec = 1; 1215220038Smarius end.tv_usec = 0; 1216220038Smarius timevaladd(&end, &cur); 1217220038Smarius for (; ((reg = SCHIZO_PCI_READ_8(sc, 1218220038Smarius TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1219220038Smarius timevalcmp(&cur, &end, <=);) 1220220038Smarius microuptime(&cur); 1221220038Smarius if ((reg & sc->sc_sync_val) != 0) 1222220038Smarius panic("%s: DMA does not sync", __func__); 1223220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 1224220038Smarius mtx_unlock_spin(&sc->sc_sync_mtx); 1225220038Smarius else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1226220038Smarius s = intr_disable(); 1227220038Smarius reg = rd(fprs); 1228220038Smarius wr(fprs, reg | FPRS_FEF, 0); 1229220038Smarius __asm __volatile("stda %%f0, [%0] %1" 1230220038Smarius : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1231220038Smarius membar(Sync); 1232220038Smarius wr(fprs, reg, 0); 1233220038Smarius intr_restore(s); 1234220038Smarius return; 1235220038Smarius } 1236220038Smarius } 1237183423Smarius 1238220038Smarius if ((op & BUS_DMASYNC_PREWRITE) != 0) 1239184428Smarius membar(Sync); 1240183423Smarius} 1241183423Smarius 1242183423Smariusstatic void 1243183423Smariusschizo_intr_enable(void *arg) 1244183423Smarius{ 1245183423Smarius struct intr_vector *iv = arg; 1246183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1247183423Smarius 1248183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1249183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1250183423Smarius} 1251183423Smarius 1252183423Smariusstatic void 1253183423Smariusschizo_intr_disable(void *arg) 1254183423Smarius{ 1255183423Smarius struct intr_vector *iv = arg; 1256183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1257183423Smarius 1258183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1259183423Smarius} 1260183423Smarius 1261183423Smariusstatic void 1262183423Smariusschizo_intr_assign(void *arg) 1263183423Smarius{ 1264183423Smarius struct intr_vector *iv = arg; 1265183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1266183423Smarius 1267183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1268183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1269183423Smarius} 1270183423Smarius 1271183423Smariusstatic void 1272183423Smariusschizo_intr_clear(void *arg) 1273183423Smarius{ 1274183423Smarius struct intr_vector *iv = arg; 1275183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1276183423Smarius 1277206018Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1278183423Smarius} 1279183423Smarius 1280183423Smariusstatic int 1281183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1282183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1283183423Smarius void **cookiep) 1284183423Smarius{ 1285183423Smarius struct schizo_softc *sc; 1286183423Smarius u_long vec; 1287220038Smarius int error; 1288183423Smarius 1289183423Smarius sc = device_get_softc(dev); 1290183423Smarius /* 1291186290Smarius * Make sure the vector is fully specified. 1292183423Smarius */ 1293183423Smarius vec = rman_get_start(ires); 1294186290Smarius if (INTIGN(vec) != sc->sc_ign) { 1295183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1296183423Smarius return (EINVAL); 1297183423Smarius } 1298183423Smarius 1299186290Smarius if (intr_vectors[vec].iv_ic == &schizo_ic) { 1300186290Smarius /* 1301186290Smarius * Ensure we use the right softc in case the interrupt 1302186290Smarius * is routed to our companion PBM for some odd reason. 1303186290Smarius */ 1304186290Smarius sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1305186290Smarius sica_sc; 1306186290Smarius } else if (intr_vectors[vec].iv_ic == NULL) { 1307186290Smarius /* 1308186290Smarius * Work around broken firmware which misses entries in 1309186290Smarius * the ino-bitmap. 1310186290Smarius */ 1311186290Smarius error = schizo_intr_register(sc, INTINO(vec)); 1312186290Smarius if (error != 0) { 1313186290Smarius device_printf(dev, "could not register interrupt " 1314186290Smarius "controller for vector 0x%lx (%d)\n", vec, error); 1315186290Smarius return (error); 1316186290Smarius } 1317190108Smarius if (bootverbose) 1318190108Smarius device_printf(dev, "belatedly registered as " 1319190108Smarius "interrupt controller for vector 0x%lx\n", vec); 1320186290Smarius } else { 1321186290Smarius device_printf(dev, 1322186290Smarius "invalid interrupt controller for vector 0x%lx\n", vec); 1323186290Smarius return (EINVAL); 1324186290Smarius } 1325183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1326183423Smarius arg, cookiep)); 1327183423Smarius} 1328183423Smarius 1329183423Smariusstatic struct resource * 1330183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1331183423Smarius u_long start, u_long end, u_long count, u_int flags) 1332183423Smarius{ 1333183423Smarius struct schizo_softc *sc; 1334183423Smarius struct resource *rv; 1335183423Smarius struct rman *rm; 1336183423Smarius bus_space_tag_t bt; 1337183423Smarius bus_space_handle_t bh; 1338183423Smarius int needactivate = flags & RF_ACTIVE; 1339183423Smarius 1340183423Smarius flags &= ~RF_ACTIVE; 1341183423Smarius 1342183423Smarius sc = device_get_softc(bus); 1343183423Smarius if (type == SYS_RES_IRQ) { 1344183423Smarius /* 1345183423Smarius * XXX: Don't accept blank ranges for now, only single 1346183423Smarius * interrupts. The other case should not happen with 1347183423Smarius * the MI PCI code... 1348183423Smarius * XXX: This may return a resource that is out of the 1349183423Smarius * range that was specified. Is this correct...? 1350183423Smarius */ 1351183423Smarius if (start != end) 1352183423Smarius panic("%s: XXX: interrupt range", __func__); 1353183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1354201199Smarius return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 1355201199Smarius type, rid, start, end, count, flags)); 1356183423Smarius } 1357183423Smarius switch (type) { 1358183423Smarius case SYS_RES_MEMORY: 1359183423Smarius rm = &sc->sc_pci_mem_rman; 1360183423Smarius bt = sc->sc_pci_memt; 1361183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1362183423Smarius break; 1363183423Smarius case SYS_RES_IOPORT: 1364183423Smarius rm = &sc->sc_pci_io_rman; 1365183423Smarius bt = sc->sc_pci_iot; 1366183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1367183423Smarius break; 1368183423Smarius default: 1369183423Smarius return (NULL); 1370183423Smarius /* NOTREACHED */ 1371183423Smarius } 1372183423Smarius 1373183423Smarius rv = rman_reserve_resource(rm, start, end, count, flags, child); 1374183423Smarius if (rv == NULL) 1375183423Smarius return (NULL); 1376183423Smarius rman_set_rid(rv, *rid); 1377183423Smarius bh += rman_get_start(rv); 1378183423Smarius rman_set_bustag(rv, bt); 1379183423Smarius rman_set_bushandle(rv, bh); 1380183423Smarius 1381183423Smarius if (needactivate) { 1382183423Smarius if (bus_activate_resource(child, type, *rid, rv)) { 1383183423Smarius rman_release_resource(rv); 1384183423Smarius return (NULL); 1385183423Smarius } 1386183423Smarius } 1387183423Smarius return (rv); 1388183423Smarius} 1389183423Smarius 1390183423Smariusstatic int 1391183423Smariusschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1392183423Smarius struct resource *r) 1393183423Smarius{ 1394183423Smarius void *p; 1395183423Smarius int error; 1396183423Smarius 1397183423Smarius if (type == SYS_RES_IRQ) 1398183423Smarius return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1399183423Smarius type, rid, r)); 1400183423Smarius if (type == SYS_RES_MEMORY) { 1401183423Smarius /* 1402185133Smarius * Need to memory-map the device space, as some drivers 1403185133Smarius * depend on the virtual address being set and usable. 1404183423Smarius */ 1405183423Smarius error = sparc64_bus_mem_map(rman_get_bustag(r), 1406183423Smarius rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1407183423Smarius if (error != 0) 1408183423Smarius return (error); 1409183423Smarius rman_set_virtual(r, p); 1410183423Smarius } 1411183423Smarius return (rman_activate_resource(r)); 1412183423Smarius} 1413183423Smarius 1414183423Smariusstatic int 1415183423Smariusschizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1416183423Smarius struct resource *r) 1417183423Smarius{ 1418183423Smarius 1419183423Smarius if (type == SYS_RES_IRQ) 1420183423Smarius return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1421183423Smarius type, rid, r)); 1422183423Smarius if (type == SYS_RES_MEMORY) { 1423183423Smarius sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1424183423Smarius rman_set_virtual(r, NULL); 1425183423Smarius } 1426183423Smarius return (rman_deactivate_resource(r)); 1427183423Smarius} 1428183423Smarius 1429183423Smariusstatic int 1430183423Smariusschizo_release_resource(device_t bus, device_t child, int type, int rid, 1431183423Smarius struct resource *r) 1432183423Smarius{ 1433183423Smarius int error; 1434183423Smarius 1435183423Smarius if (type == SYS_RES_IRQ) 1436183423Smarius return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1437183423Smarius type, rid, r)); 1438183423Smarius if (rman_get_flags(r) & RF_ACTIVE) { 1439183423Smarius error = bus_deactivate_resource(child, type, rid, r); 1440183423Smarius if (error) 1441183423Smarius return (error); 1442183423Smarius } 1443183423Smarius return (rman_release_resource(r)); 1444183423Smarius} 1445183423Smarius 1446183423Smariusstatic bus_dma_tag_t 1447220038Smariusschizo_get_dma_tag(device_t bus, device_t child __unused) 1448183423Smarius{ 1449183423Smarius struct schizo_softc *sc; 1450183423Smarius 1451183423Smarius sc = device_get_softc(bus); 1452183423Smarius return (sc->sc_pci_dmat); 1453183423Smarius} 1454183423Smarius 1455183423Smariusstatic phandle_t 1456220038Smariusschizo_get_node(device_t bus, device_t child __unused) 1457183423Smarius{ 1458183423Smarius struct schizo_softc *sc; 1459183423Smarius 1460183423Smarius sc = device_get_softc(bus); 1461183423Smarius /* We only have one child, the PCI bus, which needs our own node. */ 1462183423Smarius return (sc->sc_node); 1463183423Smarius} 1464183423Smarius 1465220038Smariusstatic void 1466220038Smariusschizo_setup_device(device_t bus, device_t child) 1467220038Smarius{ 1468220038Smarius struct schizo_softc *sc; 1469220038Smarius uint64_t reg; 1470220038Smarius int capreg; 1471220038Smarius 1472220038Smarius sc = device_get_softc(bus); 1473220038Smarius /* 1474220038Smarius * Disable bus parking in order to work around a bus hang caused by 1475220038Smarius * Casinni/Skyhawk combinations. 1476220038Smarius */ 1477220038Smarius if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1478220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1479220038Smarius STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1480220038Smarius 1481220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) { 1482220038Smarius /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1483220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1484220038Smarius (pci_read_config(child, PCIR_HDRTYPE, 1) & 1485220038Smarius PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1486220038Smarius pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1487220038Smarius pci_write_config(child, capreg + PCIXR_COMMAND, 1488220038Smarius pci_read_config(child, capreg + PCIXR_COMMAND, 1489220038Smarius 2) & 0x7c, 2); 1490220038Smarius /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1491220038Smarius if (sc->sc_mrev >= 4) { 1492220038Smarius reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1493220038Smarius 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1494220038Smarius if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1495220038Smarius XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1496220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1497220038Smarius } 1498220038Smarius } 1499220038Smarius} 1500220038Smarius 1501183423Smariusstatic bus_space_tag_t 1502183423Smariusschizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1503183423Smarius{ 1504183423Smarius bus_space_tag_t bt; 1505183423Smarius 1506201199Smarius bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1507183423Smarius M_NOWAIT | M_ZERO); 1508183423Smarius if (bt == NULL) 1509183423Smarius panic("%s: out of memory", __func__); 1510183423Smarius 1511183423Smarius bt->bst_cookie = sc; 1512183423Smarius bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1513183423Smarius bt->bst_type = type; 1514183423Smarius return (bt); 1515183423Smarius} 1516183423Smarius 1517183423Smariusstatic u_int 1518183423Smariusschizo_get_timecount(struct timecounter *tc) 1519183423Smarius{ 1520183423Smarius struct schizo_softc *sc; 1521183423Smarius 1522183423Smarius sc = tc->tc_priv; 1523223959Smarius return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1524223959Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >> 1525223959Smarius STX_CTRL_PERF_CNT_CNT0_SHIFT); 1526183423Smarius} 1527